Clocking-and-synchronisation.md

+# PLL and Timestamps 
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+The ATLASPix operates thanks to a PLL in the periphery that receive a reference clock and multiplies this clock to generate internally the clocks needed for the operation of the periphery blocks. The input clock speed can go up to 160 MHz. 
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+There is a possibility to bypass the PLL and provide an external clock directly at the output of the PLL, using register settings `EnPLL = 0` and `SelEx = 1`. See register description for more details
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+The timestamps for hits in the matrix are `TS1` and `TS2`. TS1 represent the leading edge of the discriminator pulse in a pixel, `TS2` is the falling edge.
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+In normal operation mode (register settings `EnPLL = 1` and `SelEx = 0`.), we obtain : 
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+* For an input clock of `X Mhz`, the data output rate with be `10*X Mbps`. 
+* For an input clock of `X Mhz`, the precision of the first timestamp (TS1) is `(1+ckdivend1)*2000/X ns`  (ex: `80MHz, ckdivend1=0 -> 25 ns`), where `ckdivend1` is the clock divider register for TS1
+* For an input clock of `X Mhz`, the precision of the first timestamp (TS2) is `(1+ckdivend2)*1000/X ns`  (ex: `80MHz, ckdivend2=0 -> 12.5 ns`), where `ckdivend2` is the clock divider register for TS2
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+# Synchronisation
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+It is possible to synchronize the Zynq ZC706 and ATLASPix clock to an external clock (40 MHz) using the RJ45 connector on the CaR board (J22). The clock must be provided in LVDS signal on the first pair of the RJ45 cable. 
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+Further synchronisation is possible by providing a `t0` signal on the second pair of the RJ45 cable. When `t0` is asserted, FPGA Timestamp counter for trigger, and ATLASPix internal counters are set to 0. 
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