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boreal
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Updated date
Extending support for ZCU102 board
!7
· created
Apr 03, 2024
by
Younes Otarid
Feature
Format
Simulation
Merged
0
updated
Apr 04, 2024
Encapsulating AXI4Lite bus signals into a VHDL record type
!6
· created
Mar 20, 2024
by
Younes Otarid
Format
Merged
0
updated
Mar 20, 2024
Separating the design hierarchy for multiple board support
!3
· created
Mar 10, 2024
by
Younes Otarid
Feature
Format
Merged
0
updated
Mar 10, 2024
including all caribou i/o in the design + reworking constraints setting
!1
· created
Feb 19, 2024
by
Younes Otarid
Feature
Format
Merged
0
updated
Mar 06, 2024
Code tree restructuring
!2
· created
Mar 06, 2024
by
Younes Otarid
Format
Merged
0
updated
Mar 06, 2024