Testing of LVDS pairs.

The CaR board features 17 LVDS pairs. The breakout board creates a loop for these pairs, with the exception of 17. In order to test their functionality the following will be developed:

1. Two modules capable of receiving and transmitting data with LVDS using FPGA primitives (Buffers, SERDES, DDR) in order to achieve the highest throughput both for ZYNQ-7000 and Ultrascale+ families, wi. These will be able to provide the input/output data according to the AXI4-Stream protocol.
2. A BD with a variable clocking frequency source on run time (MMCM or PLL with AXI Lite) and a DMA to transfer data from/to the memory and validate the correct transmission.