diff --git a/sources/interlaken/interface/interlaken_interface.vhd b/sources/interlaken/interface/interlaken_interface.vhd index 59cf86a9093a4918f7333083d8ea075a8c10517b..1faf14a76439d58d1fbe3e2cf19e2784631f1b4d 100644 --- a/sources/interlaken/interface/interlaken_interface.vhd +++ b/sources/interlaken/interface/interlaken_interface.vhd @@ -44,12 +44,12 @@ entity interlaken_interface is s_axis : in axis_64_array_type(0 to lanes-1); --s_axis_prog_empty : out axis_tready_array_type(0 to Lanes-1); - s_axis_aclk : in std_logic_vector(Lanes/4-1 downto 0); + s_axis_aclk : in std_logic_vector(Lanes-1 downto 0); s_axis_tready : out axis_tready_array_type(0 to Lanes-1); ----Receiver output signals----------------------- FlowControl : out slv_16_array(0 to Lanes-1); -- Flow control data (yet unutilized) - m_axis_aclk : in std_logic_vector(Lanes/4-1 downto 0); + m_axis_aclk : in std_logic_vector(Lanes-1 downto 0); m_axis : out axis_64_array_type(0 to Lanes-1); m_axis_tready : in axis_tready_array_type(0 to Lanes-1); m_axis_prog_empty : out axis_tready_array_type(0 to Lanes-1); @@ -58,11 +58,11 @@ entity interlaken_interface is m_axis_deburst : out axis_64_array_type(0 to lanes-1); m_axis_burst : out axis_64_array_type(0 to lanes-1); - s_axis_aresetn : out std_logic_vector(lanes/4-1 downto 0); - m_axis_aresetn : out std_logic_vector(lanes/4-1 downto 0); + s_axis_aresetn : out std_logic_vector(lanes-1 downto 0); + m_axis_aresetn : out std_logic_vector(lanes-1 downto 0); - tx_user_clk_out : out std_logic_vector(lanes/4-1 downto 0); - rx_user_clk_out : out std_logic_vector(lanes/4-1 downto 0); + tx_user_clk_out : out std_logic_vector(lanes-1 downto 0); + rx_user_clk_out : out std_logic_vector(lanes-1 downto 0); ------------------Receiver status signals----------------------- Decoder_Lock : out std_logic_vector(lanes-1 downto 0); @@ -85,7 +85,7 @@ end entity interlaken_interface; architecture interface of interlaken_interface is - signal TX_User_Clock, RX_User_Clock : std_logic_vector(lanes/4-1 downto 0); + signal TX_User_Clock, RX_User_Clock : std_logic_vector(lanes-1 downto 0); signal RX_Datavalid_Out : std_logic_vector(lanes-1 downto 0); signal RX_Header_Out : slv_3_array(0 to lanes-1); @@ -103,7 +103,7 @@ architecture interface of interlaken_interface is signal TX_Data_out_s : slv_67_array(0 to lanes-1); signal RX_Data_In_s : slv_67_array(0 to lanes-1); - signal rst_txusr_403M, rst_rxusr_403M : std_logic_vector(Lanes/4-1 downto 0); + signal rst_txusr_403M, rst_rxusr_403M : std_logic_vector(Lanes-1 downto 0); signal interlaken_rst : std_logic; begin @@ -169,15 +169,15 @@ begin Lanes => BondNumberOfLanes ) port map ( - clk => TX_User_Clock(i/4), - reset => rst_txusr_403M(i/4), -- reset, + clk => TX_User_Clock(i), + reset => rst_txusr_403M(i), -- reset, TX_Data_Out => TX_Data_out_s(i*BondNumberOfLanes to (i+1)*BondNumberOfLanes-1), --Data_Transceiver_In(i)(63 downto 0), -- 64 bits TX_Gearboxready => TX_Gearboxready_Out((i+1)*BondNumberOfLanes-1 downto i*BondNumberOfLanes), FlowControl => TX_FlowControl(i*BondNumberOfLanes to (i+1)*BondNumberOfLanes-1), HealthLane => Descrambler_Lock_tx((i+1)*BondNumberOfLanes-1 downto i*BondNumberOfLanes), m_axis_burst => m_axis_burst(i*BondNumberOfLanes to (i+1)*BondNumberOfLanes-1), - s_axis_aclk => s_axis_aclk(i/4), + s_axis_aclk => s_axis_aclk(i), s_axis => s_axis(i*BondNumberOfLanes to (i+1)*BondNumberOfLanes-1), s_axis_tready => s_axis_tready(i*BondNumberOfLanes to (i+1)*BondNumberOfLanes-1) ); @@ -197,14 +197,14 @@ begin ) port map ( - clk => RX_User_Clock(i/4), - reset => rst_rxusr_403M(i/4), -- reset, + clk => RX_User_Clock(i), + reset => rst_rxusr_403M(i), -- reset, RX_Data_In => RX_Data_In_s(i*BondNumberOfLanes to (i+1)*BondNumberOfLanes-1), FlowControl => FlowControl(i*BondNumberOfLanes to (i+1)*BondNumberOfLanes-1), RX_Datavalid => RX_Datavalid_Out((i+1)*BondNumberOfLanes-1 downto i*BondNumberOfLanes), Bitslip => open, --Ignored, bitslip is handled by Transceiver_10g_64b67b_BLOCK_SYNC_SM m_axis_deburst => m_axis_deburst(i*BondNumberOfLanes to (i+1)*BondNumberOfLanes-1), - m_axis_aclk => m_axis_aclk(i/4), + m_axis_aclk => m_axis_aclk(i), m_axis => m_axis(i*BondNumberOfLanes to (i+1)*BondNumberOfLanes-1), m_axis_tready => m_axis_tready(i*BondNumberOfLanes to (i+1)*BondNumberOfLanes-1), m_axis_prog_empty => m_axis_prog_empty(i*BondNumberOfLanes to (i+1)*BondNumberOfLanes-1), @@ -247,8 +247,8 @@ begin ) port map ( dest_out(0) => Descrambler_Lock_tx(i), - dest_clk => TX_User_Clock(i/4), - src_clk => RX_User_Clock(i/4), + dest_clk => TX_User_Clock(i), + src_clk => RX_User_Clock(i), src_in(0) => Descrambler_Lock_s(i) ); diff --git a/sources/interlaken/interface/interlaken_reset.vhd b/sources/interlaken/interface/interlaken_reset.vhd index 15022052cc019e242e15dc523b6d8c5c9fe23c19..1936944c50cab18b8fe53677db59bc721079f380 100644 --- a/sources/interlaken/interface/interlaken_reset.vhd +++ b/sources/interlaken/interface/interlaken_reset.vhd @@ -14,16 +14,16 @@ entity interlaken_reset is sys_rst : in std_logic; axis_rst_ext : in std_logic; interlaken_rst_ext : in std_logic; - s_axis_aclk : in std_logic_vector(lanes/4-1 downto 0); - m_axis_aclk : in std_logic_vector(lanes/4-1 downto 0); - s_axis_aresetn : out std_logic_vector(lanes/4-1 downto 0); - m_axis_aresetn : out std_logic_vector(lanes/4-1 downto 0); + s_axis_aclk : in std_logic_vector(lanes-1 downto 0); + m_axis_aclk : in std_logic_vector(lanes-1 downto 0); + s_axis_aresetn : out std_logic_vector(lanes-1 downto 0); + m_axis_aresetn : out std_logic_vector(lanes-1 downto 0); interlaken_rst : out std_logic ); end interlaken_reset; architecture reset_logic of interlaken_reset is - signal m_axis_rst, s_axis_rst : std_logic_vector(lanes/4-1 downto 0); + signal m_axis_rst, s_axis_rst : std_logic_vector(lanes-1 downto 0); signal axis_rst, sys_rst_sync, axis_rst_sync, interlaken_rst_sync: std_logic; begin @@ -68,7 +68,7 @@ begin src_arst => axis_rst_ext -- 1-bit input: Source asynchronous reset signal. ); - g_reset: for i in 0 to lanes/4-1 generate + g_reset: for i in 0 to lanes-1 generate xpm_cdc_rst_m_axis: xpm_cdc_single generic map ( DEST_SYNC_FF => 2, @@ -77,8 +77,8 @@ begin SRC_INPUT_REG => 1 ) port map ( - dest_out => m_axis_rst(i/4), - dest_clk => m_axis_aclk(i/4), + dest_out => m_axis_rst(i), + dest_clk => m_axis_aclk(i), src_clk => clk100, src_in => axis_rst ); @@ -91,8 +91,8 @@ begin SRC_INPUT_REG => 1 ) port map ( - dest_out => s_axis_rst(i/4), - dest_clk => s_axis_aclk(i/4), + dest_out => s_axis_rst(i), + dest_clk => s_axis_aclk(i), src_clk => clk100, src_in => axis_rst ); diff --git a/sources/interlaken/interface/interlaken_top.vhd b/sources/interlaken/interface/interlaken_top.vhd index 3053bcd2b524892ea9fa05c79941a7cfb0e36867..ddb9a7be9260bc906d79562f8054015f16e7f37f 100644 --- a/sources/interlaken/interface/interlaken_top.vhd +++ b/sources/interlaken/interface/interlaken_top.vhd @@ -47,12 +47,12 @@ architecture Test of interlaken_top is signal clk150 : std_logic; signal clk300 : std_logic; - signal m_axis_aresetn : std_logic_vector(lanes/4-1 downto 0); - signal m_axis_aclk : std_logic_vector(Lanes/4-1 downto 0); + signal m_axis_aresetn : std_logic_vector(lanes-1 downto 0); + signal m_axis_aclk : std_logic_vector(Lanes-1 downto 0); signal m_axis_tready : axis_tready_array_type(0 to Lanes-1); signal s_axis : axis_64_array_type(0 to Lanes-1); - signal s_axis_aresetn : std_logic_vector(lanes/4-1 downto 0); - signal s_axis_aclk : std_logic_vector(Lanes/4-1 downto 0); + signal s_axis_aresetn : std_logic_vector(lanes-1 downto 0); + signal s_axis_aclk : std_logic_vector(Lanes-1 downto 0); signal s_axis_tready : axis_tready_array_type(0 to Lanes-1); -- @suppress "signal s_axis_tready is never read" signal m_axis : axis_64_array_type(0 to Lanes-1); -- @suppress "signal m_axis is never read" signal m_axis_prog_empty : axis_tready_array_type(0 to Lanes-1); -- @suppress "signal m_axis_prog_empty is never read" @@ -70,7 +70,7 @@ architecture Test of interlaken_top is signal burst_crc24_error : std_logic_vector(lanes-1 downto 0); -- @suppress "signal burst_crc24_error is never read" -- @suppress "signal meta_crc32_error is never read" signal meta_crc32_error : std_logic_vector(lanes-1 downto 0); -- @suppress "signal meta_crc32_error is never read" - signal tx_user_clk_out, rx_user_clk_out : std_logic_vector(Lanes/4-1 downto 0); + signal tx_user_clk_out, rx_user_clk_out : std_logic_vector(Lanes-1 downto 0); signal m_axis_burst, m_axis_deburst : axis_64_array_type(0 to Lanes - 1); signal latency_o : std_logic_vector(15 downto 0); @@ -251,7 +251,7 @@ begin -- ADD ILA s_axis_ila : ila_0 PORT MAP ( - clk => s_axis_aclk(i/4), + clk => s_axis_aclk(i), trig_out => trig_out, trig_out_ack => trig_out_ack, trig_in => trig_in, @@ -272,7 +272,7 @@ begin m_axis_ila : ila_1 PORT MAP ( - clk => m_axis_aclk(i/4), + clk => m_axis_aclk(i), trig_out => trig_in, trig_out_ack => trig_in_ack, trig_in => trig_out, diff --git a/sources/interlaken/test/axis_data_generator.vhd b/sources/interlaken/test/axis_data_generator.vhd index 69f75c453081355dd8b4db26ef3fea938dcb6ad0..0eef74e63f60b9c8ea9b940511dd6d208ca8513e 100644 --- a/sources/interlaken/test/axis_data_generator.vhd +++ b/sources/interlaken/test/axis_data_generator.vhd @@ -11,10 +11,10 @@ entity axis_data_generator is lanes : positive := 1 ); Port ( - s_axis_aclk : in std_logic_vector(Lanes/4-1 downto 0); - m_axis_aclk : in std_logic_vector(Lanes/4-1 downto 0); - s_axis_aresetn : in std_logic_vector(lanes/4-1 downto 0); - m_axis_aresetn : in std_logic_vector(lanes/4-1 downto 0); + s_axis_aclk : in std_logic_vector(Lanes-1 downto 0); + m_axis_aclk : in std_logic_vector(Lanes-1 downto 0); + s_axis_aresetn : in std_logic_vector(lanes-1 downto 0); + m_axis_aresetn : in std_logic_vector(lanes-1 downto 0); s_axis : out axis_64_array_type(0 to Lanes-1); s_axis_tready : in axis_tready_array_type(0 to Lanes-1); @@ -57,8 +57,8 @@ begin ) port map ( dest_out => HealthLane_sync(i), -- 1-bit output: src_in synchronized to the destination clock domain. This output is registered. - dest_clk => s_axis_aclk(i/4), -- 1-bit input: Clock signal for the destination clock domain. - src_clk => m_axis_aclk(i/4), -- 1-bit input: optional; required when SRC_INPUT_REG = 1 + dest_clk => s_axis_aclk(i), -- 1-bit input: Clock signal for the destination clock domain. + src_clk => m_axis_aclk(i), -- 1-bit input: optional; required when SRC_INPUT_REG = 1 src_in => HealthLane(i) -- 1-bit input: Input signal to be synchronized to dest_clk domain. ); end generate; @@ -78,7 +78,7 @@ begin --variable count : integer; begin - if s_axis_aresetn(i/4) = '0' then + if s_axis_aresetn(i) = '0' then tdata_t1 <= (others => '0'); --for i in 0 to Lanes-1 loop @@ -87,7 +87,7 @@ begin --end loop; count <= 1; packet_num <= 1; - elsif rising_edge (s_axis_aclk(i/4)) then + elsif rising_edge (s_axis_aclk(i)) then if HealthLane_sync(i) = '1' then --for i in 0 to Lanes-1 loop s_axis(i).tvalid <= '1'; @@ -133,7 +133,7 @@ begin check_data : process(m_axis_aresetn, m_axis_aclk) variable packet_num_v, count_v : integer; begin - if m_axis_aresetn(i/4) = '0' then + if m_axis_aresetn(i) = '0' then packet_num_rx <= 1; count_rx <= 1; count_v := 0; @@ -141,7 +141,7 @@ begin valid(i) <= '0'; pkt_error_count(i) <= 0; wrd_error_count(i) <= 0; - elsif rising_edge (m_axis_aclk(i/4)) then + elsif rising_edge (m_axis_aclk(i)) then --for i in 0 to Lanes-1 loop if m_axis(i).tvalid = '1' then valid(i) <= '0'; diff --git a/sources/interlaken/transceiver/interlaken_gty.vhd b/sources/interlaken/transceiver/interlaken_gty.vhd index d27a8a7702b37e37784adf22736d56dc623ead8d..df2d044308e818cd6058531ac9e7d2769806c821 100644 --- a/sources/interlaken/transceiver/interlaken_gty.vhd +++ b/sources/interlaken/transceiver/interlaken_gty.vhd @@ -18,8 +18,8 @@ entity interlaken_gty is ); Port ( reset : in std_logic; - rst_txusr_403M_s : out std_logic_vector(Lanes/4-1 downto 0); - rst_rxusr_403M_s : out std_logic_vector(Lanes/4-1 downto 0); + rst_txusr_403M_s : out std_logic_vector(Lanes-1 downto 0); + rst_rxusr_403M_s : out std_logic_vector(Lanes-1 downto 0); -------- 156.25 MHz input, to transceiver (QSFP clock)----------- GTREFCLK_IN_P : in std_logic_vector(GTREFCLKS-1 downto 0); @@ -35,25 +35,25 @@ entity interlaken_gty is RX_In_N : in std_logic_vector(Lanes-1 downto 0); ------------- Output clocks sync. to TX/RX ---------------------- - TX_User_Clock_s : out std_logic_vector(Lanes/4-1 downto 0); - RX_User_Clock_s : out std_logic_vector(Lanes/4-1 downto 0); + TX_User_Clock_s : out std_logic_vector(Lanes-1 downto 0); + RX_User_Clock_s : out std_logic_vector(Lanes-1 downto 0); loopback_in : in std_logic_vector(2 downto 0); ------------------ User data in/out ----------------------------- - Data_Transceiver_In : in slv_64_array(0 to Lanes-1); + Data_Transceiver_In : in slv_64_array(0 to Lanes-1); Data_Transceiver_Out : out slv_64_array(0 to Lanes-1); RX_Datavalid_Out : out std_logic_vector(Lanes-1 downto 0); RX_Header_Out_s : out slv_3_array(0 to Lanes-1); RX_Headervalid_Out_s : out std_logic_vector(Lanes-1 downto 0); TX_Gearboxready_Out : out std_logic_vector(Lanes-1 downto 0); - TX_Header_In : in slv_3_array(0 to Lanes-1) + TX_Header_In : in slv_3_array(0 to Lanes-1) ); end interlaken_gty; architecture Behavioral of interlaken_gty is - signal TX_User_Clock, RX_User_Clock : std_logic_vector(Lanes/4-1 downto 0); + signal TX_User_Clock, RX_User_Clock : std_logic_vector(Lanes-1 downto 0); signal RX_Header_Out : slv_3_array(0 to Lanes-1); signal RX_Headervalid_Out : std_logic_vector(Lanes-1 downto 0); @@ -75,8 +75,8 @@ architecture Behavioral of interlaken_gty is -- signal tx_active_sync, tx_active_meta : std_logic; -- signal rx_active_sync, rx_active_meta : std_logic; signal gtwiz_userclk_rx_active_in ,gtwiz_userclk_tx_active_in : std_logic_vector((Lanes/4)-1 downto 0); - signal tx_gearbox_reset, rx_gearbox_reset : std_logic_vector((Lanes/4)-1 downto 0); - signal rst_txusr_403M, rst_rxusr_403M : std_logic_vector(Lanes/4-1 downto 0); + signal tx_gearbox_reset, rx_gearbox_reset : std_logic_vector(Lanes-1 downto 0); + signal rst_txusr_403M, rst_rxusr_403M : std_logic_vector(Lanes-1 downto 0); signal gtwiz_reset_rx_done_out : std_logic_vector((Lanes/4)-1 downto 0); signal GTREFCLK_VERSAL_BUF, GTREFCLK_VERSAL_SEL: std_logic_vector(Lanes/4-1 downto 0); @@ -148,9 +148,10 @@ begin TX_Out_P(quad*4+3 downto quad*4) <= gtytxp_out; rxgearboxslip_in <= RX_Gearboxslip_In(quad*4+3 downto quad*4); - txusrclk_in <= (others => TX_User_Clock(quad)); + + txusrclk_in <= TX_User_Clock(quad*4+3 downto quad*4); txusrclk2_in <= txusrclk_in; --Datapath 64b and intw 2; ug578 p105 - rxusrclk_in <= (others => RX_User_Clock(quad)); + rxusrclk_in <= RX_User_Clock(quad*4+3 downto quad*4); rxusrclk2_in <= rxusrclk_in; --Datapath 64b and intw 2; ug578 p105 --TEMPREMOVE @@ -220,31 +221,33 @@ begin gt_txsequence_i(quad*4+0); - loopback <= loopback_in&loopback_in&loopback_in&loopback_in; + loopback <= loopback_in & loopback_in & loopback_in & loopback_in; - INST_RST_TXUSR : xpm_cdc_async_rst - generic map ( - DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10 - INIT_SYNC_FF => 1, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values - RST_ACTIVE_HIGH => 1 -- DECIMAL; 0=active low reset, 1=active high reset - ) - port map ( - dest_arst => rst_txusr_403M(quad), -- 1-bit output: src_arst asynchronous reset signal synchronized to destination clock domain. - dest_clk => TX_User_Clock(quad), -- 1-bit input: Destination clock. - src_arst => reset -- 1-bit input: Source asynchronous reset signal. - ); - - INST_RST_RXUSR : xpm_cdc_async_rst - generic map ( - DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10 - INIT_SYNC_FF => 1, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values - RST_ACTIVE_HIGH => 1 -- DECIMAL; 0=active low reset, 1=active high reset - ) - port map ( - dest_arst => rst_rxusr_403M(quad), -- 1-bit output: src_arst asynchronous reset signal synchronized to destination clock domain. - dest_clk => RX_User_Clock(quad), -- 1-bit input: Destination clock. - src_arst => reset -- 1-bit input: Source asynchronous reset signal. - ); + g_resetsync: for i in 0 to 3 generate + INST_RST_TXUSR : xpm_cdc_async_rst + generic map ( + DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10 + INIT_SYNC_FF => 1, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values + RST_ACTIVE_HIGH => 1 -- DECIMAL; 0=active low reset, 1=active high reset + ) + port map ( + dest_arst => rst_txusr_403M(quad*4+i), -- 1-bit output: src_arst asynchronous reset signal synchronized to destination clock domain. + dest_clk => TX_User_Clock(quad*4+i), -- 1-bit input: Destination clock. + src_arst => reset -- 1-bit input: Source asynchronous reset signal. + ); + + INST_RST_RXUSR : xpm_cdc_async_rst + generic map ( + DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10 + INIT_SYNC_FF => 1, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values + RST_ACTIVE_HIGH => 1 -- DECIMAL; 0=active low reset, 1=active high reset + ) + port map ( + dest_arst => rst_rxusr_403M(quad*4+i), -- 1-bit output: src_arst asynchronous reset signal synchronized to destination clock domain. + dest_clk => RX_User_Clock(quad*4+i), -- 1-bit input: Destination clock. + src_arst => reset -- 1-bit input: Source asynchronous reset signal. + ); + end generate; g_ultrascale : if CARD_TYPE = 128 generate -------------------------- Include Transceiver ----------------------------- @@ -344,30 +347,30 @@ begin ); --end generate; ------------------------------- Buffering tx/rx out clock signals -------------------------------- - --g_clockbuffers: for i in 0 to Lanes-1 generate + g_clockbuffers: for i in 0 to 3 generate BUFG_GT_TXclk : BUFG_GT port map ( - O => TX_User_Clock(quad), + O => TX_User_Clock(quad*4+i), CE => '1', CEMASK => '0', - CLR => not_TX_Resetdone_Out(quad*4), --NOT_TX_Resetdone_Out + CLR => not_TX_Resetdone_Out(quad*4+i), --NOT_TX_Resetdone_Out CLRMASK => '0', DIV => "000", - I => txoutclk_out(quad*4) + I => txoutclk_out(quad*4+i) ); BUFG_GT_RXclk : BUFG_GT port map ( - O => RX_User_Clock(quad), + O => RX_User_Clock(quad*4+i), CE => '1', CEMASK => '0', - CLR => not_RX_Resetdone_Out(quad*4), + CLR => not_RX_Resetdone_Out(quad*4+i), CLRMASK => '0', DIV => "000", - I => rxoutclk_out(quad*4) + I => rxoutclk_out(quad*4+i) ); - --end generate; + end generate; -------------------------------- Buffering QSFP GT clock ------------------------------------- IBUFDS_GTE4_inst : IBUFDS_GTE4 @@ -674,8 +677,8 @@ begin ) port map ( dest_rst => not_TX_Resetdone_Out_tx_User_clock, - dest_clk => TX_User_Clock(quad), - src_rst => not_TX_Resetdone_Out(quad) + dest_clk => TX_User_Clock(quad*4), + src_rst => not_TX_Resetdone_Out(quad*4) ); xpm_cdc_sync_rst_inst_not_rx_resetdone_out : xpm_cdc_sync_rst generic map ( @@ -686,8 +689,8 @@ begin ) port map ( dest_rst => not_RX_Resetdone_Out_rx_User_clock, - dest_clk => RX_User_Clock(quad), - src_rst => not_RX_Resetdone_Out(quad) + dest_clk => RX_User_Clock(quad*4), + src_rst => not_RX_Resetdone_Out(quad*4) ); ------------------------------ Set GTY active signals --------------------------------------- --! FS: TX_Resetdone_Out and RX_Resetdone_out prepended with not_ because they are inverted @@ -697,7 +700,7 @@ begin if not_TX_Resetdone_Out_tx_User_clock = '1' then tx_active_meta <= '0'; tx_active_sync <= '0'; - elsif rising_edge(TX_User_Clock(quad)) then + elsif rising_edge(TX_User_Clock(quad*4)) then tx_active_meta <= '1'; tx_active_sync <= tx_active_meta; end if; @@ -708,7 +711,7 @@ begin if not_RX_Resetdone_Out_rx_User_clock = '1' then rx_active_meta <= '0'; rx_active_sync <= '0'; - elsif rising_edge(RX_User_Clock(quad)) then + elsif rising_edge(RX_User_Clock(quad*4)) then rx_active_meta <= '1'; @@ -718,47 +721,64 @@ begin end process; ------------------------------- Gearbox reset ------------------------------------- - tx_gearbox_reset_i <= rst_txusr_403M(quad) or not gtwiz_userclk_tx_active_in(quad); - rx_gearbox_reset_i <= rst_rxusr_403M(quad) or not gtwiz_reset_rx_done_out(quad); +-- tx_gearbox_reset_i <= rst_txusr_403M(quad) or not gtwiz_userclk_tx_active_in(quad); --gtwiz_userclk_tx_active_in from clk100 to txuserclk(i) +-- rx_gearbox_reset_i <= rst_rxusr_403M(quad) or not gtwiz_reset_rx_done_out(quad); - tx_gearbox_reset_sync_inst : xpm_cdc_single - generic map ( - DEST_SYNC_FF => 2, - INIT_SYNC_FF => 0, - SIM_ASSERT_CHK => 0, - SRC_INPUT_REG => 0 - ) - port map ( - dest_out => tx_gearbox_reset(quad), - dest_clk => TX_User_Clock(quad), - src_clk => clk100, - src_in => tx_gearbox_reset_i - ); - - rx_gearbox_reset_sync_inst : xpm_cdc_single - generic map ( - DEST_SYNC_FF => 2, - INIT_SYNC_FF => 0, - SIM_ASSERT_CHK => 0, - SRC_INPUT_REG => 0 - ) - port map ( - dest_out => rx_gearbox_reset(quad), - dest_clk => RX_User_Clock(quad), - src_clk => clk100, - src_in => rx_gearbox_reset_i - ); +-- tx_gearbox_reset_sync_inst : xpm_cdc_single +-- generic map ( +-- DEST_SYNC_FF => 2, +-- INIT_SYNC_FF => 0, +-- SIM_ASSERT_CHK => 0, +-- SRC_INPUT_REG => 0 +-- ) +-- port map ( +-- dest_out => tx_gearbox_reset(quad), +-- dest_clk => TX_User_Clock(quad*4), +-- src_clk => clk100, +-- src_in => tx_gearbox_reset_i +-- ); +-- rx_gearbox_reset_sync_inst : xpm_cdc_single +-- generic map ( +-- DEST_SYNC_FF => 2, +-- INIT_SYNC_FF => 0, +-- SIM_ASSERT_CHK => 0, +-- SRC_INPUT_REG => 0 +-- ) +-- port map ( +-- dest_out => rx_gearbox_reset(quad), +-- dest_clk => RX_User_Clock(quad*4), +-- src_clk => clk100, +-- src_in => rx_gearbox_reset_i +-- ); + + +-- tx_gearbox_active_sync_inst : xpm_cdc_single +-- generic map ( +-- DEST_SYNC_FF => 2, +-- INIT_SYNC_FF => 0, +-- SIM_ASSERT_CHK => 0, +-- SRC_INPUT_REG => 0 +-- ) +-- port map ( +-- dest_out => gtwiz_userclk_tx_active_sync(i), +-- dest_clk => TX_User_Clock(i), +-- src_clk => clk100, +-- src_in => gtwiz_userclk_tx_active_in(i/4) +-- ); +-- tx_gearbox_reset <= rst_txusr_403M(i) or not gtwiz_userclk_tx_active_sync(i); end generate g_quads; ------------------------------- Gearbox logic ------------------------------------- g_gearbox: for i in 0 to Lanes-1 generate + signal gtwiz_userclk_tx_active_sync, gtwiz_reset_rx_done_out_sync : std_logic_vector(lanes-1 downto 0); + begin gt_data_valid_out_i(i) <= '1' when ((gt_txsequence_i(i) /= "0010101") and (gt_txsequence_i(i) /= "0101011") and (gt_txsequence_i(i) /= "1000001")) else '0'; process(TX_User_Clock) begin - if rising_edge (TX_User_Clock(i/4)) then + if rising_edge (TX_User_Clock(i)) then gt_pause_data_valid_r(i) <= gt_data_valid_out_i(i) ; end if; end process; @@ -768,8 +788,9 @@ begin ------------------------------- TX Gearbox sequencer ------------------------------------- process(TX_User_Clock) begin - if rising_edge (TX_User_Clock(i/4)) then - if((tx_gearbox_reset(i/4)='1') or (gt_txseq_counter_r(i) = 133)) then--66)) then + if rising_edge (TX_User_Clock(i)) then + tx_gearbox_reset(i) <= rst_txusr_403M(i) or not gtwiz_userclk_tx_active_sync(i); + if((tx_gearbox_reset(i)='1') or (gt_txseq_counter_r(i) = 133)) then--66)) then gt_txseq_counter_r(i) <= (others => '0') ; else gt_txseq_counter_r(i) <= gt_txseq_counter_r(i) + 1 ; @@ -779,6 +800,44 @@ begin gt_txsequence_i(i) <= std_logic_vector(gt_txseq_counter_r(i)(7 downto 1)); --(6 downto 0)); --rx_gearbox_reset <= rst_rxusr_403M or not gtwiz_reset_rx_done_out(0); --rx_gearbox_reset <= reset or not gtwiz_reset_rx_done_out(0); + --tx_gearbox_reset(i) <= rst_txusr_403M(i) or not gtwiz_userclk_tx_active_sync(i); + --rx_gearbox_reset(i) <= rst_rxusr_403M(i) or not gtwiz_reset_rx_done_out_sync(i); + + process(RX_User_Clock) + begin + if rising_edge (RX_User_Clock(i)) then + rx_gearbox_reset(i) <= rst_rxusr_403M(i) or not gtwiz_reset_rx_done_out_sync(i); + end if; + end process; + + tx_gearbox_active_sync_inst : xpm_cdc_single + generic map ( + DEST_SYNC_FF => 2, + INIT_SYNC_FF => 0, + SIM_ASSERT_CHK => 0, + SRC_INPUT_REG => 0 + ) + port map ( + dest_out => gtwiz_userclk_tx_active_sync(i), + dest_clk => TX_User_Clock(i), + src_clk => clk100, + src_in => gtwiz_userclk_tx_active_in(i/4) + ); + + rx_gearbox_reset_sync_inst : xpm_cdc_single + generic map ( + DEST_SYNC_FF => 2, + INIT_SYNC_FF => 0, + SIM_ASSERT_CHK => 0, + SRC_INPUT_REG => 0 + ) + port map ( + dest_out => gtwiz_reset_rx_done_out_sync(i), + dest_clk => RX_User_Clock(i), + src_clk => clk100, + src_in => gtwiz_reset_rx_done_out(i/4) + ); + ------------------------------- RX Gearbox bitslip -- ------------------------------------- block_sync_sm_0_i : entity work.Transceiver_10g_64b67b_BLOCK_SYNC_SM @@ -797,8 +856,8 @@ begin RXHEADERVALID_IN => RX_Headervalid_Out(i), -- System Interface - USER_CLK => RX_User_Clock(i/4), - SYSTEM_RESET => rx_gearbox_reset(i/4) + USER_CLK => RX_User_Clock(i), + SYSTEM_RESET => rx_gearbox_reset(i) ); end generate;