diff --git a/scripts/filesets/core1990_interlaken_fileset.tcl b/scripts/filesets/core1990_interlaken_fileset.tcl
index 505f864bfbe1ff218401a806a54b327ec92dc22d..9282936848d50e933f042693578d86523408f482 100644
--- a/scripts/filesets/core1990_interlaken_fileset.tcl
+++ b/scripts/filesets/core1990_interlaken_fileset.tcl
@@ -16,7 +16,6 @@ set VHDL_FILES [concat $VHDL_FILES \
     interlaken/transmitter/scrambler.vhd \
     interlaken/transmitter/framing_burst.vhd \
     interlaken/interface/interlaken_interface.vhd \
-    interlaken/interface/interlaken_top.vhd \
     interlaken/interface/interlaken_reset.vhd \
     interlaken/test/axis_data_generator.vhd \
     interlaken/crc/crc-24.vhd \
@@ -37,12 +36,6 @@ set VHDL_FILES [concat $VHDL_FILES \
 #set SIM_FILES [concat $SIM_FILES \
 #    interlaken_top_tb.vhd ]
 
-if {$MEZZANINE == true} {     
-    set VHDL_FILES [concat $VHDL_FILES interlaken/interface/interlaken_top_mezzanine.vhd ]
-} else {
-	set VHDL_FILES [concat $VHDL_FILES interlaken/interface/interlaken_top.vhd ]
-}
-
 set VHDL_FILES_VERSAL [concat $VHDL_FILES_VERSAL \
     interlaken/transceiver/txgearbox_64b67b.vhd \
     interlaken/transceiver/rxgearbox_64b67b.vhd \
@@ -155,8 +148,8 @@ set BD_FILES_VPK180 [concat $BD_FILES_VPK180 \
 set BD_FILES_VP1802 [concat $BD_FILES_VP1802 \
   cips_bd.bd \
   transceiver_versal_interlaken_raw_gtm.bd]
-
+  
 set SIM_FILES [concat $SIM_FILES \
-     ../sources/interlaken/test/interlaken_top_tb.vhd]
+     ../simulation/UVVMtests/tb/interlaken_top_tb_uvvm.vhd]
 
 
diff --git a/scripts/filesets/interlaken_top_fileset.tcl b/scripts/filesets/interlaken_top_fileset.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..fbcb850fc4f4b409fc224e63002262bf45e1708b
--- /dev/null
+++ b/scripts/filesets/interlaken_top_fileset.tcl
@@ -0,0 +1,9 @@
+set VHDL_FILES [concat $VHDL_FILES \
+    interlaken/interface/interlaken_top.vhd 
+]
+
+if {$MEZZANINE == true} {     
+    set VHDL_FILES [concat $VHDL_FILES interlaken/interface/interlaken_top_mezzanine.vhd ]
+} else {
+	set VHDL_FILES [concat $VHDL_FILES interlaken/interface/interlaken_top.vhd ]
+}
diff --git a/scripts/interlaken_top/FLX128_import_vivado.tcl b/scripts/interlaken_top/FLX128_import_vivado.tcl
index ac3fc273b2ec09ba4185a1b97023ae3ff14c2425..e9f09912be26b3efbf32b1e7a220515df94235d9 100644
--- a/scripts/interlaken_top/FLX128_import_vivado.tcl
+++ b/scripts/interlaken_top/FLX128_import_vivado.tcl
@@ -11,6 +11,7 @@ set TOPLEVEL interlaken_top
 set MEZZANINE false
 #Import blocks for different filesets
 source ../filesets/core1990_interlaken_fileset.tcl
+source ../filesets/interlaken_top_fileset.tcl
 
 #import block designs
 
diff --git a/scripts/interlaken_top/FLX182_import_vivado.tcl b/scripts/interlaken_top/FLX182_import_vivado.tcl
index 73dccfe4749585c9bfed46988d4fe7b8ef199ee0..cdd7c87efce807a76f4886ea70e95e9870ae165a 100644
--- a/scripts/interlaken_top/FLX182_import_vivado.tcl
+++ b/scripts/interlaken_top/FLX182_import_vivado.tcl
@@ -11,6 +11,7 @@ set TOPLEVEL interlaken_top
 
 #Import blocks for different filesets
 source ../filesets/core1990_interlaken_fileset.tcl
+source ../filesets/interlaken_top_fileset.tcl
 
 #Actually execute all the filesets
 source ../helper/vivado_import_generic.tcl
diff --git a/scripts/interlaken_top/VCU108_import_vivado.tcl b/scripts/interlaken_top/VCU108_import_vivado.tcl
index 115042fd9b2e354ed72af0b5fc0323549f52c7d5..e930e3a65052c278aef9a15597e973846938cd77 100644
--- a/scripts/interlaken_top/VCU108_import_vivado.tcl
+++ b/scripts/interlaken_top/VCU108_import_vivado.tcl
@@ -11,6 +11,7 @@ set TOPLEVEL interlaken_top
 
 #Import blocks for different filesets
 source ../filesets/core1990_interlaken_fileset.tcl
+source ../filesets/interlaken_top_fileset.tcl
 
 #Actually execute all the filesets
 source ../helper/vivado_import_generic.tcl
diff --git a/scripts/interlaken_top/VCU118_import_vivado.tcl b/scripts/interlaken_top/VCU118_import_vivado.tcl
index 10f86fea34b028d6dcb1325f0e1e257ded49d86e..f69dd2e29dbb0a7a37b9fa276aa3b20329798919 100644
--- a/scripts/interlaken_top/VCU118_import_vivado.tcl
+++ b/scripts/interlaken_top/VCU118_import_vivado.tcl
@@ -12,6 +12,7 @@ set MEZZANINE false
 
 #Import blocks for different filesets
 source ../filesets/core1990_interlaken_fileset.tcl
+source ../filesets/interlaken_top_fileset.tcl
 
 #Actually execute all the filesets
 source ../helper/vivado_import_generic.tcl
diff --git a/scripts/interlaken_top/VP1802_import_vivado.tcl b/scripts/interlaken_top/VP1802_import_vivado.tcl
index ad343787334f3dde0a7ecb5b269ef83b96540539..b7088b023742d90dfbafdb1d8f8f99abc9faaa74 100644
--- a/scripts/interlaken_top/VP1802_import_vivado.tcl
+++ b/scripts/interlaken_top/VP1802_import_vivado.tcl
@@ -11,6 +11,7 @@ set TOPLEVEL interlaken_top
 set MEZZANINE false
 #Import blocks for different filesets
 source ../filesets/core1990_interlaken_fileset.tcl
+source ../filesets/interlaken_top_fileset.tcl
 
 #Actually execute all the filesets
 source ../helper/vivado_import_generic.tcl
diff --git a/scripts/interlaken_top/VPK180_import_vivado.tcl b/scripts/interlaken_top/VPK180_import_vivado.tcl
index 05af64bfcf6aa7022baba8153bb8dd710d436bd4..9d7b86e8aac2459d96f03dabedc7d81b5bc6bb7d 100644
--- a/scripts/interlaken_top/VPK180_import_vivado.tcl
+++ b/scripts/interlaken_top/VPK180_import_vivado.tcl
@@ -11,6 +11,7 @@ set TOPLEVEL interlaken_top
 set MEZZANINE false
 #Import blocks for different filesets
 source ../filesets/core1990_interlaken_fileset.tcl
+source ../filesets/interlaken_top_fileset.tcl
 
 #Actually execute all the filesets
 source ../helper/vivado_import_generic.tcl
diff --git a/sources/interlaken/receiver/interlaken_receiver_channel.vhd b/sources/interlaken/receiver/interlaken_receiver_channel.vhd
index 160479dd82b72e19a711111932ff5c46fc1f3f65..79bb2b08b7d13f8b50cf115a08a754d9f576267e 100644
--- a/sources/interlaken/receiver/interlaken_receiver_channel.vhd
+++ b/sources/interlaken/receiver/interlaken_receiver_channel.vhd
@@ -48,7 +48,7 @@ architecture receiver of interlaken_receiver_channel is
     signal axis_tready  : std_logic;
     signal axis : axis_64_type;
     
-    signal rx_packet_count, rx_byte_count : integer range 0 to 65536; -- 16 bit integer
+    --signal rx_packet_count, rx_byte_count : integer range 0 to 65536; -- 16 bit integer
     signal crc24_count, crc32_count : unsigned(15 downto 0);
     
 begin
@@ -111,26 +111,26 @@ begin
                 m_axis_prog_empty => m_axis_prog_empty      --: out std_logic
             );
             
-         stats: process (reset, clk)
-         begin
-             if reset = '1' then
-                rx_packet_count <= 0;
-                rx_byte_count <= 0;
+         --stats: process (reset, clk)
+         --begin
+             --if reset = '1' then
+                --rx_packet_count <= 0;
+                --rx_byte_count <= 0;
              
-             elsif rising_edge(clk) then
-                if m_axis_tready = '1' then
+             --elsif rising_edge(clk) then
+                --if m_axis_tready = '1' then
 
-                    if axis.tlast = '1' then
-                        rx_packet_count <= rx_packet_count + 1;
-                    end if;
+                    --if axis.tlast = '1' then
+                        --rx_packet_count <= rx_packet_count + 1;
+                    --end if;
                     
-                    if axis.tvalid = '1' then
-                        rx_byte_count <= rx_byte_count + 8;
-                    end if;
-                 end if;   
-             end if;
+                    --if axis.tvalid = '1' then
+                        --rx_byte_count <= rx_byte_count + 8;
+                    --end if;
+                 --end if;   
+             --end if;
          
-         end process;
+         --end process;
          
          crc_counters: process (reset, clk)
          begin
diff --git a/sources/interlaken/test/axis_data_generator.vhd b/sources/interlaken/test/axis_data_generator.vhd
index cfc6581424128d986f01e270bc277b51b6ec92e0..102b0bdad2f6da546adaf4685276f35306f33014 100644
--- a/sources/interlaken/test/axis_data_generator.vhd
+++ b/sources/interlaken/test/axis_data_generator.vhd
@@ -130,7 +130,7 @@ begin
     end generate;
     
     g_check: for i in 0 to Lanes-1 generate
-        signal packet_num_rx, count_rx : integer;--unsigned(31 downto 0);
+        signal packet_num_rx, count_rx : integer := 0;--unsigned(31 downto 0);
         
     begin
         check_data : process(m_axis_aresetn, m_axis_aclk)