diff --git a/sources/templates/dma_control.vhd b/sources/templates/dma_control.vhd
index 0bf88db54b45a9fbed18833f4b80e12f68165f94..f736cfc031c501b36817c13709abdb8b086a3486 100644
--- a/sources/templates/dma_control.vhd
+++ b/sources/templates/dma_control.vhd
@@ -5951,6 +5951,7 @@ end process;
-- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
--
+ register_map_control_s.TTC_DEC_CTRL.L1A_DELAY <= REG_TTC_DEC_CTRL_L1A_DELAY_C; -- Number of BC to delay the L1A distribution to the frontends
register_map_control_s.TTC_DEC_CTRL.BCID_ONBCR <= REG_TTC_DEC_CTRL_BCID_ONBCR_C; -- BCID is set to this value when BCR arrives
register_map_control_s.TTC_DEC_CTRL.ECR_BCR_SWAP <= REG_TTC_DEC_CTRL_ECR_BCR_SWAP_C; -- ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
register_map_control_s.TTC_DEC_CTRL.BUSY_OUTPUT_INHIBIT <= REG_TTC_DEC_CTRL_BUSY_OUTPUT_INHIBIT_C; -- forces the Busy LEMO output to BUSY-OFF
@@ -7882,6 +7883,8 @@ end process;
register_map_control_s.WISHBONE_CONTROL.WRITE_NOT_READ <= REG_WISHBONE_CONTROL_WRITE_NOT_READ_C; -- wishbone write command wishbone read command
register_map_control_s.WISHBONE_CONTROL.ADDRESS <= REG_WISHBONE_CONTROL_ADDRESS_C; -- Slave address for Wishbone bus
register_map_control_s.WISHBONE_WRITE.DATA <= REG_WISHBONE_WRITE_DATA_C; -- Wishbone
+ register_map_control_s.GLOBAL_STRIPS_CONFIG.TEST_MODULE_MASK <= REG_GLOBAL_STRIPS_CONFIG_TEST_MODULE_MASK_C; -- (for tests only) contains R3 mask for the simulated trigger data
+ register_map_control_s.GLOBAL_STRIPS_CONFIG.TEST_R3L1_TAG <= REG_GLOBAL_STRIPS_CONFIG_TEST_R3L1_TAG_C; -- (for tests only) contains R3 or L1 tag for the simulated trigger data
register_map_control_s.GLOBAL_STRIPS_CONFIG.TTC_GENERATE_GATING_ENABLE <= REG_GLOBAL_STRIPS_CONFIG_TTC_GENERATE_GATING_ENABLE_C; -- Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR. TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work. (See also BC_START, and BC_STOP fields)
if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
register_map_control_s.LCB_CTRL (0)(0).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_0_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
@@ -10075,26313 +10078,15336 @@ end process;
if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
register_map_control_s.R3L1_CTRL (3)(3).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_03_R3L1_3_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(0).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(0).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(0).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(0).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(0).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(0).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(0).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(0).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(0).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(0).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(0).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(0).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(0).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_0_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(0).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(0).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(0).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(0).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(0).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(0).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(0).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(0).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(0).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(0).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(0).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(0).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(0).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(0).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(0).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(1).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(1).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(1).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(1).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(1).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(1).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(1).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(1).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(1).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(1).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(1).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(1).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(1).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_1_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(1).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(1).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(1).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(1).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(1).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(1).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(1).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(1).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(1).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(1).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(1).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(1).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(1).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(1).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(1).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(2).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(2).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(2).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(2).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(2).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(2).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(2).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(2).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(2).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(2).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(2).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(2).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(2).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_2_HCC_MASK_C; -- HCC* module mask
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_CTRL.OPTIONS <= REG_MROD_CTRL_OPTIONS_C; -- Extra options for MROD
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(2).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_CTRL.GOLTESTMODE <= REG_MROD_CTRL_GOLTESTMODE_C; -- GOL Test Mode (emulate CSM):
+ -- 0: Run Data Emulator when 1; 0: stop, load emulator fifo
+ -- 1: Enable Circulate when 1; 0: send fifo data only once
+ -- 2: Enable Triggered Mode when 1; 0: run continueously (no TTC)
+ -- 3: Enable pattern generator when 1; 0: off
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(2).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP0_CSMENABLE <= REG_MROD_EP0_CSMENABLE_C; -- EP0 CSM Data Enable channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(2).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP0_EMPTYSUPPR <= REG_MROD_EP0_EMPTYSUPPR_C; -- EP0 Set Empty Suppression channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(2).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP0_HPTDCMODE <= REG_MROD_EP0_HPTDCMODE_C; -- EP0 Set HPTDC Mode channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(2).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP0_CLRFIFOS <= REG_MROD_EP0_CLRFIFOS_C; -- EP0 Clear FIFOs channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(2).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP0_EMULOADENA <= REG_MROD_EP0_EMULOADENA_C; -- EP0 Emulator Load Enable channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(2).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP0_TRXLOOPBACK <= REG_MROD_EP0_TRXLOOPBACK_C; -- EP0 Transceiver Loopback Enable channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(2).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP0_TXCVRRESET <= REG_MROD_EP0_TXCVRRESET_C; -- EP0 Transceiver Reset all channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(2).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP0_RXRESET <= REG_MROD_EP0_RXRESET_C; -- EP0 Receiver Reset channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(2).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP0_TXRESET <= REG_MROD_EP0_TXRESET_C; -- EP0 Transmitter Reset channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(2).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP1_CSMENABLE <= REG_MROD_EP1_CSMENABLE_C; -- EP1 CSM Data Enable channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(2).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP1_EMPTYSUPPR <= REG_MROD_EP1_EMPTYSUPPR_C; -- EP1 Set Empty Suppression channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(2).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP1_HPTDCMODE <= REG_MROD_EP1_HPTDCMODE_C; -- EP1 Set HPTDC Mode channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(2).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP1_CLRFIFOS <= REG_MROD_EP1_CLRFIFOS_C; -- EP1 Clear FIFOs channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(2).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP1_EMULOADENA <= REG_MROD_EP1_EMULOADENA_C; -- EP1 Emulator Load Enable channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(3).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP1_TRXLOOPBACK <= REG_MROD_EP1_TRXLOOPBACK_C; -- EP1 Transceiver Loopback Enable channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(3).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP1_TXCVRRESET <= REG_MROD_EP1_TXCVRRESET_C; -- EP1 Transceiver Reset all channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(3).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP1_RXRESET <= REG_MROD_EP1_RXRESET_C; -- EP1 Receiver Reset channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(3).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ if MROD_GENERATE_REGS = true then
+ register_map_control_s.MROD_EP1_TXRESET <= REG_MROD_EP1_TXRESET_C; -- EP1 Transmitter Reset channel 23-0
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(3).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ -----------------------------------
+ ---- GENERATED code END #1 ## ----
+ -----------------------------------
+ else
+
+ for i in 0 to NUMBER_OF_DESCRIPTORS-1 loop
+ if(dma_descriptors_25_r_s(i).enable = '1') then
+ if(last_pc_pointer_v(i) > dma_descriptors_25_w_s(i).pc_pointer + pc_ptr_gap_25_s) then --If the current pc_pointer is 16MB smaller than the last one, we change cycles. The 16MB can be changed in the register PC_PTR_GAP (bar0).
+ dma_descriptors_25_w_s(i).evencycle_pc <= not dma_descriptors_25_w_s(i).evencycle_pc; --Toggle on wrap around
end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(3).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(3).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(3).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(3).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(3).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(3).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(3).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(3).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_3_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(3).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(3).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(4)(3).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(3).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(3).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(3).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(4)(3).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(3).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(3).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(3).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(4)(3).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(3).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(3).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(3).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(4)(3).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(0).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_04_R3L1_0_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(0).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_04_R3L1_0_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(0).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_04_R3L1_0_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(1).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_04_R3L1_1_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(1).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_04_R3L1_1_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(1).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_04_R3L1_1_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(2).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_04_R3L1_2_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(2).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_04_R3L1_2_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(2).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_04_R3L1_2_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(3).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_04_R3L1_3_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(3).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_04_R3L1_3_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(3).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_04_R3L1_3_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(0).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(0).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(0).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(0).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(0).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(0).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(0).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(0).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(0).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(0).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(0).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(0).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(0).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_0_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(0).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(0).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(0).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(0).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(0).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(0).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(0).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(0).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(0).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(0).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(0).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(0).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(0).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(0).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(0).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(1).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(1).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(1).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(1).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(1).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(1).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(1).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(1).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(1).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(1).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(1).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(1).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(1).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_1_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(1).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(1).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(1).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(1).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(1).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(1).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(1).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(1).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(1).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(1).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(1).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(1).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(1).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(1).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(1).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(2).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(2).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(2).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(2).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(2).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(2).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(2).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(2).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(2).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(2).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(2).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(2).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(2).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_2_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(2).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(2).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(2).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(2).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(2).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(2).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(2).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(2).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(2).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(2).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(2).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(2).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(2).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(2).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(2).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(3).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(3).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(3).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(3).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(3).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(3).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(3).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(3).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(3).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(3).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(3).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(3).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(3).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_3_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(3).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(3).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(5)(3).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(3).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(3).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(3).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(5)(3).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(3).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(3).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(3).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(5)(3).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(3).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(3).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(3).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(5)(3).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(0).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_05_R3L1_0_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(0).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_05_R3L1_0_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(0).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_05_R3L1_0_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(1).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_05_R3L1_1_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(1).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_05_R3L1_1_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(1).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_05_R3L1_1_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(2).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_05_R3L1_2_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(2).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_05_R3L1_2_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(2).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_05_R3L1_2_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(3).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_05_R3L1_3_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(3).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_05_R3L1_3_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(3).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_05_R3L1_3_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(0).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(0).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(0).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(0).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(0).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(0).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(0).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(0).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(0).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(0).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(0).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(0).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(0).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_0_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(0).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(0).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(0).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(0).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(0).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(0).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(0).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(0).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(0).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(0).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(0).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(0).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(0).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(0).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(0).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(1).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(1).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(1).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(1).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(1).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(1).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(1).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(1).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(1).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(1).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(1).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(1).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(1).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_1_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(1).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(1).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(1).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(1).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(1).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(1).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(1).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(1).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(1).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(1).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(1).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(1).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(1).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(1).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(1).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(2).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(2).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(2).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(2).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(2).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(2).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(2).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(2).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(2).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(2).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(2).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(2).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(2).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_2_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(2).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(2).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(2).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(2).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(2).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(2).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(2).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(2).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(2).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(2).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(2).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(2).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(2).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(2).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(2).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(3).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(3).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(3).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(3).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(3).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(3).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(3).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(3).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(3).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(3).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(3).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(3).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(3).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_3_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(3).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(3).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(6)(3).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(3).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(3).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(3).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(6)(3).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(3).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(3).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(3).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(6)(3).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(3).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(3).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(3).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(6)(3).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(0).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_06_R3L1_0_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(0).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_06_R3L1_0_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(0).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_06_R3L1_0_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(1).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_06_R3L1_1_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(1).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_06_R3L1_1_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(1).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_06_R3L1_1_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(2).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_06_R3L1_2_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(2).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_06_R3L1_2_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(2).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_06_R3L1_2_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(3).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_06_R3L1_3_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(3).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_06_R3L1_3_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(3).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_06_R3L1_3_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(0).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(0).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(0).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(0).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(0).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(0).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(0).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(0).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(0).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(0).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(0).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(0).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(0).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_0_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(0).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(0).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(0).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(0).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(0).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(0).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(0).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(0).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(0).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(0).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(0).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(0).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(0).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(0).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(0).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(1).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(1).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(1).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(1).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(1).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(1).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(1).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(1).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(1).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(1).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(1).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(1).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(1).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_1_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(1).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(1).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(1).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(1).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(1).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(1).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(1).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(1).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(1).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(1).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(1).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(1).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(1).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(1).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(1).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(2).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(2).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(2).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(2).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(2).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(2).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(2).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(2).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(2).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(2).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(2).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(2).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(2).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_2_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(2).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(2).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(2).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(2).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(2).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(2).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(2).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(2).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(2).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(2).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(2).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(2).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(2).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(2).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(2).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(3).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(3).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(3).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(3).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(3).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(3).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(3).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(3).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(3).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(3).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(3).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(3).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(3).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_3_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(3).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(3).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(7)(3).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(3).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(3).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(3).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(7)(3).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(3).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(3).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(3).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(7)(3).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(3).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(3).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(3).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(7)(3).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(0).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_07_R3L1_0_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(0).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_07_R3L1_0_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(0).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_07_R3L1_0_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(1).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_07_R3L1_1_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(1).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_07_R3L1_1_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(1).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_07_R3L1_1_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(2).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_07_R3L1_2_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(2).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_07_R3L1_2_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(2).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_07_R3L1_2_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(3).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_07_R3L1_3_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(3).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_07_R3L1_3_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(3).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_07_R3L1_3_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(0).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(0).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(0).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(0).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(0).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(0).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(0).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(0).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(0).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(0).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(0).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(0).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(0).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_0_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(0).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(0).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(0).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(0).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(0).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(0).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(0).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(0).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(0).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(0).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(0).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(0).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(0).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(0).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(0).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(1).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(1).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(1).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(1).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(1).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(1).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(1).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(1).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(1).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(1).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(1).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(1).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(1).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_1_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(1).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(1).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(1).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(1).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(1).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(1).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(1).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(1).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(1).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(1).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(1).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(1).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(1).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(1).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(1).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(2).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(2).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(2).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(2).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(2).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(2).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(2).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(2).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(2).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(2).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(2).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(2).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(2).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_2_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(2).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(2).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(2).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(2).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(2).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(2).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(2).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(2).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(2).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(2).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(2).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(2).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(2).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(2).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(2).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(3).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(3).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(3).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(3).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(3).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(3).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(3).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(3).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(3).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(3).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(3).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(3).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(3).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_3_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(3).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(3).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(8)(3).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(3).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(3).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(3).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(8)(3).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(3).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(3).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(3).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(8)(3).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(3).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(3).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(3).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(8)(3).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(0).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_08_R3L1_0_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(0).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_08_R3L1_0_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(0).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_08_R3L1_0_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(1).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_08_R3L1_1_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(1).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_08_R3L1_1_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(1).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_08_R3L1_1_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(2).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_08_R3L1_2_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(2).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_08_R3L1_2_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(2).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_08_R3L1_2_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(3).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_08_R3L1_3_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(3).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_08_R3L1_3_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(3).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_08_R3L1_3_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(0).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(0).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(0).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(0).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(0).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(0).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(0).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(0).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(0).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(0).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(0).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(0).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(0).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_0_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(0).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(0).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(0).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(0).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(0).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(0).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(0).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(0).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(0).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(0).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(0).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(0).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(0).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(0).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(0).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(1).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(1).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(1).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(1).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(1).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(1).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(1).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(1).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(1).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(1).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(1).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(1).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(1).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_1_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(1).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(1).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(1).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(1).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(1).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(1).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(1).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(1).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(1).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(1).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(1).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(1).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(1).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(1).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(1).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(2).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(2).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(2).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(2).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(2).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(2).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(2).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(2).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(2).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(2).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(2).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(2).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(2).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_2_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(2).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(2).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(2).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(2).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(2).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(2).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(2).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(2).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(2).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(2).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(2).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(2).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(2).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(2).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(2).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(3).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(3).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(3).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(3).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(3).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(3).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(3).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(3).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(3).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(3).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(3).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(3).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(3).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_3_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(3).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(3).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(9)(3).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(3).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(3).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(3).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(9)(3).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(3).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(3).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(3).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(9)(3).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(3).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(3).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(3).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(9)(3).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(0).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_09_R3L1_0_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(0).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_09_R3L1_0_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(0).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_09_R3L1_0_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(1).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_09_R3L1_1_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(1).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_09_R3L1_1_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(1).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_09_R3L1_1_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(2).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_09_R3L1_2_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(2).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_09_R3L1_2_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(2).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_09_R3L1_2_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(3).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_09_R3L1_3_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(3).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_09_R3L1_3_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(3).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_09_R3L1_3_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(0).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(0).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(0).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(0).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(0).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(0).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(0).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(0).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(0).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(0).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(0).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(0).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(0).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_0_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(0).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(0).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(0).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(0).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(0).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(0).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(0).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(0).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(0).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(0).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(0).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(0).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(0).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(0).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(0).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(1).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(1).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(1).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(1).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(1).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(1).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(1).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(1).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(1).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(1).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(1).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(1).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(1).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_1_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(1).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(1).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(1).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(1).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(1).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(1).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(1).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(1).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(1).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(1).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(1).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(1).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(1).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(1).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(1).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(2).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(2).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(2).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(2).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(2).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(2).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(2).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(2).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(2).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(2).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(2).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(2).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(2).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_2_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(2).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(2).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(2).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(2).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(2).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(2).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(2).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(2).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(2).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(2).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(2).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(2).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(2).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(2).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(2).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(3).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(3).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(3).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(3).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(3).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(3).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(3).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(3).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(3).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(3).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(3).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(3).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(3).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_3_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(3).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(3).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(10)(3).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(3).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(3).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(3).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(10)(3).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(3).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(3).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(3).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(10)(3).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(3).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(3).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(3).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(10)(3).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(0).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_10_R3L1_0_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(0).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_10_R3L1_0_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(0).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_10_R3L1_0_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(1).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_10_R3L1_1_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(1).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_10_R3L1_1_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(1).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_10_R3L1_1_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(2).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_10_R3L1_2_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(2).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_10_R3L1_2_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(2).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_10_R3L1_2_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(3).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_10_R3L1_3_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(3).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_10_R3L1_3_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(3).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_10_R3L1_3_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(0).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(0).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(0).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(0).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(0).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(0).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(0).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(0).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(0).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(0).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(0).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(0).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(0).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_0_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(0).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(0).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(0).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(0).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(0).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(0).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(0).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(0).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(0).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(0).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(0).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(0).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(0).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(0).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(0).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(1).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(1).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(1).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(1).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(1).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(1).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(1).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(1).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(1).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(1).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(1).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(1).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(1).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_1_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(1).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(1).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(1).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(1).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(1).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(1).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(1).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(1).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(1).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(1).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(1).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(1).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(1).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(1).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(1).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(2).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(2).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(2).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(2).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(2).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(2).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(2).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(2).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(2).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(2).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(2).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(2).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(2).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_2_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(2).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(2).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(2).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(2).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(2).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(2).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(2).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(2).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(2).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(2).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(2).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(2).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(2).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(2).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(2).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(3).L0A_BCR_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_L0A_BCR_DELAY_C; -- TTC BCR signal will be delayed by this many BCs
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(3).L0A_FRAME_DELAY <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_L0A_FRAME_DELAY_C; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(3).FRAME_PHASE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_FRAME_PHASE_C; -- phase of LCB frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(3).TRICKLE_BC_START <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_TRICKLE_BC_START_C; -- Determines the start of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(3).TRICKLE_BC_STOP <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_TRICKLE_BC_STOP_C; -- Determines the end of the allowed BC interval for low-priority LCB frames
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(3).LCB_DESTINATION_MUX <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_LCB_DESTINATION_MUX_C; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(3).TRICKLE_TRIG_RUN <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_TRICKLE_TRIG_RUN_C; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(3).TTC_L0A_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_TTC_L0A_ENABLE_C; -- enable generating L0A frames in response to TTC system signals
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(3).TTC_GENERATE_GATING_ENABLE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_TTC_GENERATE_GATING_ENABLE_C; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(3).WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C; -- Trickle configuration memory write pointer
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(3).VALID_DATA_START <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C; -- Start address of trickle configuration in trickle memory
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(3).VALID_DATA_END <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(3).HCC_MASK <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_3_HCC_MASK_C; -- HCC* module mask
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(3).ABC_MASK_HCC_E <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(3).ABC_MASK_HCC_D <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C(11)(3).ABC_MASK_HCC_C <= REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(3).ABC_MASK_HCC_B <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(3).ABC_MASK_HCC_A <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(3).ABC_MASK_HCC_9 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8(11)(3).ABC_MASK_HCC_8 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(3).ABC_MASK_HCC_7 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(3).ABC_MASK_HCC_6 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(3).ABC_MASK_HCC_5 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4(11)(3).ABC_MASK_HCC_4 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(3).ABC_MASK_HCC_3 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(3).ABC_MASK_HCC_2 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(3).ABC_MASK_HCC_1 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0(11)(3).ABC_MASK_HCC_0 <= REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(0).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_11_R3L1_0_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(0).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_11_R3L1_0_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(0).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_11_R3L1_0_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(1).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_11_R3L1_1_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(1).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_11_R3L1_1_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(1).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_11_R3L1_1_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(2).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_11_R3L1_2_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(2).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_11_R3L1_2_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(2).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_11_R3L1_2_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(3).FRAME_PHASE <= REG_CR_ITK_R3L1_LINK_11_R3L1_3_FRAME_PHASE_C; -- phase of R3L1 frame with respect to TTC BCR signal
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(3).L1_ENABLE <= REG_CR_ITK_R3L1_LINK_11_R3L1_3_L1_ENABLE_C; -- enables sending TTC L1 signals to the front-end
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(3).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_11_R3L1_3_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_CTRL.OPTIONS <= REG_MROD_CTRL_OPTIONS_C; -- Extra options for MROD
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_CTRL.GOLTESTMODE <= REG_MROD_CTRL_GOLTESTMODE_C; -- GOL Test Mode (emulate CSM):
- -- 0: Run Data Emulator when 1; 0: stop, load emulator fifo
- -- 1: Enable Circulate when 1; 0: send fifo data only once
- -- 2: Enable Triggered Mode when 1; 0: run continueously (no TTC)
- -- 3: Enable pattern generator when 1; 0: off
-
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP0_CSMENABLE <= REG_MROD_EP0_CSMENABLE_C; -- EP0 CSM Data Enable channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP0_EMPTYSUPPR <= REG_MROD_EP0_EMPTYSUPPR_C; -- EP0 Set Empty Suppression channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP0_HPTDCMODE <= REG_MROD_EP0_HPTDCMODE_C; -- EP0 Set HPTDC Mode channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP0_CLRFIFOS <= REG_MROD_EP0_CLRFIFOS_C; -- EP0 Clear FIFOs channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP0_EMULOADENA <= REG_MROD_EP0_EMULOADENA_C; -- EP0 Emulator Load Enable channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP0_TRXLOOPBACK <= REG_MROD_EP0_TRXLOOPBACK_C; -- EP0 Transceiver Loopback Enable channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP0_TXCVRRESET <= REG_MROD_EP0_TXCVRRESET_C; -- EP0 Transceiver Reset all channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP0_RXRESET <= REG_MROD_EP0_RXRESET_C; -- EP0 Receiver Reset channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP0_TXRESET <= REG_MROD_EP0_TXRESET_C; -- EP0 Transmitter Reset channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP1_CSMENABLE <= REG_MROD_EP1_CSMENABLE_C; -- EP1 CSM Data Enable channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP1_EMPTYSUPPR <= REG_MROD_EP1_EMPTYSUPPR_C; -- EP1 Set Empty Suppression channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP1_HPTDCMODE <= REG_MROD_EP1_HPTDCMODE_C; -- EP1 Set HPTDC Mode channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP1_CLRFIFOS <= REG_MROD_EP1_CLRFIFOS_C; -- EP1 Clear FIFOs channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP1_EMULOADENA <= REG_MROD_EP1_EMULOADENA_C; -- EP1 Emulator Load Enable channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP1_TRXLOOPBACK <= REG_MROD_EP1_TRXLOOPBACK_C; -- EP1 Transceiver Loopback Enable channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP1_TXCVRRESET <= REG_MROD_EP1_TXCVRRESET_C; -- EP1 Transceiver Reset all channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP1_RXRESET <= REG_MROD_EP1_RXRESET_C; -- EP1 Receiver Reset channel 23-0
- end if;
- if MROD_GENERATE_REGS = true then
- register_map_control_s.MROD_EP1_TXRESET <= REG_MROD_EP1_TXRESET_C; -- EP1 Transmitter Reset channel 23-0
- end if;
- -----------------------------------
- ---- GENERATED code END #1 ## ----
- -----------------------------------
- else
-
- for i in 0 to NUMBER_OF_DESCRIPTORS-1 loop
- if(dma_descriptors_25_r_s(i).enable = '1') then
- if(last_pc_pointer_v(i) > dma_descriptors_25_w_s(i).pc_pointer + pc_ptr_gap_25_s) then --If the current pc_pointer is 16MB smaller than the last one, we change cycles. The 16MB can be changed in the register PC_PTR_GAP (bar0).
- dma_descriptors_25_w_s(i).evencycle_pc <= not dma_descriptors_25_w_s(i).evencycle_pc; --Toggle on wrap around
- end if;
- else
- dma_descriptors_25_w_s(i).evencycle_pc <= '0';
- end if;
- last_pc_pointer_v(i) := dma_descriptors_25_w_s(i).pc_pointer;
- end loop;
-
- dma_descriptors_enable_written_25_s <= '0';
- register_map_control_s <= register_map_control_s; --store read (PCIe Write) register map
- register_read_done_25_s <= '0';
- register_read_data_25_s <= register_read_data_25_s;
-
-
- --!
- --! generated self clearing "write only" register clear assignment
- -- Bar 0
- flush_fifo_25_s <= '0';
- dma_soft_reset_25_s <= '0';
- reset_global_soft_25_s <= '0';
-
- if register_map_control_s.DMA_BUSY_STATUS.CLEAR_LATCH="1" then
- tohost_busy_latched_25_s <= '0';
- fromhost_busy_latched_25_s <= '0';
- end if;
- if tohost_busy_25_s = '1' then
- tohost_busy_latched_25_s <= '1';
- end if;
- if fromhost_busy_25_s = '1' then
- fromhost_busy_latched_25_s <= '1';
- end if;
-
- ------------------------------------
- ---- ## GENERATED CODE BEGIN #2 ----
- ------------------------------------
- register_map_control_s.CRTOHOST_FIFO_STATUS.CLEAR <= REG_CRTOHOST_FIFO_STATUS_CLEAR_C; -- Any write to this register clears the latched FULL flags
- register_map_control_s.CRFROMHOST_FIFO_STATUS.CLEAR <= REG_CRFROMHOST_FIFO_STATUS_CLEAR_C; -- Any write to this register clears the latched FULL flags
- register_map_control_s.TTC_BUSY_CLEAR <= REG_TTC_BUSY_CLEAR_C; -- clears the latching busy bits in TTC_BUSY_ACCEPTED
- register_map_control_s.TTC_EMU_RESET <= REG_TTC_EMU_RESET_C; -- Any write to this register resets the TTC Emulator to the default state.
- register_map_control_s.TTC_ECR_MONITOR.CLEAR <= REG_TTC_ECR_MONITOR_CLEAR_C; -- Counts the number of ECRs received from the TTC system, any write to this register clears the counter
- register_map_control_s.TTC_TTYPE_MONITOR.CLEAR <= REG_TTC_TTYPE_MONITOR_CLEAR_C; -- Counts the number of TType received from the TTC system, any write to this register clears the counter
- register_map_control_s.TTC_BCR_PERIODICITY_MONITOR.CLEAR <= REG_TTC_BCR_PERIODICITY_MONITOR_CLEAR_C; -- Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
- register_map_control_s.XOFF_FM_HIGH_THRESH.CLEAR_LATCH <= REG_XOFF_FM_HIGH_THRESH_CLEAR_LATCH_C; -- Writing this register will clear all CROSS_LATCHED bits
- register_map_control_s.DMA_BUSY_STATUS.CLEAR_LATCH <= REG_DMA_BUSY_STATUS_CLEAR_LATCH_C; -- Any write to this register clears TOHOST_BUSY_LATCHED
- register_map_control_s.FM_BUSY_CHANNEL_STATUS.CLEAR_LATCH <= REG_FM_BUSY_CHANNEL_STATUS_CLEAR_LATCH_C; -- Any write to this register will clear the BUSY_LATCHED bits
- register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_STATUS.CLEAR_LATCHED <= REG_BUSY_MAIN_OUTPUT_FIFO_STATUS_CLEAR_LATCHED_C; -- Any write to this register will clear the
- register_map_control_s.I2C_WR.I2C_WREN <= REG_I2C_WR_I2C_WREN_C; -- Any write to this register triggers an I2C read or write sequence
- register_map_control_s.I2C_RD.I2C_RDEN <= REG_I2C_RD_I2C_RDEN_C; -- Any write to this register pops the last I2C data from the FIFO
- register_map_control_s.INT_TEST.TRIGGER <= REG_INT_TEST_TRIGGER_C; -- Fire a test MSIx interrupt set in IRQ
- if EMU_GENERATE_REGS then
- register_map_control_s.FMEMU_RANDOM_RAM.WE <= REG_FMEMU_RANDOM_RAM_WE_C; -- Any write to this register (DATA) triggers a write to the ramblock
- end if;
- register_map_control_s.WISHBONE_WRITE.WRITE_ENABLE <= REG_WISHBONE_WRITE_WRITE_ENABLE_C; -- Any write to this register triggers a write to the Wupper to Wishbone fifo
- register_map_control_s.WISHBONE_READ.READ_ENABLE <= REG_WISHBONE_READ_READ_ENABLE_C; -- Any write to this register triggers a read from the Wishbone to Wupper fifo
- register_map_control_s.GLOBAL_STRIPS_CONFIG.TRICKLE_TRIG_PULSE <= REG_GLOBAL_STRIPS_CONFIG_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (0)(0).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_0_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(0)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (0)(1).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_1_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(0)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (0)(2).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_2_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(0)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (0)(3).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_3_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(0)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (1)(0).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_0_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(1)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (1)(1).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_1_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(1)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (1)(2).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_2_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(1)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (1)(3).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_3_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(1)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (2)(0).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_0_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(2)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (2)(1).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_1_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(2)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (2)(2).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_2_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(2)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (2)(3).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_3_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(2)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (3)(0).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_0_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(3)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (3)(1).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_1_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(3)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (3)(2).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_2_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(3)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (3)(3).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_3_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(3)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(0).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(1).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(2).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(3).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(4)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(0).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(1).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(2).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(3).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(5)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(0).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(1).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(2).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(3).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(6)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(0).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(1).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(2).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(3).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(7)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(0).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(1).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(2).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(3).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(8)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(0).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(1).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(2).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(3).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(9)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(0).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(1).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(2).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(3).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(10)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(0).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(1).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(2).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(3).TRICKLE_TRIG_PULSE <= REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_TRICKLE_TRIG_PULSE_C; -- writing to this register issues a single trickle trigger
- end if;
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG(11)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- end if;
- -----------------------------------
- ---- GENERATED code END #2 ## ----
- -----------------------------------
-
- if(register_read_enable_25_s = '1') then
- register_read_done_25_s <= '1';
- register_read_data_25_s <= (others => '0'); --default value
- --Read registers in BAR0
- if(bar_id_25_s = "000") then
- register_read_address_v := register_read_address_25_s(19 downto 4)&"0000";
- case(register_read_address_v) is
- when REG_DESCRIPTOR_0 => register_read_data_25_s <= dma_descriptors_25_r_s( 0).end_address&
- dma_descriptors_25_r_s( 0).start_address;
- when REG_DESCRIPTOR_0a => register_read_data_25_s <= dma_descriptors_25_r_s( 0).pc_pointer&
- x"000000000000"&"000"&
- dma_descriptors_25_r_s( 0).wrap_around&
- dma_descriptors_25_r_s( 0).read_not_write&
- dma_descriptors_25_r_s( 0).dword_count;
- when REG_DESCRIPTOR_1 => register_read_data_25_s <= dma_descriptors_25_r_s( 1).end_address&
- dma_descriptors_25_r_s( 1).start_address;
- when REG_DESCRIPTOR_1a => register_read_data_25_s <= dma_descriptors_25_r_s( 1).pc_pointer&
- x"000000000000"&"000"&
- dma_descriptors_25_r_s( 1).wrap_around&
- dma_descriptors_25_r_s( 1).read_not_write&
- dma_descriptors_25_r_s( 1).dword_count;
- when REG_DESCRIPTOR_2 => register_read_data_25_s <= dma_descriptors_25_r_s( 2).end_address&
- dma_descriptors_25_r_s( 2).start_address;
- when REG_DESCRIPTOR_2a => register_read_data_25_s <= dma_descriptors_25_r_s( 2).pc_pointer&
- x"000000000000"&"000"&
- dma_descriptors_25_r_s( 2).wrap_around&
- dma_descriptors_25_r_s( 2).read_not_write&
- dma_descriptors_25_r_s( 2).dword_count;
- when REG_DESCRIPTOR_3 => register_read_data_25_s <= dma_descriptors_25_r_s( 3).end_address&
- dma_descriptors_25_r_s( 3).start_address;
- when REG_DESCRIPTOR_3a => register_read_data_25_s <= dma_descriptors_25_r_s( 3).pc_pointer&
- x"000000000000"&"000"&
- dma_descriptors_25_r_s( 3).wrap_around&
- dma_descriptors_25_r_s( 3).read_not_write&
- dma_descriptors_25_r_s( 3).dword_count;
- when REG_DESCRIPTOR_4 => register_read_data_25_s <= dma_descriptors_25_r_s( 4).end_address&
- dma_descriptors_25_r_s( 4).start_address;
- when REG_DESCRIPTOR_4a => register_read_data_25_s <= dma_descriptors_25_r_s( 4).pc_pointer&
- x"000000000000"&"000"&
- dma_descriptors_25_r_s( 4).wrap_around&
- dma_descriptors_25_r_s( 4).read_not_write&
- dma_descriptors_25_r_s( 4).dword_count;
- when REG_DESCRIPTOR_5 => register_read_data_25_s <= dma_descriptors_25_r_s( 5).end_address&
- dma_descriptors_25_r_s( 5).start_address;
- when REG_DESCRIPTOR_5a => register_read_data_25_s <= dma_descriptors_25_r_s( 5).pc_pointer&
- x"000000000000"&"000"&
- dma_descriptors_25_r_s( 5).wrap_around&
- dma_descriptors_25_r_s( 5).read_not_write&
- dma_descriptors_25_r_s( 5).dword_count;
- when REG_DESCRIPTOR_6 => register_read_data_25_s <= dma_descriptors_25_r_s( 6).end_address&
- dma_descriptors_25_r_s( 6).start_address;
- when REG_DESCRIPTOR_6a => register_read_data_25_s <= dma_descriptors_25_r_s( 6).pc_pointer&
- x"000000000000"&"000"&
- dma_descriptors_25_r_s( 6).wrap_around&
- dma_descriptors_25_r_s( 6).read_not_write&
- dma_descriptors_25_r_s( 6).dword_count;
- when REG_DESCRIPTOR_7 => register_read_data_25_s <= dma_descriptors_25_r_s( 7).end_address&
- dma_descriptors_25_r_s( 7).start_address;
- when REG_DESCRIPTOR_7a => register_read_data_25_s <= dma_descriptors_25_r_s( 7).pc_pointer&
- x"000000000000"&"000"&
- dma_descriptors_25_r_s( 7).wrap_around&
- dma_descriptors_25_r_s( 7).read_not_write&
- dma_descriptors_25_r_s( 7).dword_count;
- when REG_STATUS_0 => register_read_data_25_s <= x"000000000000000"&"0"&
- dma_descriptors_25_r_s(0 ).evencycle_pc&
- dma_status_25_s(0 ).evencycle_dma&
- (not dma_descriptors_25_r_s(0 ).enable)&
- dma_status_25_s(0 ).current_address;
- when REG_STATUS_1 => register_read_data_25_s <= x"000000000000000"&"0"&
- dma_descriptors_25_r_s(1 ).evencycle_pc&
- dma_status_25_s(1 ).evencycle_dma&
- (not dma_descriptors_25_r_s(1 ).enable)&
- dma_status_25_s(1 ).current_address;
- when REG_STATUS_2 => register_read_data_25_s <= x"000000000000000"&"0"&
- dma_descriptors_25_r_s(2 ).evencycle_pc&
- dma_status_25_s(2 ).evencycle_dma&
- (not dma_descriptors_25_r_s(2 ).enable)&
- dma_status_25_s(2 ).current_address;
- when REG_STATUS_3 => register_read_data_25_s <= x"000000000000000"&"0"&
- dma_descriptors_25_r_s(3 ).evencycle_pc&
- dma_status_25_s(2 ).evencycle_dma&
- (not dma_descriptors_25_r_s(3 ).enable)&
- dma_status_25_s(3 ).current_address;
- when REG_STATUS_4 => register_read_data_25_s <= x"000000000000000"&"0"&
- dma_descriptors_25_r_s(4 ).evencycle_pc&
- dma_status_25_s(4 ).evencycle_dma&
- (not dma_descriptors_25_r_s(4 ).enable)&
- dma_status_25_s(4 ).current_address;
- when REG_STATUS_5 => register_read_data_25_s <= x"000000000000000"&"0"&
- dma_descriptors_25_r_s(5 ).evencycle_pc&
- dma_status_25_s(5 ).evencycle_dma&
- (not dma_descriptors_25_r_s(5 ).enable)&
- dma_status_25_s(5 ).current_address;
- when REG_STATUS_6 => register_read_data_25_s <= x"000000000000000"&"0"&
- dma_descriptors_25_r_s(6 ).evencycle_pc&
- dma_status_25_s(6 ).evencycle_dma&
- (not dma_descriptors_25_r_s(6 ).enable)&
- dma_status_25_s(6 ).current_address;
- when REG_STATUS_7 => register_read_data_25_s <= x"000000000000000"&"0"&
- dma_descriptors_25_r_s(7 ).evencycle_pc&
- dma_status_25_s(7 ).evencycle_dma&
- (not dma_descriptors_25_r_s(7 ).enable)&
- dma_status_25_s(7 ).current_address;
- when REG_DESCRIPTOR_ENABLE => for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
- register_read_data_25_s(i) <= dma_descriptors_25_r_s(i).enable;
- end loop;
- register_read_data_25_s(127 downto (NUMBER_OF_DESCRIPTORS)) <= (others =>'0');
- when REG_FIFO_FLUSH => register_read_data_25_s <= (others => '0');
- when REG_DMA_RESET => register_read_data_25_s <= (others => '0');
- when REG_SOFT_RESET => register_read_data_25_s <= (others => '0');
- when REG_REGISTER_RESET => register_read_data_25_s <= (others => '0');
- when REG_FROMHOST_FULL_THRESH => register_read_data_25_s <= x"00000000_00000000" &
- x"0000_0000_0"&"000"&fromhost_pfull_threshold_assert_s&
- x"0"&"000"&fromhost_pfull_threshold_negate_s;
- when REG_TOHOST_FULL_THRESH => register_read_data_25_s <= x"00000000_00000000" &
- x"0000_0000_0"&tohost_pfull_threshold_assert_s&
- x"0"&tohost_pfull_threshold_negate_s;
- when REG_BUSY_THRESH_ASSERT => register_read_data_25_s <= x"0000_0000_0000_0000"&busy_threshold_assert;
- when REG_BUSY_THRESH_NEGATE => register_read_data_25_s <= x"0000_0000_0000_0000"&busy_threshold_negate;
- when REG_BUSY_STATUS => register_read_data_25_s <= x"0000_0000_0000_0000_0000_0000_0000_000"&"00"&
- fromhost_busy_25_s&
- tohost_busy_25_s;
- when REG_PC_PTR_GAP => register_read_data_25_s <= x"0000_0000_0000_0000"&pc_ptr_gap_25_s;
- when others => register_read_data_25_s <= (others => '0');
-
-
- end case;
- --Read registers in BAR1
- elsif(bar_id_25_s = "001") then
- register_read_address_v := register_read_address_25_s(19 downto 4)&"0000";
- case(register_read_address_v) is
- when REG_INT_VEC_00 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(0).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(0).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(0).int_vec_ctrl;
- when REG_INT_VEC_01 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(1).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(1).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(1).int_vec_ctrl;
- when REG_INT_VEC_02 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(2).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(2).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(2).int_vec_ctrl;
- when REG_INT_VEC_03 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(3).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(3).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(3).int_vec_ctrl;
- when REG_INT_VEC_04 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(4).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(4).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(4).int_vec_ctrl;
- when REG_INT_VEC_05 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(5).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(5).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(5).int_vec_ctrl;
- when REG_INT_VEC_06 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(6).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(6).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(6).int_vec_ctrl;
- when REG_INT_VEC_07 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(7).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(7).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(7).int_vec_ctrl;
- when REG_INT_VEC_08 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(8).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(8).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(8).int_vec_ctrl;
- when REG_INT_VEC_09 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(9).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(9).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(9).int_vec_ctrl;
- when REG_INT_VEC_10 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(10).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(10).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(10).int_vec_ctrl;
- when REG_INT_VEC_11 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(11).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(11).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(11).int_vec_ctrl;
- when REG_INT_VEC_12 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(12).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(12).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(12).int_vec_ctrl;
- when REG_INT_VEC_13 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(13).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(13).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(13).int_vec_ctrl;
- when REG_INT_VEC_14 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(14).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(14).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(14).int_vec_ctrl;
- when REG_INT_VEC_15 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(15).int_vec_add;
- register_read_data_25_s(95 downto 64) <= int_vector_25_s(15).int_vec_data;
- register_read_data_25_s(127 downto 96) <= int_vector_25_s(15).int_vec_ctrl;
- when REG_INT_TAB_EN => register_read_data_25_s(NUMBER_OF_INTERRUPTS-1 downto 0) <= int_table_en_s;
- when others => register_read_data_25_s <= (others => '0');
- end case;
- --Read registers in BAR2
- elsif(bar_id_25_s = "010") then
- register_read_address_v := register_read_address_25_s(19 downto 4)&"0000";
- case(register_read_address_v) is
- --!
- --! generated registers read
- ------------------------------------
- ---- ## GENERATED code BEGIN #3 ----
- ------------------------------------
- --
- -- Control Registers
- --
- when REG_STATUS_LEDS => register_read_data_25_s(7 downto 0) <= register_map_control_s.STATUS_LEDS; -- Board GPIO Leds
- when REG_TIMEOUT_CTRL => register_read_data_25_s(32 downto 32) <= register_map_control_s.TIMEOUT_CTRL.ENABLE; -- 1 enables the timout trailer generation for ToHost mode
- register_read_data_25_s(31 downto 0) <= register_map_control_s.TIMEOUT_CTRL.TIMEOUT; -- Number of 40 MHz clock cycles after which a timeout occurs.
- when REG_CRTOHOST_FIFO_STATUS => register_read_data_25_s(64 downto 64) <= register_map_control_s.CRTOHOST_FIFO_STATUS.CLEAR; -- Any write to this register clears the latched FULL flags
- register_read_data_25_s(47 downto 24) <= register_map_monitor_s.register_map_crtohost_monitor.CRTOHOST_FIFO_STATUS.FULL; -- Every bit represents the full flag of a channel FIFO
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.register_map_crtohost_monitor.CRTOHOST_FIFO_STATUS.FULL_LATCHED; -- like FULL but a latched state, clear by writing to this register
- when REG_CRFROMHOST_FIFO_STATUS => register_read_data_25_s(64 downto 64) <= register_map_control_s.CRFROMHOST_FIFO_STATUS.CLEAR; -- Any write to this register clears the latched FULL flags
- register_read_data_25_s(47 downto 24) <= register_map_monitor_s.register_map_crfromhost_monitor.CRFROMHOST_FIFO_STATUS.FULL; -- Every bit represents the full flag of a channel FIFO
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.register_map_crfromhost_monitor.CRFROMHOST_FIFO_STATUS.FULL_LATCHED; -- like FULL but a latched state, clear by writing to this register
- when REG_BROADCAST_ENABLE_00 =>
- if GBT_NUM > 0 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_01 =>
- if GBT_NUM > 1 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(1); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_02 =>
- if GBT_NUM > 2 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(2); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_03 =>
- if GBT_NUM > 3 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(3); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_04 =>
- if GBT_NUM > 4 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(4); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_05 =>
- if GBT_NUM > 5 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(5); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_06 =>
- if GBT_NUM > 6 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(6); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_07 =>
- if GBT_NUM > 7 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(7); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_08 =>
- if GBT_NUM > 8 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(8); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_09 =>
- if GBT_NUM > 9 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(9); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_10 =>
- if GBT_NUM > 10 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(10); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_11 =>
- if GBT_NUM > 11 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(11); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_12 =>
- if GBT_NUM > 12 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(12); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_13 =>
- if GBT_NUM > 13 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(13); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_14 =>
- if GBT_NUM > 14 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(14); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_15 =>
- if GBT_NUM > 15 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(15); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_16 =>
- if GBT_NUM > 16 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(16); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_17 =>
- if GBT_NUM > 17 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(17); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_18 =>
- if GBT_NUM > 18 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(18); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_19 =>
- if GBT_NUM > 19 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(19); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_20 =>
- if GBT_NUM > 20 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(20); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_21 =>
- if GBT_NUM > 21 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(21); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_22 =>
- if GBT_NUM > 22 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(22); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_23 =>
- if GBT_NUM > 23 then
- register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(23); -- Enable path to be included in a broadcast message.
- end if;
- when REG_LINK_00_HAS_STREAM_ID =>
- if GBT_NUM > 0 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(0).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(0).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(0).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(0).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(0).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(0).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(0).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_01_HAS_STREAM_ID =>
- if GBT_NUM > 1 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(1).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(1).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(1).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(1).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(1).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(1).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(1).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_02_HAS_STREAM_ID =>
- if GBT_NUM > 2 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(2).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(2).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(2).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(2).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(2).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(2).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(2).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_03_HAS_STREAM_ID =>
- if GBT_NUM > 3 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(3).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(3).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(3).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(3).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(3).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(3).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(3).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_04_HAS_STREAM_ID =>
- if GBT_NUM > 4 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(4).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(4).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(4).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(4).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(4).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(4).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(4).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_05_HAS_STREAM_ID =>
- if GBT_NUM > 5 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(5).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(5).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(5).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(5).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(5).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(5).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(5).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_06_HAS_STREAM_ID =>
- if GBT_NUM > 6 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(6).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(6).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(6).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(6).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(6).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(6).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(6).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_07_HAS_STREAM_ID =>
- if GBT_NUM > 7 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(7).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(7).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(7).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(7).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(7).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(7).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(7).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_08_HAS_STREAM_ID =>
- if GBT_NUM > 8 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(8).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(8).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(8).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(8).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(8).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(8).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(8).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_09_HAS_STREAM_ID =>
- if GBT_NUM > 9 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(9).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(9).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(9).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(9).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(9).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(9).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(9).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_10_HAS_STREAM_ID =>
- if GBT_NUM > 10 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(10).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(10).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(10).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(10).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(10).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(10).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(10).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_11_HAS_STREAM_ID =>
- if GBT_NUM > 11 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(11).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(11).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(11).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(11).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(11).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(11).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(11).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_12_HAS_STREAM_ID =>
- if GBT_NUM > 12 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(12).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(12).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(12).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(12).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(12).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(12).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(12).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_13_HAS_STREAM_ID =>
- if GBT_NUM > 13 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(13).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(13).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(13).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(13).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(13).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(13).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(13).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_14_HAS_STREAM_ID =>
- if GBT_NUM > 14 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(14).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(14).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(14).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(14).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(14).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(14).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(14).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_15_HAS_STREAM_ID =>
- if GBT_NUM > 15 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(15).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(15).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(15).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(15).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(15).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(15).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(15).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_16_HAS_STREAM_ID =>
- if GBT_NUM > 16 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(16).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(16).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(16).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(16).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(16).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(16).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(16).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_17_HAS_STREAM_ID =>
- if GBT_NUM > 17 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(17).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(17).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(17).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(17).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(17).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(17).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(17).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_18_HAS_STREAM_ID =>
- if GBT_NUM > 18 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(18).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(18).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(18).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(18).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(18).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(18).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(18).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_19_HAS_STREAM_ID =>
- if GBT_NUM > 19 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(19).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(19).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(19).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(19).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(19).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(19).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(19).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_20_HAS_STREAM_ID =>
- if GBT_NUM > 20 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(20).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(20).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(20).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(20).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(20).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(20).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(20).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_21_HAS_STREAM_ID =>
- if GBT_NUM > 21 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(21).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(21).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(21).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(21).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(21).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(21).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(21).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_22_HAS_STREAM_ID =>
- if GBT_NUM > 22 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(22).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(22).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(22).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(22).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(22).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(22).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(22).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_23_HAS_STREAM_ID =>
- if GBT_NUM > 23 then
- register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(23).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(23).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(23).EGROUP4; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(23).EGROUP3; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(23).EGROUP2; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(23).EGROUP1; -- EPATH is associated with a STREAM ID
- register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(23).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_DECODING_LINK00_EGROUP0_CTRL =>
- if GBT_NUM > 0 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (0)(0).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(0).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK00_EGROUP1_CTRL =>
- if GBT_NUM > 0 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (0)(1).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(1).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK00_EGROUP2_CTRL =>
- if GBT_NUM > 0 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (0)(2).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(2).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK00_EGROUP3_CTRL =>
- if GBT_NUM > 0 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (0)(3).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(3).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK00_EGROUP4_CTRL =>
- if GBT_NUM > 0 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (0)(4).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(4).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK00_EGROUP5_CTRL =>
- if GBT_NUM > 0 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (0)(5).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(5).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK00_EGROUP6_CTRL =>
- if GBT_NUM > 0 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (0)(6).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(6).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK01_EGROUP0_CTRL =>
- if GBT_NUM > 1 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (1)(0).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(0).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK01_EGROUP1_CTRL =>
- if GBT_NUM > 1 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (1)(1).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(1).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK01_EGROUP2_CTRL =>
- if GBT_NUM > 1 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (1)(2).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(2).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK01_EGROUP3_CTRL =>
- if GBT_NUM > 1 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (1)(3).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(3).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK01_EGROUP4_CTRL =>
- if GBT_NUM > 1 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (1)(4).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(4).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK01_EGROUP5_CTRL =>
- if GBT_NUM > 1 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (1)(5).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(5).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK01_EGROUP6_CTRL =>
- if GBT_NUM > 1 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (1)(6).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(6).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK02_EGROUP0_CTRL =>
- if GBT_NUM > 2 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (2)(0).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(0).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK02_EGROUP1_CTRL =>
- if GBT_NUM > 2 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (2)(1).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(1).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK02_EGROUP2_CTRL =>
- if GBT_NUM > 2 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (2)(2).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(2).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK02_EGROUP3_CTRL =>
- if GBT_NUM > 2 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (2)(3).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(3).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK02_EGROUP4_CTRL =>
- if GBT_NUM > 2 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (2)(4).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(4).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK02_EGROUP5_CTRL =>
- if GBT_NUM > 2 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (2)(5).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(5).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK02_EGROUP6_CTRL =>
- if GBT_NUM > 2 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (2)(6).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(6).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK03_EGROUP0_CTRL =>
- if GBT_NUM > 3 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (3)(0).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(0).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK03_EGROUP1_CTRL =>
- if GBT_NUM > 3 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (3)(1).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(1).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK03_EGROUP2_CTRL =>
- if GBT_NUM > 3 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (3)(2).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(2).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK03_EGROUP3_CTRL =>
- if GBT_NUM > 3 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (3)(3).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(3).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK03_EGROUP4_CTRL =>
- if GBT_NUM > 3 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (3)(4).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(4).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK03_EGROUP5_CTRL =>
- if GBT_NUM > 3 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (3)(5).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(5).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK03_EGROUP6_CTRL =>
- if GBT_NUM > 3 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (3)(6).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(6).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK04_EGROUP0_CTRL =>
- if GBT_NUM > 4 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (4)(0).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(0).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK04_EGROUP1_CTRL =>
- if GBT_NUM > 4 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (4)(1).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(1).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK04_EGROUP2_CTRL =>
- if GBT_NUM > 4 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (4)(2).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(2).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK04_EGROUP3_CTRL =>
- if GBT_NUM > 4 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (4)(3).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(3).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK04_EGROUP4_CTRL =>
- if GBT_NUM > 4 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (4)(4).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(4).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK04_EGROUP5_CTRL =>
- if GBT_NUM > 4 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (4)(5).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(5).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK04_EGROUP6_CTRL =>
- if GBT_NUM > 4 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (4)(6).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(6).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK05_EGROUP0_CTRL =>
- if GBT_NUM > 5 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (5)(0).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(0).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK05_EGROUP1_CTRL =>
- if GBT_NUM > 5 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (5)(1).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(1).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK05_EGROUP2_CTRL =>
- if GBT_NUM > 5 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (5)(2).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(2).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK05_EGROUP3_CTRL =>
- if GBT_NUM > 5 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (5)(3).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(3).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK05_EGROUP4_CTRL =>
- if GBT_NUM > 5 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (5)(4).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(4).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK05_EGROUP5_CTRL =>
- if GBT_NUM > 5 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (5)(5).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(5).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK05_EGROUP6_CTRL =>
- if GBT_NUM > 5 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (5)(6).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(6).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK06_EGROUP0_CTRL =>
- if GBT_NUM > 6 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (6)(0).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(0).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK06_EGROUP1_CTRL =>
- if GBT_NUM > 6 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (6)(1).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(1).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK06_EGROUP2_CTRL =>
- if GBT_NUM > 6 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (6)(2).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(2).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK06_EGROUP3_CTRL =>
- if GBT_NUM > 6 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (6)(3).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(3).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK06_EGROUP4_CTRL =>
- if GBT_NUM > 6 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (6)(4).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(4).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK06_EGROUP5_CTRL =>
- if GBT_NUM > 6 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (6)(5).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(5).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK06_EGROUP6_CTRL =>
- if GBT_NUM > 6 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (6)(6).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(6).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK07_EGROUP0_CTRL =>
- if GBT_NUM > 7 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (7)(0).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(0).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK07_EGROUP1_CTRL =>
- if GBT_NUM > 7 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (7)(1).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(1).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK07_EGROUP2_CTRL =>
- if GBT_NUM > 7 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (7)(2).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(2).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK07_EGROUP3_CTRL =>
- if GBT_NUM > 7 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (7)(3).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(3).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK07_EGROUP4_CTRL =>
- if GBT_NUM > 7 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (7)(4).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(4).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK07_EGROUP5_CTRL =>
- if GBT_NUM > 7 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (7)(5).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(5).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK07_EGROUP6_CTRL =>
- if GBT_NUM > 7 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (7)(6).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(6).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK08_EGROUP0_CTRL =>
- if GBT_NUM > 8 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (8)(0).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(0).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK08_EGROUP1_CTRL =>
- if GBT_NUM > 8 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (8)(1).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(1).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK08_EGROUP2_CTRL =>
- if GBT_NUM > 8 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (8)(2).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(2).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK08_EGROUP3_CTRL =>
- if GBT_NUM > 8 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (8)(3).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(3).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK08_EGROUP4_CTRL =>
- if GBT_NUM > 8 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (8)(4).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(4).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK08_EGROUP5_CTRL =>
- if GBT_NUM > 8 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (8)(5).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(5).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK08_EGROUP6_CTRL =>
- if GBT_NUM > 8 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (8)(6).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(6).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK09_EGROUP0_CTRL =>
- if GBT_NUM > 9 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (9)(0).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(0).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK09_EGROUP1_CTRL =>
- if GBT_NUM > 9 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (9)(1).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(1).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK09_EGROUP2_CTRL =>
- if GBT_NUM > 9 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (9)(2).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(2).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK09_EGROUP3_CTRL =>
- if GBT_NUM > 9 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (9)(3).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(3).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK09_EGROUP4_CTRL =>
- if GBT_NUM > 9 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (9)(4).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(4).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK09_EGROUP5_CTRL =>
- if GBT_NUM > 9 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (9)(5).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(5).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK09_EGROUP6_CTRL =>
- if GBT_NUM > 9 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (9)(6).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(6).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK10_EGROUP0_CTRL =>
- if GBT_NUM > 10 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (10)(0).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(0).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK10_EGROUP1_CTRL =>
- if GBT_NUM > 10 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (10)(1).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(1).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK10_EGROUP2_CTRL =>
- if GBT_NUM > 10 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (10)(2).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(2).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK10_EGROUP3_CTRL =>
- if GBT_NUM > 10 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (10)(3).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(3).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK10_EGROUP4_CTRL =>
- if GBT_NUM > 10 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (10)(4).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(4).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK10_EGROUP5_CTRL =>
- if GBT_NUM > 10 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (10)(5).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(5).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK10_EGROUP6_CTRL =>
- if GBT_NUM > 10 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (10)(6).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(6).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK11_EGROUP0_CTRL =>
- if GBT_NUM > 11 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (11)(0).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(0).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK11_EGROUP1_CTRL =>
- if GBT_NUM > 11 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (11)(1).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(1).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK11_EGROUP2_CTRL =>
- if GBT_NUM > 11 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (11)(2).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(2).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK11_EGROUP3_CTRL =>
- if GBT_NUM > 11 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (11)(3).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(3).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK11_EGROUP4_CTRL =>
- if GBT_NUM > 11 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (11)(4).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(4).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK11_EGROUP5_CTRL =>
- if GBT_NUM > 11 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (11)(5).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(5).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK11_EGROUP6_CTRL =>
- if GBT_NUM > 11 then
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (11)(6).EPATH_ALMOST_FULL; -- FIFO full indication
- register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(6).EPATH_ENA; -- Enable bits per EPROC
- end if;
- when REG_MINI_EGROUP_TOHOST_00 =>
- if GBT_NUM > 0 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (0).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(0).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(0).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (0).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(0).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(0).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (0).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(0).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(0).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(0).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_01 =>
- if GBT_NUM > 1 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (1).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(1).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(1).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (1).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(1).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(1).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (1).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(1).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(1).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(1).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_02 =>
- if GBT_NUM > 2 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (2).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(2).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(2).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (2).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(2).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(2).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (2).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(2).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(2).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(2).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_03 =>
- if GBT_NUM > 3 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (3).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(3).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(3).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (3).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(3).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(3).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (3).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(3).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(3).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(3).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_04 =>
- if GBT_NUM > 4 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (4).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(4).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(4).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (4).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(4).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(4).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (4).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(4).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(4).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(4).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_05 =>
- if GBT_NUM > 5 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (5).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(5).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(5).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (5).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(5).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(5).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (5).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(5).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(5).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(5).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_06 =>
- if GBT_NUM > 6 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (6).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(6).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(6).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (6).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(6).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(6).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (6).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(6).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(6).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(6).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_07 =>
- if GBT_NUM > 7 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (7).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(7).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(7).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (7).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(7).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(7).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (7).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(7).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(7).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(7).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_08 =>
- if GBT_NUM > 8 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (8).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(8).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(8).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (8).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(8).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(8).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (8).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(8).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(8).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(8).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_09 =>
- if GBT_NUM > 9 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (9).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(9).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(9).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (9).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(9).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(9).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (9).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(9).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(9).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(9).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_10 =>
- if GBT_NUM > 10 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (10).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(10).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(10).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (10).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(10).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(10).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (10).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(10).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(10).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(10).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_11 =>
- if GBT_NUM > 11 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (11).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(11).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(11).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (11).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(11).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(11).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (11).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(11).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(11).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(11).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_12 =>
- if GBT_NUM > 12 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (12).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(12).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(12).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (12).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(12).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(12).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (12).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(12).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(12).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(12).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_13 =>
- if GBT_NUM > 13 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (13).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(13).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(13).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (13).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(13).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(13).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (13).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(13).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(13).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(13).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_14 =>
- if GBT_NUM > 14 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (14).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(14).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(14).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (14).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(14).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(14).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (14).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(14).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(14).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(14).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_15 =>
- if GBT_NUM > 15 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (15).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(15).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(15).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (15).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(15).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(15).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (15).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(15).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(15).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(15).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_16 =>
- if GBT_NUM > 16 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (16).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(16).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(16).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (16).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(16).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(16).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (16).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(16).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(16).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(16).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_17 =>
- if GBT_NUM > 17 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (17).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(17).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(17).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (17).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(17).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(17).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (17).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(17).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(17).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(17).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_18 =>
- if GBT_NUM > 18 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (18).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(18).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(18).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (18).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(18).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(18).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (18).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(18).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(18).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(18).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_19 =>
- if GBT_NUM > 19 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (19).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(19).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(19).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (19).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(19).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(19).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (19).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(19).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(19).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(19).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_20 =>
- if GBT_NUM > 20 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (20).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(20).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(20).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (20).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(20).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(20).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (20).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(20).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(20).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(20).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_21 =>
- if GBT_NUM > 21 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (21).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(21).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(21).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (21).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(21).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(21).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (21).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(21).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(21).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(21).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_22 =>
- if GBT_NUM > 22 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (22).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(22).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(22).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (22).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(22).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(22).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (22).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(22).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(22).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(22).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_23 =>
- if GBT_NUM > 23 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (23).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(23).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(23).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (23).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(23).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(23).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (23).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(23).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(23).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(23).EC_ENABLE; -- Enables the EC channel
- end if;
- when REG_TTC_TOHOST_ENABLE => register_read_data_25_s(0 downto 0) <= register_map_control_s.TTC_TOHOST_ENABLE; -- Enables the ToHost Mini Egroup in TTC mode
- when REG_DECODING_REVERSE_10B => register_read_data_25_s(0 downto 0) <= register_map_control_s.DECODING_REVERSE_10B; -- Reverse 10-bit word of elink data for 8b10b E-links
- -- 1: Receive 10-bit word in ToHost E-Paths, MSB first
- -- 0: Receive 10-bit word in ToHost E-Paths, LSB first
-
- when REG_ENCODING_REVERSE_10B => register_read_data_25_s(0 downto 0) <= register_map_control_s.ENCODING_REVERSE_10B; -- Reverse 10-bit word of elink data for 8b10b E-links. 1 MSB first, 0 LSB first
- when REG_ENCODING_LINK00_EGROUP0_CTRL =>
- if GBT_NUM > 0 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (0)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(0).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK00_EGROUP1_CTRL =>
- if GBT_NUM > 0 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (0)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(1).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK00_EGROUP2_CTRL =>
- if GBT_NUM > 0 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (0)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(2).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK00_EGROUP3_CTRL =>
- if GBT_NUM > 0 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (0)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(3).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK00_EGROUP4_CTRL =>
- if GBT_NUM > 0 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (0)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(4).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK01_EGROUP0_CTRL =>
- if GBT_NUM > 1 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (1)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(0).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK01_EGROUP1_CTRL =>
- if GBT_NUM > 1 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (1)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(1).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK01_EGROUP2_CTRL =>
- if GBT_NUM > 1 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (1)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(2).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK01_EGROUP3_CTRL =>
- if GBT_NUM > 1 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (1)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(3).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK01_EGROUP4_CTRL =>
- if GBT_NUM > 1 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (1)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(4).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK02_EGROUP0_CTRL =>
- if GBT_NUM > 2 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (2)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(0).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK02_EGROUP1_CTRL =>
- if GBT_NUM > 2 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (2)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(1).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK02_EGROUP2_CTRL =>
- if GBT_NUM > 2 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (2)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(2).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK02_EGROUP3_CTRL =>
- if GBT_NUM > 2 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (2)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(3).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK02_EGROUP4_CTRL =>
- if GBT_NUM > 2 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (2)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(4).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK03_EGROUP0_CTRL =>
- if GBT_NUM > 3 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (3)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(0).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK03_EGROUP1_CTRL =>
- if GBT_NUM > 3 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (3)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(1).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK03_EGROUP2_CTRL =>
- if GBT_NUM > 3 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (3)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(2).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK03_EGROUP3_CTRL =>
- if GBT_NUM > 3 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (3)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(3).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK03_EGROUP4_CTRL =>
- if GBT_NUM > 3 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (3)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(4).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK04_EGROUP0_CTRL =>
- if GBT_NUM > 4 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (4)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(0).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK04_EGROUP1_CTRL =>
- if GBT_NUM > 4 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (4)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(1).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK04_EGROUP2_CTRL =>
- if GBT_NUM > 4 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (4)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(2).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK04_EGROUP3_CTRL =>
- if GBT_NUM > 4 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (4)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(3).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK04_EGROUP4_CTRL =>
- if GBT_NUM > 4 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (4)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(4).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK05_EGROUP0_CTRL =>
- if GBT_NUM > 5 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (5)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(0).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK05_EGROUP1_CTRL =>
- if GBT_NUM > 5 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (5)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(1).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK05_EGROUP2_CTRL =>
- if GBT_NUM > 5 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (5)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(2).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK05_EGROUP3_CTRL =>
- if GBT_NUM > 5 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (5)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(3).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK05_EGROUP4_CTRL =>
- if GBT_NUM > 5 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (5)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(4).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK06_EGROUP0_CTRL =>
- if GBT_NUM > 6 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (6)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(0).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK06_EGROUP1_CTRL =>
- if GBT_NUM > 6 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (6)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(1).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK06_EGROUP2_CTRL =>
- if GBT_NUM > 6 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (6)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(2).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK06_EGROUP3_CTRL =>
- if GBT_NUM > 6 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (6)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(3).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK06_EGROUP4_CTRL =>
- if GBT_NUM > 6 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (6)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(4).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK07_EGROUP0_CTRL =>
- if GBT_NUM > 7 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (7)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(0).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK07_EGROUP1_CTRL =>
- if GBT_NUM > 7 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (7)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(1).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK07_EGROUP2_CTRL =>
- if GBT_NUM > 7 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (7)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(2).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK07_EGROUP3_CTRL =>
- if GBT_NUM > 7 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (7)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(3).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK07_EGROUP4_CTRL =>
- if GBT_NUM > 7 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (7)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(4).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK08_EGROUP0_CTRL =>
- if GBT_NUM > 8 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (8)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(0).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK08_EGROUP1_CTRL =>
- if GBT_NUM > 8 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (8)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(1).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK08_EGROUP2_CTRL =>
- if GBT_NUM > 8 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (8)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(2).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK08_EGROUP3_CTRL =>
- if GBT_NUM > 8 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (8)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(3).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK08_EGROUP4_CTRL =>
- if GBT_NUM > 8 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (8)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(4).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK09_EGROUP0_CTRL =>
- if GBT_NUM > 9 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (9)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(0).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK09_EGROUP1_CTRL =>
- if GBT_NUM > 9 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (9)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(1).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK09_EGROUP2_CTRL =>
- if GBT_NUM > 9 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (9)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(2).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK09_EGROUP3_CTRL =>
- if GBT_NUM > 9 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (9)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(3).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK09_EGROUP4_CTRL =>
- if GBT_NUM > 9 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (9)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(4).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK10_EGROUP0_CTRL =>
- if GBT_NUM > 10 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (10)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(0).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK10_EGROUP1_CTRL =>
- if GBT_NUM > 10 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (10)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(1).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK10_EGROUP2_CTRL =>
- if GBT_NUM > 10 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (10)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(2).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK10_EGROUP3_CTRL =>
- if GBT_NUM > 10 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (10)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(3).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK10_EGROUP4_CTRL =>
- if GBT_NUM > 10 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (10)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(4).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK11_EGROUP0_CTRL =>
- if GBT_NUM > 11 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (11)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(0).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK11_EGROUP1_CTRL =>
- if GBT_NUM > 11 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (11)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(1).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK11_EGROUP2_CTRL =>
- if GBT_NUM > 11 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (11)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(2).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK11_EGROUP3_CTRL =>
- if GBT_NUM > 11 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (11)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(3).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK11_EGROUP4_CTRL =>
- if GBT_NUM > 11 then
- register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
- register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (11)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
- register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
- register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(4).EPATH_ENA; -- Enable bits per E-PATH
- end if;
- when REG_MINI_EGROUP_FROMHOST_00 =>
- if GBT_NUM > 0 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (0).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(0).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(0).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (0).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(0).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(0).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (0).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(0).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(0).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(0).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_01 =>
- if GBT_NUM > 1 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (1).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(1).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(1).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (1).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(1).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(1).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (1).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(1).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(1).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(1).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_02 =>
- if GBT_NUM > 2 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (2).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(2).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(2).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (2).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(2).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(2).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (2).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(2).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(2).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(2).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_03 =>
- if GBT_NUM > 3 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (3).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(3).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(3).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (3).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(3).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(3).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (3).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(3).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(3).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(3).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_04 =>
- if GBT_NUM > 4 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (4).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(4).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(4).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (4).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(4).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(4).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (4).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(4).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(4).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(4).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_05 =>
- if GBT_NUM > 5 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (5).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(5).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(5).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (5).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(5).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(5).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (5).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(5).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(5).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(5).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_06 =>
- if GBT_NUM > 6 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (6).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(6).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(6).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (6).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(6).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(6).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (6).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(6).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(6).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(6).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_07 =>
- if GBT_NUM > 7 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (7).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(7).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(7).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (7).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(7).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(7).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (7).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(7).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(7).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(7).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_08 =>
- if GBT_NUM > 8 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (8).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(8).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(8).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (8).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(8).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(8).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (8).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(8).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(8).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(8).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_09 =>
- if GBT_NUM > 9 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (9).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(9).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(9).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (9).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(9).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(9).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (9).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(9).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(9).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(9).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_10 =>
- if GBT_NUM > 10 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (10).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(10).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(10).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (10).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(10).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(10).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (10).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(10).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(10).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(10).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_11 =>
- if GBT_NUM > 11 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (11).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(11).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(11).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (11).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(11).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(11).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (11).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(11).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(11).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(11).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_12 =>
- if GBT_NUM > 12 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (12).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(12).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(12).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (12).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(12).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(12).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (12).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(12).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(12).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(12).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_13 =>
- if GBT_NUM > 13 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (13).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(13).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(13).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (13).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(13).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(13).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (13).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(13).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(13).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(13).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_14 =>
- if GBT_NUM > 14 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (14).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(14).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(14).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (14).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(14).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(14).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (14).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(14).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(14).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(14).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_15 =>
- if GBT_NUM > 15 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (15).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(15).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(15).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (15).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(15).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(15).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (15).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(15).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(15).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(15).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_16 =>
- if GBT_NUM > 16 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (16).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(16).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(16).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (16).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(16).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(16).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (16).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(16).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(16).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(16).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_17 =>
- if GBT_NUM > 17 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (17).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(17).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(17).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (17).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(17).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(17).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (17).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(17).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(17).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(17).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_18 =>
- if GBT_NUM > 18 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (18).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(18).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(18).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (18).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(18).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(18).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (18).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(18).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(18).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(18).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_19 =>
- if GBT_NUM > 19 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (19).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(19).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(19).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (19).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(19).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(19).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (19).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(19).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(19).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(19).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_20 =>
- if GBT_NUM > 20 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (20).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(20).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(20).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (20).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(20).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(20).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (20).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(20).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(20).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(20).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_21 =>
- if GBT_NUM > 21 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (21).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(21).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(21).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (21).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(21).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(21).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (21).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(21).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(21).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(21).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_22 =>
- if GBT_NUM > 22 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (22).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(22).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(22).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (22).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(22).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(22).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (22).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(22).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(22).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(22).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_23 =>
- if GBT_NUM > 23 then
- register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (23).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
- register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(23).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(23).AUX_ENABLE; -- Enables the AUX channel
- register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (23).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
- register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(23).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(23).IC_ENABLE; -- Enables the IC channel
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (23).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
- register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(23).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(23).EC_ENCODING; -- Configures encoding of the EC channel
- register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(23).EC_ENABLE; -- Configures the FromHost Mini egroup
- end if;
- when REG_FE_EMU_ENA => register_read_data_25_s(1 downto 1) <= register_map_control_s.FE_EMU_ENA.EMU_TOFRONTEND; -- Enable GBT dummy emulator ToFrontEnd
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FE_EMU_ENA.EMU_TOHOST; -- Enable GBT dummy emulator ToHost
- when REG_FE_EMU_CONFIG => register_read_data_25_s(54 downto 47) <= register_map_control_s.FE_EMU_CONFIG.WE; -- write enable array, every bit is one emulator RAM block
- register_read_data_25_s(46 downto 33) <= register_map_control_s.FE_EMU_CONFIG.WRADDR; -- write address bus
- register_read_data_25_s(32 downto 0) <= register_map_control_s.FE_EMU_CONFIG.WRDATA; -- write data bus
- when REG_FE_EMU_READ => register_read_data_25_s(35 downto 33) <= register_map_control_s.FE_EMU_READ.SEL; -- Select ramblock to read back
- register_read_data_25_s(32 downto 0) <= register_map_monitor_s.register_map_gbtemu_monitor.FE_EMU_READ.DATA; -- Read back ramblock at FE_EMU_CONFIG.WRADDR
- when REG_GBT_CHANNEL_DISABLE => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_CHANNEL_DISABLE; -- Disable selected lpGBT, GBT or FULL mode channel
- when REG_GBT_GENERAL_CTRL => register_read_data_25_s(63 downto 0) <= register_map_control_s.GBT_GENERAL_CTRL; -- Alignment chk reset (not self clearing)
- when REG_GBT_MODE_CTRL => register_read_data_25_s(2 downto 2) <= register_map_control_s.GBT_MODE_CTRL.RX_ALIGN_TB_SW; -- RX_ALIGN_TB_SW
- register_read_data_25_s(1 downto 1) <= register_map_control_s.GBT_MODE_CTRL.RX_ALIGN_SW; -- RX_ALIGN_SW
- register_read_data_25_s(0 downto 0) <= register_map_control_s.GBT_MODE_CTRL.DESMUX_USE_SW; -- DESMUX_USE_SW
- when REG_GBT_RXSLIDE_SELECT =>
- if GBT_GENERATE_ALL_REGS then
- register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_RXSLIDE_SELECT; -- RxSlide select [47:0]
- end if;
- when REG_GBT_RXSLIDE_MANUAL =>
- if GBT_GENERATE_ALL_REGS then
- register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_RXSLIDE_MANUAL; -- RxSlide select [47:0]
- end if;
- when REG_GBT_TXUSRRDY =>
- if GBT_GENERATE_ALL_REGS then
- register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TXUSRRDY; -- TxUsrRdy [47:0]
- end if;
- when REG_GBT_RXUSRRDY =>
- if GBT_GENERATE_ALL_REGS then
- register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_RXUSRRDY; -- RxUsrRdy [47:0]
- end if;
- when REG_GBT_SOFT_RESET => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_SOFT_RESET; -- SOFT_RESET [47:0]
- when REG_GBT_GTTX_RESET => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_GTTX_RESET; -- GTTX_RESET [47:0]
- when REG_GBT_GTRX_RESET => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_GTRX_RESET; -- GTRX_RESET [47:0]
- when REG_GBT_PLL_RESET => register_read_data_25_s(59 downto 48) <= register_map_control_s.GBT_PLL_RESET.QPLL_RESET; -- QPLL_RESET [11:0]
- register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_PLL_RESET.CPLL_RESET; -- CPLL_RESET [47:0]
- when REG_GBT_SOFT_TX_RESET =>
- if GBT_GENERATE_ALL_REGS then
- register_read_data_25_s(59 downto 48) <= register_map_control_s.GBT_SOFT_TX_RESET.RESET_ALL; -- SOFT_TX_RESET_ALL [11:0]
- register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_SOFT_TX_RESET.RESET_GT; -- SOFT_TX_RESET_GT [47:0]
- end if;
- when REG_GBT_SOFT_RX_RESET =>
- if GBT_GENERATE_ALL_REGS then
- register_read_data_25_s(59 downto 48) <= register_map_control_s.GBT_SOFT_RX_RESET.RESET_ALL; -- SOFT_TX_RESET_ALL [11:0]
- register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_SOFT_RX_RESET.RESET_GT; -- SOFT_TX_RESET_GT [47:0]
- end if;
- when REG_GBT_ODD_EVEN =>
- if GBT_GENERATE_ALL_REGS then
- register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_ODD_EVEN; -- OddEven [47:0]
- end if;
- when REG_GBT_TOPBOT =>
- if GBT_GENERATE_ALL_REGS then
- register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TOPBOT; -- TopBot [47:0]
- end if;
- when REG_GBT_TX_TC_DLY_VALUE1 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TX_TC_DLY_VALUE1; -- TX_TC_DLY_VALUE [47:0]
- when REG_GBT_TX_TC_DLY_VALUE2 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TX_TC_DLY_VALUE2; -- TX_TC_DLY_VALUE [95:48]
- when REG_GBT_TX_TC_DLY_VALUE3 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TX_TC_DLY_VALUE3; -- TX_TC_DLY_VALUE [143:96]
- when REG_GBT_TX_TC_DLY_VALUE4 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TX_TC_DLY_VALUE4; -- TX_TC_DLY_VALUE [191:144]
- when REG_GBT_DATA_TXFORMAT1 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_DATA_TXFORMAT1; -- DATA_TXFORMAT [47:0]
- when REG_GBT_DATA_TXFORMAT2 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_DATA_TXFORMAT2; -- DATA_TXFORMAT [95:48]
- when REG_GBT_DATA_RXFORMAT1 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_DATA_RXFORMAT1; -- DATA_RXFORMAT [47:0]
- when REG_GBT_DATA_RXFORMAT2 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_DATA_RXFORMAT2; -- DATA_RXFORMAT [95:0]
- when REG_GBT_TX_RESET => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TX_RESET; -- TX Logic reset [47:0]
- when REG_GBT_RX_RESET => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_RX_RESET; -- RX Logic reset [47:0]
- when REG_GBT_TX_TC_METHOD => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TX_TC_METHOD; -- TX time domain crossing method [47:0]
- when REG_GBT_OUTMUX_SEL => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_OUTMUX_SEL; -- Descrambler output MUX selection [47:0]
- when REG_GBT_TC_EDGE => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TC_EDGE; -- Sampling edge selection for TX domain crossing [47:0]
- when REG_GBT_TXPOLARITY => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TXPOLARITY; -- 0: default polarity
- -- 1: reversed polarity for transmitter of GTH channels
-
- when REG_GBT_RXPOLARITY => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_RXPOLARITY; -- 0: default polarity
- -- 1: reversed polarity for the receiver of the GTH channels
-
- when REG_GTH_LOOPBACK_CONTROL => register_read_data_25_s(2 downto 0) <= register_map_control_s.GTH_LOOPBACK_CONTROL; -- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- -- 000: Normal operation
- -- 001: Near-End PCS Loopback
- -- 010: Near-End PMA Loopback
- -- 011: Reserved
- -- 100: Far-End PMA Loopback
- -- 101: Reserved
- -- 110: Far-End PCS Loopback
-
- when REG_GBT_TOHOST_FANOUT => register_read_data_25_s(48 downto 48) <= register_map_control_s.GBT_TOHOST_FANOUT.LOCK; -- Locks this particular register. If set prevents software from touching it.
- register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TOHOST_FANOUT.SEL; -- ToHost FanOut/Selector. Every bitfield is a channel:
- -- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- -- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- when REG_GBT_TOFRONTEND_FANOUT => register_read_data_25_s(48 downto 48) <= register_map_control_s.GBT_TOFRONTEND_FANOUT.LOCK; -- Locks this particular register. If set prevents software from touching it.
- register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TOFRONTEND_FANOUT.SEL; -- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- -- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- -- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
- --
-
- when REG_TTC_DEC_CTRL => register_read_data_25_s(26 downto 15) <= register_map_control_s.TTC_DEC_CTRL.BCID_ONBCR; -- BCID is set to this value when BCR arrives
- register_read_data_25_s(14 downto 14) <= register_map_monitor_s.register_map_ttc_monitor.TTC_DEC_CTRL.BUSY_OUTPUT_STATUS; -- Actual status of the BUSY LEMO output signal
- register_read_data_25_s(13 downto 13) <= register_map_control_s.TTC_DEC_CTRL.ECR_BCR_SWAP; -- ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
- register_read_data_25_s(12 downto 12) <= register_map_control_s.TTC_DEC_CTRL.BUSY_OUTPUT_INHIBIT; -- forces the Busy LEMO output to BUSY-OFF
- register_read_data_25_s(11 downto 11) <= register_map_control_s.TTC_DEC_CTRL.TOHOST_RST; -- reset toHost in ttc decoder
- register_read_data_25_s(10 downto 10) <= register_map_control_s.TTC_DEC_CTRL.TT_BCH_EN; -- trigger type enable / disable for TTC-ToHost
- register_read_data_25_s(9 downto 2) <= register_map_control_s.TTC_DEC_CTRL.XL1ID_SW; -- set XL1ID value, the value to be set by XL1ID_RST signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.TTC_DEC_CTRL.XL1ID_RST; -- giving a trigger signal to reset XL1ID value
- register_read_data_25_s(0 downto 0) <= register_map_control_s.TTC_DEC_CTRL.MASTER_BUSY; -- L1A trigger throttling
- when REG_TTC_EMU => register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_ttc_monitor.TTC_EMU.FULL; -- TTC Emulator memory full indication
- register_read_data_25_s(1 downto 1) <= register_map_control_s.TTC_EMU.SEL; -- Select TTC data source 1 TTC Emu | 0 TTC Decoder
- register_read_data_25_s(0 downto 0) <= register_map_control_s.TTC_EMU.ENA; -- Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
- when REG_TTC_DELAY_00 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_01 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (1); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_02 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (2); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_03 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (3); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_04 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (4); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_05 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (5); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_06 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (6); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_07 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (7); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_08 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (8); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_09 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (9); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_10 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (10); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_11 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (11); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_12 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (12); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_13 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (13); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_14 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (14); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_15 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (15); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_16 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (16); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_17 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (17); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_18 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (18); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_19 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (19); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_20 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (20); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_21 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (21); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_22 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (22); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_23 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (23); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_24 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (24); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_25 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (25); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_26 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (26); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_27 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (27); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_28 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (28); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_29 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (29); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_30 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (30); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_31 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (31); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_32 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (32); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_33 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (33); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_34 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (34); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_35 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (35); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_36 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (36); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_37 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (37); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_38 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (38); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_39 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (39); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_40 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (40); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_41 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (41); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_42 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (42); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_43 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (43); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_44 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (44); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_45 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (45); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_46 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (46); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_47 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (47); -- Controls the TTC Fanout delay values
- when REG_TTC_BUSY_TIMING_CTRL => register_read_data_25_s(51 downto 32) <= register_map_control_s.TTC_BUSY_TIMING_CTRL.PRESCALE; -- Prescales the 40MHz clock to create an internal slow clock
- register_read_data_25_s(31 downto 16) <= register_map_control_s.TTC_BUSY_TIMING_CTRL.BUSY_WIDTH; -- Minimum number of 40MHz clocks that the busy is asserted
- register_read_data_25_s(15 downto 0) <= register_map_control_s.TTC_BUSY_TIMING_CTRL.LIMIT_TIME; -- Number of prescaled clocks a given busy must be asserted before it is recognized
- when REG_TTC_BUSY_CLEAR => register_read_data_25_s(64 downto 64) <= register_map_control_s.TTC_BUSY_CLEAR; -- clears the latching busy bits in TTC_BUSY_ACCEPTED
- when REG_TTC_EMU_CONTROL => register_read_data_25_s(32 downto 27) <= register_map_control_s.TTC_EMU_CONTROL.BROADCAST; -- Broadcast data
- register_read_data_25_s(26 downto 26) <= register_map_control_s.TTC_EMU_CONTROL.ECR; -- Event counter reset
- register_read_data_25_s(25 downto 25) <= register_map_control_s.TTC_EMU_CONTROL.BCR; -- Bunch counter reset
- register_read_data_25_s(24 downto 24) <= register_map_control_s.TTC_EMU_CONTROL.L1A; -- Level 1 Accept
- when REG_TTC_EMU_L1A_PERIOD => register_read_data_25_s(31 downto 0) <= register_map_control_s.TTC_EMU_L1A_PERIOD; -- L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
- when REG_TTC_EMU_ECR_PERIOD => register_read_data_25_s(31 downto 0) <= register_map_control_s.TTC_EMU_ECR_PERIOD; -- ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
- when REG_TTC_EMU_BCR_PERIOD => register_read_data_25_s(31 downto 0) <= register_map_control_s.TTC_EMU_BCR_PERIOD; -- BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
- when REG_TTC_EMU_LONG_CHANNEL_DATA => register_read_data_25_s(31 downto 0) <= register_map_control_s.TTC_EMU_LONG_CHANNEL_DATA; -- Long channel data for the TTC emulator
- when REG_TTC_EMU_RESET => register_read_data_25_s(64 downto 64) <= register_map_control_s.TTC_EMU_RESET; -- Any write to this register resets the TTC Emulator to the default state.
- when REG_TTC_ECR_MONITOR => register_read_data_25_s(64 downto 64) <= register_map_control_s.TTC_ECR_MONITOR.CLEAR; -- Counts the number of ECRs received from the TTC system, any write to this register clears the counter
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_ECR_MONITOR.VALUE; -- Counts the number of ECRs received from the TTC system, any write to this register clears the counter
- when REG_TTC_TTYPE_MONITOR => register_read_data_25_s(64 downto 64) <= register_map_control_s.TTC_TTYPE_MONITOR.CLEAR; -- Counts the number of TType received from the TTC system, any write to this register clears the counter
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_TTYPE_MONITOR.VALUE; -- Counts the number of TType received from the TTC system, any write to this register clears the counter
- when REG_TTC_BCR_PERIODICITY_MONITOR => register_read_data_25_s(64 downto 64) <= register_map_control_s.TTC_BCR_PERIODICITY_MONITOR.CLEAR; -- Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BCR_PERIODICITY_MONITOR.VALUE; -- Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
- when REG_XOFF_FM_CH_FIFO_THRESH_LOW => register_read_data_25_s(3 downto 0) <= register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW; -- Controls the low threshold of the channel fifo in FULL mode on which
- -- an Xon will be asserted, bitfields control 4 MSB
-
- when REG_XOFF_FM_CH_FIFO_THRESH_HIGH => register_read_data_25_s(3 downto 0) <= register_map_control_s.XOFF_FM_CH_FIFO_THRESH_HIGH; -- Controls the high threshold of the channel fifo in FULL mode on which
- -- an Xoff will be asserted, bitfields control 4 MSB - name: XOFF_FM_LOW_THRESH_CROSSED
-
- when REG_XOFF_FM_HIGH_THRESH => register_read_data_25_s(64 downto 64) <= register_map_control_s.XOFF_FM_HIGH_THRESH.CLEAR_LATCH; -- Writing this register will clear all CROSS_LATCHED bits
- register_read_data_25_s(47 downto 24) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_FM_HIGH_THRESH.CROSS_LATCHED; -- FIFO filled beyond the high threshold, 1 latch bit per channel
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_FM_HIGH_THRESH.CROSSED; -- FIFO filled beyond the high threshold, 1 bit per channel
- when REG_XOFF_FM_SOFT_XOFF => register_read_data_25_s(23 downto 0) <= register_map_control_s.XOFF_FM_SOFT_XOFF; -- Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
- when REG_XOFF_ENABLE => register_read_data_25_s(23 downto 0) <= register_map_control_s.XOFF_ENABLE; -- Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
- when REG_DMA_BUSY_STATUS => register_read_data_25_s(64 downto 64) <= register_map_control_s.DMA_BUSY_STATUS.CLEAR_LATCH; -- Any write to this register clears TOHOST_BUSY_LATCHED
- register_read_data_25_s(4 downto 4) <= register_map_control_s.DMA_BUSY_STATUS.ENABLE; -- Enable the DMA buffer on the server as a source of busy
- register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_xoff_monitor.DMA_BUSY_STATUS.TOHOST_BUSY_LATCHED; -- A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_xoff_monitor.DMA_BUSY_STATUS.FROMHOST_BUSY_LATCHED; -- A fromhost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_xoff_monitor.DMA_BUSY_STATUS.FROMHOST_BUSY; -- A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.DMA_BUSY_STATUS.TOHOST_BUSY; -- A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- when REG_FM_BUSY_CHANNEL_STATUS => register_read_data_25_s(64 downto 64) <= register_map_control_s.FM_BUSY_CHANNEL_STATUS.CLEAR_LATCH; -- Any write to this register will clear the BUSY_LATCHED bits
- register_read_data_25_s(47 downto 24) <= register_map_monitor_s.register_map_xoff_monitor.FM_BUSY_CHANNEL_STATUS.BUSY_LATCHED; -- one Indicates that the given FULL mode channel has received BUSY-ON
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.FM_BUSY_CHANNEL_STATUS.BUSY; -- one Indicates that the given FULL mode channel is currently in BUSY state
- when REG_BUSY_MAIN_OUTPUT_FIFO_THRESH => register_read_data_25_s(24 downto 24) <= register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_THRESH.BUSY_ENABLE; -- Enable busy generation if thresholds are crossed
- register_read_data_25_s(23 downto 12) <= register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_THRESH.LOW; -- Low, Negate threshold of busy generation from main output fifo
- register_read_data_25_s(11 downto 0) <= register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_THRESH.HIGH; -- High, Assert threshold of busy generation from main output fifo
- when REG_BUSY_MAIN_OUTPUT_FIFO_STATUS => register_read_data_25_s(64 downto 64) <= register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_STATUS.CLEAR_LATCHED; -- Any write to this register will clear the
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_xoff_monitor.BUSY_MAIN_OUTPUT_FIFO_STATUS.HIGH_THRESH_CROSSED_LATCHED; -- Main output fifo has been full beyond HIGH THRESHOLD, write to clear
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_xoff_monitor.BUSY_MAIN_OUTPUT_FIFO_STATUS.HIGH_THRESH_CROSSED; -- Main output fifo is full beyond HIGH THRESHOLD
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.BUSY_MAIN_OUTPUT_FIFO_STATUS.LOW_THRESH_CROSSED; -- Main output fifo is full beyond LOW THRESHOLD
- when REG_ELINK_BUSY_ENABLE00 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE01 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (1); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE02 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (2); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE03 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (3); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE04 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (4); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE05 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (5); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE06 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (6); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE07 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (7); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE08 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (8); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE09 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (9); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE10 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (10); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE11 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (11); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE12 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (12); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE13 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (13); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE14 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (14); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE15 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (15); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE16 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (16); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE17 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (17); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE18 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (18); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE19 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (19); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE20 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (20); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE21 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (21); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE22 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (22); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE23 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (23); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_HK_CTRL_I2C => register_read_data_25_s(1 downto 1) <= register_map_control_s.HK_CTRL_I2C.CONFIG_TRIG; -- i2c_config_trig
- register_read_data_25_s(0 downto 0) <= register_map_control_s.HK_CTRL_I2C.CLKFREQ_SEL; -- i2c_clkfreq_sel
- when REG_HK_CTRL_FMC => register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_hk_monitor.HK_CTRL_FMC.SI5345_LOL; -- Loss of lock pin, only connected on FLX711
- register_read_data_25_s(6 downto 5) <= register_map_control_s.HK_CTRL_FMC.SI5345_INSEL; -- Selects the input clock source
- -- 0 : FPGA (FMC LA01)
- -- 1 : FMC OSC (40.079 MHz)
- -- 2 : FPGA (FMC LA18)
-
- register_read_data_25_s(4 downto 3) <= register_map_control_s.HK_CTRL_FMC.SI5345_A; -- Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- register_read_data_25_s(2 downto 2) <= register_map_control_s.HK_CTRL_FMC.SI5345_OE; -- Si5345 active low output enable (0:enable)
- register_read_data_25_s(1 downto 1) <= register_map_control_s.HK_CTRL_FMC.SI5345_RSTN; -- Si5345 active low output enable (0:reset)
- register_read_data_25_s(0 downto 0) <= register_map_control_s.HK_CTRL_FMC.SI5345_SEL; -- Si5345 programming mode
- -- 1 : I2C mode (default)
- -- 0 : SPI mode
-
- when REG_HK_MON_FMC => register_read_data_25_s(1 downto 1) <= register_map_control_s.HK_MON_FMC.SI5345_LOL; -- Si5345 Loss Of Lock pin
- register_read_data_25_s(0 downto 0) <= register_map_control_s.HK_MON_FMC.SI5345_INTR; -- Si5345 Interrupt flagging chip change of status
- when REG_MMCM_MAIN => register_read_data_25_s(3 downto 3) <= register_map_control_s.MMCM_MAIN.LCLK_SEL; -- 1: LCLK
- -- 0: TTC
-
- register_read_data_25_s(2 downto 1) <= register_map_monitor_s.register_map_hk_monitor.MMCM_MAIN.MAIN_INPUT; -- Main MMCM Oscillator Input
- -- 2: LCLK fixed
- -- 1: TTC fixed
- -- 0: selectable
-
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_hk_monitor.MMCM_MAIN.PLL_LOCK; -- Main MMCM PLL Lock Status
- when REG_I2C_WR => register_read_data_25_s(64 downto 64) <= register_map_control_s.I2C_WR.I2C_WREN; -- Any write to this register triggers an I2C read or write sequence
- register_read_data_25_s(25 downto 25) <= register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL; -- I2C FIFO full
- register_read_data_25_s(24 downto 24) <= register_map_control_s.I2C_WR.WRITE_2BYTES; -- Write two bytes
- register_read_data_25_s(23 downto 16) <= register_map_control_s.I2C_WR.DATA_BYTE2; -- Data byte 2
- register_read_data_25_s(15 downto 8) <= register_map_control_s.I2C_WR.DATA_BYTE1; -- Data byte 1
- register_read_data_25_s(7 downto 1) <= register_map_control_s.I2C_WR.SLAVE_ADDRESS; -- Slave address
- register_read_data_25_s(0 downto 0) <= register_map_control_s.I2C_WR.READ_NOT_WRITE; -- READ/<o>WRITE</o>
- when REG_I2C_RD => register_read_data_25_s(64 downto 64) <= register_map_control_s.I2C_RD.I2C_RDEN; -- Any write to this register pops the last I2C data from the FIFO
- register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY; -- I2C FIFO Empty
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_DOUT; -- I2C READ Data
- when REG_INT_TEST => register_read_data_25_s(64 downto 64) <= register_map_control_s.INT_TEST.TRIGGER; -- Fire a test MSIx interrupt set in IRQ
- register_read_data_25_s(3 downto 0) <= register_map_control_s.INT_TEST.IRQ; -- Set this field to a value equal to the MSIX interrupt to be fired. The write triggers the interrupt immediately.
- when REG_CONFIG_FLASH_WR => register_read_data_25_s(57 downto 57) <= register_map_control_s.CONFIG_FLASH_WR.FAST_WRITE; -- Write command only. Only used for fast programming.
- register_read_data_25_s(56 downto 56) <= register_map_control_s.CONFIG_FLASH_WR.FAST_READ; -- Status reading without command writing. Only used for fast programming.
- register_read_data_25_s(55 downto 55) <= register_map_control_s.CONFIG_FLASH_WR.PAR_CTRL; -- Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- register_read_data_25_s(54 downto 53) <= register_map_control_s.CONFIG_FLASH_WR.PAR_WR; -- Choose Flash partition. Valid when PAR_CTRL is 1.
- register_read_data_25_s(52 downto 52) <= register_map_control_s.CONFIG_FLASH_WR.FLASH_SEL; -- 1 takes control over flash, 0 gives JTAG control over flash
- register_read_data_25_s(51 downto 51) <= register_map_control_s.CONFIG_FLASH_WR.DO_INIT; -- Untested feature, don't use it yet.
- register_read_data_25_s(50 downto 50) <= register_map_control_s.CONFIG_FLASH_WR.DO_READSTATUS; -- Reads status from flash
- register_read_data_25_s(49 downto 49) <= register_map_control_s.CONFIG_FLASH_WR.DO_CLEARSTATUS; -- Clears status reading from flash, back to normal flash operation
- register_read_data_25_s(48 downto 48) <= register_map_control_s.CONFIG_FLASH_WR.DO_ERASEBLOCK; -- Erased the current block of the flash, this register has to be cleared by software
- register_read_data_25_s(47 downto 47) <= register_map_control_s.CONFIG_FLASH_WR.DO_UNLOCK_BLOCK; -- Unlock writes to the current block, this register has to be cleared by software
- register_read_data_25_s(46 downto 46) <= register_map_control_s.CONFIG_FLASH_WR.DO_READ; -- Reads the 16 bits from current address, this register has to be cleared by software
- register_read_data_25_s(45 downto 45) <= register_map_control_s.CONFIG_FLASH_WR.DO_WRITE; -- Writes the 16 bits to current address, this register has to be cleared by software
- register_read_data_25_s(44 downto 44) <= register_map_control_s.CONFIG_FLASH_WR.DO_READDEVICEID; -- DIN should return 0x0089, this register has to be cleared by software
- register_read_data_25_s(43 downto 43) <= register_map_control_s.CONFIG_FLASH_WR.DO_RESET; -- Can be used in the future, currently disconnected in firmware
- register_read_data_25_s(42 downto 16) <= register_map_control_s.CONFIG_FLASH_WR.ADDRESS; -- Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- register_read_data_25_s(15 downto 0) <= register_map_control_s.CONFIG_FLASH_WR.WRITE_DATA; -- Value of data to write towards flash
- when REG_RXUSRCLK_FREQ => register_read_data_25_s(38 downto 38) <= register_map_monitor_s.register_map_hk_monitor.RXUSRCLK_FREQ.VALID; -- Indicates that the frequency measurement is valid
- register_read_data_25_s(37 downto 32) <= register_map_control_s.RXUSRCLK_FREQ.CHANNEL; -- Select the Transceiver channel to measure the clock from.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_hk_monitor.RXUSRCLK_FREQ.VAL; -- Frequency in Hz of the selected channel
- when REG_FELIG_DATA_GEN_CONFIG_00 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(0).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(0).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(0).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(0).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(0).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(0).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_01 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(1).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(1).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(1).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(1).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(1).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(1).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_02 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(2).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(2).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(2).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(2).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(2).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(2).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_03 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(3).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(3).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(3).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(3).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(3).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(3).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_04 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(4).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(4).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(4).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(4).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(4).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(4).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_05 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(5).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(5).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(5).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(5).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(5).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(5).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_06 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(6).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(6).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(6).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(6).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(6).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(6).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_07 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(7).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(7).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(7).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(7).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(7).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(7).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_08 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(8).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(8).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(8).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(8).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(8).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(8).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_09 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(9).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(9).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(9).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(9).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(9).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(9).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_10 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(10).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(10).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(10).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(10).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(10).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(10).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_11 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(11).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(11).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(11).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(11).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(11).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(11).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_12 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(12).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(12).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(12).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(12).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(12).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(12).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_13 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(13).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(13).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(13).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(13).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(13).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(13).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_14 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(14).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(14).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(14).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(14).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(14).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(14).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_15 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(15).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(15).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(15).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(15).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(15).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(15).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_16 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(16).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(16).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(16).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(16).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(16).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(16).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_17 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(17).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(17).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(17).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(17).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(17).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(17).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_18 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(18).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(18).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(18).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(18).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(18).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(18).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_19 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(19).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(19).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(19).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(19).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(19).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(19).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_20 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(20).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(20).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(20).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(20).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(20).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(20).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_21 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(21).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(21).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(21).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(21).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(21).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(21).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_22 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(22).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(22).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(22).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(22).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(22).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(22).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_DATA_GEN_CONFIG_23 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(23).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(23).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
- register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(23).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(23).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(23).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
- register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(23).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
- when REG_FELIG_ELINK_CONFIG_00 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(0).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(0).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(0).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_01 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(1).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(1).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(1).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_02 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(2).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(2).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(2).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_03 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(3).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(3).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(3).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_04 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(4).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(4).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(4).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_05 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(5).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(5).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(5).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_06 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(6).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(6).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(6).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_07 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(7).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(7).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(7).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_08 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(8).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(8).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(8).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_09 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(9).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(9).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(9).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_10 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(10).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(10).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(10).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_11 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(11).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(11).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(11).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_12 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(12).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(12).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(12).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_13 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(13).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(13).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(13).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_14 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(14).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(14).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(14).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_15 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(15).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(15).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(15).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_16 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(16).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(16).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(16).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_17 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(17).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(17).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(17).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_18 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(18).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(18).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(18).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_19 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(19).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(19).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(19).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_20 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(20).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(20).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(20).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_21 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(21).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(21).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(21).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_22 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(22).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(22).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(22).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_CONFIG_23 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(23).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(23).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(23).OUTPUT_WIDTH; -- FELIG elink data output width.
- end if;
- when REG_FELIG_ELINK_ENABLE_00 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_01 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(1); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_02 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(2); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_03 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(3); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_04 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(4); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_05 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(5); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_06 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(6); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_07 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(7); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_08 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(8); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_09 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(9); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_10 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(10); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_11 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(11); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_12 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(12); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_13 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(13); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_14 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(14); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_15 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(15); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_16 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(16); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_17 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(17); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_18 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(18); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_19 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(19); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_20 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(20); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_21 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(21); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_22 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(22); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_ELINK_ENABLE_23 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(23); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
- end if;
- when REG_FELIG_GLOBAL_CONTROL =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 36) <= register_map_control_s.FELIG_GLOBAL_CONTROL.FAKE_L1A_RATE; -- Sets the internal fake L1 trigger rate. [25ns/LSB]
- register_read_data_25_s(35 downto 14) <= register_map_control_s.FELIG_GLOBAL_CONTROL.PICXO_OFFSET_PPM; -- When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
- register_read_data_25_s(12 downto 12) <= register_map_control_s.FELIG_GLOBAL_CONTROL.TRACK_DATA; -- FELIG GT core control. Must be set to enable normal operation.
- register_read_data_25_s(11 downto 11) <= register_map_control_s.FELIG_GLOBAL_CONTROL.RXUSERRDY; -- FELIG GT core control. Must be set to enable normal operation.
- register_read_data_25_s(10 downto 10) <= register_map_control_s.FELIG_GLOBAL_CONTROL.TXUSERRDY; -- FELIG GT core control. Must be set to enable normal operation.
- register_read_data_25_s(9 downto 9) <= register_map_control_s.FELIG_GLOBAL_CONTROL.AUTO_RESET; -- FELIG GT core control. If set the GT core automatically resets on data error.
- register_read_data_25_s(8 downto 8) <= register_map_control_s.FELIG_GLOBAL_CONTROL.PICXO_RESET; -- FELIG GT core control. Manual PICXO reset.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_GLOBAL_CONTROL.GTTX_RESET; -- FELIG GT core control. Manual GT TX reset
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_GLOBAL_CONTROL.CPLL_RESET; -- FELIG GT core control. Manual CPLL reset.
- register_read_data_25_s(5 downto 0) <= register_map_control_s.FELIG_GLOBAL_CONTROL.X3_X4_OUTPUT_SELECT; -- X3/X4 SMA output source select.
- end if;
- when REG_FELIG_LANE_CONFIG_00 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(0).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(0).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(0).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(0).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(0).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(0).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(0).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(0).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(0).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(0).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(0).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_01 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(1).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(1).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(1).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(1).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(1).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(1).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(1).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(1).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(1).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(1).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(1).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_02 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(2).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(2).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(2).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(2).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(2).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(2).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(2).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(2).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(2).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(2).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(2).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_03 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(3).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(3).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(3).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(3).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(3).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(3).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(3).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(3).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(3).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(3).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(3).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_04 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(4).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(4).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(4).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(4).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(4).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(4).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(4).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(4).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(4).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(4).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(4).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_05 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(5).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(5).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(5).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(5).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(5).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(5).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(5).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(5).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(5).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(5).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(5).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_06 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(6).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(6).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(6).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(6).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(6).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(6).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(6).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(6).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(6).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(6).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(6).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_07 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(7).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(7).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(7).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(7).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(7).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(7).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(7).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(7).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(7).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(7).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(7).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_08 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(8).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(8).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(8).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(8).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(8).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(8).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(8).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(8).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(8).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(8).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(8).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_09 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(9).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(9).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(9).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(9).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(9).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(9).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(9).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(9).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(9).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(9).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(9).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_10 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(10).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(10).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(10).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(10).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(10).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(10).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(10).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(10).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(10).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(10).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(10).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_11 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(11).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(11).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(11).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(11).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(11).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(11).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(11).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(11).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(11).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(11).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(11).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_12 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(12).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(12).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(12).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(12).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(12).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(12).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(12).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(12).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(12).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(12).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(12).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_13 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(13).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(13).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(13).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(13).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(13).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(13).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(13).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(13).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(13).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(13).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(13).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_14 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(14).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(14).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(14).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(14).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(14).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(14).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(14).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(14).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(14).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(14).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(14).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_15 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(15).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(15).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(15).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(15).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(15).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(15).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(15).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(15).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(15).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(15).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(15).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_16 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(16).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(16).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(16).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(16).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(16).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(16).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(16).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(16).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(16).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(16).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(16).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_17 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(17).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(17).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(17).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(17).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(17).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(17).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(17).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(17).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(17).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(17).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(17).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_18 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(18).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(18).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(18).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(18).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(18).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(18).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(18).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(18).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(18).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(18).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(18).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_19 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(19).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(19).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(19).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(19).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(19).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(19).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(19).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(19).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(19).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(19).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(19).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_20 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(20).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(20).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(20).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(20).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(20).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(20).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(20).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(20).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(20).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(20).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(20).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_21 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(21).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(21).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(21).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(21).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(21).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(21).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(21).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(21).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(21).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(21).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(21).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_22 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(22).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(22).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(22).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(22).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(22).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(22).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(22).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(22).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(22).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(22).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(22).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_LANE_CONFIG_23 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(23).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(23).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(23).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(23).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(23).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(23).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(23).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(23).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(23).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(23).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(23).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
- end if;
- when REG_FELIG_MON_FREQ_GLOBAL =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_control_s.FELIG_MON_FREQ_GLOBAL.XTAL_100MHZ; -- FELIG local oscillator frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_control_s.FELIG_MON_FREQ_GLOBAL.CLK_41_667MHZ; -- FELIG PCIE MGTREFCLK frequency[Hz].
- end if;
- when REG_FELIG_RESET =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_RESET.LB_FIFO; -- One bit per lane. When set to 1, resets all loopback FIFOs.
- register_read_data_25_s(47 downto 24) <= register_map_control_s.FELIG_RESET.FRAMEGEN; -- One bit per lane. When set to 1, resets all FELIG link checking logic.
- register_read_data_25_s(23 downto 0) <= register_map_control_s.FELIG_RESET.LANE; -- One bit per lane. When set to 1, resets all FELIG lane logic.
- end if;
- when REG_FELIG_RX_SLIDE_RESET =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.FELIG_RX_SLIDE_RESET; -- One bit per lane. When set to 1, resets the gbt rx slide counter.
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_00 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(0).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(0).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_01 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(1).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(1).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_02 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(2).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(2).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_03 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(3).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(3).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_04 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(4).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(4).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_05 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(5).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(5).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_06 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(6).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(6).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_07 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(7).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(7).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_08 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(8).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(8).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_09 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(9).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(9).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_10 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(10).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(10).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_11 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(11).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(11).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_12 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(12).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(12).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_13 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(13).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(13).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_14 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(14).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(14).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_15 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(15).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(15).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_16 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(16).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(16).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_17 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(17).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(17).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_18 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(18).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(18).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_19 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(19).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(19).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_20 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(20).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(20).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_21 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(21).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(21).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_22 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(22).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(22).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_23 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(23).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
- register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(23).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
- end if;
- when REG_FMEMU_EVENT_INFO =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_control_s.FMEMU_EVENT_INFO.L1ID; -- 32b field to show L1ID
- register_read_data_25_s(31 downto 0) <= register_map_control_s.FMEMU_EVENT_INFO.BCID; -- 32b field to show BCID
- end if;
- when REG_FMEMU_COUNTERS =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.FMEMU_COUNTERS.WORD_CNT; -- Number of 32b words in one chunk
- register_read_data_25_s(47 downto 32) <= register_map_control_s.FMEMU_COUNTERS.IDLE_CNT; -- Minimum number of idles between chunks
- register_read_data_25_s(31 downto 16) <= register_map_control_s.FMEMU_COUNTERS.L1A_CNT; -- Number of chunks to send if not in TTC mode
- register_read_data_25_s(15 downto 8) <= register_map_control_s.FMEMU_COUNTERS.BUSY_TH_HIGH; -- Assert BUSY-ON above this threshold
- register_read_data_25_s(7 downto 0) <= register_map_control_s.FMEMU_COUNTERS.BUSY_TH_LOW; -- De-assert BUSY-ON below this threshold
- end if;
- when REG_FMEMU_CONTROL =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 56) <= register_map_control_s.FMEMU_CONTROL.L1A_BITNR; -- Bitfield for L1A in TTC frame
- register_read_data_25_s(55 downto 48) <= register_map_control_s.FMEMU_CONTROL.XONXOFF_BITNR; -- Bitfield for Xon/Xoff in TTC frame
- register_read_data_25_s(47 downto 47) <= register_map_control_s.FMEMU_CONTROL.EMU_START; -- Start emulator functionality
- register_read_data_25_s(46 downto 46) <= register_map_control_s.FMEMU_CONTROL.TTC_MODE; -- Control the emulator by TTC input or by RegMap (1/0)
- register_read_data_25_s(45 downto 45) <= register_map_control_s.FMEMU_CONTROL.XONXOFF; -- Debug Xon/Xoff functionality (1/0)
- register_read_data_25_s(44 downto 44) <= register_map_control_s.FMEMU_CONTROL.INLC_CRC32; -- 0: No checksum
- -- 1: Append the data with a CRC32
-
- register_read_data_25_s(43 downto 43) <= register_map_control_s.FMEMU_CONTROL.BCR; -- Reset BCID to 0
- register_read_data_25_s(42 downto 42) <= register_map_control_s.FMEMU_CONTROL.ECR; -- Reset L1ID to 0
- register_read_data_25_s(41 downto 41) <= register_map_control_s.FMEMU_CONTROL.DATA_SRC_SEL; -- Data source select
- -- 0: Data input comes from EMURAM
- -- 1: Data input comes from PCIe
-
- register_read_data_25_s(40 downto 32) <= register_map_monitor_s.register_map_generators.FMEMU_CONTROL.INT_STATUS_EMU; -- Read internal status emulator
- register_read_data_25_s(31 downto 16) <= register_map_control_s.FMEMU_CONTROL.FFU_FM_EMU_T; -- For Future Use (trigger registers)
- register_read_data_25_s(15 downto 0) <= register_map_control_s.FMEMU_CONTROL.FFU_FM_EMU_W; -- For Future Use (write registers)
- end if;
- when REG_FMEMU_RANDOM_RAM_ADDR =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FMEMU_RANDOM_RAM_ADDR; -- Controls the address of the ramblock for the random number generator
- end if;
- when REG_FMEMU_RANDOM_RAM =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.FMEMU_RANDOM_RAM.WE; -- Any write to this register (DATA) triggers a write to the ramblock
- register_read_data_25_s(39 downto 16) <= register_map_control_s.FMEMU_RANDOM_RAM.CHANNEL_SELECT; -- Enable write enable only for the selected channel
- register_read_data_25_s(15 downto 0) <= register_map_control_s.FMEMU_RANDOM_RAM.DATA; -- DATA field to be written to FMEMU_RANDOM_RAM_ADDR
- end if;
- when REG_FMEMU_RANDOM_CONTROL =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(20 downto 20) <= register_map_control_s.FMEMU_RANDOM_CONTROL.SELECT_RANDOM; -- 1 enables the random chunk length, 0 uses a constant chunk length
- register_read_data_25_s(19 downto 10) <= register_map_control_s.FMEMU_RANDOM_CONTROL.SEED; -- Seed for the random number generator, should not be 0
- register_read_data_25_s(9 downto 0) <= register_map_control_s.FMEMU_RANDOM_CONTROL.POLYNOMIAL; -- POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
- end if;
- when REG_WISHBONE_CONTROL => register_read_data_25_s(32 downto 32) <= register_map_control_s.WISHBONE_CONTROL.WRITE_NOT_READ; -- wishbone write command wishbone read command
- register_read_data_25_s(31 downto 0) <= register_map_control_s.WISHBONE_CONTROL.ADDRESS; -- Slave address for Wishbone bus
- when REG_WISHBONE_WRITE => register_read_data_25_s(64 downto 64) <= register_map_control_s.WISHBONE_WRITE.WRITE_ENABLE; -- Any write to this register triggers a write to the Wupper to Wishbone fifo
- register_read_data_25_s(32 downto 32) <= register_map_monitor_s.wishbone_monitor.WISHBONE_WRITE.FULL; -- Wishbone
- register_read_data_25_s(31 downto 0) <= register_map_control_s.WISHBONE_WRITE.DATA; -- Wishbone
- when REG_WISHBONE_READ => register_read_data_25_s(64 downto 64) <= register_map_control_s.WISHBONE_READ.READ_ENABLE; -- Any write to this register triggers a read from the Wishbone to Wupper fifo
- register_read_data_25_s(32 downto 32) <= register_map_monitor_s.wishbone_monitor.WISHBONE_READ.EMPTY; -- Indicates that the Wishbone to Wupper fifo is empty
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.wishbone_monitor.WISHBONE_READ.DATA; -- Wishbone read data
- when REG_GLOBAL_STRIPS_CONFIG => register_read_data_25_s(64 downto 64) <= register_map_control_s.GLOBAL_STRIPS_CONFIG.TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
- register_read_data_25_s(0 downto 0) <= register_map_control_s.GLOBAL_STRIPS_CONFIG.TTC_GENERATE_GATING_ENABLE; -- Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR. TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work. (See also BC_START, and BC_STOP fields)
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_0 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (0)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (0)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (0)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (0)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (0)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (0)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (0)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (0)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (0)(0).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (0)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(0).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(0).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_1 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (0)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (0)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (0)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (0)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (0)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (0)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (0)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (0)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (0)(1).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (0)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(1).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(1).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_2 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (0)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (0)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (0)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (0)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (0)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (0)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (0)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (0)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (0)(2).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (0)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(2).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(2).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_3 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (0)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (0)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (0)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (0)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (0)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (0)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (0)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (0)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (0)(3).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (0)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(3).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(3).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_R3L1_LINK_00_R3L1_0 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (0)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (0)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (0)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_00_R3L1_1 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (0)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (0)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (0)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_00_R3L1_2 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (0)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (0)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (0)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_00_R3L1_3 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (0)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (0)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (0)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_0 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (1)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (1)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (1)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (1)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (1)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (1)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (1)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (1)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (1)(0).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (1)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(0).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(0).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_1 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (1)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (1)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (1)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (1)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (1)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (1)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (1)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (1)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (1)(1).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (1)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(1).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(1).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_2 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (1)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (1)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (1)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (1)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (1)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (1)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (1)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (1)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (1)(2).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (1)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(2).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(2).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_3 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (1)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (1)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (1)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (1)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (1)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (1)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (1)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (1)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (1)(3).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (1)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(3).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(3).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_R3L1_LINK_01_R3L1_0 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (1)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (1)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (1)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_01_R3L1_1 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (1)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (1)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (1)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_01_R3L1_2 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (1)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (1)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (1)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_01_R3L1_3 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (1)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (1)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (1)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_0 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (2)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (2)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (2)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (2)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (2)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (2)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (2)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (2)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (2)(0).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (2)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(0).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(0).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_1 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (2)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (2)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (2)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (2)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (2)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (2)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (2)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (2)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (2)(1).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (2)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(1).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(1).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_2 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (2)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (2)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (2)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (2)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (2)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (2)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (2)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (2)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (2)(2).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (2)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(2).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(2).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_3 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (2)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (2)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (2)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (2)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (2)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (2)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (2)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (2)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (2)(3).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (2)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(3).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(3).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_R3L1_LINK_02_R3L1_0 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (2)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (2)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (2)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_02_R3L1_1 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (2)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (2)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (2)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_02_R3L1_2 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (2)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (2)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (2)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_02_R3L1_3 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (2)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (2)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (2)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_0 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (3)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (3)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (3)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (3)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (3)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (3)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (3)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (3)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (3)(0).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (3)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(0).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(0).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_1 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (3)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (3)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (3)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (3)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (3)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (3)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (3)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (3)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (3)(1).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (3)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(1).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(1).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_2 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (3)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (3)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (3)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (3)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (3)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (3)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (3)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (3)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (3)(2).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (3)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(2).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(2).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_3 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (3)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (3)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (3)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (3)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (3)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (3)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (3)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (3)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (3)(3).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (3)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(3).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(3).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_R3L1_LINK_03_R3L1_0 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (3)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (3)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (3)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_03_R3L1_1 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (3)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (3)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (3)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_03_R3L1_2 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (3)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (3)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (3)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_03_R3L1_3 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (3)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (3)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (3)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (4)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (4)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (4)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (4)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (4)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (4)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (4)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (4)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (4)(0).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (4)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(0).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(0).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (4)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (4)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (4)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (4)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (4)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (4)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (4)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (4)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (4)(1).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (4)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(1).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(1).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (4)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (4)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (4)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (4)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (4)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (4)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (4)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (4)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (4)(2).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (4)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(2).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(2).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (4)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (4)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (4)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (4)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (4)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (4)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (4)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (4)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (4)(3).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (4)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(3).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(4)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(3).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(4)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(4)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(4)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(4)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_R3L1_LINK_04_R3L1_0 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (4)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (4)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (4)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_04_R3L1_1 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (4)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (4)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (4)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_04_R3L1_2 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (4)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (4)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (4)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_04_R3L1_3 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (4)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (4)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (4)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (5)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (5)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (5)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (5)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (5)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (5)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (5)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (5)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (5)(0).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (5)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(0).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(0).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (5)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (5)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (5)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (5)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (5)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (5)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (5)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (5)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (5)(1).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (5)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(1).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(1).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (5)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (5)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (5)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (5)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (5)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (5)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (5)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (5)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (5)(2).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (5)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(2).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(2).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (5)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (5)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (5)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (5)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (5)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (5)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (5)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (5)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (5)(3).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (5)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(3).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(5)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(3).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(5)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(5)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(5)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(5)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_R3L1_LINK_05_R3L1_0 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (5)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (5)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (5)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_05_R3L1_1 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (5)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (5)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (5)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_05_R3L1_2 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (5)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (5)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (5)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_05_R3L1_3 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (5)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (5)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (5)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (6)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (6)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (6)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (6)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (6)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (6)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (6)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (6)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (6)(0).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (6)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(0).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(0).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (6)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (6)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (6)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (6)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (6)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (6)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (6)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (6)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (6)(1).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (6)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(1).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(1).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (6)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (6)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (6)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (6)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (6)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (6)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (6)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (6)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (6)(2).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (6)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(2).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(2).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (6)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (6)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (6)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (6)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (6)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (6)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (6)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (6)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (6)(3).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (6)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(3).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(6)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(3).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(6)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(6)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(6)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(6)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_R3L1_LINK_06_R3L1_0 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (6)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (6)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (6)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_06_R3L1_1 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (6)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (6)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (6)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_06_R3L1_2 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (6)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (6)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (6)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_06_R3L1_3 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (6)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (6)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (6)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (7)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (7)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (7)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (7)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (7)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (7)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (7)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (7)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (7)(0).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (7)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(0).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(0).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (7)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (7)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (7)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (7)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (7)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (7)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (7)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (7)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (7)(1).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (7)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(1).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(1).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (7)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (7)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (7)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (7)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (7)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (7)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (7)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (7)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (7)(2).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (7)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(2).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(2).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (7)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (7)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (7)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (7)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (7)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (7)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (7)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (7)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (7)(3).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (7)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(3).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(7)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(3).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(7)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(7)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(7)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(7)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_R3L1_LINK_07_R3L1_0 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (7)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (7)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (7)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_07_R3L1_1 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (7)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (7)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (7)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_07_R3L1_2 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (7)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (7)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (7)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_07_R3L1_3 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (7)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (7)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (7)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (8)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (8)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (8)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (8)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (8)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (8)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (8)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (8)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (8)(0).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (8)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(0).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(0).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (8)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (8)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (8)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (8)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (8)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (8)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (8)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (8)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (8)(1).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (8)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(1).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(1).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (8)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (8)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (8)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (8)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (8)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (8)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (8)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (8)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (8)(2).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (8)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(2).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(2).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (8)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (8)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (8)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (8)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (8)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (8)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (8)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (8)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (8)(3).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (8)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(3).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(8)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(3).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(8)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(8)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(8)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(8)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_R3L1_LINK_08_R3L1_0 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (8)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (8)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (8)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_08_R3L1_1 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (8)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (8)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (8)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_08_R3L1_2 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (8)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (8)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (8)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_08_R3L1_3 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (8)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (8)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (8)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (9)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (9)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (9)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (9)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (9)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (9)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (9)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (9)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (9)(0).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (9)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(0).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(0).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (9)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (9)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (9)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (9)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (9)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (9)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (9)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (9)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (9)(1).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (9)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(1).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(1).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (9)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (9)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (9)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (9)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (9)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (9)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (9)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (9)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (9)(2).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (9)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(2).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(2).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (9)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (9)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (9)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (9)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (9)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (9)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (9)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (9)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (9)(3).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (9)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(3).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(9)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(3).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(9)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(9)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(9)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(9)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_R3L1_LINK_09_R3L1_0 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (9)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (9)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (9)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_09_R3L1_1 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (9)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (9)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (9)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_09_R3L1_2 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (9)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (9)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (9)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_09_R3L1_3 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (9)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (9)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (9)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (10)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (10)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (10)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (10)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (10)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (10)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (10)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (10)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (10)(0).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (10)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(0).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(0).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (10)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (10)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (10)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (10)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (10)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (10)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (10)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (10)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (10)(1).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (10)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(1).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(1).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (10)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (10)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (10)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (10)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (10)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (10)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (10)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (10)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (10)(2).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (10)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(2).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(2).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (10)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (10)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (10)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (10)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (10)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (10)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (10)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (10)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (10)(3).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (10)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(3).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(10)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(3).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(10)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(10)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(10)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(10)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_R3L1_LINK_10_R3L1_0 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (10)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (10)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (10)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_10_R3L1_1 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (10)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (10)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (10)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_10_R3L1_2 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (10)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (10)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (10)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_10_R3L1_3 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (10)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (10)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (10)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (11)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (11)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (11)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (11)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (11)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (11)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (11)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (11)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (11)(0).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (11)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(0).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(0).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (11)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (11)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (11)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (11)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (11)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (11)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (11)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (11)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (11)(1).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (11)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(1).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(1).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (11)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (11)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (11)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (11)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (11)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (11)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (11)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (11)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (11)(2).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (11)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(2).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(2).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (11)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
- register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (11)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (11)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
- register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (11)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (11)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (11)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (11)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (11)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
- register_read_data_25_s(1 downto 1) <= register_map_control_s.LCB_CTRL (11)(3).TRICKLE_TRIG_PULSE; -- writing to this register issues a single trickle trigger
- register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (11)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(3).WRITE_PTR; -- Trickle configuration memory write pointer
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(11)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(3).HCC_MASK; -- HCC* module mask
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(11)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(11)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(11)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(11)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- end if;
- when REG_CR_ITK_R3L1_LINK_11_R3L1_0 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (11)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (11)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (11)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_11_R3L1_1 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (11)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (11)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (11)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_11_R3L1_2 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (11)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (11)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (11)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_11_R3L1_3 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (11)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
- register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (11)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
- register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (11)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_MROD_CTRL =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(15 downto 4) <= register_map_control_s.MROD_CTRL.OPTIONS; -- Extra options for MROD
- register_read_data_25_s(3 downto 0) <= register_map_control_s.MROD_CTRL.GOLTESTMODE; -- GOL Test Mode (emulate CSM):
- -- 0: Run Data Emulator when 1; 0: stop, load emulator fifo
- -- 1: Enable Circulate when 1; 0: send fifo data only once
- -- 2: Enable Triggered Mode when 1; 0: run continueously (no TTC)
- -- 3: Enable pattern generator when 1; 0: off
-
- end if;
- when REG_MROD_EP0_CSMENABLE =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_CSMENABLE; -- EP0 CSM Data Enable channel 23-0
- end if;
- when REG_MROD_EP0_EMPTYSUPPR =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_EMPTYSUPPR; -- EP0 Set Empty Suppression channel 23-0
- end if;
- when REG_MROD_EP0_HPTDCMODE =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_HPTDCMODE; -- EP0 Set HPTDC Mode channel 23-0
- end if;
- when REG_MROD_EP0_CLRFIFOS =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_CLRFIFOS; -- EP0 Clear FIFOs channel 23-0
- end if;
- when REG_MROD_EP0_EMULOADENA =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_EMULOADENA; -- EP0 Emulator Load Enable channel 23-0
- end if;
- when REG_MROD_EP0_TRXLOOPBACK =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_TRXLOOPBACK; -- EP0 Transceiver Loopback Enable channel 23-0
- end if;
- when REG_MROD_EP0_TXCVRRESET =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_TXCVRRESET; -- EP0 Transceiver Reset all channel 23-0
- end if;
- when REG_MROD_EP0_RXRESET =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_RXRESET; -- EP0 Receiver Reset channel 23-0
- end if;
- when REG_MROD_EP0_TXRESET =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_TXRESET; -- EP0 Transmitter Reset channel 23-0
- end if;
- when REG_MROD_EP1_CSMENABLE =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_CSMENABLE; -- EP1 CSM Data Enable channel 23-0
- end if;
- when REG_MROD_EP1_EMPTYSUPPR =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_EMPTYSUPPR; -- EP1 Set Empty Suppression channel 23-0
- end if;
- when REG_MROD_EP1_HPTDCMODE =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_HPTDCMODE; -- EP1 Set HPTDC Mode channel 23-0
- end if;
- when REG_MROD_EP1_CLRFIFOS =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_CLRFIFOS; -- EP1 Clear FIFOs channel 23-0
- end if;
- when REG_MROD_EP1_EMULOADENA =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_EMULOADENA; -- EP1 Emulator Load Enable channel 23-0
- end if;
- when REG_MROD_EP1_TRXLOOPBACK =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_TRXLOOPBACK; -- EP1 Transceiver Loopback Enable channel 23-0
- end if;
- when REG_MROD_EP1_TXCVRRESET =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_TXCVRRESET; -- EP1 Transceiver Reset all channel 23-0
- end if;
- when REG_MROD_EP1_RXRESET =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_RXRESET; -- EP1 Receiver Reset channel 23-0
- end if;
- when REG_MROD_EP1_TXRESET =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_TXRESET; -- EP1 Transmitter Reset channel 23-0
- end if;
-
- --
- -- Monitor registers
- --
-
-
--- GenericBoardInformation
- when REG_REG_MAP_VERSION => register_read_data_25_s(15 downto 0) <= std_logic_vector(to_unsigned(1280,16)); -- Register Map Version, 5.0 formatted as 0x0500
- when REG_BOARD_ID_TIMESTAMP => register_read_data_25_s(39 downto 0) <= BUILD_DATETIME; -- Board ID Date / Time in BCD format YYMMDDhhmm
- when REG_GIT_COMMIT_TIME => register_read_data_25_s(39 downto 0) <= COMMIT_DATETIME; -- Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
- when REG_GIT_TAG => register_read_data_25_s(63 downto 0) <= GIT_TAG(63 downto 0); -- String containing the current GIT TAG
- when REG_GIT_COMMIT_NUMBER => register_read_data_25_s(31 downto 0) <= std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32)); -- Number of GIT commits after current GIT_TAG
- when REG_GIT_HASH => register_read_data_25_s(31 downto 0) <= GIT_HASH(159 downto 128); -- Short GIT hash (32 bit)
- when REG_GENERIC_CONSTANTS => register_read_data_25_s(15 downto 8) <= std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8)); -- Number of Interrupts
- register_read_data_25_s(7 downto 0) <= std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8)); -- Number of Descriptors
- when REG_NUM_OF_CHANNELS => register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS; -- Number of GBT or FULL mode Channels
- when REG_CARD_TYPE => register_read_data_25_s(63 downto 0) <= std_logic_vector(to_unsigned(CARD_TYPE,64)); -- Card Type:
- -- - 709 (0x2c5): FLX709, VC709
- -- - 710 (0x2c6): FLX710, HTG710
- -- - 711 (0x2c7): FLX711, BNL711
- -- - 712 (0x2c8): FLX712, BNL712
- -- - 128 (0x080): FLX128, VCU128
-
- when REG_GENERATE_GBT => register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.GENERATE_GBT; -- 1 when the GBT Wrapper is included in the design
- when REG_OPTO_TRX_NUM => register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_gen_board_info.OPTO_TRX_NUM; -- Number of optical transceivers in the design
- when REG_GENERATE_TTC_EMU => register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.GENERATE_TTC_EMU; -- 1 when TTC emulator is generated
- when REG_INCLUDE_EGROUP_0 => register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).FROMHOST_02; -- FromHost EPROC02 is included in this EGROUP
- register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).FROMHOST_04; -- FromHost EPROC04 is included in this EGROUP
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).FROMHOST_08; -- FromHost EPROC8 is included in this EGROUP
- register_read_data_25_s(5 downto 5) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).FROMHOST_HDLC; -- FromHost HDLC is included in this EGROUP
- register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).TOHOST_02; -- ToHost EPROC02 is included in this EGROUP
- register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).TOHOST_04; -- ToHost EPROC04 is included in this EGROUP
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).TOHOST_08; -- ToHost EPROC08 is included in this EGROUP
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).TOHOST_16; -- ToHost EPROC16 is included in this EGROUP
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).TOHOST_HDLC; -- ToHost HDLC is included in this EGROUP
- when REG_INCLUDE_EGROUP_1 => register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).FROMHOST_02; -- FromHost EPROC02 is included in this EGROUP
- register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).FROMHOST_04; -- FromHost EPROC04 is included in this EGROUP
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).FROMHOST_08; -- FromHost EPROC8 is included in this EGROUP
- register_read_data_25_s(5 downto 5) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).FROMHOST_HDLC; -- FromHost HDLC is included in this EGROUP
- register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).TOHOST_02; -- ToHost EPROC02 is included in this EGROUP
- register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).TOHOST_04; -- ToHost EPROC04 is included in this EGROUP
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).TOHOST_08; -- ToHost EPROC08 is included in this EGROUP
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).TOHOST_16; -- ToHost EPROC16 is included in this EGROUP
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).TOHOST_HDLC; -- ToHost HDLC is included in this EGROUP
- when REG_INCLUDE_EGROUP_2 => register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).FROMHOST_02; -- FromHost EPROC02 is included in this EGROUP
- register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).FROMHOST_04; -- FromHost EPROC04 is included in this EGROUP
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).FROMHOST_08; -- FromHost EPROC8 is included in this EGROUP
- register_read_data_25_s(5 downto 5) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).FROMHOST_HDLC; -- FromHost HDLC is included in this EGROUP
- register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).TOHOST_02; -- ToHost EPROC02 is included in this EGROUP
- register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).TOHOST_04; -- ToHost EPROC04 is included in this EGROUP
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).TOHOST_08; -- ToHost EPROC08 is included in this EGROUP
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).TOHOST_16; -- ToHost EPROC16 is included in this EGROUP
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).TOHOST_HDLC; -- ToHost HDLC is included in this EGROUP
- when REG_INCLUDE_EGROUP_3 => register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).FROMHOST_02; -- FromHost EPROC02 is included in this EGROUP
- register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).FROMHOST_04; -- FromHost EPROC04 is included in this EGROUP
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).FROMHOST_08; -- FromHost EPROC8 is included in this EGROUP
- register_read_data_25_s(5 downto 5) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).FROMHOST_HDLC; -- FromHost HDLC is included in this EGROUP
- register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).TOHOST_02; -- ToHost EPROC02 is included in this EGROUP
- register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).TOHOST_04; -- ToHost EPROC04 is included in this EGROUP
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).TOHOST_08; -- ToHost EPROC08 is included in this EGROUP
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).TOHOST_16; -- ToHost EPROC16 is included in this EGROUP
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).TOHOST_HDLC; -- ToHost HDLC is included in this EGROUP
- when REG_INCLUDE_EGROUP_4 => register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).FROMHOST_02; -- FromHost EPROC02 is included in this EGROUP
- register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).FROMHOST_04; -- FromHost EPROC04 is included in this EGROUP
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).FROMHOST_08; -- FromHost EPROC8 is included in this EGROUP
- register_read_data_25_s(5 downto 5) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).FROMHOST_HDLC; -- FromHost HDLC is included in this EGROUP
- register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).TOHOST_02; -- ToHost EPROC02 is included in this EGROUP
- register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).TOHOST_04; -- ToHost EPROC04 is included in this EGROUP
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).TOHOST_08; -- ToHost EPROC08 is included in this EGROUP
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).TOHOST_16; -- ToHost EPROC16 is included in this EGROUP
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).TOHOST_HDLC; -- ToHost HDLC is included in this EGROUP
- when REG_INCLUDE_EGROUP_5 => register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).FROMHOST_02; -- FromHost EPROC02 is included in this EGROUP
- register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).FROMHOST_04; -- FromHost EPROC04 is included in this EGROUP
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).FROMHOST_08; -- FromHost EPROC8 is included in this EGROUP
- register_read_data_25_s(5 downto 5) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).FROMHOST_HDLC; -- FromHost HDLC is included in this EGROUP
- register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).TOHOST_02; -- ToHost EPROC02 is included in this EGROUP
- register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).TOHOST_04; -- ToHost EPROC04 is included in this EGROUP
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).TOHOST_08; -- ToHost EPROC08 is included in this EGROUP
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).TOHOST_16; -- ToHost EPROC16 is included in this EGROUP
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).TOHOST_HDLC; -- ToHost HDLC is included in this EGROUP
- when REG_INCLUDE_EGROUP_6 => register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).FROMHOST_02; -- FromHost EPROC02 is included in this EGROUP
- register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).FROMHOST_04; -- FromHost EPROC04 is included in this EGROUP
- register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).FROMHOST_08; -- FromHost EPROC8 is included in this EGROUP
- register_read_data_25_s(5 downto 5) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).FROMHOST_HDLC; -- FromHost HDLC is included in this EGROUP
- register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).TOHOST_02; -- ToHost EPROC02 is included in this EGROUP
- register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).TOHOST_04; -- ToHost EPROC04 is included in this EGROUP
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).TOHOST_08; -- ToHost EPROC08 is included in this EGROUP
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).TOHOST_16; -- ToHost EPROC16 is included in this EGROUP
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).TOHOST_HDLC; -- ToHost HDLC is included in this EGROUP
- when REG_WIDE_MODE => register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.WIDE_MODE; -- GBT is configured in Wide mode
- when REG_FIRMWARE_MODE => register_read_data_25_s(3 downto 0) <= register_map_monitor_s.register_map_gen_board_info.FIRMWARE_MODE; -- 0: GBT mode
- -- 1: FULL mode
- -- 2: LTDB mode (GBT mode with only IC and TTC links)
- -- 3: FEI4 mode
- -- 4: ITK Pixel
- -- 5: ITK Strip
- -- 6: FELIG
- -- 7: FULL mode emulator
- -- 8: FELIX_MROD mode
- -- 9: lpGBT mode
- --
-
- when REG_GTREFCLK_SOURCE => register_read_data_25_s(1 downto 0) <= register_map_monitor_s.register_map_gen_board_info.GTREFCLK_SOURCE; -- 0: Transceiver reference Clock source from Si5345
- -- 1: Transceiver reference Clock source from Si5324
- -- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- when REG_CR_GENERICS => register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.CR_GENERICS.XOFF_INCLUDED; -- Xoff bits (usually full mode) can be generated by the FromHost Central Router
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.CR_GENERICS.DIRECT_MODE_INCLUDED; -- Indicates that the Direct mode functionality was built in the Central Router
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.CR_GENERICS.FROM_HOST_INCLUDED; -- Indicates that the From Host path of the Central router was included in the design
- when REG_BLOCKSIZE => register_read_data_25_s(15 downto 0) <= register_map_monitor_s.register_map_gen_board_info.BLOCKSIZE; -- Number of bytes in a block
- when REG_PCIE_ENDPOINT => register_read_data_25_s(0 downto 0) <= std_logic_vector(to_unsigned(PCIE_ENDPOINT, 1)); -- Indicator of the PCIe endpoint on BNL71x cards with two endpoints. 0 or 1
- when REG_CHUNK_TRAILER_32B => register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.CHUNK_TRAILER_32B; -- Indicator that the chunk trailer is in the new 32-bit format
- when REG_PCIE_ENDPOINTS => register_read_data_25_s(1 downto 0) <= register_map_monitor_s.register_map_gen_board_info.PCIE_ENDPOINTS; -- Number of PCIe endpoints on the card. The BNL71x cards have 2 endpoints
- when REG_SUPERCHUNK_FACTOR => register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_gen_board_info.SUPERCHUNK_FACTOR; -- Number of full mode chunks glued together as one chunk
-
--- CRToHostControlsAndMonitors
- when REG_MAX_TIMEOUT => register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_crtohost_monitor.MAX_TIMEOUT; -- Maximum allowed timeout value
-
--- CRFromHostControlsAndMonitors
-
--- DecodingControlsAndMonitors
- when REG_DECODING_LINK_ALIGNED_00 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (0); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_01 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (1); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_02 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (2); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_03 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (3); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_04 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (4); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_05 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (5); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_06 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (6); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_07 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (7); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_08 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (8); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_09 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (9); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_10 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (10); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_11 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (11); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_12 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (12); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_13 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (13); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_14 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (14); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_15 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (15); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_16 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (16); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_17 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (17); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_18 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (18); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_19 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (19); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_20 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (20); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_21 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (21); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_22 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (22); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_DECODING_LINK_ALIGNED_23 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (23); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- when REG_RD53B_PROCESSOR_00 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (0).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (0).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (0).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (0).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_01 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (1).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (1).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (1).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (1).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_02 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (2).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (2).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (2).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (2).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_03 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (3).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (3).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (3).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (3).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_04 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (4).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (4).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (4).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (4).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_05 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (5).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (5).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (5).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (5).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_06 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (6).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (6).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (6).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (6).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_07 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (7).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (7).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (7).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (7).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_08 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (8).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (8).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (8).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (8).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_09 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (9).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (9).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (9).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (9).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_10 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (10).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (10).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (10).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (10).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_11 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (11).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (11).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (11).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (11).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_12 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (12).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (12).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (12).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (12).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_13 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (13).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (13).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (13).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (13).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_14 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (14).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (14).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (14).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (14).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_15 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (15).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (15).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (15).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (15).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_16 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (16).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (16).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (16).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (16).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_17 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (17).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (17).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (17).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (17).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_18 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (18).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (18).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (18).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (18).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_19 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (19).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (19).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (19).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (19).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_20 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (20).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (20).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (20).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (20).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_21 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (21).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (21).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (21).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (21).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_22 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (22).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (22).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (22).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (22).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_23 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (23).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (23).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (23).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (23).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_24 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (24).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (24).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (24).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (24).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_25 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (25).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (25).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (25).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (25).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_26 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (26).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (26).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (26).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (26).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_27 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (27).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (27).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (27).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (27).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_28 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (28).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (28).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (28).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (28).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_29 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (29).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (29).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (29).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (29).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_30 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (30).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (30).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (30).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (30).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_31 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (31).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (31).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (31).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (31).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_32 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (32).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (32).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (32).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (32).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_33 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (33).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (33).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (33).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (33).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_34 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (34).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (34).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (34).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (34).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_35 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (35).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (35).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (35).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (35).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_36 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (36).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (36).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (36).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (36).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_37 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (37).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (37).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (37).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (37).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_38 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (38).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (38).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (38).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (38).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_39 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (39).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (39).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (39).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (39).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_40 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (40).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (40).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (40).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (40).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_41 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (41).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (41).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (41).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (41).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_42 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (42).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (42).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (42).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (42).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_43 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (43).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (43).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (43).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (43).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_44 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (44).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (44).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (44).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (44).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_45 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (45).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (45).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (45).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (45).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_46 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (46).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (46).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (46).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (46).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_47 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (47).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (47).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (47).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (47).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_48 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (48).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (48).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (48).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (48).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_49 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (49).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (49).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (49).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (49).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_50 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (50).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (50).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (50).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (50).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_51 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (51).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (51).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (51).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (51).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_52 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (52).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (52).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (52).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (52).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_53 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (53).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (53).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (53).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (53).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_54 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (54).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (54).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (54).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (54).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_55 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (55).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (55).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (55).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (55).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_56 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (56).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (56).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (56).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (56).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_57 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (57).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (57).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (57).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (57).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_58 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (58).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (58).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (58).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (58).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_59 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (59).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (59).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (59).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (59).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_60 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (60).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (60).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (60).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (60).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_61 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (61).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (61).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (61).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (61).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_62 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (62).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (62).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (62).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (62).DROP_TOT; -- Decoding block
- when REG_RD53B_PROCESSOR_63 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (63).ENABLE_MULTICHIP; -- Decoding block
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (63).ENABLE_BINARYTREE; -- Decoding block
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (63).ENABLE_TOT; -- Decoding block
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (63).DROP_TOT; -- Decoding block
-
--- EncodingControlsAndMonitors
-
--- FrontendEmulatorControlsAndMonitors
-
--- LinkWrapperMonitors
- when REG_GBT_VERSION => register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_link_monitor.GBT_VERSION.DATE; -- Date
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_link_monitor.GBT_VERSION.GBT_VERSION; -- GBT Version
- register_read_data_25_s(31 downto 16) <= register_map_monitor_s.register_map_link_monitor.GBT_VERSION.GTH_IP_VERSION; -- GTH IP Version
- register_read_data_25_s(15 downto 3) <= register_map_monitor_s.register_map_link_monitor.GBT_VERSION.RESERVED; -- Reserved
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_link_monitor.GBT_VERSION.GTHREFCLK_SEL; -- GTHREFCLK SEL
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_link_monitor.GBT_VERSION.RX_CLK_SEL; -- RX CLK SEL
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_VERSION.PLL_SEL; -- PLL SEL
- when REG_GBT_TXRESET_DONE => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_TXRESET_DONE; -- TX Reset done [47:0]
- when REG_GBT_RXRESET_DONE => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_RXRESET_DONE; -- RX Reset done [47:0]
- when REG_GBT_TXFSMRESET_DONE => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_TXFSMRESET_DONE; -- TX FSM Reset done [47:0]
- when REG_GBT_RXFSMRESET_DONE => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_RXFSMRESET_DONE; -- RX FSM Reset done [47:0]
- when REG_GBT_CPLL_FBCLK_LOST => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_CPLL_FBCLK_LOST; -- CPLL FBCLK LOST [47:0]
- when REG_GBT_PLL_LOCK => register_read_data_25_s(59 downto 48) <= register_map_monitor_s.register_map_link_monitor.GBT_PLL_LOCK.QPLL_LOCK; -- QPLL LOCK [11:0]
- register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_PLL_LOCK.CPLL_LOCK; -- CPLL LOCK [47:0]
- when REG_GBT_RXCDR_LOCK => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_RXCDR_LOCK; -- RX CDR LOCK [47:0]
- when REG_GBT_CLK_SAMPLED => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_CLK_SAMPLED; -- clk sampled [47:0]
- when REG_GBT_RX_IS_HEADER =>
- if GBT_GENERATE_ALL_REGS then
- register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_RX_IS_HEADER; -- RX IS HEADER [47:0]
- end if;
- when REG_GBT_RX_IS_DATA =>
- if GBT_GENERATE_ALL_REGS then
- register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_RX_IS_DATA; -- RX IS DATA [47:0]
- end if;
- when REG_GBT_RX_HEADER_FOUND =>
- if GBT_GENERATE_ALL_REGS then
- register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_RX_HEADER_FOUND; -- RX HEADER FOUND [47:0]
- end if;
- when REG_GBT_ALIGNMENT_DONE => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_ALIGNMENT_DONE; -- RX ALIGNMENT DONE [47:0]
- when REG_GBT_OUT_MUX_STATUS => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_OUT_MUX_STATUS; -- GBT output mux status [47:0]
- when REG_GBT_ERROR => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_ERROR; -- Error flags [47:0]
- when REG_GBT_GBT_TOPBOT_C =>
- if GBT_GENERATE_ALL_REGS then
- register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_GBT_TOPBOT_C; -- TopBot_c [47:0]
- end if;
- when REG_GBT_FM_RX_DISP_ERROR1 => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_FM_RX_DISP_ERROR1; -- Rx disparity error [47:0]
- when REG_GBT_FM_RX_DISP_ERROR2 => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_FM_RX_DISP_ERROR2; -- Rx disparity error [96:48]
- when REG_GBT_FM_RX_NOTINTABLE1 => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_FM_RX_NOTINTABLE1; -- Rx not in table [47:0]
- when REG_GBT_FM_RX_NOTINTABLE2 => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_FM_RX_NOTINTABLE2; -- Rx not in table [96:48]
-
--- TTCBUSYControlsAndMonitors
- when REG_TTC_DEC_MON => register_read_data_25_s(15 downto 5) <= register_map_monitor_s.register_map_ttc_monitor.TTC_DEC_MON.TH_FF_COUNT; -- ToHostData Fifo counts
- register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_ttc_monitor.TTC_DEC_MON.TH_FF_FULL; -- ToHostData Fifo status 1:full 0:not full
- register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_ttc_monitor.TTC_DEC_MON.TH_FF_EMPTY; -- ToHostData Fifo status 1:empty 0:not empty
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_DEC_MON.TTC_BIT_ERR; -- double bit, single bit and comm error in TTC data
- when REG_TTC_BUSY_ACCEPTED00 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (0); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED01 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (1); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED02 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (2); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED03 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (3); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED04 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (4); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED05 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (5); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED06 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (6); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED07 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (7); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED08 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (8); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED09 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (9); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED10 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (10); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED11 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (11); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED12 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (12); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED13 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (13); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED14 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (14); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED15 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (15); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED16 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (16); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED17 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (17); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED18 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (18); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED19 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (19); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED20 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (20); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED21 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (21); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED22 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (22); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_BUSY_ACCEPTED23 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (23); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- when REG_TTC_L1ID_MONITOR => register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_L1ID_MONITOR; -- Monitor L1ID and XL1ID.
-
--- XOFF_BUSYControlsAndMonitors
- when REG_XOFF_FM_LOW_THRESH_CROSSED => register_read_data_25_s(23 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_FM_LOW_THRESH_CROSSED; -- FIFO filled beyond the low threshold, 1 bit per channel
- when REG_XOFF_PEAK_DURATION00 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (0); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION00 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (0); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT00 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (0); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION01 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (1); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION01 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (1); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT01 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (1); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION02 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (2); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION02 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (2); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT02 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (2); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION03 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (3); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION03 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (3); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT03 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (3); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION04 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (4); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION04 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (4); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT04 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (4); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION05 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (5); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION05 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (5); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT05 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (5); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION06 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (6); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION06 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (6); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT06 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (6); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION07 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (7); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION07 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (7); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT07 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (7); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION08 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (8); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION08 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (8); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT08 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (8); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION09 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (9); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION09 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (9); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT09 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (9); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION10 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (10); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION10 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (10); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT10 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (10); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION11 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (11); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION11 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (11); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT11 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (11); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION12 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (12); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION12 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (12); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT12 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (12); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION13 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (13); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION13 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (13); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT13 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (13); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION14 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (14); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION14 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (14); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT14 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (14); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION15 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (15); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION15 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (15); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT15 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (15); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION16 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (16); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION16 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (16); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT16 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (16); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION17 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (17); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION17 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (17); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT17 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (17); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION18 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (18); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION18 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (18); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT18 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (18); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION19 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (19); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION19 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (19); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT19 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (19); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION20 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (20); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION20 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (20); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT20 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (20); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION21 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (21); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION21 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (21); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT21 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (21); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION22 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (22); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION22 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (22); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT22 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (22); -- Total number of XOFF events per channel that occurred since a reset.
- when REG_XOFF_PEAK_DURATION23 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (23); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- when REG_XOFF_TOTAL_DURATION23 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (23); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- when REG_XOFF_COUNT23 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (23); -- Total number of XOFF events per channel that occurred since a reset.
-
--- HouseKeepingControlsAndMonitors
- when REG_LMK_LOCKED => register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_hk_monitor.LMK_LOCKED; -- LMK Chip on BNL-711 locked
- when REG_FPGA_CORE_TEMP => register_read_data_25_s(11 downto 0) <= register_map_monitor_s.register_map_hk_monitor.FPGA_CORE_TEMP; -- XADC temperature monitor for the FPGA CORE
- -- for FLX709, FLX710
- -- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- -- for FLX711
- -- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
-
- when REG_FPGA_CORE_VCCINT => register_read_data_25_s(11 downto 0) <= register_map_monitor_s.register_map_hk_monitor.FPGA_CORE_VCCINT; -- XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- when REG_FPGA_CORE_VCCAUX => register_read_data_25_s(11 downto 0) <= register_map_monitor_s.register_map_hk_monitor.FPGA_CORE_VCCAUX; -- XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- when REG_FPGA_CORE_VCCBRAM => register_read_data_25_s(11 downto 0) <= register_map_monitor_s.register_map_hk_monitor.FPGA_CORE_VCCBRAM; -- XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
- when REG_FPGA_DNA => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_hk_monitor.FPGA_DNA; -- Unique identifier of the FPGA
- when REG_CONFIG_FLASH_RD => register_read_data_25_s(19 downto 18) <= register_map_monitor_s.register_map_hk_monitor.CONFIG_FLASH_RD.PAR_RD; -- Show which Flash partition is selected.
- register_read_data_25_s(17 downto 17) <= register_map_monitor_s.register_map_hk_monitor.CONFIG_FLASH_RD.FLASH_REQ_DONE; -- Request done
- register_read_data_25_s(16 downto 16) <= register_map_monitor_s.register_map_hk_monitor.CONFIG_FLASH_RD.FLASH_BUSY; -- Flash operation busy
- register_read_data_25_s(15 downto 0) <= register_map_monitor_s.register_map_hk_monitor.CONFIG_FLASH_RD.READ_DATA; -- Value of data read from flash
- when REG_SI5324_STATUS => register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_hk_monitor.SI5324_STATUS.LOL; -- Loss of Lock Si5324
- register_read_data_25_s(8 downto 0) <= register_map_monitor_s.register_map_hk_monitor.SI5324_STATUS.LOS; -- Loss of Signal Si5324
- when REG_TACH_CNT => register_read_data_25_s(19 downto 0) <= register_map_monitor_s.register_map_hk_monitor.TACH_CNT; -- Readout of the Fan tachometer speed of the BNL712 board
-
--- Generators
- when REG_FELIG_MON_TTC_0_00 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (0).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (0).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (0).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (0).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (0).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (0).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_01 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (1).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (1).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (1).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (1).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (1).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (1).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_02 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (2).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (2).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (2).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (2).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (2).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (2).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_03 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (3).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (3).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (3).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (3).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (3).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (3).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_04 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (4).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (4).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (4).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (4).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (4).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (4).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_05 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (5).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (5).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (5).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (5).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (5).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (5).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_06 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (6).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (6).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (6).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (6).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (6).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (6).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_07 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (7).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (7).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (7).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (7).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (7).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (7).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_08 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (8).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (8).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (8).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (8).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (8).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (8).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_09 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (9).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (9).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (9).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (9).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (9).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (9).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_10 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (10).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (10).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (10).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (10).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (10).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (10).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_11 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (11).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (11).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (11).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (11).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (11).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (11).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_12 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (12).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (12).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (12).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (12).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (12).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (12).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_13 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (13).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (13).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (13).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (13).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (13).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (13).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_14 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (14).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (14).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (14).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (14).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (14).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (14).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_15 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (15).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (15).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (15).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (15).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (15).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (15).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_16 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (16).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (16).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (16).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (16).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (16).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (16).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_17 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (17).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (17).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (17).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (17).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (17).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (17).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_18 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (18).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (18).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (18).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (18).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (18).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (18).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_19 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (19).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (19).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (19).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (19).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (19).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (19).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_20 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (20).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (20).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (20).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (20).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (20).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (20).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_21 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (21).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (21).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (21).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (21).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (21).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (21).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_22 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (22).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (22).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (22).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (22).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (22).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (22).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_0_23 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (23).L1ID; -- Live TTC data monitor.
- register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (23).XL1ID; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (23).BCID; -- Live TTC data monitor.
- register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (23).RESERVED0; -- Live TTC data monitor.
- register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (23).LEN; -- Live TTC data monitor.
- register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (23).FMT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_00 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (0).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (0).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (0).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_01 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (1).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (1).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (1).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_02 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (2).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (2).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (2).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_03 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (3).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (3).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (3).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_04 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (4).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (4).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (4).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_05 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (5).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (5).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (5).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_06 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (6).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (6).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (6).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_07 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (7).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (7).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (7).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_08 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (8).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (8).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (8).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_09 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (9).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (9).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (9).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_10 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (10).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (10).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (10).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_11 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (11).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (11).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (11).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_12 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (12).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (12).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (12).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_13 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (13).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (13).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (13).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_14 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (14).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (14).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (14).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_15 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (15).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (15).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (15).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_16 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (16).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (16).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (16).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_17 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (17).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (17).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (17).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_18 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (18).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (18).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (18).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_19 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (19).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (19).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (19).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_20 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (20).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (20).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (20).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_21 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (21).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (21).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (21).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_22 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (22).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (22).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (22).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_TTC_1_23 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (23).RESERVED1; -- Live TTC data monitor.
- register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (23).TRIGGER_TYPE; -- Live TTC data monitor.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (23).ORBIT; -- Live TTC data monitor.
- end if;
- when REG_FELIG_MON_COUNTERS_00 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (0).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (0).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_01 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (1).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (1).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_02 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (2).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (2).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_03 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (3).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (3).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_04 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (4).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (4).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_05 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (5).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (5).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_06 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (6).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (6).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_07 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (7).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (7).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_08 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (8).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (8).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_09 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (9).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (9).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_10 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (10).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (10).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_11 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (11).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (11).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_12 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (12).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (12).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_13 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (13).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (13).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_14 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (14).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (14).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_15 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (15).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (15).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_16 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (16).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (16).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_17 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (17).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (17).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_18 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (18).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (18).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_19 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (19).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (19).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_20 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (20).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (20).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_21 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (21).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (21).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_22 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (22).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (22).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_COUNTERS_23 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (23).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (23).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
- end if;
- when REG_FELIG_MON_FREQ_00 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (0).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (0).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_01 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (1).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (1).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_02 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (2).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (2).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_03 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (3).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (3).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_04 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (4).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (4).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_05 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (5).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (5).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_06 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (6).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (6).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_07 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (7).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (7).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_08 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (8).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (8).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_09 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (9).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (9).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_10 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (10).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (10).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_11 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (11).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (11).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_12 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (12).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (12).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_13 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (13).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (13).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_14 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (14).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (14).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_15 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (15).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (15).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_16 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (16).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (16).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_17 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (17).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (17).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_18 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (18).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (18).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_19 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (19).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (19).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_20 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (20).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (20).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_21 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (21).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (21).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_22 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (22).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (22).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_FREQ_23 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (23).TX; -- FELIG regenerated TX clock frequency[Hz].
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (23).RX; -- FELIG recovered RX clock frequency[Hz].
- end if;
- when REG_FELIG_MON_L1A_ID_00 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (0); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_01 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (1); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_02 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (2); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_03 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (3); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_04 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (4); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_05 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (5); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_06 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (6); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_07 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (7); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_08 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (8); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_09 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (9); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_10 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (10); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_11 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (11); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_12 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (12); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_13 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (13); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_14 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (14); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_15 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (15); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_16 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (16); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_17 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (17); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_18 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (18); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_19 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (19); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_20 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (20); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_21 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (21); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_22 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (22); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_L1A_ID_23 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (23); -- FELIG's last L1 ID.
- end if;
- when REG_FELIG_MON_PICXO_00 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (0).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (0).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_01 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (1).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (1).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_02 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (2).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (2).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_03 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (3).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (3).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_04 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (4).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (4).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_05 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (5).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (5).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_06 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (6).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (6).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_07 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (7).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (7).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_08 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (8).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (8).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_09 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (9).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (9).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_10 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (10).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (10).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_11 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (11).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (11).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_12 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (12).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (12).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_13 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (13).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (13).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_14 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (14).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (14).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_15 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (15).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (15).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_16 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (16).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (16).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_17 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (17).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (17).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_18 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (18).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (18).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_19 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (19).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (19).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_20 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (20).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (20).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_21 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (21).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (21).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_22 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (22).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (22).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_PICXO_23 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (23).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (23).ERROR; -- Value indicates RX to TX frequency tracking error.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_00 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (0); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_01 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (1); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_02 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (2); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_03 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (3); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_04 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (4); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_05 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (5); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_06 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (6); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_07 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (7); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_08 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (8); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_09 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (9); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_10 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (10); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_11 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (11); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_12 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (12); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_13 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (13); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_14 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (14); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_15 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (15); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_16 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (16); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_17 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (17); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_18 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (18); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_19 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (19); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_20 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (20); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_21 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (21); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_22 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (22); -- data fifo status 2:write done 1:full 0:empty.
- end if;
- when REG_FELIG_MON_ITK_STRIPS_23 =>
- if EMU_GENERATE_REGS then
- register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (23); -- data fifo status 2:write done 1:full 0:empty.
- end if;
-
--- Wishbone
- when REG_WISHBONE_STATUS => register_read_data_25_s(4 downto 4) <= register_map_monitor_s.wishbone_monitor.WISHBONE_STATUS.INT; -- interrupt
- register_read_data_25_s(3 downto 3) <= register_map_monitor_s.wishbone_monitor.WISHBONE_STATUS.RETRY; -- Interface is not ready to accept data cycle should be retried
- register_read_data_25_s(2 downto 2) <= register_map_monitor_s.wishbone_monitor.WISHBONE_STATUS.STALL; -- When pipelined mode slave can't accept additional transactions in its queue
- register_read_data_25_s(1 downto 1) <= register_map_monitor_s.wishbone_monitor.WISHBONE_STATUS.ACKNOWLEDGE; -- Indicates the termination of a normal bus cycle
- register_read_data_25_s(0 downto 0) <= register_map_monitor_s.wishbone_monitor.WISHBONE_STATUS.ERROR; -- Address not mapped by the crossbar
-
--- MRODmonitors
- when REG_MROD_EP0_CSMH_EMPTY =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_CSMH_EMPTY; -- CSM Handler FIFO Empty 23-0
- end if;
- when REG_MROD_EP0_CSMH_FULL =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_CSMH_FULL; -- CSM Handler FIFO Full 23-0
- end if;
- when REG_MROD_EP0_RXLOCKED =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_RXLOCKED; -- EP0 Receiver Locked monitor 23-0
- end if;
- when REG_MROD_EP0_TXLOCKED =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_TXLOCKED; -- EP0 Transmitter Locked monitor 23-0
- end if;
- when REG_MROD_EP1_CSMH_EMPTY =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_CSMH_EMPTY; -- CSM Handler FIFO Empty 23-0
- end if;
- when REG_MROD_EP1_CSMH_FULL =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_CSMH_FULL; -- CSM Handler FIFO Full 23-0
- end if;
- when REG_MROD_EP1_RXLOCKED =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_RXLOCKED; -- EP1 Receiver Locked monitor 23-0
- end if;
- when REG_MROD_EP1_TXLOCKED =>
- if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_TXLOCKED; -- EP1 Transmitter Locked monitor 23-0
- end if;
- -----------------------------------
- ---- GENERATED code END #3 ## ----
- -----------------------------------
- when others => register_read_data_25_s <= (others => '0');
- end case;
- else --None of BAR0, BAR1 or BAR2 selected
- register_read_data_25_s <= (others => '0');
- end if;
- end if;
-
- register_write_done_25_s <= '0';
- if(register_write_enable_25_s = '1') then
- --! Apply byte enable and word enable to Register writes
- register_write_data_25_v := register_read_data_25_s;
-
- case (register_word_address_25_s(3 downto 2)) is
- when "00" =>
- case (dword_count_25_s(2 downto 0)) is --write 1 or 2 dwords
- when "001" =>
- for i in 0 to 3 loop
- if first_be_25_s(i) = '1' then
- register_write_data_25_v(7+i*8 downto i*8) := register_write_data_25_nobe_s(7+i*8 downto i*8);
- end if;
- end loop;
- when "010" =>
- for i in 0 to 3 loop
- if first_be_25_s(i) = '1' then
- register_write_data_25_v(7+i*8 downto i*8) := register_write_data_25_nobe_s(7+i*8 downto i*8);
- end if;
- end loop;
- for i in 0 to 3 loop
- if last_be_25_s(i) = '1' then
- register_write_data_25_v(39+i*8 downto 32+i*8) := register_write_data_25_nobe_s(39+i*8 downto 32+i*8);
- end if;
- end loop;
- when others => NULL;
- end case;
- when "01" =>
- for i in 0 to 3 loop
- if first_be_25_s(i) = '1' then
- register_write_data_25_v(39+i*8 downto 32+i*8) := register_write_data_25_nobe_s(7+i*8 downto i*8);
- end if;
- end loop;
- when "10" =>
- case (dword_count_25_s(2 downto 0)) is --write 1 or 2 dwords
- when "001" =>
- for i in 0 to 3 loop
- if first_be_25_s(i) = '1' then
- register_write_data_25_v(71+i*8 downto 64+i*8) := register_write_data_25_nobe_s(7+i*8 downto i*8);
- end if;
- end loop;
- when "010" =>
- for i in 0 to 3 loop
- if first_be_25_s(i) = '1' then
- register_write_data_25_v(71+i*8 downto 64+i*8) := register_write_data_25_nobe_s(7+i*8 downto i*8);
- end if;
- end loop;
- for i in 0 to 3 loop
- if last_be_25_s(i) = '1' then
- register_write_data_25_v(103+i*8 downto 96+i*8) := register_write_data_25_nobe_s(39+i*8 downto 32+i*8);
- end if;
- end loop;
- when others => NULL;
- end case;
- when "11" =>
- for i in 0 to 3 loop
- if first_be_25_s(i) = '1' then
- register_write_data_25_v(103+i*8 downto 96+i*8) := register_write_data_25_nobe_s(7+i*8 downto i*8);
- end if;
- end loop;
- when others => NULL;
- end case;
-
- --! End byte enable / word enable
-
-
- register_write_done_25_s <= '1';
- --Write registers in BAR0
- if(bar_id_25_s = "000") then
- register_write_address_v := register_write_address_25_s(19 downto 4)&"0000";
- case(register_write_address_v) is
- when REG_DESCRIPTOR_0 => dma_descriptors_25_w_s( 0).end_address <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 0).start_address <= register_write_data_25_v(63 downto 0);
- when REG_DESCRIPTOR_0a => dma_descriptors_25_w_s( 0).pc_pointer <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 0).wrap_around <= register_write_data_25_v(12);
- --dma_descriptors_25_w_s( 0).read_not_write <= register_write_data_25_v(11);
- dma_descriptors_25_w_s( 0).dword_count <= register_write_data_25_v(10 downto 0);
- when REG_DESCRIPTOR_1 => dma_descriptors_25_w_s( 1).end_address <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 1).start_address <= register_write_data_25_v(63 downto 0);
- when REG_DESCRIPTOR_1a => dma_descriptors_25_w_s( 1).pc_pointer <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 1).wrap_around <= register_write_data_25_v(12);
- --dma_descriptors_25_w_s( 1).read_not_write <= register_write_data_25_v(11);
- dma_descriptors_25_w_s( 1).dword_count <= register_write_data_25_v(10 downto 0);
- when REG_DESCRIPTOR_2 => dma_descriptors_25_w_s( 2).end_address <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 2).start_address <= register_write_data_25_v(63 downto 0);
- when REG_DESCRIPTOR_2a => dma_descriptors_25_w_s( 2).pc_pointer <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 2).wrap_around <= register_write_data_25_v(12);
- --dma_descriptors_25_w_s( 2).read_not_write <= register_write_data_25_v(11);
- dma_descriptors_25_w_s( 2).dword_count <= register_write_data_25_v(10 downto 0);
- when REG_DESCRIPTOR_3 => dma_descriptors_25_w_s( 3).end_address <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 3).start_address <= register_write_data_25_v(63 downto 0);
- when REG_DESCRIPTOR_3a => dma_descriptors_25_w_s( 3).pc_pointer <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 3).wrap_around <= register_write_data_25_v(12);
- --dma_descriptors_25_w_s( 3).read_not_write <= register_write_data_25_v(11);
- dma_descriptors_25_w_s( 3).dword_count <= register_write_data_25_v(10 downto 0);
- when REG_DESCRIPTOR_4 => dma_descriptors_25_w_s( 4).end_address <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 4).start_address <= register_write_data_25_v(63 downto 0);
- when REG_DESCRIPTOR_4a => dma_descriptors_25_w_s( 4).pc_pointer <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 4).wrap_around <= register_write_data_25_v(12);
- --dma_descriptors_25_w_s( 4).read_not_write <= register_write_data_25_v(11);
- dma_descriptors_25_w_s( 4).dword_count <= register_write_data_25_v(10 downto 0);
- when REG_DESCRIPTOR_5 => dma_descriptors_25_w_s( 5).end_address <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 5).start_address <= register_write_data_25_v(63 downto 0);
- when REG_DESCRIPTOR_5a => dma_descriptors_25_w_s( 5).pc_pointer <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 5).wrap_around <= register_write_data_25_v(12);
- --dma_descriptors_25_w_s( 5).read_not_write <= register_write_data_25_v(11);
- dma_descriptors_25_w_s( 5).dword_count <= register_write_data_25_v(10 downto 0);
- when REG_DESCRIPTOR_6 => dma_descriptors_25_w_s( 6).end_address <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 6).start_address <= register_write_data_25_v(63 downto 0);
- when REG_DESCRIPTOR_6a => dma_descriptors_25_w_s( 6).pc_pointer <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 6).wrap_around <= register_write_data_25_v(12);
- --dma_descriptors_25_w_s( 6).read_not_write <= register_write_data_25_v(11);
- dma_descriptors_25_w_s( 6).dword_count <= register_write_data_25_v(10 downto 0);
- when REG_DESCRIPTOR_7 => dma_descriptors_25_w_s( 7).end_address <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 7).start_address <= register_write_data_25_v(63 downto 0);
- when REG_DESCRIPTOR_7a => dma_descriptors_25_w_s( 7).pc_pointer <= register_write_data_25_v(127 downto 64);
- dma_descriptors_25_w_s( 7).wrap_around <= register_write_data_25_v(12);
- --dma_descriptors_25_w_s( 7).read_not_write <= register_write_data_25_v(11);
- dma_descriptors_25_w_s( 7).dword_count <= register_write_data_25_v(10 downto 0);
- when REG_DESCRIPTOR_ENABLE => for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
- dma_descriptors_25_w_s(i).enable <= register_write_data_25_v(i);
- end loop;
- dma_descriptors_enable_written_25_s <= '1';
- when REG_FIFO_FLUSH => flush_fifo_25_s <= '1';
- when REG_DMA_RESET => dma_soft_reset_25_s <= '1';
- when REG_SOFT_RESET => reset_global_soft_25_s <= '1';
- when REG_REGISTER_RESET => reset_register_map_s <= '1';
- when REG_FROMHOST_FULL_THRESH => fromhost_pfull_threshold_assert_s <= register_write_data_25_v(24 downto 16);
- fromhost_pfull_threshold_negate_s <= register_write_data_25_v( 8 downto 0);
- when REG_TOHOST_FULL_THRESH => tohost_pfull_threshold_assert_s <= register_write_data_25_v(27 downto 16);
- tohost_pfull_threshold_negate_s <= register_write_data_25_v(11 downto 0);
- when REG_BUSY_THRESH_ASSERT => busy_threshold_assert <= register_write_data_25_v(63 downto 0);
- when REG_BUSY_THRESH_NEGATE => busy_threshold_negate <= register_write_data_25_v(63 downto 0);
- when REG_PC_PTR_GAP => pc_ptr_gap_25_s <= register_write_data_25_v(63 downto 0);
- when others => --do nothing
-
- end case;
- --Write registers in BAR1
- elsif(bar_id_25_s = "001") then
- register_write_address_v := register_write_address_25_s(19 downto 4)&"0000";
- case(register_write_address_v) is
- when REG_INT_VEC_00 => int_vector_25_s(0).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(0).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(0).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_VEC_01 => int_vector_25_s(1).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(1).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(1).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_VEC_02 => int_vector_25_s(2).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(2).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(2).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_VEC_03 => int_vector_25_s(3).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(3).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(3).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_VEC_04 => int_vector_25_s(4).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(4).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(4).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_VEC_05 => int_vector_25_s(5).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(5).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(5).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_VEC_06 => int_vector_25_s(6).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(6).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(6).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_VEC_07 => int_vector_25_s(7).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(7).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(7).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_VEC_08 => int_vector_25_s(8).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(8).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(8).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_VEC_09 => int_vector_25_s(9).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(9).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(9).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_VEC_10 => int_vector_25_s(10).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(10).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(10).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_VEC_11 => int_vector_25_s(11).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(11).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(11).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_VEC_12 => int_vector_25_s(12).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(12).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(12).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_VEC_13 => int_vector_25_s(13).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(13).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(13).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_VEC_14 => int_vector_25_s(14).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(14).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(14).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_VEC_15 => int_vector_25_s(15).int_vec_add <= register_write_data_25_v(63 downto 0);
- int_vector_25_s(15).int_vec_data <= register_write_data_25_v(95 downto 64);
- int_vector_25_s(15).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
- when REG_INT_TAB_EN => int_table_en_s <= register_write_data_25_v(NUMBER_OF_INTERRUPTS-1 downto 0);
- when others =>
- end case;
- --Write registers in BAR2
- elsif(bar_id_25_s = "010") then
- register_write_address_v := register_write_address_25_s(19 downto 4)&"0000";
- case(register_write_address_v) is
- --!
- --! generated registers write
- -------------------------------------
- ---- ## GENERATED code BEGIN #4 ----
- -------------------------------------
- when REG_STATUS_LEDS => register_map_control_s.STATUS_LEDS <= register_write_data_25_v(7 downto 0); -- Board GPIO Leds
- when REG_TIMEOUT_CTRL => register_map_control_s.TIMEOUT_CTRL.ENABLE <= register_write_data_25_v(32 downto 32); -- 1 enables the timout trailer generation for ToHost mode
- register_map_control_s.TIMEOUT_CTRL.TIMEOUT <= register_write_data_25_v(31 downto 0); -- Number of 40 MHz clock cycles after which a timeout occurs.
- when REG_CRTOHOST_FIFO_STATUS => register_map_control_s.CRTOHOST_FIFO_STATUS.CLEAR <= "1"; -- Any write to this register clears the latched FULL flags
- when REG_CRFROMHOST_FIFO_STATUS => register_map_control_s.CRFROMHOST_FIFO_STATUS.CLEAR <= "1"; -- Any write to this register clears the latched FULL flags
- when REG_BROADCAST_ENABLE_00 =>
- if GBT_NUM > 0 then
- register_map_control_s.BROADCAST_ENABLE (0) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_01 =>
- if GBT_NUM > 1 then
- register_map_control_s.BROADCAST_ENABLE (1) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_02 =>
- if GBT_NUM > 2 then
- register_map_control_s.BROADCAST_ENABLE (2) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_03 =>
- if GBT_NUM > 3 then
- register_map_control_s.BROADCAST_ENABLE (3) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_04 =>
- if GBT_NUM > 4 then
- register_map_control_s.BROADCAST_ENABLE (4) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_05 =>
- if GBT_NUM > 5 then
- register_map_control_s.BROADCAST_ENABLE (5) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_06 =>
- if GBT_NUM > 6 then
- register_map_control_s.BROADCAST_ENABLE (6) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_07 =>
- if GBT_NUM > 7 then
- register_map_control_s.BROADCAST_ENABLE (7) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_08 =>
- if GBT_NUM > 8 then
- register_map_control_s.BROADCAST_ENABLE (8) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_09 =>
- if GBT_NUM > 9 then
- register_map_control_s.BROADCAST_ENABLE (9) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_10 =>
- if GBT_NUM > 10 then
- register_map_control_s.BROADCAST_ENABLE (10) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_11 =>
- if GBT_NUM > 11 then
- register_map_control_s.BROADCAST_ENABLE (11) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_12 =>
- if GBT_NUM > 12 then
- register_map_control_s.BROADCAST_ENABLE (12) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_13 =>
- if GBT_NUM > 13 then
- register_map_control_s.BROADCAST_ENABLE (13) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_14 =>
- if GBT_NUM > 14 then
- register_map_control_s.BROADCAST_ENABLE (14) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_15 =>
- if GBT_NUM > 15 then
- register_map_control_s.BROADCAST_ENABLE (15) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_16 =>
- if GBT_NUM > 16 then
- register_map_control_s.BROADCAST_ENABLE (16) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_17 =>
- if GBT_NUM > 17 then
- register_map_control_s.BROADCAST_ENABLE (17) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_18 =>
- if GBT_NUM > 18 then
- register_map_control_s.BROADCAST_ENABLE (18) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_19 =>
- if GBT_NUM > 19 then
- register_map_control_s.BROADCAST_ENABLE (19) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_20 =>
- if GBT_NUM > 20 then
- register_map_control_s.BROADCAST_ENABLE (20) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_21 =>
- if GBT_NUM > 21 then
- register_map_control_s.BROADCAST_ENABLE (21) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_22 =>
- if GBT_NUM > 22 then
- register_map_control_s.BROADCAST_ENABLE (22) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_BROADCAST_ENABLE_23 =>
- if GBT_NUM > 23 then
- register_map_control_s.BROADCAST_ENABLE (23) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
- end if;
- when REG_LINK_00_HAS_STREAM_ID =>
- if GBT_NUM > 0 then
- register_map_control_s.HAS_STREAM_ID (0).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (0).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (0).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (0).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (0).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (0).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (0).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_01_HAS_STREAM_ID =>
- if GBT_NUM > 1 then
- register_map_control_s.HAS_STREAM_ID (1).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (1).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (1).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (1).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (1).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (1).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (1).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_02_HAS_STREAM_ID =>
- if GBT_NUM > 2 then
- register_map_control_s.HAS_STREAM_ID (2).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (2).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (2).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (2).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (2).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (2).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (2).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_03_HAS_STREAM_ID =>
- if GBT_NUM > 3 then
- register_map_control_s.HAS_STREAM_ID (3).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (3).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (3).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (3).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (3).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (3).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (3).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_04_HAS_STREAM_ID =>
- if GBT_NUM > 4 then
- register_map_control_s.HAS_STREAM_ID (4).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (4).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (4).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (4).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (4).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (4).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (4).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_05_HAS_STREAM_ID =>
- if GBT_NUM > 5 then
- register_map_control_s.HAS_STREAM_ID (5).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (5).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (5).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (5).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (5).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (5).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (5).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_06_HAS_STREAM_ID =>
- if GBT_NUM > 6 then
- register_map_control_s.HAS_STREAM_ID (6).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (6).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (6).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (6).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (6).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (6).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (6).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_07_HAS_STREAM_ID =>
- if GBT_NUM > 7 then
- register_map_control_s.HAS_STREAM_ID (7).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (7).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (7).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (7).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (7).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (7).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (7).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_08_HAS_STREAM_ID =>
- if GBT_NUM > 8 then
- register_map_control_s.HAS_STREAM_ID (8).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (8).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (8).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (8).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (8).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (8).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (8).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_09_HAS_STREAM_ID =>
- if GBT_NUM > 9 then
- register_map_control_s.HAS_STREAM_ID (9).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (9).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (9).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (9).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (9).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (9).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (9).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_10_HAS_STREAM_ID =>
- if GBT_NUM > 10 then
- register_map_control_s.HAS_STREAM_ID (10).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (10).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (10).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (10).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (10).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (10).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (10).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_11_HAS_STREAM_ID =>
- if GBT_NUM > 11 then
- register_map_control_s.HAS_STREAM_ID (11).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (11).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (11).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (11).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (11).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (11).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (11).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_12_HAS_STREAM_ID =>
- if GBT_NUM > 12 then
- register_map_control_s.HAS_STREAM_ID (12).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (12).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (12).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (12).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (12).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (12).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (12).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_13_HAS_STREAM_ID =>
- if GBT_NUM > 13 then
- register_map_control_s.HAS_STREAM_ID (13).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (13).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (13).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (13).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (13).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (13).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (13).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_14_HAS_STREAM_ID =>
- if GBT_NUM > 14 then
- register_map_control_s.HAS_STREAM_ID (14).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (14).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (14).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (14).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (14).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (14).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (14).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_15_HAS_STREAM_ID =>
- if GBT_NUM > 15 then
- register_map_control_s.HAS_STREAM_ID (15).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (15).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (15).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (15).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (15).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (15).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (15).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_16_HAS_STREAM_ID =>
- if GBT_NUM > 16 then
- register_map_control_s.HAS_STREAM_ID (16).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (16).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (16).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (16).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (16).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (16).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (16).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_17_HAS_STREAM_ID =>
- if GBT_NUM > 17 then
- register_map_control_s.HAS_STREAM_ID (17).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (17).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (17).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (17).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (17).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (17).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (17).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_18_HAS_STREAM_ID =>
- if GBT_NUM > 18 then
- register_map_control_s.HAS_STREAM_ID (18).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (18).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (18).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (18).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (18).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (18).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (18).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_19_HAS_STREAM_ID =>
- if GBT_NUM > 19 then
- register_map_control_s.HAS_STREAM_ID (19).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (19).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (19).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (19).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (19).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (19).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (19).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_20_HAS_STREAM_ID =>
- if GBT_NUM > 20 then
- register_map_control_s.HAS_STREAM_ID (20).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (20).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (20).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (20).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (20).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (20).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (20).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_21_HAS_STREAM_ID =>
- if GBT_NUM > 21 then
- register_map_control_s.HAS_STREAM_ID (21).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (21).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (21).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (21).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (21).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (21).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (21).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_22_HAS_STREAM_ID =>
- if GBT_NUM > 22 then
- register_map_control_s.HAS_STREAM_ID (22).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (22).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (22).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (22).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (22).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (22).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (22).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_LINK_23_HAS_STREAM_ID =>
- if GBT_NUM > 23 then
- register_map_control_s.HAS_STREAM_ID (23).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (23).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (23).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (23).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (23).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (23).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
- register_map_control_s.HAS_STREAM_ID (23).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
- end if;
- when REG_DECODING_LINK00_EGROUP0_CTRL =>
- if GBT_NUM > 0 then
- register_map_control_s.DECODING_EGROUP_CTRL (0)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (0)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (0)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (0)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK00_EGROUP1_CTRL =>
- if GBT_NUM > 0 then
- register_map_control_s.DECODING_EGROUP_CTRL (0)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (0)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (0)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (0)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK00_EGROUP2_CTRL =>
- if GBT_NUM > 0 then
- register_map_control_s.DECODING_EGROUP_CTRL (0)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (0)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (0)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (0)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK00_EGROUP3_CTRL =>
- if GBT_NUM > 0 then
- register_map_control_s.DECODING_EGROUP_CTRL (0)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (0)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (0)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (0)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK00_EGROUP4_CTRL =>
- if GBT_NUM > 0 then
- register_map_control_s.DECODING_EGROUP_CTRL (0)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (0)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (0)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (0)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK00_EGROUP5_CTRL =>
- if GBT_NUM > 0 then
- register_map_control_s.DECODING_EGROUP_CTRL (0)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (0)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (0)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (0)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK00_EGROUP6_CTRL =>
- if GBT_NUM > 0 then
- register_map_control_s.DECODING_EGROUP_CTRL (0)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (0)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (0)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (0)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK01_EGROUP0_CTRL =>
- if GBT_NUM > 1 then
- register_map_control_s.DECODING_EGROUP_CTRL (1)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (1)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (1)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (1)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK01_EGROUP1_CTRL =>
- if GBT_NUM > 1 then
- register_map_control_s.DECODING_EGROUP_CTRL (1)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (1)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (1)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (1)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK01_EGROUP2_CTRL =>
- if GBT_NUM > 1 then
- register_map_control_s.DECODING_EGROUP_CTRL (1)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (1)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (1)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (1)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK01_EGROUP3_CTRL =>
- if GBT_NUM > 1 then
- register_map_control_s.DECODING_EGROUP_CTRL (1)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (1)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (1)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (1)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK01_EGROUP4_CTRL =>
- if GBT_NUM > 1 then
- register_map_control_s.DECODING_EGROUP_CTRL (1)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (1)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (1)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (1)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK01_EGROUP5_CTRL =>
- if GBT_NUM > 1 then
- register_map_control_s.DECODING_EGROUP_CTRL (1)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (1)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (1)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (1)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK01_EGROUP6_CTRL =>
- if GBT_NUM > 1 then
- register_map_control_s.DECODING_EGROUP_CTRL (1)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (1)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (1)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (1)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK02_EGROUP0_CTRL =>
- if GBT_NUM > 2 then
- register_map_control_s.DECODING_EGROUP_CTRL (2)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (2)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (2)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (2)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK02_EGROUP1_CTRL =>
- if GBT_NUM > 2 then
- register_map_control_s.DECODING_EGROUP_CTRL (2)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (2)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (2)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (2)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK02_EGROUP2_CTRL =>
- if GBT_NUM > 2 then
- register_map_control_s.DECODING_EGROUP_CTRL (2)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (2)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (2)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (2)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK02_EGROUP3_CTRL =>
- if GBT_NUM > 2 then
- register_map_control_s.DECODING_EGROUP_CTRL (2)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (2)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (2)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (2)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK02_EGROUP4_CTRL =>
- if GBT_NUM > 2 then
- register_map_control_s.DECODING_EGROUP_CTRL (2)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (2)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (2)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (2)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK02_EGROUP5_CTRL =>
- if GBT_NUM > 2 then
- register_map_control_s.DECODING_EGROUP_CTRL (2)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (2)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (2)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (2)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK02_EGROUP6_CTRL =>
- if GBT_NUM > 2 then
- register_map_control_s.DECODING_EGROUP_CTRL (2)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (2)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (2)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (2)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK03_EGROUP0_CTRL =>
- if GBT_NUM > 3 then
- register_map_control_s.DECODING_EGROUP_CTRL (3)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (3)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (3)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (3)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK03_EGROUP1_CTRL =>
- if GBT_NUM > 3 then
- register_map_control_s.DECODING_EGROUP_CTRL (3)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (3)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (3)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (3)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK03_EGROUP2_CTRL =>
- if GBT_NUM > 3 then
- register_map_control_s.DECODING_EGROUP_CTRL (3)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (3)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (3)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (3)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK03_EGROUP3_CTRL =>
- if GBT_NUM > 3 then
- register_map_control_s.DECODING_EGROUP_CTRL (3)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (3)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (3)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (3)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK03_EGROUP4_CTRL =>
- if GBT_NUM > 3 then
- register_map_control_s.DECODING_EGROUP_CTRL (3)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (3)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (3)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (3)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK03_EGROUP5_CTRL =>
- if GBT_NUM > 3 then
- register_map_control_s.DECODING_EGROUP_CTRL (3)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (3)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (3)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (3)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK03_EGROUP6_CTRL =>
- if GBT_NUM > 3 then
- register_map_control_s.DECODING_EGROUP_CTRL (3)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (3)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (3)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (3)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK04_EGROUP0_CTRL =>
- if GBT_NUM > 4 then
- register_map_control_s.DECODING_EGROUP_CTRL (4)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (4)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (4)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (4)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK04_EGROUP1_CTRL =>
- if GBT_NUM > 4 then
- register_map_control_s.DECODING_EGROUP_CTRL (4)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (4)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (4)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (4)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK04_EGROUP2_CTRL =>
- if GBT_NUM > 4 then
- register_map_control_s.DECODING_EGROUP_CTRL (4)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (4)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (4)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (4)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK04_EGROUP3_CTRL =>
- if GBT_NUM > 4 then
- register_map_control_s.DECODING_EGROUP_CTRL (4)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (4)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (4)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (4)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK04_EGROUP4_CTRL =>
- if GBT_NUM > 4 then
- register_map_control_s.DECODING_EGROUP_CTRL (4)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (4)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (4)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (4)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK04_EGROUP5_CTRL =>
- if GBT_NUM > 4 then
- register_map_control_s.DECODING_EGROUP_CTRL (4)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (4)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (4)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (4)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK04_EGROUP6_CTRL =>
- if GBT_NUM > 4 then
- register_map_control_s.DECODING_EGROUP_CTRL (4)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (4)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (4)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (4)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK05_EGROUP0_CTRL =>
- if GBT_NUM > 5 then
- register_map_control_s.DECODING_EGROUP_CTRL (5)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (5)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (5)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (5)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK05_EGROUP1_CTRL =>
- if GBT_NUM > 5 then
- register_map_control_s.DECODING_EGROUP_CTRL (5)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (5)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (5)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (5)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK05_EGROUP2_CTRL =>
- if GBT_NUM > 5 then
- register_map_control_s.DECODING_EGROUP_CTRL (5)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (5)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (5)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (5)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK05_EGROUP3_CTRL =>
- if GBT_NUM > 5 then
- register_map_control_s.DECODING_EGROUP_CTRL (5)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (5)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (5)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (5)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK05_EGROUP4_CTRL =>
- if GBT_NUM > 5 then
- register_map_control_s.DECODING_EGROUP_CTRL (5)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (5)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (5)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (5)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK05_EGROUP5_CTRL =>
- if GBT_NUM > 5 then
- register_map_control_s.DECODING_EGROUP_CTRL (5)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (5)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (5)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (5)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK05_EGROUP6_CTRL =>
- if GBT_NUM > 5 then
- register_map_control_s.DECODING_EGROUP_CTRL (5)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (5)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (5)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (5)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK06_EGROUP0_CTRL =>
- if GBT_NUM > 6 then
- register_map_control_s.DECODING_EGROUP_CTRL (6)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (6)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (6)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (6)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK06_EGROUP1_CTRL =>
- if GBT_NUM > 6 then
- register_map_control_s.DECODING_EGROUP_CTRL (6)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (6)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (6)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (6)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK06_EGROUP2_CTRL =>
- if GBT_NUM > 6 then
- register_map_control_s.DECODING_EGROUP_CTRL (6)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (6)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (6)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (6)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK06_EGROUP3_CTRL =>
- if GBT_NUM > 6 then
- register_map_control_s.DECODING_EGROUP_CTRL (6)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (6)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (6)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (6)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK06_EGROUP4_CTRL =>
- if GBT_NUM > 6 then
- register_map_control_s.DECODING_EGROUP_CTRL (6)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (6)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (6)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (6)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK06_EGROUP5_CTRL =>
- if GBT_NUM > 6 then
- register_map_control_s.DECODING_EGROUP_CTRL (6)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (6)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (6)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (6)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK06_EGROUP6_CTRL =>
- if GBT_NUM > 6 then
- register_map_control_s.DECODING_EGROUP_CTRL (6)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (6)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (6)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (6)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK07_EGROUP0_CTRL =>
- if GBT_NUM > 7 then
- register_map_control_s.DECODING_EGROUP_CTRL (7)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (7)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (7)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (7)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK07_EGROUP1_CTRL =>
- if GBT_NUM > 7 then
- register_map_control_s.DECODING_EGROUP_CTRL (7)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (7)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (7)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (7)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK07_EGROUP2_CTRL =>
- if GBT_NUM > 7 then
- register_map_control_s.DECODING_EGROUP_CTRL (7)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (7)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (7)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (7)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK07_EGROUP3_CTRL =>
- if GBT_NUM > 7 then
- register_map_control_s.DECODING_EGROUP_CTRL (7)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (7)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (7)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (7)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK07_EGROUP4_CTRL =>
- if GBT_NUM > 7 then
- register_map_control_s.DECODING_EGROUP_CTRL (7)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (7)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (7)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (7)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK07_EGROUP5_CTRL =>
- if GBT_NUM > 7 then
- register_map_control_s.DECODING_EGROUP_CTRL (7)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (7)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (7)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (7)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK07_EGROUP6_CTRL =>
- if GBT_NUM > 7 then
- register_map_control_s.DECODING_EGROUP_CTRL (7)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (7)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (7)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (7)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK08_EGROUP0_CTRL =>
- if GBT_NUM > 8 then
- register_map_control_s.DECODING_EGROUP_CTRL (8)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (8)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (8)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (8)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK08_EGROUP1_CTRL =>
- if GBT_NUM > 8 then
- register_map_control_s.DECODING_EGROUP_CTRL (8)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (8)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (8)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (8)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK08_EGROUP2_CTRL =>
- if GBT_NUM > 8 then
- register_map_control_s.DECODING_EGROUP_CTRL (8)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (8)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (8)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (8)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK08_EGROUP3_CTRL =>
- if GBT_NUM > 8 then
- register_map_control_s.DECODING_EGROUP_CTRL (8)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (8)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (8)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (8)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK08_EGROUP4_CTRL =>
- if GBT_NUM > 8 then
- register_map_control_s.DECODING_EGROUP_CTRL (8)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (8)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (8)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (8)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK08_EGROUP5_CTRL =>
- if GBT_NUM > 8 then
- register_map_control_s.DECODING_EGROUP_CTRL (8)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (8)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (8)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (8)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK08_EGROUP6_CTRL =>
- if GBT_NUM > 8 then
- register_map_control_s.DECODING_EGROUP_CTRL (8)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (8)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (8)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (8)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK09_EGROUP0_CTRL =>
- if GBT_NUM > 9 then
- register_map_control_s.DECODING_EGROUP_CTRL (9)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (9)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (9)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (9)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK09_EGROUP1_CTRL =>
- if GBT_NUM > 9 then
- register_map_control_s.DECODING_EGROUP_CTRL (9)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (9)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (9)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (9)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK09_EGROUP2_CTRL =>
- if GBT_NUM > 9 then
- register_map_control_s.DECODING_EGROUP_CTRL (9)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (9)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (9)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (9)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK09_EGROUP3_CTRL =>
- if GBT_NUM > 9 then
- register_map_control_s.DECODING_EGROUP_CTRL (9)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (9)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (9)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (9)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK09_EGROUP4_CTRL =>
- if GBT_NUM > 9 then
- register_map_control_s.DECODING_EGROUP_CTRL (9)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (9)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (9)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (9)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK09_EGROUP5_CTRL =>
- if GBT_NUM > 9 then
- register_map_control_s.DECODING_EGROUP_CTRL (9)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (9)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (9)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (9)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK09_EGROUP6_CTRL =>
- if GBT_NUM > 9 then
- register_map_control_s.DECODING_EGROUP_CTRL (9)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (9)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (9)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (9)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK10_EGROUP0_CTRL =>
- if GBT_NUM > 10 then
- register_map_control_s.DECODING_EGROUP_CTRL (10)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (10)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (10)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (10)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK10_EGROUP1_CTRL =>
- if GBT_NUM > 10 then
- register_map_control_s.DECODING_EGROUP_CTRL (10)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (10)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (10)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (10)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK10_EGROUP2_CTRL =>
- if GBT_NUM > 10 then
- register_map_control_s.DECODING_EGROUP_CTRL (10)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (10)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (10)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (10)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK10_EGROUP3_CTRL =>
- if GBT_NUM > 10 then
- register_map_control_s.DECODING_EGROUP_CTRL (10)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (10)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (10)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (10)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK10_EGROUP4_CTRL =>
- if GBT_NUM > 10 then
- register_map_control_s.DECODING_EGROUP_CTRL (10)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (10)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (10)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (10)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK10_EGROUP5_CTRL =>
- if GBT_NUM > 10 then
- register_map_control_s.DECODING_EGROUP_CTRL (10)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (10)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (10)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (10)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK10_EGROUP6_CTRL =>
- if GBT_NUM > 10 then
- register_map_control_s.DECODING_EGROUP_CTRL (10)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (10)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (10)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (10)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK11_EGROUP0_CTRL =>
- if GBT_NUM > 11 then
- register_map_control_s.DECODING_EGROUP_CTRL (11)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (11)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (11)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (11)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK11_EGROUP1_CTRL =>
- if GBT_NUM > 11 then
- register_map_control_s.DECODING_EGROUP_CTRL (11)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (11)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (11)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (11)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK11_EGROUP2_CTRL =>
- if GBT_NUM > 11 then
- register_map_control_s.DECODING_EGROUP_CTRL (11)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (11)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (11)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (11)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK11_EGROUP3_CTRL =>
- if GBT_NUM > 11 then
- register_map_control_s.DECODING_EGROUP_CTRL (11)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (11)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (11)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (11)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK11_EGROUP4_CTRL =>
- if GBT_NUM > 11 then
- register_map_control_s.DECODING_EGROUP_CTRL (11)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (11)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (11)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (11)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK11_EGROUP5_CTRL =>
- if GBT_NUM > 11 then
- register_map_control_s.DECODING_EGROUP_CTRL (11)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (11)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (11)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (11)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_DECODING_LINK11_EGROUP6_CTRL =>
- if GBT_NUM > 11 then
- register_map_control_s.DECODING_EGROUP_CTRL (11)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.DECODING_EGROUP_CTRL (11)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
- -- 0: direct mode
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: TTC
- -- 4: ITk Strips 8b10b
- -- 5: ITk Pixel
- -- 6: Endeavour
- -- 7-15: reserved
-
- register_map_control_s.DECODING_EGROUP_CTRL (11)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- register_map_control_s.DECODING_EGROUP_CTRL (11)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
- end if;
- when REG_MINI_EGROUP_TOHOST_00 =>
- if GBT_NUM > 0 then
- register_map_control_s.MINI_EGROUP_TOHOST (0).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (0).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (0).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (0).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (0).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (0).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (0).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_01 =>
- if GBT_NUM > 1 then
- register_map_control_s.MINI_EGROUP_TOHOST (1).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (1).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (1).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (1).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (1).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (1).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (1).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_02 =>
- if GBT_NUM > 2 then
- register_map_control_s.MINI_EGROUP_TOHOST (2).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (2).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (2).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (2).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (2).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (2).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (2).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_03 =>
- if GBT_NUM > 3 then
- register_map_control_s.MINI_EGROUP_TOHOST (3).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (3).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (3).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (3).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (3).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (3).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (3).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_04 =>
- if GBT_NUM > 4 then
- register_map_control_s.MINI_EGROUP_TOHOST (4).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (4).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (4).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (4).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (4).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (4).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (4).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_05 =>
- if GBT_NUM > 5 then
- register_map_control_s.MINI_EGROUP_TOHOST (5).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (5).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (5).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (5).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (5).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (5).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (5).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_06 =>
- if GBT_NUM > 6 then
- register_map_control_s.MINI_EGROUP_TOHOST (6).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (6).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (6).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (6).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (6).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (6).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (6).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_07 =>
- if GBT_NUM > 7 then
- register_map_control_s.MINI_EGROUP_TOHOST (7).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (7).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (7).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (7).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (7).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (7).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (7).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_08 =>
- if GBT_NUM > 8 then
- register_map_control_s.MINI_EGROUP_TOHOST (8).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (8).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (8).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (8).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (8).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (8).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (8).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_09 =>
- if GBT_NUM > 9 then
- register_map_control_s.MINI_EGROUP_TOHOST (9).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (9).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (9).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (9).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (9).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (9).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (9).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_10 =>
- if GBT_NUM > 10 then
- register_map_control_s.MINI_EGROUP_TOHOST (10).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (10).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (10).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (10).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (10).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (10).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (10).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_11 =>
- if GBT_NUM > 11 then
- register_map_control_s.MINI_EGROUP_TOHOST (11).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (11).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (11).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (11).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (11).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (11).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (11).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_12 =>
- if GBT_NUM > 12 then
- register_map_control_s.MINI_EGROUP_TOHOST (12).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (12).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (12).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (12).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (12).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (12).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (12).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_13 =>
- if GBT_NUM > 13 then
- register_map_control_s.MINI_EGROUP_TOHOST (13).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (13).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (13).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (13).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (13).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (13).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (13).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_14 =>
- if GBT_NUM > 14 then
- register_map_control_s.MINI_EGROUP_TOHOST (14).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (14).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (14).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (14).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (14).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (14).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (14).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_15 =>
- if GBT_NUM > 15 then
- register_map_control_s.MINI_EGROUP_TOHOST (15).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (15).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (15).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (15).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (15).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (15).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (15).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_16 =>
- if GBT_NUM > 16 then
- register_map_control_s.MINI_EGROUP_TOHOST (16).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (16).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (16).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (16).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (16).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (16).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (16).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_17 =>
- if GBT_NUM > 17 then
- register_map_control_s.MINI_EGROUP_TOHOST (17).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (17).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (17).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (17).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (17).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (17).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (17).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_18 =>
- if GBT_NUM > 18 then
- register_map_control_s.MINI_EGROUP_TOHOST (18).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (18).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (18).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (18).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (18).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (18).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (18).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_19 =>
- if GBT_NUM > 19 then
- register_map_control_s.MINI_EGROUP_TOHOST (19).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (19).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (19).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (19).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (19).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (19).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (19).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_20 =>
- if GBT_NUM > 20 then
- register_map_control_s.MINI_EGROUP_TOHOST (20).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (20).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (20).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (20).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (20).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (20).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (20).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_21 =>
- if GBT_NUM > 21 then
- register_map_control_s.MINI_EGROUP_TOHOST (21).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (21).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (21).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (21).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (21).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (21).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (21).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_22 =>
- if GBT_NUM > 22 then
- register_map_control_s.MINI_EGROUP_TOHOST (22).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (22).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (22).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (22).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (22).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (22).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (22).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_MINI_EGROUP_TOHOST_23 =>
- if GBT_NUM > 23 then
- register_map_control_s.MINI_EGROUP_TOHOST (23).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (23).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_TOHOST (23).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (23).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_TOHOST (23).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_TOHOST (23).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_TOHOST (23).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
- end if;
- when REG_TTC_TOHOST_ENABLE => register_map_control_s.TTC_TOHOST_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the ToHost Mini Egroup in TTC mode
- when REG_DECODING_REVERSE_10B => register_map_control_s.DECODING_REVERSE_10B <= register_write_data_25_v(0 downto 0); -- Reverse 10-bit word of elink data for 8b10b E-links
- -- 1: Receive 10-bit word in ToHost E-Paths, MSB first
- -- 0: Receive 10-bit word in ToHost E-Paths, LSB first
-
- when REG_ENCODING_REVERSE_10B => register_map_control_s.ENCODING_REVERSE_10B <= register_write_data_25_v(0 downto 0); -- Reverse 10-bit word of elink data for 8b10b E-links. 1 MSB first, 0 LSB first
- when REG_ENCODING_LINK00_EGROUP0_CTRL =>
- if GBT_NUM > 0 then
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK00_EGROUP1_CTRL =>
- if GBT_NUM > 0 then
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK00_EGROUP2_CTRL =>
- if GBT_NUM > 0 then
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK00_EGROUP3_CTRL =>
- if GBT_NUM > 0 then
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK00_EGROUP4_CTRL =>
- if GBT_NUM > 0 then
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (0)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK01_EGROUP0_CTRL =>
- if GBT_NUM > 1 then
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK01_EGROUP1_CTRL =>
- if GBT_NUM > 1 then
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK01_EGROUP2_CTRL =>
- if GBT_NUM > 1 then
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK01_EGROUP3_CTRL =>
- if GBT_NUM > 1 then
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK01_EGROUP4_CTRL =>
- if GBT_NUM > 1 then
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (1)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK02_EGROUP0_CTRL =>
- if GBT_NUM > 2 then
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK02_EGROUP1_CTRL =>
- if GBT_NUM > 2 then
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK02_EGROUP2_CTRL =>
- if GBT_NUM > 2 then
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK02_EGROUP3_CTRL =>
- if GBT_NUM > 2 then
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK02_EGROUP4_CTRL =>
- if GBT_NUM > 2 then
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (2)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK03_EGROUP0_CTRL =>
- if GBT_NUM > 3 then
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK03_EGROUP1_CTRL =>
- if GBT_NUM > 3 then
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK03_EGROUP2_CTRL =>
- if GBT_NUM > 3 then
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK03_EGROUP3_CTRL =>
- if GBT_NUM > 3 then
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK03_EGROUP4_CTRL =>
- if GBT_NUM > 3 then
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (3)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK04_EGROUP0_CTRL =>
- if GBT_NUM > 4 then
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK04_EGROUP1_CTRL =>
- if GBT_NUM > 4 then
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK04_EGROUP2_CTRL =>
- if GBT_NUM > 4 then
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK04_EGROUP3_CTRL =>
- if GBT_NUM > 4 then
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK04_EGROUP4_CTRL =>
- if GBT_NUM > 4 then
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (4)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK05_EGROUP0_CTRL =>
- if GBT_NUM > 5 then
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK05_EGROUP1_CTRL =>
- if GBT_NUM > 5 then
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK05_EGROUP2_CTRL =>
- if GBT_NUM > 5 then
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK05_EGROUP3_CTRL =>
- if GBT_NUM > 5 then
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK05_EGROUP4_CTRL =>
- if GBT_NUM > 5 then
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (5)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK06_EGROUP0_CTRL =>
- if GBT_NUM > 6 then
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK06_EGROUP1_CTRL =>
- if GBT_NUM > 6 then
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK06_EGROUP2_CTRL =>
- if GBT_NUM > 6 then
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK06_EGROUP3_CTRL =>
- if GBT_NUM > 6 then
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK06_EGROUP4_CTRL =>
- if GBT_NUM > 6 then
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (6)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK07_EGROUP0_CTRL =>
- if GBT_NUM > 7 then
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK07_EGROUP1_CTRL =>
- if GBT_NUM > 7 then
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK07_EGROUP2_CTRL =>
- if GBT_NUM > 7 then
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK07_EGROUP3_CTRL =>
- if GBT_NUM > 7 then
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK07_EGROUP4_CTRL =>
- if GBT_NUM > 7 then
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (7)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK08_EGROUP0_CTRL =>
- if GBT_NUM > 8 then
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK08_EGROUP1_CTRL =>
- if GBT_NUM > 8 then
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK08_EGROUP2_CTRL =>
- if GBT_NUM > 8 then
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK08_EGROUP3_CTRL =>
- if GBT_NUM > 8 then
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK08_EGROUP4_CTRL =>
- if GBT_NUM > 8 then
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (8)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK09_EGROUP0_CTRL =>
- if GBT_NUM > 9 then
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK09_EGROUP1_CTRL =>
- if GBT_NUM > 9 then
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK09_EGROUP2_CTRL =>
- if GBT_NUM > 9 then
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK09_EGROUP3_CTRL =>
- if GBT_NUM > 9 then
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK09_EGROUP4_CTRL =>
- if GBT_NUM > 9 then
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (9)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK10_EGROUP0_CTRL =>
- if GBT_NUM > 10 then
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK10_EGROUP1_CTRL =>
- if GBT_NUM > 10 then
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK10_EGROUP2_CTRL =>
- if GBT_NUM > 10 then
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK10_EGROUP3_CTRL =>
- if GBT_NUM > 10 then
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK10_EGROUP4_CTRL =>
- if GBT_NUM > 10 then
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (10)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK11_EGROUP0_CTRL =>
- if GBT_NUM > 11 then
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK11_EGROUP1_CTRL =>
- if GBT_NUM > 11 then
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK11_EGROUP2_CTRL =>
- if GBT_NUM > 11 then
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK11_EGROUP3_CTRL =>
- if GBT_NUM > 11 then
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_ENCODING_LINK11_EGROUP4_CTRL =>
- if GBT_NUM > 11 then
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
- -- 0: 2 bit 80 Mb/s
- -- 1: 4 bit 160 Mb/s
- -- 2: 8 bit 320 Mb/s
-
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
- -- 0: No encoding
- -- 1: 8b10b mode
- -- 2: HDLC mode
- -- 3: ITk Strip LCB
- -- 4: ITk Pixel
- -- 5: Endeavour
- -- 6: reserved
- -- 7: reserved
- -- greater than 7: TTC mode, see firmware Phase 2 specification doc
-
- register_map_control_s.ENCODING_EGROUP_CTRL (11)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
- end if;
- when REG_MINI_EGROUP_FROMHOST_00 =>
- if GBT_NUM > 0 then
- register_map_control_s.MINI_EGROUP_FROMHOST (0).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (0).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (0).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (0).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (0).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (0).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (0).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_01 =>
- if GBT_NUM > 1 then
- register_map_control_s.MINI_EGROUP_FROMHOST (1).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (1).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (1).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (1).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (1).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (1).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (1).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_02 =>
- if GBT_NUM > 2 then
- register_map_control_s.MINI_EGROUP_FROMHOST (2).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (2).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (2).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (2).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (2).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (2).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (2).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_03 =>
- if GBT_NUM > 3 then
- register_map_control_s.MINI_EGROUP_FROMHOST (3).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (3).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (3).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (3).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (3).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (3).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (3).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_04 =>
- if GBT_NUM > 4 then
- register_map_control_s.MINI_EGROUP_FROMHOST (4).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (4).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (4).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (4).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (4).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (4).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (4).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_05 =>
- if GBT_NUM > 5 then
- register_map_control_s.MINI_EGROUP_FROMHOST (5).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (5).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (5).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (5).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (5).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (5).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (5).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_06 =>
- if GBT_NUM > 6 then
- register_map_control_s.MINI_EGROUP_FROMHOST (6).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (6).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (6).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (6).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (6).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (6).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (6).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_07 =>
- if GBT_NUM > 7 then
- register_map_control_s.MINI_EGROUP_FROMHOST (7).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (7).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (7).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (7).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (7).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (7).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (7).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_08 =>
- if GBT_NUM > 8 then
- register_map_control_s.MINI_EGROUP_FROMHOST (8).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (8).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (8).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (8).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (8).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (8).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (8).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_09 =>
- if GBT_NUM > 9 then
- register_map_control_s.MINI_EGROUP_FROMHOST (9).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (9).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (9).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (9).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (9).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (9).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (9).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_10 =>
- if GBT_NUM > 10 then
- register_map_control_s.MINI_EGROUP_FROMHOST (10).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (10).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (10).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (10).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (10).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (10).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (10).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_11 =>
- if GBT_NUM > 11 then
- register_map_control_s.MINI_EGROUP_FROMHOST (11).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (11).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (11).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (11).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (11).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (11).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (11).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_12 =>
- if GBT_NUM > 12 then
- register_map_control_s.MINI_EGROUP_FROMHOST (12).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (12).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (12).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (12).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (12).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (12).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (12).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_13 =>
- if GBT_NUM > 13 then
- register_map_control_s.MINI_EGROUP_FROMHOST (13).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (13).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (13).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (13).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (13).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (13).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (13).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_14 =>
- if GBT_NUM > 14 then
- register_map_control_s.MINI_EGROUP_FROMHOST (14).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (14).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (14).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (14).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (14).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (14).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (14).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_15 =>
- if GBT_NUM > 15 then
- register_map_control_s.MINI_EGROUP_FROMHOST (15).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (15).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (15).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (15).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (15).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (15).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (15).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_16 =>
- if GBT_NUM > 16 then
- register_map_control_s.MINI_EGROUP_FROMHOST (16).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (16).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (16).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (16).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (16).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (16).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (16).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_17 =>
- if GBT_NUM > 17 then
- register_map_control_s.MINI_EGROUP_FROMHOST (17).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (17).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (17).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (17).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (17).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (17).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (17).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_18 =>
- if GBT_NUM > 18 then
- register_map_control_s.MINI_EGROUP_FROMHOST (18).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (18).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (18).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (18).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (18).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (18).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (18).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_19 =>
- if GBT_NUM > 19 then
- register_map_control_s.MINI_EGROUP_FROMHOST (19).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (19).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (19).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (19).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (19).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (19).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (19).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_20 =>
- if GBT_NUM > 20 then
- register_map_control_s.MINI_EGROUP_FROMHOST (20).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (20).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (20).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (20).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (20).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (20).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (20).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_21 =>
- if GBT_NUM > 21 then
- register_map_control_s.MINI_EGROUP_FROMHOST (21).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (21).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (21).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (21).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (21).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (21).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (21).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_22 =>
- if GBT_NUM > 22 then
- register_map_control_s.MINI_EGROUP_FROMHOST (22).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (22).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (22).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (22).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (22).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (22).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (22).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_MINI_EGROUP_FROMHOST_23 =>
- if GBT_NUM > 23 then
- register_map_control_s.MINI_EGROUP_FROMHOST (23).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (23).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
- register_map_control_s.MINI_EGROUP_FROMHOST (23).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (23).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (23).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
- register_map_control_s.MINI_EGROUP_FROMHOST (23).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
- register_map_control_s.MINI_EGROUP_FROMHOST (23).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
- end if;
- when REG_FE_EMU_ENA => register_map_control_s.FE_EMU_ENA.EMU_TOFRONTEND <= register_write_data_25_v(1 downto 1); -- Enable GBT dummy emulator ToFrontEnd
- register_map_control_s.FE_EMU_ENA.EMU_TOHOST <= register_write_data_25_v(0 downto 0); -- Enable GBT dummy emulator ToHost
- when REG_FE_EMU_CONFIG => register_map_control_s.FE_EMU_CONFIG.WE <= register_write_data_25_v(54 downto 47); -- write enable array, every bit is one emulator RAM block
- register_map_control_s.FE_EMU_CONFIG.WRADDR <= register_write_data_25_v(46 downto 33); -- write address bus
- register_map_control_s.FE_EMU_CONFIG.WRDATA <= register_write_data_25_v(32 downto 0); -- write data bus
- when REG_FE_EMU_READ => register_map_control_s.FE_EMU_READ.SEL <= register_write_data_25_v(35 downto 33); -- Select ramblock to read back
- when REG_GBT_CHANNEL_DISABLE => register_map_control_s.GBT_CHANNEL_DISABLE <= register_write_data_25_v(47 downto 0); -- Disable selected lpGBT, GBT or FULL mode channel
- when REG_GBT_GENERAL_CTRL => register_map_control_s.GBT_GENERAL_CTRL <= register_write_data_25_v(63 downto 0); -- Alignment chk reset (not self clearing)
- when REG_GBT_MODE_CTRL => register_map_control_s.GBT_MODE_CTRL.RX_ALIGN_TB_SW <= register_write_data_25_v(2 downto 2); -- RX_ALIGN_TB_SW
- register_map_control_s.GBT_MODE_CTRL.RX_ALIGN_SW <= register_write_data_25_v(1 downto 1); -- RX_ALIGN_SW
- register_map_control_s.GBT_MODE_CTRL.DESMUX_USE_SW <= register_write_data_25_v(0 downto 0); -- DESMUX_USE_SW
+ else
+ dma_descriptors_25_w_s(i).evencycle_pc <= '0';
+ end if;
+ last_pc_pointer_v(i) := dma_descriptors_25_w_s(i).pc_pointer;
+ end loop;
+
+ dma_descriptors_enable_written_25_s <= '0';
+ register_map_control_s <= register_map_control_s; --store read (PCIe Write) register map
+ register_read_done_25_s <= '0';
+ register_read_data_25_s <= register_read_data_25_s;
+
+
+ --!
+ --! generated self clearing "write only" register clear assignment
+ -- Bar 0
+ flush_fifo_25_s <= '0';
+ dma_soft_reset_25_s <= '0';
+ reset_global_soft_25_s <= '0';
+
+ if register_map_control_s.DMA_BUSY_STATUS.CLEAR_LATCH="1" then
+ tohost_busy_latched_25_s <= '0';
+ fromhost_busy_latched_25_s <= '0';
+ end if;
+ if tohost_busy_25_s = '1' then
+ tohost_busy_latched_25_s <= '1';
+ end if;
+ if fromhost_busy_25_s = '1' then
+ fromhost_busy_latched_25_s <= '1';
+ end if;
+
+ ------------------------------------
+ ---- ## GENERATED CODE BEGIN #2 ----
+ ------------------------------------
+ register_map_control_s.CRTOHOST_FIFO_STATUS.CLEAR <= REG_CRTOHOST_FIFO_STATUS_CLEAR_C; -- Any write to this register clears the latched FULL flags
+ register_map_control_s.CRFROMHOST_FIFO_STATUS.CLEAR <= REG_CRFROMHOST_FIFO_STATUS_CLEAR_C; -- Any write to this register clears the latched FULL flags
+ register_map_control_s.TTC_BUSY_CLEAR <= REG_TTC_BUSY_CLEAR_C; -- clears the latching busy bits in TTC_BUSY_ACCEPTED
+ register_map_control_s.TTC_EMU_RESET <= REG_TTC_EMU_RESET_C; -- Any write to this register resets the TTC Emulator to the default state.
+ register_map_control_s.TTC_ECR_MONITOR.CLEAR <= REG_TTC_ECR_MONITOR_CLEAR_C; -- Counts the number of ECRs received from the TTC system, any write to this register clears the counter
+ register_map_control_s.TTC_TTYPE_MONITOR.CLEAR <= REG_TTC_TTYPE_MONITOR_CLEAR_C; -- Counts the number of TType received from the TTC system, any write to this register clears the counter
+ register_map_control_s.TTC_BCR_PERIODICITY_MONITOR.CLEAR <= REG_TTC_BCR_PERIODICITY_MONITOR_CLEAR_C; -- Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
+ register_map_control_s.XOFF_FM_HIGH_THRESH.CLEAR_LATCH <= REG_XOFF_FM_HIGH_THRESH_CLEAR_LATCH_C; -- Writing this register will clear all CROSS_LATCHED bits
+ register_map_control_s.DMA_BUSY_STATUS.CLEAR_LATCH <= REG_DMA_BUSY_STATUS_CLEAR_LATCH_C; -- Any write to this register clears TOHOST_BUSY_LATCHED
+ register_map_control_s.FM_BUSY_CHANNEL_STATUS.CLEAR_LATCH <= REG_FM_BUSY_CHANNEL_STATUS_CLEAR_LATCH_C; -- Any write to this register will clear the BUSY_LATCHED bits
+ register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_STATUS.CLEAR_LATCHED <= REG_BUSY_MAIN_OUTPUT_FIFO_STATUS_CLEAR_LATCHED_C; -- Any write to this register will clear the
+ register_map_control_s.I2C_WR.I2C_WREN <= REG_I2C_WR_I2C_WREN_C; -- Any write to this register triggers an I2C read or write sequence
+ register_map_control_s.I2C_RD.I2C_RDEN <= REG_I2C_RD_I2C_RDEN_C; -- Any write to this register pops the last I2C data from the FIFO
+ register_map_control_s.INT_TEST.TRIGGER <= REG_INT_TEST_TRIGGER_C; -- Fire a test MSIx interrupt set in IRQ
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FMEMU_RANDOM_RAM.WE <= REG_FMEMU_RANDOM_RAM_WE_C; -- Any write to this register (DATA) triggers a write to the ramblock
+ end if;
+ register_map_control_s.WISHBONE_WRITE.WRITE_ENABLE <= REG_WISHBONE_WRITE_WRITE_ENABLE_C; -- Any write to this register triggers a write to the Wupper to Wishbone fifo
+ register_map_control_s.WISHBONE_READ.READ_ENABLE <= REG_WISHBONE_READ_READ_ENABLE_C; -- Any write to this register triggers a read from the Wishbone to Wupper fifo
+ register_map_control_s.GLOBAL_TRICKLE_TRIGGER <= REG_GLOBAL_TRICKLE_TRIGGER_C; -- writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(0)(0) <= REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_0_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(0)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(0)(1) <= REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_1_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(0)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(0)(2) <= REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_2_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(0)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(0)(3) <= REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_3_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(0)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(1)(0) <= REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_0_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(1)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(1)(1) <= REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_1_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(1)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(1)(2) <= REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_2_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(1)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(1)(3) <= REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_3_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(1)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(2)(0) <= REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_0_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(2)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(2)(1) <= REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_1_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(2)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(2)(2) <= REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_2_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(2)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(2)(3) <= REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_3_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(2)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(3)(0) <= REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_0_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(3)(0).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(3)(1) <= REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_1_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(3)(1).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(3)(2) <= REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_2_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(3)(2).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER(3)(3) <= REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_3_C; -- writing to this register issues a single trickle trigger
+ end if;
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG(3)(3).MOVE_WRITE_PTR <= REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ end if;
+ register_map_control_s.STRIPS_R3_TRIGGER <= REG_STRIPS_R3_TRIGGER_C; -- (for tests only) simulate R3 trigger (issues 4-5 sequential triggers)
+ register_map_control_s.STRIPS_L1_TRIGGER <= REG_STRIPS_L1_TRIGGER_C; -- (for tests only) simulate L1 trigger (issues 4-5 sequential triggers)
+ register_map_control_s.STRIPS_R3L1_TRIGGER <= REG_STRIPS_R3L1_TRIGGER_C; -- (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)
+ -----------------------------------
+ ---- GENERATED code END #2 ## ----
+ -----------------------------------
+
+ if(register_read_enable_25_s = '1') then
+ register_read_done_25_s <= '1';
+ register_read_data_25_s <= (others => '0'); --default value
+ --Read registers in BAR0
+ if(bar_id_25_s = "000") then
+ register_read_address_v := register_read_address_25_s(19 downto 4)&"0000";
+ case(register_read_address_v) is
+ when REG_DESCRIPTOR_0 => register_read_data_25_s <= dma_descriptors_25_r_s( 0).end_address&
+ dma_descriptors_25_r_s( 0).start_address;
+ when REG_DESCRIPTOR_0a => register_read_data_25_s <= dma_descriptors_25_r_s( 0).pc_pointer&
+ x"000000000000"&"000"&
+ dma_descriptors_25_r_s( 0).wrap_around&
+ dma_descriptors_25_r_s( 0).read_not_write&
+ dma_descriptors_25_r_s( 0).dword_count;
+ when REG_DESCRIPTOR_1 => register_read_data_25_s <= dma_descriptors_25_r_s( 1).end_address&
+ dma_descriptors_25_r_s( 1).start_address;
+ when REG_DESCRIPTOR_1a => register_read_data_25_s <= dma_descriptors_25_r_s( 1).pc_pointer&
+ x"000000000000"&"000"&
+ dma_descriptors_25_r_s( 1).wrap_around&
+ dma_descriptors_25_r_s( 1).read_not_write&
+ dma_descriptors_25_r_s( 1).dword_count;
+ when REG_DESCRIPTOR_2 => register_read_data_25_s <= dma_descriptors_25_r_s( 2).end_address&
+ dma_descriptors_25_r_s( 2).start_address;
+ when REG_DESCRIPTOR_2a => register_read_data_25_s <= dma_descriptors_25_r_s( 2).pc_pointer&
+ x"000000000000"&"000"&
+ dma_descriptors_25_r_s( 2).wrap_around&
+ dma_descriptors_25_r_s( 2).read_not_write&
+ dma_descriptors_25_r_s( 2).dword_count;
+ when REG_DESCRIPTOR_3 => register_read_data_25_s <= dma_descriptors_25_r_s( 3).end_address&
+ dma_descriptors_25_r_s( 3).start_address;
+ when REG_DESCRIPTOR_3a => register_read_data_25_s <= dma_descriptors_25_r_s( 3).pc_pointer&
+ x"000000000000"&"000"&
+ dma_descriptors_25_r_s( 3).wrap_around&
+ dma_descriptors_25_r_s( 3).read_not_write&
+ dma_descriptors_25_r_s( 3).dword_count;
+ when REG_DESCRIPTOR_4 => register_read_data_25_s <= dma_descriptors_25_r_s( 4).end_address&
+ dma_descriptors_25_r_s( 4).start_address;
+ when REG_DESCRIPTOR_4a => register_read_data_25_s <= dma_descriptors_25_r_s( 4).pc_pointer&
+ x"000000000000"&"000"&
+ dma_descriptors_25_r_s( 4).wrap_around&
+ dma_descriptors_25_r_s( 4).read_not_write&
+ dma_descriptors_25_r_s( 4).dword_count;
+ when REG_DESCRIPTOR_5 => register_read_data_25_s <= dma_descriptors_25_r_s( 5).end_address&
+ dma_descriptors_25_r_s( 5).start_address;
+ when REG_DESCRIPTOR_5a => register_read_data_25_s <= dma_descriptors_25_r_s( 5).pc_pointer&
+ x"000000000000"&"000"&
+ dma_descriptors_25_r_s( 5).wrap_around&
+ dma_descriptors_25_r_s( 5).read_not_write&
+ dma_descriptors_25_r_s( 5).dword_count;
+ when REG_DESCRIPTOR_6 => register_read_data_25_s <= dma_descriptors_25_r_s( 6).end_address&
+ dma_descriptors_25_r_s( 6).start_address;
+ when REG_DESCRIPTOR_6a => register_read_data_25_s <= dma_descriptors_25_r_s( 6).pc_pointer&
+ x"000000000000"&"000"&
+ dma_descriptors_25_r_s( 6).wrap_around&
+ dma_descriptors_25_r_s( 6).read_not_write&
+ dma_descriptors_25_r_s( 6).dword_count;
+ when REG_DESCRIPTOR_7 => register_read_data_25_s <= dma_descriptors_25_r_s( 7).end_address&
+ dma_descriptors_25_r_s( 7).start_address;
+ when REG_DESCRIPTOR_7a => register_read_data_25_s <= dma_descriptors_25_r_s( 7).pc_pointer&
+ x"000000000000"&"000"&
+ dma_descriptors_25_r_s( 7).wrap_around&
+ dma_descriptors_25_r_s( 7).read_not_write&
+ dma_descriptors_25_r_s( 7).dword_count;
+ when REG_STATUS_0 => register_read_data_25_s <= x"000000000000000"&"0"&
+ dma_descriptors_25_r_s(0 ).evencycle_pc&
+ dma_status_25_s(0 ).evencycle_dma&
+ (not dma_descriptors_25_r_s(0 ).enable)&
+ dma_status_25_s(0 ).current_address;
+ when REG_STATUS_1 => register_read_data_25_s <= x"000000000000000"&"0"&
+ dma_descriptors_25_r_s(1 ).evencycle_pc&
+ dma_status_25_s(1 ).evencycle_dma&
+ (not dma_descriptors_25_r_s(1 ).enable)&
+ dma_status_25_s(1 ).current_address;
+ when REG_STATUS_2 => register_read_data_25_s <= x"000000000000000"&"0"&
+ dma_descriptors_25_r_s(2 ).evencycle_pc&
+ dma_status_25_s(2 ).evencycle_dma&
+ (not dma_descriptors_25_r_s(2 ).enable)&
+ dma_status_25_s(2 ).current_address;
+ when REG_STATUS_3 => register_read_data_25_s <= x"000000000000000"&"0"&
+ dma_descriptors_25_r_s(3 ).evencycle_pc&
+ dma_status_25_s(2 ).evencycle_dma&
+ (not dma_descriptors_25_r_s(3 ).enable)&
+ dma_status_25_s(3 ).current_address;
+ when REG_STATUS_4 => register_read_data_25_s <= x"000000000000000"&"0"&
+ dma_descriptors_25_r_s(4 ).evencycle_pc&
+ dma_status_25_s(4 ).evencycle_dma&
+ (not dma_descriptors_25_r_s(4 ).enable)&
+ dma_status_25_s(4 ).current_address;
+ when REG_STATUS_5 => register_read_data_25_s <= x"000000000000000"&"0"&
+ dma_descriptors_25_r_s(5 ).evencycle_pc&
+ dma_status_25_s(5 ).evencycle_dma&
+ (not dma_descriptors_25_r_s(5 ).enable)&
+ dma_status_25_s(5 ).current_address;
+ when REG_STATUS_6 => register_read_data_25_s <= x"000000000000000"&"0"&
+ dma_descriptors_25_r_s(6 ).evencycle_pc&
+ dma_status_25_s(6 ).evencycle_dma&
+ (not dma_descriptors_25_r_s(6 ).enable)&
+ dma_status_25_s(6 ).current_address;
+ when REG_STATUS_7 => register_read_data_25_s <= x"000000000000000"&"0"&
+ dma_descriptors_25_r_s(7 ).evencycle_pc&
+ dma_status_25_s(7 ).evencycle_dma&
+ (not dma_descriptors_25_r_s(7 ).enable)&
+ dma_status_25_s(7 ).current_address;
+ when REG_DESCRIPTOR_ENABLE => for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
+ register_read_data_25_s(i) <= dma_descriptors_25_r_s(i).enable;
+ end loop;
+ register_read_data_25_s(127 downto (NUMBER_OF_DESCRIPTORS)) <= (others =>'0');
+ when REG_FIFO_FLUSH => register_read_data_25_s <= (others => '0');
+ when REG_DMA_RESET => register_read_data_25_s <= (others => '0');
+ when REG_SOFT_RESET => register_read_data_25_s <= (others => '0');
+ when REG_REGISTER_RESET => register_read_data_25_s <= (others => '0');
+ when REG_FROMHOST_FULL_THRESH => register_read_data_25_s <= x"00000000_00000000" &
+ x"0000_0000_0"&"000"&fromhost_pfull_threshold_assert_s&
+ x"0"&"000"&fromhost_pfull_threshold_negate_s;
+ when REG_TOHOST_FULL_THRESH => register_read_data_25_s <= x"00000000_00000000" &
+ x"0000_0000_0"&tohost_pfull_threshold_assert_s&
+ x"0"&tohost_pfull_threshold_negate_s;
+ when REG_BUSY_THRESH_ASSERT => register_read_data_25_s <= x"0000_0000_0000_0000"&busy_threshold_assert;
+ when REG_BUSY_THRESH_NEGATE => register_read_data_25_s <= x"0000_0000_0000_0000"&busy_threshold_negate;
+ when REG_BUSY_STATUS => register_read_data_25_s <= x"0000_0000_0000_0000_0000_0000_0000_000"&"00"&
+ fromhost_busy_25_s&
+ tohost_busy_25_s;
+ when REG_PC_PTR_GAP => register_read_data_25_s <= x"0000_0000_0000_0000"&pc_ptr_gap_25_s;
+ when others => register_read_data_25_s <= (others => '0');
+
+
+ end case;
+ --Read registers in BAR1
+ elsif(bar_id_25_s = "001") then
+ register_read_address_v := register_read_address_25_s(19 downto 4)&"0000";
+ case(register_read_address_v) is
+ when REG_INT_VEC_00 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(0).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(0).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(0).int_vec_ctrl;
+ when REG_INT_VEC_01 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(1).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(1).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(1).int_vec_ctrl;
+ when REG_INT_VEC_02 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(2).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(2).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(2).int_vec_ctrl;
+ when REG_INT_VEC_03 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(3).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(3).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(3).int_vec_ctrl;
+ when REG_INT_VEC_04 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(4).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(4).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(4).int_vec_ctrl;
+ when REG_INT_VEC_05 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(5).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(5).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(5).int_vec_ctrl;
+ when REG_INT_VEC_06 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(6).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(6).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(6).int_vec_ctrl;
+ when REG_INT_VEC_07 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(7).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(7).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(7).int_vec_ctrl;
+ when REG_INT_VEC_08 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(8).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(8).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(8).int_vec_ctrl;
+ when REG_INT_VEC_09 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(9).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(9).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(9).int_vec_ctrl;
+ when REG_INT_VEC_10 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(10).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(10).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(10).int_vec_ctrl;
+ when REG_INT_VEC_11 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(11).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(11).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(11).int_vec_ctrl;
+ when REG_INT_VEC_12 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(12).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(12).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(12).int_vec_ctrl;
+ when REG_INT_VEC_13 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(13).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(13).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(13).int_vec_ctrl;
+ when REG_INT_VEC_14 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(14).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(14).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(14).int_vec_ctrl;
+ when REG_INT_VEC_15 => register_read_data_25_s(63 downto 0) <= int_vector_25_s(15).int_vec_add;
+ register_read_data_25_s(95 downto 64) <= int_vector_25_s(15).int_vec_data;
+ register_read_data_25_s(127 downto 96) <= int_vector_25_s(15).int_vec_ctrl;
+ when REG_INT_TAB_EN => register_read_data_25_s(NUMBER_OF_INTERRUPTS-1 downto 0) <= int_table_en_s;
+ when others => register_read_data_25_s <= (others => '0');
+ end case;
+ --Read registers in BAR2
+ elsif(bar_id_25_s = "010") then
+ register_read_address_v := register_read_address_25_s(19 downto 4)&"0000";
+ case(register_read_address_v) is
+ --!
+ --! generated registers read
+ ------------------------------------
+ ---- ## GENERATED code BEGIN #3 ----
+ ------------------------------------
+ --
+ -- Control Registers
+ --
+ when REG_STATUS_LEDS => register_read_data_25_s(7 downto 0) <= register_map_control_s.STATUS_LEDS; -- Board GPIO Leds
+ when REG_TIMEOUT_CTRL => register_read_data_25_s(32 downto 32) <= register_map_control_s.TIMEOUT_CTRL.ENABLE; -- 1 enables the timout trailer generation for ToHost mode
+ register_read_data_25_s(31 downto 0) <= register_map_control_s.TIMEOUT_CTRL.TIMEOUT; -- Number of 40 MHz clock cycles after which a timeout occurs.
+ when REG_CRTOHOST_FIFO_STATUS => register_read_data_25_s(64 downto 64) <= register_map_control_s.CRTOHOST_FIFO_STATUS.CLEAR; -- Any write to this register clears the latched FULL flags
+ register_read_data_25_s(47 downto 24) <= register_map_monitor_s.register_map_crtohost_monitor.CRTOHOST_FIFO_STATUS.FULL; -- Every bit represents the full flag of a channel FIFO
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.register_map_crtohost_monitor.CRTOHOST_FIFO_STATUS.FULL_LATCHED; -- like FULL but a latched state, clear by writing to this register
+ when REG_CRFROMHOST_FIFO_STATUS => register_read_data_25_s(64 downto 64) <= register_map_control_s.CRFROMHOST_FIFO_STATUS.CLEAR; -- Any write to this register clears the latched FULL flags
+ register_read_data_25_s(47 downto 24) <= register_map_monitor_s.register_map_crfromhost_monitor.CRFROMHOST_FIFO_STATUS.FULL; -- Every bit represents the full flag of a channel FIFO
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.register_map_crfromhost_monitor.CRFROMHOST_FIFO_STATUS.FULL_LATCHED; -- like FULL but a latched state, clear by writing to this register
+ when REG_BROADCAST_ENABLE_00 =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(0); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_01 =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(1); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_02 =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(2); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_03 =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(3); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_04 =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(4); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_05 =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(5); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_06 =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(6); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_07 =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(7); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_08 =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(8); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_09 =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(9); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_10 =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(10); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_11 =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(11); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_12 =>
+ if GBT_NUM > 12 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(12); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_13 =>
+ if GBT_NUM > 13 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(13); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_14 =>
+ if GBT_NUM > 14 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(14); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_15 =>
+ if GBT_NUM > 15 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(15); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_16 =>
+ if GBT_NUM > 16 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(16); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_17 =>
+ if GBT_NUM > 17 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(17); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_18 =>
+ if GBT_NUM > 18 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(18); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_19 =>
+ if GBT_NUM > 19 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(19); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_20 =>
+ if GBT_NUM > 20 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(20); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_21 =>
+ if GBT_NUM > 21 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(21); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_22 =>
+ if GBT_NUM > 22 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(22); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_BROADCAST_ENABLE_23 =>
+ if GBT_NUM > 23 then
+ register_read_data_25_s(41 downto 0) <= register_map_control_s.BROADCAST_ENABLE(23); -- Enable path to be included in a broadcast message.
+ end if;
+ when REG_LINK_00_HAS_STREAM_ID =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(0).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(0).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(0).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(0).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(0).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(0).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(0).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_01_HAS_STREAM_ID =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(1).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(1).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(1).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(1).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(1).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(1).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(1).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_02_HAS_STREAM_ID =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(2).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(2).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(2).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(2).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(2).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(2).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(2).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_03_HAS_STREAM_ID =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(3).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(3).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(3).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(3).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(3).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(3).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(3).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_04_HAS_STREAM_ID =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(4).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(4).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(4).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(4).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(4).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(4).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(4).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_05_HAS_STREAM_ID =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(5).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(5).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(5).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(5).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(5).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(5).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(5).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_06_HAS_STREAM_ID =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(6).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(6).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(6).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(6).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(6).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(6).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(6).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_07_HAS_STREAM_ID =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(7).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(7).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(7).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(7).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(7).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(7).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(7).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_08_HAS_STREAM_ID =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(8).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(8).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(8).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(8).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(8).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(8).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(8).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_09_HAS_STREAM_ID =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(9).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(9).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(9).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(9).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(9).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(9).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(9).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_10_HAS_STREAM_ID =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(10).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(10).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(10).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(10).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(10).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(10).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(10).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_11_HAS_STREAM_ID =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(11).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(11).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(11).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(11).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(11).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(11).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(11).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_12_HAS_STREAM_ID =>
+ if GBT_NUM > 12 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(12).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(12).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(12).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(12).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(12).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(12).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(12).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_13_HAS_STREAM_ID =>
+ if GBT_NUM > 13 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(13).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(13).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(13).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(13).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(13).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(13).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(13).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_14_HAS_STREAM_ID =>
+ if GBT_NUM > 14 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(14).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(14).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(14).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(14).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(14).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(14).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(14).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_15_HAS_STREAM_ID =>
+ if GBT_NUM > 15 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(15).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(15).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(15).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(15).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(15).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(15).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(15).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_16_HAS_STREAM_ID =>
+ if GBT_NUM > 16 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(16).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(16).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(16).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(16).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(16).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(16).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(16).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_17_HAS_STREAM_ID =>
+ if GBT_NUM > 17 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(17).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(17).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(17).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(17).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(17).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(17).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(17).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_18_HAS_STREAM_ID =>
+ if GBT_NUM > 18 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(18).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(18).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(18).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(18).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(18).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(18).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(18).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_19_HAS_STREAM_ID =>
+ if GBT_NUM > 19 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(19).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(19).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(19).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(19).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(19).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(19).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(19).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_20_HAS_STREAM_ID =>
+ if GBT_NUM > 20 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(20).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(20).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(20).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(20).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(20).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(20).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(20).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_21_HAS_STREAM_ID =>
+ if GBT_NUM > 21 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(21).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(21).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(21).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(21).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(21).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(21).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(21).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_22_HAS_STREAM_ID =>
+ if GBT_NUM > 22 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(22).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(22).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(22).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(22).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(22).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(22).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(22).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_LINK_23_HAS_STREAM_ID =>
+ if GBT_NUM > 23 then
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.HAS_STREAM_ID(23).EGROUP6; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(47 downto 40) <= register_map_control_s.HAS_STREAM_ID(23).EGROUP5; -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_read_data_25_s(39 downto 32) <= register_map_control_s.HAS_STREAM_ID(23).EGROUP4; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(31 downto 24) <= register_map_control_s.HAS_STREAM_ID(23).EGROUP3; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.HAS_STREAM_ID(23).EGROUP2; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.HAS_STREAM_ID(23).EGROUP1; -- EPATH is associated with a STREAM ID
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.HAS_STREAM_ID(23).EGROUP0; -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+ end if;
+ when REG_DECODING_LINK00_EGROUP0_CTRL =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (0)(0).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(0).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK00_EGROUP1_CTRL =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (0)(1).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(1).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK00_EGROUP2_CTRL =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (0)(2).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(2).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK00_EGROUP3_CTRL =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (0)(3).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(3).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK00_EGROUP4_CTRL =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (0)(4).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(4).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK00_EGROUP5_CTRL =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (0)(5).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(5).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK00_EGROUP6_CTRL =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (0)(6).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(0)(6).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK01_EGROUP0_CTRL =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (1)(0).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(0).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK01_EGROUP1_CTRL =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (1)(1).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(1).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK01_EGROUP2_CTRL =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (1)(2).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(2).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK01_EGROUP3_CTRL =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (1)(3).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(3).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK01_EGROUP4_CTRL =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (1)(4).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(4).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK01_EGROUP5_CTRL =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (1)(5).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(5).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK01_EGROUP6_CTRL =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (1)(6).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(1)(6).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK02_EGROUP0_CTRL =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (2)(0).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(0).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK02_EGROUP1_CTRL =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (2)(1).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(1).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK02_EGROUP2_CTRL =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (2)(2).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(2).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK02_EGROUP3_CTRL =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (2)(3).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(3).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK02_EGROUP4_CTRL =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (2)(4).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(4).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK02_EGROUP5_CTRL =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (2)(5).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(5).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK02_EGROUP6_CTRL =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (2)(6).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(2)(6).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK03_EGROUP0_CTRL =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (3)(0).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(0).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK03_EGROUP1_CTRL =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (3)(1).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(1).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK03_EGROUP2_CTRL =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (3)(2).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(2).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK03_EGROUP3_CTRL =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (3)(3).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(3).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK03_EGROUP4_CTRL =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (3)(4).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(4).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK03_EGROUP5_CTRL =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (3)(5).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(5).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK03_EGROUP6_CTRL =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (3)(6).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(3)(6).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK04_EGROUP0_CTRL =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (4)(0).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(0).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK04_EGROUP1_CTRL =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (4)(1).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(1).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK04_EGROUP2_CTRL =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (4)(2).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(2).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK04_EGROUP3_CTRL =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (4)(3).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(3).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK04_EGROUP4_CTRL =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (4)(4).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(4).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK04_EGROUP5_CTRL =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (4)(5).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(5).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK04_EGROUP6_CTRL =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (4)(6).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(4)(6).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK05_EGROUP0_CTRL =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (5)(0).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(0).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK05_EGROUP1_CTRL =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (5)(1).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(1).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK05_EGROUP2_CTRL =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (5)(2).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(2).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK05_EGROUP3_CTRL =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (5)(3).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(3).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK05_EGROUP4_CTRL =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (5)(4).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(4).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK05_EGROUP5_CTRL =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (5)(5).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(5).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK05_EGROUP6_CTRL =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (5)(6).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(5)(6).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK06_EGROUP0_CTRL =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (6)(0).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(0).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK06_EGROUP1_CTRL =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (6)(1).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(1).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK06_EGROUP2_CTRL =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (6)(2).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(2).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK06_EGROUP3_CTRL =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (6)(3).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(3).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK06_EGROUP4_CTRL =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (6)(4).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(4).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK06_EGROUP5_CTRL =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (6)(5).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(5).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK06_EGROUP6_CTRL =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (6)(6).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(6)(6).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK07_EGROUP0_CTRL =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (7)(0).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(0).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK07_EGROUP1_CTRL =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (7)(1).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(1).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK07_EGROUP2_CTRL =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (7)(2).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(2).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK07_EGROUP3_CTRL =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (7)(3).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(3).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK07_EGROUP4_CTRL =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (7)(4).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(4).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK07_EGROUP5_CTRL =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (7)(5).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(5).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK07_EGROUP6_CTRL =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (7)(6).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(7)(6).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK08_EGROUP0_CTRL =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (8)(0).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(0).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK08_EGROUP1_CTRL =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (8)(1).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(1).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK08_EGROUP2_CTRL =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (8)(2).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(2).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK08_EGROUP3_CTRL =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (8)(3).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(3).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK08_EGROUP4_CTRL =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (8)(4).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(4).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK08_EGROUP5_CTRL =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (8)(5).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(5).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK08_EGROUP6_CTRL =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (8)(6).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(8)(6).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK09_EGROUP0_CTRL =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (9)(0).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(0).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK09_EGROUP1_CTRL =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (9)(1).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(1).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK09_EGROUP2_CTRL =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (9)(2).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(2).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK09_EGROUP3_CTRL =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (9)(3).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(3).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK09_EGROUP4_CTRL =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (9)(4).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(4).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK09_EGROUP5_CTRL =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (9)(5).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(5).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK09_EGROUP6_CTRL =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (9)(6).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(9)(6).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK10_EGROUP0_CTRL =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (10)(0).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(0).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK10_EGROUP1_CTRL =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (10)(1).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(1).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK10_EGROUP2_CTRL =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (10)(2).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(2).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK10_EGROUP3_CTRL =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (10)(3).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(3).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK10_EGROUP4_CTRL =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (10)(4).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(4).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK10_EGROUP5_CTRL =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (10)(5).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(5).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK10_EGROUP6_CTRL =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (10)(6).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(10)(6).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK11_EGROUP0_CTRL =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (11)(0).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(0).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(0).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK11_EGROUP1_CTRL =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (11)(1).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(1).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(1).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK11_EGROUP2_CTRL =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (11)(2).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(2).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(2).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK11_EGROUP3_CTRL =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (11)(3).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(3).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(3).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK11_EGROUP4_CTRL =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (11)(4).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(4).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(4).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK11_EGROUP5_CTRL =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (11)(5).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(5).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(5).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(5).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(5).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK11_EGROUP6_CTRL =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_EGROUP_CTRL (11)(6).EPATH_ALMOST_FULL; -- FIFO full indication
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(6).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 11) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(6).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_read_data_25_s(10 downto 8) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(6).EPATH_WIDTH; -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.DECODING_EGROUP_CTRL(11)(6).EPATH_ENA; -- Enable bits per EPROC
+ end if;
+ when REG_MINI_EGROUP_TOHOST_00 =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (0).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(0).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(0).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (0).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(0).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(0).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (0).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(0).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(0).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(0).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_01 =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (1).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(1).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(1).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (1).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(1).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(1).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (1).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(1).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(1).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(1).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_02 =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (2).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(2).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(2).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (2).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(2).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(2).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (2).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(2).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(2).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(2).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_03 =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (3).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(3).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(3).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (3).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(3).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(3).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (3).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(3).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(3).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(3).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_04 =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (4).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(4).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(4).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (4).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(4).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(4).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (4).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(4).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(4).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(4).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_05 =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (5).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(5).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(5).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (5).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(5).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(5).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (5).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(5).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(5).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(5).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_06 =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (6).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(6).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(6).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (6).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(6).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(6).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (6).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(6).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(6).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(6).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_07 =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (7).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(7).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(7).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (7).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(7).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(7).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (7).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(7).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(7).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(7).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_08 =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (8).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(8).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(8).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (8).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(8).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(8).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (8).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(8).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(8).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(8).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_09 =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (9).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(9).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(9).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (9).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(9).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(9).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (9).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(9).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(9).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(9).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_10 =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (10).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(10).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(10).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (10).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(10).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(10).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (10).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(10).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(10).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(10).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_11 =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (11).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(11).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(11).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (11).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(11).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(11).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (11).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(11).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(11).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(11).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_12 =>
+ if GBT_NUM > 12 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (12).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(12).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(12).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (12).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(12).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(12).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (12).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(12).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(12).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(12).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_13 =>
+ if GBT_NUM > 13 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (13).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(13).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(13).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (13).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(13).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(13).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (13).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(13).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(13).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(13).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_14 =>
+ if GBT_NUM > 14 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (14).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(14).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(14).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (14).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(14).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(14).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (14).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(14).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(14).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(14).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_15 =>
+ if GBT_NUM > 15 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (15).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(15).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(15).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (15).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(15).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(15).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (15).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(15).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(15).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(15).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_16 =>
+ if GBT_NUM > 16 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (16).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(16).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(16).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (16).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(16).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(16).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (16).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(16).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(16).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(16).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_17 =>
+ if GBT_NUM > 17 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (17).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(17).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(17).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (17).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(17).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(17).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (17).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(17).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(17).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(17).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_18 =>
+ if GBT_NUM > 18 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (18).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(18).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(18).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (18).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(18).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(18).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (18).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(18).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(18).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(18).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_19 =>
+ if GBT_NUM > 19 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (19).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(19).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(19).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (19).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(19).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(19).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (19).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(19).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(19).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(19).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_20 =>
+ if GBT_NUM > 20 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (20).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(20).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(20).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (20).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(20).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(20).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (20).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(20).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(20).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(20).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_21 =>
+ if GBT_NUM > 21 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (21).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(21).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(21).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (21).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(21).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(21).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (21).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(21).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(21).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(21).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_22 =>
+ if GBT_NUM > 22 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (22).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(22).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(22).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (22).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(22).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(22).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (22).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(22).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(22).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(22).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_23 =>
+ if GBT_NUM > 23 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (23).AUX_ALMOST_FULL; -- Indicator that the AUX path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_TOHOST(23).AUX_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_TOHOST(23).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (23).IC_ALMOST_FULL; -- Indicator that the IC path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_TOHOST(23).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_TOHOST(23).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_decoding_monitor.MINI_EGROUP_TOHOST (23).EC_ALMOST_FULL; -- Indicator that the EC path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_TOHOST(23).EC_BIT_SWAPPING; -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_TOHOST(23).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_TOHOST(23).EC_ENABLE; -- Enables the EC channel
+ end if;
+ when REG_TTC_TOHOST_ENABLE => register_read_data_25_s(0 downto 0) <= register_map_control_s.TTC_TOHOST_ENABLE; -- Enables the ToHost Mini Egroup in TTC mode
+ when REG_DECODING_REVERSE_10B => register_read_data_25_s(0 downto 0) <= register_map_control_s.DECODING_REVERSE_10B; -- Reverse 10-bit word of elink data for 8b10b E-links
+ -- 1: Receive 10-bit word in ToHost E-Paths, MSB first
+ -- 0: Receive 10-bit word in ToHost E-Paths, LSB first
+
+ when REG_ENCODING_REVERSE_10B => register_read_data_25_s(0 downto 0) <= register_map_control_s.ENCODING_REVERSE_10B; -- Reverse 10-bit word of elink data for 8b10b E-links. 1 MSB first, 0 LSB first
+ when REG_ENCODING_LINK00_EGROUP0_CTRL =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (0)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(0).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK00_EGROUP1_CTRL =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (0)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(1).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK00_EGROUP2_CTRL =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (0)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(2).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK00_EGROUP3_CTRL =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (0)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(3).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK00_EGROUP4_CTRL =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (0)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(0)(4).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK01_EGROUP0_CTRL =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (1)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(0).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK01_EGROUP1_CTRL =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (1)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(1).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK01_EGROUP2_CTRL =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (1)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(2).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK01_EGROUP3_CTRL =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (1)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(3).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK01_EGROUP4_CTRL =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (1)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(1)(4).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK02_EGROUP0_CTRL =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (2)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(0).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK02_EGROUP1_CTRL =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (2)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(1).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK02_EGROUP2_CTRL =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (2)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(2).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK02_EGROUP3_CTRL =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (2)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(3).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK02_EGROUP4_CTRL =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (2)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(2)(4).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK03_EGROUP0_CTRL =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (3)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(0).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK03_EGROUP1_CTRL =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (3)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(1).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK03_EGROUP2_CTRL =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (3)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(2).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK03_EGROUP3_CTRL =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (3)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(3).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK03_EGROUP4_CTRL =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (3)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(3)(4).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK04_EGROUP0_CTRL =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (4)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(0).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK04_EGROUP1_CTRL =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (4)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(1).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK04_EGROUP2_CTRL =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (4)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(2).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK04_EGROUP3_CTRL =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (4)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(3).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK04_EGROUP4_CTRL =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (4)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(4)(4).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK05_EGROUP0_CTRL =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (5)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(0).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK05_EGROUP1_CTRL =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (5)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(1).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK05_EGROUP2_CTRL =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (5)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(2).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK05_EGROUP3_CTRL =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (5)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(3).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK05_EGROUP4_CTRL =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (5)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(5)(4).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK06_EGROUP0_CTRL =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (6)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(0).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK06_EGROUP1_CTRL =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (6)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(1).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK06_EGROUP2_CTRL =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (6)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(2).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK06_EGROUP3_CTRL =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (6)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(3).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK06_EGROUP4_CTRL =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (6)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(6)(4).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK07_EGROUP0_CTRL =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (7)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(0).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK07_EGROUP1_CTRL =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (7)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(1).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK07_EGROUP2_CTRL =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (7)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(2).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK07_EGROUP3_CTRL =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (7)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(3).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK07_EGROUP4_CTRL =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (7)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(7)(4).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK08_EGROUP0_CTRL =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (8)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(0).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK08_EGROUP1_CTRL =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (8)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(1).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK08_EGROUP2_CTRL =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (8)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(2).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK08_EGROUP3_CTRL =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (8)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(3).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK08_EGROUP4_CTRL =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (8)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(8)(4).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK09_EGROUP0_CTRL =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (9)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(0).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK09_EGROUP1_CTRL =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (9)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(1).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK09_EGROUP2_CTRL =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (9)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(2).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK09_EGROUP3_CTRL =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (9)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(3).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK09_EGROUP4_CTRL =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (9)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(9)(4).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK10_EGROUP0_CTRL =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (10)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(0).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK10_EGROUP1_CTRL =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (10)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(1).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK10_EGROUP2_CTRL =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (10)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(2).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK10_EGROUP3_CTRL =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (10)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(3).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK10_EGROUP4_CTRL =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (10)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(10)(4).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK11_EGROUP0_CTRL =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(0).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (11)(0).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(0).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(0).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(0).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(0).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK11_EGROUP1_CTRL =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(1).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (11)(1).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(1).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(1).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(1).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(1).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK11_EGROUP2_CTRL =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(2).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (11)(2).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(2).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(2).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(2).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(2).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK11_EGROUP3_CTRL =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(3).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (11)(3).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(3).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(3).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(3).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(3).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK11_EGROUP4_CTRL =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(62 downto 59) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(4).TTC_OPTION; -- Selects TTC bits sent to the E-link
+ register_read_data_25_s(58 downto 51) <= register_map_monitor_s.register_map_encoding_monitor.ENCODING_EGROUP_CTRL (11)(4).EPATH_ALMOST_FULL; -- Indiator that the EPATH FIFO is almost full
+ register_read_data_25_s(50 downto 43) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(4).REVERSE_ELINKS; -- enables bit reversing for the elink in the given epath
+ register_read_data_25_s(42 downto 40) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(4).EPATH_WIDTH; -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
+
+ register_read_data_25_s(39 downto 8) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(4).PATH_ENCODING; -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.ENCODING_EGROUP_CTRL(11)(4).EPATH_ENA; -- Enable bits per E-PATH
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_00 =>
+ if GBT_NUM > 0 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (0).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(0).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(0).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (0).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(0).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(0).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (0).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(0).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(0).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(0).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_01 =>
+ if GBT_NUM > 1 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (1).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(1).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(1).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (1).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(1).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(1).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (1).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(1).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(1).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(1).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_02 =>
+ if GBT_NUM > 2 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (2).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(2).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(2).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (2).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(2).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(2).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (2).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(2).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(2).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(2).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_03 =>
+ if GBT_NUM > 3 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (3).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(3).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(3).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (3).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(3).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(3).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (3).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(3).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(3).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(3).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_04 =>
+ if GBT_NUM > 4 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (4).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(4).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(4).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (4).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(4).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(4).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (4).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(4).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(4).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(4).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_05 =>
+ if GBT_NUM > 5 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (5).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(5).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(5).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (5).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(5).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(5).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (5).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(5).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(5).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(5).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_06 =>
+ if GBT_NUM > 6 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (6).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(6).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(6).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (6).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(6).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(6).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (6).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(6).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(6).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(6).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_07 =>
+ if GBT_NUM > 7 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (7).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(7).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(7).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (7).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(7).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(7).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (7).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(7).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(7).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(7).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_08 =>
+ if GBT_NUM > 8 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (8).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(8).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(8).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (8).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(8).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(8).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (8).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(8).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(8).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(8).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_09 =>
+ if GBT_NUM > 9 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (9).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(9).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(9).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (9).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(9).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(9).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (9).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(9).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(9).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(9).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_10 =>
+ if GBT_NUM > 10 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (10).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(10).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(10).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (10).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(10).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(10).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (10).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(10).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(10).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(10).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_11 =>
+ if GBT_NUM > 11 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (11).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(11).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(11).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (11).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(11).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(11).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (11).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(11).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(11).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(11).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_12 =>
+ if GBT_NUM > 12 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (12).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(12).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(12).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (12).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(12).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(12).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (12).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(12).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(12).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(12).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_13 =>
+ if GBT_NUM > 13 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (13).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(13).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(13).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (13).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(13).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(13).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (13).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(13).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(13).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(13).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_14 =>
+ if GBT_NUM > 14 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (14).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(14).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(14).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (14).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(14).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(14).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (14).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(14).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(14).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(14).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_15 =>
+ if GBT_NUM > 15 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (15).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(15).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(15).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (15).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(15).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(15).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (15).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(15).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(15).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(15).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_16 =>
+ if GBT_NUM > 16 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (16).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(16).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(16).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (16).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(16).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(16).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (16).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(16).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(16).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(16).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_17 =>
+ if GBT_NUM > 17 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (17).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(17).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(17).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (17).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(17).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(17).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (17).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(17).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(17).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(17).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_18 =>
+ if GBT_NUM > 18 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (18).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(18).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(18).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (18).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(18).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(18).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (18).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(18).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(18).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(18).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_19 =>
+ if GBT_NUM > 19 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (19).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(19).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(19).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (19).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(19).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(19).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (19).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(19).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(19).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(19).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_20 =>
+ if GBT_NUM > 20 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (20).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(20).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(20).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (20).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(20).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(20).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (20).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(20).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(20).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(20).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_21 =>
+ if GBT_NUM > 21 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (21).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(21).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(21).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (21).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(21).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(21).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (21).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(21).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(21).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(21).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_22 =>
+ if GBT_NUM > 22 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (22).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(22).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(22).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (22).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(22).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(22).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (22).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(22).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(22).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(22).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_23 =>
+ if GBT_NUM > 23 then
+ register_read_data_25_s(12 downto 12) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (23).AUX_ALMOST_FULL; -- Indicator that the AUX Path FIFO is almost full
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.MINI_EGROUP_FROMHOST(23).AUX_BIT_SWAPPING; -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.MINI_EGROUP_FROMHOST(23).AUX_ENABLE; -- Enables the AUX channel
+ register_read_data_25_s(9 downto 9) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (23).IC_ALMOST_FULL; -- Indicator that the IC Path FIFO is almost full
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.MINI_EGROUP_FROMHOST(23).IC_BIT_SWAPPING; -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.MINI_EGROUP_FROMHOST(23).IC_ENABLE; -- Enables the IC channel
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_encoding_monitor.MINI_EGROUP_FROMHOST (23).EC_ALMOST_FULL; -- Indicator that the EC Path FIFO is almost full
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.MINI_EGROUP_FROMHOST(23).EC_BIT_SWAPPING; -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_read_data_25_s(4 downto 1) <= register_map_control_s.MINI_EGROUP_FROMHOST(23).EC_ENCODING; -- Configures encoding of the EC channel
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.MINI_EGROUP_FROMHOST(23).EC_ENABLE; -- Configures the FromHost Mini egroup
+ end if;
+ when REG_FE_EMU_ENA => register_read_data_25_s(1 downto 1) <= register_map_control_s.FE_EMU_ENA.EMU_TOFRONTEND; -- Enable GBT dummy emulator ToFrontEnd
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FE_EMU_ENA.EMU_TOHOST; -- Enable GBT dummy emulator ToHost
+ when REG_FE_EMU_CONFIG => register_read_data_25_s(54 downto 47) <= register_map_control_s.FE_EMU_CONFIG.WE; -- write enable array, every bit is one emulator RAM block
+ register_read_data_25_s(46 downto 33) <= register_map_control_s.FE_EMU_CONFIG.WRADDR; -- write address bus
+ register_read_data_25_s(32 downto 0) <= register_map_control_s.FE_EMU_CONFIG.WRDATA; -- write data bus
+ when REG_FE_EMU_READ => register_read_data_25_s(35 downto 33) <= register_map_control_s.FE_EMU_READ.SEL; -- Select ramblock to read back
+ register_read_data_25_s(32 downto 0) <= register_map_monitor_s.register_map_gbtemu_monitor.FE_EMU_READ.DATA; -- Read back ramblock at FE_EMU_CONFIG.WRADDR
+ when REG_GBT_CHANNEL_DISABLE => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_CHANNEL_DISABLE; -- Disable selected lpGBT, GBT or FULL mode channel
+ when REG_GBT_GENERAL_CTRL => register_read_data_25_s(63 downto 0) <= register_map_control_s.GBT_GENERAL_CTRL; -- Alignment chk reset (not self clearing)
+ when REG_GBT_MODE_CTRL => register_read_data_25_s(2 downto 2) <= register_map_control_s.GBT_MODE_CTRL.RX_ALIGN_TB_SW; -- RX_ALIGN_TB_SW
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.GBT_MODE_CTRL.RX_ALIGN_SW; -- RX_ALIGN_SW
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.GBT_MODE_CTRL.DESMUX_USE_SW; -- DESMUX_USE_SW
when REG_GBT_RXSLIDE_SELECT =>
- if GBT_GENERATE_ALL_REGS then
- register_map_control_s.GBT_RXSLIDE_SELECT <= register_write_data_25_v(47 downto 0); -- RxSlide select [47:0]
- end if;
+ if GBT_GENERATE_ALL_REGS then
+ register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_RXSLIDE_SELECT; -- RxSlide select [47:0]
+ end if;
when REG_GBT_RXSLIDE_MANUAL =>
- if GBT_GENERATE_ALL_REGS then
- register_map_control_s.GBT_RXSLIDE_MANUAL <= register_write_data_25_v(47 downto 0); -- RxSlide select [47:0]
- end if;
+ if GBT_GENERATE_ALL_REGS then
+ register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_RXSLIDE_MANUAL; -- RxSlide select [47:0]
+ end if;
when REG_GBT_TXUSRRDY =>
- if GBT_GENERATE_ALL_REGS then
- register_map_control_s.GBT_TXUSRRDY <= register_write_data_25_v(47 downto 0); -- TxUsrRdy [47:0]
- end if;
+ if GBT_GENERATE_ALL_REGS then
+ register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TXUSRRDY; -- TxUsrRdy [47:0]
+ end if;
when REG_GBT_RXUSRRDY =>
- if GBT_GENERATE_ALL_REGS then
- register_map_control_s.GBT_RXUSRRDY <= register_write_data_25_v(47 downto 0); -- RxUsrRdy [47:0]
- end if;
- when REG_GBT_SOFT_RESET => register_map_control_s.GBT_SOFT_RESET <= register_write_data_25_v(47 downto 0); -- SOFT_RESET [47:0]
- when REG_GBT_GTTX_RESET => register_map_control_s.GBT_GTTX_RESET <= register_write_data_25_v(47 downto 0); -- GTTX_RESET [47:0]
- when REG_GBT_GTRX_RESET => register_map_control_s.GBT_GTRX_RESET <= register_write_data_25_v(47 downto 0); -- GTRX_RESET [47:0]
- when REG_GBT_PLL_RESET => register_map_control_s.GBT_PLL_RESET.QPLL_RESET <= register_write_data_25_v(59 downto 48); -- QPLL_RESET [11:0]
- register_map_control_s.GBT_PLL_RESET.CPLL_RESET <= register_write_data_25_v(47 downto 0); -- CPLL_RESET [47:0]
+ if GBT_GENERATE_ALL_REGS then
+ register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_RXUSRRDY; -- RxUsrRdy [47:0]
+ end if;
+ when REG_GBT_SOFT_RESET => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_SOFT_RESET; -- SOFT_RESET [47:0]
+ when REG_GBT_GTTX_RESET => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_GTTX_RESET; -- GTTX_RESET [47:0]
+ when REG_GBT_GTRX_RESET => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_GTRX_RESET; -- GTRX_RESET [47:0]
+ when REG_GBT_PLL_RESET => register_read_data_25_s(59 downto 48) <= register_map_control_s.GBT_PLL_RESET.QPLL_RESET; -- QPLL_RESET [11:0]
+ register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_PLL_RESET.CPLL_RESET; -- CPLL_RESET [47:0]
when REG_GBT_SOFT_TX_RESET =>
- if GBT_GENERATE_ALL_REGS then
- register_map_control_s.GBT_SOFT_TX_RESET.RESET_ALL <= register_write_data_25_v(59 downto 48); -- SOFT_TX_RESET_ALL [11:0]
- register_map_control_s.GBT_SOFT_TX_RESET.RESET_GT <= register_write_data_25_v(47 downto 0); -- SOFT_TX_RESET_GT [47:0]
- end if;
+ if GBT_GENERATE_ALL_REGS then
+ register_read_data_25_s(59 downto 48) <= register_map_control_s.GBT_SOFT_TX_RESET.RESET_ALL; -- SOFT_TX_RESET_ALL [11:0]
+ register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_SOFT_TX_RESET.RESET_GT; -- SOFT_TX_RESET_GT [47:0]
+ end if;
when REG_GBT_SOFT_RX_RESET =>
- if GBT_GENERATE_ALL_REGS then
- register_map_control_s.GBT_SOFT_RX_RESET.RESET_ALL <= register_write_data_25_v(59 downto 48); -- SOFT_TX_RESET_ALL [11:0]
- register_map_control_s.GBT_SOFT_RX_RESET.RESET_GT <= register_write_data_25_v(47 downto 0); -- SOFT_TX_RESET_GT [47:0]
- end if;
+ if GBT_GENERATE_ALL_REGS then
+ register_read_data_25_s(59 downto 48) <= register_map_control_s.GBT_SOFT_RX_RESET.RESET_ALL; -- SOFT_TX_RESET_ALL [11:0]
+ register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_SOFT_RX_RESET.RESET_GT; -- SOFT_TX_RESET_GT [47:0]
+ end if;
when REG_GBT_ODD_EVEN =>
- if GBT_GENERATE_ALL_REGS then
- register_map_control_s.GBT_ODD_EVEN <= register_write_data_25_v(47 downto 0); -- OddEven [47:0]
- end if;
- when REG_GBT_TOPBOT =>
- if GBT_GENERATE_ALL_REGS then
- register_map_control_s.GBT_TOPBOT <= register_write_data_25_v(47 downto 0); -- TopBot [47:0]
- end if;
- when REG_GBT_TX_TC_DLY_VALUE1 => register_map_control_s.GBT_TX_TC_DLY_VALUE1 <= register_write_data_25_v(47 downto 0); -- TX_TC_DLY_VALUE [47:0]
- when REG_GBT_TX_TC_DLY_VALUE2 => register_map_control_s.GBT_TX_TC_DLY_VALUE2 <= register_write_data_25_v(47 downto 0); -- TX_TC_DLY_VALUE [95:48]
- when REG_GBT_TX_TC_DLY_VALUE3 => register_map_control_s.GBT_TX_TC_DLY_VALUE3 <= register_write_data_25_v(47 downto 0); -- TX_TC_DLY_VALUE [143:96]
- when REG_GBT_TX_TC_DLY_VALUE4 => register_map_control_s.GBT_TX_TC_DLY_VALUE4 <= register_write_data_25_v(47 downto 0); -- TX_TC_DLY_VALUE [191:144]
- when REG_GBT_DATA_TXFORMAT1 => register_map_control_s.GBT_DATA_TXFORMAT1 <= register_write_data_25_v(47 downto 0); -- DATA_TXFORMAT [47:0]
- when REG_GBT_DATA_TXFORMAT2 => register_map_control_s.GBT_DATA_TXFORMAT2 <= register_write_data_25_v(47 downto 0); -- DATA_TXFORMAT [95:48]
- when REG_GBT_DATA_RXFORMAT1 => register_map_control_s.GBT_DATA_RXFORMAT1 <= register_write_data_25_v(47 downto 0); -- DATA_RXFORMAT [47:0]
- when REG_GBT_DATA_RXFORMAT2 => register_map_control_s.GBT_DATA_RXFORMAT2 <= register_write_data_25_v(47 downto 0); -- DATA_RXFORMAT [95:0]
- when REG_GBT_TX_RESET => register_map_control_s.GBT_TX_RESET <= register_write_data_25_v(47 downto 0); -- TX Logic reset [47:0]
- when REG_GBT_RX_RESET => register_map_control_s.GBT_RX_RESET <= register_write_data_25_v(47 downto 0); -- RX Logic reset [47:0]
- when REG_GBT_TX_TC_METHOD => register_map_control_s.GBT_TX_TC_METHOD <= register_write_data_25_v(47 downto 0); -- TX time domain crossing method [47:0]
- when REG_GBT_OUTMUX_SEL => register_map_control_s.GBT_OUTMUX_SEL <= register_write_data_25_v(47 downto 0); -- Descrambler output MUX selection [47:0]
- when REG_GBT_TC_EDGE => register_map_control_s.GBT_TC_EDGE <= register_write_data_25_v(47 downto 0); -- Sampling edge selection for TX domain crossing [47:0]
- when REG_GBT_TXPOLARITY => register_map_control_s.GBT_TXPOLARITY <= register_write_data_25_v(47 downto 0); -- 0: default polarity
- -- 1: reversed polarity for transmitter of GTH channels
-
- when REG_GBT_RXPOLARITY => register_map_control_s.GBT_RXPOLARITY <= register_write_data_25_v(47 downto 0); -- 0: default polarity
- -- 1: reversed polarity for the receiver of the GTH channels
-
- when REG_GTH_LOOPBACK_CONTROL => register_map_control_s.GTH_LOOPBACK_CONTROL <= register_write_data_25_v(2 downto 0); -- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- -- 000: Normal operation
- -- 001: Near-End PCS Loopback
- -- 010: Near-End PMA Loopback
- -- 011: Reserved
- -- 100: Far-End PMA Loopback
- -- 101: Reserved
- -- 110: Far-End PCS Loopback
-
- when REG_GBT_TOHOST_FANOUT => register_map_control_s.GBT_TOHOST_FANOUT.LOCK <= register_write_data_25_v(48 downto 48); -- Locks this particular register. If set prevents software from touching it.
- register_map_control_s.GBT_TOHOST_FANOUT.SEL <= register_write_data_25_v(47 downto 0); -- ToHost FanOut/Selector. Every bitfield is a channel:
- -- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- -- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- when REG_GBT_TOFRONTEND_FANOUT => register_map_control_s.GBT_TOFRONTEND_FANOUT.LOCK <= register_write_data_25_v(48 downto 48); -- Locks this particular register. If set prevents software from touching it.
- register_map_control_s.GBT_TOFRONTEND_FANOUT.SEL <= register_write_data_25_v(47 downto 0); -- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- -- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- -- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
- --
-
- when REG_TTC_DEC_CTRL => register_map_control_s.TTC_DEC_CTRL.BCID_ONBCR <= register_write_data_25_v(26 downto 15); -- BCID is set to this value when BCR arrives
- register_map_control_s.TTC_DEC_CTRL.ECR_BCR_SWAP <= register_write_data_25_v(13 downto 13); -- ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
- register_map_control_s.TTC_DEC_CTRL.BUSY_OUTPUT_INHIBIT <= register_write_data_25_v(12 downto 12); -- forces the Busy LEMO output to BUSY-OFF
- register_map_control_s.TTC_DEC_CTRL.TOHOST_RST <= register_write_data_25_v(11 downto 11); -- reset toHost in ttc decoder
- register_map_control_s.TTC_DEC_CTRL.TT_BCH_EN <= register_write_data_25_v(10 downto 10); -- trigger type enable / disable for TTC-ToHost
- register_map_control_s.TTC_DEC_CTRL.XL1ID_SW <= register_write_data_25_v(9 downto 2); -- set XL1ID value, the value to be set by XL1ID_RST signal
- register_map_control_s.TTC_DEC_CTRL.XL1ID_RST <= register_write_data_25_v(1 downto 1); -- giving a trigger signal to reset XL1ID value
- register_map_control_s.TTC_DEC_CTRL.MASTER_BUSY <= register_write_data_25_v(0 downto 0); -- L1A trigger throttling
- when REG_TTC_EMU => register_map_control_s.TTC_EMU.SEL <= register_write_data_25_v(1 downto 1); -- Select TTC data source 1 TTC Emu | 0 TTC Decoder
- register_map_control_s.TTC_EMU.ENA <= register_write_data_25_v(0 downto 0); -- Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
- when REG_TTC_DELAY_00 => register_map_control_s.TTC_DELAY (0) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_01 => register_map_control_s.TTC_DELAY (1) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_02 => register_map_control_s.TTC_DELAY (2) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_03 => register_map_control_s.TTC_DELAY (3) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_04 => register_map_control_s.TTC_DELAY (4) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_05 => register_map_control_s.TTC_DELAY (5) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_06 => register_map_control_s.TTC_DELAY (6) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_07 => register_map_control_s.TTC_DELAY (7) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_08 => register_map_control_s.TTC_DELAY (8) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_09 => register_map_control_s.TTC_DELAY (9) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_10 => register_map_control_s.TTC_DELAY (10) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_11 => register_map_control_s.TTC_DELAY (11) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_12 => register_map_control_s.TTC_DELAY (12) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_13 => register_map_control_s.TTC_DELAY (13) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_14 => register_map_control_s.TTC_DELAY (14) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_15 => register_map_control_s.TTC_DELAY (15) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_16 => register_map_control_s.TTC_DELAY (16) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_17 => register_map_control_s.TTC_DELAY (17) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_18 => register_map_control_s.TTC_DELAY (18) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_19 => register_map_control_s.TTC_DELAY (19) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_20 => register_map_control_s.TTC_DELAY (20) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_21 => register_map_control_s.TTC_DELAY (21) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_22 => register_map_control_s.TTC_DELAY (22) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_23 => register_map_control_s.TTC_DELAY (23) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_24 => register_map_control_s.TTC_DELAY (24) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_25 => register_map_control_s.TTC_DELAY (25) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_26 => register_map_control_s.TTC_DELAY (26) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_27 => register_map_control_s.TTC_DELAY (27) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_28 => register_map_control_s.TTC_DELAY (28) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_29 => register_map_control_s.TTC_DELAY (29) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_30 => register_map_control_s.TTC_DELAY (30) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_31 => register_map_control_s.TTC_DELAY (31) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_32 => register_map_control_s.TTC_DELAY (32) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_33 => register_map_control_s.TTC_DELAY (33) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_34 => register_map_control_s.TTC_DELAY (34) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_35 => register_map_control_s.TTC_DELAY (35) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_36 => register_map_control_s.TTC_DELAY (36) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_37 => register_map_control_s.TTC_DELAY (37) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_38 => register_map_control_s.TTC_DELAY (38) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_39 => register_map_control_s.TTC_DELAY (39) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_40 => register_map_control_s.TTC_DELAY (40) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_41 => register_map_control_s.TTC_DELAY (41) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_42 => register_map_control_s.TTC_DELAY (42) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_43 => register_map_control_s.TTC_DELAY (43) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_44 => register_map_control_s.TTC_DELAY (44) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_45 => register_map_control_s.TTC_DELAY (45) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_46 => register_map_control_s.TTC_DELAY (46) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_DELAY_47 => register_map_control_s.TTC_DELAY (47) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
- when REG_TTC_BUSY_TIMING_CTRL => register_map_control_s.TTC_BUSY_TIMING_CTRL.PRESCALE <= register_write_data_25_v(51 downto 32); -- Prescales the 40MHz clock to create an internal slow clock
- register_map_control_s.TTC_BUSY_TIMING_CTRL.BUSY_WIDTH <= register_write_data_25_v(31 downto 16); -- Minimum number of 40MHz clocks that the busy is asserted
- register_map_control_s.TTC_BUSY_TIMING_CTRL.LIMIT_TIME <= register_write_data_25_v(15 downto 0); -- Number of prescaled clocks a given busy must be asserted before it is recognized
- when REG_TTC_BUSY_CLEAR => register_map_control_s.TTC_BUSY_CLEAR <= "1"; -- clears the latching busy bits in TTC_BUSY_ACCEPTED
- when REG_TTC_EMU_CONTROL => register_map_control_s.TTC_EMU_CONTROL.BROADCAST <= register_write_data_25_v(32 downto 27); -- Broadcast data
- register_map_control_s.TTC_EMU_CONTROL.ECR <= register_write_data_25_v(26 downto 26); -- Event counter reset
- register_map_control_s.TTC_EMU_CONTROL.BCR <= register_write_data_25_v(25 downto 25); -- Bunch counter reset
- register_map_control_s.TTC_EMU_CONTROL.L1A <= register_write_data_25_v(24 downto 24); -- Level 1 Accept
- when REG_TTC_EMU_L1A_PERIOD => register_map_control_s.TTC_EMU_L1A_PERIOD <= register_write_data_25_v(31 downto 0); -- L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
- when REG_TTC_EMU_ECR_PERIOD => register_map_control_s.TTC_EMU_ECR_PERIOD <= register_write_data_25_v(31 downto 0); -- ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
- when REG_TTC_EMU_BCR_PERIOD => register_map_control_s.TTC_EMU_BCR_PERIOD <= register_write_data_25_v(31 downto 0); -- BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
- when REG_TTC_EMU_LONG_CHANNEL_DATA => register_map_control_s.TTC_EMU_LONG_CHANNEL_DATA <= register_write_data_25_v(31 downto 0); -- Long channel data for the TTC emulator
- when REG_TTC_EMU_RESET => register_map_control_s.TTC_EMU_RESET <= "1"; -- Any write to this register resets the TTC Emulator to the default state.
- when REG_TTC_ECR_MONITOR => register_map_control_s.TTC_ECR_MONITOR.CLEAR <= "1"; -- Counts the number of ECRs received from the TTC system, any write to this register clears the counter
- when REG_TTC_TTYPE_MONITOR => register_map_control_s.TTC_TTYPE_MONITOR.CLEAR <= "1"; -- Counts the number of TType received from the TTC system, any write to this register clears the counter
- when REG_TTC_BCR_PERIODICITY_MONITOR => register_map_control_s.TTC_BCR_PERIODICITY_MONITOR.CLEAR <= "1"; -- Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
- when REG_XOFF_FM_CH_FIFO_THRESH_LOW => register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW <= register_write_data_25_v(3 downto 0); -- Controls the low threshold of the channel fifo in FULL mode on which
- -- an Xon will be asserted, bitfields control 4 MSB
-
- when REG_XOFF_FM_CH_FIFO_THRESH_HIGH => register_map_control_s.XOFF_FM_CH_FIFO_THRESH_HIGH <= register_write_data_25_v(3 downto 0); -- Controls the high threshold of the channel fifo in FULL mode on which
- -- an Xoff will be asserted, bitfields control 4 MSB - name: XOFF_FM_LOW_THRESH_CROSSED
-
- when REG_XOFF_FM_HIGH_THRESH => register_map_control_s.XOFF_FM_HIGH_THRESH.CLEAR_LATCH <= "1"; -- Writing this register will clear all CROSS_LATCHED bits
- when REG_XOFF_FM_SOFT_XOFF => register_map_control_s.XOFF_FM_SOFT_XOFF <= register_write_data_25_v(23 downto 0); -- Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
- when REG_XOFF_ENABLE => register_map_control_s.XOFF_ENABLE <= register_write_data_25_v(23 downto 0); -- Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
- when REG_DMA_BUSY_STATUS => register_map_control_s.DMA_BUSY_STATUS.CLEAR_LATCH <= "1"; -- Any write to this register clears TOHOST_BUSY_LATCHED
- register_map_control_s.DMA_BUSY_STATUS.ENABLE <= register_write_data_25_v(4 downto 4); -- Enable the DMA buffer on the server as a source of busy
- when REG_FM_BUSY_CHANNEL_STATUS => register_map_control_s.FM_BUSY_CHANNEL_STATUS.CLEAR_LATCH <= "1"; -- Any write to this register will clear the BUSY_LATCHED bits
- when REG_BUSY_MAIN_OUTPUT_FIFO_THRESH => register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_THRESH.BUSY_ENABLE <= register_write_data_25_v(24 downto 24); -- Enable busy generation if thresholds are crossed
- register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_THRESH.LOW <= register_write_data_25_v(23 downto 12); -- Low, Negate threshold of busy generation from main output fifo
- register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_THRESH.HIGH <= register_write_data_25_v(11 downto 0); -- High, Assert threshold of busy generation from main output fifo
- when REG_BUSY_MAIN_OUTPUT_FIFO_STATUS => register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_STATUS.CLEAR_LATCHED <= "1"; -- Any write to this register will clear the
- when REG_ELINK_BUSY_ENABLE00 => register_map_control_s.ELINK_BUSY_ENABLE (0) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE01 => register_map_control_s.ELINK_BUSY_ENABLE (1) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE02 => register_map_control_s.ELINK_BUSY_ENABLE (2) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE03 => register_map_control_s.ELINK_BUSY_ENABLE (3) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE04 => register_map_control_s.ELINK_BUSY_ENABLE (4) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE05 => register_map_control_s.ELINK_BUSY_ENABLE (5) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE06 => register_map_control_s.ELINK_BUSY_ENABLE (6) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE07 => register_map_control_s.ELINK_BUSY_ENABLE (7) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE08 => register_map_control_s.ELINK_BUSY_ENABLE (8) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE09 => register_map_control_s.ELINK_BUSY_ENABLE (9) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE10 => register_map_control_s.ELINK_BUSY_ENABLE (10) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE11 => register_map_control_s.ELINK_BUSY_ENABLE (11) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE12 => register_map_control_s.ELINK_BUSY_ENABLE (12) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE13 => register_map_control_s.ELINK_BUSY_ENABLE (13) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE14 => register_map_control_s.ELINK_BUSY_ENABLE (14) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE15 => register_map_control_s.ELINK_BUSY_ENABLE (15) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE16 => register_map_control_s.ELINK_BUSY_ENABLE (16) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE17 => register_map_control_s.ELINK_BUSY_ENABLE (17) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE18 => register_map_control_s.ELINK_BUSY_ENABLE (18) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE19 => register_map_control_s.ELINK_BUSY_ENABLE (19) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE20 => register_map_control_s.ELINK_BUSY_ENABLE (20) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE21 => register_map_control_s.ELINK_BUSY_ENABLE (21) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE22 => register_map_control_s.ELINK_BUSY_ENABLE (22) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_ELINK_BUSY_ENABLE23 => register_map_control_s.ELINK_BUSY_ENABLE (23) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- when REG_HK_CTRL_I2C => register_map_control_s.HK_CTRL_I2C.CONFIG_TRIG <= register_write_data_25_v(1 downto 1); -- i2c_config_trig
- register_map_control_s.HK_CTRL_I2C.CLKFREQ_SEL <= register_write_data_25_v(0 downto 0); -- i2c_clkfreq_sel
- when REG_HK_CTRL_FMC => register_map_control_s.HK_CTRL_FMC.SI5345_INSEL <= register_write_data_25_v(6 downto 5); -- Selects the input clock source
- -- 0 : FPGA (FMC LA01)
- -- 1 : FMC OSC (40.079 MHz)
- -- 2 : FPGA (FMC LA18)
-
- register_map_control_s.HK_CTRL_FMC.SI5345_A <= register_write_data_25_v(4 downto 3); -- Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- register_map_control_s.HK_CTRL_FMC.SI5345_OE <= register_write_data_25_v(2 downto 2); -- Si5345 active low output enable (0:enable)
- register_map_control_s.HK_CTRL_FMC.SI5345_RSTN <= register_write_data_25_v(1 downto 1); -- Si5345 active low output enable (0:reset)
- register_map_control_s.HK_CTRL_FMC.SI5345_SEL <= register_write_data_25_v(0 downto 0); -- Si5345 programming mode
- -- 1 : I2C mode (default)
- -- 0 : SPI mode
-
- when REG_HK_MON_FMC => register_map_control_s.HK_MON_FMC.SI5345_LOL <= register_write_data_25_v(1 downto 1); -- Si5345 Loss Of Lock pin
- register_map_control_s.HK_MON_FMC.SI5345_INTR <= register_write_data_25_v(0 downto 0); -- Si5345 Interrupt flagging chip change of status
- when REG_MMCM_MAIN => register_map_control_s.MMCM_MAIN.LCLK_SEL <= register_write_data_25_v(3 downto 3); -- 1: LCLK
- -- 0: TTC
-
- when REG_I2C_WR => register_map_control_s.I2C_WR.I2C_WREN <= not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL; -- Any write to this register triggers an I2C read or write sequence
- register_map_control_s.I2C_WR.WRITE_2BYTES <= register_write_data_25_v(24 downto 24); -- Write two bytes
- register_map_control_s.I2C_WR.DATA_BYTE2 <= register_write_data_25_v(23 downto 16); -- Data byte 2
- register_map_control_s.I2C_WR.DATA_BYTE1 <= register_write_data_25_v(15 downto 8); -- Data byte 1
- register_map_control_s.I2C_WR.SLAVE_ADDRESS <= register_write_data_25_v(7 downto 1); -- Slave address
- register_map_control_s.I2C_WR.READ_NOT_WRITE <= register_write_data_25_v(0 downto 0); -- READ/<o>WRITE</o>
- when REG_I2C_RD => register_map_control_s.I2C_RD.I2C_RDEN <= not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY; -- Any write to this register pops the last I2C data from the FIFO
- when REG_INT_TEST => register_map_control_s.INT_TEST.TRIGGER <= "1"; -- Fire a test MSIx interrupt set in IRQ
- register_map_control_s.INT_TEST.IRQ <= register_write_data_25_v(3 downto 0); -- Set this field to a value equal to the MSIX interrupt to be fired. The write triggers the interrupt immediately.
- when REG_CONFIG_FLASH_WR => register_map_control_s.CONFIG_FLASH_WR.FAST_WRITE <= register_write_data_25_v(57 downto 57); -- Write command only. Only used for fast programming.
- register_map_control_s.CONFIG_FLASH_WR.FAST_READ <= register_write_data_25_v(56 downto 56); -- Status reading without command writing. Only used for fast programming.
- register_map_control_s.CONFIG_FLASH_WR.PAR_CTRL <= register_write_data_25_v(55 downto 55); -- Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- register_map_control_s.CONFIG_FLASH_WR.PAR_WR <= register_write_data_25_v(54 downto 53); -- Choose Flash partition. Valid when PAR_CTRL is 1.
- register_map_control_s.CONFIG_FLASH_WR.FLASH_SEL <= register_write_data_25_v(52 downto 52); -- 1 takes control over flash, 0 gives JTAG control over flash
- register_map_control_s.CONFIG_FLASH_WR.DO_INIT <= register_write_data_25_v(51 downto 51); -- Untested feature, don't use it yet.
- register_map_control_s.CONFIG_FLASH_WR.DO_READSTATUS <= register_write_data_25_v(50 downto 50); -- Reads status from flash
- register_map_control_s.CONFIG_FLASH_WR.DO_CLEARSTATUS <= register_write_data_25_v(49 downto 49); -- Clears status reading from flash, back to normal flash operation
- register_map_control_s.CONFIG_FLASH_WR.DO_ERASEBLOCK <= register_write_data_25_v(48 downto 48); -- Erased the current block of the flash, this register has to be cleared by software
- register_map_control_s.CONFIG_FLASH_WR.DO_UNLOCK_BLOCK <= register_write_data_25_v(47 downto 47); -- Unlock writes to the current block, this register has to be cleared by software
- register_map_control_s.CONFIG_FLASH_WR.DO_READ <= register_write_data_25_v(46 downto 46); -- Reads the 16 bits from current address, this register has to be cleared by software
- register_map_control_s.CONFIG_FLASH_WR.DO_WRITE <= register_write_data_25_v(45 downto 45); -- Writes the 16 bits to current address, this register has to be cleared by software
- register_map_control_s.CONFIG_FLASH_WR.DO_READDEVICEID <= register_write_data_25_v(44 downto 44); -- DIN should return 0x0089, this register has to be cleared by software
- register_map_control_s.CONFIG_FLASH_WR.DO_RESET <= register_write_data_25_v(43 downto 43); -- Can be used in the future, currently disconnected in firmware
- register_map_control_s.CONFIG_FLASH_WR.ADDRESS <= register_write_data_25_v(42 downto 16); -- Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- register_map_control_s.CONFIG_FLASH_WR.WRITE_DATA <= register_write_data_25_v(15 downto 0); -- Value of data to write towards flash
- when REG_RXUSRCLK_FREQ => register_map_control_s.RXUSRCLK_FREQ.CHANNEL <= register_write_data_25_v(37 downto 32); -- Select the Transceiver channel to measure the clock from.
+ if GBT_GENERATE_ALL_REGS then
+ register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_ODD_EVEN; -- OddEven [47:0]
+ end if;
+ when REG_GBT_TOPBOT =>
+ if GBT_GENERATE_ALL_REGS then
+ register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TOPBOT; -- TopBot [47:0]
+ end if;
+ when REG_GBT_TX_TC_DLY_VALUE1 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TX_TC_DLY_VALUE1; -- TX_TC_DLY_VALUE [47:0]
+ when REG_GBT_TX_TC_DLY_VALUE2 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TX_TC_DLY_VALUE2; -- TX_TC_DLY_VALUE [95:48]
+ when REG_GBT_TX_TC_DLY_VALUE3 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TX_TC_DLY_VALUE3; -- TX_TC_DLY_VALUE [143:96]
+ when REG_GBT_TX_TC_DLY_VALUE4 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TX_TC_DLY_VALUE4; -- TX_TC_DLY_VALUE [191:144]
+ when REG_GBT_DATA_TXFORMAT1 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_DATA_TXFORMAT1; -- DATA_TXFORMAT [47:0]
+ when REG_GBT_DATA_TXFORMAT2 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_DATA_TXFORMAT2; -- DATA_TXFORMAT [95:48]
+ when REG_GBT_DATA_RXFORMAT1 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_DATA_RXFORMAT1; -- DATA_RXFORMAT [47:0]
+ when REG_GBT_DATA_RXFORMAT2 => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_DATA_RXFORMAT2; -- DATA_RXFORMAT [95:0]
+ when REG_GBT_TX_RESET => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TX_RESET; -- TX Logic reset [47:0]
+ when REG_GBT_RX_RESET => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_RX_RESET; -- RX Logic reset [47:0]
+ when REG_GBT_TX_TC_METHOD => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TX_TC_METHOD; -- TX time domain crossing method [47:0]
+ when REG_GBT_OUTMUX_SEL => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_OUTMUX_SEL; -- Descrambler output MUX selection [47:0]
+ when REG_GBT_TC_EDGE => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TC_EDGE; -- Sampling edge selection for TX domain crossing [47:0]
+ when REG_GBT_TXPOLARITY => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TXPOLARITY; -- 0: default polarity
+ -- 1: reversed polarity for transmitter of GTH channels
+
+ when REG_GBT_RXPOLARITY => register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_RXPOLARITY; -- 0: default polarity
+ -- 1: reversed polarity for the receiver of the GTH channels
+
+ when REG_GTH_LOOPBACK_CONTROL => register_read_data_25_s(2 downto 0) <= register_map_control_s.GTH_LOOPBACK_CONTROL; -- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
+ -- 000: Normal operation
+ -- 001: Near-End PCS Loopback
+ -- 010: Near-End PMA Loopback
+ -- 011: Reserved
+ -- 100: Far-End PMA Loopback
+ -- 101: Reserved
+ -- 110: Far-End PCS Loopback
+
+ when REG_GBT_TOHOST_FANOUT => register_read_data_25_s(48 downto 48) <= register_map_control_s.GBT_TOHOST_FANOUT.LOCK; -- Locks this particular register. If set prevents software from touching it.
+ register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TOHOST_FANOUT.SEL; -- ToHost FanOut/Selector. Every bitfield is a channel:
+ -- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
+ -- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
+
+ when REG_GBT_TOFRONTEND_FANOUT => register_read_data_25_s(48 downto 48) <= register_map_control_s.GBT_TOFRONTEND_FANOUT.LOCK; -- Locks this particular register. If set prevents software from touching it.
+ register_read_data_25_s(47 downto 0) <= register_map_control_s.GBT_TOFRONTEND_FANOUT.SEL; -- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
+ -- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
+ -- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
+ --
+
+ when REG_TTC_DEC_CTRL => register_read_data_25_s(30 downto 27) <= register_map_control_s.TTC_DEC_CTRL.L1A_DELAY; -- Number of BC to delay the L1A distribution to the frontends
+ register_read_data_25_s(26 downto 15) <= register_map_control_s.TTC_DEC_CTRL.BCID_ONBCR; -- BCID is set to this value when BCR arrives
+ register_read_data_25_s(14 downto 14) <= register_map_monitor_s.register_map_ttc_monitor.TTC_DEC_CTRL.BUSY_OUTPUT_STATUS; -- Actual status of the BUSY LEMO output signal
+ register_read_data_25_s(13 downto 13) <= register_map_control_s.TTC_DEC_CTRL.ECR_BCR_SWAP; -- ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
+ register_read_data_25_s(12 downto 12) <= register_map_control_s.TTC_DEC_CTRL.BUSY_OUTPUT_INHIBIT; -- forces the Busy LEMO output to BUSY-OFF
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.TTC_DEC_CTRL.TOHOST_RST; -- reset toHost in ttc decoder
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.TTC_DEC_CTRL.TT_BCH_EN; -- trigger type enable / disable for TTC-ToHost
+ register_read_data_25_s(9 downto 2) <= register_map_control_s.TTC_DEC_CTRL.XL1ID_SW; -- set XL1ID value, the value to be set by XL1ID_RST signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.TTC_DEC_CTRL.XL1ID_RST; -- giving a trigger signal to reset XL1ID value
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.TTC_DEC_CTRL.MASTER_BUSY; -- L1A trigger throttling
+ when REG_TTC_EMU => register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_ttc_monitor.TTC_EMU.FULL; -- TTC Emulator memory full indication
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.TTC_EMU.SEL; -- Select TTC data source 1 TTC Emu | 0 TTC Decoder
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.TTC_EMU.ENA; -- Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
+ when REG_TTC_DELAY_00 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_01 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (1); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_02 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (2); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_03 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (3); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_04 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (4); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_05 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (5); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_06 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (6); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_07 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (7); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_08 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (8); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_09 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (9); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_10 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (10); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_11 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (11); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_12 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (12); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_13 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (13); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_14 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (14); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_15 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (15); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_16 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (16); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_17 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (17); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_18 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (18); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_19 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (19); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_20 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (20); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_21 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (21); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_22 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (22); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_23 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (23); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_24 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (24); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_25 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (25); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_26 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (26); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_27 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (27); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_28 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (28); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_29 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (29); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_30 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (30); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_31 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (31); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_32 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (32); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_33 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (33); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_34 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (34); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_35 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (35); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_36 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (36); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_37 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (37); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_38 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (38); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_39 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (39); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_40 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (40); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_41 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (41); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_42 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (42); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_43 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (43); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_44 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (44); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_45 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (45); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_46 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (46); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_47 => register_read_data_25_s(3 downto 0) <= register_map_control_s.TTC_DELAY (47); -- Controls the TTC Fanout delay values
+ when REG_TTC_BUSY_TIMING_CTRL => register_read_data_25_s(51 downto 32) <= register_map_control_s.TTC_BUSY_TIMING_CTRL.PRESCALE; -- Prescales the 40MHz clock to create an internal slow clock
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.TTC_BUSY_TIMING_CTRL.BUSY_WIDTH; -- Minimum number of 40MHz clocks that the busy is asserted
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.TTC_BUSY_TIMING_CTRL.LIMIT_TIME; -- Number of prescaled clocks a given busy must be asserted before it is recognized
+ when REG_TTC_BUSY_CLEAR => register_read_data_25_s(64 downto 64) <= register_map_control_s.TTC_BUSY_CLEAR; -- clears the latching busy bits in TTC_BUSY_ACCEPTED
+ when REG_TTC_EMU_CONTROL => register_read_data_25_s(32 downto 27) <= register_map_control_s.TTC_EMU_CONTROL.BROADCAST; -- Broadcast data
+ register_read_data_25_s(26 downto 26) <= register_map_control_s.TTC_EMU_CONTROL.ECR; -- Event counter reset
+ register_read_data_25_s(25 downto 25) <= register_map_control_s.TTC_EMU_CONTROL.BCR; -- Bunch counter reset
+ register_read_data_25_s(24 downto 24) <= register_map_control_s.TTC_EMU_CONTROL.L1A; -- Level 1 Accept
+ when REG_TTC_EMU_L1A_PERIOD => register_read_data_25_s(31 downto 0) <= register_map_control_s.TTC_EMU_L1A_PERIOD; -- L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
+ when REG_TTC_EMU_ECR_PERIOD => register_read_data_25_s(31 downto 0) <= register_map_control_s.TTC_EMU_ECR_PERIOD; -- ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
+ when REG_TTC_EMU_BCR_PERIOD => register_read_data_25_s(31 downto 0) <= register_map_control_s.TTC_EMU_BCR_PERIOD; -- BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
+ when REG_TTC_EMU_LONG_CHANNEL_DATA => register_read_data_25_s(31 downto 0) <= register_map_control_s.TTC_EMU_LONG_CHANNEL_DATA; -- Long channel data for the TTC emulator
+ when REG_TTC_EMU_RESET => register_read_data_25_s(64 downto 64) <= register_map_control_s.TTC_EMU_RESET; -- Any write to this register resets the TTC Emulator to the default state.
+ when REG_TTC_ECR_MONITOR => register_read_data_25_s(64 downto 64) <= register_map_control_s.TTC_ECR_MONITOR.CLEAR; -- Counts the number of ECRs received from the TTC system, any write to this register clears the counter
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_ECR_MONITOR.VALUE; -- Counts the number of ECRs received from the TTC system, any write to this register clears the counter
+ when REG_TTC_TTYPE_MONITOR => register_read_data_25_s(64 downto 64) <= register_map_control_s.TTC_TTYPE_MONITOR.CLEAR; -- Counts the number of TType received from the TTC system, any write to this register clears the counter
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_TTYPE_MONITOR.VALUE; -- Counts the number of TType received from the TTC system, any write to this register clears the counter
+ when REG_TTC_BCR_PERIODICITY_MONITOR => register_read_data_25_s(64 downto 64) <= register_map_control_s.TTC_BCR_PERIODICITY_MONITOR.CLEAR; -- Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BCR_PERIODICITY_MONITOR.VALUE; -- Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
+ when REG_XOFF_FM_CH_FIFO_THRESH_LOW => register_read_data_25_s(3 downto 0) <= register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW; -- Controls the low threshold of the channel fifo in FULL mode on which
+ -- an Xon will be asserted, bitfields control 4 MSB
+
+ when REG_XOFF_FM_CH_FIFO_THRESH_HIGH => register_read_data_25_s(3 downto 0) <= register_map_control_s.XOFF_FM_CH_FIFO_THRESH_HIGH; -- Controls the high threshold of the channel fifo in FULL mode on which
+ -- an Xoff will be asserted, bitfields control 4 MSB - name: XOFF_FM_LOW_THRESH_CROSSED
+
+ when REG_XOFF_FM_HIGH_THRESH => register_read_data_25_s(64 downto 64) <= register_map_control_s.XOFF_FM_HIGH_THRESH.CLEAR_LATCH; -- Writing this register will clear all CROSS_LATCHED bits
+ register_read_data_25_s(47 downto 24) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_FM_HIGH_THRESH.CROSS_LATCHED; -- FIFO filled beyond the high threshold, 1 latch bit per channel
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_FM_HIGH_THRESH.CROSSED; -- FIFO filled beyond the high threshold, 1 bit per channel
+ when REG_XOFF_FM_SOFT_XOFF => register_read_data_25_s(23 downto 0) <= register_map_control_s.XOFF_FM_SOFT_XOFF; -- Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
+ when REG_XOFF_ENABLE => register_read_data_25_s(23 downto 0) <= register_map_control_s.XOFF_ENABLE; -- Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
+ when REG_DMA_BUSY_STATUS => register_read_data_25_s(64 downto 64) <= register_map_control_s.DMA_BUSY_STATUS.CLEAR_LATCH; -- Any write to this register clears TOHOST_BUSY_LATCHED
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.DMA_BUSY_STATUS.ENABLE; -- Enable the DMA buffer on the server as a source of busy
+ register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_xoff_monitor.DMA_BUSY_STATUS.TOHOST_BUSY_LATCHED; -- A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_xoff_monitor.DMA_BUSY_STATUS.FROMHOST_BUSY_LATCHED; -- A fromhost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_xoff_monitor.DMA_BUSY_STATUS.FROMHOST_BUSY; -- A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.DMA_BUSY_STATUS.TOHOST_BUSY; -- A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
+ when REG_FM_BUSY_CHANNEL_STATUS => register_read_data_25_s(64 downto 64) <= register_map_control_s.FM_BUSY_CHANNEL_STATUS.CLEAR_LATCH; -- Any write to this register will clear the BUSY_LATCHED bits
+ register_read_data_25_s(47 downto 24) <= register_map_monitor_s.register_map_xoff_monitor.FM_BUSY_CHANNEL_STATUS.BUSY_LATCHED; -- one Indicates that the given FULL mode channel has received BUSY-ON
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.FM_BUSY_CHANNEL_STATUS.BUSY; -- one Indicates that the given FULL mode channel is currently in BUSY state
+ when REG_BUSY_MAIN_OUTPUT_FIFO_THRESH => register_read_data_25_s(24 downto 24) <= register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_THRESH.BUSY_ENABLE; -- Enable busy generation if thresholds are crossed
+ register_read_data_25_s(23 downto 12) <= register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_THRESH.LOW; -- Low, Negate threshold of busy generation from main output fifo
+ register_read_data_25_s(11 downto 0) <= register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_THRESH.HIGH; -- High, Assert threshold of busy generation from main output fifo
+ when REG_BUSY_MAIN_OUTPUT_FIFO_STATUS => register_read_data_25_s(64 downto 64) <= register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_STATUS.CLEAR_LATCHED; -- Any write to this register will clear the
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_xoff_monitor.BUSY_MAIN_OUTPUT_FIFO_STATUS.HIGH_THRESH_CROSSED_LATCHED; -- Main output fifo has been full beyond HIGH THRESHOLD, write to clear
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_xoff_monitor.BUSY_MAIN_OUTPUT_FIFO_STATUS.HIGH_THRESH_CROSSED; -- Main output fifo is full beyond HIGH THRESHOLD
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.BUSY_MAIN_OUTPUT_FIFO_STATUS.LOW_THRESH_CROSSED; -- Main output fifo is full beyond LOW THRESHOLD
+ when REG_ELINK_BUSY_ENABLE00 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE01 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (1); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE02 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (2); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE03 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (3); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE04 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (4); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE05 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (5); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE06 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (6); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE07 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (7); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE08 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (8); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE09 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (9); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE10 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (10); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE11 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (11); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE12 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (12); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE13 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (13); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE14 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (14); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE15 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (15); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE16 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (16); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE17 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (17); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE18 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (18); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE19 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (19); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE20 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (20); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE21 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (21); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE22 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (22); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE23 => register_read_data_25_s(56 downto 0) <= register_map_control_s.ELINK_BUSY_ENABLE (23); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_HK_CTRL_I2C => register_read_data_25_s(1 downto 1) <= register_map_control_s.HK_CTRL_I2C.CONFIG_TRIG; -- i2c_config_trig
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.HK_CTRL_I2C.CLKFREQ_SEL; -- i2c_clkfreq_sel
+ when REG_HK_CTRL_FMC => register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_hk_monitor.HK_CTRL_FMC.SI5345_LOL; -- Loss of lock pin, only connected on FLX711
+ register_read_data_25_s(6 downto 5) <= register_map_control_s.HK_CTRL_FMC.SI5345_INSEL; -- Selects the input clock source
+ -- 0 : FPGA (FMC LA01)
+ -- 1 : FMC OSC (40.079 MHz)
+ -- 2 : FPGA (FMC LA18)
+
+ register_read_data_25_s(4 downto 3) <= register_map_control_s.HK_CTRL_FMC.SI5345_A; -- Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.HK_CTRL_FMC.SI5345_OE; -- Si5345 active low output enable (0:enable)
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.HK_CTRL_FMC.SI5345_RSTN; -- Si5345 active low output enable (0:reset)
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.HK_CTRL_FMC.SI5345_SEL; -- Si5345 programming mode
+ -- 1 : I2C mode (default)
+ -- 0 : SPI mode
+
+ when REG_HK_MON_FMC => register_read_data_25_s(1 downto 1) <= register_map_control_s.HK_MON_FMC.SI5345_LOL; -- Si5345 Loss Of Lock pin
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.HK_MON_FMC.SI5345_INTR; -- Si5345 Interrupt flagging chip change of status
+ when REG_MMCM_MAIN => register_read_data_25_s(3 downto 3) <= register_map_control_s.MMCM_MAIN.LCLK_SEL; -- 1: LCLK
+ -- 0: TTC
+
+ register_read_data_25_s(2 downto 1) <= register_map_monitor_s.register_map_hk_monitor.MMCM_MAIN.MAIN_INPUT; -- Main MMCM Oscillator Input
+ -- 2: LCLK fixed
+ -- 1: TTC fixed
+ -- 0: selectable
+
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_hk_monitor.MMCM_MAIN.PLL_LOCK; -- Main MMCM PLL Lock Status
+ when REG_I2C_WR => register_read_data_25_s(64 downto 64) <= register_map_control_s.I2C_WR.I2C_WREN; -- Any write to this register triggers an I2C read or write sequence
+ register_read_data_25_s(25 downto 25) <= register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL; -- I2C FIFO full
+ register_read_data_25_s(24 downto 24) <= register_map_control_s.I2C_WR.WRITE_2BYTES; -- Write two bytes
+ register_read_data_25_s(23 downto 16) <= register_map_control_s.I2C_WR.DATA_BYTE2; -- Data byte 2
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.I2C_WR.DATA_BYTE1; -- Data byte 1
+ register_read_data_25_s(7 downto 1) <= register_map_control_s.I2C_WR.SLAVE_ADDRESS; -- Slave address
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.I2C_WR.READ_NOT_WRITE; -- READ/<o>WRITE</o>
+ when REG_I2C_RD => register_read_data_25_s(64 downto 64) <= register_map_control_s.I2C_RD.I2C_RDEN; -- Any write to this register pops the last I2C data from the FIFO
+ register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY; -- I2C FIFO Empty
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_DOUT; -- I2C READ Data
+ when REG_INT_TEST => register_read_data_25_s(64 downto 64) <= register_map_control_s.INT_TEST.TRIGGER; -- Fire a test MSIx interrupt set in IRQ
+ register_read_data_25_s(3 downto 0) <= register_map_control_s.INT_TEST.IRQ; -- Set this field to a value equal to the MSIX interrupt to be fired. The write triggers the interrupt immediately.
+ when REG_CONFIG_FLASH_WR => register_read_data_25_s(57 downto 57) <= register_map_control_s.CONFIG_FLASH_WR.FAST_WRITE; -- Write command only. Only used for fast programming.
+ register_read_data_25_s(56 downto 56) <= register_map_control_s.CONFIG_FLASH_WR.FAST_READ; -- Status reading without command writing. Only used for fast programming.
+ register_read_data_25_s(55 downto 55) <= register_map_control_s.CONFIG_FLASH_WR.PAR_CTRL; -- Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
+ register_read_data_25_s(54 downto 53) <= register_map_control_s.CONFIG_FLASH_WR.PAR_WR; -- Choose Flash partition. Valid when PAR_CTRL is 1.
+ register_read_data_25_s(52 downto 52) <= register_map_control_s.CONFIG_FLASH_WR.FLASH_SEL; -- 1 takes control over flash, 0 gives JTAG control over flash
+ register_read_data_25_s(51 downto 51) <= register_map_control_s.CONFIG_FLASH_WR.DO_INIT; -- Untested feature, don't use it yet.
+ register_read_data_25_s(50 downto 50) <= register_map_control_s.CONFIG_FLASH_WR.DO_READSTATUS; -- Reads status from flash
+ register_read_data_25_s(49 downto 49) <= register_map_control_s.CONFIG_FLASH_WR.DO_CLEARSTATUS; -- Clears status reading from flash, back to normal flash operation
+ register_read_data_25_s(48 downto 48) <= register_map_control_s.CONFIG_FLASH_WR.DO_ERASEBLOCK; -- Erased the current block of the flash, this register has to be cleared by software
+ register_read_data_25_s(47 downto 47) <= register_map_control_s.CONFIG_FLASH_WR.DO_UNLOCK_BLOCK; -- Unlock writes to the current block, this register has to be cleared by software
+ register_read_data_25_s(46 downto 46) <= register_map_control_s.CONFIG_FLASH_WR.DO_READ; -- Reads the 16 bits from current address, this register has to be cleared by software
+ register_read_data_25_s(45 downto 45) <= register_map_control_s.CONFIG_FLASH_WR.DO_WRITE; -- Writes the 16 bits to current address, this register has to be cleared by software
+ register_read_data_25_s(44 downto 44) <= register_map_control_s.CONFIG_FLASH_WR.DO_READDEVICEID; -- DIN should return 0x0089, this register has to be cleared by software
+ register_read_data_25_s(43 downto 43) <= register_map_control_s.CONFIG_FLASH_WR.DO_RESET; -- Can be used in the future, currently disconnected in firmware
+ register_read_data_25_s(42 downto 16) <= register_map_control_s.CONFIG_FLASH_WR.ADDRESS; -- Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.CONFIG_FLASH_WR.WRITE_DATA; -- Value of data to write towards flash
+ when REG_RXUSRCLK_FREQ => register_read_data_25_s(38 downto 38) <= register_map_monitor_s.register_map_hk_monitor.RXUSRCLK_FREQ.VALID; -- Indicates that the frequency measurement is valid
+ register_read_data_25_s(37 downto 32) <= register_map_control_s.RXUSRCLK_FREQ.CHANNEL; -- Select the Transceiver channel to measure the clock from.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_hk_monitor.RXUSRCLK_FREQ.VAL; -- Frequency in Hz of the selected channel
when REG_FELIG_DATA_GEN_CONFIG_00 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (0).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (0).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (0).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (0).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (0).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (0).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(0).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(0).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(0).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(0).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(0).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(0).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
when REG_FELIG_DATA_GEN_CONFIG_01 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (1).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (1).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (1).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (1).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (1).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (1).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(1).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(1).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(1).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(1).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(1).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(1).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
when REG_FELIG_DATA_GEN_CONFIG_02 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (2).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (2).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (2).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (2).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (2).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (2).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(2).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(2).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(2).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(2).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(2).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(2).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
when REG_FELIG_DATA_GEN_CONFIG_03 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (3).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (3).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (3).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (3).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (3).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (3).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(3).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(3).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(3).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(3).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(3).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(3).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
when REG_FELIG_DATA_GEN_CONFIG_04 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (4).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (4).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (4).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (4).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (4).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (4).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(4).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(4).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(4).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(4).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(4).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(4).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
when REG_FELIG_DATA_GEN_CONFIG_05 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (5).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (5).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (5).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (5).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (5).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (5).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(5).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(5).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(5).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(5).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(5).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(5).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
when REG_FELIG_DATA_GEN_CONFIG_06 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (6).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (6).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (6).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (6).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (6).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (6).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(6).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(6).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(6).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(6).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(6).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(6).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
when REG_FELIG_DATA_GEN_CONFIG_07 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (7).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (7).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (7).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (7).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (7).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (7).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(7).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(7).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(7).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(7).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(7).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(7).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
when REG_FELIG_DATA_GEN_CONFIG_08 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (8).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (8).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (8).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (8).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (8).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (8).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(8).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(8).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(8).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(8).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(8).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(8).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
when REG_FELIG_DATA_GEN_CONFIG_09 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (9).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (9).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (9).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (9).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (9).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (9).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(9).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(9).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(9).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(9).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(9).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(9).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
when REG_FELIG_DATA_GEN_CONFIG_10 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (10).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (10).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (10).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (10).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (10).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (10).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(10).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(10).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(10).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(10).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(10).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(10).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
when REG_FELIG_DATA_GEN_CONFIG_11 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (11).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (11).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (11).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (11).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (11).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (11).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
- end if;
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(11).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(11).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(11).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(11).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(11).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(11).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
when REG_FELIG_DATA_GEN_CONFIG_12 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (12).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (12).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (12).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (12).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (12).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (12).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(12).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(12).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(12).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(12).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(12).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(12).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_13 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(13).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(13).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(13).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(13).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(13).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(13).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_14 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(14).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(14).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(14).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(14).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(14).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(14).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_15 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(15).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(15).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(15).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(15).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(15).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(15).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_16 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(16).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(16).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(16).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(16).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(16).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(16).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_17 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(17).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(17).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(17).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(17).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(17).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(17).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_18 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(18).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(18).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(18).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(18).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(18).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(18).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_19 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(19).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(19).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(19).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(19).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(19).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(19).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_20 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(20).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(20).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(20).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(20).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(20).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(20).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_21 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(21).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(21).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(21).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(21).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(21).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(21).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_22 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(22).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(22).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(22).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(22).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(22).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(22).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_23 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(23).USERDATA; -- Sets static payload word. When PATTERN_SEL=1.
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(23).CHUNK_LENGTH; -- FELIG data generator chunk-length in bytes.
+ register_read_data_25_s(19 downto 15) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(23).RESET; -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_read_data_25_s(14 downto 10) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(23).SW_BUSY; -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_read_data_25_s(9 downto 5) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(23).DATA_FORMAT; -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_read_data_25_s(4 downto 0) <= register_map_control_s.FELIG_DATA_GEN_CONFIG(23).PATTERN_SEL; -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_ELINK_CONFIG_00 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(0).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(0).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(0).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_01 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(1).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(1).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(1).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_02 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(2).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(2).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(2).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_03 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(3).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(3).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(3).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_04 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(4).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(4).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(4).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_05 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(5).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(5).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(5).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_06 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(6).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(6).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(6).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_07 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(7).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(7).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(7).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_08 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(8).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(8).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(8).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_09 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(9).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(9).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(9).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_10 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(10).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(10).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(10).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_11 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(11).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(11).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(11).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_12 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(12).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(12).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(12).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_13 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(13).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(13).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(13).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_14 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(14).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(14).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(14).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_15 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(15).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(15).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(15).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_16 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(16).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(16).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(16).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_17 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(17).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(17).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(17).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_18 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(18).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(18).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(18).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_19 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(19).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(19).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(19).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_20 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(20).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(20).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(20).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_21 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(21).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(21).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(21).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_22 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(22).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(22).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(22).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_23 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 35) <= register_map_control_s.FELIG_ELINK_CONFIG(23).ENDIAN_MOD; -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_ELINK_CONFIG(23).INPUT_WIDTH; -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FELIG_ELINK_CONFIG(23).OUTPUT_WIDTH; -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_00 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_01 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(1); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_02 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(2); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_03 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(3); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_04 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(4); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_05 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(5); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_06 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(6); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_07 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(7); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_08 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(8); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_09 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(9); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_10 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(10); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_11 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(11); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_12 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(12); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_13 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(13); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_14 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(14); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_15 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(15); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_16 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(16); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_17 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(17); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_18 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(18); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_19 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(19); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_20 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(20); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_21 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(21); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_22 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(22); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_ELINK_ENABLE_23 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(39 downto 0) <= register_map_control_s.FELIG_ELINK_ENABLE(23); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ end if;
+ when REG_FELIG_GLOBAL_CONTROL =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 36) <= register_map_control_s.FELIG_GLOBAL_CONTROL.FAKE_L1A_RATE; -- Sets the internal fake L1 trigger rate. [25ns/LSB]
+ register_read_data_25_s(35 downto 14) <= register_map_control_s.FELIG_GLOBAL_CONTROL.PICXO_OFFSET_PPM; -- When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
+ register_read_data_25_s(12 downto 12) <= register_map_control_s.FELIG_GLOBAL_CONTROL.TRACK_DATA; -- FELIG GT core control. Must be set to enable normal operation.
+ register_read_data_25_s(11 downto 11) <= register_map_control_s.FELIG_GLOBAL_CONTROL.RXUSERRDY; -- FELIG GT core control. Must be set to enable normal operation.
+ register_read_data_25_s(10 downto 10) <= register_map_control_s.FELIG_GLOBAL_CONTROL.TXUSERRDY; -- FELIG GT core control. Must be set to enable normal operation.
+ register_read_data_25_s(9 downto 9) <= register_map_control_s.FELIG_GLOBAL_CONTROL.AUTO_RESET; -- FELIG GT core control. If set the GT core automatically resets on data error.
+ register_read_data_25_s(8 downto 8) <= register_map_control_s.FELIG_GLOBAL_CONTROL.PICXO_RESET; -- FELIG GT core control. Manual PICXO reset.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_GLOBAL_CONTROL.GTTX_RESET; -- FELIG GT core control. Manual GT TX reset
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_GLOBAL_CONTROL.CPLL_RESET; -- FELIG GT core control. Manual CPLL reset.
+ register_read_data_25_s(5 downto 0) <= register_map_control_s.FELIG_GLOBAL_CONTROL.X3_X4_OUTPUT_SELECT; -- X3/X4 SMA output source select.
+ end if;
+ when REG_FELIG_LANE_CONFIG_00 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(0).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(0).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(0).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(0).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(0).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(0).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(0).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(0).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(0).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(0).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(0).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_01 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(1).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(1).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(1).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(1).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(1).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(1).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(1).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(1).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(1).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(1).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(1).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_02 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(2).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(2).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(2).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(2).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(2).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(2).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(2).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(2).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(2).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(2).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(2).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_03 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(3).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(3).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(3).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(3).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(3).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(3).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(3).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(3).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(3).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(3).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(3).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_04 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(4).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(4).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(4).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(4).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(4).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(4).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(4).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(4).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(4).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(4).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(4).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_05 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(5).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(5).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(5).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(5).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(5).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(5).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(5).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(5).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(5).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(5).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(5).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_06 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(6).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(6).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(6).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(6).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(6).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(6).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(6).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(6).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(6).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(6).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(6).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_07 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(7).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(7).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(7).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(7).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(7).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(7).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(7).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(7).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(7).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(7).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(7).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_08 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(8).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(8).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(8).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(8).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(8).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(8).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(8).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(8).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(8).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(8).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(8).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_09 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(9).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(9).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(9).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(9).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(9).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(9).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(9).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(9).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(9).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(9).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(9).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_10 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(10).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(10).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(10).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(10).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(10).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(10).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(10).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(10).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(10).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(10).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(10).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_11 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(11).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(11).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(11).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(11).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(11).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(11).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(11).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(11).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(11).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(11).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(11).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_12 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(12).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(12).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(12).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(12).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(12).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(12).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(12).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(12).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(12).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(12).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(12).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_13 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(13).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(13).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(13).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(13).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(13).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(13).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(13).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(13).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(13).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(13).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(13).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_14 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(14).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(14).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(14).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(14).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(14).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(14).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(14).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(14).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(14).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(14).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(14).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_15 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(15).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(15).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(15).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(15).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(15).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(15).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(15).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(15).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(15).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(15).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(15).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_16 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(16).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(16).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(16).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(16).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(16).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(16).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(16).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(16).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(16).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(16).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(16).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_17 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(17).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(17).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(17).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(17).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(17).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(17).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(17).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(17).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(17).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(17).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(17).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_18 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(18).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(18).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(18).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(18).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(18).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(18).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(18).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(18).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(18).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(18).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(18).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_19 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(19).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(19).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(19).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(19).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(19).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(19).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(19).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(19).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(19).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(19).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(19).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_20 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(20).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(20).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(20).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(20).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(20).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(20).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(20).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(20).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(20).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(20).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(20).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_21 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(21).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(21).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(21).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(21).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(21).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(21).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(21).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(21).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(21).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(21).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(21).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_22 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(22).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(22).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(22).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(22).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(22).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(22).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(22).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(22).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(22).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(22).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(22).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_23 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 42) <= register_map_control_s.FELIG_LANE_CONFIG(23).B_CH_BIT_SEL; -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_read_data_25_s(41 downto 35) <= register_map_control_s.FELIG_LANE_CONFIG(23).A_CH_BIT_SEL; -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_read_data_25_s(34 downto 30) <= register_map_control_s.FELIG_LANE_CONFIG(23).LB_FIFO_DELAY; -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_read_data_25_s(7 downto 7) <= register_map_control_s.FELIG_LANE_CONFIG(23).ELINK_SYNC; -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_read_data_25_s(6 downto 6) <= register_map_control_s.FELIG_LANE_CONFIG(23).PICXO_OFFEST_EN; -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_read_data_25_s(5 downto 5) <= register_map_control_s.FELIG_LANE_CONFIG(23).PI_HOLD; -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_read_data_25_s(4 downto 4) <= register_map_control_s.FELIG_LANE_CONFIG(23).GBT_LB_ENABLE; -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.FELIG_LANE_CONFIG(23).GBH_LB_ENABLE; -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.FELIG_LANE_CONFIG(23).L1A_SOURCE; -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.FELIG_LANE_CONFIG(23).GBT_EMU_SOURCE; -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.FELIG_LANE_CONFIG(23).FG_SOURCE; -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_MON_FREQ_GLOBAL =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_control_s.FELIG_MON_FREQ_GLOBAL.XTAL_100MHZ; -- FELIG local oscillator frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_control_s.FELIG_MON_FREQ_GLOBAL.CLK_41_667MHZ; -- FELIG PCIE MGTREFCLK frequency[Hz].
+ end if;
+ when REG_FELIG_RESET =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FELIG_RESET.LB_FIFO; -- One bit per lane. When set to 1, resets all loopback FIFOs.
+ register_read_data_25_s(47 downto 24) <= register_map_control_s.FELIG_RESET.FRAMEGEN; -- One bit per lane. When set to 1, resets all FELIG link checking logic.
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.FELIG_RESET.LANE; -- One bit per lane. When set to 1, resets all FELIG lane logic.
+ end if;
+ when REG_FELIG_RX_SLIDE_RESET =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.FELIG_RX_SLIDE_RESET; -- One bit per lane. When set to 1, resets the gbt rx slide counter.
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_00 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(0).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(0).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_01 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(1).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(1).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_02 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(2).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(2).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_03 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(3).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(3).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_04 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(4).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(4).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_05 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(5).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(5).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_06 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(6).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(6).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_07 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(7).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(7).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_08 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(8).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(8).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_09 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(9).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(9).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_10 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(10).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(10).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_11 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(11).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(11).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_12 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(12).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(12).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_13 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(13).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(13).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_14 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(14).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(14).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_15 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(15).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(15).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_16 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(16).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(16).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_17 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(17).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(17).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_18 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(18).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(18).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_19 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(19).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(19).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_20 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(20).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(20).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_21 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(21).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(21).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_22 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(22).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(22).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_23 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(19 downto 17) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(23).ITKS_FIFO_CTL; -- data fifo control 2:rst 1:rd 0:wr.
+ register_read_data_25_s(16 downto 0) <= register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(23).ITKS_FIFO_DATA; -- itks emu data 16:last word 15-0:data word
+ end if;
+ when REG_FMEMU_EVENT_INFO =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_control_s.FMEMU_EVENT_INFO.L1ID; -- 32b field to show L1ID
+ register_read_data_25_s(31 downto 0) <= register_map_control_s.FMEMU_EVENT_INFO.BCID; -- 32b field to show BCID
+ end if;
+ when REG_FMEMU_COUNTERS =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.FMEMU_COUNTERS.WORD_CNT; -- Number of 32b words in one chunk
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.FMEMU_COUNTERS.IDLE_CNT; -- Minimum number of idles between chunks
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.FMEMU_COUNTERS.L1A_CNT; -- Number of chunks to send if not in TTC mode
+ register_read_data_25_s(15 downto 8) <= register_map_control_s.FMEMU_COUNTERS.BUSY_TH_HIGH; -- Assert BUSY-ON above this threshold
+ register_read_data_25_s(7 downto 0) <= register_map_control_s.FMEMU_COUNTERS.BUSY_TH_LOW; -- De-assert BUSY-ON below this threshold
+ end if;
+ when REG_FMEMU_CONTROL =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 56) <= register_map_control_s.FMEMU_CONTROL.L1A_BITNR; -- Bitfield for L1A in TTC frame
+ register_read_data_25_s(55 downto 48) <= register_map_control_s.FMEMU_CONTROL.XONXOFF_BITNR; -- Bitfield for Xon/Xoff in TTC frame
+ register_read_data_25_s(47 downto 47) <= register_map_control_s.FMEMU_CONTROL.EMU_START; -- Start emulator functionality
+ register_read_data_25_s(46 downto 46) <= register_map_control_s.FMEMU_CONTROL.TTC_MODE; -- Control the emulator by TTC input or by RegMap (1/0)
+ register_read_data_25_s(45 downto 45) <= register_map_control_s.FMEMU_CONTROL.XONXOFF; -- Debug Xon/Xoff functionality (1/0)
+ register_read_data_25_s(44 downto 44) <= register_map_control_s.FMEMU_CONTROL.INLC_CRC32; -- 0: No checksum
+ -- 1: Append the data with a CRC32
+
+ register_read_data_25_s(43 downto 43) <= register_map_control_s.FMEMU_CONTROL.BCR; -- Reset BCID to 0
+ register_read_data_25_s(42 downto 42) <= register_map_control_s.FMEMU_CONTROL.ECR; -- Reset L1ID to 0
+ register_read_data_25_s(41 downto 41) <= register_map_control_s.FMEMU_CONTROL.DATA_SRC_SEL; -- Data source select
+ -- 0: Data input comes from EMURAM
+ -- 1: Data input comes from PCIe
+
+ register_read_data_25_s(40 downto 32) <= register_map_monitor_s.register_map_generators.FMEMU_CONTROL.INT_STATUS_EMU; -- Read internal status emulator
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.FMEMU_CONTROL.FFU_FM_EMU_T; -- For Future Use (trigger registers)
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.FMEMU_CONTROL.FFU_FM_EMU_W; -- For Future Use (write registers)
+ end if;
+ when REG_FMEMU_RANDOM_RAM_ADDR =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FMEMU_RANDOM_RAM_ADDR; -- Controls the address of the ramblock for the random number generator
+ end if;
+ when REG_FMEMU_RANDOM_RAM =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.FMEMU_RANDOM_RAM.WE; -- Any write to this register (DATA) triggers a write to the ramblock
+ register_read_data_25_s(39 downto 16) <= register_map_control_s.FMEMU_RANDOM_RAM.CHANNEL_SELECT; -- Enable write enable only for the selected channel
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.FMEMU_RANDOM_RAM.DATA; -- DATA field to be written to FMEMU_RANDOM_RAM_ADDR
+ end if;
+ when REG_FMEMU_RANDOM_CONTROL =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(20 downto 20) <= register_map_control_s.FMEMU_RANDOM_CONTROL.SELECT_RANDOM; -- 1 enables the random chunk length, 0 uses a constant chunk length
+ register_read_data_25_s(19 downto 10) <= register_map_control_s.FMEMU_RANDOM_CONTROL.SEED; -- Seed for the random number generator, should not be 0
+ register_read_data_25_s(9 downto 0) <= register_map_control_s.FMEMU_RANDOM_CONTROL.POLYNOMIAL; -- POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
+ end if;
+ when REG_WISHBONE_CONTROL => register_read_data_25_s(32 downto 32) <= register_map_control_s.WISHBONE_CONTROL.WRITE_NOT_READ; -- wishbone write command wishbone read command
+ register_read_data_25_s(31 downto 0) <= register_map_control_s.WISHBONE_CONTROL.ADDRESS; -- Slave address for Wishbone bus
+ when REG_WISHBONE_WRITE => register_read_data_25_s(64 downto 64) <= register_map_control_s.WISHBONE_WRITE.WRITE_ENABLE; -- Any write to this register triggers a write to the Wupper to Wishbone fifo
+ register_read_data_25_s(32 downto 32) <= register_map_monitor_s.wishbone_monitor.WISHBONE_WRITE.FULL; -- Wishbone
+ register_read_data_25_s(31 downto 0) <= register_map_control_s.WISHBONE_WRITE.DATA; -- Wishbone
+ when REG_WISHBONE_READ => register_read_data_25_s(64 downto 64) <= register_map_control_s.WISHBONE_READ.READ_ENABLE; -- Any write to this register triggers a read from the Wishbone to Wupper fifo
+ register_read_data_25_s(32 downto 32) <= register_map_monitor_s.wishbone_monitor.WISHBONE_READ.EMPTY; -- Indicates that the Wishbone to Wupper fifo is empty
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.wishbone_monitor.WISHBONE_READ.DATA; -- Wishbone read data
+ when REG_GLOBAL_STRIPS_CONFIG => register_read_data_25_s(15 downto 11) <= register_map_control_s.GLOBAL_STRIPS_CONFIG.TEST_MODULE_MASK; -- (for tests only) contains R3 mask for the simulated trigger data
+ register_read_data_25_s(10 downto 4) <= register_map_control_s.GLOBAL_STRIPS_CONFIG.TEST_R3L1_TAG; -- (for tests only) contains R3 or L1 tag for the simulated trigger data
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.GLOBAL_STRIPS_CONFIG.TTC_GENERATE_GATING_ENABLE; -- Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR. TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work. (See also BC_START, and BC_STOP fields)
+ when REG_GLOBAL_TRICKLE_TRIGGER => register_read_data_25_s(64 downto 64) <= register_map_control_s.GLOBAL_TRICKLE_TRIGGER; -- writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (0)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (0)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (0)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (0)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (0)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (0)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (0)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (0)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (0)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(0)(0); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(0).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(0).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (0)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (0)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (0)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (0)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (0)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (0)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (0)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (0)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (0)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(0)(1); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(1).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(1).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (0)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (0)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (0)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (0)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (0)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (0)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (0)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (0)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (0)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(0)(2); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(2).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(2).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (0)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (0)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (0)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (0)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (0)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (0)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (0)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (0)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (0)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(0)(3); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(3).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(0)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(3).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(0)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(0)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(0)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(0)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_R3L1_LINK_00_R3L1_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (0)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (0)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (0)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_00_R3L1_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (0)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (0)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (0)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_00_R3L1_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (0)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (0)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (0)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_00_R3L1_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (0)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (0)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (0)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (1)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (1)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (1)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (1)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (1)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (1)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (1)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (1)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (1)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(1)(0); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(0).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(0).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (1)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (1)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (1)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (1)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (1)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (1)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (1)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (1)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (1)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(1)(1); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(1).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(1).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (1)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (1)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (1)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (1)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (1)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (1)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (1)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (1)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (1)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(1)(2); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(2).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(2).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (1)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (1)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (1)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (1)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (1)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (1)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (1)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (1)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (1)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(1)(3); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(3).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(1)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(3).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(1)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(1)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(1)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(1)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_R3L1_LINK_01_R3L1_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (1)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (1)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (1)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_01_R3L1_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (1)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (1)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (1)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_01_R3L1_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (1)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (1)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (1)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_01_R3L1_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (1)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (1)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (1)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (2)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (2)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (2)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (2)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (2)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (2)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (2)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (2)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (2)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(2)(0); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(0).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(0).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (2)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (2)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (2)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (2)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (2)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (2)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (2)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (2)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (2)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(2)(1); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(1).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(1).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (2)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (2)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (2)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (2)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (2)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (2)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (2)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (2)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (2)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(2)(2); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(2).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(2).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (2)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (2)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (2)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (2)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (2)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (2)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (2)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (2)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (2)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(2)(3); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(3).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(2)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(3).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(2)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(2)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(2)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(2)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_R3L1_LINK_02_R3L1_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (2)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (2)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (2)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_02_R3L1_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (2)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (2)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (2)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_02_R3L1_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (2)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (2)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (2)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_02_R3L1_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (2)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (2)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (2)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (3)(0).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (3)(0).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (3)(0).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (3)(0).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (3)(0).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (3)(0).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (3)(0).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (3)(0).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (3)(0).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(3)(0); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(0).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(0).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(0).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(0).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(0).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(0).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(0).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(0).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(0).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(0).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(0).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(0).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(0).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(0).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(0).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(0).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(0).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(0).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(0).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(0).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (3)(1).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (3)(1).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (3)(1).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (3)(1).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (3)(1).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (3)(1).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (3)(1).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (3)(1).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (3)(1).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(3)(1); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(1).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(1).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(1).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(1).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(1).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(1).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(1).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(1).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(1).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(1).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(1).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(1).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(1).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(1).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(1).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(1).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(1).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(1).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(1).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(1).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (3)(2).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (3)(2).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (3)(2).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (3)(2).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (3)(2).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (3)(2).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (3)(2).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (3)(2).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (3)(2).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(3)(2); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(2).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(2).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(2).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(2).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(2).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(2).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(2).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(2).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(2).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(2).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(2).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(2).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(2).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(2).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(2).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(2).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(2).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(2).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(2).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(2).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(49 downto 38) <= register_map_control_s.LCB_CTRL (3)(3).L0A_BCR_DELAY; -- TTC BCR signal will be delayed by this many BCs
+ register_read_data_25_s(37 downto 34) <= register_map_control_s.LCB_CTRL (3)(3).L0A_FRAME_DELAY; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+
+ register_read_data_25_s(33 downto 32) <= register_map_control_s.LCB_CTRL (3)(3).FRAME_PHASE; -- phase of LCB frame with respect to TTC BCR signal
+ register_read_data_25_s(31 downto 20) <= register_map_control_s.LCB_CTRL (3)(3).TRICKLE_BC_START; -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(19 downto 8) <= register_map_control_s.LCB_CTRL (3)(3).TRICKLE_BC_STOP; -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_read_data_25_s(5 downto 4) <= register_map_control_s.LCB_CTRL (3)(3).LCB_DESTINATION_MUX; -- Determines where the elink data is sent to:
+ -- 00: command decoder (use same command encoding format as trickle configuration)
+ -- 01: trickle memory (see phase2 documentation for command encoding format)
+ -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ -- 11: (invalid, don't use)
+
+ register_read_data_25_s(3 downto 3) <= register_map_control_s.LCB_CTRL (3)(3).TRICKLE_TRIG_RUN; -- if enabled, trickle configuration is sent out continuously to the front-end
+ -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+
+ register_read_data_25_s(2 downto 2) <= register_map_control_s.LCB_CTRL (3)(3).TTC_L0A_ENABLE; -- enable generating L0A frames in response to TTC system signals
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.LCB_CTRL (3)(3).TTC_GENERATE_GATING_ENABLE; -- enables generating trickle gating signal in response to TTC BCR.
+ -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ -- (See also BC_START, and BC_STOP fields)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.TRICKLE_TRIGGER(3)(3); -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(64 downto 64) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(3).MOVE_WRITE_PTR; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(3).WRITE_PTR; -- Trickle configuration memory write pointer
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(3).VALID_DATA_START; -- Start address of trickle configuration in trickle memory
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_TRICKLE_CONFIG(3)(3).VALID_DATA_END; -- Stop address of trickle configuration in trickle memory (last valid byte)
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(3).HCC_MASK; -- HCC* module mask
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(3).ABC_MASK_HCC_E; -- Masks register commands with destination hcc_id = 0xE
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(3).ABC_MASK_HCC_D; -- Masks register commands with destination hcc_id = 0xD
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.HCC_ABC_MASK_E_C(3)(3).ABC_MASK_HCC_C; -- Masks register commands with destination hcc_id = 0xC
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(3).ABC_MASK_HCC_B; -- Masks register commands with destination hcc_id = 0xB
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(3).ABC_MASK_HCC_A; -- Masks register commands with destination hcc_id = 0xA
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(3).ABC_MASK_HCC_9; -- Masks register commands with destination hcc_id = 0x9
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_B_8(3)(3).ABC_MASK_HCC_8; -- Masks register commands with destination hcc_id = 0x8
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(3).ABC_MASK_HCC_7; -- Masks register commands with destination hcc_id = 0x7
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(3).ABC_MASK_HCC_6; -- Masks register commands with destination hcc_id = 0x6
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(3).ABC_MASK_HCC_5; -- Masks register commands with destination hcc_id = 0x5
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_7_4(3)(3).ABC_MASK_HCC_4; -- Masks register commands with destination hcc_id = 0x4
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(63 downto 48) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(3).ABC_MASK_HCC_3; -- Masks register commands with destination hcc_id = 0x3
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(47 downto 32) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(3).ABC_MASK_HCC_2; -- Masks register commands with destination hcc_id = 0x2
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(31 downto 16) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(3).ABC_MASK_HCC_1; -- Masks register commands with destination hcc_id = 0x1
+ -- mask(i) <=> (abc_id = i)
+
+ register_read_data_25_s(15 downto 0) <= register_map_control_s.LCB_ABC_MASK_3_0(3)(3).ABC_MASK_HCC_0; -- Masks register commands with destination hcc_id = 0x0
+ -- mask(i) <=> (abc_id = i)
+
+ end if;
+ when REG_CR_ITK_R3L1_LINK_03_R3L1_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (3)(0).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (3)(0).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (3)(0).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_03_R3L1_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (3)(1).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (3)(1).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (3)(1).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_03_R3L1_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (3)(2).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (3)(2).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (3)(2).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_03_R3L1_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_read_data_25_s(3 downto 2) <= register_map_control_s.R3L1_CTRL (3)(3).FRAME_PHASE; -- phase of R3L1 frame with respect to TTC BCR signal
+ register_read_data_25_s(1 downto 1) <= register_map_control_s.R3L1_CTRL (3)(3).L1_ENABLE; -- enables sending TTC L1 signals to the front-end
+ register_read_data_25_s(0 downto 0) <= register_map_control_s.R3L1_CTRL (3)(3).R3_ENABLE; -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_STRIPS_R3_TRIGGER => register_read_data_25_s(64 downto 64) <= register_map_control_s.STRIPS_R3_TRIGGER; -- (for tests only) simulate R3 trigger (issues 4-5 sequential triggers)
+ when REG_STRIPS_L1_TRIGGER => register_read_data_25_s(64 downto 64) <= register_map_control_s.STRIPS_L1_TRIGGER; -- (for tests only) simulate L1 trigger (issues 4-5 sequential triggers)
+ when REG_STRIPS_R3L1_TRIGGER => register_read_data_25_s(64 downto 64) <= register_map_control_s.STRIPS_R3L1_TRIGGER; -- (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)
+ when REG_MROD_CTRL =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(15 downto 4) <= register_map_control_s.MROD_CTRL.OPTIONS; -- Extra options for MROD
+ register_read_data_25_s(3 downto 0) <= register_map_control_s.MROD_CTRL.GOLTESTMODE; -- GOL Test Mode (emulate CSM):
+ -- 0: Run Data Emulator when 1; 0: stop, load emulator fifo
+ -- 1: Enable Circulate when 1; 0: send fifo data only once
+ -- 2: Enable Triggered Mode when 1; 0: run continueously (no TTC)
+ -- 3: Enable pattern generator when 1; 0: off
+
+ end if;
+ when REG_MROD_EP0_CSMENABLE =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_CSMENABLE; -- EP0 CSM Data Enable channel 23-0
+ end if;
+ when REG_MROD_EP0_EMPTYSUPPR =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_EMPTYSUPPR; -- EP0 Set Empty Suppression channel 23-0
+ end if;
+ when REG_MROD_EP0_HPTDCMODE =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_HPTDCMODE; -- EP0 Set HPTDC Mode channel 23-0
+ end if;
+ when REG_MROD_EP0_CLRFIFOS =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_CLRFIFOS; -- EP0 Clear FIFOs channel 23-0
+ end if;
+ when REG_MROD_EP0_EMULOADENA =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_EMULOADENA; -- EP0 Emulator Load Enable channel 23-0
+ end if;
+ when REG_MROD_EP0_TRXLOOPBACK =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_TRXLOOPBACK; -- EP0 Transceiver Loopback Enable channel 23-0
+ end if;
+ when REG_MROD_EP0_TXCVRRESET =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_TXCVRRESET; -- EP0 Transceiver Reset all channel 23-0
+ end if;
+ when REG_MROD_EP0_RXRESET =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_RXRESET; -- EP0 Receiver Reset channel 23-0
+ end if;
+ when REG_MROD_EP0_TXRESET =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_TXRESET; -- EP0 Transmitter Reset channel 23-0
+ end if;
+ when REG_MROD_EP1_CSMENABLE =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_CSMENABLE; -- EP1 CSM Data Enable channel 23-0
+ end if;
+ when REG_MROD_EP1_EMPTYSUPPR =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_EMPTYSUPPR; -- EP1 Set Empty Suppression channel 23-0
+ end if;
+ when REG_MROD_EP1_HPTDCMODE =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_HPTDCMODE; -- EP1 Set HPTDC Mode channel 23-0
+ end if;
+ when REG_MROD_EP1_CLRFIFOS =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_CLRFIFOS; -- EP1 Clear FIFOs channel 23-0
+ end if;
+ when REG_MROD_EP1_EMULOADENA =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_EMULOADENA; -- EP1 Emulator Load Enable channel 23-0
+ end if;
+ when REG_MROD_EP1_TRXLOOPBACK =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_TRXLOOPBACK; -- EP1 Transceiver Loopback Enable channel 23-0
+ end if;
+ when REG_MROD_EP1_TXCVRRESET =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_TXCVRRESET; -- EP1 Transceiver Reset all channel 23-0
+ end if;
+ when REG_MROD_EP1_RXRESET =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_RXRESET; -- EP1 Receiver Reset channel 23-0
+ end if;
+ when REG_MROD_EP1_TXRESET =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_TXRESET; -- EP1 Transmitter Reset channel 23-0
+ end if;
+
+ --
+ -- Monitor registers
+ --
+
+
+-- GenericBoardInformation
+ when REG_REG_MAP_VERSION => register_read_data_25_s(15 downto 0) <= std_logic_vector(to_unsigned(1280,16)); -- Register Map Version, 5.0 formatted as 0x0500
+ when REG_BOARD_ID_TIMESTAMP => register_read_data_25_s(39 downto 0) <= BUILD_DATETIME; -- Board ID Date / Time in BCD format YYMMDDhhmm
+ when REG_GIT_COMMIT_TIME => register_read_data_25_s(39 downto 0) <= COMMIT_DATETIME; -- Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
+ when REG_GIT_TAG => register_read_data_25_s(63 downto 0) <= GIT_TAG(63 downto 0); -- String containing the current GIT TAG
+ when REG_GIT_COMMIT_NUMBER => register_read_data_25_s(31 downto 0) <= std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32)); -- Number of GIT commits after current GIT_TAG
+ when REG_GIT_HASH => register_read_data_25_s(31 downto 0) <= GIT_HASH(159 downto 128); -- Short GIT hash (32 bit)
+ when REG_GENERIC_CONSTANTS => register_read_data_25_s(15 downto 8) <= std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8)); -- Number of Interrupts
+ register_read_data_25_s(7 downto 0) <= std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8)); -- Number of Descriptors
+ when REG_NUM_OF_CHANNELS => register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS; -- Number of GBT or FULL mode Channels
+ when REG_CARD_TYPE => register_read_data_25_s(63 downto 0) <= std_logic_vector(to_unsigned(CARD_TYPE,64)); -- Card Type:
+ -- - 709 (0x2c5): FLX709, VC709
+ -- - 710 (0x2c6): FLX710, HTG710
+ -- - 711 (0x2c7): FLX711, BNL711
+ -- - 712 (0x2c8): FLX712, BNL712
+ -- - 128 (0x080): FLX128, VCU128
+
+ when REG_GENERATE_GBT => register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.GENERATE_GBT; -- 1 when the GBT Wrapper is included in the design
+ when REG_OPTO_TRX_NUM => register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_gen_board_info.OPTO_TRX_NUM; -- Number of optical transceivers in the design
+ when REG_GENERATE_TTC_EMU => register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.GENERATE_TTC_EMU; -- 1 when TTC emulator is generated
+ when REG_INCLUDE_EGROUP_0 => register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).FROMHOST_02; -- FromHost EPROC02 is included in this EGROUP
+ register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).FROMHOST_04; -- FromHost EPROC04 is included in this EGROUP
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).FROMHOST_08; -- FromHost EPROC8 is included in this EGROUP
+ register_read_data_25_s(5 downto 5) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).FROMHOST_HDLC; -- FromHost HDLC is included in this EGROUP
+ register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).TOHOST_02; -- ToHost EPROC02 is included in this EGROUP
+ register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).TOHOST_04; -- ToHost EPROC04 is included in this EGROUP
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).TOHOST_08; -- ToHost EPROC08 is included in this EGROUP
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).TOHOST_16; -- ToHost EPROC16 is included in this EGROUP
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (0).TOHOST_HDLC; -- ToHost HDLC is included in this EGROUP
+ when REG_INCLUDE_EGROUP_1 => register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).FROMHOST_02; -- FromHost EPROC02 is included in this EGROUP
+ register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).FROMHOST_04; -- FromHost EPROC04 is included in this EGROUP
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).FROMHOST_08; -- FromHost EPROC8 is included in this EGROUP
+ register_read_data_25_s(5 downto 5) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).FROMHOST_HDLC; -- FromHost HDLC is included in this EGROUP
+ register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).TOHOST_02; -- ToHost EPROC02 is included in this EGROUP
+ register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).TOHOST_04; -- ToHost EPROC04 is included in this EGROUP
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).TOHOST_08; -- ToHost EPROC08 is included in this EGROUP
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).TOHOST_16; -- ToHost EPROC16 is included in this EGROUP
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (1).TOHOST_HDLC; -- ToHost HDLC is included in this EGROUP
+ when REG_INCLUDE_EGROUP_2 => register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).FROMHOST_02; -- FromHost EPROC02 is included in this EGROUP
+ register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).FROMHOST_04; -- FromHost EPROC04 is included in this EGROUP
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).FROMHOST_08; -- FromHost EPROC8 is included in this EGROUP
+ register_read_data_25_s(5 downto 5) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).FROMHOST_HDLC; -- FromHost HDLC is included in this EGROUP
+ register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).TOHOST_02; -- ToHost EPROC02 is included in this EGROUP
+ register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).TOHOST_04; -- ToHost EPROC04 is included in this EGROUP
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).TOHOST_08; -- ToHost EPROC08 is included in this EGROUP
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).TOHOST_16; -- ToHost EPROC16 is included in this EGROUP
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (2).TOHOST_HDLC; -- ToHost HDLC is included in this EGROUP
+ when REG_INCLUDE_EGROUP_3 => register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).FROMHOST_02; -- FromHost EPROC02 is included in this EGROUP
+ register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).FROMHOST_04; -- FromHost EPROC04 is included in this EGROUP
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).FROMHOST_08; -- FromHost EPROC8 is included in this EGROUP
+ register_read_data_25_s(5 downto 5) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).FROMHOST_HDLC; -- FromHost HDLC is included in this EGROUP
+ register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).TOHOST_02; -- ToHost EPROC02 is included in this EGROUP
+ register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).TOHOST_04; -- ToHost EPROC04 is included in this EGROUP
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).TOHOST_08; -- ToHost EPROC08 is included in this EGROUP
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).TOHOST_16; -- ToHost EPROC16 is included in this EGROUP
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (3).TOHOST_HDLC; -- ToHost HDLC is included in this EGROUP
+ when REG_INCLUDE_EGROUP_4 => register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).FROMHOST_02; -- FromHost EPROC02 is included in this EGROUP
+ register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).FROMHOST_04; -- FromHost EPROC04 is included in this EGROUP
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).FROMHOST_08; -- FromHost EPROC8 is included in this EGROUP
+ register_read_data_25_s(5 downto 5) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).FROMHOST_HDLC; -- FromHost HDLC is included in this EGROUP
+ register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).TOHOST_02; -- ToHost EPROC02 is included in this EGROUP
+ register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).TOHOST_04; -- ToHost EPROC04 is included in this EGROUP
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).TOHOST_08; -- ToHost EPROC08 is included in this EGROUP
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).TOHOST_16; -- ToHost EPROC16 is included in this EGROUP
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (4).TOHOST_HDLC; -- ToHost HDLC is included in this EGROUP
+ when REG_INCLUDE_EGROUP_5 => register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).FROMHOST_02; -- FromHost EPROC02 is included in this EGROUP
+ register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).FROMHOST_04; -- FromHost EPROC04 is included in this EGROUP
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).FROMHOST_08; -- FromHost EPROC8 is included in this EGROUP
+ register_read_data_25_s(5 downto 5) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).FROMHOST_HDLC; -- FromHost HDLC is included in this EGROUP
+ register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).TOHOST_02; -- ToHost EPROC02 is included in this EGROUP
+ register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).TOHOST_04; -- ToHost EPROC04 is included in this EGROUP
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).TOHOST_08; -- ToHost EPROC08 is included in this EGROUP
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).TOHOST_16; -- ToHost EPROC16 is included in this EGROUP
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (5).TOHOST_HDLC; -- ToHost HDLC is included in this EGROUP
+ when REG_INCLUDE_EGROUP_6 => register_read_data_25_s(8 downto 8) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).FROMHOST_02; -- FromHost EPROC02 is included in this EGROUP
+ register_read_data_25_s(7 downto 7) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).FROMHOST_04; -- FromHost EPROC04 is included in this EGROUP
+ register_read_data_25_s(6 downto 6) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).FROMHOST_08; -- FromHost EPROC8 is included in this EGROUP
+ register_read_data_25_s(5 downto 5) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).FROMHOST_HDLC; -- FromHost HDLC is included in this EGROUP
+ register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).TOHOST_02; -- ToHost EPROC02 is included in this EGROUP
+ register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).TOHOST_04; -- ToHost EPROC04 is included in this EGROUP
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).TOHOST_08; -- ToHost EPROC08 is included in this EGROUP
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).TOHOST_16; -- ToHost EPROC16 is included in this EGROUP
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.INCLUDE_EGROUP (6).TOHOST_HDLC; -- ToHost HDLC is included in this EGROUP
+ when REG_WIDE_MODE => register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.WIDE_MODE; -- GBT is configured in Wide mode
+ when REG_FIRMWARE_MODE => register_read_data_25_s(3 downto 0) <= register_map_monitor_s.register_map_gen_board_info.FIRMWARE_MODE; -- 0: GBT mode
+ -- 1: FULL mode
+ -- 2: LTDB mode (GBT mode with only IC and TTC links)
+ -- 3: FEI4 mode
+ -- 4: ITK Pixel
+ -- 5: ITK Strip
+ -- 6: FELIG
+ -- 7: FULL mode emulator
+ -- 8: FELIX_MROD mode
+ -- 9: lpGBT mode
+ --
+
+ when REG_GTREFCLK_SOURCE => register_read_data_25_s(1 downto 0) <= register_map_monitor_s.register_map_gen_board_info.GTREFCLK_SOURCE; -- 0: Transceiver reference Clock source from Si5345
+ -- 1: Transceiver reference Clock source from Si5324
+ -- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
+
+ when REG_CR_GENERICS => register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_gen_board_info.CR_GENERICS.XOFF_INCLUDED; -- Xoff bits (usually full mode) can be generated by the FromHost Central Router
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_gen_board_info.CR_GENERICS.DIRECT_MODE_INCLUDED; -- Indicates that the Direct mode functionality was built in the Central Router
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.CR_GENERICS.FROM_HOST_INCLUDED; -- Indicates that the From Host path of the Central router was included in the design
+ when REG_BLOCKSIZE => register_read_data_25_s(15 downto 0) <= register_map_monitor_s.register_map_gen_board_info.BLOCKSIZE; -- Number of bytes in a block
+ when REG_PCIE_ENDPOINT => register_read_data_25_s(0 downto 0) <= std_logic_vector(to_unsigned(PCIE_ENDPOINT, 1)); -- Indicator of the PCIe endpoint on BNL71x cards with two endpoints. 0 or 1
+ when REG_CHUNK_TRAILER_32B => register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_gen_board_info.CHUNK_TRAILER_32B; -- Indicator that the chunk trailer is in the new 32-bit format
+ when REG_PCIE_ENDPOINTS => register_read_data_25_s(1 downto 0) <= register_map_monitor_s.register_map_gen_board_info.PCIE_ENDPOINTS; -- Number of PCIe endpoints on the card. The BNL71x cards have 2 endpoints
+ when REG_SUPERCHUNK_FACTOR => register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_gen_board_info.SUPERCHUNK_FACTOR; -- Number of full mode chunks glued together as one chunk
+
+-- CRToHostControlsAndMonitors
+ when REG_MAX_TIMEOUT => register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_crtohost_monitor.MAX_TIMEOUT; -- Maximum allowed timeout value
+
+-- CRFromHostControlsAndMonitors
+
+-- DecodingControlsAndMonitors
+ when REG_DECODING_LINK_ALIGNED_00 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (0); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_01 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (1); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_02 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (2); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_03 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (3); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_04 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (4); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_05 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (5); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_06 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (6); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_07 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (7); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_08 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (8); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_09 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (9); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_10 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (10); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_11 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (11); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_12 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (12); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_13 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (13); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_14 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (14); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_15 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (15); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_16 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (16); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_17 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (17); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_18 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (18); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_19 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (19); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_20 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (20); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_21 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (21); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_22 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (22); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_DECODING_LINK_ALIGNED_23 => register_read_data_25_s(57 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.DECODING_LINK_ALIGNED (23); -- Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
+ when REG_RD53B_PROCESSOR_00 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (0).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (0).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (0).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (0).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_01 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (1).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (1).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (1).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (1).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_02 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (2).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (2).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (2).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (2).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_03 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (3).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (3).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (3).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (3).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_04 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (4).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (4).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (4).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (4).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_05 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (5).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (5).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (5).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (5).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_06 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (6).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (6).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (6).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (6).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_07 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (7).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (7).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (7).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (7).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_08 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (8).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (8).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (8).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (8).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_09 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (9).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (9).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (9).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (9).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_10 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (10).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (10).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (10).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (10).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_11 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (11).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (11).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (11).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (11).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_12 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (12).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (12).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (12).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (12).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_13 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (13).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (13).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (13).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (13).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_14 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (14).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (14).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (14).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (14).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_15 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (15).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (15).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (15).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (15).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_16 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (16).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (16).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (16).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (16).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_17 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (17).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (17).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (17).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (17).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_18 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (18).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (18).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (18).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (18).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_19 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (19).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (19).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (19).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (19).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_20 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (20).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (20).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (20).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (20).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_21 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (21).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (21).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (21).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (21).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_22 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (22).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (22).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (22).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (22).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_23 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (23).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (23).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (23).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (23).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_24 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (24).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (24).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (24).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (24).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_25 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (25).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (25).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (25).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (25).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_26 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (26).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (26).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (26).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (26).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_27 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (27).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (27).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (27).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (27).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_28 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (28).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (28).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (28).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (28).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_29 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (29).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (29).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (29).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (29).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_30 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (30).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (30).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (30).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (30).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_31 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (31).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (31).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (31).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (31).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_32 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (32).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (32).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (32).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (32).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_33 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (33).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (33).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (33).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (33).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_34 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (34).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (34).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (34).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (34).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_35 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (35).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (35).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (35).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (35).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_36 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (36).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (36).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (36).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (36).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_37 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (37).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (37).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (37).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (37).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_38 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (38).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (38).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (38).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (38).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_39 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (39).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (39).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (39).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (39).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_40 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (40).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (40).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (40).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (40).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_41 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (41).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (41).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (41).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (41).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_42 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (42).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (42).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (42).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (42).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_43 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (43).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (43).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (43).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (43).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_44 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (44).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (44).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (44).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (44).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_45 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (45).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (45).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (45).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (45).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_46 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (46).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (46).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (46).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (46).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_47 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (47).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (47).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (47).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (47).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_48 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (48).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (48).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (48).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (48).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_49 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (49).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (49).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (49).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (49).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_50 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (50).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (50).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (50).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (50).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_51 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (51).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (51).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (51).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (51).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_52 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (52).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (52).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (52).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (52).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_53 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (53).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (53).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (53).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (53).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_54 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (54).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (54).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (54).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (54).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_55 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (55).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (55).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (55).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (55).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_56 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (56).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (56).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (56).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (56).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_57 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (57).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (57).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (57).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (57).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_58 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (58).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (58).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (58).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (58).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_59 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (59).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (59).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (59).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (59).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_60 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (60).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (60).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (60).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (60).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_61 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (61).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (61).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (61).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (61).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_62 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (62).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (62).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (62).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (62).DROP_TOT; -- Decoding block
+ when REG_RD53B_PROCESSOR_63 => register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (63).ENABLE_MULTICHIP; -- Decoding block
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (63).ENABLE_BINARYTREE; -- Decoding block
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (63).ENABLE_TOT; -- Decoding block
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_decoding_monitor.RD53B_PROCESSOR (63).DROP_TOT; -- Decoding block
+
+-- EncodingControlsAndMonitors
+
+-- FrontendEmulatorControlsAndMonitors
+
+-- LinkWrapperMonitors
+ when REG_GBT_VERSION => register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_link_monitor.GBT_VERSION.DATE; -- Date
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_link_monitor.GBT_VERSION.GBT_VERSION; -- GBT Version
+ register_read_data_25_s(31 downto 16) <= register_map_monitor_s.register_map_link_monitor.GBT_VERSION.GTH_IP_VERSION; -- GTH IP Version
+ register_read_data_25_s(15 downto 3) <= register_map_monitor_s.register_map_link_monitor.GBT_VERSION.RESERVED; -- Reserved
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.register_map_link_monitor.GBT_VERSION.GTHREFCLK_SEL; -- GTHREFCLK SEL
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.register_map_link_monitor.GBT_VERSION.RX_CLK_SEL; -- RX CLK SEL
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_VERSION.PLL_SEL; -- PLL SEL
+ when REG_GBT_TXRESET_DONE => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_TXRESET_DONE; -- TX Reset done [47:0]
+ when REG_GBT_RXRESET_DONE => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_RXRESET_DONE; -- RX Reset done [47:0]
+ when REG_GBT_TXFSMRESET_DONE => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_TXFSMRESET_DONE; -- TX FSM Reset done [47:0]
+ when REG_GBT_RXFSMRESET_DONE => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_RXFSMRESET_DONE; -- RX FSM Reset done [47:0]
+ when REG_GBT_CPLL_FBCLK_LOST => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_CPLL_FBCLK_LOST; -- CPLL FBCLK LOST [47:0]
+ when REG_GBT_PLL_LOCK => register_read_data_25_s(59 downto 48) <= register_map_monitor_s.register_map_link_monitor.GBT_PLL_LOCK.QPLL_LOCK; -- QPLL LOCK [11:0]
+ register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_PLL_LOCK.CPLL_LOCK; -- CPLL LOCK [47:0]
+ when REG_GBT_RXCDR_LOCK => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_RXCDR_LOCK; -- RX CDR LOCK [47:0]
+ when REG_GBT_CLK_SAMPLED => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_CLK_SAMPLED; -- clk sampled [47:0]
+ when REG_GBT_RX_IS_HEADER =>
+ if GBT_GENERATE_ALL_REGS then
+ register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_RX_IS_HEADER; -- RX IS HEADER [47:0]
+ end if;
+ when REG_GBT_RX_IS_DATA =>
+ if GBT_GENERATE_ALL_REGS then
+ register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_RX_IS_DATA; -- RX IS DATA [47:0]
+ end if;
+ when REG_GBT_RX_HEADER_FOUND =>
+ if GBT_GENERATE_ALL_REGS then
+ register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_RX_HEADER_FOUND; -- RX HEADER FOUND [47:0]
+ end if;
+ when REG_GBT_ALIGNMENT_DONE => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_ALIGNMENT_DONE; -- RX ALIGNMENT DONE [47:0]
+ when REG_GBT_OUT_MUX_STATUS => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_OUT_MUX_STATUS; -- GBT output mux status [47:0]
+ when REG_GBT_ERROR => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_ERROR; -- Error flags [47:0]
+ when REG_GBT_GBT_TOPBOT_C =>
+ if GBT_GENERATE_ALL_REGS then
+ register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_GBT_TOPBOT_C; -- TopBot_c [47:0]
+ end if;
+ when REG_GBT_FM_RX_DISP_ERROR1 => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_FM_RX_DISP_ERROR1; -- Rx disparity error [47:0]
+ when REG_GBT_FM_RX_DISP_ERROR2 => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_FM_RX_DISP_ERROR2; -- Rx disparity error [96:48]
+ when REG_GBT_FM_RX_NOTINTABLE1 => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_FM_RX_NOTINTABLE1; -- Rx not in table [47:0]
+ when REG_GBT_FM_RX_NOTINTABLE2 => register_read_data_25_s(47 downto 0) <= register_map_monitor_s.register_map_link_monitor.GBT_FM_RX_NOTINTABLE2; -- Rx not in table [96:48]
+
+-- TTCBUSYControlsAndMonitors
+ when REG_TTC_DEC_MON => register_read_data_25_s(15 downto 5) <= register_map_monitor_s.register_map_ttc_monitor.TTC_DEC_MON.TH_FF_COUNT; -- ToHostData Fifo counts
+ register_read_data_25_s(4 downto 4) <= register_map_monitor_s.register_map_ttc_monitor.TTC_DEC_MON.TH_FF_FULL; -- ToHostData Fifo status 1:full 0:not full
+ register_read_data_25_s(3 downto 3) <= register_map_monitor_s.register_map_ttc_monitor.TTC_DEC_MON.TH_FF_EMPTY; -- ToHostData Fifo status 1:empty 0:not empty
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_DEC_MON.TTC_BIT_ERR; -- double bit, single bit and comm error in TTC data
+ when REG_TTC_BUSY_ACCEPTED00 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (0); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED01 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (1); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED02 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (2); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED03 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (3); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED04 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (4); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED05 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (5); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED06 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (6); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED07 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (7); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED08 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (8); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED09 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (9); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED10 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (10); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED11 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (11); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED12 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (12); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED13 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (13); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED14 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (14); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED15 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (15); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED16 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (16); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED17 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (17); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED18 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (18); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED19 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (19); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED20 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (20); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED21 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (21); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED22 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (22); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_BUSY_ACCEPTED23 => register_read_data_25_s(56 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_BUSY_ACCEPTED (23); -- busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ when REG_TTC_L1ID_MONITOR => register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_ttc_monitor.TTC_L1ID_MONITOR; -- Monitor L1ID and XL1ID.
+
+-- XOFF_BUSYControlsAndMonitors
+ when REG_XOFF_FM_LOW_THRESH_CROSSED => register_read_data_25_s(23 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_FM_LOW_THRESH_CROSSED; -- FIFO filled beyond the low threshold, 1 bit per channel
+ when REG_XOFF_PEAK_DURATION00 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (0); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION00 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (0); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT00 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (0); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION01 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (1); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION01 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (1); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT01 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (1); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION02 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (2); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION02 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (2); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT02 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (2); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION03 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (3); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION03 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (3); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT03 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (3); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION04 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (4); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION04 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (4); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT04 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (4); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION05 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (5); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION05 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (5); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT05 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (5); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION06 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (6); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION06 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (6); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT06 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (6); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION07 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (7); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION07 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (7); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT07 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (7); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION08 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (8); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION08 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (8); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT08 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (8); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION09 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (9); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION09 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (9); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT09 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (9); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION10 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (10); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION10 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (10); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT10 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (10); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION11 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (11); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION11 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (11); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT11 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (11); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION12 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (12); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION12 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (12); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT12 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (12); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION13 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (13); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION13 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (13); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT13 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (13); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION14 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (14); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION14 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (14); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT14 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (14); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION15 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (15); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION15 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (15); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT15 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (15); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION16 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (16); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION16 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (16); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT16 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (16); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION17 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (17); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION17 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (17); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT17 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (17); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION18 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (18); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION18 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (18); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT18 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (18); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION19 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (19); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION19 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (19); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT19 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (19); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION20 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (20); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION20 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (20); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT20 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (20); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION21 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (21); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION21 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (21); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT21 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (21); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION22 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (22); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION22 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (22); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT22 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (22); -- Total number of XOFF events per channel that occurred since a reset.
+ when REG_XOFF_PEAK_DURATION23 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_PEAK_DURATION (23); -- Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ when REG_XOFF_TOTAL_DURATION23 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_TOTAL_DURATION (23); -- Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ when REG_XOFF_COUNT23 => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_xoff_monitor.XOFF_COUNT (23); -- Total number of XOFF events per channel that occurred since a reset.
+
+-- HouseKeepingControlsAndMonitors
+ when REG_LMK_LOCKED => register_read_data_25_s(0 downto 0) <= register_map_monitor_s.register_map_hk_monitor.LMK_LOCKED; -- LMK Chip on BNL-711 locked
+ when REG_FPGA_CORE_TEMP => register_read_data_25_s(11 downto 0) <= register_map_monitor_s.register_map_hk_monitor.FPGA_CORE_TEMP; -- XADC temperature monitor for the FPGA CORE
+ -- for FLX709, FLX710
+ -- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
+ -- for FLX711
+ -- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
+
+ when REG_FPGA_CORE_VCCINT => register_read_data_25_s(11 downto 0) <= register_map_monitor_s.register_map_hk_monitor.FPGA_CORE_VCCINT; -- XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
+ when REG_FPGA_CORE_VCCAUX => register_read_data_25_s(11 downto 0) <= register_map_monitor_s.register_map_hk_monitor.FPGA_CORE_VCCAUX; -- XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
+ when REG_FPGA_CORE_VCCBRAM => register_read_data_25_s(11 downto 0) <= register_map_monitor_s.register_map_hk_monitor.FPGA_CORE_VCCBRAM; -- XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
+ when REG_FPGA_DNA => register_read_data_25_s(63 downto 0) <= register_map_monitor_s.register_map_hk_monitor.FPGA_DNA; -- Unique identifier of the FPGA
+ when REG_CONFIG_FLASH_RD => register_read_data_25_s(19 downto 18) <= register_map_monitor_s.register_map_hk_monitor.CONFIG_FLASH_RD.PAR_RD; -- Show which Flash partition is selected.
+ register_read_data_25_s(17 downto 17) <= register_map_monitor_s.register_map_hk_monitor.CONFIG_FLASH_RD.FLASH_REQ_DONE; -- Request done
+ register_read_data_25_s(16 downto 16) <= register_map_monitor_s.register_map_hk_monitor.CONFIG_FLASH_RD.FLASH_BUSY; -- Flash operation busy
+ register_read_data_25_s(15 downto 0) <= register_map_monitor_s.register_map_hk_monitor.CONFIG_FLASH_RD.READ_DATA; -- Value of data read from flash
+ when REG_SI5324_STATUS => register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_hk_monitor.SI5324_STATUS.LOL; -- Loss of Lock Si5324
+ register_read_data_25_s(8 downto 0) <= register_map_monitor_s.register_map_hk_monitor.SI5324_STATUS.LOS; -- Loss of Signal Si5324
+ when REG_TACH_CNT => register_read_data_25_s(19 downto 0) <= register_map_monitor_s.register_map_hk_monitor.TACH_CNT; -- Readout of the Fan tachometer speed of the BNL712 board
+
+-- Generators
+ when REG_FELIG_MON_TTC_0_00 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (0).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (0).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (0).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (0).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (0).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (0).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_01 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (1).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (1).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (1).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (1).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (1).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (1).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_02 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (2).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (2).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (2).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (2).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (2).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (2).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_03 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (3).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (3).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (3).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (3).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (3).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (3).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_04 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (4).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (4).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (4).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (4).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (4).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (4).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_05 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (5).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (5).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (5).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (5).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (5).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (5).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_06 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (6).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (6).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (6).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (6).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (6).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (6).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_07 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (7).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (7).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (7).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (7).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (7).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (7).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_08 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (8).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (8).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (8).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (8).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (8).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (8).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_09 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (9).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (9).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (9).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (9).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (9).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (9).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_10 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (10).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (10).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (10).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (10).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (10).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (10).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_11 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (11).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (11).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (11).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (11).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (11).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (11).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_12 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (12).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (12).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (12).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (12).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (12).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (12).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_13 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (13).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (13).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (13).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (13).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (13).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (13).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_14 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (14).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (14).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (14).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (14).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (14).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (14).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_15 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (15).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (15).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (15).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (15).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (15).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (15).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_16 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (16).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (16).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (16).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (16).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (16).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (16).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_17 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (17).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (17).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (17).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (17).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (17).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (17).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_18 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (18).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (18).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (18).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (18).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (18).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (18).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_19 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (19).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (19).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (19).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (19).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (19).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (19).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_20 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (20).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (20).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (20).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (20).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (20).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (20).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_21 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (21).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (21).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (21).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (21).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (21).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (21).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_22 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (22).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (22).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (22).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (22).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (22).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (22).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_0_23 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 40) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (23).L1ID; -- Live TTC data monitor.
+ register_read_data_25_s(39 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (23).XL1ID; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 20) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (23).BCID; -- Live TTC data monitor.
+ register_read_data_25_s(19 downto 16) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (23).RESERVED0; -- Live TTC data monitor.
+ register_read_data_25_s(15 downto 8) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (23).LEN; -- Live TTC data monitor.
+ register_read_data_25_s(7 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_0 (23).FMT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_00 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (0).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (0).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (0).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_01 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (1).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (1).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (1).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_02 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (2).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (2).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (2).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_03 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (3).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (3).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (3).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_04 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (4).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (4).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (4).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_05 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (5).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (5).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (5).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_06 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (6).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (6).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (6).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_07 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (7).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (7).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (7).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_08 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (8).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (8).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (8).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_09 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (9).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (9).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (9).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_10 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (10).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (10).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (10).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_11 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (11).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (11).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (11).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_12 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (12).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (12).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (12).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_13 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (13).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (13).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (13).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_14 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (14).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (14).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (14).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_15 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (15).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (15).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (15).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_16 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (16).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (16).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (16).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_17 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (17).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (17).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (17).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_18 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (18).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (18).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (18).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_19 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (19).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (19).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (19).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_20 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (20).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (20).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (20).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_21 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (21).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (21).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (21).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_22 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (22).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (22).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (22).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_TTC_1_23 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 48) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (23).RESERVED1; -- Live TTC data monitor.
+ register_read_data_25_s(47 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (23).TRIGGER_TYPE; -- Live TTC data monitor.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_TTC_1 (23).ORBIT; -- Live TTC data monitor.
+ end if;
+ when REG_FELIG_MON_COUNTERS_00 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (0).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (0).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_01 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (1).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (1).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_02 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (2).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (2).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_03 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (3).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (3).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_04 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (4).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (4).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_05 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (5).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (5).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_06 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (6).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (6).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_07 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (7).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (7).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_08 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (8).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (8).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_09 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (9).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (9).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_10 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (10).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (10).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_11 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (11).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (11).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_12 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (12).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (12).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_13 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (13).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (13).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_14 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (14).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (14).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_15 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (15).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (15).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_16 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (16).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (16).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_17 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (17).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (17).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_18 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (18).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (18).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_19 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (19).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (19).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_20 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (20).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (20).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_21 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (21).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (21).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_22 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (22).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (22).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_COUNTERS_23 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (23).SLIDE_COUNT; -- Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_COUNTERS (23).FC_ERROR_COUNT; -- When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+ end if;
+ when REG_FELIG_MON_FREQ_00 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (0).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (0).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_01 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (1).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (1).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_02 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (2).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (2).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_03 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (3).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (3).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_04 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (4).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (4).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_05 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (5).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (5).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_06 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (6).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (6).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_07 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (7).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (7).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_08 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (8).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (8).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_09 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (9).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (9).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_10 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (10).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (10).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_11 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (11).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (11).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_12 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (12).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (12).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_13 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (13).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (13).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_14 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (14).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (14).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_15 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (15).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (15).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_16 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (16).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (16).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_17 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (17).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (17).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_18 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (18).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (18).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_19 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (19).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (19).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_20 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (20).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (20).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_21 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (21).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (21).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_22 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (22).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (22).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_FREQ_23 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(63 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (23).TX; -- FELIG regenerated TX clock frequency[Hz].
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_FREQ (23).RX; -- FELIG recovered RX clock frequency[Hz].
+ end if;
+ when REG_FELIG_MON_L1A_ID_00 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (0); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_01 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (1); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_02 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (2); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_03 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (3); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_04 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (4); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_05 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (5); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_06 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (6); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_07 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (7); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_08 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (8); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_09 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (9); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_10 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (10); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_11 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (11); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_12 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (12); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_13 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (13); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_14 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (14); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_15 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (15); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_16 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (16); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_17 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (17); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_18 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (18); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_19 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (19); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_20 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (20); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_21 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (21); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_22 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (22); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_L1A_ID_23 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(31 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_L1A_ID (23); -- FELIG's last L1 ID.
+ end if;
+ when REG_FELIG_MON_PICXO_00 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (0).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (0).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_01 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (1).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (1).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_02 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (2).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (2).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_03 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (3).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (3).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_04 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (4).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (4).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_05 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (5).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (5).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_06 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (6).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (6).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_07 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (7).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (7).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_08 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (8).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (8).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_09 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (9).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (9).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_10 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (10).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (10).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_11 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (11).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (11).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_12 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (12).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (12).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_13 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (13).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (13).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_14 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (14).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (14).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_15 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (15).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (15).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_16 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (16).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (16).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_17 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (17).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (17).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_18 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (18).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (18).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_19 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (19).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (19).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_20 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (20).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (20).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_21 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (21).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (21).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_22 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (22).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (22).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_PICXO_23 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(53 downto 32) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (23).VLOT; -- Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ register_read_data_25_s(20 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_PICXO (23).ERROR; -- Value indicates RX to TX frequency tracking error.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_00 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (0); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_01 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (1); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_02 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (2); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_03 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (3); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_04 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (4); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_05 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (5); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_06 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (6); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_07 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (7); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_08 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (8); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_09 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (9); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_10 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (10); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_11 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (11); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_12 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (12); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_13 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (13); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_14 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (14); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_15 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (15); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_16 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (16); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_17 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (17); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_18 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (18); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_19 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (19); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_20 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (20); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_21 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (21); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_22 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (22); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+ when REG_FELIG_MON_ITK_STRIPS_23 =>
+ if EMU_GENERATE_REGS then
+ register_read_data_25_s(2 downto 0) <= register_map_monitor_s.register_map_generators.FELIG_MON_ITK_STRIPS (23); -- data fifo status 2:write done 1:full 0:empty.
+ end if;
+
+-- Wishbone
+ when REG_WISHBONE_STATUS => register_read_data_25_s(4 downto 4) <= register_map_monitor_s.wishbone_monitor.WISHBONE_STATUS.INT; -- interrupt
+ register_read_data_25_s(3 downto 3) <= register_map_monitor_s.wishbone_monitor.WISHBONE_STATUS.RETRY; -- Interface is not ready to accept data cycle should be retried
+ register_read_data_25_s(2 downto 2) <= register_map_monitor_s.wishbone_monitor.WISHBONE_STATUS.STALL; -- When pipelined mode slave can't accept additional transactions in its queue
+ register_read_data_25_s(1 downto 1) <= register_map_monitor_s.wishbone_monitor.WISHBONE_STATUS.ACKNOWLEDGE; -- Indicates the termination of a normal bus cycle
+ register_read_data_25_s(0 downto 0) <= register_map_monitor_s.wishbone_monitor.WISHBONE_STATUS.ERROR; -- Address not mapped by the crossbar
+
+-- MRODmonitors
+ when REG_MROD_EP0_CSMH_EMPTY =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_CSMH_EMPTY; -- CSM Handler FIFO Empty 23-0
+ end if;
+ when REG_MROD_EP0_CSMH_FULL =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_CSMH_FULL; -- CSM Handler FIFO Full 23-0
+ end if;
+ when REG_MROD_EP0_RXLOCKED =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_RXLOCKED; -- EP0 Receiver Locked monitor 23-0
+ end if;
+ when REG_MROD_EP0_TXLOCKED =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_TXLOCKED; -- EP0 Transmitter Locked monitor 23-0
+ end if;
+ when REG_MROD_EP1_CSMH_EMPTY =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_CSMH_EMPTY; -- CSM Handler FIFO Empty 23-0
+ end if;
+ when REG_MROD_EP1_CSMH_FULL =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_CSMH_FULL; -- CSM Handler FIFO Full 23-0
+ end if;
+ when REG_MROD_EP1_RXLOCKED =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_RXLOCKED; -- EP1 Receiver Locked monitor 23-0
+ end if;
+ when REG_MROD_EP1_TXLOCKED =>
+ if MROD_GENERATE_REGS = true then
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_TXLOCKED; -- EP1 Transmitter Locked monitor 23-0
+ end if;
+ -----------------------------------
+ ---- GENERATED code END #3 ## ----
+ -----------------------------------
+ when others => register_read_data_25_s <= (others => '0');
+ end case;
+ else --None of BAR0, BAR1 or BAR2 selected
+ register_read_data_25_s <= (others => '0');
+ end if;
+ end if;
+
+ register_write_done_25_s <= '0';
+ if(register_write_enable_25_s = '1') then
+ --! Apply byte enable and word enable to Register writes
+ register_write_data_25_v := register_read_data_25_s;
+
+ case (register_word_address_25_s(3 downto 2)) is
+ when "00" =>
+ case (dword_count_25_s(2 downto 0)) is --write 1 or 2 dwords
+ when "001" =>
+ for i in 0 to 3 loop
+ if first_be_25_s(i) = '1' then
+ register_write_data_25_v(7+i*8 downto i*8) := register_write_data_25_nobe_s(7+i*8 downto i*8);
+ end if;
+ end loop;
+ when "010" =>
+ for i in 0 to 3 loop
+ if first_be_25_s(i) = '1' then
+ register_write_data_25_v(7+i*8 downto i*8) := register_write_data_25_nobe_s(7+i*8 downto i*8);
+ end if;
+ end loop;
+ for i in 0 to 3 loop
+ if last_be_25_s(i) = '1' then
+ register_write_data_25_v(39+i*8 downto 32+i*8) := register_write_data_25_nobe_s(39+i*8 downto 32+i*8);
+ end if;
+ end loop;
+ when others => NULL;
+ end case;
+ when "01" =>
+ for i in 0 to 3 loop
+ if first_be_25_s(i) = '1' then
+ register_write_data_25_v(39+i*8 downto 32+i*8) := register_write_data_25_nobe_s(7+i*8 downto i*8);
+ end if;
+ end loop;
+ when "10" =>
+ case (dword_count_25_s(2 downto 0)) is --write 1 or 2 dwords
+ when "001" =>
+ for i in 0 to 3 loop
+ if first_be_25_s(i) = '1' then
+ register_write_data_25_v(71+i*8 downto 64+i*8) := register_write_data_25_nobe_s(7+i*8 downto i*8);
+ end if;
+ end loop;
+ when "010" =>
+ for i in 0 to 3 loop
+ if first_be_25_s(i) = '1' then
+ register_write_data_25_v(71+i*8 downto 64+i*8) := register_write_data_25_nobe_s(7+i*8 downto i*8);
+ end if;
+ end loop;
+ for i in 0 to 3 loop
+ if last_be_25_s(i) = '1' then
+ register_write_data_25_v(103+i*8 downto 96+i*8) := register_write_data_25_nobe_s(39+i*8 downto 32+i*8);
+ end if;
+ end loop;
+ when others => NULL;
+ end case;
+ when "11" =>
+ for i in 0 to 3 loop
+ if first_be_25_s(i) = '1' then
+ register_write_data_25_v(103+i*8 downto 96+i*8) := register_write_data_25_nobe_s(7+i*8 downto i*8);
+ end if;
+ end loop;
+ when others => NULL;
+ end case;
+
+ --! End byte enable / word enable
+
+
+ register_write_done_25_s <= '1';
+ --Write registers in BAR0
+ if(bar_id_25_s = "000") then
+ register_write_address_v := register_write_address_25_s(19 downto 4)&"0000";
+ case(register_write_address_v) is
+ when REG_DESCRIPTOR_0 => dma_descriptors_25_w_s( 0).end_address <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 0).start_address <= register_write_data_25_v(63 downto 0);
+ when REG_DESCRIPTOR_0a => dma_descriptors_25_w_s( 0).pc_pointer <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 0).wrap_around <= register_write_data_25_v(12);
+ --dma_descriptors_25_w_s( 0).read_not_write <= register_write_data_25_v(11);
+ dma_descriptors_25_w_s( 0).dword_count <= register_write_data_25_v(10 downto 0);
+ when REG_DESCRIPTOR_1 => dma_descriptors_25_w_s( 1).end_address <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 1).start_address <= register_write_data_25_v(63 downto 0);
+ when REG_DESCRIPTOR_1a => dma_descriptors_25_w_s( 1).pc_pointer <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 1).wrap_around <= register_write_data_25_v(12);
+ --dma_descriptors_25_w_s( 1).read_not_write <= register_write_data_25_v(11);
+ dma_descriptors_25_w_s( 1).dword_count <= register_write_data_25_v(10 downto 0);
+ when REG_DESCRIPTOR_2 => dma_descriptors_25_w_s( 2).end_address <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 2).start_address <= register_write_data_25_v(63 downto 0);
+ when REG_DESCRIPTOR_2a => dma_descriptors_25_w_s( 2).pc_pointer <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 2).wrap_around <= register_write_data_25_v(12);
+ --dma_descriptors_25_w_s( 2).read_not_write <= register_write_data_25_v(11);
+ dma_descriptors_25_w_s( 2).dword_count <= register_write_data_25_v(10 downto 0);
+ when REG_DESCRIPTOR_3 => dma_descriptors_25_w_s( 3).end_address <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 3).start_address <= register_write_data_25_v(63 downto 0);
+ when REG_DESCRIPTOR_3a => dma_descriptors_25_w_s( 3).pc_pointer <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 3).wrap_around <= register_write_data_25_v(12);
+ --dma_descriptors_25_w_s( 3).read_not_write <= register_write_data_25_v(11);
+ dma_descriptors_25_w_s( 3).dword_count <= register_write_data_25_v(10 downto 0);
+ when REG_DESCRIPTOR_4 => dma_descriptors_25_w_s( 4).end_address <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 4).start_address <= register_write_data_25_v(63 downto 0);
+ when REG_DESCRIPTOR_4a => dma_descriptors_25_w_s( 4).pc_pointer <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 4).wrap_around <= register_write_data_25_v(12);
+ --dma_descriptors_25_w_s( 4).read_not_write <= register_write_data_25_v(11);
+ dma_descriptors_25_w_s( 4).dword_count <= register_write_data_25_v(10 downto 0);
+ when REG_DESCRIPTOR_5 => dma_descriptors_25_w_s( 5).end_address <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 5).start_address <= register_write_data_25_v(63 downto 0);
+ when REG_DESCRIPTOR_5a => dma_descriptors_25_w_s( 5).pc_pointer <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 5).wrap_around <= register_write_data_25_v(12);
+ --dma_descriptors_25_w_s( 5).read_not_write <= register_write_data_25_v(11);
+ dma_descriptors_25_w_s( 5).dword_count <= register_write_data_25_v(10 downto 0);
+ when REG_DESCRIPTOR_6 => dma_descriptors_25_w_s( 6).end_address <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 6).start_address <= register_write_data_25_v(63 downto 0);
+ when REG_DESCRIPTOR_6a => dma_descriptors_25_w_s( 6).pc_pointer <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 6).wrap_around <= register_write_data_25_v(12);
+ --dma_descriptors_25_w_s( 6).read_not_write <= register_write_data_25_v(11);
+ dma_descriptors_25_w_s( 6).dword_count <= register_write_data_25_v(10 downto 0);
+ when REG_DESCRIPTOR_7 => dma_descriptors_25_w_s( 7).end_address <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 7).start_address <= register_write_data_25_v(63 downto 0);
+ when REG_DESCRIPTOR_7a => dma_descriptors_25_w_s( 7).pc_pointer <= register_write_data_25_v(127 downto 64);
+ dma_descriptors_25_w_s( 7).wrap_around <= register_write_data_25_v(12);
+ --dma_descriptors_25_w_s( 7).read_not_write <= register_write_data_25_v(11);
+ dma_descriptors_25_w_s( 7).dword_count <= register_write_data_25_v(10 downto 0);
+ when REG_DESCRIPTOR_ENABLE => for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
+ dma_descriptors_25_w_s(i).enable <= register_write_data_25_v(i);
+ end loop;
+ dma_descriptors_enable_written_25_s <= '1';
+ when REG_FIFO_FLUSH => flush_fifo_25_s <= '1';
+ when REG_DMA_RESET => dma_soft_reset_25_s <= '1';
+ when REG_SOFT_RESET => reset_global_soft_25_s <= '1';
+ when REG_REGISTER_RESET => reset_register_map_s <= '1';
+ when REG_FROMHOST_FULL_THRESH => fromhost_pfull_threshold_assert_s <= register_write_data_25_v(24 downto 16);
+ fromhost_pfull_threshold_negate_s <= register_write_data_25_v( 8 downto 0);
+ when REG_TOHOST_FULL_THRESH => tohost_pfull_threshold_assert_s <= register_write_data_25_v(27 downto 16);
+ tohost_pfull_threshold_negate_s <= register_write_data_25_v(11 downto 0);
+ when REG_BUSY_THRESH_ASSERT => busy_threshold_assert <= register_write_data_25_v(63 downto 0);
+ when REG_BUSY_THRESH_NEGATE => busy_threshold_negate <= register_write_data_25_v(63 downto 0);
+ when REG_PC_PTR_GAP => pc_ptr_gap_25_s <= register_write_data_25_v(63 downto 0);
+ when others => --do nothing
+
+ end case;
+ --Write registers in BAR1
+ elsif(bar_id_25_s = "001") then
+ register_write_address_v := register_write_address_25_s(19 downto 4)&"0000";
+ case(register_write_address_v) is
+ when REG_INT_VEC_00 => int_vector_25_s(0).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(0).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(0).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_VEC_01 => int_vector_25_s(1).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(1).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(1).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_VEC_02 => int_vector_25_s(2).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(2).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(2).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_VEC_03 => int_vector_25_s(3).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(3).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(3).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_VEC_04 => int_vector_25_s(4).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(4).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(4).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_VEC_05 => int_vector_25_s(5).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(5).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(5).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_VEC_06 => int_vector_25_s(6).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(6).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(6).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_VEC_07 => int_vector_25_s(7).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(7).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(7).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_VEC_08 => int_vector_25_s(8).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(8).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(8).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_VEC_09 => int_vector_25_s(9).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(9).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(9).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_VEC_10 => int_vector_25_s(10).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(10).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(10).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_VEC_11 => int_vector_25_s(11).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(11).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(11).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_VEC_12 => int_vector_25_s(12).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(12).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(12).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_VEC_13 => int_vector_25_s(13).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(13).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(13).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_VEC_14 => int_vector_25_s(14).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(14).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(14).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_VEC_15 => int_vector_25_s(15).int_vec_add <= register_write_data_25_v(63 downto 0);
+ int_vector_25_s(15).int_vec_data <= register_write_data_25_v(95 downto 64);
+ int_vector_25_s(15).int_vec_ctrl <= register_write_data_25_v(127 downto 96);
+ when REG_INT_TAB_EN => int_table_en_s <= register_write_data_25_v(NUMBER_OF_INTERRUPTS-1 downto 0);
+ when others =>
+ end case;
+ --Write registers in BAR2
+ elsif(bar_id_25_s = "010") then
+ register_write_address_v := register_write_address_25_s(19 downto 4)&"0000";
+ case(register_write_address_v) is
+ --!
+ --! generated registers write
+ -------------------------------------
+ ---- ## GENERATED code BEGIN #4 ----
+ -------------------------------------
+ when REG_STATUS_LEDS => register_map_control_s.STATUS_LEDS <= register_write_data_25_v(7 downto 0); -- Board GPIO Leds
+ when REG_TIMEOUT_CTRL => register_map_control_s.TIMEOUT_CTRL.ENABLE <= register_write_data_25_v(32 downto 32); -- 1 enables the timout trailer generation for ToHost mode
+ register_map_control_s.TIMEOUT_CTRL.TIMEOUT <= register_write_data_25_v(31 downto 0); -- Number of 40 MHz clock cycles after which a timeout occurs.
+ when REG_CRTOHOST_FIFO_STATUS => register_map_control_s.CRTOHOST_FIFO_STATUS.CLEAR <= "1"; -- Any write to this register clears the latched FULL flags
+ when REG_CRFROMHOST_FIFO_STATUS => register_map_control_s.CRFROMHOST_FIFO_STATUS.CLEAR <= "1"; -- Any write to this register clears the latched FULL flags
+ when REG_BROADCAST_ENABLE_00 =>
+ if GBT_NUM > 0 then
+ register_map_control_s.BROADCAST_ENABLE (0) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_DATA_GEN_CONFIG_13 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (13).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (13).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (13).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (13).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (13).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (13).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ when REG_BROADCAST_ENABLE_01 =>
+ if GBT_NUM > 1 then
+ register_map_control_s.BROADCAST_ENABLE (1) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_DATA_GEN_CONFIG_14 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (14).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (14).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (14).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (14).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (14).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (14).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ when REG_BROADCAST_ENABLE_02 =>
+ if GBT_NUM > 2 then
+ register_map_control_s.BROADCAST_ENABLE (2) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_DATA_GEN_CONFIG_15 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (15).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (15).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (15).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (15).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (15).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (15).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ when REG_BROADCAST_ENABLE_03 =>
+ if GBT_NUM > 3 then
+ register_map_control_s.BROADCAST_ENABLE (3) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_DATA_GEN_CONFIG_16 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (16).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (16).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (16).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (16).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (16).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (16).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ when REG_BROADCAST_ENABLE_04 =>
+ if GBT_NUM > 4 then
+ register_map_control_s.BROADCAST_ENABLE (4) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_DATA_GEN_CONFIG_17 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (17).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (17).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (17).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (17).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (17).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (17).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ when REG_BROADCAST_ENABLE_05 =>
+ if GBT_NUM > 5 then
+ register_map_control_s.BROADCAST_ENABLE (5) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_DATA_GEN_CONFIG_18 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (18).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (18).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (18).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (18).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (18).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (18).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ when REG_BROADCAST_ENABLE_06 =>
+ if GBT_NUM > 6 then
+ register_map_control_s.BROADCAST_ENABLE (6) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_DATA_GEN_CONFIG_19 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (19).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (19).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (19).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (19).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (19).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (19).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ when REG_BROADCAST_ENABLE_07 =>
+ if GBT_NUM > 7 then
+ register_map_control_s.BROADCAST_ENABLE (7) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_DATA_GEN_CONFIG_20 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (20).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (20).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (20).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (20).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (20).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (20).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ when REG_BROADCAST_ENABLE_08 =>
+ if GBT_NUM > 8 then
+ register_map_control_s.BROADCAST_ENABLE (8) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_DATA_GEN_CONFIG_21 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (21).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (21).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (21).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (21).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (21).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (21).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ when REG_BROADCAST_ENABLE_09 =>
+ if GBT_NUM > 9 then
+ register_map_control_s.BROADCAST_ENABLE (9) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_DATA_GEN_CONFIG_22 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (22).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (22).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (22).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (22).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (22).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (22).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ when REG_BROADCAST_ENABLE_10 =>
+ if GBT_NUM > 10 then
+ register_map_control_s.BROADCAST_ENABLE (10) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_DATA_GEN_CONFIG_23 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_DATA_GEN_CONFIG (23).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (23).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (23).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (23).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (23).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
- register_map_control_s.FELIG_DATA_GEN_CONFIG (23).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ when REG_BROADCAST_ENABLE_11 =>
+ if GBT_NUM > 11 then
+ register_map_control_s.BROADCAST_ENABLE (11) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_ELINK_CONFIG_00 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (0).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (0).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (0).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_BROADCAST_ENABLE_12 =>
+ if GBT_NUM > 12 then
+ register_map_control_s.BROADCAST_ENABLE (12) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_ELINK_CONFIG_01 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (1).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (1).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (1).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_BROADCAST_ENABLE_13 =>
+ if GBT_NUM > 13 then
+ register_map_control_s.BROADCAST_ENABLE (13) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_ELINK_CONFIG_02 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (2).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (2).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (2).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_BROADCAST_ENABLE_14 =>
+ if GBT_NUM > 14 then
+ register_map_control_s.BROADCAST_ENABLE (14) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_ELINK_CONFIG_03 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (3).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (3).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (3).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_BROADCAST_ENABLE_15 =>
+ if GBT_NUM > 15 then
+ register_map_control_s.BROADCAST_ENABLE (15) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_ELINK_CONFIG_04 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (4).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (4).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (4).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_BROADCAST_ENABLE_16 =>
+ if GBT_NUM > 16 then
+ register_map_control_s.BROADCAST_ENABLE (16) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_ELINK_CONFIG_05 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (5).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (5).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (5).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_BROADCAST_ENABLE_17 =>
+ if GBT_NUM > 17 then
+ register_map_control_s.BROADCAST_ENABLE (17) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_ELINK_CONFIG_06 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (6).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (6).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (6).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_BROADCAST_ENABLE_18 =>
+ if GBT_NUM > 18 then
+ register_map_control_s.BROADCAST_ENABLE (18) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_ELINK_CONFIG_07 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (7).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (7).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (7).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_BROADCAST_ENABLE_19 =>
+ if GBT_NUM > 19 then
+ register_map_control_s.BROADCAST_ENABLE (19) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_ELINK_CONFIG_08 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (8).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (8).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (8).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_BROADCAST_ENABLE_20 =>
+ if GBT_NUM > 20 then
+ register_map_control_s.BROADCAST_ENABLE (20) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_ELINK_CONFIG_09 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (9).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (9).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (9).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_BROADCAST_ENABLE_21 =>
+ if GBT_NUM > 21 then
+ register_map_control_s.BROADCAST_ENABLE (21) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_ELINK_CONFIG_10 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (10).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (10).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (10).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_BROADCAST_ENABLE_22 =>
+ if GBT_NUM > 22 then
+ register_map_control_s.BROADCAST_ENABLE (22) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_ELINK_CONFIG_11 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (11).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (11).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (11).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_BROADCAST_ENABLE_23 =>
+ if GBT_NUM > 23 then
+ register_map_control_s.BROADCAST_ENABLE (23) <= register_write_data_25_v(41 downto 0); -- Enable path to be included in a broadcast message.
end if;
- when REG_FELIG_ELINK_CONFIG_12 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (12).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (12).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (12).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_LINK_00_HAS_STREAM_ID =>
+ if GBT_NUM > 0 then
+ register_map_control_s.HAS_STREAM_ID (0).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (0).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (0).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (0).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (0).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (0).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (0).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_CONFIG_13 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (13).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (13).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (13).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_LINK_01_HAS_STREAM_ID =>
+ if GBT_NUM > 1 then
+ register_map_control_s.HAS_STREAM_ID (1).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (1).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (1).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (1).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (1).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (1).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (1).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_CONFIG_14 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (14).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (14).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (14).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_LINK_02_HAS_STREAM_ID =>
+ if GBT_NUM > 2 then
+ register_map_control_s.HAS_STREAM_ID (2).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (2).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (2).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (2).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (2).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (2).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (2).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_CONFIG_15 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (15).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (15).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (15).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_LINK_03_HAS_STREAM_ID =>
+ if GBT_NUM > 3 then
+ register_map_control_s.HAS_STREAM_ID (3).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (3).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (3).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (3).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (3).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (3).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (3).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_CONFIG_16 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (16).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (16).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (16).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_LINK_04_HAS_STREAM_ID =>
+ if GBT_NUM > 4 then
+ register_map_control_s.HAS_STREAM_ID (4).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (4).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (4).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (4).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (4).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (4).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (4).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_CONFIG_17 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (17).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (17).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (17).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_LINK_05_HAS_STREAM_ID =>
+ if GBT_NUM > 5 then
+ register_map_control_s.HAS_STREAM_ID (5).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (5).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (5).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (5).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (5).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (5).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (5).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_CONFIG_18 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (18).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (18).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (18).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_LINK_06_HAS_STREAM_ID =>
+ if GBT_NUM > 6 then
+ register_map_control_s.HAS_STREAM_ID (6).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (6).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (6).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (6).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (6).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (6).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (6).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_CONFIG_19 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (19).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (19).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (19).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_LINK_07_HAS_STREAM_ID =>
+ if GBT_NUM > 7 then
+ register_map_control_s.HAS_STREAM_ID (7).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (7).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (7).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (7).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (7).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (7).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (7).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_CONFIG_20 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (20).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (20).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (20).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_LINK_08_HAS_STREAM_ID =>
+ if GBT_NUM > 8 then
+ register_map_control_s.HAS_STREAM_ID (8).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (8).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (8).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (8).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (8).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (8).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (8).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_CONFIG_21 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (21).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (21).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (21).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_LINK_09_HAS_STREAM_ID =>
+ if GBT_NUM > 9 then
+ register_map_control_s.HAS_STREAM_ID (9).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (9).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (9).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (9).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (9).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (9).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (9).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_CONFIG_22 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (22).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (22).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (22).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_LINK_10_HAS_STREAM_ID =>
+ if GBT_NUM > 10 then
+ register_map_control_s.HAS_STREAM_ID (10).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (10).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (10).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (10).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (10).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (10).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (10).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_CONFIG_23 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_CONFIG (23).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- register_map_control_s.FELIG_ELINK_CONFIG (23).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- register_map_control_s.FELIG_ELINK_CONFIG (23).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ when REG_LINK_11_HAS_STREAM_ID =>
+ if GBT_NUM > 11 then
+ register_map_control_s.HAS_STREAM_ID (11).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (11).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (11).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (11).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (11).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (11).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (11).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_ENABLE_00 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (0) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_LINK_12_HAS_STREAM_ID =>
+ if GBT_NUM > 12 then
+ register_map_control_s.HAS_STREAM_ID (12).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (12).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (12).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (12).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (12).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (12).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (12).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_ENABLE_01 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (1) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_LINK_13_HAS_STREAM_ID =>
+ if GBT_NUM > 13 then
+ register_map_control_s.HAS_STREAM_ID (13).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (13).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (13).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (13).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (13).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (13).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (13).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_ENABLE_02 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (2) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_LINK_14_HAS_STREAM_ID =>
+ if GBT_NUM > 14 then
+ register_map_control_s.HAS_STREAM_ID (14).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (14).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (14).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (14).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (14).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (14).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (14).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_ENABLE_03 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (3) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_LINK_15_HAS_STREAM_ID =>
+ if GBT_NUM > 15 then
+ register_map_control_s.HAS_STREAM_ID (15).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (15).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (15).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (15).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (15).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (15).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (15).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_ENABLE_04 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (4) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_LINK_16_HAS_STREAM_ID =>
+ if GBT_NUM > 16 then
+ register_map_control_s.HAS_STREAM_ID (16).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (16).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (16).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (16).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (16).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (16).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (16).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_ENABLE_05 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (5) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_LINK_17_HAS_STREAM_ID =>
+ if GBT_NUM > 17 then
+ register_map_control_s.HAS_STREAM_ID (17).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (17).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (17).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (17).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (17).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (17).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (17).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_ENABLE_06 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (6) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_LINK_18_HAS_STREAM_ID =>
+ if GBT_NUM > 18 then
+ register_map_control_s.HAS_STREAM_ID (18).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (18).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (18).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (18).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (18).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (18).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (18).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_ENABLE_07 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (7) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_LINK_19_HAS_STREAM_ID =>
+ if GBT_NUM > 19 then
+ register_map_control_s.HAS_STREAM_ID (19).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (19).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (19).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (19).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (19).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (19).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (19).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_ENABLE_08 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (8) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_LINK_20_HAS_STREAM_ID =>
+ if GBT_NUM > 20 then
+ register_map_control_s.HAS_STREAM_ID (20).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (20).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (20).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (20).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (20).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (20).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (20).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_ENABLE_09 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (9) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_LINK_21_HAS_STREAM_ID =>
+ if GBT_NUM > 21 then
+ register_map_control_s.HAS_STREAM_ID (21).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (21).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (21).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (21).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (21).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (21).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (21).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_ENABLE_10 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (10) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_LINK_22_HAS_STREAM_ID =>
+ if GBT_NUM > 22 then
+ register_map_control_s.HAS_STREAM_ID (22).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (22).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (22).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (22).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (22).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (22).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (22).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_ENABLE_11 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (11) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_LINK_23_HAS_STREAM_ID =>
+ if GBT_NUM > 23 then
+ register_map_control_s.HAS_STREAM_ID (23).EGROUP6 <= register_write_data_25_v(55 downto 48); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (23).EGROUP5 <= register_write_data_25_v(47 downto 40); -- EPATH (Wide mode or lpGBT) is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (23).EGROUP4 <= register_write_data_25_v(39 downto 32); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (23).EGROUP3 <= register_write_data_25_v(31 downto 24); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (23).EGROUP2 <= register_write_data_25_v(23 downto 16); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (23).EGROUP1 <= register_write_data_25_v(15 downto 8); -- EPATH is associated with a STREAM ID
+ register_map_control_s.HAS_STREAM_ID (23).EGROUP0 <= register_write_data_25_v(7 downto 0); -- EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
end if;
- when REG_FELIG_ELINK_ENABLE_12 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (12) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_DECODING_LINK00_EGROUP0_CTRL =>
+ if GBT_NUM > 0 then
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ELINK_ENABLE_13 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (13) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_DECODING_LINK00_EGROUP1_CTRL =>
+ if GBT_NUM > 0 then
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ELINK_ENABLE_14 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (14) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_DECODING_LINK00_EGROUP2_CTRL =>
+ if GBT_NUM > 0 then
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ELINK_ENABLE_15 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (15) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_DECODING_LINK00_EGROUP3_CTRL =>
+ if GBT_NUM > 0 then
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ELINK_ENABLE_16 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (16) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_DECODING_LINK00_EGROUP4_CTRL =>
+ if GBT_NUM > 0 then
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ELINK_ENABLE_17 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (17) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_DECODING_LINK00_EGROUP5_CTRL =>
+ if GBT_NUM > 0 then
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ELINK_ENABLE_18 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (18) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_DECODING_LINK00_EGROUP6_CTRL =>
+ if GBT_NUM > 0 then
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (0)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ELINK_ENABLE_19 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (19) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_DECODING_LINK01_EGROUP0_CTRL =>
+ if GBT_NUM > 1 then
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ELINK_ENABLE_20 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (20) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_DECODING_LINK01_EGROUP1_CTRL =>
+ if GBT_NUM > 1 then
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ELINK_ENABLE_21 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (21) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_DECODING_LINK01_EGROUP2_CTRL =>
+ if GBT_NUM > 1 then
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ELINK_ENABLE_22 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (22) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_DECODING_LINK01_EGROUP3_CTRL =>
+ if GBT_NUM > 1 then
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ELINK_ENABLE_23 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ELINK_ENABLE (23) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+ when REG_DECODING_LINK01_EGROUP4_CTRL =>
+ if GBT_NUM > 1 then
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_GLOBAL_CONTROL =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_GLOBAL_CONTROL.FAKE_L1A_RATE <= register_write_data_25_v(63 downto 36); -- Sets the internal fake L1 trigger rate. [25ns/LSB]
- register_map_control_s.FELIG_GLOBAL_CONTROL.PICXO_OFFSET_PPM <= register_write_data_25_v(35 downto 14); -- When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
- register_map_control_s.FELIG_GLOBAL_CONTROL.TRACK_DATA <= register_write_data_25_v(12 downto 12); -- FELIG GT core control. Must be set to enable normal operation.
- register_map_control_s.FELIG_GLOBAL_CONTROL.RXUSERRDY <= register_write_data_25_v(11 downto 11); -- FELIG GT core control. Must be set to enable normal operation.
- register_map_control_s.FELIG_GLOBAL_CONTROL.TXUSERRDY <= register_write_data_25_v(10 downto 10); -- FELIG GT core control. Must be set to enable normal operation.
- register_map_control_s.FELIG_GLOBAL_CONTROL.AUTO_RESET <= register_write_data_25_v(9 downto 9); -- FELIG GT core control. If set the GT core automatically resets on data error.
- register_map_control_s.FELIG_GLOBAL_CONTROL.PICXO_RESET <= register_write_data_25_v(8 downto 8); -- FELIG GT core control. Manual PICXO reset.
- register_map_control_s.FELIG_GLOBAL_CONTROL.GTTX_RESET <= register_write_data_25_v(7 downto 7); -- FELIG GT core control. Manual GT TX reset
- register_map_control_s.FELIG_GLOBAL_CONTROL.CPLL_RESET <= register_write_data_25_v(6 downto 6); -- FELIG GT core control. Manual CPLL reset.
- register_map_control_s.FELIG_GLOBAL_CONTROL.X3_X4_OUTPUT_SELECT <= register_write_data_25_v(5 downto 0); -- X3/X4 SMA output source select.
+ when REG_DECODING_LINK01_EGROUP5_CTRL =>
+ if GBT_NUM > 1 then
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_00 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (0).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (0).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (0).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (0).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (0).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (0).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (0).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (0).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (0).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (0).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (0).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK01_EGROUP6_CTRL =>
+ if GBT_NUM > 1 then
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (1)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_01 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (1).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (1).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (1).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (1).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (1).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (1).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (1).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (1).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (1).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (1).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (1).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK02_EGROUP0_CTRL =>
+ if GBT_NUM > 2 then
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_02 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (2).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (2).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (2).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (2).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (2).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (2).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (2).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (2).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (2).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (2).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (2).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK02_EGROUP1_CTRL =>
+ if GBT_NUM > 2 then
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_03 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (3).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (3).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (3).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (3).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (3).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (3).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (3).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (3).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (3).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (3).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (3).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK02_EGROUP2_CTRL =>
+ if GBT_NUM > 2 then
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_04 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (4).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (4).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (4).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (4).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (4).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (4).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (4).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (4).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (4).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (4).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (4).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK02_EGROUP3_CTRL =>
+ if GBT_NUM > 2 then
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_05 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (5).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (5).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (5).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (5).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (5).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (5).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (5).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (5).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (5).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (5).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (5).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK02_EGROUP4_CTRL =>
+ if GBT_NUM > 2 then
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_06 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (6).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (6).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (6).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (6).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (6).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (6).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (6).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (6).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (6).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (6).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (6).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK02_EGROUP5_CTRL =>
+ if GBT_NUM > 2 then
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_07 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (7).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (7).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (7).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (7).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (7).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (7).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (7).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (7).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (7).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (7).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (7).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK02_EGROUP6_CTRL =>
+ if GBT_NUM > 2 then
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (2)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_08 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (8).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (8).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (8).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (8).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (8).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (8).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (8).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (8).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (8).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (8).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (8).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK03_EGROUP0_CTRL =>
+ if GBT_NUM > 3 then
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_09 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (9).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (9).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (9).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (9).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (9).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (9).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (9).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (9).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (9).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (9).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (9).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK03_EGROUP1_CTRL =>
+ if GBT_NUM > 3 then
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_10 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (10).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (10).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (10).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (10).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (10).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (10).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (10).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (10).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (10).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (10).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (10).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK03_EGROUP2_CTRL =>
+ if GBT_NUM > 3 then
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_11 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (11).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (11).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (11).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (11).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (11).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (11).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (11).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (11).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (11).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (11).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (11).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK03_EGROUP3_CTRL =>
+ if GBT_NUM > 3 then
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_12 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (12).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (12).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (12).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (12).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (12).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (12).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (12).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (12).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (12).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (12).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (12).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK03_EGROUP4_CTRL =>
+ if GBT_NUM > 3 then
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_13 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (13).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (13).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (13).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (13).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (13).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (13).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (13).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (13).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (13).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (13).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (13).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK03_EGROUP5_CTRL =>
+ if GBT_NUM > 3 then
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_14 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (14).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (14).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (14).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (14).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (14).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (14).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (14).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (14).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (14).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (14).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (14).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK03_EGROUP6_CTRL =>
+ if GBT_NUM > 3 then
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (3)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_15 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (15).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (15).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (15).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (15).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (15).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (15).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (15).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (15).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (15).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (15).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (15).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK04_EGROUP0_CTRL =>
+ if GBT_NUM > 4 then
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_16 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (16).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (16).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (16).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (16).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (16).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (16).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (16).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (16).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (16).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (16).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (16).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK04_EGROUP1_CTRL =>
+ if GBT_NUM > 4 then
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_17 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (17).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (17).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (17).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (17).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (17).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (17).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (17).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (17).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (17).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (17).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (17).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK04_EGROUP2_CTRL =>
+ if GBT_NUM > 4 then
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_18 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (18).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (18).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (18).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (18).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (18).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (18).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (18).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (18).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (18).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (18).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (18).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK04_EGROUP3_CTRL =>
+ if GBT_NUM > 4 then
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_19 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (19).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (19).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (19).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (19).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (19).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (19).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (19).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (19).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (19).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (19).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (19).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK04_EGROUP4_CTRL =>
+ if GBT_NUM > 4 then
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_20 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (20).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (20).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (20).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (20).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (20).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (20).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (20).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (20).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (20).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (20).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (20).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK04_EGROUP5_CTRL =>
+ if GBT_NUM > 4 then
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_21 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (21).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (21).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (21).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (21).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (21).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (21).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (21).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (21).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (21).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (21).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (21).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK04_EGROUP6_CTRL =>
+ if GBT_NUM > 4 then
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (4)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_22 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (22).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (22).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (22).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (22).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (22).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (22).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (22).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (22).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (22).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (22).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (22).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK05_EGROUP0_CTRL =>
+ if GBT_NUM > 5 then
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_LANE_CONFIG_23 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_LANE_CONFIG (23).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- register_map_control_s.FELIG_LANE_CONFIG (23).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
- register_map_control_s.FELIG_LANE_CONFIG (23).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- register_map_control_s.FELIG_LANE_CONFIG (23).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- register_map_control_s.FELIG_LANE_CONFIG (23).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- register_map_control_s.FELIG_LANE_CONFIG (23).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- register_map_control_s.FELIG_LANE_CONFIG (23).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (23).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- register_map_control_s.FELIG_LANE_CONFIG (23).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- register_map_control_s.FELIG_LANE_CONFIG (23).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- register_map_control_s.FELIG_LANE_CONFIG (23).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ when REG_DECODING_LINK05_EGROUP1_CTRL =>
+ if GBT_NUM > 5 then
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_MON_FREQ_GLOBAL =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_MON_FREQ_GLOBAL.XTAL_100MHZ <= register_write_data_25_v(63 downto 32); -- FELIG local oscillator frequency[Hz].
- register_map_control_s.FELIG_MON_FREQ_GLOBAL.CLK_41_667MHZ <= register_write_data_25_v(31 downto 0); -- FELIG PCIE MGTREFCLK frequency[Hz].
+ when REG_DECODING_LINK05_EGROUP2_CTRL =>
+ if GBT_NUM > 5 then
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_RESET =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_RESET.LB_FIFO <= register_write_data_25_v(63 downto 48); -- One bit per lane. When set to 1, resets all loopback FIFOs.
- register_map_control_s.FELIG_RESET.FRAMEGEN <= register_write_data_25_v(47 downto 24); -- One bit per lane. When set to 1, resets all FELIG link checking logic.
- register_map_control_s.FELIG_RESET.LANE <= register_write_data_25_v(23 downto 0); -- One bit per lane. When set to 1, resets all FELIG lane logic.
+ when REG_DECODING_LINK05_EGROUP3_CTRL =>
+ if GBT_NUM > 5 then
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_RX_SLIDE_RESET =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_RX_SLIDE_RESET <= register_write_data_25_v(23 downto 0); -- One bit per lane. When set to 1, resets the gbt rx slide counter.
+ when REG_DECODING_LINK05_EGROUP4_CTRL =>
+ if GBT_NUM > 5 then
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_00 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(0).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(0).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK05_EGROUP5_CTRL =>
+ if GBT_NUM > 5 then
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_01 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(1).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(1).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK05_EGROUP6_CTRL =>
+ if GBT_NUM > 5 then
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (5)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_02 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(2).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(2).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK06_EGROUP0_CTRL =>
+ if GBT_NUM > 6 then
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_03 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(3).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(3).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK06_EGROUP1_CTRL =>
+ if GBT_NUM > 6 then
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_04 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(4).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(4).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK06_EGROUP2_CTRL =>
+ if GBT_NUM > 6 then
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_05 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(5).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(5).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK06_EGROUP3_CTRL =>
+ if GBT_NUM > 6 then
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_06 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(6).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(6).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK06_EGROUP4_CTRL =>
+ if GBT_NUM > 6 then
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_07 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(7).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(7).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK06_EGROUP5_CTRL =>
+ if GBT_NUM > 6 then
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_08 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(8).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(8).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK06_EGROUP6_CTRL =>
+ if GBT_NUM > 6 then
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (6)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_09 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(9).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(9).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK07_EGROUP0_CTRL =>
+ if GBT_NUM > 7 then
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_10 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(10).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(10).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK07_EGROUP1_CTRL =>
+ if GBT_NUM > 7 then
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_11 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(11).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(11).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK07_EGROUP2_CTRL =>
+ if GBT_NUM > 7 then
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_12 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(12).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(12).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK07_EGROUP3_CTRL =>
+ if GBT_NUM > 7 then
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_13 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(13).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(13).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK07_EGROUP4_CTRL =>
+ if GBT_NUM > 7 then
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_14 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(14).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(14).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK07_EGROUP5_CTRL =>
+ if GBT_NUM > 7 then
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_15 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(15).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(15).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK07_EGROUP6_CTRL =>
+ if GBT_NUM > 7 then
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (7)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_16 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(16).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(16).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK08_EGROUP0_CTRL =>
+ if GBT_NUM > 8 then
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_17 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(17).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(17).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK08_EGROUP1_CTRL =>
+ if GBT_NUM > 8 then
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_18 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(18).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(18).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK08_EGROUP2_CTRL =>
+ if GBT_NUM > 8 then
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_19 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(19).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(19).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK08_EGROUP3_CTRL =>
+ if GBT_NUM > 8 then
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_20 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(20).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(20).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK08_EGROUP4_CTRL =>
+ if GBT_NUM > 8 then
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_21 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(21).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(21).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK08_EGROUP5_CTRL =>
+ if GBT_NUM > 8 then
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_22 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(22).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(22).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK08_EGROUP6_CTRL =>
+ if GBT_NUM > 8 then
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (8)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_23 =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(23).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
- register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(23).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
+ when REG_DECODING_LINK09_EGROUP0_CTRL =>
+ if GBT_NUM > 9 then
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FMEMU_EVENT_INFO =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FMEMU_EVENT_INFO.L1ID <= register_write_data_25_v(63 downto 32); -- 32b field to show L1ID
- register_map_control_s.FMEMU_EVENT_INFO.BCID <= register_write_data_25_v(31 downto 0); -- 32b field to show BCID
+ when REG_DECODING_LINK09_EGROUP1_CTRL =>
+ if GBT_NUM > 9 then
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FMEMU_COUNTERS =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FMEMU_COUNTERS.WORD_CNT <= register_write_data_25_v(63 downto 48); -- Number of 32b words in one chunk
- register_map_control_s.FMEMU_COUNTERS.IDLE_CNT <= register_write_data_25_v(47 downto 32); -- Minimum number of idles between chunks
- register_map_control_s.FMEMU_COUNTERS.L1A_CNT <= register_write_data_25_v(31 downto 16); -- Number of chunks to send if not in TTC mode
- register_map_control_s.FMEMU_COUNTERS.BUSY_TH_HIGH <= register_write_data_25_v(15 downto 8); -- Assert BUSY-ON above this threshold
- register_map_control_s.FMEMU_COUNTERS.BUSY_TH_LOW <= register_write_data_25_v(7 downto 0); -- De-assert BUSY-ON below this threshold
+ when REG_DECODING_LINK09_EGROUP2_CTRL =>
+ if GBT_NUM > 9 then
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FMEMU_CONTROL =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FMEMU_CONTROL.L1A_BITNR <= register_write_data_25_v(63 downto 56); -- Bitfield for L1A in TTC frame
- register_map_control_s.FMEMU_CONTROL.XONXOFF_BITNR <= register_write_data_25_v(55 downto 48); -- Bitfield for Xon/Xoff in TTC frame
- register_map_control_s.FMEMU_CONTROL.EMU_START <= register_write_data_25_v(47 downto 47); -- Start emulator functionality
- register_map_control_s.FMEMU_CONTROL.TTC_MODE <= register_write_data_25_v(46 downto 46); -- Control the emulator by TTC input or by RegMap (1/0)
- register_map_control_s.FMEMU_CONTROL.XONXOFF <= register_write_data_25_v(45 downto 45); -- Debug Xon/Xoff functionality (1/0)
- register_map_control_s.FMEMU_CONTROL.INLC_CRC32 <= register_write_data_25_v(44 downto 44); -- 0: No checksum
- -- 1: Append the data with a CRC32
+ when REG_DECODING_LINK09_EGROUP3_CTRL =>
+ if GBT_NUM > 9 then
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
- register_map_control_s.FMEMU_CONTROL.BCR <= register_write_data_25_v(43 downto 43); -- Reset BCID to 0
- register_map_control_s.FMEMU_CONTROL.ECR <= register_write_data_25_v(42 downto 42); -- Reset L1ID to 0
- register_map_control_s.FMEMU_CONTROL.DATA_SRC_SEL <= register_write_data_25_v(41 downto 41); -- Data source select
- -- 0: Data input comes from EMURAM
- -- 1: Data input comes from PCIe
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK09_EGROUP4_CTRL =>
+ if GBT_NUM > 9 then
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
- register_map_control_s.FMEMU_CONTROL.FFU_FM_EMU_T <= register_write_data_25_v(31 downto 16); -- For Future Use (trigger registers)
- register_map_control_s.FMEMU_CONTROL.FFU_FM_EMU_W <= register_write_data_25_v(15 downto 0); -- For Future Use (write registers)
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FMEMU_RANDOM_RAM_ADDR =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FMEMU_RANDOM_RAM_ADDR <= register_write_data_25_v(9 downto 0); -- Controls the address of the ramblock for the random number generator
+ when REG_DECODING_LINK09_EGROUP5_CTRL =>
+ if GBT_NUM > 9 then
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FMEMU_RANDOM_RAM =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FMEMU_RANDOM_RAM.WE <= "1"; -- Any write to this register (DATA) triggers a write to the ramblock
- register_map_control_s.FMEMU_RANDOM_RAM.CHANNEL_SELECT <= register_write_data_25_v(39 downto 16); -- Enable write enable only for the selected channel
- register_map_control_s.FMEMU_RANDOM_RAM.DATA <= register_write_data_25_v(15 downto 0); -- DATA field to be written to FMEMU_RANDOM_RAM_ADDR
+ when REG_DECODING_LINK09_EGROUP6_CTRL =>
+ if GBT_NUM > 9 then
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (9)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_FMEMU_RANDOM_CONTROL =>
- if EMU_GENERATE_REGS then
- register_map_control_s.FMEMU_RANDOM_CONTROL.SELECT_RANDOM <= register_write_data_25_v(20 downto 20); -- 1 enables the random chunk length, 0 uses a constant chunk length
- register_map_control_s.FMEMU_RANDOM_CONTROL.SEED <= register_write_data_25_v(19 downto 10); -- Seed for the random number generator, should not be 0
- register_map_control_s.FMEMU_RANDOM_CONTROL.POLYNOMIAL <= register_write_data_25_v(9 downto 0); -- POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
+ when REG_DECODING_LINK10_EGROUP0_CTRL =>
+ if GBT_NUM > 10 then
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_WISHBONE_CONTROL => register_map_control_s.WISHBONE_CONTROL.WRITE_NOT_READ <= register_write_data_25_v(32 downto 32); -- wishbone write command wishbone read command
- register_map_control_s.WISHBONE_CONTROL.ADDRESS <= register_write_data_25_v(31 downto 0); -- Slave address for Wishbone bus
- when REG_WISHBONE_WRITE => register_map_control_s.WISHBONE_WRITE.WRITE_ENABLE <= "1"; -- Any write to this register triggers a write to the Wupper to Wishbone fifo
- register_map_control_s.WISHBONE_WRITE.DATA <= register_write_data_25_v(31 downto 0); -- Wishbone
- when REG_WISHBONE_READ => register_map_control_s.WISHBONE_READ.READ_ENABLE <= "1"; -- Any write to this register triggers a read from the Wishbone to Wupper fifo
- when REG_GLOBAL_STRIPS_CONFIG => register_map_control_s.GLOBAL_STRIPS_CONFIG.TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
- register_map_control_s.GLOBAL_STRIPS_CONFIG.TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR. TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work. (See also BC_START, and BC_STOP fields)
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_0 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (0)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (0)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+ when REG_DECODING_LINK10_EGROUP1_CTRL =>
+ if GBT_NUM > 10 then
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
- register_map_control_s.LCB_CTRL (0)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (0)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (0)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (0)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK10_EGROUP2_CTRL =>
+ if GBT_NUM > 10 then
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
- register_map_control_s.LCB_CTRL (0)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK10_EGROUP3_CTRL =>
+ if GBT_NUM > 10 then
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
- register_map_control_s.LCB_CTRL (0)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (0)(0).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (0)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK10_EGROUP4_CTRL =>
+ if GBT_NUM > 10 then
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_DECODING_LINK10_EGROUP5_CTRL =>
+ if GBT_NUM > 10 then
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (0)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (0)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (0)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (0)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
+ when REG_DECODING_LINK10_EGROUP6_CTRL =>
+ if GBT_NUM > 10 then
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (10)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
+ when REG_DECODING_LINK11_EGROUP0_CTRL =>
+ if GBT_NUM > 11 then
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(0).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(0).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK11_EGROUP1_CTRL =>
+ if GBT_NUM > 11 then
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(1).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(1).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK11_EGROUP2_CTRL =>
+ if GBT_NUM > 11 then
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(2).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(2).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
+ when REG_DECODING_LINK11_EGROUP3_CTRL =>
+ if GBT_NUM > 11 then
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(3).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(3).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK11_EGROUP4_CTRL =>
+ if GBT_NUM > 11 then
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(4).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(4).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK11_EGROUP5_CTRL =>
+ if GBT_NUM > 11 then
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(5).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(5).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(5).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(5).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
+ end if;
+ when REG_DECODING_LINK11_EGROUP6_CTRL =>
+ if GBT_NUM > 11 then
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(6).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(6).PATH_ENCODING <= register_write_data_25_v(42 downto 11); -- Encoding for every EPATH, 4 bits per E-path
+ -- 0: direct mode
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: TTC
+ -- 4: ITk Strips 8b10b
+ -- 5: ITk Pixel
+ -- 6: Endeavour
+ -- 7-15: reserved
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(6).EPATH_WIDTH <= register_write_data_25_v(10 downto 8); -- Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
+ register_map_control_s.DECODING_EGROUP_CTRL (11)(6).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per EPROC
+ end if;
+ when REG_MINI_EGROUP_TOHOST_00 =>
+ if GBT_NUM > 0 then
+ register_map_control_s.MINI_EGROUP_TOHOST (0).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (0).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (0).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (0).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (0).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (0).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (0).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_01 =>
+ if GBT_NUM > 1 then
+ register_map_control_s.MINI_EGROUP_TOHOST (1).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (1).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (1).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (1).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (1).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (1).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (1).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_02 =>
+ if GBT_NUM > 2 then
+ register_map_control_s.MINI_EGROUP_TOHOST (2).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (2).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (2).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (2).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (2).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (2).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (2).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_03 =>
+ if GBT_NUM > 3 then
+ register_map_control_s.MINI_EGROUP_TOHOST (3).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (3).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (3).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (3).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (3).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (3).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (3).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_04 =>
+ if GBT_NUM > 4 then
+ register_map_control_s.MINI_EGROUP_TOHOST (4).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (4).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (4).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (4).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (4).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (4).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (4).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_05 =>
+ if GBT_NUM > 5 then
+ register_map_control_s.MINI_EGROUP_TOHOST (5).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (5).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (5).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (5).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (5).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (5).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (5).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_06 =>
+ if GBT_NUM > 6 then
+ register_map_control_s.MINI_EGROUP_TOHOST (6).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (6).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (6).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (6).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (6).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (6).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (6).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_07 =>
+ if GBT_NUM > 7 then
+ register_map_control_s.MINI_EGROUP_TOHOST (7).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (7).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (7).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (7).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (7).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (7).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (7).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
+ end if;
+ when REG_MINI_EGROUP_TOHOST_08 =>
+ if GBT_NUM > 8 then
+ register_map_control_s.MINI_EGROUP_TOHOST (8).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (8).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (8).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (8).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (8).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (8).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (8).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_TOHOST_09 =>
+ if GBT_NUM > 9 then
+ register_map_control_s.MINI_EGROUP_TOHOST (9).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (9).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (9).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (9).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (9).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (9).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (9).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_1 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (0)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (0)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (0)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (0)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (0)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (0)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (0)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (0)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (0)(1).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (0)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_MINI_EGROUP_TOHOST_10 =>
+ if GBT_NUM > 10 then
+ register_map_control_s.MINI_EGROUP_TOHOST (10).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (10).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (10).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (10).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (10).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (10).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (10).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_MINI_EGROUP_TOHOST_11 =>
+ if GBT_NUM > 11 then
+ register_map_control_s.MINI_EGROUP_TOHOST (11).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (11).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (11).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (11).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (11).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (11).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (11).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (0)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (0)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (0)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (0)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_TOHOST_12 =>
+ if GBT_NUM > 12 then
+ register_map_control_s.MINI_EGROUP_TOHOST (12).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (12).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (12).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (12).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (12).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (12).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (12).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_TOHOST_13 =>
+ if GBT_NUM > 13 then
+ register_map_control_s.MINI_EGROUP_TOHOST (13).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (13).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (13).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (13).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (13).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (13).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (13).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_TOHOST_14 =>
+ if GBT_NUM > 14 then
+ register_map_control_s.MINI_EGROUP_TOHOST (14).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (14).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (14).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (14).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (14).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (14).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (14).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_TOHOST_15 =>
+ if GBT_NUM > 15 then
+ register_map_control_s.MINI_EGROUP_TOHOST (15).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (15).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (15).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (15).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (15).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (15).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (15).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_2 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (0)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (0)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (0)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (0)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (0)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (0)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (0)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (0)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (0)(2).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (0)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_MINI_EGROUP_TOHOST_16 =>
+ if GBT_NUM > 16 then
+ register_map_control_s.MINI_EGROUP_TOHOST (16).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (16).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (16).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (16).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (16).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (16).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (16).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_MINI_EGROUP_TOHOST_17 =>
+ if GBT_NUM > 17 then
+ register_map_control_s.MINI_EGROUP_TOHOST (17).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (17).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (17).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (17).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (17).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (17).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (17).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (0)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (0)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (0)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (0)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_TOHOST_18 =>
+ if GBT_NUM > 18 then
+ register_map_control_s.MINI_EGROUP_TOHOST (18).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (18).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (18).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (18).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (18).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (18).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (18).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_TOHOST_19 =>
+ if GBT_NUM > 19 then
+ register_map_control_s.MINI_EGROUP_TOHOST (19).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (19).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (19).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (19).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (19).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (19).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (19).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_TOHOST_20 =>
+ if GBT_NUM > 20 then
+ register_map_control_s.MINI_EGROUP_TOHOST (20).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (20).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (20).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (20).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (20).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (20).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (20).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_TOHOST_21 =>
+ if GBT_NUM > 21 then
+ register_map_control_s.MINI_EGROUP_TOHOST (21).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (21).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (21).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (21).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (21).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (21).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (21).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_3 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (0)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (0)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (0)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (0)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (0)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (0)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (0)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (0)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (0)(3).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (0)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_MINI_EGROUP_TOHOST_22 =>
+ if GBT_NUM > 22 then
+ register_map_control_s.MINI_EGROUP_TOHOST (22).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (22).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (22).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (22).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (22).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (22).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (22).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (0)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_MINI_EGROUP_TOHOST_23 =>
+ if GBT_NUM > 23 then
+ register_map_control_s.MINI_EGROUP_TOHOST (23).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (23).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_TOHOST (23).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (23).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (23).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two input bits of EC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_TOHOST (23).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_TOHOST (23).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the EC channel
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (0)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (0)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
+ when REG_TTC_TOHOST_ENABLE => register_map_control_s.TTC_TOHOST_ENABLE <= register_write_data_25_v(0 downto 0); -- Enables the ToHost Mini Egroup in TTC mode
+ when REG_DECODING_REVERSE_10B => register_map_control_s.DECODING_REVERSE_10B <= register_write_data_25_v(0 downto 0); -- Reverse 10-bit word of elink data for 8b10b E-links
+ -- 1: Receive 10-bit word in ToHost E-Paths, MSB first
+ -- 0: Receive 10-bit word in ToHost E-Paths, LSB first
- register_map_control_s.HCC_ABC_MASK_E_C (0)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_REVERSE_10B => register_map_control_s.ENCODING_REVERSE_10B <= register_write_data_25_v(0 downto 0); -- Reverse 10-bit word of elink data for 8b10b E-links. 1 MSB first, 0 LSB first
+ when REG_ENCODING_LINK00_EGROUP0_CTRL =>
+ if GBT_NUM > 0 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.HCC_ABC_MASK_E_C (0)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK00_EGROUP1_CTRL =>
+ if GBT_NUM > 0 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_B_8 (0)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK00_EGROUP2_CTRL =>
+ if GBT_NUM > 0 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_7_4 (0)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK00_EGROUP3_CTRL =>
+ if GBT_NUM > 0 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_3_0 (0)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_R3L1_LINK_00_R3L1_0 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (0)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (0)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (0)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_00_R3L1_1 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (0)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (0)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (0)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_00_R3L1_2 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (0)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (0)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (0)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_00_R3L1_3 =>
- if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (0)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (0)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (0)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_0 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (1)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (1)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+ when REG_ENCODING_LINK00_EGROUP4_CTRL =>
+ if GBT_NUM > 0 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_CTRL (1)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (1)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (1)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (1)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_CTRL (1)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+ register_map_control_s.ENCODING_EGROUP_CTRL (0)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK01_EGROUP0_CTRL =>
+ if GBT_NUM > 1 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_CTRL (1)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (1)(0).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (1)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_ENCODING_LINK01_EGROUP1_CTRL =>
+ if GBT_NUM > 1 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (1)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_ENCODING_LINK01_EGROUP2_CTRL =>
+ if GBT_NUM > 1 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.HCC_ABC_MASK_E_C (1)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.HCC_ABC_MASK_E_C (1)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK01_EGROUP3_CTRL =>
+ if GBT_NUM > 1 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.HCC_ABC_MASK_E_C (1)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK01_EGROUP4_CTRL =>
+ if GBT_NUM > 1 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (1)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK02_EGROUP0_CTRL =>
+ if GBT_NUM > 2 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK02_EGROUP1_CTRL =>
+ if GBT_NUM > 2 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK02_EGROUP2_CTRL =>
+ if GBT_NUM > 2 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK02_EGROUP3_CTRL =>
+ if GBT_NUM > 2 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK02_EGROUP4_CTRL =>
+ if GBT_NUM > 2 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (2)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_1 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (1)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (1)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+ when REG_ENCODING_LINK03_EGROUP0_CTRL =>
+ if GBT_NUM > 3 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_CTRL (1)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (1)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (1)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (1)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_CTRL (1)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK03_EGROUP1_CTRL =>
+ if GBT_NUM > 3 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_CTRL (1)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (1)(1).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (1)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_ENCODING_LINK03_EGROUP2_CTRL =>
+ if GBT_NUM > 3 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (1)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_ENCODING_LINK03_EGROUP3_CTRL =>
+ if GBT_NUM > 3 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.HCC_ABC_MASK_E_C (1)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.HCC_ABC_MASK_E_C (1)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK03_EGROUP4_CTRL =>
+ if GBT_NUM > 3 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.HCC_ABC_MASK_E_C (1)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (3)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK04_EGROUP0_CTRL =>
+ if GBT_NUM > 4 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK04_EGROUP1_CTRL =>
+ if GBT_NUM > 4 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK04_EGROUP2_CTRL =>
+ if GBT_NUM > 4 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK04_EGROUP3_CTRL =>
+ if GBT_NUM > 4 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK04_EGROUP4_CTRL =>
+ if GBT_NUM > 4 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (4)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK05_EGROUP0_CTRL =>
+ if GBT_NUM > 5 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_2 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (1)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (1)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+ when REG_ENCODING_LINK05_EGROUP1_CTRL =>
+ if GBT_NUM > 5 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_CTRL (1)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (1)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (1)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (1)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_CTRL (1)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK05_EGROUP2_CTRL =>
+ if GBT_NUM > 5 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_CTRL (1)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (1)(2).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (1)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_ENCODING_LINK05_EGROUP3_CTRL =>
+ if GBT_NUM > 5 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (1)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_ENCODING_LINK05_EGROUP4_CTRL =>
+ if GBT_NUM > 5 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.HCC_ABC_MASK_E_C (1)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.HCC_ABC_MASK_E_C (1)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (5)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK06_EGROUP0_CTRL =>
+ if GBT_NUM > 6 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.HCC_ABC_MASK_E_C (1)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK06_EGROUP1_CTRL =>
+ if GBT_NUM > 6 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK06_EGROUP2_CTRL =>
+ if GBT_NUM > 6 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK06_EGROUP3_CTRL =>
+ if GBT_NUM > 6 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK06_EGROUP4_CTRL =>
+ if GBT_NUM > 6 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (6)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK07_EGROUP0_CTRL =>
+ if GBT_NUM > 7 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_3 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (1)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (1)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+ when REG_ENCODING_LINK07_EGROUP1_CTRL =>
+ if GBT_NUM > 7 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_CTRL (1)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (1)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (1)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (1)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_CTRL (1)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK07_EGROUP2_CTRL =>
+ if GBT_NUM > 7 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_CTRL (1)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (1)(3).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (1)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_ENCODING_LINK07_EGROUP3_CTRL =>
+ if GBT_NUM > 7 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (1)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (1)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_ENCODING_LINK07_EGROUP4_CTRL =>
+ if GBT_NUM > 7 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.HCC_ABC_MASK_E_C (1)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.HCC_ABC_MASK_E_C (1)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (7)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK08_EGROUP0_CTRL =>
+ if GBT_NUM > 8 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.HCC_ABC_MASK_E_C (1)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK08_EGROUP1_CTRL =>
+ if GBT_NUM > 8 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK08_EGROUP2_CTRL =>
+ if GBT_NUM > 8 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_B_8 (1)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK08_EGROUP3_CTRL =>
+ if GBT_NUM > 8 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK08_EGROUP4_CTRL =>
+ if GBT_NUM > 8 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_7_4 (1)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (8)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK09_EGROUP0_CTRL =>
+ if GBT_NUM > 9 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK09_EGROUP1_CTRL =>
+ if GBT_NUM > 9 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_3_0 (1)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_R3L1_LINK_01_R3L1_0 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (1)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (1)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (1)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_01_R3L1_1 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (1)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (1)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (1)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_01_R3L1_2 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (1)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (1)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (1)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_01_R3L1_3 =>
- if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (1)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (1)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (1)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_0 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (2)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (2)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+ when REG_ENCODING_LINK09_EGROUP2_CTRL =>
+ if GBT_NUM > 9 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_CTRL (2)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (2)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (2)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (2)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_CTRL (2)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK09_EGROUP3_CTRL =>
+ if GBT_NUM > 9 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_CTRL (2)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (2)(0).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (2)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_ENCODING_LINK09_EGROUP4_CTRL =>
+ if GBT_NUM > 9 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+
+ register_map_control_s.ENCODING_EGROUP_CTRL (9)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (2)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_ENCODING_LINK10_EGROUP0_CTRL =>
+ if GBT_NUM > 10 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.HCC_ABC_MASK_E_C (2)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.HCC_ABC_MASK_E_C (2)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK10_EGROUP1_CTRL =>
+ if GBT_NUM > 10 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.HCC_ABC_MASK_E_C (2)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK10_EGROUP2_CTRL =>
+ if GBT_NUM > 10 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK10_EGROUP3_CTRL =>
+ if GBT_NUM > 10 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK10_EGROUP4_CTRL =>
+ if GBT_NUM > 10 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (10)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK11_EGROUP0_CTRL =>
+ if GBT_NUM > 11 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(0).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(0).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(0).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(0).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(0).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
+ when REG_ENCODING_LINK11_EGROUP1_CTRL =>
+ if GBT_NUM > 11 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(1).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(1).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(1).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(1).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(1).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK11_EGROUP2_CTRL =>
+ if GBT_NUM > 11 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(2).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(2).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(2).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(2).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(2).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_1 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (2)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (2)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+ when REG_ENCODING_LINK11_EGROUP3_CTRL =>
+ if GBT_NUM > 11 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(3).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(3).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(3).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_CTRL (2)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (2)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (2)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (2)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(3).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
- register_map_control_s.LCB_CTRL (2)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(3).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
+ end if;
+ when REG_ENCODING_LINK11_EGROUP4_CTRL =>
+ if GBT_NUM > 11 then
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(4).TTC_OPTION <= register_write_data_25_v(62 downto 59); -- Selects TTC bits sent to the E-link
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(4).REVERSE_ELINKS <= register_write_data_25_v(50 downto 43); -- enables bit reversing for the elink in the given epath
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(4).EPATH_WIDTH <= register_write_data_25_v(42 downto 40); -- Width of the Elinks in the egroup
+ -- 0: 2 bit 80 Mb/s
+ -- 1: 4 bit 160 Mb/s
+ -- 2: 8 bit 320 Mb/s
- register_map_control_s.LCB_CTRL (2)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (2)(1).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (2)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(4).PATH_ENCODING <= register_write_data_25_v(39 downto 8); -- Encoding for every EPATH, 4 bits per E-Path
+ -- 0: No encoding
+ -- 1: 8b10b mode
+ -- 2: HDLC mode
+ -- 3: ITk Strip LCB
+ -- 4: ITk Pixel
+ -- 5: Endeavour
+ -- 6: reserved
+ -- 7: reserved
+ -- greater than 7: TTC mode, see firmware Phase 2 specification doc
+ register_map_control_s.ENCODING_EGROUP_CTRL (11)(4).EPATH_ENA <= register_write_data_25_v(7 downto 0); -- Enable bits per E-PATH
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_MINI_EGROUP_FROMHOST_00 =>
+ if GBT_NUM > 0 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (0).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (0).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (0).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (0).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (0).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (0).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (0).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (2)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (2)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (2)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (2)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_FROMHOST_01 =>
+ if GBT_NUM > 1 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (1).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (1).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (1).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (1).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (1).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (1).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (1).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_02 =>
+ if GBT_NUM > 2 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (2).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (2).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (2).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (2).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (2).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (2).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (2).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_03 =>
+ if GBT_NUM > 3 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (3).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (3).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (3).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (3).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (3).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (3).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (3).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_04 =>
+ if GBT_NUM > 4 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (4).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (4).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (4).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (4).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (4).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (4).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (4).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_05 =>
+ if GBT_NUM > 5 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (5).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (5).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (5).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (5).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (5).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (5).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (5).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_06 =>
+ if GBT_NUM > 6 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (6).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (6).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (6).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (6).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (6).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (6).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (6).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_FROMHOST_07 =>
+ if GBT_NUM > 7 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (7).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (7).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (7).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (7).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (7).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (7).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (7).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_FROMHOST_08 =>
+ if GBT_NUM > 8 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (8).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (8).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (8).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (8).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (8).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (8).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (8).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_FROMHOST_09 =>
+ if GBT_NUM > 9 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (9).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (9).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (9).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (9).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (9).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (9).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (9).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_2 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (2)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (2)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (2)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (2)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (2)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (2)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (2)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (2)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (2)(2).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (2)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_MINI_EGROUP_FROMHOST_10 =>
+ if GBT_NUM > 10 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (10).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (10).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (10).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (10).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (10).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (10).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (10).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_MINI_EGROUP_FROMHOST_11 =>
+ if GBT_NUM > 11 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (11).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (11).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (11).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (11).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (11).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (11).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (11).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (2)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (2)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (2)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (2)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_FROMHOST_12 =>
+ if GBT_NUM > 12 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (12).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (12).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (12).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (12).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (12).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (12).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (12).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_FROMHOST_13 =>
+ if GBT_NUM > 13 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (13).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (13).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (13).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (13).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (13).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (13).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (13).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_FROMHOST_14 =>
+ if GBT_NUM > 14 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (14).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (14).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (14).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (14).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (14).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (14).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (14).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_FROMHOST_15 =>
+ if GBT_NUM > 15 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (15).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (15).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (15).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (15).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (15).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (15).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (15).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_3 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (2)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (2)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (2)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (2)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (2)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (2)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (2)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (2)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (2)(3).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (2)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_MINI_EGROUP_FROMHOST_16 =>
+ if GBT_NUM > 16 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (16).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (16).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (16).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (16).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (16).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (16).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (16).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
+ end if;
+ when REG_MINI_EGROUP_FROMHOST_17 =>
+ if GBT_NUM > 17 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (17).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (17).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (17).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (17).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (17).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (17).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (17).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (2)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_MINI_EGROUP_FROMHOST_18 =>
+ if GBT_NUM > 18 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (18).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (18).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (18).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (18).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (18).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (18).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (18).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (2)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (2)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (2)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (2)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_FROMHOST_19 =>
+ if GBT_NUM > 19 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (19).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (19).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (19).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (19).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (19).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (19).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (19).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (2)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_FROMHOST_20 =>
+ if GBT_NUM > 20 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (20).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (20).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (20).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (20).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (20).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (20).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (20).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (2)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_FROMHOST_21 =>
+ if GBT_NUM > 21 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (21).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (21).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (21).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (21).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (21).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (21).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (21).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (2)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_MINI_EGROUP_FROMHOST_22 =>
+ if GBT_NUM > 22 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (22).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (22).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (22).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (22).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (22).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (22).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (22).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_R3L1_LINK_02_R3L1_0 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (2)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (2)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (2)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ when REG_MINI_EGROUP_FROMHOST_23 =>
+ if GBT_NUM > 23 then
+ register_map_control_s.MINI_EGROUP_FROMHOST (23).AUX_BIT_SWAPPING <= register_write_data_25_v(11 downto 11); -- 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (23).AUX_ENABLE <= register_write_data_25_v(10 downto 10); -- Enables the AUX channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (23).IC_BIT_SWAPPING <= register_write_data_25_v(8 downto 8); -- 0: two input bits of IC e-link are as documented, 1: two input bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (23).IC_ENABLE <= register_write_data_25_v(7 downto 7); -- Enables the IC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (23).EC_BIT_SWAPPING <= register_write_data_25_v(5 downto 5); -- 0: two output bits of EC e-link are as documented, 1: two output bits are swapped
+ register_map_control_s.MINI_EGROUP_FROMHOST (23).EC_ENCODING <= register_write_data_25_v(4 downto 1); -- Configures encoding of the EC channel
+ register_map_control_s.MINI_EGROUP_FROMHOST (23).EC_ENABLE <= register_write_data_25_v(0 downto 0); -- Configures the FromHost Mini egroup
end if;
- when REG_CR_ITK_R3L1_LINK_02_R3L1_1 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (2)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (2)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (2)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ when REG_FE_EMU_ENA => register_map_control_s.FE_EMU_ENA.EMU_TOFRONTEND <= register_write_data_25_v(1 downto 1); -- Enable GBT dummy emulator ToFrontEnd
+ register_map_control_s.FE_EMU_ENA.EMU_TOHOST <= register_write_data_25_v(0 downto 0); -- Enable GBT dummy emulator ToHost
+ when REG_FE_EMU_CONFIG => register_map_control_s.FE_EMU_CONFIG.WE <= register_write_data_25_v(54 downto 47); -- write enable array, every bit is one emulator RAM block
+ register_map_control_s.FE_EMU_CONFIG.WRADDR <= register_write_data_25_v(46 downto 33); -- write address bus
+ register_map_control_s.FE_EMU_CONFIG.WRDATA <= register_write_data_25_v(32 downto 0); -- write data bus
+ when REG_FE_EMU_READ => register_map_control_s.FE_EMU_READ.SEL <= register_write_data_25_v(35 downto 33); -- Select ramblock to read back
+ when REG_GBT_CHANNEL_DISABLE => register_map_control_s.GBT_CHANNEL_DISABLE <= register_write_data_25_v(47 downto 0); -- Disable selected lpGBT, GBT or FULL mode channel
+ when REG_GBT_GENERAL_CTRL => register_map_control_s.GBT_GENERAL_CTRL <= register_write_data_25_v(63 downto 0); -- Alignment chk reset (not self clearing)
+ when REG_GBT_MODE_CTRL => register_map_control_s.GBT_MODE_CTRL.RX_ALIGN_TB_SW <= register_write_data_25_v(2 downto 2); -- RX_ALIGN_TB_SW
+ register_map_control_s.GBT_MODE_CTRL.RX_ALIGN_SW <= register_write_data_25_v(1 downto 1); -- RX_ALIGN_SW
+ register_map_control_s.GBT_MODE_CTRL.DESMUX_USE_SW <= register_write_data_25_v(0 downto 0); -- DESMUX_USE_SW
+ when REG_GBT_RXSLIDE_SELECT =>
+ if GBT_GENERATE_ALL_REGS then
+ register_map_control_s.GBT_RXSLIDE_SELECT <= register_write_data_25_v(47 downto 0); -- RxSlide select [47:0]
end if;
- when REG_CR_ITK_R3L1_LINK_02_R3L1_2 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (2)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (2)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (2)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ when REG_GBT_RXSLIDE_MANUAL =>
+ if GBT_GENERATE_ALL_REGS then
+ register_map_control_s.GBT_RXSLIDE_MANUAL <= register_write_data_25_v(47 downto 0); -- RxSlide select [47:0]
end if;
- when REG_CR_ITK_R3L1_LINK_02_R3L1_3 =>
- if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (2)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (2)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (2)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ when REG_GBT_TXUSRRDY =>
+ if GBT_GENERATE_ALL_REGS then
+ register_map_control_s.GBT_TXUSRRDY <= register_write_data_25_v(47 downto 0); -- TxUsrRdy [47:0]
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_0 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (3)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (3)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (3)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (3)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (3)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (3)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (3)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (3)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (3)(0).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (3)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_GBT_RXUSRRDY =>
+ if GBT_GENERATE_ALL_REGS then
+ register_map_control_s.GBT_RXUSRRDY <= register_write_data_25_v(47 downto 0); -- RxUsrRdy [47:0]
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_GBT_SOFT_RESET => register_map_control_s.GBT_SOFT_RESET <= register_write_data_25_v(47 downto 0); -- SOFT_RESET [47:0]
+ when REG_GBT_GTTX_RESET => register_map_control_s.GBT_GTTX_RESET <= register_write_data_25_v(47 downto 0); -- GTTX_RESET [47:0]
+ when REG_GBT_GTRX_RESET => register_map_control_s.GBT_GTRX_RESET <= register_write_data_25_v(47 downto 0); -- GTRX_RESET [47:0]
+ when REG_GBT_PLL_RESET => register_map_control_s.GBT_PLL_RESET.QPLL_RESET <= register_write_data_25_v(59 downto 48); -- QPLL_RESET [11:0]
+ register_map_control_s.GBT_PLL_RESET.CPLL_RESET <= register_write_data_25_v(47 downto 0); -- CPLL_RESET [47:0]
+ when REG_GBT_SOFT_TX_RESET =>
+ if GBT_GENERATE_ALL_REGS then
+ register_map_control_s.GBT_SOFT_TX_RESET.RESET_ALL <= register_write_data_25_v(59 downto 48); -- SOFT_TX_RESET_ALL [11:0]
+ register_map_control_s.GBT_SOFT_TX_RESET.RESET_GT <= register_write_data_25_v(47 downto 0); -- SOFT_TX_RESET_GT [47:0]
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (3)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (3)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (3)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (3)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_GBT_SOFT_RX_RESET =>
+ if GBT_GENERATE_ALL_REGS then
+ register_map_control_s.GBT_SOFT_RX_RESET.RESET_ALL <= register_write_data_25_v(59 downto 48); -- SOFT_TX_RESET_ALL [11:0]
+ register_map_control_s.GBT_SOFT_RX_RESET.RESET_GT <= register_write_data_25_v(47 downto 0); -- SOFT_TX_RESET_GT [47:0]
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_GBT_ODD_EVEN =>
+ if GBT_GENERATE_ALL_REGS then
+ register_map_control_s.GBT_ODD_EVEN <= register_write_data_25_v(47 downto 0); -- OddEven [47:0]
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
+ when REG_GBT_TOPBOT =>
+ if GBT_GENERATE_ALL_REGS then
+ register_map_control_s.GBT_TOPBOT <= register_write_data_25_v(47 downto 0); -- TopBot [47:0]
+ end if;
+ when REG_GBT_TX_TC_DLY_VALUE1 => register_map_control_s.GBT_TX_TC_DLY_VALUE1 <= register_write_data_25_v(47 downto 0); -- TX_TC_DLY_VALUE [47:0]
+ when REG_GBT_TX_TC_DLY_VALUE2 => register_map_control_s.GBT_TX_TC_DLY_VALUE2 <= register_write_data_25_v(47 downto 0); -- TX_TC_DLY_VALUE [95:48]
+ when REG_GBT_TX_TC_DLY_VALUE3 => register_map_control_s.GBT_TX_TC_DLY_VALUE3 <= register_write_data_25_v(47 downto 0); -- TX_TC_DLY_VALUE [143:96]
+ when REG_GBT_TX_TC_DLY_VALUE4 => register_map_control_s.GBT_TX_TC_DLY_VALUE4 <= register_write_data_25_v(47 downto 0); -- TX_TC_DLY_VALUE [191:144]
+ when REG_GBT_DATA_TXFORMAT1 => register_map_control_s.GBT_DATA_TXFORMAT1 <= register_write_data_25_v(47 downto 0); -- DATA_TXFORMAT [47:0]
+ when REG_GBT_DATA_TXFORMAT2 => register_map_control_s.GBT_DATA_TXFORMAT2 <= register_write_data_25_v(47 downto 0); -- DATA_TXFORMAT [95:48]
+ when REG_GBT_DATA_RXFORMAT1 => register_map_control_s.GBT_DATA_RXFORMAT1 <= register_write_data_25_v(47 downto 0); -- DATA_RXFORMAT [47:0]
+ when REG_GBT_DATA_RXFORMAT2 => register_map_control_s.GBT_DATA_RXFORMAT2 <= register_write_data_25_v(47 downto 0); -- DATA_RXFORMAT [95:0]
+ when REG_GBT_TX_RESET => register_map_control_s.GBT_TX_RESET <= register_write_data_25_v(47 downto 0); -- TX Logic reset [47:0]
+ when REG_GBT_RX_RESET => register_map_control_s.GBT_RX_RESET <= register_write_data_25_v(47 downto 0); -- RX Logic reset [47:0]
+ when REG_GBT_TX_TC_METHOD => register_map_control_s.GBT_TX_TC_METHOD <= register_write_data_25_v(47 downto 0); -- TX time domain crossing method [47:0]
+ when REG_GBT_OUTMUX_SEL => register_map_control_s.GBT_OUTMUX_SEL <= register_write_data_25_v(47 downto 0); -- Descrambler output MUX selection [47:0]
+ when REG_GBT_TC_EDGE => register_map_control_s.GBT_TC_EDGE <= register_write_data_25_v(47 downto 0); -- Sampling edge selection for TX domain crossing [47:0]
+ when REG_GBT_TXPOLARITY => register_map_control_s.GBT_TXPOLARITY <= register_write_data_25_v(47 downto 0); -- 0: default polarity
+ -- 1: reversed polarity for transmitter of GTH channels
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
+ when REG_GBT_RXPOLARITY => register_map_control_s.GBT_RXPOLARITY <= register_write_data_25_v(47 downto 0); -- 0: default polarity
+ -- 1: reversed polarity for the receiver of the GTH channels
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
+ when REG_GTH_LOOPBACK_CONTROL => register_map_control_s.GTH_LOOPBACK_CONTROL <= register_write_data_25_v(2 downto 0); -- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
+ -- 000: Normal operation
+ -- 001: Near-End PCS Loopback
+ -- 010: Near-End PMA Loopback
+ -- 011: Reserved
+ -- 100: Far-End PMA Loopback
+ -- 101: Reserved
+ -- 110: Far-End PCS Loopback
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
+ when REG_GBT_TOHOST_FANOUT => register_map_control_s.GBT_TOHOST_FANOUT.LOCK <= register_write_data_25_v(48 downto 48); -- Locks this particular register. If set prevents software from touching it.
+ register_map_control_s.GBT_TOHOST_FANOUT.SEL <= register_write_data_25_v(47 downto 0); -- ToHost FanOut/Selector. Every bitfield is a channel:
+ -- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
+ -- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
+ when REG_GBT_TOFRONTEND_FANOUT => register_map_control_s.GBT_TOFRONTEND_FANOUT.LOCK <= register_write_data_25_v(48 downto 48); -- Locks this particular register. If set prevents software from touching it.
+ register_map_control_s.GBT_TOFRONTEND_FANOUT.SEL <= register_write_data_25_v(47 downto 0); -- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
+ -- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
+ -- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
+ --
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
+ when REG_TTC_DEC_CTRL => register_map_control_s.TTC_DEC_CTRL.L1A_DELAY <= register_write_data_25_v(30 downto 27); -- Number of BC to delay the L1A distribution to the frontends
+ register_map_control_s.TTC_DEC_CTRL.BCID_ONBCR <= register_write_data_25_v(26 downto 15); -- BCID is set to this value when BCR arrives
+ register_map_control_s.TTC_DEC_CTRL.ECR_BCR_SWAP <= register_write_data_25_v(13 downto 13); -- ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
+ register_map_control_s.TTC_DEC_CTRL.BUSY_OUTPUT_INHIBIT <= register_write_data_25_v(12 downto 12); -- forces the Busy LEMO output to BUSY-OFF
+ register_map_control_s.TTC_DEC_CTRL.TOHOST_RST <= register_write_data_25_v(11 downto 11); -- reset toHost in ttc decoder
+ register_map_control_s.TTC_DEC_CTRL.TT_BCH_EN <= register_write_data_25_v(10 downto 10); -- trigger type enable / disable for TTC-ToHost
+ register_map_control_s.TTC_DEC_CTRL.XL1ID_SW <= register_write_data_25_v(9 downto 2); -- set XL1ID value, the value to be set by XL1ID_RST signal
+ register_map_control_s.TTC_DEC_CTRL.XL1ID_RST <= register_write_data_25_v(1 downto 1); -- giving a trigger signal to reset XL1ID value
+ register_map_control_s.TTC_DEC_CTRL.MASTER_BUSY <= register_write_data_25_v(0 downto 0); -- L1A trigger throttling
+ when REG_TTC_EMU => register_map_control_s.TTC_EMU.SEL <= register_write_data_25_v(1 downto 1); -- Select TTC data source 1 TTC Emu | 0 TTC Decoder
+ register_map_control_s.TTC_EMU.ENA <= register_write_data_25_v(0 downto 0); -- Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
+ when REG_TTC_DELAY_00 => register_map_control_s.TTC_DELAY (0) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_01 => register_map_control_s.TTC_DELAY (1) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_02 => register_map_control_s.TTC_DELAY (2) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_03 => register_map_control_s.TTC_DELAY (3) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_04 => register_map_control_s.TTC_DELAY (4) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_05 => register_map_control_s.TTC_DELAY (5) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_06 => register_map_control_s.TTC_DELAY (6) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_07 => register_map_control_s.TTC_DELAY (7) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_08 => register_map_control_s.TTC_DELAY (8) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_09 => register_map_control_s.TTC_DELAY (9) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_10 => register_map_control_s.TTC_DELAY (10) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_11 => register_map_control_s.TTC_DELAY (11) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_12 => register_map_control_s.TTC_DELAY (12) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_13 => register_map_control_s.TTC_DELAY (13) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_14 => register_map_control_s.TTC_DELAY (14) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_15 => register_map_control_s.TTC_DELAY (15) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_16 => register_map_control_s.TTC_DELAY (16) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_17 => register_map_control_s.TTC_DELAY (17) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_18 => register_map_control_s.TTC_DELAY (18) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_19 => register_map_control_s.TTC_DELAY (19) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_20 => register_map_control_s.TTC_DELAY (20) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_21 => register_map_control_s.TTC_DELAY (21) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_22 => register_map_control_s.TTC_DELAY (22) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_23 => register_map_control_s.TTC_DELAY (23) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_24 => register_map_control_s.TTC_DELAY (24) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_25 => register_map_control_s.TTC_DELAY (25) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_26 => register_map_control_s.TTC_DELAY (26) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_27 => register_map_control_s.TTC_DELAY (27) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_28 => register_map_control_s.TTC_DELAY (28) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_29 => register_map_control_s.TTC_DELAY (29) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_30 => register_map_control_s.TTC_DELAY (30) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_31 => register_map_control_s.TTC_DELAY (31) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_32 => register_map_control_s.TTC_DELAY (32) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_33 => register_map_control_s.TTC_DELAY (33) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_34 => register_map_control_s.TTC_DELAY (34) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_35 => register_map_control_s.TTC_DELAY (35) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_36 => register_map_control_s.TTC_DELAY (36) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_37 => register_map_control_s.TTC_DELAY (37) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_38 => register_map_control_s.TTC_DELAY (38) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_39 => register_map_control_s.TTC_DELAY (39) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_40 => register_map_control_s.TTC_DELAY (40) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_41 => register_map_control_s.TTC_DELAY (41) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_42 => register_map_control_s.TTC_DELAY (42) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_43 => register_map_control_s.TTC_DELAY (43) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_44 => register_map_control_s.TTC_DELAY (44) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_45 => register_map_control_s.TTC_DELAY (45) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_46 => register_map_control_s.TTC_DELAY (46) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_DELAY_47 => register_map_control_s.TTC_DELAY (47) <= register_write_data_25_v(3 downto 0); -- Controls the TTC Fanout delay values
+ when REG_TTC_BUSY_TIMING_CTRL => register_map_control_s.TTC_BUSY_TIMING_CTRL.PRESCALE <= register_write_data_25_v(51 downto 32); -- Prescales the 40MHz clock to create an internal slow clock
+ register_map_control_s.TTC_BUSY_TIMING_CTRL.BUSY_WIDTH <= register_write_data_25_v(31 downto 16); -- Minimum number of 40MHz clocks that the busy is asserted
+ register_map_control_s.TTC_BUSY_TIMING_CTRL.LIMIT_TIME <= register_write_data_25_v(15 downto 0); -- Number of prescaled clocks a given busy must be asserted before it is recognized
+ when REG_TTC_BUSY_CLEAR => register_map_control_s.TTC_BUSY_CLEAR <= "1"; -- clears the latching busy bits in TTC_BUSY_ACCEPTED
+ when REG_TTC_EMU_CONTROL => register_map_control_s.TTC_EMU_CONTROL.BROADCAST <= register_write_data_25_v(32 downto 27); -- Broadcast data
+ register_map_control_s.TTC_EMU_CONTROL.ECR <= register_write_data_25_v(26 downto 26); -- Event counter reset
+ register_map_control_s.TTC_EMU_CONTROL.BCR <= register_write_data_25_v(25 downto 25); -- Bunch counter reset
+ register_map_control_s.TTC_EMU_CONTROL.L1A <= register_write_data_25_v(24 downto 24); -- Level 1 Accept
+ when REG_TTC_EMU_L1A_PERIOD => register_map_control_s.TTC_EMU_L1A_PERIOD <= register_write_data_25_v(31 downto 0); -- L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
+ when REG_TTC_EMU_ECR_PERIOD => register_map_control_s.TTC_EMU_ECR_PERIOD <= register_write_data_25_v(31 downto 0); -- ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
+ when REG_TTC_EMU_BCR_PERIOD => register_map_control_s.TTC_EMU_BCR_PERIOD <= register_write_data_25_v(31 downto 0); -- BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
+ when REG_TTC_EMU_LONG_CHANNEL_DATA => register_map_control_s.TTC_EMU_LONG_CHANNEL_DATA <= register_write_data_25_v(31 downto 0); -- Long channel data for the TTC emulator
+ when REG_TTC_EMU_RESET => register_map_control_s.TTC_EMU_RESET <= "1"; -- Any write to this register resets the TTC Emulator to the default state.
+ when REG_TTC_ECR_MONITOR => register_map_control_s.TTC_ECR_MONITOR.CLEAR <= "1"; -- Counts the number of ECRs received from the TTC system, any write to this register clears the counter
+ when REG_TTC_TTYPE_MONITOR => register_map_control_s.TTC_TTYPE_MONITOR.CLEAR <= "1"; -- Counts the number of TType received from the TTC system, any write to this register clears the counter
+ when REG_TTC_BCR_PERIODICITY_MONITOR => register_map_control_s.TTC_BCR_PERIODICITY_MONITOR.CLEAR <= "1"; -- Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
+ when REG_XOFF_FM_CH_FIFO_THRESH_LOW => register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW <= register_write_data_25_v(3 downto 0); -- Controls the low threshold of the channel fifo in FULL mode on which
+ -- an Xon will be asserted, bitfields control 4 MSB
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_1 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (3)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (3)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+ when REG_XOFF_FM_CH_FIFO_THRESH_HIGH => register_map_control_s.XOFF_FM_CH_FIFO_THRESH_HIGH <= register_write_data_25_v(3 downto 0); -- Controls the high threshold of the channel fifo in FULL mode on which
+ -- an Xoff will be asserted, bitfields control 4 MSB - name: XOFF_FM_LOW_THRESH_CROSSED
- register_map_control_s.LCB_CTRL (3)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (3)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (3)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (3)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
+ when REG_XOFF_FM_HIGH_THRESH => register_map_control_s.XOFF_FM_HIGH_THRESH.CLEAR_LATCH <= "1"; -- Writing this register will clear all CROSS_LATCHED bits
+ when REG_XOFF_FM_SOFT_XOFF => register_map_control_s.XOFF_FM_SOFT_XOFF <= register_write_data_25_v(23 downto 0); -- Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
+ when REG_XOFF_ENABLE => register_map_control_s.XOFF_ENABLE <= register_write_data_25_v(23 downto 0); -- Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
+ when REG_DMA_BUSY_STATUS => register_map_control_s.DMA_BUSY_STATUS.CLEAR_LATCH <= "1"; -- Any write to this register clears TOHOST_BUSY_LATCHED
+ register_map_control_s.DMA_BUSY_STATUS.ENABLE <= register_write_data_25_v(4 downto 4); -- Enable the DMA buffer on the server as a source of busy
+ when REG_FM_BUSY_CHANNEL_STATUS => register_map_control_s.FM_BUSY_CHANNEL_STATUS.CLEAR_LATCH <= "1"; -- Any write to this register will clear the BUSY_LATCHED bits
+ when REG_BUSY_MAIN_OUTPUT_FIFO_THRESH => register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_THRESH.BUSY_ENABLE <= register_write_data_25_v(24 downto 24); -- Enable busy generation if thresholds are crossed
+ register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_THRESH.LOW <= register_write_data_25_v(23 downto 12); -- Low, Negate threshold of busy generation from main output fifo
+ register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_THRESH.HIGH <= register_write_data_25_v(11 downto 0); -- High, Assert threshold of busy generation from main output fifo
+ when REG_BUSY_MAIN_OUTPUT_FIFO_STATUS => register_map_control_s.BUSY_MAIN_OUTPUT_FIFO_STATUS.CLEAR_LATCHED <= "1"; -- Any write to this register will clear the
+ when REG_ELINK_BUSY_ENABLE00 => register_map_control_s.ELINK_BUSY_ENABLE (0) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE01 => register_map_control_s.ELINK_BUSY_ENABLE (1) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE02 => register_map_control_s.ELINK_BUSY_ENABLE (2) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE03 => register_map_control_s.ELINK_BUSY_ENABLE (3) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE04 => register_map_control_s.ELINK_BUSY_ENABLE (4) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE05 => register_map_control_s.ELINK_BUSY_ENABLE (5) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE06 => register_map_control_s.ELINK_BUSY_ENABLE (6) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE07 => register_map_control_s.ELINK_BUSY_ENABLE (7) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE08 => register_map_control_s.ELINK_BUSY_ENABLE (8) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE09 => register_map_control_s.ELINK_BUSY_ENABLE (9) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE10 => register_map_control_s.ELINK_BUSY_ENABLE (10) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE11 => register_map_control_s.ELINK_BUSY_ENABLE (11) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE12 => register_map_control_s.ELINK_BUSY_ENABLE (12) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE13 => register_map_control_s.ELINK_BUSY_ENABLE (13) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE14 => register_map_control_s.ELINK_BUSY_ENABLE (14) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE15 => register_map_control_s.ELINK_BUSY_ENABLE (15) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE16 => register_map_control_s.ELINK_BUSY_ENABLE (16) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE17 => register_map_control_s.ELINK_BUSY_ENABLE (17) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE18 => register_map_control_s.ELINK_BUSY_ENABLE (18) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE19 => register_map_control_s.ELINK_BUSY_ENABLE (19) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE20 => register_map_control_s.ELINK_BUSY_ENABLE (20) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE21 => register_map_control_s.ELINK_BUSY_ENABLE (21) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE22 => register_map_control_s.ELINK_BUSY_ENABLE (22) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_ELINK_BUSY_ENABLE23 => register_map_control_s.ELINK_BUSY_ENABLE (23) <= register_write_data_25_v(56 downto 0); -- Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ when REG_HK_CTRL_I2C => register_map_control_s.HK_CTRL_I2C.CONFIG_TRIG <= register_write_data_25_v(1 downto 1); -- i2c_config_trig
+ register_map_control_s.HK_CTRL_I2C.CLKFREQ_SEL <= register_write_data_25_v(0 downto 0); -- i2c_clkfreq_sel
+ when REG_HK_CTRL_FMC => register_map_control_s.HK_CTRL_FMC.SI5345_INSEL <= register_write_data_25_v(6 downto 5); -- Selects the input clock source
+ -- 0 : FPGA (FMC LA01)
+ -- 1 : FMC OSC (40.079 MHz)
+ -- 2 : FPGA (FMC LA18)
- register_map_control_s.LCB_CTRL (3)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+ register_map_control_s.HK_CTRL_FMC.SI5345_A <= register_write_data_25_v(4 downto 3); -- Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
+ register_map_control_s.HK_CTRL_FMC.SI5345_OE <= register_write_data_25_v(2 downto 2); -- Si5345 active low output enable (0:enable)
+ register_map_control_s.HK_CTRL_FMC.SI5345_RSTN <= register_write_data_25_v(1 downto 1); -- Si5345 active low output enable (0:reset)
+ register_map_control_s.HK_CTRL_FMC.SI5345_SEL <= register_write_data_25_v(0 downto 0); -- Si5345 programming mode
+ -- 1 : I2C mode (default)
+ -- 0 : SPI mode
- register_map_control_s.LCB_CTRL (3)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (3)(1).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (3)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
+ when REG_HK_MON_FMC => register_map_control_s.HK_MON_FMC.SI5345_LOL <= register_write_data_25_v(1 downto 1); -- Si5345 Loss Of Lock pin
+ register_map_control_s.HK_MON_FMC.SI5345_INTR <= register_write_data_25_v(0 downto 0); -- Si5345 Interrupt flagging chip change of status
+ when REG_MMCM_MAIN => register_map_control_s.MMCM_MAIN.LCLK_SEL <= register_write_data_25_v(3 downto 3); -- 1: LCLK
+ -- 0: TTC
+ when REG_I2C_WR => register_map_control_s.I2C_WR.I2C_WREN <= not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL; -- Any write to this register triggers an I2C read or write sequence
+ register_map_control_s.I2C_WR.WRITE_2BYTES <= register_write_data_25_v(24 downto 24); -- Write two bytes
+ register_map_control_s.I2C_WR.DATA_BYTE2 <= register_write_data_25_v(23 downto 16); -- Data byte 2
+ register_map_control_s.I2C_WR.DATA_BYTE1 <= register_write_data_25_v(15 downto 8); -- Data byte 1
+ register_map_control_s.I2C_WR.SLAVE_ADDRESS <= register_write_data_25_v(7 downto 1); -- Slave address
+ register_map_control_s.I2C_WR.READ_NOT_WRITE <= register_write_data_25_v(0 downto 0); -- READ/<o>WRITE</o>
+ when REG_I2C_RD => register_map_control_s.I2C_RD.I2C_RDEN <= not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY; -- Any write to this register pops the last I2C data from the FIFO
+ when REG_INT_TEST => register_map_control_s.INT_TEST.TRIGGER <= "1"; -- Fire a test MSIx interrupt set in IRQ
+ register_map_control_s.INT_TEST.IRQ <= register_write_data_25_v(3 downto 0); -- Set this field to a value equal to the MSIX interrupt to be fired. The write triggers the interrupt immediately.
+ when REG_CONFIG_FLASH_WR => register_map_control_s.CONFIG_FLASH_WR.FAST_WRITE <= register_write_data_25_v(57 downto 57); -- Write command only. Only used for fast programming.
+ register_map_control_s.CONFIG_FLASH_WR.FAST_READ <= register_write_data_25_v(56 downto 56); -- Status reading without command writing. Only used for fast programming.
+ register_map_control_s.CONFIG_FLASH_WR.PAR_CTRL <= register_write_data_25_v(55 downto 55); -- Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
+ register_map_control_s.CONFIG_FLASH_WR.PAR_WR <= register_write_data_25_v(54 downto 53); -- Choose Flash partition. Valid when PAR_CTRL is 1.
+ register_map_control_s.CONFIG_FLASH_WR.FLASH_SEL <= register_write_data_25_v(52 downto 52); -- 1 takes control over flash, 0 gives JTAG control over flash
+ register_map_control_s.CONFIG_FLASH_WR.DO_INIT <= register_write_data_25_v(51 downto 51); -- Untested feature, don't use it yet.
+ register_map_control_s.CONFIG_FLASH_WR.DO_READSTATUS <= register_write_data_25_v(50 downto 50); -- Reads status from flash
+ register_map_control_s.CONFIG_FLASH_WR.DO_CLEARSTATUS <= register_write_data_25_v(49 downto 49); -- Clears status reading from flash, back to normal flash operation
+ register_map_control_s.CONFIG_FLASH_WR.DO_ERASEBLOCK <= register_write_data_25_v(48 downto 48); -- Erased the current block of the flash, this register has to be cleared by software
+ register_map_control_s.CONFIG_FLASH_WR.DO_UNLOCK_BLOCK <= register_write_data_25_v(47 downto 47); -- Unlock writes to the current block, this register has to be cleared by software
+ register_map_control_s.CONFIG_FLASH_WR.DO_READ <= register_write_data_25_v(46 downto 46); -- Reads the 16 bits from current address, this register has to be cleared by software
+ register_map_control_s.CONFIG_FLASH_WR.DO_WRITE <= register_write_data_25_v(45 downto 45); -- Writes the 16 bits to current address, this register has to be cleared by software
+ register_map_control_s.CONFIG_FLASH_WR.DO_READDEVICEID <= register_write_data_25_v(44 downto 44); -- DIN should return 0x0089, this register has to be cleared by software
+ register_map_control_s.CONFIG_FLASH_WR.DO_RESET <= register_write_data_25_v(43 downto 43); -- Can be used in the future, currently disconnected in firmware
+ register_map_control_s.CONFIG_FLASH_WR.ADDRESS <= register_write_data_25_v(42 downto 16); -- Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
+ register_map_control_s.CONFIG_FLASH_WR.WRITE_DATA <= register_write_data_25_v(15 downto 0); -- Value of data to write towards flash
+ when REG_RXUSRCLK_FREQ => register_map_control_s.RXUSRCLK_FREQ.CHANNEL <= register_write_data_25_v(37 downto 32); -- Select the Transceiver channel to measure the clock from.
+ when REG_FELIG_DATA_GEN_CONFIG_00 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (0).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (0).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (0).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (0).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (0).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (0).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_01 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (1).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (1).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (1).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (1).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (1).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (1).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_02 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (2).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (2).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (2).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (2).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (2).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (2).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_03 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (3).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (3).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (3).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (3).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (3).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (3).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_04 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (4).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (4).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (4).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (4).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (4).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (4).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_05 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (5).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (5).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (5).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (5).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (5).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (5).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_DATA_GEN_CONFIG_06 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (6).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (6).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (6).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (6).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (6).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (6).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (3)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (3)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (3)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (3)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_DATA_GEN_CONFIG_07 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (7).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (7).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (7).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (7).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (7).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (7).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_DATA_GEN_CONFIG_08 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (8).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (8).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (8).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (8).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (8).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (8).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_DATA_GEN_CONFIG_09 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (9).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (9).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (9).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (9).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (9).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (9).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_DATA_GEN_CONFIG_10 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (10).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (10).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (10).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (10).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (10).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (10).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_2 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (3)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (3)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (3)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (3)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (3)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (3)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (3)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (3)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (3)(2).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (3)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_DATA_GEN_CONFIG_11 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (11).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (11).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (11).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (11).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (11).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (11).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_DATA_GEN_CONFIG_12 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (12).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (12).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (12).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (12).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (12).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (12).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (3)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (3)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (3)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (3)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_DATA_GEN_CONFIG_13 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (13).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (13).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (13).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (13).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (13).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (13).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_DATA_GEN_CONFIG_14 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (14).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (14).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (14).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (14).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (14).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (14).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_DATA_GEN_CONFIG_15 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (15).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (15).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (15).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (15).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (15).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (15).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_DATA_GEN_CONFIG_16 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (16).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (16).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (16).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (16).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (16).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (16).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_17 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (17).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (17).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (17).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (17).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (17).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (17).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+ end if;
+ when REG_FELIG_DATA_GEN_CONFIG_18 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (18).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (18).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (18).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (18).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (18).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (18).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_3 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (3)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (3)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (3)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (3)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (3)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (3)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (3)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (3)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (3)(3).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (3)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_DATA_GEN_CONFIG_19 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (19).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (19).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (19).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (19).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (19).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (19).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (3)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_DATA_GEN_CONFIG_20 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (20).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (20).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (20).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (20).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (20).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (20).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (3)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (3)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (3)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (3)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_DATA_GEN_CONFIG_21 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (21).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (21).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (21).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (21).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (21).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (21).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (3)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_DATA_GEN_CONFIG_22 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (22).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (22).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (22).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (22).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (22).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (22).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (3)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_DATA_GEN_CONFIG_23 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (23).USERDATA <= register_write_data_25_v(63 downto 48); -- Sets static payload word. When PATTERN_SEL=1.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (23).CHUNK_LENGTH <= register_write_data_25_v(47 downto 32); -- FELIG data generator chunk-length in bytes.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (23).RESET <= register_write_data_25_v(19 downto 15); -- FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (23).SW_BUSY <= register_write_data_25_v(14 downto 10); -- FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (23).DATA_FORMAT <= register_write_data_25_v(9 downto 5); -- FELIG data generator format. 0:8b10b, 1:direct.
+ register_map_control_s.FELIG_DATA_GEN_CONFIG (23).PATTERN_SEL <= register_write_data_25_v(4 downto 0); -- FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (3)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_CONFIG_00 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (0).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (0).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (0).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_R3L1_LINK_03_R3L1_0 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (3)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (3)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (3)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ when REG_FELIG_ELINK_CONFIG_01 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (1).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (1).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (1).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_R3L1_LINK_03_R3L1_1 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (3)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (3)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (3)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ when REG_FELIG_ELINK_CONFIG_02 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (2).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (2).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (2).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_R3L1_LINK_03_R3L1_2 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (3)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (3)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (3)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ when REG_FELIG_ELINK_CONFIG_03 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (3).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (3).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (3).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_R3L1_LINK_03_R3L1_3 =>
- if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (3)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (3)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (3)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ when REG_FELIG_ELINK_CONFIG_04 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (4).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (4).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (4).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (4)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (4)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (4)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (4)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (4)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (4)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (4)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (4)(0).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (4)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_ELINK_CONFIG_05 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (5).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (5).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (5).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_ELINK_CONFIG_06 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (6).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (6).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (6).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (4)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (4)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (4)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (4)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_CONFIG_07 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (7).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (7).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (7).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_CONFIG_08 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (8).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (8).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (8).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_CONFIG_09 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (9).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (9).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (9).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_CONFIG_10 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (10).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (10).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (10).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_11 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (11).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (11).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (11).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
+ end if;
+ when REG_FELIG_ELINK_CONFIG_12 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (12).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (12).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (12).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (4)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (4)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (4)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (4)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (4)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (4)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (4)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (4)(1).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (4)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_ELINK_CONFIG_13 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (13).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (13).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (13).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_ELINK_CONFIG_14 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (14).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (14).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (14).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (4)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (4)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (4)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (4)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_CONFIG_15 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (15).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (15).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (15).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_CONFIG_16 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (16).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (16).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (16).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_CONFIG_17 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (17).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (17).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (17).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_CONFIG_18 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (18).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (18).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (18).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (4)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (4)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (4)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (4)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (4)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (4)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (4)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (4)(2).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (4)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_ELINK_CONFIG_19 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (19).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (19).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (19).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_ELINK_CONFIG_20 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (20).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (20).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (20).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (4)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (4)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (4)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (4)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_CONFIG_21 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (21).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (21).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (21).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_CONFIG_22 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (22).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (22).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (22).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_CONFIG_23 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_CONFIG (23).ENDIAN_MOD <= register_write_data_25_v(39 downto 35); -- FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ register_map_control_s.FELIG_ELINK_CONFIG (23).INPUT_WIDTH <= register_write_data_25_v(34 downto 30); -- FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ register_map_control_s.FELIG_ELINK_CONFIG (23).OUTPUT_WIDTH <= register_write_data_25_v(9 downto 0); -- FELIG elink data output width.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_00 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (0) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (4)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (4)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (4)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (4)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (4)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (4)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (4)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (4)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (4)(3).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (4)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_ELINK_ENABLE_01 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (1) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (4)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_ELINK_ENABLE_02 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (2) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (4)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (4)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (4)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (4)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_03 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (3) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (4)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_04 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (4) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (4)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_05 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (5) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (4)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_06 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (6) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_R3L1_LINK_04_R3L1_0 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (4)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (4)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_04_R3L1_1 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (4)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (4)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_04_R3L1_2 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (4)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (4)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_04_R3L1_3 =>
- if (GBT_NUM > 4 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (4)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (4)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (4)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (5)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (5)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (5)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (5)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (5)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (5)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (5)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (5)(0).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (5)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_ELINK_ENABLE_07 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (7) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_ELINK_ENABLE_08 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (8) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (5)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (5)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (5)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (5)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_09 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (9) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_10 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (10) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_11 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (11) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_12 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (12) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (5)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (5)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (5)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (5)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (5)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (5)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (5)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (5)(1).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (5)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_ELINK_ENABLE_13 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (13) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_ELINK_ENABLE_14 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (14) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (5)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (5)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (5)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (5)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_15 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (15) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_16 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (16) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_17 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (17) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_18 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (18) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (5)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (5)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (5)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (5)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (5)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (5)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (5)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (5)(2).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (5)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_ELINK_ENABLE_19 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (19) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_ELINK_ENABLE_20 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (20) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (5)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (5)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (5)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (5)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_21 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (21) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_22 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (22) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ELINK_ENABLE_23 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ELINK_ENABLE (23) <= register_write_data_25_v(39 downto 0); -- FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_GLOBAL_CONTROL =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_GLOBAL_CONTROL.FAKE_L1A_RATE <= register_write_data_25_v(63 downto 36); -- Sets the internal fake L1 trigger rate. [25ns/LSB]
+ register_map_control_s.FELIG_GLOBAL_CONTROL.PICXO_OFFSET_PPM <= register_write_data_25_v(35 downto 14); -- When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
+ register_map_control_s.FELIG_GLOBAL_CONTROL.TRACK_DATA <= register_write_data_25_v(12 downto 12); -- FELIG GT core control. Must be set to enable normal operation.
+ register_map_control_s.FELIG_GLOBAL_CONTROL.RXUSERRDY <= register_write_data_25_v(11 downto 11); -- FELIG GT core control. Must be set to enable normal operation.
+ register_map_control_s.FELIG_GLOBAL_CONTROL.TXUSERRDY <= register_write_data_25_v(10 downto 10); -- FELIG GT core control. Must be set to enable normal operation.
+ register_map_control_s.FELIG_GLOBAL_CONTROL.AUTO_RESET <= register_write_data_25_v(9 downto 9); -- FELIG GT core control. If set the GT core automatically resets on data error.
+ register_map_control_s.FELIG_GLOBAL_CONTROL.PICXO_RESET <= register_write_data_25_v(8 downto 8); -- FELIG GT core control. Manual PICXO reset.
+ register_map_control_s.FELIG_GLOBAL_CONTROL.GTTX_RESET <= register_write_data_25_v(7 downto 7); -- FELIG GT core control. Manual GT TX reset
+ register_map_control_s.FELIG_GLOBAL_CONTROL.CPLL_RESET <= register_write_data_25_v(6 downto 6); -- FELIG GT core control. Manual CPLL reset.
+ register_map_control_s.FELIG_GLOBAL_CONTROL.X3_X4_OUTPUT_SELECT <= register_write_data_25_v(5 downto 0); -- X3/X4 SMA output source select.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (5)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (5)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (5)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (5)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (5)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (5)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (5)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (5)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (5)(3).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (5)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_LANE_CONFIG_00 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (0).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (0).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (0).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (0).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (0).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (0).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (0).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (0).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (0).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (0).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (0).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (5)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_LANE_CONFIG_01 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (1).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (1).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (1).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (1).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (1).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (1).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (1).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (1).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (1).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (1).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (1).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (5)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (5)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (5)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (5)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_LANE_CONFIG_02 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (2).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (2).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (2).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (2).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (2).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (2).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (2).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (2).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (2).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (2).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (2).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (5)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_LANE_CONFIG_03 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (3).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (3).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (3).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (3).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (3).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (3).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (3).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (3).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (3).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (3).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (3).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (5)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_LANE_CONFIG_04 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (4).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (4).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (4).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (4).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (4).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (4).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (4).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (4).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (4).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (4).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (4).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (5)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_LANE_CONFIG_05 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (5).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (5).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (5).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (5).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (5).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (5).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (5).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (5).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (5).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (5).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (5).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_R3L1_LINK_05_R3L1_0 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (5)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (5)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_05_R3L1_1 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (5)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (5)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_05_R3L1_2 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (5)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (5)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_05_R3L1_3 =>
- if (GBT_NUM > 5 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (5)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (5)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (5)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (6)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (6)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (6)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (6)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (6)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (6)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (6)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (6)(0).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (6)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_LANE_CONFIG_06 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (6).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (6).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (6).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (6).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (6).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (6).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (6).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (6).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (6).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (6).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (6).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_LANE_CONFIG_07 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (7).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (7).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (7).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (7).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (7).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (7).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (7).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (7).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (7).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (7).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (7).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (6)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (6)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (6)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (6)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_LANE_CONFIG_08 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (8).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (8).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (8).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (8).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (8).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (8).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (8).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (8).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (8).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (8).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (8).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_LANE_CONFIG_09 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (9).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (9).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (9).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (9).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (9).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (9).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (9).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (9).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (9).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (9).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (9).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_LANE_CONFIG_10 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (10).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (10).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (10).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (10).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (10).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (10).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (10).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (10).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (10).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (10).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (10).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_LANE_CONFIG_11 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (11).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (11).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (11).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (11).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (11).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (11).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (11).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (11).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (11).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (11).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (11).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (6)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (6)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (6)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (6)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (6)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (6)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (6)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (6)(1).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (6)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_LANE_CONFIG_12 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (12).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (12).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (12).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (12).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (12).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (12).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (12).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (12).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (12).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (12).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (12).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_LANE_CONFIG_13 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (13).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (13).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (13).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (13).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (13).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (13).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (13).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (13).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (13).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (13).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (13).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (6)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (6)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (6)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (6)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_LANE_CONFIG_14 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (14).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (14).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (14).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (14).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (14).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (14).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (14).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (14).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (14).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (14).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (14).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_LANE_CONFIG_15 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (15).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (15).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (15).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (15).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (15).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (15).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (15).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (15).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (15).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (15).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (15).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_LANE_CONFIG_16 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (16).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (16).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (16).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (16).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (16).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (16).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (16).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (16).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (16).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (16).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (16).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+ end if;
+ when REG_FELIG_LANE_CONFIG_17 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (17).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (17).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (17).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (17).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (17).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (17).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (17).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (17).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (17).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (17).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (17).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_LANE_CONFIG_18 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (18).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (18).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (18).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (18).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (18).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (18).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (18).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (18).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (18).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (18).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (18).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (6)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (6)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (6)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (6)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (6)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (6)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (6)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (6)(2).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (6)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_LANE_CONFIG_19 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (19).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (19).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (19).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (19).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (19).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (19).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (19).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (19).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (19).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (19).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (19).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_LANE_CONFIG_20 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (20).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (20).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (20).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (20).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (20).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (20).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (20).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (20).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (20).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (20).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (20).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (6)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (6)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (6)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (6)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_LANE_CONFIG_21 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (21).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (21).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (21).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (21).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (21).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (21).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (21).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (21).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (21).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (21).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (21).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_LANE_CONFIG_22 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (22).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (22).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (22).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (22).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (22).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (22).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (22).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (22).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (22).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (22).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (22).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_LANE_CONFIG_23 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_LANE_CONFIG (23).B_CH_BIT_SEL <= register_write_data_25_v(63 downto 42); -- When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ register_map_control_s.FELIG_LANE_CONFIG (23).A_CH_BIT_SEL <= register_write_data_25_v(41 downto 35); -- Selects the bit from the received FELIX data from which to extract the L1A.
+ register_map_control_s.FELIG_LANE_CONFIG (23).LB_FIFO_DELAY <= register_write_data_25_v(34 downto 30); -- When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ register_map_control_s.FELIG_LANE_CONFIG (23).ELINK_SYNC <= register_write_data_25_v(7 downto 7); -- When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ register_map_control_s.FELIG_LANE_CONFIG (23).PICXO_OFFEST_EN <= register_write_data_25_v(6 downto 6); -- FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ register_map_control_s.FELIG_LANE_CONFIG (23).PI_HOLD <= register_write_data_25_v(5 downto 5); -- FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ register_map_control_s.FELIG_LANE_CONFIG (23).GBT_LB_ENABLE <= register_write_data_25_v(4 downto 4); -- FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (23).GBH_LB_ENABLE <= register_write_data_25_v(3 downto 3); -- FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ register_map_control_s.FELIG_LANE_CONFIG (23).L1A_SOURCE <= register_write_data_25_v(2 downto 2); -- FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ register_map_control_s.FELIG_LANE_CONFIG (23).GBT_EMU_SOURCE <= register_write_data_25_v(1 downto 1); -- FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ register_map_control_s.FELIG_LANE_CONFIG (23).FG_SOURCE <= register_write_data_25_v(0 downto 0); -- FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_MON_FREQ_GLOBAL =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_MON_FREQ_GLOBAL.XTAL_100MHZ <= register_write_data_25_v(63 downto 32); -- FELIG local oscillator frequency[Hz].
+ register_map_control_s.FELIG_MON_FREQ_GLOBAL.CLK_41_667MHZ <= register_write_data_25_v(31 downto 0); -- FELIG PCIE MGTREFCLK frequency[Hz].
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (6)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (6)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (6)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (6)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (6)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (6)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (6)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (6)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (6)(3).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (6)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_RESET =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_RESET.LB_FIFO <= register_write_data_25_v(63 downto 48); -- One bit per lane. When set to 1, resets all loopback FIFOs.
+ register_map_control_s.FELIG_RESET.FRAMEGEN <= register_write_data_25_v(47 downto 24); -- One bit per lane. When set to 1, resets all FELIG link checking logic.
+ register_map_control_s.FELIG_RESET.LANE <= register_write_data_25_v(23 downto 0); -- One bit per lane. When set to 1, resets all FELIG lane logic.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (6)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_RX_SLIDE_RESET =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_RX_SLIDE_RESET <= register_write_data_25_v(23 downto 0); -- One bit per lane. When set to 1, resets the gbt rx slide counter.
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (6)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (6)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (6)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (6)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_00 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(0).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(0).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (6)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_01 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(1).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(1).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (6)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_02 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(2).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(2).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (6)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_03 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(3).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(3).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_R3L1_LINK_06_R3L1_0 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (6)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (6)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_06_R3L1_1 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (6)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (6)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_06_R3L1_2 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (6)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (6)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_06_R3L1_3 =>
- if (GBT_NUM > 6 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (6)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (6)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (6)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (7)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (7)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (7)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (7)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (7)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (7)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (7)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (7)(0).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (7)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_04 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(4).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(4).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_05 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(5).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(5).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (7)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (7)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (7)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (7)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_06 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(6).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(6).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_07 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(7).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(7).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_08 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(8).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(8).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_09 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(9).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(9).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (7)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (7)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (7)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (7)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (7)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (7)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (7)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (7)(1).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (7)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_10 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(10).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(10).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_11 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(11).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(11).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (7)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (7)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (7)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (7)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_12 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(12).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(12).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_13 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(13).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(13).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_14 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(14).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(14).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_15 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(15).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(15).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (7)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (7)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (7)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (7)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (7)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (7)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (7)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (7)(2).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (7)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_16 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(16).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(16).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_17 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(17).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(17).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (7)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (7)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (7)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (7)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_18 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(18).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(18).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_19 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(19).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(19).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_20 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(20).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(20).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_21 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(21).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(21).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (7)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (7)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- register_map_control_s.LCB_CTRL (7)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (7)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (7)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (7)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- register_map_control_s.LCB_CTRL (7)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- register_map_control_s.LCB_CTRL (7)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (7)(3).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (7)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_22 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(22).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(22).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (7)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ when REG_FELIG_ITK_STRIPS_DATA_GEN_CONFIG_23 =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(23).ITKS_FIFO_CTL <= register_write_data_25_v(19 downto 17); -- data fifo control 2:rst 1:rd 0:wr.
+ register_map_control_s.FELIG_ITK_STRIPS_DATA_GEN_CONFIG(23).ITKS_FIFO_DATA <= register_write_data_25_v(16 downto 0); -- itks emu data 16:last word 15-0:data word
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (7)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
-
- register_map_control_s.HCC_ABC_MASK_E_C (7)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (7)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.HCC_ABC_MASK_E_C (7)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FMEMU_EVENT_INFO =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FMEMU_EVENT_INFO.L1ID <= register_write_data_25_v(63 downto 32); -- 32b field to show L1ID
+ register_map_control_s.FMEMU_EVENT_INFO.BCID <= register_write_data_25_v(31 downto 0); -- 32b field to show BCID
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_B_8 (7)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FMEMU_COUNTERS =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FMEMU_COUNTERS.WORD_CNT <= register_write_data_25_v(63 downto 48); -- Number of 32b words in one chunk
+ register_map_control_s.FMEMU_COUNTERS.IDLE_CNT <= register_write_data_25_v(47 downto 32); -- Minimum number of idles between chunks
+ register_map_control_s.FMEMU_COUNTERS.L1A_CNT <= register_write_data_25_v(31 downto 16); -- Number of chunks to send if not in TTC mode
+ register_map_control_s.FMEMU_COUNTERS.BUSY_TH_HIGH <= register_write_data_25_v(15 downto 8); -- Assert BUSY-ON above this threshold
+ register_map_control_s.FMEMU_COUNTERS.BUSY_TH_LOW <= register_write_data_25_v(7 downto 0); -- De-assert BUSY-ON below this threshold
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
+ when REG_FMEMU_CONTROL =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FMEMU_CONTROL.L1A_BITNR <= register_write_data_25_v(63 downto 56); -- Bitfield for L1A in TTC frame
+ register_map_control_s.FMEMU_CONTROL.XONXOFF_BITNR <= register_write_data_25_v(55 downto 48); -- Bitfield for Xon/Xoff in TTC frame
+ register_map_control_s.FMEMU_CONTROL.EMU_START <= register_write_data_25_v(47 downto 47); -- Start emulator functionality
+ register_map_control_s.FMEMU_CONTROL.TTC_MODE <= register_write_data_25_v(46 downto 46); -- Control the emulator by TTC input or by RegMap (1/0)
+ register_map_control_s.FMEMU_CONTROL.XONXOFF <= register_write_data_25_v(45 downto 45); -- Debug Xon/Xoff functionality (1/0)
+ register_map_control_s.FMEMU_CONTROL.INLC_CRC32 <= register_write_data_25_v(44 downto 44); -- 0: No checksum
+ -- 1: Append the data with a CRC32
- register_map_control_s.LCB_ABC_MASK_7_4 (7)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
+ register_map_control_s.FMEMU_CONTROL.BCR <= register_write_data_25_v(43 downto 43); -- Reset BCID to 0
+ register_map_control_s.FMEMU_CONTROL.ECR <= register_write_data_25_v(42 downto 42); -- Reset L1ID to 0
+ register_map_control_s.FMEMU_CONTROL.DATA_SRC_SEL <= register_write_data_25_v(41 downto 41); -- Data source select
+ -- 0: Data input comes from EMURAM
+ -- 1: Data input comes from PCIe
+ register_map_control_s.FMEMU_CONTROL.FFU_FM_EMU_T <= register_write_data_25_v(31 downto 16); -- For Future Use (trigger registers)
+ register_map_control_s.FMEMU_CONTROL.FFU_FM_EMU_W <= register_write_data_25_v(15 downto 0); -- For Future Use (write registers)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- register_map_control_s.LCB_ABC_MASK_3_0 (7)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
+ when REG_FMEMU_RANDOM_RAM_ADDR =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FMEMU_RANDOM_RAM_ADDR <= register_write_data_25_v(9 downto 0); -- Controls the address of the ramblock for the random number generator
+ end if;
+ when REG_FMEMU_RANDOM_RAM =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FMEMU_RANDOM_RAM.WE <= "1"; -- Any write to this register (DATA) triggers a write to the ramblock
+ register_map_control_s.FMEMU_RANDOM_RAM.CHANNEL_SELECT <= register_write_data_25_v(39 downto 16); -- Enable write enable only for the selected channel
+ register_map_control_s.FMEMU_RANDOM_RAM.DATA <= register_write_data_25_v(15 downto 0); -- DATA field to be written to FMEMU_RANDOM_RAM_ADDR
+ end if;
+ when REG_FMEMU_RANDOM_CONTROL =>
+ if EMU_GENERATE_REGS then
+ register_map_control_s.FMEMU_RANDOM_CONTROL.SELECT_RANDOM <= register_write_data_25_v(20 downto 20); -- 1 enables the random chunk length, 0 uses a constant chunk length
+ register_map_control_s.FMEMU_RANDOM_CONTROL.SEED <= register_write_data_25_v(19 downto 10); -- Seed for the random number generator, should not be 0
+ register_map_control_s.FMEMU_RANDOM_CONTROL.POLYNOMIAL <= register_write_data_25_v(9 downto 0); -- POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
end if;
- when REG_CR_ITK_R3L1_LINK_07_R3L1_0 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (7)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (7)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_07_R3L1_1 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (7)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (7)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_07_R3L1_2 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (7)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (7)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_07_R3L1_3 =>
- if (GBT_NUM > 7 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (7)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (7)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (7)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (8)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_WISHBONE_CONTROL => register_map_control_s.WISHBONE_CONTROL.WRITE_NOT_READ <= register_write_data_25_v(32 downto 32); -- wishbone write command wishbone read command
+ register_map_control_s.WISHBONE_CONTROL.ADDRESS <= register_write_data_25_v(31 downto 0); -- Slave address for Wishbone bus
+ when REG_WISHBONE_WRITE => register_map_control_s.WISHBONE_WRITE.WRITE_ENABLE <= "1"; -- Any write to this register triggers a write to the Wupper to Wishbone fifo
+ register_map_control_s.WISHBONE_WRITE.DATA <= register_write_data_25_v(31 downto 0); -- Wishbone
+ when REG_WISHBONE_READ => register_map_control_s.WISHBONE_READ.READ_ENABLE <= "1"; -- Any write to this register triggers a read from the Wishbone to Wupper fifo
+ when REG_GLOBAL_STRIPS_CONFIG => register_map_control_s.GLOBAL_STRIPS_CONFIG.TEST_MODULE_MASK <= register_write_data_25_v(15 downto 11); -- (for tests only) contains R3 mask for the simulated trigger data
+ register_map_control_s.GLOBAL_STRIPS_CONFIG.TEST_R3L1_TAG <= register_write_data_25_v(10 downto 4); -- (for tests only) contains R3 or L1 tag for the simulated trigger data
+ register_map_control_s.GLOBAL_STRIPS_CONFIG.TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(1 downto 1); -- Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR. TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work. (See also BC_START, and BC_STOP fields)
+ when REG_GLOBAL_TRICKLE_TRIGGER => register_map_control_s.GLOBAL_TRICKLE_TRIGGER <= "1"; -- writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (0)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (0)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (8)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (8)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (8)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (8)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (0)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (0)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (0)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (0)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (8)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (0)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (8)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (8)(0).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (8)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (0)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (0)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (0)(0) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (8)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (8)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (8)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (8)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (8)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (0)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (0)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (8)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (8)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (8)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (8)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (0)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (0)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (0)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (0)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (8)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (0)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (8)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (8)(1).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (8)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (0)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (0)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (0)(1) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (8)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (8)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (8)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (8)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (8)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (0)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (0)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (8)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (8)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (8)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (8)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (0)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (0)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (0)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (0)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (8)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (0)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (8)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (8)(2).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (8)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (0)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (0)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (0)(2) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (8)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (8)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (8)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (8)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (8)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (8)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (0)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (0)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (8)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (8)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (8)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (8)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (0)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (0)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (0)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (0)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (8)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (0)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (8)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (8)(3).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (8)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (0)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (0)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (0)(3) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (8)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (0)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (8)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (8)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (8)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (8)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (0)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (8)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (0)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (8)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (0)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (8)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (0)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_R3L1_LINK_08_R3L1_0 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (8)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (8)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_08_R3L1_1 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (8)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (8)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_08_R3L1_2 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (8)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (8)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_08_R3L1_3 =>
- if (GBT_NUM > 8 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (8)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (8)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (8)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (9)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_CR_ITK_R3L1_LINK_00_R3L1_0 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (0)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (0)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (0)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_00_R3L1_1 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (0)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (0)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (0)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_00_R3L1_2 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (0)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (0)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (0)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_00_R3L1_3 =>
+ if (GBT_NUM > 0 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (0)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (0)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (0)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (1)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (1)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (9)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (9)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (9)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (9)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (1)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (1)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (1)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (1)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (9)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (1)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (9)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (9)(0).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (9)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (1)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (1)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (1)(0) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (9)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (9)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (9)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (9)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (9)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (1)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (1)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (9)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (9)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (9)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (9)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (1)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (1)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (1)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (1)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (9)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (1)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (9)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (9)(1).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (9)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (1)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (1)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (1)(1) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (9)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (9)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (9)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (9)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (9)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (1)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (1)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (9)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (9)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (9)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (9)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (1)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (1)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (1)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (1)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (9)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (1)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (9)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (9)(2).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (9)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (1)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (1)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (1)(2) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (9)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (9)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (9)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (9)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (9)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (9)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (1)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (1)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (9)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (9)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (9)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (9)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (1)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (1)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (1)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (1)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (9)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (1)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (9)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (9)(3).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (9)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (1)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (1)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (1)(3) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (9)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (1)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (9)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (9)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (9)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (9)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (1)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (9)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (1)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (9)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (1)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (9)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (1)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_R3L1_LINK_09_R3L1_0 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (9)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (9)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_09_R3L1_1 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (9)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (9)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_09_R3L1_2 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (9)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (9)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_09_R3L1_3 =>
- if (GBT_NUM > 9 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (9)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (9)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (9)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (10)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_CR_ITK_R3L1_LINK_01_R3L1_0 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (1)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (1)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (1)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_01_R3L1_1 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (1)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (1)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (1)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_01_R3L1_2 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (1)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (1)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (1)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_01_R3L1_3 =>
+ if (GBT_NUM > 1 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (1)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (1)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (1)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (2)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (2)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (10)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (10)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (10)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (10)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (2)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (2)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (2)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (2)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (10)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (2)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (10)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (10)(0).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (10)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (2)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (2)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (2)(0) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (10)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (10)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (10)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (10)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (10)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (2)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (2)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (10)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (10)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (10)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (10)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (2)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (2)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (2)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (2)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (10)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (2)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (10)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (10)(1).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (10)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (2)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (2)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (2)(1) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (10)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (10)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (10)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (10)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (10)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (2)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (2)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (10)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (10)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (10)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (10)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (2)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (2)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (2)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (2)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (10)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (2)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (10)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (10)(2).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (10)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (2)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (2)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (2)(2) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (10)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (10)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (10)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (10)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (10)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (10)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (2)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (2)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (10)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (10)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (10)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (10)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (2)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (2)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (2)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (2)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (10)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (2)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (10)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (10)(3).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (10)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (2)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (2)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (2)(3) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (10)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (2)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (10)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (10)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (10)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (10)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (2)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (10)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (2)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (10)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (2)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (10)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (2)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_R3L1_LINK_10_R3L1_0 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (10)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (10)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_10_R3L1_1 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (10)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (10)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_10_R3L1_2 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (10)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (10)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_R3L1_LINK_10_R3L1_3 =>
- if (GBT_NUM > 10 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (10)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (10)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (10)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
- end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (11)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_CR_ITK_R3L1_LINK_02_R3L1_0 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (2)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (2)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (2)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_02_R3L1_1 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (2)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (2)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (2)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_02_R3L1_2 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (2)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (2)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (2)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_R3L1_LINK_02_R3L1_3 =>
+ if (GBT_NUM > 2 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (2)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (2)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (2)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (3)(0).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (3)(0).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (11)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (11)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (11)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (11)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (3)(0).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (3)(0).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (3)(0).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (3)(0).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (11)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (3)(0).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (11)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (11)(0).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (11)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (3)(0).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (3)(0).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_0 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (3)(0) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(0).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(0).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(0).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(0).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_0 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (11)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(0).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (11)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(0).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (11)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(0).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (11)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(0).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_0 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(0).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(0).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(0).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(0).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_0 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(0).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(0).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(0).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(0).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_0 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(0).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(0).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(0).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(0).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (11)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (3)(1).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (3)(1).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (11)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (11)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (11)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (11)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (3)(1).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (3)(1).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (3)(1).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (3)(1).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (11)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (3)(1).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (11)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (11)(1).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (11)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (3)(1).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (3)(1).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_1 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (3)(1) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(1).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(1).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(1).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(1).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_1 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (11)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(1).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (11)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(1).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (11)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(1).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (11)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(1).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_1 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(1).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(1).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(1).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(1).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_1 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(1).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(1).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(1).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(1).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_1 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(1).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(1).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(1).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(1).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (11)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (3)(2).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (3)(2).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (11)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (11)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (11)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (11)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (3)(2).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (3)(2).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (3)(2).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (3)(2).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (11)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (3)(2).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (11)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (11)(2).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (11)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (3)(2).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (3)(2).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_2 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (3)(2) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(2).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(2).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(2).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(2).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_2 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (11)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(2).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (11)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(2).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (11)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(2).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (11)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(2).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_2 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(2).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(2).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(2).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(2).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_2 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(2).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(2).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(2).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(2).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_2 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(2).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(2).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(2).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(2).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_CTRL (11)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
- register_map_control_s.LCB_CTRL (11)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_CTRL (3)(3).L0A_BCR_DELAY <= register_write_data_25_v(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
+ register_map_control_s.LCB_CTRL (3)(3).L0A_FRAME_DELAY <= register_write_data_25_v(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- register_map_control_s.LCB_CTRL (11)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
- register_map_control_s.LCB_CTRL (11)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (11)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
- register_map_control_s.LCB_CTRL (11)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
+ register_map_control_s.LCB_CTRL (3)(3).FRAME_PHASE <= register_write_data_25_v(33 downto 32); -- phase of LCB frame with respect to TTC BCR signal
+ register_map_control_s.LCB_CTRL (3)(3).TRICKLE_BC_START <= register_write_data_25_v(31 downto 20); -- Determines the start of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (3)(3).TRICKLE_BC_STOP <= register_write_data_25_v(19 downto 8); -- Determines the end of the allowed BC interval for low-priority LCB frames
+ register_map_control_s.LCB_CTRL (3)(3).LCB_DESTINATION_MUX <= register_write_data_25_v(5 downto 4); -- Determines where the elink data is sent to:
-- 00: command decoder (use same command encoding format as trickle configuration)
-- 01: trickle memory (see phase2 documentation for command encoding format)
-- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
-- 11: (invalid, don't use)
- register_map_control_s.LCB_CTRL (11)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
+ register_map_control_s.LCB_CTRL (3)(3).TRICKLE_TRIG_RUN <= register_write_data_25_v(3 downto 3); -- if enabled, trickle configuration is sent out continuously to the front-end
-- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- register_map_control_s.LCB_CTRL (11)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- register_map_control_s.LCB_CTRL (11)(3).TRICKLE_TRIG_PULSE <= "1"; -- writing to this register issues a single trickle trigger
- register_map_control_s.LCB_CTRL (11)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
+ register_map_control_s.LCB_CTRL (3)(3).TTC_L0A_ENABLE <= register_write_data_25_v(2 downto 2); -- enable generating L0A frames in response to TTC system signals
+ register_map_control_s.LCB_CTRL (3)(3).TTC_GENERATE_GATING_ENABLE <= register_write_data_25_v(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_3 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.TRICKLE_TRIGGER (3)(3) <= "1"; -- writing to this register issues a single trickle trigger
+ end if;
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(3).MOVE_WRITE_PTR <= "1"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
- register_map_control_s.LCB_TRICKLE_CONFIG (11)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(3).WRITE_PTR <= register_write_data_25_v(47 downto 32); -- Trickle configuration memory write pointer
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(3).VALID_DATA_START <= register_write_data_25_v(31 downto 16); -- Start address of trickle configuration in trickle memory
+ register_map_control_s.LCB_TRICKLE_CONFIG (3)(3).VALID_DATA_END <= register_write_data_25_v(15 downto 0); -- Stop address of trickle configuration in trickle memory (last valid byte)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_3 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.HCC_ABC_MASK_E_C (11)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(3).HCC_MASK <= register_write_data_25_v(63 downto 48); -- HCC* module mask
- register_map_control_s.HCC_ABC_MASK_E_C (11)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(3).ABC_MASK_HCC_E <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xE
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (11)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(3).ABC_MASK_HCC_D <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0xD
-- mask(i) <=> (abc_id = i)
- register_map_control_s.HCC_ABC_MASK_E_C (11)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
+ register_map_control_s.HCC_ABC_MASK_E_C (3)(3).ABC_MASK_HCC_C <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0xC
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_3 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(3).ABC_MASK_HCC_B <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(3).ABC_MASK_HCC_A <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0xA
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(3).ABC_MASK_HCC_9 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x9
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_B_8 (11)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
+ register_map_control_s.LCB_ABC_MASK_B_8 (3)(3).ABC_MASK_HCC_8 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x8
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_3 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(3).ABC_MASK_HCC_7 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(3).ABC_MASK_HCC_6 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x6
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(3).ABC_MASK_HCC_5 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x5
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_7_4 (11)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
+ register_map_control_s.LCB_ABC_MASK_7_4 (3)(3).ABC_MASK_HCC_4 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x4
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_3 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
+ when REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(3).ABC_MASK_HCC_3 <= register_write_data_25_v(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(3).ABC_MASK_HCC_2 <= register_write_data_25_v(47 downto 32); -- Masks register commands with destination hcc_id = 0x2
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(3).ABC_MASK_HCC_1 <= register_write_data_25_v(31 downto 16); -- Masks register commands with destination hcc_id = 0x1
-- mask(i) <=> (abc_id = i)
- register_map_control_s.LCB_ABC_MASK_3_0 (11)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
+ register_map_control_s.LCB_ABC_MASK_3_0 (3)(3).ABC_MASK_HCC_0 <= register_write_data_25_v(15 downto 0); -- Masks register commands with destination hcc_id = 0x0
-- mask(i) <=> (abc_id = i)
end if;
- when REG_CR_ITK_R3L1_LINK_11_R3L1_0 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (11)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (11)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ when REG_CR_ITK_R3L1_LINK_03_R3L1_0 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (3)(0).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (3)(0).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (3)(0).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
end if;
- when REG_CR_ITK_R3L1_LINK_11_R3L1_1 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (11)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (11)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ when REG_CR_ITK_R3L1_LINK_03_R3L1_1 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (3)(1).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (3)(1).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (3)(1).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
end if;
- when REG_CR_ITK_R3L1_LINK_11_R3L1_2 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (11)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (11)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ when REG_CR_ITK_R3L1_LINK_03_R3L1_2 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (3)(2).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (3)(2).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (3)(2).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
end if;
- when REG_CR_ITK_R3L1_LINK_11_R3L1_3 =>
- if (GBT_NUM > 11 and FIRMWARE_MODE = 5) then
- register_map_control_s.R3L1_CTRL (11)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
- register_map_control_s.R3L1_CTRL (11)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
- register_map_control_s.R3L1_CTRL (11)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
+ when REG_CR_ITK_R3L1_LINK_03_R3L1_3 =>
+ if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
+ register_map_control_s.R3L1_CTRL (3)(3).FRAME_PHASE <= register_write_data_25_v(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
+ register_map_control_s.R3L1_CTRL (3)(3).L1_ENABLE <= register_write_data_25_v(1 downto 1); -- enables sending TTC L1 signals to the front-end
+ register_map_control_s.R3L1_CTRL (3)(3).R3_ENABLE <= register_write_data_25_v(0 downto 0); -- enables sending RoI R3 signals to the front-end
end if;
+ when REG_STRIPS_R3_TRIGGER => register_map_control_s.STRIPS_R3_TRIGGER <= "1"; -- (for tests only) simulate R3 trigger (issues 4-5 sequential triggers)
+ when REG_STRIPS_L1_TRIGGER => register_map_control_s.STRIPS_L1_TRIGGER <= "1"; -- (for tests only) simulate L1 trigger (issues 4-5 sequential triggers)
+ when REG_STRIPS_R3L1_TRIGGER => register_map_control_s.STRIPS_R3L1_TRIGGER <= "1"; -- (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)
when REG_MROD_CTRL =>
if MROD_GENERATE_REGS = true then
register_map_control_s.MROD_CTRL.OPTIONS <= register_write_data_25_v(15 downto 4); -- Extra options for MROD
diff --git a/sources/templates/pcie_package.vhd b/sources/templates/pcie_package.vhd
index 53aa1aee069b66ca3f3220319fb012111aadccf7..6d426c7aed03ec27280412b7974332846be984ed 100644
--- a/sources/templates/pcie_package.vhd
+++ b/sources/templates/pcie_package.vhd
@@ -1297,392 +1297,156 @@ package pcie_package is
--** ITK_STRIPS_CTRL
constant REG_GLOBAL_STRIPS_CONFIG : std_logic_vector(19 downto 0) := x"0d000";
+ constant REG_GLOBAL_TRICKLE_TRIGGER : std_logic_vector(19 downto 0) := x"0d010";
--** ITK_STRIPS_GBT
--** ITK_STRIPS_LCB_LINKS
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_0 : std_logic_vector(19 downto 0) := x"0d010";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0d020";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0d030";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0d040";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0d050";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0d060";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_1 : std_logic_vector(19 downto 0) := x"0d070";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0d080";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0d090";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0d0a0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0d0b0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0d0c0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_2 : std_logic_vector(19 downto 0) := x"0d0d0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0d0e0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0d0f0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0d100";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0d110";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0d120";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_3 : std_logic_vector(19 downto 0) := x"0d130";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0d140";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0d150";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0d160";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0d170";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0d180";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_0 : std_logic_vector(19 downto 0) := x"0d020";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_0 : std_logic_vector(19 downto 0) := x"0d030";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0d040";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0d050";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0d060";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0d070";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0d080";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_1 : std_logic_vector(19 downto 0) := x"0d090";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_1 : std_logic_vector(19 downto 0) := x"0d0a0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0d0b0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0d0c0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0d0d0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0d0e0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0d0f0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_2 : std_logic_vector(19 downto 0) := x"0d100";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_2 : std_logic_vector(19 downto 0) := x"0d110";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0d120";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0d130";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0d140";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0d150";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0d160";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_3 : std_logic_vector(19 downto 0) := x"0d170";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_3 : std_logic_vector(19 downto 0) := x"0d180";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0d190";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0d1a0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0d1b0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0d1c0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0d1d0";
--** ITK_STRIPS_R3L1_LINKS
- constant REG_CR_ITK_R3L1_LINK_00_R3L1_0 : std_logic_vector(19 downto 0) := x"0d190";
- constant REG_CR_ITK_R3L1_LINK_00_R3L1_1 : std_logic_vector(19 downto 0) := x"0d1a0";
- constant REG_CR_ITK_R3L1_LINK_00_R3L1_2 : std_logic_vector(19 downto 0) := x"0d1b0";
- constant REG_CR_ITK_R3L1_LINK_00_R3L1_3 : std_logic_vector(19 downto 0) := x"0d1c0";
+ constant REG_CR_ITK_R3L1_LINK_00_R3L1_0 : std_logic_vector(19 downto 0) := x"0d1e0";
+ constant REG_CR_ITK_R3L1_LINK_00_R3L1_1 : std_logic_vector(19 downto 0) := x"0d1f0";
+ constant REG_CR_ITK_R3L1_LINK_00_R3L1_2 : std_logic_vector(19 downto 0) := x"0d200";
+ constant REG_CR_ITK_R3L1_LINK_00_R3L1_3 : std_logic_vector(19 downto 0) := x"0d210";
--** ITK_STRIPS_LCB_LINKS
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_0 : std_logic_vector(19 downto 0) := x"0d1d0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0d1e0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0d1f0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0d200";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0d210";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0d220";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_1 : std_logic_vector(19 downto 0) := x"0d230";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0d240";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0d250";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0d260";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0d270";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0d280";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_2 : std_logic_vector(19 downto 0) := x"0d290";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0d2a0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0d2b0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0d2c0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0d2d0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0d2e0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_3 : std_logic_vector(19 downto 0) := x"0d2f0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0d300";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0d310";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0d320";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0d330";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0d340";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_0 : std_logic_vector(19 downto 0) := x"0d220";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_0 : std_logic_vector(19 downto 0) := x"0d230";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0d240";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0d250";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0d260";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0d270";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0d280";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_1 : std_logic_vector(19 downto 0) := x"0d290";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_1 : std_logic_vector(19 downto 0) := x"0d2a0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0d2b0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0d2c0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0d2d0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0d2e0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0d2f0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_2 : std_logic_vector(19 downto 0) := x"0d300";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_2 : std_logic_vector(19 downto 0) := x"0d310";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0d320";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0d330";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0d340";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0d350";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0d360";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_3 : std_logic_vector(19 downto 0) := x"0d370";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_3 : std_logic_vector(19 downto 0) := x"0d380";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0d390";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0d3a0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0d3b0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0d3c0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0d3d0";
--** ITK_STRIPS_R3L1_LINKS
- constant REG_CR_ITK_R3L1_LINK_01_R3L1_0 : std_logic_vector(19 downto 0) := x"0d350";
- constant REG_CR_ITK_R3L1_LINK_01_R3L1_1 : std_logic_vector(19 downto 0) := x"0d360";
- constant REG_CR_ITK_R3L1_LINK_01_R3L1_2 : std_logic_vector(19 downto 0) := x"0d370";
- constant REG_CR_ITK_R3L1_LINK_01_R3L1_3 : std_logic_vector(19 downto 0) := x"0d380";
+ constant REG_CR_ITK_R3L1_LINK_01_R3L1_0 : std_logic_vector(19 downto 0) := x"0d3e0";
+ constant REG_CR_ITK_R3L1_LINK_01_R3L1_1 : std_logic_vector(19 downto 0) := x"0d3f0";
+ constant REG_CR_ITK_R3L1_LINK_01_R3L1_2 : std_logic_vector(19 downto 0) := x"0d400";
+ constant REG_CR_ITK_R3L1_LINK_01_R3L1_3 : std_logic_vector(19 downto 0) := x"0d410";
--** ITK_STRIPS_LCB_LINKS
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_0 : std_logic_vector(19 downto 0) := x"0d390";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0d3a0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0d3b0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0d3c0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0d3d0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0d3e0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_1 : std_logic_vector(19 downto 0) := x"0d3f0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0d400";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0d410";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0d420";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0d430";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0d440";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_2 : std_logic_vector(19 downto 0) := x"0d450";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0d460";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0d470";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0d480";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0d490";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0d4a0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_3 : std_logic_vector(19 downto 0) := x"0d4b0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0d4c0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0d4d0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0d4e0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0d4f0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0d500";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_0 : std_logic_vector(19 downto 0) := x"0d420";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_0 : std_logic_vector(19 downto 0) := x"0d430";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0d440";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0d450";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0d460";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0d470";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0d480";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_1 : std_logic_vector(19 downto 0) := x"0d490";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_1 : std_logic_vector(19 downto 0) := x"0d4a0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0d4b0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0d4c0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0d4d0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0d4e0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0d4f0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_2 : std_logic_vector(19 downto 0) := x"0d500";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_2 : std_logic_vector(19 downto 0) := x"0d510";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0d520";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0d530";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0d540";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0d550";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0d560";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_3 : std_logic_vector(19 downto 0) := x"0d570";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_3 : std_logic_vector(19 downto 0) := x"0d580";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0d590";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0d5a0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0d5b0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0d5c0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0d5d0";
--** ITK_STRIPS_R3L1_LINKS
- constant REG_CR_ITK_R3L1_LINK_02_R3L1_0 : std_logic_vector(19 downto 0) := x"0d510";
- constant REG_CR_ITK_R3L1_LINK_02_R3L1_1 : std_logic_vector(19 downto 0) := x"0d520";
- constant REG_CR_ITK_R3L1_LINK_02_R3L1_2 : std_logic_vector(19 downto 0) := x"0d530";
- constant REG_CR_ITK_R3L1_LINK_02_R3L1_3 : std_logic_vector(19 downto 0) := x"0d540";
+ constant REG_CR_ITK_R3L1_LINK_02_R3L1_0 : std_logic_vector(19 downto 0) := x"0d5e0";
+ constant REG_CR_ITK_R3L1_LINK_02_R3L1_1 : std_logic_vector(19 downto 0) := x"0d5f0";
+ constant REG_CR_ITK_R3L1_LINK_02_R3L1_2 : std_logic_vector(19 downto 0) := x"0d600";
+ constant REG_CR_ITK_R3L1_LINK_02_R3L1_3 : std_logic_vector(19 downto 0) := x"0d610";
--** ITK_STRIPS_LCB_LINKS
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_0 : std_logic_vector(19 downto 0) := x"0d550";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0d560";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0d570";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0d580";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0d590";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0d5a0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_1 : std_logic_vector(19 downto 0) := x"0d5b0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0d5c0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0d5d0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0d5e0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0d5f0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0d600";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_2 : std_logic_vector(19 downto 0) := x"0d610";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0d620";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0d630";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0d640";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0d650";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0d660";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_3 : std_logic_vector(19 downto 0) := x"0d670";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0d680";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0d690";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0d6a0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0d6b0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0d6c0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_0 : std_logic_vector(19 downto 0) := x"0d620";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_0 : std_logic_vector(19 downto 0) := x"0d630";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0d640";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0d650";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0d660";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0d670";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0d680";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_1 : std_logic_vector(19 downto 0) := x"0d690";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_1 : std_logic_vector(19 downto 0) := x"0d6a0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0d6b0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0d6c0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0d6d0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0d6e0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0d6f0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_2 : std_logic_vector(19 downto 0) := x"0d700";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_2 : std_logic_vector(19 downto 0) := x"0d710";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0d720";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0d730";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0d740";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0d750";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0d760";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_3 : std_logic_vector(19 downto 0) := x"0d770";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_3 : std_logic_vector(19 downto 0) := x"0d780";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0d790";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0d7a0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0d7b0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0d7c0";
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0d7d0";
--** ITK_STRIPS_R3L1_LINKS
- constant REG_CR_ITK_R3L1_LINK_03_R3L1_0 : std_logic_vector(19 downto 0) := x"0d6d0";
- constant REG_CR_ITK_R3L1_LINK_03_R3L1_1 : std_logic_vector(19 downto 0) := x"0d6e0";
- constant REG_CR_ITK_R3L1_LINK_03_R3L1_2 : std_logic_vector(19 downto 0) := x"0d6f0";
- constant REG_CR_ITK_R3L1_LINK_03_R3L1_3 : std_logic_vector(19 downto 0) := x"0d700";
-
- --** ITK_STRIPS_LCB_LINKS
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0 : std_logic_vector(19 downto 0) := x"0d710";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0d720";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0d730";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0d740";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0d750";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0d760";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1 : std_logic_vector(19 downto 0) := x"0d770";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0d780";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0d790";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0d7a0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0d7b0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0d7c0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2 : std_logic_vector(19 downto 0) := x"0d7d0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0d7e0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0d7f0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0d800";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0d810";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0d820";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3 : std_logic_vector(19 downto 0) := x"0d830";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0d840";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0d850";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0d860";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0d870";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0d880";
-
- --** ITK_STRIPS_R3L1_LINKS
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_0 : std_logic_vector(19 downto 0) := x"0d890";
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_1 : std_logic_vector(19 downto 0) := x"0d8a0";
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_2 : std_logic_vector(19 downto 0) := x"0d8b0";
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_3 : std_logic_vector(19 downto 0) := x"0d8c0";
-
- --** ITK_STRIPS_LCB_LINKS
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0 : std_logic_vector(19 downto 0) := x"0d8d0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0d8e0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0d8f0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0d900";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0d910";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0d920";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1 : std_logic_vector(19 downto 0) := x"0d930";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0d940";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0d950";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0d960";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0d970";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0d980";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2 : std_logic_vector(19 downto 0) := x"0d990";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0d9a0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0d9b0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0d9c0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0d9d0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0d9e0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3 : std_logic_vector(19 downto 0) := x"0d9f0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0da00";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0da10";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0da20";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0da30";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0da40";
-
- --** ITK_STRIPS_R3L1_LINKS
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_0 : std_logic_vector(19 downto 0) := x"0da50";
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_1 : std_logic_vector(19 downto 0) := x"0da60";
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_2 : std_logic_vector(19 downto 0) := x"0da70";
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_3 : std_logic_vector(19 downto 0) := x"0da80";
-
- --** ITK_STRIPS_LCB_LINKS
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0 : std_logic_vector(19 downto 0) := x"0da90";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0daa0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0dab0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0dac0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0dad0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0dae0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1 : std_logic_vector(19 downto 0) := x"0daf0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0db00";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0db10";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0db20";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0db30";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0db40";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2 : std_logic_vector(19 downto 0) := x"0db50";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0db60";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0db70";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0db80";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0db90";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0dba0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3 : std_logic_vector(19 downto 0) := x"0dbb0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0dbc0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0dbd0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0dbe0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0dbf0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0dc00";
-
- --** ITK_STRIPS_R3L1_LINKS
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_0 : std_logic_vector(19 downto 0) := x"0dc10";
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_1 : std_logic_vector(19 downto 0) := x"0dc20";
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_2 : std_logic_vector(19 downto 0) := x"0dc30";
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_3 : std_logic_vector(19 downto 0) := x"0dc40";
-
- --** ITK_STRIPS_LCB_LINKS
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0 : std_logic_vector(19 downto 0) := x"0dc50";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0dc60";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0dc70";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0dc80";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0dc90";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0dca0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1 : std_logic_vector(19 downto 0) := x"0dcb0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0dcc0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0dcd0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0dce0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0dcf0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0dd00";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2 : std_logic_vector(19 downto 0) := x"0dd10";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0dd20";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0dd30";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0dd40";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0dd50";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0dd60";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3 : std_logic_vector(19 downto 0) := x"0dd70";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0dd80";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0dd90";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0dda0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0ddb0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0ddc0";
-
- --** ITK_STRIPS_R3L1_LINKS
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_0 : std_logic_vector(19 downto 0) := x"0ddd0";
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_1 : std_logic_vector(19 downto 0) := x"0dde0";
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_2 : std_logic_vector(19 downto 0) := x"0ddf0";
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_3 : std_logic_vector(19 downto 0) := x"0de00";
-
- --** ITK_STRIPS_LCB_LINKS
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0 : std_logic_vector(19 downto 0) := x"0de10";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0de20";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0de30";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0de40";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0de50";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0de60";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1 : std_logic_vector(19 downto 0) := x"0de70";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0de80";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0de90";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0dea0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0deb0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0dec0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2 : std_logic_vector(19 downto 0) := x"0ded0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0dee0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0def0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0df00";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0df10";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0df20";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3 : std_logic_vector(19 downto 0) := x"0df30";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0df40";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0df50";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0df60";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0df70";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0df80";
-
- --** ITK_STRIPS_R3L1_LINKS
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_0 : std_logic_vector(19 downto 0) := x"0df90";
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_1 : std_logic_vector(19 downto 0) := x"0dfa0";
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_2 : std_logic_vector(19 downto 0) := x"0dfb0";
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_3 : std_logic_vector(19 downto 0) := x"0dfc0";
-
- --** ITK_STRIPS_LCB_LINKS
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0 : std_logic_vector(19 downto 0) := x"0dfd0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0dfe0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0dff0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0e000";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0e010";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0e020";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1 : std_logic_vector(19 downto 0) := x"0e030";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0e040";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0e050";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0e060";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0e070";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0e080";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2 : std_logic_vector(19 downto 0) := x"0e090";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0e0a0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0e0b0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0e0c0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0e0d0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0e0e0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3 : std_logic_vector(19 downto 0) := x"0e0f0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0e100";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0e110";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0e120";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0e130";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0e140";
-
- --** ITK_STRIPS_R3L1_LINKS
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_0 : std_logic_vector(19 downto 0) := x"0e150";
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_1 : std_logic_vector(19 downto 0) := x"0e160";
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_2 : std_logic_vector(19 downto 0) := x"0e170";
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_3 : std_logic_vector(19 downto 0) := x"0e180";
-
- --** ITK_STRIPS_LCB_LINKS
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0 : std_logic_vector(19 downto 0) := x"0e190";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0e1a0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0e1b0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0e1c0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0e1d0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0e1e0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1 : std_logic_vector(19 downto 0) := x"0e1f0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0e200";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0e210";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0e220";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0e230";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0e240";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2 : std_logic_vector(19 downto 0) := x"0e250";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0e260";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0e270";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0e280";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0e290";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0e2a0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3 : std_logic_vector(19 downto 0) := x"0e2b0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0e2c0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0e2d0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0e2e0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0e2f0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0e300";
-
- --** ITK_STRIPS_R3L1_LINKS
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_0 : std_logic_vector(19 downto 0) := x"0e310";
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_1 : std_logic_vector(19 downto 0) := x"0e320";
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_2 : std_logic_vector(19 downto 0) := x"0e330";
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_3 : std_logic_vector(19 downto 0) := x"0e340";
-
- --** ITK_STRIPS_LCB_LINKS
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0 : std_logic_vector(19 downto 0) := x"0e350";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_0 : std_logic_vector(19 downto 0) := x"0e360";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_0 : std_logic_vector(19 downto 0) := x"0e370";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_0 : std_logic_vector(19 downto 0) := x"0e380";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_0 : std_logic_vector(19 downto 0) := x"0e390";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_0 : std_logic_vector(19 downto 0) := x"0e3a0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1 : std_logic_vector(19 downto 0) := x"0e3b0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_1 : std_logic_vector(19 downto 0) := x"0e3c0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_1 : std_logic_vector(19 downto 0) := x"0e3d0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_1 : std_logic_vector(19 downto 0) := x"0e3e0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_1 : std_logic_vector(19 downto 0) := x"0e3f0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_1 : std_logic_vector(19 downto 0) := x"0e400";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2 : std_logic_vector(19 downto 0) := x"0e410";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_2 : std_logic_vector(19 downto 0) := x"0e420";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_2 : std_logic_vector(19 downto 0) := x"0e430";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_2 : std_logic_vector(19 downto 0) := x"0e440";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_2 : std_logic_vector(19 downto 0) := x"0e450";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_2 : std_logic_vector(19 downto 0) := x"0e460";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3 : std_logic_vector(19 downto 0) := x"0e470";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_3 : std_logic_vector(19 downto 0) := x"0e480";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_3 : std_logic_vector(19 downto 0) := x"0e490";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_3 : std_logic_vector(19 downto 0) := x"0e4a0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_3 : std_logic_vector(19 downto 0) := x"0e4b0";
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_3 : std_logic_vector(19 downto 0) := x"0e4c0";
-
- --** ITK_STRIPS_R3L1_LINKS
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_0 : std_logic_vector(19 downto 0) := x"0e4d0";
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_1 : std_logic_vector(19 downto 0) := x"0e4e0";
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_2 : std_logic_vector(19 downto 0) := x"0e4f0";
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_3 : std_logic_vector(19 downto 0) := x"0e500";
+ constant REG_CR_ITK_R3L1_LINK_03_R3L1_0 : std_logic_vector(19 downto 0) := x"0d7e0";
+ constant REG_CR_ITK_R3L1_LINK_03_R3L1_1 : std_logic_vector(19 downto 0) := x"0d7f0";
+ constant REG_CR_ITK_R3L1_LINK_03_R3L1_2 : std_logic_vector(19 downto 0) := x"0d800";
+ constant REG_CR_ITK_R3L1_LINK_03_R3L1_3 : std_logic_vector(19 downto 0) := x"0d810";
+ constant REG_STRIPS_R3_TRIGGER : std_logic_vector(19 downto 0) := x"0d820";
+ constant REG_STRIPS_L1_TRIGGER : std_logic_vector(19 downto 0) := x"0d830";
+ constant REG_STRIPS_R3L1_TRIGGER : std_logic_vector(19 downto 0) := x"0d840";
--** MRODregisters
constant REG_MROD_CTRL : std_logic_vector(19 downto 0) := x"0f000";
@@ -1870,6 +1634,7 @@ package pcie_package is
end record;
type bitfield_ttc_dec_ctrl_w_type is record
+ L1A_DELAY : std_logic_vector(30 downto 27); -- Number of BC to delay the L1A distribution to the frontends
BCID_ONBCR : std_logic_vector(26 downto 15); -- BCID is set to this value when BCR arrives
ECR_BCR_SWAP : std_logic_vector(13 downto 13); -- ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
BUSY_OUTPUT_INHIBIT : std_logic_vector(12 downto 12); -- forces the Busy LEMO output to BUSY-OFF
@@ -2131,12 +1896,13 @@ package pcie_package is
READ_ENABLE : std_logic_vector(64 downto 64); -- Any write to this register triggers a read from the Wishbone to Wupper fifo
end record;
- type bitfield_global_strips_config_t_type is record
- TRICKLE_TRIG_PULSE : std_logic_vector(64 downto 64); -- writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
- TTC_GENERATE_GATING_ENABLE : std_logic_vector(0 downto 0); -- Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR. TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work. (See also BC_START, and BC_STOP fields)
+ type bitfield_global_strips_config_w_type is record
+ TEST_MODULE_MASK : std_logic_vector(15 downto 11); -- (for tests only) contains R3 mask for the simulated trigger data
+ TEST_R3L1_TAG : std_logic_vector(10 downto 4); -- (for tests only) contains R3 or L1 tag for the simulated trigger data
+ TTC_GENERATE_GATING_ENABLE : std_logic_vector(1 downto 1); -- Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR. TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work. (See also BC_START, and BC_STOP fields)
end record;
- type bitfield_lcb_ctrl_t_type is record
+ type bitfield_lcb_ctrl_w_type is record
L0A_BCR_DELAY : std_logic_vector(49 downto 38); -- TTC BCR signal will be delayed by this many BCs
L0A_FRAME_DELAY : std_logic_vector(37 downto 34); -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
@@ -2155,19 +1921,19 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
TTC_L0A_ENABLE : std_logic_vector(2 downto 2); -- enable generating L0A frames in response to TTC system signals
- TRICKLE_TRIG_PULSE : std_logic_vector(1 downto 1); -- writing to this register issues a single trickle trigger
TTC_GENERATE_GATING_ENABLE : std_logic_vector(0 downto 0); -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
end record;
--Array of registers
- type bitfield_lcb_ctrl_t_array_type is array (0 to 3) of bitfield_lcb_ctrl_t_type;
+ type bitfield_lcb_ctrl_w_array_type is array (0 to 3) of bitfield_lcb_ctrl_w_type;
--Two dimensional array of registers
- type bitfield_lcb_ctrl_t_2d_array_type is array (0 to 11) of bitfield_lcb_ctrl_t_array_type;
+ type bitfield_lcb_ctrl_w_2d_array_type is array (0 to 3) of bitfield_lcb_ctrl_w_array_type;
+ --Array of registers (std_logic_vector)
+ type bitfield_trickle_trigger_t_array_type is array (0 to 3) of std_logic_vector(64 downto 64); -- writing to this register issues a single trickle trigger
type bitfield_lcb_trickle_config_t_type is record
- MOVE_WRITE_PTR : std_logic_vector(64 downto 64); -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ MOVE_WRITE_PTR : std_logic_vector(64 downto 64); -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
WRITE_PTR : std_logic_vector(47 downto 32); -- Trickle configuration memory write pointer
VALID_DATA_START : std_logic_vector(31 downto 16); -- Start address of trickle configuration in trickle memory
@@ -2176,7 +1942,7 @@ package pcie_package is
--Array of registers
type bitfield_lcb_trickle_config_t_array_type is array (0 to 3) of bitfield_lcb_trickle_config_t_type;
--Two dimensional array of registers
- type bitfield_lcb_trickle_config_t_2d_array_type is array (0 to 11) of bitfield_lcb_trickle_config_t_array_type;
+ type bitfield_lcb_trickle_config_t_2d_array_type is array (0 to 3) of bitfield_lcb_trickle_config_t_array_type;
type bitfield_hcc_abc_mask_e_c_w_type is record
HCC_MASK : std_logic_vector(63 downto 48); -- HCC* module mask
@@ -2193,7 +1959,7 @@ package pcie_package is
--Array of registers
type bitfield_hcc_abc_mask_e_c_w_array_type is array (0 to 3) of bitfield_hcc_abc_mask_e_c_w_type;
--Two dimensional array of registers
- type bitfield_hcc_abc_mask_e_c_w_2d_array_type is array (0 to 11) of bitfield_hcc_abc_mask_e_c_w_array_type;
+ type bitfield_hcc_abc_mask_e_c_w_2d_array_type is array (0 to 3) of bitfield_hcc_abc_mask_e_c_w_array_type;
type bitfield_lcb_abc_mask_b_8_w_type is record
ABC_MASK_HCC_B : std_logic_vector(63 downto 48); -- Masks register commands with destination hcc_id = 0xB
-- mask(i) <=> (abc_id = i)
@@ -2211,7 +1977,7 @@ package pcie_package is
--Array of registers
type bitfield_lcb_abc_mask_b_8_w_array_type is array (0 to 3) of bitfield_lcb_abc_mask_b_8_w_type;
--Two dimensional array of registers
- type bitfield_lcb_abc_mask_b_8_w_2d_array_type is array (0 to 11) of bitfield_lcb_abc_mask_b_8_w_array_type;
+ type bitfield_lcb_abc_mask_b_8_w_2d_array_type is array (0 to 3) of bitfield_lcb_abc_mask_b_8_w_array_type;
type bitfield_lcb_abc_mask_7_4_w_type is record
ABC_MASK_HCC_7 : std_logic_vector(63 downto 48); -- Masks register commands with destination hcc_id = 0x7
-- mask(i) <=> (abc_id = i)
@@ -2229,7 +1995,7 @@ package pcie_package is
--Array of registers
type bitfield_lcb_abc_mask_7_4_w_array_type is array (0 to 3) of bitfield_lcb_abc_mask_7_4_w_type;
--Two dimensional array of registers
- type bitfield_lcb_abc_mask_7_4_w_2d_array_type is array (0 to 11) of bitfield_lcb_abc_mask_7_4_w_array_type;
+ type bitfield_lcb_abc_mask_7_4_w_2d_array_type is array (0 to 3) of bitfield_lcb_abc_mask_7_4_w_array_type;
type bitfield_lcb_abc_mask_3_0_w_type is record
ABC_MASK_HCC_3 : std_logic_vector(63 downto 48); -- Masks register commands with destination hcc_id = 0x3
-- mask(i) <=> (abc_id = i)
@@ -2247,7 +2013,7 @@ package pcie_package is
--Array of registers
type bitfield_lcb_abc_mask_3_0_w_array_type is array (0 to 3) of bitfield_lcb_abc_mask_3_0_w_type;
--Two dimensional array of registers
- type bitfield_lcb_abc_mask_3_0_w_2d_array_type is array (0 to 11) of bitfield_lcb_abc_mask_3_0_w_array_type;
+ type bitfield_lcb_abc_mask_3_0_w_2d_array_type is array (0 to 3) of bitfield_lcb_abc_mask_3_0_w_array_type;
type bitfield_r3l1_ctrl_w_type is record
FRAME_PHASE : std_logic_vector(3 downto 2); -- phase of R3L1 frame with respect to TTC BCR signal
L1_ENABLE : std_logic_vector(1 downto 1); -- enables sending TTC L1 signals to the front-end
@@ -2256,7 +2022,13 @@ package pcie_package is
--Array of registers
type bitfield_r3l1_ctrl_w_array_type is array (0 to 3) of bitfield_r3l1_ctrl_w_type;
--Two dimensional array of registers
- type bitfield_r3l1_ctrl_w_2d_array_type is array (0 to 11) of bitfield_r3l1_ctrl_w_array_type;
+ type bitfield_r3l1_ctrl_w_2d_array_type is array (0 to 3) of bitfield_r3l1_ctrl_w_array_type;
+ --Array of registers (std_logic_vector)
+ type bitfield_trickle_trigger_t_array_type is array (0 to 3) of std_logic_vector(64 downto 64); -- writing to this register issues a single trickle trigger
+ --Array of registers (std_logic_vector)
+ type bitfield_trickle_trigger_t_array_type is array (0 to 3) of std_logic_vector(64 downto 64); -- writing to this register issues a single trickle trigger
+ --Array of registers (std_logic_vector)
+ type bitfield_trickle_trigger_t_array_type is array (0 to 3) of std_logic_vector(64 downto 64); -- writing to this register issues a single trickle trigger
type bitfield_mrod_ctrl_w_type is record
OPTIONS : std_logic_vector(15 downto 4); -- Extra options for MROD
GOLTESTMODE : std_logic_vector(3 downto 0); -- GOL Test Mode (emulate CSM):
@@ -2389,8 +2161,10 @@ package pcie_package is
WISHBONE_CONTROL : bitfield_wishbone_control_w_type; -- Wishbone
WISHBONE_WRITE : bitfield_wishbone_write_t_type; -- Wishbone
WISHBONE_READ : bitfield_wishbone_read_t_type; -- Wishbone
- GLOBAL_STRIPS_CONFIG : bitfield_global_strips_config_t_type; -- Synchronous trigger for all LCB links on device
- LCB_CTRL : bitfield_lcb_ctrl_t_2d_array_type; -- Determines LCB link configuration
+ GLOBAL_STRIPS_CONFIG : bitfield_global_strips_config_w_type; -- Synchronous trigger for all LCB links on device
+ GLOBAL_TRICKLE_TRIGGER : std_logic_vector(64 downto 64); -- writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
+ LCB_CTRL : bitfield_lcb_ctrl_w_2d_array_type; -- Determines LCB link configuration
+ TRICKLE_TRIGGER : bitfield_trickle_trigger_t_2d_array_type;
LCB_TRICKLE_CONFIG : bitfield_lcb_trickle_config_t_2d_array_type; -- Trickle trigger configuration
HCC_ABC_MASK_E_C : bitfield_hcc_abc_mask_e_c_w_2d_array_type; -- Disables register commands addressed to masked HCC*/ABC* chips. Register commands for which
-- corresponding mask bit is set to '1' will be ignored by the command encoder.
@@ -2413,6 +2187,9 @@ package pcie_package is
-- modules without overwriting the entire trickle configuratrion memory.
R3L1_CTRL : bitfield_r3l1_ctrl_w_2d_array_type; -- Determines R3L1 link configuration
+ STRIPS_R3_TRIGGER : std_logic_vector(64 downto 64); -- (for tests only) simulate R3 trigger (issues 4-5 sequential triggers)
+ STRIPS_L1_TRIGGER : std_logic_vector(64 downto 64); -- (for tests only) simulate L1 trigger (issues 4-5 sequential triggers)
+ STRIPS_R3L1_TRIGGER : std_logic_vector(64 downto 64); -- (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)
MROD_CTRL : bitfield_mrod_ctrl_w_type; -- Specific registers for MROD
MROD_EP0_CSMENABLE : std_logic_vector(23 downto 0); -- EP0 CSM Data Enable channel 23-0
MROD_EP0_EMPTYSUPPR : std_logic_vector(23 downto 0); -- EP0 Set Empty Suppression channel 23-0
@@ -5281,6 +5058,7 @@ package pcie_package is
-- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
--
+ constant REG_TTC_DEC_CTRL_L1A_DELAY_C : std_logic_vector(30 downto 27) := x"0"; -- Number of BC to delay the L1A distribution to the frontends
constant REG_TTC_DEC_CTRL_BCID_ONBCR_C : std_logic_vector(26 downto 15) := x"000"; -- BCID is set to this value when BCR arrives
constant REG_TTC_DEC_CTRL_ECR_BCR_SWAP_C : std_logic_vector(13 downto 13) := "0"; -- ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
constant REG_TTC_DEC_CTRL_BUSY_OUTPUT_INHIBIT_C : std_logic_vector(12 downto 12) := "0"; -- forces the Busy LEMO output to BUSY-OFF
@@ -6043,8 +5821,10 @@ package pcie_package is
constant REG_WISHBONE_WRITE_WRITE_ENABLE_C : std_logic_vector(64 downto 64) := "0"; -- Any write to this register triggers a write to the Wupper to Wishbone fifo
constant REG_WISHBONE_WRITE_DATA_C : std_logic_vector(31 downto 0) := x"00000000"; -- Wishbone
constant REG_WISHBONE_READ_READ_ENABLE_C : std_logic_vector(64 downto 64) := "0"; -- Any write to this register triggers a read from the Wishbone to Wupper fifo
- constant REG_GLOBAL_STRIPS_CONFIG_TRICKLE_TRIG_PULSE_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
- constant REG_GLOBAL_STRIPS_CONFIG_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR. TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work. (See also BC_START, and BC_STOP fields)
+ constant REG_GLOBAL_STRIPS_CONFIG_TEST_MODULE_MASK_C: std_logic_vector(15 downto 11) := "00000"; -- (for tests only) contains R3 mask for the simulated trigger data
+ constant REG_GLOBAL_STRIPS_CONFIG_TEST_R3L1_TAG_C: std_logic_vector(10 downto 4) := "0000000"; -- (for tests only) contains R3 or L1 tag for the simulated trigger data
+ constant REG_GLOBAL_STRIPS_CONFIG_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR. TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work. (See also BC_START, and BC_STOP fields)
+ constant REG_GLOBAL_TRICKLE_TRIGGER_C : std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_0_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_0_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
-- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
@@ -6063,13 +5843,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_0_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_0_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_0_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_0_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -6139,13 +5918,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_1_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_1_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_1_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_1_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -6215,13 +5993,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_2_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_2_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_2_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_2_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -6291,13 +6068,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_3_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_3_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_LCB_3_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_3_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -6379,13 +6155,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_0_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_0_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_0_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_0_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -6455,13 +6230,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_1_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_1_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_1_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_1_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -6531,13 +6305,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_2_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_2_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_2_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_2_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -6607,13 +6380,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_3_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_3_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_LCB_3_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_TRIGGER_3_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_01_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -6695,13 +6467,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_0_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_0_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_0_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_0_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -6771,13 +6542,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_1_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_1_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_1_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_1_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -6847,13 +6617,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_2_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_2_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_2_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_2_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -6923,13 +6692,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_3_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_3_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_LCB_3_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_TRIGGER_3_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_02_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -7011,13 +6779,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_0_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_0_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_0_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_0_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -7087,13 +6854,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_1_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_1_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_1_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_1_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -7163,13 +6929,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_2_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_2_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_2_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_2_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -7239,13 +7004,12 @@ package pcie_package is
-- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_3_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_3_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_LCB_3_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
-- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
-- (See also BC_START, and BC_STOP fields)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_3_C: std_logic_vector(64 downto 64) := "0"; -- writing to this register issues a single trickle trigger
+ constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
constant REG_CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
@@ -7309,2534 +7073,9 @@ package pcie_package is
constant REG_CR_ITK_R3L1_LINK_03_R3L1_3_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
constant REG_CR_ITK_R3L1_LINK_03_R3L1_3_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
constant REG_CR_ITK_R3L1_LINK_03_R3L1_3_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_0_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_0_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_1_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_1_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_2_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_2_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_LCB_3_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_3_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_04_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_0_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_0_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_0_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_1_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_1_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_1_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_2_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_2_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_2_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_3_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_3_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_04_R3L1_3_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_0_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_0_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_1_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_1_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_2_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_2_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_LCB_3_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_3_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_05_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_0_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_0_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_0_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_1_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_1_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_1_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_2_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_2_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_2_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_3_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_3_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_05_R3L1_3_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_0_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_0_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_1_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_1_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_2_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_2_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_LCB_3_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_3_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_06_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_0_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_0_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_0_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_1_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_1_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_1_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_2_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_2_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_2_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_3_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_3_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_06_R3L1_3_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_0_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_0_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_1_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_1_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_2_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_2_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_LCB_3_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_3_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_07_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_0_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_0_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_0_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_1_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_1_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_1_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_2_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_2_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_2_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_3_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_3_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_07_R3L1_3_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_0_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_0_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_1_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_1_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_2_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_2_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_LCB_3_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_3_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_08_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_0_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_0_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_0_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_1_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_1_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_1_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_2_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_2_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_2_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_3_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_3_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_08_R3L1_3_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_0_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_0_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_1_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_1_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_2_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_2_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_LCB_3_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_3_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_09_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_0_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_0_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_0_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_1_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_1_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_1_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_2_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_2_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_2_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_3_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_3_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_09_R3L1_3_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_0_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_0_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_1_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_1_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_2_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_2_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_LCB_3_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_3_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_10_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_0_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_0_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_0_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_1_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_1_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_1_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_2_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_2_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_2_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_3_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_3_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_10_R3L1_3_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_0_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_0_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_0_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_0_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_0_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_0_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_0_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_0_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_0_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_0_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_0_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_1_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_1_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_1_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_1_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_1_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_1_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_1_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_1_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_1_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_1_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_1_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_2_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_2_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_2_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_2_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_2_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_2_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_2_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_2_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_2_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_2_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_2_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_L0A_BCR_DELAY_C: std_logic_vector(49 downto 38) := x"000"; -- TTC BCR signal will be delayed by this many BCs
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_L0A_FRAME_DELAY_C: std_logic_vector(37 downto 34) := x"0"; -- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- -- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_FRAME_PHASE_C: std_logic_vector(33 downto 32) := "00"; -- phase of LCB frame with respect to TTC BCR signal
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_TRICKLE_BC_START_C: std_logic_vector(31 downto 20) := x"000"; -- Determines the start of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_TRICKLE_BC_STOP_C: std_logic_vector(19 downto 8) := x"000"; -- Determines the end of the allowed BC interval for low-priority LCB frames
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_LCB_DESTINATION_MUX_C: std_logic_vector(5 downto 4) := "00"; -- Determines where the elink data is sent to:
- -- 00: command decoder (use same command encoding format as trickle configuration)
- -- 01: trickle memory (see phase2 documentation for command encoding format)
- -- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- -- 11: (invalid, don't use)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_TRICKLE_TRIG_RUN_C: std_logic_vector(3 downto 3) := "0"; -- if enabled, trickle configuration is sent out continuously to the front-end
- -- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- -- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_TTC_L0A_ENABLE_C: std_logic_vector(2 downto 2) := "0"; -- enable generating L0A frames in response to TTC system signals
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_TRICKLE_TRIG_PULSE_C: std_logic_vector(1 downto 1) := "0"; -- writing to this register issues a single trickle trigger
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_LCB_3_TTC_GENERATE_GATING_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables generating trickle gating signal in response to TTC BCR.
- -- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- -- (See also BC_START, and BC_STOP fields)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_3_MOVE_WRITE_PTR_C: std_logic_vector(64 downto 64) := "0"; -- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- -- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_3_WRITE_PTR_C: std_logic_vector(47 downto 32) := x"0000"; -- Trickle configuration memory write pointer
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_START_C: std_logic_vector(31 downto 16) := x"0000"; -- Start address of trickle configuration in trickle memory
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_3_VALID_DATA_END_C: std_logic_vector(15 downto 0) := x"0000"; -- Stop address of trickle configuration in trickle memory (last valid byte)
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_3_HCC_MASK_C: std_logic_vector(63 downto 48) := x"0000"; -- HCC* module mask
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_3_ABC_MASK_HCC_E_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xE
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_3_ABC_MASK_HCC_D_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0xD
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_3_ABC_MASK_HCC_C_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0xC
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_B_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0xB
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_A_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0xA
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_9_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x9
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_3_ABC_MASK_HCC_8_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x8
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_7_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x7
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_6_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x6
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_5_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x5
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_3_ABC_MASK_HCC_4_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x4
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_3_C: std_logic_vector(63 downto 48) := x"0000"; -- Masks register commands with destination hcc_id = 0x3
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_2_C: std_logic_vector(47 downto 32) := x"0000"; -- Masks register commands with destination hcc_id = 0x2
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_1_C: std_logic_vector(31 downto 16) := x"0000"; -- Masks register commands with destination hcc_id = 0x1
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_3_ABC_MASK_HCC_0_C: std_logic_vector(15 downto 0) := x"0000"; -- Masks register commands with destination hcc_id = 0x0
- -- mask(i) <=> (abc_id = i)
-
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_0_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_0_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_0_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_1_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_1_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_1_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_2_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_2_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_2_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_3_FRAME_PHASE_C: std_logic_vector(3 downto 2) := "00"; -- phase of R3L1 frame with respect to TTC BCR signal
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_3_L1_ENABLE_C: std_logic_vector(1 downto 1) := "0"; -- enables sending TTC L1 signals to the front-end
- constant REG_CR_ITK_R3L1_LINK_11_R3L1_3_R3_ENABLE_C: std_logic_vector(0 downto 0) := "0"; -- enables sending RoI R3 signals to the front-end
+ constant REG_STRIPS_R3_TRIGGER_C : std_logic_vector(64 downto 64) := "0"; -- (for tests only) simulate R3 trigger (issues 4-5 sequential triggers)
+ constant REG_STRIPS_L1_TRIGGER_C : std_logic_vector(64 downto 64) := "0"; -- (for tests only) simulate L1 trigger (issues 4-5 sequential triggers)
+ constant REG_STRIPS_R3L1_TRIGGER_C : std_logic_vector(64 downto 64) := "0"; -- (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)
constant REG_MROD_CTRL_OPTIONS_C : std_logic_vector(15 downto 4) := x"000"; -- Extra options for MROD
constant REG_MROD_CTRL_GOLTESTMODE_C : std_logic_vector(3 downto 0) := x"0"; -- GOL Test Mode (emulate CSM):
-- 0: Run Data Emulator when 1; 0: stop, load emulator fifo
diff --git a/sources/templates/registermap.tex b/sources/templates/registermap.tex
index 3c7b597a679d322320c5272bb633aea9b43f5759..509711904c69515770bf067006bacbc677ff87e6 100644
--- a/sources/templates/registermap.tex
+++ b/sources/templates/registermap.tex
@@ -352,7 +352,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
\cline{3-7}
& & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
& & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
- & & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: ITk Strips 8b10b\newline 4: ITk Pixel Aurora / RD53B\newline 5: Endeavour\newline 6-15: reserved\newline \\
+ & & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
& & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
& & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\
\hline
@@ -362,7 +362,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
\cline{3-7}
& & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
& & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
- & & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: ITk Strips 8b10b\newline 4: ITk Pixel Aurora / RD53B\newline 5: Endeavour\newline 6-15: reserved\newline \\
+ & & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
& & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
& & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\
\hline
@@ -374,7 +374,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
\cline{3-7}
& & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
& & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
- & & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: ITk Strips 8b10b\newline 4: ITk Pixel Aurora / RD53B\newline 5: Endeavour\newline 6-15: reserved\newline \\
+ & & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
& & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
& & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\
\hline
@@ -384,7 +384,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
\cline{3-7}
& & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
& & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
- & & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: ITk Strips 8b10b\newline 4: ITk Pixel Aurora / RD53B\newline 5: Endeavour\newline 6-15: reserved\newline \\
+ & & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
& & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
& & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\
\hline
@@ -453,6 +453,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
\hline
0x3010 & 0,1 & \multicolumn{5}{l|}{ENCODING\_LINK00\_EGROUP0\_CTRL} \\
\cline{3-7}
+ & & & TTC\_OPTION & 62:59 & W & Selects TTC bits sent to the E-link \\
& & & EPATH\_ALMOST\_FULL & 58:51 & R & Indiator that the EPATH FIFO is almost full \\
& & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
& & & EPATH\_WIDTH & 42:40 & W & Width of the Elinks in the egroup\newline 0: 2 bit 80 Mb/s\newline 1: 4 bit 160 Mb/s\newline 2: 8 bit 320 Mb/s\newline \\
@@ -463,6 +464,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
\hline
0x3050 & 0,1 & \multicolumn{5}{l|}{ENCODING\_LINK00\_EGROUP4\_CTRL} \\
\cline{3-7}
+ & & & TTC\_OPTION & 62:59 & W & Selects TTC bits sent to the E-link \\
& & & EPATH\_ALMOST\_FULL & 58:51 & R & Indiator that the EPATH FIFO is almost full \\
& & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
& & & EPATH\_WIDTH & 42:40 & W & Width of the Elinks in the egroup\newline 0: 2 bit 80 Mb/s\newline 1: 4 bit 160 Mb/s\newline 2: 8 bit 320 Mb/s\newline \\
@@ -475,6 +477,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
\hline
0x3380 & 0,1 & \multicolumn{5}{l|}{ENCODING\_LINK11\_EGROUP0\_CTRL} \\
\cline{3-7}
+ & & & TTC\_OPTION & 62:59 & W & Selects TTC bits sent to the E-link \\
& & & EPATH\_ALMOST\_FULL & 58:51 & R & Indiator that the EPATH FIFO is almost full \\
& & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
& & & EPATH\_WIDTH & 42:40 & W & Width of the Elinks in the egroup\newline 0: 2 bit 80 Mb/s\newline 1: 4 bit 160 Mb/s\newline 2: 8 bit 320 Mb/s\newline \\
@@ -485,6 +488,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
\hline
0x33C0 & 0,1 & \multicolumn{5}{l|}{ENCODING\_LINK11\_EGROUP4\_CTRL} \\
\cline{3-7}
+ & & & TTC\_OPTION & 62:59 & W & Selects TTC bits sent to the E-link \\
& & & EPATH\_ALMOST\_FULL & 58:51 & R & Indiator that the EPATH FIFO is almost full \\
& & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
& & & EPATH\_WIDTH & 42:40 & W & Width of the Elinks in the egroup\newline 0: 2 bit 80 Mb/s\newline 1: 4 bit 160 Mb/s\newline 2: 8 bit 320 Mb/s\newline \\
@@ -730,6 +734,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
\hline
0x7000 & 0 & \multicolumn{5}{l|}{TTC\_DEC\_CTRL} \\
\cline{3-7}
+ & & & L1A\_DELAY & 30:27 & W & Number of BC to delay the L1A distribution to the frontends \\
& & & BCID\_ONBCR & 26:15 & W & BCID is set to this value when BCR arrives \\
& & & BUSY\_OUTPUT\_STATUS & 14 & R & Actual status of the BUSY LEMO output signal \\
& & & ECR\_BCR\_SWAP & 13 & W & ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC) \\
@@ -1308,14 +1313,18 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
\hline
0xD000 & 0,1 & \multicolumn{5}{l|}{GLOBAL\_STRIPS\_CONFIG} \\
\cline{3-7}
- & & & TRICKLE\_TRIG\_PULSE & any & T & writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device \\
- & & & TTC\_GENERATE\_GATING\_ENABLE & 0 & W & Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR. TRICKLE\_TRIG\_RUN must also be enabled for the trickle configuration to work. (See also BC\_START, and BC\_STOP fields) \\
+ & & & TEST\_MODULE\_MASK & 15:11 & W & (for tests only) contains R3 mask for the simulated trigger data \\
+ & & & TEST\_R3L1\_TAG & 10:4 & W & (for tests only) contains R3 or L1 tag for the simulated trigger data \\
+ & & & TTC\_GENERATE\_GATING\_ENABLE & 1 & W & Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR. TRICKLE\_TRIG\_RUN must also be enabled for the trickle configuration to work. (See also BC\_START, and BC\_STOP fields) \\
+\hline
+0xD010 & 0,1 & \multicolumn{2}{l|}{GLOBAL\_TRICKLE\_TRIGGER} &
+any & T & writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device \\
\hline
\multicolumn{7}{|c|}{ITK\_STRIPS\_GBT} \\
\hline
\multicolumn{7}{|c|}{ITK\_STRIPS\_LCB\_LINKS} \\
\hline
-0xD010 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_LCB\_0} \\
+0xD020 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_LCB\_0} \\
\cline{3-7}
& & & L0A\_BCR\_DELAY & 49:38 & W & TTC BCR signal will be delayed by this many BCs \\
& & & L0A\_FRAME\_DELAY & 37:34 & W & By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,\newline and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.\newline \\
@@ -1325,39 +1334,40 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
& & & LCB\_DESTINATION\_MUX & 5:4 & W & Determines where the elink data is sent to:\newline 00: command decoder (use same command encoding format as trickle configuration)\newline 01: trickle memory (see phase2 documentation for command encoding format)\newline 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)\newline 11: (invalid, don't use)\newline \\
& & & TRICKLE\_TRIG\_RUN & 3 & W & if enabled, trickle configuration is sent out continuously to the front-end\newline (use together with TTC\_GENERATE\_GATING\_EN for sending trickle configuration\newline continuously during a specified BC range. See also BC\_START, and BC\_STOP fields.)\newline \\
& & & TTC\_L0A\_ENABLE & 2 & W & enable generating L0A frames in response to TTC system signals \\
- & & & TRICKLE\_TRIG\_PULSE & 1 & T & writing to this register issues a single trickle trigger \\
& & & TTC\_GENERATE\_GATING\_ENABLE & 0 & W & enables generating trickle gating signal in response to TTC BCR.\newline TRICKLE\_TRIG\_RUN must also be enabled for the trickle configuration to work.\newline (See also BC\_START, and BC\_STOP fields) \newline \\
\hline
-0xD020 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_TRICKLE\_MEMORY\_CONFIG\_0} \\
+0xD030 & 0,1 & \multicolumn{2}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_TRICKLE\_TRIGGER\_0} &
+any & T & writing to this register issues a single trickle trigger \\
+\hline
+0xD040 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_TRICKLE\_MEMORY\_CONFIG\_0} \\
\cline{3-7}
- & & & MOVE\_WRITE\_PTR & any & T & Writing to this register moves trickle configuration memory write pointer to WRITE\_PTR address.\newline The memory must not be actively read out when this signal is sent, otherwise it will be ignored.\newline \\
- & & & ACTUAL\_ADDRESS\_WIDTH & 57:48 & R & Actual valid address width of trickle configuration memory \\
+ & & & MOVE\_WRITE\_PTR & any & T & Writing to this register moves trickle configuration memory write pointer to WRITE\_PTR address\newline \\
& & & WRITE\_PTR & 47:32 & W & Trickle configuration memory write pointer \\
& & & VALID\_DATA\_START & 31:16 & W & Start address of trickle configuration in trickle memory \\
& & & VALID\_DATA\_END & 15:0 & W & Stop address of trickle configuration in trickle memory (last valid byte) \\
\hline
-0xD030 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_MODULE\_MASK\_F\_C\_0} \\
+0xD050 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_MODULE\_MASK\_F\_C\_0} \\
\cline{3-7}
& & & HCC\_MASK & 63:48 & W & HCC* module mask \newline \\
& & & ABC\_MASK\_HCC\_E & 47:32 & W & Masks register commands with destination hcc\_id = 0xE\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_D & 31:16 & W & Masks register commands with destination hcc\_id = 0xD\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_C & 15:0 & W & Masks register commands with destination hcc\_id = 0xC\newline mask(i) <=> (abc\_id = i)\newline \\
\hline
-0xD040 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_ABC\_MODULE\_MASK\_B\_8\_0} \\
+0xD060 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_ABC\_MODULE\_MASK\_B\_8\_0} \\
\cline{3-7}
& & & ABC\_MASK\_HCC\_B & 63:48 & W & Masks register commands with destination hcc\_id = 0xB \newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_A & 47:32 & W & Masks register commands with destination hcc\_id = 0xA\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_9 & 31:16 & W & Masks register commands with destination hcc\_id = 0x9\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_8 & 15:0 & W & Masks register commands with destination hcc\_id = 0x8\newline mask(i) <=> (abc\_id = i)\newline \\
\hline
-0xD050 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_ABC\_MODULE\_MASK\_7\_4\_0} \\
+0xD070 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_ABC\_MODULE\_MASK\_7\_4\_0} \\
\cline{3-7}
& & & ABC\_MASK\_HCC\_7 & 63:48 & W & Masks register commands with destination hcc\_id = 0x7 \newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_6 & 47:32 & W & Masks register commands with destination hcc\_id = 0x6\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_5 & 31:16 & W & Masks register commands with destination hcc\_id = 0x5\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_4 & 15:0 & W & Masks register commands with destination hcc\_id = 0x4\newline mask(i) <=> (abc\_id = i)\newline \\
\hline
-0xD060 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_ABC\_MODULE\_MASK\_3\_0\_0} \\
+0xD080 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_ABC\_MODULE\_MASK\_3\_0\_0} \\
\cline{3-7}
& & & ABC\_MASK\_HCC\_3 & 63:48 & W & Masks register commands with destination hcc\_id = 0x3 \newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_2 & 47:32 & W & Masks register commands with destination hcc\_id = 0x2\newline mask(i) <=> (abc\_id = i) \newline \\
@@ -1366,7 +1376,7 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
\hline
\multicolumn{7}{|c|}{\ldots} \\
\hline
-0xD130 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_LCB\_3} \\
+0xD170 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_LCB\_3} \\
\cline{3-7}
& & & L0A\_BCR\_DELAY & 49:38 & W & TTC BCR signal will be delayed by this many BCs \\
& & & L0A\_FRAME\_DELAY & 37:34 & W & By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,\newline and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.\newline \\
@@ -1376,39 +1386,40 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
& & & LCB\_DESTINATION\_MUX & 5:4 & W & Determines where the elink data is sent to:\newline 00: command decoder (use same command encoding format as trickle configuration)\newline 01: trickle memory (see phase2 documentation for command encoding format)\newline 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)\newline 11: (invalid, don't use)\newline \\
& & & TRICKLE\_TRIG\_RUN & 3 & W & if enabled, trickle configuration is sent out continuously to the front-end\newline (use together with TTC\_GENERATE\_GATING\_EN for sending trickle configuration\newline continuously during a specified BC range. See also BC\_START, and BC\_STOP fields.)\newline \\
& & & TTC\_L0A\_ENABLE & 2 & W & enable generating L0A frames in response to TTC system signals \\
- & & & TRICKLE\_TRIG\_PULSE & 1 & T & writing to this register issues a single trickle trigger \\
& & & TTC\_GENERATE\_GATING\_ENABLE & 0 & W & enables generating trickle gating signal in response to TTC BCR.\newline TRICKLE\_TRIG\_RUN must also be enabled for the trickle configuration to work.\newline (See also BC\_START, and BC\_STOP fields) \newline \\
\hline
-0xD140 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_TRICKLE\_MEMORY\_CONFIG\_3} \\
+0xD180 & 0,1 & \multicolumn{2}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_TRICKLE\_TRIGGER\_3} &
+any & T & writing to this register issues a single trickle trigger \\
+\hline
+0xD190 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_TRICKLE\_MEMORY\_CONFIG\_3} \\
\cline{3-7}
- & & & MOVE\_WRITE\_PTR & any & T & Writing to this register moves trickle configuration memory write pointer to WRITE\_PTR address.\newline The memory must not be actively read out when this signal is sent, otherwise it will be ignored.\newline \\
- & & & ACTUAL\_ADDRESS\_WIDTH & 57:48 & R & Actual valid address width of trickle configuration memory \\
+ & & & MOVE\_WRITE\_PTR & any & T & Writing to this register moves trickle configuration memory write pointer to WRITE\_PTR address\newline \\
& & & WRITE\_PTR & 47:32 & W & Trickle configuration memory write pointer \\
& & & VALID\_DATA\_START & 31:16 & W & Start address of trickle configuration in trickle memory \\
& & & VALID\_DATA\_END & 15:0 & W & Stop address of trickle configuration in trickle memory (last valid byte) \\
\hline
-0xD150 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_MODULE\_MASK\_F\_C\_3} \\
+0xD1A0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_MODULE\_MASK\_F\_C\_3} \\
\cline{3-7}
& & & HCC\_MASK & 63:48 & W & HCC* module mask \newline \\
& & & ABC\_MASK\_HCC\_E & 47:32 & W & Masks register commands with destination hcc\_id = 0xE\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_D & 31:16 & W & Masks register commands with destination hcc\_id = 0xD\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_C & 15:0 & W & Masks register commands with destination hcc\_id = 0xC\newline mask(i) <=> (abc\_id = i)\newline \\
\hline
-0xD160 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_ABC\_MODULE\_MASK\_B\_8\_3} \\
+0xD1B0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_ABC\_MODULE\_MASK\_B\_8\_3} \\
\cline{3-7}
& & & ABC\_MASK\_HCC\_B & 63:48 & W & Masks register commands with destination hcc\_id = 0xB \newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_A & 47:32 & W & Masks register commands with destination hcc\_id = 0xA\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_9 & 31:16 & W & Masks register commands with destination hcc\_id = 0x9\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_8 & 15:0 & W & Masks register commands with destination hcc\_id = 0x8\newline mask(i) <=> (abc\_id = i)\newline \\
\hline
-0xD170 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_ABC\_MODULE\_MASK\_7\_4\_3} \\
+0xD1C0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_ABC\_MODULE\_MASK\_7\_4\_3} \\
\cline{3-7}
& & & ABC\_MASK\_HCC\_7 & 63:48 & W & Masks register commands with destination hcc\_id = 0x7 \newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_6 & 47:32 & W & Masks register commands with destination hcc\_id = 0x6\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_5 & 31:16 & W & Masks register commands with destination hcc\_id = 0x5\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_4 & 15:0 & W & Masks register commands with destination hcc\_id = 0x4\newline mask(i) <=> (abc\_id = i)\newline \\
\hline
-0xD180 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_ABC\_MODULE\_MASK\_3\_0\_3} \\
+0xD1D0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_00\_ABC\_MODULE\_MASK\_3\_0\_3} \\
\cline{3-7}
& & & ABC\_MASK\_HCC\_3 & 63:48 & W & Masks register commands with destination hcc\_id = 0x3 \newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_2 & 47:32 & W & Masks register commands with destination hcc\_id = 0x2\newline mask(i) <=> (abc\_id = i) \newline \\
@@ -1417,7 +1428,7 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
\hline
\multicolumn{7}{|c|}{ITK\_STRIPS\_R3 L1\_LINKS} \\
\hline
-0xD190 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_R3L1\_LINK\_00\_R3L1\_0} \\
+0xD1E0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_R3L1\_LINK\_00\_R3L1\_0} \\
\cline{3-7}
& & & FRAME\_PHASE & 3:2 & W & phase of R3L1 frame with respect to TTC BCR signal \\
& & & L1\_ENABLE & 1 & W & enables sending TTC L1 signals to the front-end \\
@@ -1425,7 +1436,7 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
\hline
\multicolumn{7}{|c|}{\ldots} \\
\hline
-0xD1C0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_R3L1\_LINK\_00\_R3L1\_3} \\
+0xD210 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_R3L1\_LINK\_00\_R3L1\_3} \\
\cline{3-7}
& & & FRAME\_PHASE & 3:2 & W & phase of R3L1 frame with respect to TTC BCR signal \\
& & & L1\_ENABLE & 1 & W & enables sending TTC L1 signals to the front-end \\
@@ -1435,7 +1446,7 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
\hline
\multicolumn{7}{|c|}{ITK\_STRIPS\_LCB\_LINKS} \\
\hline
-0xE350 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_11\_LCB\_0} \\
+0xD620 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_03\_LCB\_0} \\
\cline{3-7}
& & & L0A\_BCR\_DELAY & 49:38 & W & TTC BCR signal will be delayed by this many BCs \\
& & & L0A\_FRAME\_DELAY & 37:34 & W & By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,\newline and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.\newline \\
@@ -1445,39 +1456,40 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
& & & LCB\_DESTINATION\_MUX & 5:4 & W & Determines where the elink data is sent to:\newline 00: command decoder (use same command encoding format as trickle configuration)\newline 01: trickle memory (see phase2 documentation for command encoding format)\newline 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)\newline 11: (invalid, don't use)\newline \\
& & & TRICKLE\_TRIG\_RUN & 3 & W & if enabled, trickle configuration is sent out continuously to the front-end\newline (use together with TTC\_GENERATE\_GATING\_EN for sending trickle configuration\newline continuously during a specified BC range. See also BC\_START, and BC\_STOP fields.)\newline \\
& & & TTC\_L0A\_ENABLE & 2 & W & enable generating L0A frames in response to TTC system signals \\
- & & & TRICKLE\_TRIG\_PULSE & 1 & T & writing to this register issues a single trickle trigger \\
& & & TTC\_GENERATE\_GATING\_ENABLE & 0 & W & enables generating trickle gating signal in response to TTC BCR.\newline TRICKLE\_TRIG\_RUN must also be enabled for the trickle configuration to work.\newline (See also BC\_START, and BC\_STOP fields) \newline \\
\hline
-0xE360 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_11\_TRICKLE\_MEMORY\_CONFIG\_0} \\
+0xD630 & 0,1 & \multicolumn{2}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_03\_TRICKLE\_TRIGGER\_0} &
+any & T & writing to this register issues a single trickle trigger \\
+\hline
+0xD640 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_03\_TRICKLE\_MEMORY\_CONFIG\_0} \\
\cline{3-7}
- & & & MOVE\_WRITE\_PTR & any & T & Writing to this register moves trickle configuration memory write pointer to WRITE\_PTR address.\newline The memory must not be actively read out when this signal is sent, otherwise it will be ignored.\newline \\
- & & & ACTUAL\_ADDRESS\_WIDTH & 57:48 & R & Actual valid address width of trickle configuration memory \\
+ & & & MOVE\_WRITE\_PTR & any & T & Writing to this register moves trickle configuration memory write pointer to WRITE\_PTR address\newline \\
& & & WRITE\_PTR & 47:32 & W & Trickle configuration memory write pointer \\
& & & VALID\_DATA\_START & 31:16 & W & Start address of trickle configuration in trickle memory \\
& & & VALID\_DATA\_END & 15:0 & W & Stop address of trickle configuration in trickle memory (last valid byte) \\
\hline
-0xE370 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_11\_MODULE\_MASK\_F\_C\_0} \\
+0xD650 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_03\_MODULE\_MASK\_F\_C\_0} \\
\cline{3-7}
& & & HCC\_MASK & 63:48 & W & HCC* module mask \newline \\
& & & ABC\_MASK\_HCC\_E & 47:32 & W & Masks register commands with destination hcc\_id = 0xE\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_D & 31:16 & W & Masks register commands with destination hcc\_id = 0xD\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_C & 15:0 & W & Masks register commands with destination hcc\_id = 0xC\newline mask(i) <=> (abc\_id = i)\newline \\
\hline
-0xE380 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_11\_ABC\_MODULE\_MASK\_B\_8\_0} \\
+0xD660 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_03\_ABC\_MODULE\_MASK\_B\_8\_0} \\
\cline{3-7}
& & & ABC\_MASK\_HCC\_B & 63:48 & W & Masks register commands with destination hcc\_id = 0xB \newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_A & 47:32 & W & Masks register commands with destination hcc\_id = 0xA\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_9 & 31:16 & W & Masks register commands with destination hcc\_id = 0x9\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_8 & 15:0 & W & Masks register commands with destination hcc\_id = 0x8\newline mask(i) <=> (abc\_id = i)\newline \\
\hline
-0xE390 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_11\_ABC\_MODULE\_MASK\_7\_4\_0} \\
+0xD670 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_03\_ABC\_MODULE\_MASK\_7\_4\_0} \\
\cline{3-7}
& & & ABC\_MASK\_HCC\_7 & 63:48 & W & Masks register commands with destination hcc\_id = 0x7 \newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_6 & 47:32 & W & Masks register commands with destination hcc\_id = 0x6\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_5 & 31:16 & W & Masks register commands with destination hcc\_id = 0x5\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_4 & 15:0 & W & Masks register commands with destination hcc\_id = 0x4\newline mask(i) <=> (abc\_id = i)\newline \\
\hline
-0xE3A0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_11\_ABC\_MODULE\_MASK\_3\_0\_0} \\
+0xD680 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_03\_ABC\_MODULE\_MASK\_3\_0\_0} \\
\cline{3-7}
& & & ABC\_MASK\_HCC\_3 & 63:48 & W & Masks register commands with destination hcc\_id = 0x3 \newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_2 & 47:32 & W & Masks register commands with destination hcc\_id = 0x2\newline mask(i) <=> (abc\_id = i) \newline \\
@@ -1486,7 +1498,7 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
\hline
\multicolumn{7}{|c|}{\ldots} \\
\hline
-0xE470 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_11\_LCB\_3} \\
+0xD770 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_03\_LCB\_3} \\
\cline{3-7}
& & & L0A\_BCR\_DELAY & 49:38 & W & TTC BCR signal will be delayed by this many BCs \\
& & & L0A\_FRAME\_DELAY & 37:34 & W & By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,\newline and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.\newline \\
@@ -1496,39 +1508,40 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
& & & LCB\_DESTINATION\_MUX & 5:4 & W & Determines where the elink data is sent to:\newline 00: command decoder (use same command encoding format as trickle configuration)\newline 01: trickle memory (see phase2 documentation for command encoding format)\newline 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)\newline 11: (invalid, don't use)\newline \\
& & & TRICKLE\_TRIG\_RUN & 3 & W & if enabled, trickle configuration is sent out continuously to the front-end\newline (use together with TTC\_GENERATE\_GATING\_EN for sending trickle configuration\newline continuously during a specified BC range. See also BC\_START, and BC\_STOP fields.)\newline \\
& & & TTC\_L0A\_ENABLE & 2 & W & enable generating L0A frames in response to TTC system signals \\
- & & & TRICKLE\_TRIG\_PULSE & 1 & T & writing to this register issues a single trickle trigger \\
& & & TTC\_GENERATE\_GATING\_ENABLE & 0 & W & enables generating trickle gating signal in response to TTC BCR.\newline TRICKLE\_TRIG\_RUN must also be enabled for the trickle configuration to work.\newline (See also BC\_START, and BC\_STOP fields) \newline \\
\hline
-0xE480 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_11\_TRICKLE\_MEMORY\_CONFIG\_3} \\
+0xD780 & 0,1 & \multicolumn{2}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_03\_TRICKLE\_TRIGGER\_3} &
+any & T & writing to this register issues a single trickle trigger \\
+\hline
+0xD790 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_03\_TRICKLE\_MEMORY\_CONFIG\_3} \\
\cline{3-7}
- & & & MOVE\_WRITE\_PTR & any & T & Writing to this register moves trickle configuration memory write pointer to WRITE\_PTR address.\newline The memory must not be actively read out when this signal is sent, otherwise it will be ignored.\newline \\
- & & & ACTUAL\_ADDRESS\_WIDTH & 57:48 & R & Actual valid address width of trickle configuration memory \\
+ & & & MOVE\_WRITE\_PTR & any & T & Writing to this register moves trickle configuration memory write pointer to WRITE\_PTR address\newline \\
& & & WRITE\_PTR & 47:32 & W & Trickle configuration memory write pointer \\
& & & VALID\_DATA\_START & 31:16 & W & Start address of trickle configuration in trickle memory \\
& & & VALID\_DATA\_END & 15:0 & W & Stop address of trickle configuration in trickle memory (last valid byte) \\
\hline
-0xE490 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_11\_MODULE\_MASK\_F\_C\_3} \\
+0xD7A0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_03\_MODULE\_MASK\_F\_C\_3} \\
\cline{3-7}
& & & HCC\_MASK & 63:48 & W & HCC* module mask \newline \\
& & & ABC\_MASK\_HCC\_E & 47:32 & W & Masks register commands with destination hcc\_id = 0xE\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_D & 31:16 & W & Masks register commands with destination hcc\_id = 0xD\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_C & 15:0 & W & Masks register commands with destination hcc\_id = 0xC\newline mask(i) <=> (abc\_id = i)\newline \\
\hline
-0xE4A0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_11\_ABC\_MODULE\_MASK\_B\_8\_3} \\
+0xD7B0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_03\_ABC\_MODULE\_MASK\_B\_8\_3} \\
\cline{3-7}
& & & ABC\_MASK\_HCC\_B & 63:48 & W & Masks register commands with destination hcc\_id = 0xB \newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_A & 47:32 & W & Masks register commands with destination hcc\_id = 0xA\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_9 & 31:16 & W & Masks register commands with destination hcc\_id = 0x9\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_8 & 15:0 & W & Masks register commands with destination hcc\_id = 0x8\newline mask(i) <=> (abc\_id = i)\newline \\
\hline
-0xE4B0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_11\_ABC\_MODULE\_MASK\_7\_4\_3} \\
+0xD7C0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_03\_ABC\_MODULE\_MASK\_7\_4\_3} \\
\cline{3-7}
& & & ABC\_MASK\_HCC\_7 & 63:48 & W & Masks register commands with destination hcc\_id = 0x7 \newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_6 & 47:32 & W & Masks register commands with destination hcc\_id = 0x6\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_5 & 31:16 & W & Masks register commands with destination hcc\_id = 0x5\newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_4 & 15:0 & W & Masks register commands with destination hcc\_id = 0x4\newline mask(i) <=> (abc\_id = i)\newline \\
\hline
-0xE4C0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_11\_ABC\_MODULE\_MASK\_3\_0\_3} \\
+0xD7D0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_STRIPS\_LCB\_LINKS\_03\_ABC\_MODULE\_MASK\_3\_0\_3} \\
\cline{3-7}
& & & ABC\_MASK\_HCC\_3 & 63:48 & W & Masks register commands with destination hcc\_id = 0x3 \newline mask(i) <=> (abc\_id = i) \newline \\
& & & ABC\_MASK\_HCC\_2 & 47:32 & W & Masks register commands with destination hcc\_id = 0x2\newline mask(i) <=> (abc\_id = i) \newline \\
@@ -1537,7 +1550,7 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
\hline
\multicolumn{7}{|c|}{ITK\_STRIPS\_R3 L1\_LINKS} \\
\hline
-0xE4D0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_R3L1\_LINK\_11\_R3L1\_0} \\
+0xD7E0 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_R3L1\_LINK\_03\_R3L1\_0} \\
\cline{3-7}
& & & FRAME\_PHASE & 3:2 & W & phase of R3L1 frame with respect to TTC BCR signal \\
& & & L1\_ENABLE & 1 & W & enables sending TTC L1 signals to the front-end \\
@@ -1545,12 +1558,21 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
\hline
\multicolumn{7}{|c|}{\ldots} \\
\hline
-0xE500 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_R3L1\_LINK\_11\_R3L1\_3} \\
+0xD810 & 0,1 & \multicolumn{5}{l|}{CR\_ITK\_R3L1\_LINK\_03\_R3L1\_3} \\
\cline{3-7}
& & & FRAME\_PHASE & 3:2 & W & phase of R3L1 frame with respect to TTC BCR signal \\
& & & L1\_ENABLE & 1 & W & enables sending TTC L1 signals to the front-end \\
& & & R3\_ENABLE & 0 & W & enables sending RoI R3 signals to the front-end \\
\hline
+0xD820 & 0,1 & \multicolumn{2}{l|}{STRIPS\_R3\_TRIGGER} &
+any & T & (for tests only) simulate R3 trigger (issues 4-5 sequential triggers) \\
+\hline
+0xD830 & 0,1 & \multicolumn{2}{l|}{STRIPS\_L1\_TRIGGER} &
+any & T & (for tests only) simulate L1 trigger (issues 4-5 sequential triggers) \\
+\hline
+0xD840 & 0,1 & \multicolumn{2}{l|}{STRIPS\_R3L1\_TRIGGER} &
+any & T & (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers) \\
+\hline
\multicolumn{7}{|c|}{MRO Dregisters} \\
\hline
0xF000 & 0 & \multicolumn{5}{l|}{MROD\_CTRL} \\
diff --git a/sources/templates/registers-4.10.html b/sources/templates/registers-4.10.html
index 436e4dde38c2db6199694c507aaaf41fbda4f9a4..7a309d58b01d5ee2ba74801dcca3a20324e142d5 100644
--- a/sources/templates/registers-4.10.html
+++ b/sources/templates/registers-4.10.html
@@ -2296,9 +2296,15 @@ th {
<td colspan="7" class="group">TTC_DEC_CTRLMON</td>
</tr>
<tr>
- <td rowspan="9">0x8000</td>
- <td rowspan="9">0</td>
- <td rowspan="9">TTC_DEC_CTRL</td>
+ <td rowspan="10">0x8000</td>
+ <td rowspan="10">0</td>
+ <td rowspan="10">TTC_DEC_CTRL</td>
+ <td class="name">L1A_DELAY</td>
+ <td class="range">30..27</td>
+ <td class="type">W</td>
+ <td class="desc">Number of BC to delay the L1A distribution to the frontends</td>
+ </tr>
+ <tr>
<td class="name">BCID_ONBCR</td>
<td class="range">26..15</td>
<td class="type">W</td>
@@ -4270,20 +4276,35 @@ th {
<td colspan="7" class="group">ITK_STRIPS_CTRL</td>
</tr>
<tr>
- <td rowspan="2">0xD000</td>
- <td rowspan="2">0,1</td>
- <td rowspan="2">GLOBAL_STRIPS_CONFIG</td>
- <td class="name">TRICKLE_TRIG_PULSE</td>
- <td class="range">any</td>
- <td class="type">T</td>
- <td class="desc">writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device</td>
+ <td rowspan="3">0xD000</td>
+ <td rowspan="3">0,1</td>
+ <td rowspan="3">GLOBAL_STRIPS_CONFIG</td>
+ <td class="name">TEST_MODULE_MASK</td>
+ <td class="range">15..11</td>
+ <td class="type">W</td>
+ <td class="desc">(for tests only) contains R3 mask for the simulated trigger data</td>
+ </tr>
+ <tr>
+ <td class="name">TEST_R3L1_TAG</td>
+ <td class="range">10..4</td>
+ <td class="type">W</td>
+ <td class="desc">(for tests only) contains R3 or L1 tag for the simulated trigger data</td>
</tr>
<tr>
<td class="name">TTC_GENERATE_GATING_ENABLE</td>
- <td class="range">0</td>
+ <td class="range">1</td>
<td class="type">W</td>
<td class="desc">Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR. TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work. (See also BC_START, and BC_STOP fields)</td>
</tr>
+ <tr>
+ <td rowspan="1">0xD010</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">GLOBAL_TRICKLE_TRIGGER</td>
+ <td class="name"></td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device</td>
+ </tr>
<tr>
<td colspan="7" class="group">ITK_STRIPS_GBT</td>
</tr>
@@ -4291,9 +4312,9 @@ th {
<td colspan="7" class="group">ITK_STRIPS_LCB_LINKS</td>
</tr>
<tr>
- <td rowspan="10">0xD010</td>
- <td rowspan="10">0,1</td>
- <td rowspan="10">CR_ITK_STRIPS_LCB_LINKS_00_LCB_0</td>
+ <td rowspan="9">0xD020</td>
+ <td rowspan="9">0,1</td>
+ <td rowspan="9">CR_ITK_STRIPS_LCB_LINKS_00_LCB_0</td>
<td class="name">L0A_BCR_DELAY</td>
<td class="range">49..38</td>
<td class="type">W</td>
@@ -4341,12 +4362,6 @@ th {
<td class="type">W</td>
<td class="desc">enable generating L0A frames in response to TTC system signals</td>
</tr>
- <tr>
- <td class="name">TRICKLE_TRIG_PULSE</td>
- <td class="range">1</td>
- <td class="type">T</td>
- <td class="desc">writing to this register issues a single trickle trigger</td>
- </tr>
<tr>
<td class="name">TTC_GENERATE_GATING_ENABLE</td>
<td class="range">0</td>
@@ -4354,19 +4369,22 @@ th {
<td class="desc">enables generating trickle gating signal in response to TTC BCR.<br/>TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.<br/>(See also BC_START, and BC_STOP fields) <br/></td>
</tr>
<tr>
- <td rowspan="5">0xD020</td>
- <td rowspan="5">0,1</td>
- <td rowspan="5">CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0</td>
- <td class="name">MOVE_WRITE_PTR</td>
+ <td rowspan="1">0xD030</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_0</td>
+ <td class="name"></td>
<td class="range">any</td>
<td class="type">T</td>
- <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.<br/>The memory must not be actively read out when this signal is sent, otherwise it will be ignored.<br/></td>
+ <td class="desc">writing to this register issues a single trickle trigger</td>
</tr>
<tr>
- <td class="name">ACTUAL_ADDRESS_WIDTH</td>
- <td class="range">57..48</td>
- <td class="type">R</td>
- <td class="desc">Actual valid address width of trickle configuration memory</td>
+ <td rowspan="4">0xD040</td>
+ <td rowspan="4">0,1</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0</td>
+ <td class="name">MOVE_WRITE_PTR</td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address<br/></td>
</tr>
<tr>
<td class="name">WRITE_PTR</td>
@@ -4387,7 +4405,7 @@ th {
<td class="desc">Stop address of trickle configuration in trickle memory (last valid byte)</td>
</tr>
<tr>
- <td rowspan="4">0xD030</td>
+ <td rowspan="4">0xD050</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_0</td>
<td class="name">HCC_MASK</td>
@@ -4414,7 +4432,7 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0xC<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xD040</td>
+ <td rowspan="4">0xD060</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_0</td>
<td class="name">ABC_MASK_HCC_B</td>
@@ -4441,7 +4459,7 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x8<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xD050</td>
+ <td rowspan="4">0xD070</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_0</td>
<td class="name">ABC_MASK_HCC_7</td>
@@ -4468,7 +4486,7 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x4<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xD060</td>
+ <td rowspan="4">0xD080</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_0</td>
<td class="name">ABC_MASK_HCC_3</td>
@@ -4498,9 +4516,9 @@ th {
<td colspan="7" class="group">...</td>
</tr>
<tr>
- <td rowspan="10">0xD130</td>
- <td rowspan="10">0,1</td>
- <td rowspan="10">CR_ITK_STRIPS_LCB_LINKS_00_LCB_3</td>
+ <td rowspan="9">0xD170</td>
+ <td rowspan="9">0,1</td>
+ <td rowspan="9">CR_ITK_STRIPS_LCB_LINKS_00_LCB_3</td>
<td class="name">L0A_BCR_DELAY</td>
<td class="range">49..38</td>
<td class="type">W</td>
@@ -4548,12 +4566,6 @@ th {
<td class="type">W</td>
<td class="desc">enable generating L0A frames in response to TTC system signals</td>
</tr>
- <tr>
- <td class="name">TRICKLE_TRIG_PULSE</td>
- <td class="range">1</td>
- <td class="type">T</td>
- <td class="desc">writing to this register issues a single trickle trigger</td>
- </tr>
<tr>
<td class="name">TTC_GENERATE_GATING_ENABLE</td>
<td class="range">0</td>
@@ -4561,19 +4573,22 @@ th {
<td class="desc">enables generating trickle gating signal in response to TTC BCR.<br/>TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.<br/>(See also BC_START, and BC_STOP fields) <br/></td>
</tr>
<tr>
- <td rowspan="5">0xD140</td>
- <td rowspan="5">0,1</td>
- <td rowspan="5">CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3</td>
- <td class="name">MOVE_WRITE_PTR</td>
+ <td rowspan="1">0xD180</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_3</td>
+ <td class="name"></td>
<td class="range">any</td>
<td class="type">T</td>
- <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.<br/>The memory must not be actively read out when this signal is sent, otherwise it will be ignored.<br/></td>
+ <td class="desc">writing to this register issues a single trickle trigger</td>
</tr>
<tr>
- <td class="name">ACTUAL_ADDRESS_WIDTH</td>
- <td class="range">57..48</td>
- <td class="type">R</td>
- <td class="desc">Actual valid address width of trickle configuration memory</td>
+ <td rowspan="4">0xD190</td>
+ <td rowspan="4">0,1</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3</td>
+ <td class="name">MOVE_WRITE_PTR</td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address<br/></td>
</tr>
<tr>
<td class="name">WRITE_PTR</td>
@@ -4594,7 +4609,7 @@ th {
<td class="desc">Stop address of trickle configuration in trickle memory (last valid byte)</td>
</tr>
<tr>
- <td rowspan="4">0xD150</td>
+ <td rowspan="4">0xD1A0</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_3</td>
<td class="name">HCC_MASK</td>
@@ -4621,7 +4636,7 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0xC<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xD160</td>
+ <td rowspan="4">0xD1B0</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_3</td>
<td class="name">ABC_MASK_HCC_B</td>
@@ -4648,7 +4663,7 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x8<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xD170</td>
+ <td rowspan="4">0xD1C0</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_3</td>
<td class="name">ABC_MASK_HCC_7</td>
@@ -4675,7 +4690,7 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x4<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xD180</td>
+ <td rowspan="4">0xD1D0</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_3</td>
<td class="name">ABC_MASK_HCC_3</td>
@@ -4705,7 +4720,7 @@ th {
<td colspan="7" class="group">ITK_STRIPS_R3 L1_LINKS</td>
</tr>
<tr>
- <td rowspan="3">0xD190</td>
+ <td rowspan="3">0xD1E0</td>
<td rowspan="3">0,1</td>
<td rowspan="3">CR_ITK_R3L1_LINK_00_R3L1_0</td>
<td class="name">FRAME_PHASE</td>
@@ -4729,7 +4744,7 @@ th {
<td colspan="7" class="group">...</td>
</tr>
<tr>
- <td rowspan="3">0xD1C0</td>
+ <td rowspan="3">0xD210</td>
<td rowspan="3">0,1</td>
<td rowspan="3">CR_ITK_R3L1_LINK_00_R3L1_3</td>
<td class="name">FRAME_PHASE</td>
@@ -4756,9 +4771,9 @@ th {
<td colspan="7" class="group">ITK_STRIPS_LCB_LINKS</td>
</tr>
<tr>
- <td rowspan="10">0xE350</td>
- <td rowspan="10">0,1</td>
- <td rowspan="10">CR_ITK_STRIPS_LCB_LINKS_11_LCB_0</td>
+ <td rowspan="9">0xD620</td>
+ <td rowspan="9">0,1</td>
+ <td rowspan="9">CR_ITK_STRIPS_LCB_LINKS_03_LCB_0</td>
<td class="name">L0A_BCR_DELAY</td>
<td class="range">49..38</td>
<td class="type">W</td>
@@ -4806,12 +4821,6 @@ th {
<td class="type">W</td>
<td class="desc">enable generating L0A frames in response to TTC system signals</td>
</tr>
- <tr>
- <td class="name">TRICKLE_TRIG_PULSE</td>
- <td class="range">1</td>
- <td class="type">T</td>
- <td class="desc">writing to this register issues a single trickle trigger</td>
- </tr>
<tr>
<td class="name">TTC_GENERATE_GATING_ENABLE</td>
<td class="range">0</td>
@@ -4819,19 +4828,22 @@ th {
<td class="desc">enables generating trickle gating signal in response to TTC BCR.<br/>TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.<br/>(See also BC_START, and BC_STOP fields) <br/></td>
</tr>
<tr>
- <td rowspan="5">0xE360</td>
- <td rowspan="5">0,1</td>
- <td rowspan="5">CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_0</td>
- <td class="name">MOVE_WRITE_PTR</td>
+ <td rowspan="1">0xD630</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_0</td>
+ <td class="name"></td>
<td class="range">any</td>
<td class="type">T</td>
- <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.<br/>The memory must not be actively read out when this signal is sent, otherwise it will be ignored.<br/></td>
+ <td class="desc">writing to this register issues a single trickle trigger</td>
</tr>
<tr>
- <td class="name">ACTUAL_ADDRESS_WIDTH</td>
- <td class="range">57..48</td>
- <td class="type">R</td>
- <td class="desc">Actual valid address width of trickle configuration memory</td>
+ <td rowspan="4">0xD640</td>
+ <td rowspan="4">0,1</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_0</td>
+ <td class="name">MOVE_WRITE_PTR</td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address<br/></td>
</tr>
<tr>
<td class="name">WRITE_PTR</td>
@@ -4852,9 +4864,9 @@ th {
<td class="desc">Stop address of trickle configuration in trickle memory (last valid byte)</td>
</tr>
<tr>
- <td rowspan="4">0xE370</td>
+ <td rowspan="4">0xD650</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_0</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_0</td>
<td class="name">HCC_MASK</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -4879,9 +4891,9 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0xC<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xE380</td>
+ <td rowspan="4">0xD660</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_0</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_0</td>
<td class="name">ABC_MASK_HCC_B</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -4906,9 +4918,9 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x8<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xE390</td>
+ <td rowspan="4">0xD670</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_0</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_0</td>
<td class="name">ABC_MASK_HCC_7</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -4933,9 +4945,9 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x4<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xE3A0</td>
+ <td rowspan="4">0xD680</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_0</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_0</td>
<td class="name">ABC_MASK_HCC_3</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -4963,9 +4975,9 @@ th {
<td colspan="7" class="group">...</td>
</tr>
<tr>
- <td rowspan="10">0xE470</td>
- <td rowspan="10">0,1</td>
- <td rowspan="10">CR_ITK_STRIPS_LCB_LINKS_11_LCB_3</td>
+ <td rowspan="9">0xD770</td>
+ <td rowspan="9">0,1</td>
+ <td rowspan="9">CR_ITK_STRIPS_LCB_LINKS_03_LCB_3</td>
<td class="name">L0A_BCR_DELAY</td>
<td class="range">49..38</td>
<td class="type">W</td>
@@ -5013,12 +5025,6 @@ th {
<td class="type">W</td>
<td class="desc">enable generating L0A frames in response to TTC system signals</td>
</tr>
- <tr>
- <td class="name">TRICKLE_TRIG_PULSE</td>
- <td class="range">1</td>
- <td class="type">T</td>
- <td class="desc">writing to this register issues a single trickle trigger</td>
- </tr>
<tr>
<td class="name">TTC_GENERATE_GATING_ENABLE</td>
<td class="range">0</td>
@@ -5026,19 +5032,22 @@ th {
<td class="desc">enables generating trickle gating signal in response to TTC BCR.<br/>TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.<br/>(See also BC_START, and BC_STOP fields) <br/></td>
</tr>
<tr>
- <td rowspan="5">0xE480</td>
- <td rowspan="5">0,1</td>
- <td rowspan="5">CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_3</td>
- <td class="name">MOVE_WRITE_PTR</td>
+ <td rowspan="1">0xD780</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_3</td>
+ <td class="name"></td>
<td class="range">any</td>
<td class="type">T</td>
- <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.<br/>The memory must not be actively read out when this signal is sent, otherwise it will be ignored.<br/></td>
+ <td class="desc">writing to this register issues a single trickle trigger</td>
</tr>
<tr>
- <td class="name">ACTUAL_ADDRESS_WIDTH</td>
- <td class="range">57..48</td>
- <td class="type">R</td>
- <td class="desc">Actual valid address width of trickle configuration memory</td>
+ <td rowspan="4">0xD790</td>
+ <td rowspan="4">0,1</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_3</td>
+ <td class="name">MOVE_WRITE_PTR</td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address<br/></td>
</tr>
<tr>
<td class="name">WRITE_PTR</td>
@@ -5059,9 +5068,9 @@ th {
<td class="desc">Stop address of trickle configuration in trickle memory (last valid byte)</td>
</tr>
<tr>
- <td rowspan="4">0xE490</td>
+ <td rowspan="4">0xD7A0</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_3</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_3</td>
<td class="name">HCC_MASK</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -5086,9 +5095,9 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0xC<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xE4A0</td>
+ <td rowspan="4">0xD7B0</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_3</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_3</td>
<td class="name">ABC_MASK_HCC_B</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -5113,9 +5122,9 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x8<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xE4B0</td>
+ <td rowspan="4">0xD7C0</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_3</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_3</td>
<td class="name">ABC_MASK_HCC_7</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -5140,9 +5149,9 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x4<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xE4C0</td>
+ <td rowspan="4">0xD7D0</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_3</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_3</td>
<td class="name">ABC_MASK_HCC_3</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -5170,9 +5179,9 @@ th {
<td colspan="7" class="group">ITK_STRIPS_R3 L1_LINKS</td>
</tr>
<tr>
- <td rowspan="3">0xE4D0</td>
+ <td rowspan="3">0xD7E0</td>
<td rowspan="3">0,1</td>
- <td rowspan="3">CR_ITK_R3L1_LINK_11_R3L1_0</td>
+ <td rowspan="3">CR_ITK_R3L1_LINK_03_R3L1_0</td>
<td class="name">FRAME_PHASE</td>
<td class="range">3..2</td>
<td class="type">W</td>
@@ -5194,9 +5203,9 @@ th {
<td colspan="7" class="group">...</td>
</tr>
<tr>
- <td rowspan="3">0xE500</td>
+ <td rowspan="3">0xD810</td>
<td rowspan="3">0,1</td>
- <td rowspan="3">CR_ITK_R3L1_LINK_11_R3L1_3</td>
+ <td rowspan="3">CR_ITK_R3L1_LINK_03_R3L1_3</td>
<td class="name">FRAME_PHASE</td>
<td class="range">3..2</td>
<td class="type">W</td>
@@ -5214,6 +5223,33 @@ th {
<td class="type">W</td>
<td class="desc">enables sending RoI R3 signals to the front-end</td>
</tr>
+ <tr>
+ <td rowspan="1">0xD820</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">STRIPS_R3_TRIGGER</td>
+ <td class="name"></td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">(for tests only) simulate R3 trigger (issues 4-5 sequential triggers)</td>
+ </tr>
+ <tr>
+ <td rowspan="1">0xD830</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">STRIPS_L1_TRIGGER</td>
+ <td class="name"></td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">(for tests only) simulate L1 trigger (issues 4-5 sequential triggers)</td>
+ </tr>
+ <tr>
+ <td rowspan="1">0xD840</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">STRIPS_R3L1_TRIGGER</td>
+ <td class="name"></td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">(for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)</td>
+ </tr>
<tr>
<td colspan="7" class="group">MRO Dregisters</td>
</tr>
diff --git a/sources/templates/registers-4.10.yaml b/sources/templates/registers-4.10.yaml
index 086b0ae788d123346a5cafe64a18625affd7354c..08d8eaf6cfc2b59a510bb8b8fae09d3b297dbe60 100644
--- a/sources/templates/registers-4.10.yaml
+++ b/sources/templates/registers-4.10.yaml
@@ -796,41 +796,59 @@ EGROUP_FROMHOST:
# ----------------------- ITk strips link configuration start -----------------------
-# Global trickle trigger (all LCB links on this device)
-
-# Maximum LCB links count:
-
-# x24 lpGBT links
-# x4 LCB links per stave
-# x4 R3L1 links per stave
-# => 96 LCB links
-# => 96 R3L1 links
-
-
-
ITK_STRIPS_CTRL:
- entries:
+ entries:
- name: GLOBAL_STRIPS_CONFIG
desc: Synchronous trigger for all LCB links on device
type: W
bitfield:
- - range: any
- type: T
- name: TRICKLE_TRIG_PULSE
- desc: writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
- value: 1
- - range: 0
+ - range: 15..11
+ type: W
+ name: TEST_MODULE_MASK
+ desc: (for tests only) contains R3 mask for the simulated trigger data
+ default: 0x0
+ - range: 10..4
+ type: W
+ name: TEST_R3L1_TAG
+ desc: (for tests only) contains R3 or L1 tag for the simulated trigger data
+ default: 0x0
+ - range: 1
type: W
name: TTC_GENERATE_GATING_ENABLE
desc: Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR.
TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
(See also BC_START, and BC_STOP fields)
- default: 0x0
-
+ default: 0x0
+ - name: GLOBAL_TRICKLE_TRIGGER
+ type: T
+ bitfield:
+ - range: any
+ value: 1
+ desc: writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
+
- ref: ITK_STRIPS_GBT
+ - name: STRIPS_R3_TRIGGER
+ type: T
+ bitfield:
+ - range: any
+ value: 1
+ desc: (for tests only) simulate R3 trigger (issues 4-5 sequential triggers)
+ - name: STRIPS_L1_TRIGGER
+ type: T
+ bitfield:
+ - range: any
+ desc: (for tests only) simulate L1 trigger (issues 4-5 sequential triggers)
+ value: 1
+ - name: STRIPS_R3L1_TRIGGER
+ type: T
+ bitfield:
+ - range: any
+ desc: (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)
+ value: 1
+
ITK_STRIPS_GBT:
- number: 12
+ number: 4
format_name: STRIPS
generate: (GBT_NUM > {index:1} and FIRMWARE_MODE = 5)
entries:
@@ -898,11 +916,6 @@ ITK_STRIPS_LCB_LINKS:
name: TTC_L0A_ENABLE
default: 0x0
desc: enable generating L0A frames in response to TTC system signals
- - range: 1
- type: T
- name: TRICKLE_TRIG_PULSE
- value: 1
- desc: writing to this register issues a single trickle trigger
- range: 0
type: W
name: TTC_GENERATE_GATING_ENABLE
@@ -911,6 +924,14 @@ ITK_STRIPS_LCB_LINKS:
enables generating trickle gating signal in response to TTC BCR.
TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
(See also BC_START, and BC_STOP fields)
+ - name: TRICKLE_TRIGGER
+ format_name: CR_{parent}_{name}_{index}
+ type_name: TRICKLE_TRIGGER
+ type: T
+ bitfield:
+ - range: any
+ desc: writing to this register issues a single trickle trigger
+ value: 1
- name: TRICKLE_MEMORY_CONFIG
format_name: CR_{parent}_{name}_{index}
type_name: LCB_TRICKLE_CONFIG
@@ -922,13 +943,7 @@ ITK_STRIPS_LCB_LINKS:
name: MOVE_WRITE_PTR
value: 1
desc: |
- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
- - range: 57..48
- type: R
- name: ACTUAL_ADDRESS_WIDTH
- value: std_logic_vector(to_unsigned(18,10))
- desc: Actual valid address width of trickle configuration memory
+ Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- range: 47..32
type: W
name: WRITE_PTR
@@ -1095,45 +1110,7 @@ ITK_STRIPS_LCB_LINKS:
desc: |
Masks register commands with destination hcc_id = 0x0
mask(i) <=> (abc_id = i)
- # - name: LINK_STATS
- # format_name: CR_{parent}_{name}
- # type_name: LCB_STATS
- # desc: LCB link statistics
- # type: R
- # bitfield:
- # - range: 48..32
- # type: R
- # name: TTC_FRAME_RECEIVED_COUNT
- # default: 0x0
- # desc: The number of received BCR and L0 frames from TTC system since last reset
- # - range: 31..16
- # type: R
- # name: TTC_FRAME_SENT_COUNT
- # default: 0x0
- # desc: The number of TTC BCR and L0 frames forwarded to the front-end since last reset
- # - range: 15..0
- # type: R
- # name: CMD_DECODER_ERROR_COUNT
- # default: 0x0
- # desc: The number of errors encountered by LCB command decoder since last reset
- # - name: ELINK_RECENT_DATA
- # format_name: CR_{parent}_{name}
- # desc: Most recent data sent into this elink from host (MSB = oldest)
- # type: R
- # bitfield:
- # - range: any
- # type: R
- # name: value
- # default: 0x0
- # - name: ELINK_BYTE_COUNT
- # format_name: CR_{parent}_{name}
- # desc: The number of bytes written to the elink since last reset
- # type: R
- # bitfield:
- # - range: any
- # type: R
- # name: value
- # default: 0x0
+
ITK_STRIPS_R3L1_LINKS:
number: 4
@@ -1161,66 +1138,7 @@ ITK_STRIPS_R3L1_LINKS:
name: R3_ENABLE
default: 0x0
desc: enables sending RoI R3 signals to the front-end
- # - name: LINK_STATUS
- # format_name: CR_{parent}_{name}_{index}
- # type_name: R3L1_STATUS
- # desc: R3L1 link status
- # type: R
- # bitfield:
- # - range: 1
- # type: R
- # name: L1_FIFO_OVERFLOW
- # default: 0x0
- # desc: Whether overflow condition occured in L1 frame FIFO
- # - range: 0
- # type: R
- # name: R3_FIFO_OVERFLOW
- # default: 0x0
- # desc: Whether overflow condition occured in R3 frame FIFO
- # - name: LINK_STATS
- # format_name: CR_{parent}_{name}_{index}
- # type_name: R3L1_STATS
- # desc: R3L1 link statistics
- # type: R
- # bitfield:
- # - range: 63..48
- # type: R
- # name: L1_RECEIVED_COUNT
- # default: 0x0
- # desc: The number of L1 frames received from TTC system since last reset
- # - range: 47..32
- # type: R
- # name: R3_RECEIVED_COUNT
- # default: 0x0
- # desc: The number of R3 frames received from RoI system since last reset
- # - range: 31..16
- # type: R
- # name: L1_SENT_COUNT
- # default: 0x0
- # desc: The number of L1 frames sent to front-end since last reset
- # - range: 15..0
- # type: R
- # name: R3_SENT_COUNT
- # default: 0x0
- # desc: The number of R3 frames sent to front-end since last reset
- # - name: ELINK_RECENT_DATA
- # format_name: CR_{parent}_{name}_{index}
- # desc: Most recent data sent into this elink from host (MSB = oldest)
- # type: R
- # bitfield:
- # - range: any
- # type: R
- # name: value
- # default: 0x0
- # - name: ELINK_BYTE_COUNT
- # format_name: CR_{parent}_{name}_{index}
- # desc: The number of bytes written to the elink since last reset
- # type: R
- # bitfield:
- # - range: any
- # type: R
- # name: value
- # default: 0x0
+
# ----------------------- ITk strips link configuration end -----------------------
@@ -2092,6 +2010,10 @@ TTC_DEC_CTRLMON:
type_name: TTC_DEC_CTRLS
type: W
bitfield:
+ - range: 30..27
+ name: L1A_DELAY
+ type: W
+ desc: Number of BC to delay the L1A distribution to the frontends
- range: 26..15
name: BCID_ONBCR
type: W
diff --git a/sources/templates/registers-5.0.html b/sources/templates/registers-5.0.html
index 553333bc5cb3285fdc28e8f772a348588ca62f09..67f3dc5a425e83b5842f9d89b4e4cc343b6b7cc6 100644
--- a/sources/templates/registers-5.0.html
+++ b/sources/templates/registers-5.0.html
@@ -2278,9 +2278,15 @@ th {
<td colspan="7" class="group">TTC_DEC_CTRLMON</td>
</tr>
<tr>
- <td rowspan="9">0x7000</td>
- <td rowspan="9">0</td>
- <td rowspan="9">TTC_DEC_CTRL</td>
+ <td rowspan="10">0x7000</td>
+ <td rowspan="10">0</td>
+ <td rowspan="10">TTC_DEC_CTRL</td>
+ <td class="name">L1A_DELAY</td>
+ <td class="range">30..27</td>
+ <td class="type">W</td>
+ <td class="desc">Number of BC to delay the L1A distribution to the frontends</td>
+ </tr>
+ <tr>
<td class="name">BCID_ONBCR</td>
<td class="range">26..15</td>
<td class="type">W</td>
@@ -4252,20 +4258,35 @@ th {
<td colspan="7" class="group">ITK_STRIPS_CTRL</td>
</tr>
<tr>
- <td rowspan="2">0xD000</td>
- <td rowspan="2">0,1</td>
- <td rowspan="2">GLOBAL_STRIPS_CONFIG</td>
- <td class="name">TRICKLE_TRIG_PULSE</td>
- <td class="range">any</td>
- <td class="type">T</td>
- <td class="desc">writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device</td>
+ <td rowspan="3">0xD000</td>
+ <td rowspan="3">0,1</td>
+ <td rowspan="3">GLOBAL_STRIPS_CONFIG</td>
+ <td class="name">TEST_MODULE_MASK</td>
+ <td class="range">15..11</td>
+ <td class="type">W</td>
+ <td class="desc">(for tests only) contains R3 mask for the simulated trigger data</td>
+ </tr>
+ <tr>
+ <td class="name">TEST_R3L1_TAG</td>
+ <td class="range">10..4</td>
+ <td class="type">W</td>
+ <td class="desc">(for tests only) contains R3 or L1 tag for the simulated trigger data</td>
</tr>
<tr>
<td class="name">TTC_GENERATE_GATING_ENABLE</td>
- <td class="range">0</td>
+ <td class="range">1</td>
<td class="type">W</td>
<td class="desc">Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR. TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work. (See also BC_START, and BC_STOP fields)</td>
</tr>
+ <tr>
+ <td rowspan="1">0xD010</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">GLOBAL_TRICKLE_TRIGGER</td>
+ <td class="name"></td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device</td>
+ </tr>
<tr>
<td colspan="7" class="group">ITK_STRIPS_GBT</td>
</tr>
@@ -4273,9 +4294,9 @@ th {
<td colspan="7" class="group">ITK_STRIPS_LCB_LINKS</td>
</tr>
<tr>
- <td rowspan="10">0xD010</td>
- <td rowspan="10">0,1</td>
- <td rowspan="10">CR_ITK_STRIPS_LCB_LINKS_00_LCB_0</td>
+ <td rowspan="9">0xD020</td>
+ <td rowspan="9">0,1</td>
+ <td rowspan="9">CR_ITK_STRIPS_LCB_LINKS_00_LCB_0</td>
<td class="name">L0A_BCR_DELAY</td>
<td class="range">49..38</td>
<td class="type">W</td>
@@ -4323,12 +4344,6 @@ th {
<td class="type">W</td>
<td class="desc">enable generating L0A frames in response to TTC system signals</td>
</tr>
- <tr>
- <td class="name">TRICKLE_TRIG_PULSE</td>
- <td class="range">1</td>
- <td class="type">T</td>
- <td class="desc">writing to this register issues a single trickle trigger</td>
- </tr>
<tr>
<td class="name">TTC_GENERATE_GATING_ENABLE</td>
<td class="range">0</td>
@@ -4336,19 +4351,22 @@ th {
<td class="desc">enables generating trickle gating signal in response to TTC BCR.<br/>TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.<br/>(See also BC_START, and BC_STOP fields) <br/></td>
</tr>
<tr>
- <td rowspan="5">0xD020</td>
- <td rowspan="5">0,1</td>
- <td rowspan="5">CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0</td>
- <td class="name">MOVE_WRITE_PTR</td>
+ <td rowspan="1">0xD030</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_0</td>
+ <td class="name"></td>
<td class="range">any</td>
<td class="type">T</td>
- <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.<br/>The memory must not be actively read out when this signal is sent, otherwise it will be ignored.<br/></td>
+ <td class="desc">writing to this register issues a single trickle trigger</td>
</tr>
<tr>
- <td class="name">ACTUAL_ADDRESS_WIDTH</td>
- <td class="range">57..48</td>
- <td class="type">R</td>
- <td class="desc">Actual valid address width of trickle configuration memory</td>
+ <td rowspan="4">0xD040</td>
+ <td rowspan="4">0,1</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_0</td>
+ <td class="name">MOVE_WRITE_PTR</td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address<br/></td>
</tr>
<tr>
<td class="name">WRITE_PTR</td>
@@ -4369,7 +4387,7 @@ th {
<td class="desc">Stop address of trickle configuration in trickle memory (last valid byte)</td>
</tr>
<tr>
- <td rowspan="4">0xD030</td>
+ <td rowspan="4">0xD050</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_0</td>
<td class="name">HCC_MASK</td>
@@ -4396,7 +4414,7 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0xC<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xD040</td>
+ <td rowspan="4">0xD060</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_0</td>
<td class="name">ABC_MASK_HCC_B</td>
@@ -4423,7 +4441,7 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x8<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xD050</td>
+ <td rowspan="4">0xD070</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_0</td>
<td class="name">ABC_MASK_HCC_7</td>
@@ -4450,7 +4468,7 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x4<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xD060</td>
+ <td rowspan="4">0xD080</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_0</td>
<td class="name">ABC_MASK_HCC_3</td>
@@ -4480,9 +4498,9 @@ th {
<td colspan="7" class="group">...</td>
</tr>
<tr>
- <td rowspan="10">0xD130</td>
- <td rowspan="10">0,1</td>
- <td rowspan="10">CR_ITK_STRIPS_LCB_LINKS_00_LCB_3</td>
+ <td rowspan="9">0xD170</td>
+ <td rowspan="9">0,1</td>
+ <td rowspan="9">CR_ITK_STRIPS_LCB_LINKS_00_LCB_3</td>
<td class="name">L0A_BCR_DELAY</td>
<td class="range">49..38</td>
<td class="type">W</td>
@@ -4530,12 +4548,6 @@ th {
<td class="type">W</td>
<td class="desc">enable generating L0A frames in response to TTC system signals</td>
</tr>
- <tr>
- <td class="name">TRICKLE_TRIG_PULSE</td>
- <td class="range">1</td>
- <td class="type">T</td>
- <td class="desc">writing to this register issues a single trickle trigger</td>
- </tr>
<tr>
<td class="name">TTC_GENERATE_GATING_ENABLE</td>
<td class="range">0</td>
@@ -4543,19 +4555,22 @@ th {
<td class="desc">enables generating trickle gating signal in response to TTC BCR.<br/>TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.<br/>(See also BC_START, and BC_STOP fields) <br/></td>
</tr>
<tr>
- <td rowspan="5">0xD140</td>
- <td rowspan="5">0,1</td>
- <td rowspan="5">CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3</td>
- <td class="name">MOVE_WRITE_PTR</td>
+ <td rowspan="1">0xD180</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_TRIGGER_3</td>
+ <td class="name"></td>
<td class="range">any</td>
<td class="type">T</td>
- <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.<br/>The memory must not be actively read out when this signal is sent, otherwise it will be ignored.<br/></td>
+ <td class="desc">writing to this register issues a single trickle trigger</td>
</tr>
<tr>
- <td class="name">ACTUAL_ADDRESS_WIDTH</td>
- <td class="range">57..48</td>
- <td class="type">R</td>
- <td class="desc">Actual valid address width of trickle configuration memory</td>
+ <td rowspan="4">0xD190</td>
+ <td rowspan="4">0,1</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_TRICKLE_MEMORY_CONFIG_3</td>
+ <td class="name">MOVE_WRITE_PTR</td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address<br/></td>
</tr>
<tr>
<td class="name">WRITE_PTR</td>
@@ -4576,7 +4591,7 @@ th {
<td class="desc">Stop address of trickle configuration in trickle memory (last valid byte)</td>
</tr>
<tr>
- <td rowspan="4">0xD150</td>
+ <td rowspan="4">0xD1A0</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_MODULE_MASK_F_C_3</td>
<td class="name">HCC_MASK</td>
@@ -4603,7 +4618,7 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0xC<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xD160</td>
+ <td rowspan="4">0xD1B0</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_B_8_3</td>
<td class="name">ABC_MASK_HCC_B</td>
@@ -4630,7 +4645,7 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x8<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xD170</td>
+ <td rowspan="4">0xD1C0</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_7_4_3</td>
<td class="name">ABC_MASK_HCC_7</td>
@@ -4657,7 +4672,7 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x4<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xD180</td>
+ <td rowspan="4">0xD1D0</td>
<td rowspan="4">0,1</td>
<td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_00_ABC_MODULE_MASK_3_0_3</td>
<td class="name">ABC_MASK_HCC_3</td>
@@ -4687,7 +4702,7 @@ th {
<td colspan="7" class="group">ITK_STRIPS_R3 L1_LINKS</td>
</tr>
<tr>
- <td rowspan="3">0xD190</td>
+ <td rowspan="3">0xD1E0</td>
<td rowspan="3">0,1</td>
<td rowspan="3">CR_ITK_R3L1_LINK_00_R3L1_0</td>
<td class="name">FRAME_PHASE</td>
@@ -4711,7 +4726,7 @@ th {
<td colspan="7" class="group">...</td>
</tr>
<tr>
- <td rowspan="3">0xD1C0</td>
+ <td rowspan="3">0xD210</td>
<td rowspan="3">0,1</td>
<td rowspan="3">CR_ITK_R3L1_LINK_00_R3L1_3</td>
<td class="name">FRAME_PHASE</td>
@@ -4738,9 +4753,9 @@ th {
<td colspan="7" class="group">ITK_STRIPS_LCB_LINKS</td>
</tr>
<tr>
- <td rowspan="10">0xE350</td>
- <td rowspan="10">0,1</td>
- <td rowspan="10">CR_ITK_STRIPS_LCB_LINKS_11_LCB_0</td>
+ <td rowspan="9">0xD620</td>
+ <td rowspan="9">0,1</td>
+ <td rowspan="9">CR_ITK_STRIPS_LCB_LINKS_03_LCB_0</td>
<td class="name">L0A_BCR_DELAY</td>
<td class="range">49..38</td>
<td class="type">W</td>
@@ -4788,12 +4803,6 @@ th {
<td class="type">W</td>
<td class="desc">enable generating L0A frames in response to TTC system signals</td>
</tr>
- <tr>
- <td class="name">TRICKLE_TRIG_PULSE</td>
- <td class="range">1</td>
- <td class="type">T</td>
- <td class="desc">writing to this register issues a single trickle trigger</td>
- </tr>
<tr>
<td class="name">TTC_GENERATE_GATING_ENABLE</td>
<td class="range">0</td>
@@ -4801,19 +4810,22 @@ th {
<td class="desc">enables generating trickle gating signal in response to TTC BCR.<br/>TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.<br/>(See also BC_START, and BC_STOP fields) <br/></td>
</tr>
<tr>
- <td rowspan="5">0xE360</td>
- <td rowspan="5">0,1</td>
- <td rowspan="5">CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_0</td>
- <td class="name">MOVE_WRITE_PTR</td>
+ <td rowspan="1">0xD630</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_0</td>
+ <td class="name"></td>
<td class="range">any</td>
<td class="type">T</td>
- <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.<br/>The memory must not be actively read out when this signal is sent, otherwise it will be ignored.<br/></td>
+ <td class="desc">writing to this register issues a single trickle trigger</td>
</tr>
<tr>
- <td class="name">ACTUAL_ADDRESS_WIDTH</td>
- <td class="range">57..48</td>
- <td class="type">R</td>
- <td class="desc">Actual valid address width of trickle configuration memory</td>
+ <td rowspan="4">0xD640</td>
+ <td rowspan="4">0,1</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_0</td>
+ <td class="name">MOVE_WRITE_PTR</td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address<br/></td>
</tr>
<tr>
<td class="name">WRITE_PTR</td>
@@ -4834,9 +4846,9 @@ th {
<td class="desc">Stop address of trickle configuration in trickle memory (last valid byte)</td>
</tr>
<tr>
- <td rowspan="4">0xE370</td>
+ <td rowspan="4">0xD650</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_0</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_0</td>
<td class="name">HCC_MASK</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -4861,9 +4873,9 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0xC<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xE380</td>
+ <td rowspan="4">0xD660</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_0</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_0</td>
<td class="name">ABC_MASK_HCC_B</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -4888,9 +4900,9 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x8<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xE390</td>
+ <td rowspan="4">0xD670</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_0</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_0</td>
<td class="name">ABC_MASK_HCC_7</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -4915,9 +4927,9 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x4<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xE3A0</td>
+ <td rowspan="4">0xD680</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_0</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_0</td>
<td class="name">ABC_MASK_HCC_3</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -4945,9 +4957,9 @@ th {
<td colspan="7" class="group">...</td>
</tr>
<tr>
- <td rowspan="10">0xE470</td>
- <td rowspan="10">0,1</td>
- <td rowspan="10">CR_ITK_STRIPS_LCB_LINKS_11_LCB_3</td>
+ <td rowspan="9">0xD770</td>
+ <td rowspan="9">0,1</td>
+ <td rowspan="9">CR_ITK_STRIPS_LCB_LINKS_03_LCB_3</td>
<td class="name">L0A_BCR_DELAY</td>
<td class="range">49..38</td>
<td class="type">W</td>
@@ -4995,12 +5007,6 @@ th {
<td class="type">W</td>
<td class="desc">enable generating L0A frames in response to TTC system signals</td>
</tr>
- <tr>
- <td class="name">TRICKLE_TRIG_PULSE</td>
- <td class="range">1</td>
- <td class="type">T</td>
- <td class="desc">writing to this register issues a single trickle trigger</td>
- </tr>
<tr>
<td class="name">TTC_GENERATE_GATING_ENABLE</td>
<td class="range">0</td>
@@ -5008,19 +5014,22 @@ th {
<td class="desc">enables generating trickle gating signal in response to TTC BCR.<br/>TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.<br/>(See also BC_START, and BC_STOP fields) <br/></td>
</tr>
<tr>
- <td rowspan="5">0xE480</td>
- <td rowspan="5">0,1</td>
- <td rowspan="5">CR_ITK_STRIPS_LCB_LINKS_11_TRICKLE_MEMORY_CONFIG_3</td>
- <td class="name">MOVE_WRITE_PTR</td>
+ <td rowspan="1">0xD780</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_TRIGGER_3</td>
+ <td class="name"></td>
<td class="range">any</td>
<td class="type">T</td>
- <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.<br/>The memory must not be actively read out when this signal is sent, otherwise it will be ignored.<br/></td>
+ <td class="desc">writing to this register issues a single trickle trigger</td>
</tr>
<tr>
- <td class="name">ACTUAL_ADDRESS_WIDTH</td>
- <td class="range">57..48</td>
- <td class="type">R</td>
- <td class="desc">Actual valid address width of trickle configuration memory</td>
+ <td rowspan="4">0xD790</td>
+ <td rowspan="4">0,1</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_TRICKLE_MEMORY_CONFIG_3</td>
+ <td class="name">MOVE_WRITE_PTR</td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address<br/></td>
</tr>
<tr>
<td class="name">WRITE_PTR</td>
@@ -5041,9 +5050,9 @@ th {
<td class="desc">Stop address of trickle configuration in trickle memory (last valid byte)</td>
</tr>
<tr>
- <td rowspan="4">0xE490</td>
+ <td rowspan="4">0xD7A0</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_MODULE_MASK_F_C_3</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_MODULE_MASK_F_C_3</td>
<td class="name">HCC_MASK</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -5068,9 +5077,9 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0xC<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xE4A0</td>
+ <td rowspan="4">0xD7B0</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_B_8_3</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_B_8_3</td>
<td class="name">ABC_MASK_HCC_B</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -5095,9 +5104,9 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x8<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xE4B0</td>
+ <td rowspan="4">0xD7C0</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_7_4_3</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_7_4_3</td>
<td class="name">ABC_MASK_HCC_7</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -5122,9 +5131,9 @@ th {
<td class="desc">Masks register commands with destination hcc_id = 0x4<br/>mask(i) <=> (abc_id = i)<br/></td>
</tr>
<tr>
- <td rowspan="4">0xE4C0</td>
+ <td rowspan="4">0xD7D0</td>
<td rowspan="4">0,1</td>
- <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_11_ABC_MODULE_MASK_3_0_3</td>
+ <td rowspan="4">CR_ITK_STRIPS_LCB_LINKS_03_ABC_MODULE_MASK_3_0_3</td>
<td class="name">ABC_MASK_HCC_3</td>
<td class="range">63..48</td>
<td class="type">W</td>
@@ -5152,9 +5161,9 @@ th {
<td colspan="7" class="group">ITK_STRIPS_R3 L1_LINKS</td>
</tr>
<tr>
- <td rowspan="3">0xE4D0</td>
+ <td rowspan="3">0xD7E0</td>
<td rowspan="3">0,1</td>
- <td rowspan="3">CR_ITK_R3L1_LINK_11_R3L1_0</td>
+ <td rowspan="3">CR_ITK_R3L1_LINK_03_R3L1_0</td>
<td class="name">FRAME_PHASE</td>
<td class="range">3..2</td>
<td class="type">W</td>
@@ -5176,9 +5185,9 @@ th {
<td colspan="7" class="group">...</td>
</tr>
<tr>
- <td rowspan="3">0xE500</td>
+ <td rowspan="3">0xD810</td>
<td rowspan="3">0,1</td>
- <td rowspan="3">CR_ITK_R3L1_LINK_11_R3L1_3</td>
+ <td rowspan="3">CR_ITK_R3L1_LINK_03_R3L1_3</td>
<td class="name">FRAME_PHASE</td>
<td class="range">3..2</td>
<td class="type">W</td>
@@ -5196,6 +5205,33 @@ th {
<td class="type">W</td>
<td class="desc">enables sending RoI R3 signals to the front-end</td>
</tr>
+ <tr>
+ <td rowspan="1">0xD820</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">STRIPS_R3_TRIGGER</td>
+ <td class="name"></td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">(for tests only) simulate R3 trigger (issues 4-5 sequential triggers)</td>
+ </tr>
+ <tr>
+ <td rowspan="1">0xD830</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">STRIPS_L1_TRIGGER</td>
+ <td class="name"></td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">(for tests only) simulate L1 trigger (issues 4-5 sequential triggers)</td>
+ </tr>
+ <tr>
+ <td rowspan="1">0xD840</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">STRIPS_R3L1_TRIGGER</td>
+ <td class="name"></td>
+ <td class="range">any</td>
+ <td class="type">T</td>
+ <td class="desc">(for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)</td>
+ </tr>
<tr>
<td colspan="7" class="group">MRO Dregisters</td>
</tr>
diff --git a/sources/templates/registers-5.0.yaml b/sources/templates/registers-5.0.yaml
index ea4371d548750e9326d402e468cec1e7b657e0bf..c3e5c2239e6c3beedbafb2e3d54e831a279c320c 100644
--- a/sources/templates/registers-5.0.yaml
+++ b/sources/templates/registers-5.0.yaml
@@ -1487,6 +1487,10 @@ TTC_DEC_CTRLMON:
type_name: TTC_DEC_CTRLS
type: W
bitfield:
+ - range: 30..27
+ name: L1A_DELAY
+ type: W
+ desc: Number of BC to delay the L1A distribution to the frontends
- range: 26..15
name: BCID_ONBCR
type: W
@@ -2630,38 +2634,59 @@ Wishbone:
# ----------------------- ITk strips link configuration start -----------------------
-# Global trickle trigger (all LCB links on this device)
-
-# Maximum LCB links count:
-
-# x24 lpGBT links
-# x4 LCB links per stave
-# x4 R3L1 links per stave
-# => 96 LCB links
-# => 96 R3L1 links
ITK_STRIPS_CTRL:
- entries:
+ entries:
- name: GLOBAL_STRIPS_CONFIG
desc: Synchronous trigger for all LCB links on device
type: W
bitfield:
- - range: any
- type: T
- name: TRICKLE_TRIG_PULSE
- desc: writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
- value: 1
- - range: 0
+ - range: 15..11
+ type: W
+ name: TEST_MODULE_MASK
+ desc: (for tests only) contains R3 mask for the simulated trigger data
+ default: 0x0
+ - range: 10..4
+ type: W
+ name: TEST_R3L1_TAG
+ desc: (for tests only) contains R3 or L1 tag for the simulated trigger data
+ default: 0x0
+ - range: 1
type: W
name: TTC_GENERATE_GATING_ENABLE
desc: Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR.
TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
(See also BC_START, and BC_STOP fields)
- default: 0x0
-
+ default: 0x0
+ - name: GLOBAL_TRICKLE_TRIGGER
+ type: T
+ bitfield:
+ - range: any
+ value: 1
+ desc: writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
+
- ref: ITK_STRIPS_GBT
+ - name: STRIPS_R3_TRIGGER
+ type: T
+ bitfield:
+ - range: any
+ value: 1
+ desc: (for tests only) simulate R3 trigger (issues 4-5 sequential triggers)
+ - name: STRIPS_L1_TRIGGER
+ type: T
+ bitfield:
+ - range: any
+ desc: (for tests only) simulate L1 trigger (issues 4-5 sequential triggers)
+ value: 1
+ - name: STRIPS_R3L1_TRIGGER
+ type: T
+ bitfield:
+ - range: any
+ desc: (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)
+ value: 1
+
ITK_STRIPS_GBT:
- number: 12
+ number: 4
format_name: STRIPS
generate: (GBT_NUM > {index:1} and FIRMWARE_MODE = 5)
entries:
@@ -2729,11 +2754,6 @@ ITK_STRIPS_LCB_LINKS:
name: TTC_L0A_ENABLE
default: 0x0
desc: enable generating L0A frames in response to TTC system signals
- - range: 1
- type: T
- name: TRICKLE_TRIG_PULSE
- value: 1
- desc: writing to this register issues a single trickle trigger
- range: 0
type: W
name: TTC_GENERATE_GATING_ENABLE
@@ -2742,6 +2762,14 @@ ITK_STRIPS_LCB_LINKS:
enables generating trickle gating signal in response to TTC BCR.
TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
(See also BC_START, and BC_STOP fields)
+ - name: TRICKLE_TRIGGER
+ format_name: CR_{parent}_{name}_{index}
+ type_name: TRICKLE_TRIGGER
+ type: T
+ bitfield:
+ - range: any
+ desc: writing to this register issues a single trickle trigger
+ value: 1
- name: TRICKLE_MEMORY_CONFIG
format_name: CR_{parent}_{name}_{index}
type_name: LCB_TRICKLE_CONFIG
@@ -2753,13 +2781,7 @@ ITK_STRIPS_LCB_LINKS:
name: MOVE_WRITE_PTR
value: 1
desc: |
- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address.
- The memory must not be actively read out when this signal is sent, otherwise it will be ignored.
- - range: 57..48
- type: R
- name: ACTUAL_ADDRESS_WIDTH
- value: std_logic_vector(to_unsigned(18,10))
- desc: Actual valid address width of trickle configuration memory
+ Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- range: 47..32
type: W
name: WRITE_PTR
@@ -2926,45 +2948,7 @@ ITK_STRIPS_LCB_LINKS:
desc: |
Masks register commands with destination hcc_id = 0x0
mask(i) <=> (abc_id = i)
- # - name: LINK_STATS
- # format_name: CR_{parent}_{name}
- # type_name: LCB_STATS
- # desc: LCB link statistics
- # type: R
- # bitfield:
- # - range: 48..32
- # type: R
- # name: TTC_FRAME_RECEIVED_COUNT
- # default: 0x0
- # desc: The number of received BCR and L0 frames from TTC system since last reset
- # - range: 31..16
- # type: R
- # name: TTC_FRAME_SENT_COUNT
- # default: 0x0
- # desc: The number of TTC BCR and L0 frames forwarded to the front-end since last reset
- # - range: 15..0
- # type: R
- # name: CMD_DECODER_ERROR_COUNT
- # default: 0x0
- # desc: The number of errors encountered by LCB command decoder since last reset
- # - name: ELINK_RECENT_DATA
- # format_name: CR_{parent}_{name}
- # desc: Most recent data sent into this elink from host (MSB = oldest)
- # type: R
- # bitfield:
- # - range: any
- # type: R
- # name: value
- # default: 0x0
- # - name: ELINK_BYTE_COUNT
- # format_name: CR_{parent}_{name}
- # desc: The number of bytes written to the elink since last reset
- # type: R
- # bitfield:
- # - range: any
- # type: R
- # name: value
- # default: 0x0
+
ITK_STRIPS_R3L1_LINKS:
number: 4
@@ -2992,67 +2976,8 @@ ITK_STRIPS_R3L1_LINKS:
name: R3_ENABLE
default: 0x0
desc: enables sending RoI R3 signals to the front-end
- # - name: LINK_STATUS
- # format_name: CR_{parent}_{name}_{index}
- # type_name: R3L1_STATUS
- # desc: R3L1 link status
- # type: R
- # bitfield:
- # - range: 1
- # type: R
- # name: L1_FIFO_OVERFLOW
- # default: 0x0
- # desc: Whether overflow condition occured in L1 frame FIFO
- # - range: 0
- # type: R
- # name: R3_FIFO_OVERFLOW
- # default: 0x0
- # desc: Whether overflow condition occured in R3 frame FIFO
- # - name: LINK_STATS
- # format_name: CR_{parent}_{name}_{index}
- # type_name: R3L1_STATS
- # desc: R3L1 link statistics
- # type: R
- # bitfield:
- # - range: 63..48
- # type: R
- # name: L1_RECEIVED_COUNT
- # default: 0x0
- # desc: The number of L1 frames received from TTC system since last reset
- # - range: 47..32
- # type: R
- # name: R3_RECEIVED_COUNT
- # default: 0x0
- # desc: The number of R3 frames received from RoI system since last reset
- # - range: 31..16
- # type: R
- # name: L1_SENT_COUNT
- # default: 0x0
- # desc: The number of L1 frames sent to front-end since last reset
- # - range: 15..0
- # type: R
- # name: R3_SENT_COUNT
- # default: 0x0
- # desc: The number of R3 frames sent to front-end since last reset
- # - name: ELINK_RECENT_DATA
- # format_name: CR_{parent}_{name}_{index}
- # desc: Most recent data sent into this elink from host (MSB = oldest)
- # type: R
- # bitfield:
- # - range: any
- # type: R
- # name: value
- # default: 0x0
- # - name: ELINK_BYTE_COUNT
- # format_name: CR_{parent}_{name}_{index}
- # desc: The number of bytes written to the elink since last reset
- # type: R
- # bitfield:
- # - range: any
- # type: R
- # name: value
- # default: 0x0
-
+
+
# ----------------------- ITk strips link configuration end -----------------------
diff --git a/sources/templates/registers-diff-4.10-5.0.html b/sources/templates/registers-diff-4.10-5.0.html
index 37222d70968b085227a27bd574becba45a6ee4fd..1e43cab2d53217fd5911da23beef9520e261cae1 100644
--- a/sources/templates/registers-diff-4.10-5.0.html
+++ b/sources/templates/registers-diff-4.10-5.0.html
@@ -42463,15 +42463,23 @@ th {
<td colspan="10" class="group"></td>
</tr>
<tr>
- <td class="sequence" rowspan="10">807*</td>
- <td class="state changedChanged" rowspan="10">Changed</td>
- <td class="address changedNone" rowspan="10">0x8000</td>
- <td class="endpoints changedNone" rowspan="10">0</td>
+ <td class="sequence" rowspan="11">807*</td>
+ <td class="state changedChanged" rowspan="11">Changed</td>
+ <td class="address changedNone" rowspan="11">0x8000</td>
+ <td class="endpoints changedNone" rowspan="11">0</td>
<td class="name changedNone" colspan="7">TTC_DEC_CTRL</td>
</tr>
<tr>
- <td rowspan="9"></td>
+ <td rowspan="10"></td>
+ <td class="state changed"></td>
+ <td class="field changedNone">L1A_DELAY</td>
+ <td class="range changedNone">30..27</td>
+ <td class="type changedNone">W</td>
+ <td class="desc changedNone">Number of BC to delay the L1A distribution to the frontends</td>
+ <td class="value changedNone">None</td>
+ </tr>
+ <tr>
<td class="state changed"></td>
<td class="field changedNone">BCID_ONBCR</td>
<td class="range changedNone">26..15</td>
@@ -42545,15 +42553,23 @@ th {
</tr>
<tr>
- <td class="sequence" rowspan="10">807*</td>
- <td class="state changedInto" rowspan="10">Into</td>
- <td class="address changedTrue" rowspan="10">0x7000</td>
- <td class="endpoints changedFalse" rowspan="10">0</td>
+ <td class="sequence" rowspan="11">807*</td>
+ <td class="state changedInto" rowspan="11">Into</td>
+ <td class="address changedTrue" rowspan="11">0x7000</td>
+ <td class="endpoints changedFalse" rowspan="11">0</td>
<td class="name changedNone" colspan="7">TTC_DEC_CTRL</td>
</tr>
<tr>
- <td rowspan="9"></td>
+ <td rowspan="10"></td>
+ <td class="state changed"></td>
+ <td class="field changedNone">L1A_DELAY</td>
+ <td class="range changedFalse">30..27</td>
+ <td class="type changedFalse">W</td>
+ <td class="desc changedFalse">Number of BC to delay the L1A distribution to the frontends</td>
+ <td class="value changedFalse">None</td>
+ </tr>
+ <tr>
<td class="state changed"></td>
<td class="field changedNone">BCID_ONBCR</td>
<td class="range changedFalse">26..15</td>
diff --git a/sources/templates/registers.pdf b/sources/templates/registers.pdf
index d1dbb1685db768a4132c3f4b51a0e9d3f276995d..9fbb837fb77de55f7a5596161095b8df244c4ffa 100644
Binary files a/sources/templates/registers.pdf and b/sources/templates/registers.pdf differ