diff --git a/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd b/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd
index 383f024b1300578c487ef59a83f32bb14e408913..3a5672ab0e75cecbe7df40c31eb2350f8c707d13 100644
--- a/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd
+++ b/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd
@@ -371,6 +371,9 @@ architecture Behavioral of FELIX_gbt_wrapper_KCU is
   signal rxpolarity_RXUSRCLK : std_logic_vector(GBT_NUM-1 downto 0); 
   signal txpolarity_TXUSRCLK : std_logic_vector(GBT_NUM-1 downto 0); 
 
+  attribute use_dsp : string;
+  --attribute use_dsp of fec_error_cnt : signal is "yes";
+  
 begin
 
   FRAME_LOCKED_O <= alignment_done_f(GBT_NUM-1 downto 0);
@@ -809,9 +812,11 @@ end generate g_refclk_48ch;
 
   register_map_gbt_monitor.GBT_OUT_MUX_STATUS(47 downto 0)    <= outsel_o(47 downto 0);
   register_map_gbt_monitor.GBT_ERROR(47 downto 0)             <= error_f(47 downto 0);
+  
 
   error_gen : for i in 47 downto 0 generate
     signal fec_error_cnt: std_logic_vector(31 downto 0);
+    attribute use_dsp of fec_error_cnt : signal is "yes";
     signal error_f_p1: std_logic;
   begin
     error_f(i) <= error_orig(i) and alignment_done_f(i);
diff --git a/sources/centralRouter/EPROC_OUT8.vhd b/sources/centralRouter/EPROC_OUT8.vhd
index 5b1ddd6156131d010731bb85095ce0e2ba0a11f4..a3c432eee15f7065222ce1d90ee03a77fef14ff3 100644
--- a/sources/centralRouter/EPROC_OUT8.vhd
+++ b/sources/centralRouter/EPROC_OUT8.vhd
@@ -66,7 +66,7 @@ constant zeros8bit  : std_logic_vector (7 downto 0) := (others=>'0');
 signal EdataOUT_ENC8b10b_case, EdataOUT_direct_case, EdataOUT_HDLC_case, EdataOUT_TTC3_case, EdataOUT_TTC4_case, EdataOUT_TTC4_case_old, EdataOUT_TTC7_case: std_logic_vector (7 downto 0);
 signal rst40_s, rst160_s, rst40_case001, rst160_case001, rst_case011 : std_logic;
 signal getDataTrig_ENC8b10b_case, getDataTrig_direct_case, getDataTrig_HDLC_case : std_logic;
-signal edata_out_s : std_logic_vector (7 downto 0);
+signal edata_out_s : std_logic_vector (7 downto 0) := "01010101";
 signal ao_edata_out: std_logic_vector (7 downto 0); --IG always on data out
 
 signal TTCin_r  : std_logic_vector(17 downto 0); -- use to sync the TTCin vector with the extended BCR pulse. RL: changed dimention to 16 downto 0
@@ -75,6 +75,8 @@ signal TTCin_r9 : std_logic; -- broadcast bit#7 signal. When set, extend the BCR
 signal ENA_160: std_logic;
 signal ENCODING_160: std_logic_vector(3 downto 0);
 signal new_SCA_reset_cnt: std_logic := '1'; --for NSW FLXUSER-648
+signal LFSRstate : STD_LOGIC_VECTOR(9 downto 0) := "1010101010";--for NSW FLXUSER-648
+
 begin
 
 Module_enable: if (
@@ -173,7 +175,7 @@ begin
         when "00"   => edata_out_s <= EdataOUT_direct_case;
         when "01"   => edata_out_s <= EdataOUT_ENC8b10b_case;
         when "10"   => edata_out_s <= EdataOUT_HDLC_case;
-        when others => edata_out_s <= (others => '0');
+        when others => edata_out_s <= "01010101"; --(others => '0');
     end case;
 end process;
 
@@ -199,7 +201,7 @@ Module_disable: if  (
                         (includeNoEncodingCase = false)
                     ) generate
 
-    edata_out_s <= (others => '0');
+    edata_out_s <= "01010101"; --(others => '0');
     getDataTrig <= '0';
 
 end generate Module_disable;
@@ -235,17 +237,23 @@ rst_case011 <= '0' when ((rst40_s = '0') and ((ENCODING(2 downto 0) = "011") or
 --RL: TTCin(15)   <= add_d8(4); Brcst[6]
 --RL: TTCin(16)   <= add_d8(5); Brcst[7]
 
+new_SCA_reset_cnt <= LFSRstate(0);
+
 ttc_r: process(bitCLK)
 begin
     if bitCLK'event and bitCLK = '1' then
     
-        new_SCA_reset_cnt <= not new_SCA_reset_cnt; -- 20 MHz counter    
+        --new_SCA_reset_cnt <= not new_SCA_reset_cnt; -- the 20 MHz counter    
     
         if (rst_case011 = '1') then
             EdataOUT_TTC3_case <= zeros8bit;
             EdataOUT_TTC4_case <= zeros8bit;
             EdataOUT_TTC7_case <= zeros8bit;
+            LFSRstate <= "1010101010";
         else
+        
+            LFSRstate <= LFSRstate(9) xor LFSRstate(7) xor LFSRstate(6) xor LFSRstate(1) & LFSRstate(9 downto 1);
+            
             EdataOUT_TTC3_case <= TTCin(1) & TTCin(7 downto 2) & TTCin(0);
             --IG: Read Out Controller implementation:
             --IG: TTCin(2) - data overwrite by TTCin_r2 and extend to 2 clock cycles once an "OCR" (pulse from brc_t2(1)) set
@@ -336,7 +344,7 @@ port map(
 	data4    => EdataOUT_TTC4_case,
 	data5    => EdataOUT_TTC4_case_old,--zeros8bit, --FEI4 
 	data6    => EdataOUT_TTC7_case,
-	data7    => zeros8bit,
+	data7    => "01010101", --zeros8bit,
 	sel      => ENCODING(2 downto 0),
 	data_out => ao_edata_out
 	);