diff --git a/sources/feligHG710/data_generator/elink_data_emulator.vhd b/sources/feligHG710/data_generator/elink_data_emulator.vhd
index 87b967e86fda0d57e98d2c2658c09c6f3ad55e88..ce583c9ade36aa1335e77526f6520a3ac4475c6c 100644
--- a/sources/feligHG710/data_generator/elink_data_emulator.vhd
+++ b/sources/feligHG710/data_generator/elink_data_emulator.vhd
@@ -18,419 +18,428 @@
--! See the License for the specific language governing permissions and
--! limitations under the License.
---==============================================================================
---
--- Argonne National Laboratory
--- High Energy Physics
--- Electronics Group
---
--- Engineer: John Anderson, Soo Ryu
--- Modified By: Michael Oberling
---
--- Design Name: elink_data_emulator_lightweight
--- Version: 1.0
--- Date: 9/13/2017
---
--- Description: Coming soon.
---
--- Change Log: V1.0 -
---
---==============================================================================
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
---MT
-use IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
---
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-use work.type_lib.ALL;
-
-use work.centralRouter_package.all;
-
---Frans 1
-use work.pcie_package.all;
-entity elink_data_emulator is
-generic (
- epath : std_logic_vector (4 downto 0);
- egroup : std_logic_vector (2 downto 0);
- --Frans 2
- LANE_ID : integer := 0
-
-);
-port (
- clk40 : in STD_LOGIC;
- clk240 : in STD_LOGIC;
- emu_control : in lane_emulator_control;
- elink_data_out : out STD_LOGIC_VECTOR (9 downto 0);
- elink_data_re : in std_logic;
- l1a_trig : in STD_LOGIC;
- l1a_id : in STD_LOGIC_VECTOR (15 downto 0);
- flag_data_gen : out std_logic; --RL added to be used to sync the read enables
- SELECT_RANDOM : in std_logic_vector(0 downto 0);
- chunk_length_out : out std_logic_vector(11 downto 0) ;
- --MT 2 (Fran 2)
- FMEMU_RANDOM_RAM_ADDR : in std_logic_vector(9 downto 0); -- Controls the address of the ramblock for the random number generator
- FMEMU_RANDOM_RAM : in bitfield_fmemu_random_ram_t_type;
- FMEMU_RANDOM_CONTROL : in bitfield_fmemu_random_control_w_type--;
- --SS (SWAP LSB MSB)
- --fhCR_REVERSE_10B : in std_logic
-);
-end entity elink_data_emulator;
-
-architecture Behavioral of elink_data_emulator is
-
- signal elinkdata_o : std_logic_vector(17 downto 0); -- 18 bit input to the elinkinterface
- signal elinkdata_rdy_o : std_logic;
-
- signal elink_tx_rst : std_logic;
- signal fifo_flush : std_logic;
- signal efifoPfull : std_logic;
-
- signal efifoDoutRdy, efifoFull, efifoEmpty : std_logic := '0';
- signal EDATA_OUT : std_logic_vector(9 downto 0) := (others => '0');
- signal efifoDout_8b10b: std_logic_vector(9 downto 0) := (others => '0');
- signal enc10bit : std_logic_vector (9 downto 0);
- signal enc10bitRdy : std_logic;
-
- --Frans 1
- signal chunk_length : std_logic_vector(11 downto 0);
-
- --Frans 2
- signal chunk_length_trig: std_logic;
- signal random_chunk_length : std_logic_vector(15 downto 0);
-
-
- --MT checker
- signal rst_chk : std_logic:= '0';
- signal datacode_chk : std_logic_vector(1 downto 0) := (others => '0');
- signal data_chk : std_logic_vector(15 downto 0) := (others => '0');
- signal valid_chk : std_logic := '0';
- signal count_chk : std_logic_vector(10 downto 0) := (others => '0');
- type STCHK is (st_idl, st_start, st_count) ;
- signal state_chk : STCHK := st_idl;
- signal err_chk : std_logic := '0';
-
- --upstreamEpathFifoWrap
- signal count_fifochk : std_logic_vector(15 downto 0) := (others => '0');
-
- --MT checker upstream fifo
- signal data_upstfifochk : std_logic_vector(9 downto 0) := (others => '0');
- signal valid_upstfifochk : std_logic := '0';
- signal count_upstfifochk : std_logic_vector(10 downto 0) := (others => '0');
- signal state_upstfifochk : STCHK := st_idl;
- signal err_upstfifochk : std_logic := '0';
-
- --MT checker2
- signal rst_chk2 : std_logic:= '0';
- signal data_chk2 : std_logic_vector(9 downto 0) := (others => '0');
- signal count_chk2 : std_logic_vector(10 downto 0) := (others => '0');
- signal state_chk2 : STCHK := st_idl;
- signal err_chk2 : std_logic := '0';
- signal isEOP_chk2 : std_logic := '0';
- signal valid_chk2 : std_logic := '0';
-
-begin
-
- data_gen : entity work.elink_packet_generator
- generic map (
- epath => epath,
- egroup => egroup
- )
- port map (
- clk_i => clk240,
- rst_i => emu_control.reset,
- ewidth => emu_control.output_width,
- pattern_sel_i => emu_control.pattern_select,
- userdata_i => emu_control.userdata,
- chunk_length_i => chunk_length, --Frans 1 emu_control.chunk_length(11 downto 0), -- length of packet in bytes, 12bits = 4kBytes
- sw_busy_i => emu_control.sw_busy,
- elinkdata_o => elinkdata_o, -- 18bit = 2bit datacode & 16bit data
- l1trigger_i => l1a_trig, -- L1 trigger
- l1a_id => l1a_id,
- elinkdata_rdy_o => elinkdata_rdy_o,
- --Frans 2
- chunk_length_trig_o => chunk_length_trig
- );
-
---Frans 1
-
- --chunkLengthSel: process(register_map_control_40xtal, emu_control) --, random_chunk_length)
- --begin
- -- if register_map_control_40xtal.FMEMU_RANDOM_CONTROL.SELECT_RANDOM = "0" then
- -- chunk_length <= emu_control.chunk_length(11 downto 0);
- -- else
- -- chunk_length <= X"01A"; --random_chunk_length(11 downto 0);
- -- end if;
- --end process;
---
--- chunk_length <= emu_control.chunk_length(11 downto 0) when (SELECT_RANDOM = "0") else
--- X"01A";
-
- chunk_length_out <= chunk_length;
-
---Frans 2
- chunk_length <= emu_control.chunk_length(11 downto 0) when (SELECT_RANDOM = "0") else
- random_chunk_length(11 downto 0);
-
-
- random_gen0: entity work.Random_gen
- generic map(
- LANE_ID => LANE_ID
- )
- port map(
- rst => elink_tx_rst,--: in std_logic;
- clk40 => clk40,--: in std_logic;
- clk240 => clk240,--: in std_logic;
--- register_map_control => register_map_control_40xtal,--: in register_map_control_type;
- rg_rst => elink_tx_rst,--: in std_logic;
- rg_enb => chunk_length_trig,--: in std_logic;
- rg_doutb => random_chunk_length, --: out std_logic_vector(15 downto 0)
- --MT 2 (Fran 2)
- FMEMU_RANDOM_RAM_ADDR => FMEMU_RANDOM_RAM_ADDR ,
- FMEMU_RANDOM_RAM => FMEMU_RANDOM_RAM ,
- FMEMU_RANDOM_CONTROL => FMEMU_RANDOM_CONTROL
- );
---
-
-
- --MT checker
---datacode: elinkdata_o(17 downto 16)
---data: elinkdata_o(15 downto 0)
---valid elinkdata_rdy_o
- rst_chk <= emu_control.reset;
- datacode_chk <= elinkdata_o(17 downto 16);
- data_chk <= elinkdata_o(15 downto 0);
- valid_chk <= elinkdata_rdy_o;
- checker: process (clk240, rst_chk)
- begin
- if rst_chk = '1' then
- state_chk <= st_idl;
- count_chk <= (others => '0');
- err_chk <= '0';
- elsif clk240'event and clk240='1' then
- if valid_chk = '1' then
- sm_checker: case state_chk is
- when st_idl =>
- count_chk <= (others => '0');
- err_chk <= '0';
--- if data_chk = X"AA00" and datacode_chk = "10" then
- if datacode_chk = "10" then
- state_chk <= st_start;
- end if;
- when st_start =>
--- if data_chk = X"0000" and datacode_chk = "01" then
- if datacode_chk = "01" then
- state_chk <= st_idl;
- count_chk <= (others => '0');
- else
- state_chk <= st_count;
- count_chk <= count_chk + 1;
- end if;
- when st_count =>
- if datacode_chk = "01" then
- state_chk <= st_idl;
- count_chk <= (others => '0');
- elsif datacode_chk = "00" then
- state_chk <= st_count;
- count_chk <= count_chk + 1;
- else
- state_chk <= st_idl;
- err_chk <= '1';
- count_chk <= (others => '0');
- end if;
- end case sm_checker;
- end if;
- end if;
- end process;
-
- ------------------------------------------------------------
- -- EPATH_FIFO
- ------------------------------------------------------------
- UEF_IN : entity work.upstreamEpathFifoWrap
- port map(
- bitCLK => '0',
- rst => elink_tx_rst,
- fifoFLUSH => fifo_flush,
- clk => clk240,
- ---
- wr_en => elinkdata_rdy_o,
- din => elinkdata_o,
- ---
- rd_en => elink_data_re,
- dout => EDATA_OUT,
- doutRdy => efifoDoutRdy,
- ---
- full => efifoFull,
- empty => efifoEmpty,
- prog_full => efifoPfull
- );
-
-
- --MT count data in the fifo
- fifochk: process (clk240, elink_tx_rst, fifo_flush)
- begin
- if elink_tx_rst = '1' or fifo_flush = '1' then
- count_fifochk <= (others => '0');
- elsif clk240'event and clk240='1' then
- if elinkdata_rdy_o = '1' and elink_data_re = '1' then
- count_fifochk <= count_fifochk; --+1 -1
- elsif elinkdata_rdy_o = '1' and elink_data_re = '0' then
- count_fifochk <= count_fifochk + 1; --+1
- elsif elinkdata_rdy_o = '0' and elink_data_re = '1' and count_fifochk /= X"0000" then
- count_fifochk <= count_fifochk - 1; ---1
- else
- count_fifochk <= count_fifochk; --0
- end if;
- end if;
- end process;
- --
-
- --MT
- --MT checker upstream fifo
- data_upstfifochk <= EDATA_OUT;
- valid_upstfifochk <= efifoDoutRdy;
- checker_upstfifo: process (clk240, elink_tx_rst, fifo_flush)
- begin
- if elink_tx_rst = '1' or fifo_flush = '1' then
- count_upstfifochk <= (others => '0');
- err_upstfifochk <= '0';
- elsif clk240'event and clk240='1' then
- if valid_upstfifochk = '1' then
- fifo_checker: case state_upstfifochk is
- when st_idl =>
- count_upstfifochk <= (others => '0');
- err_upstfifochk <= '0';
- if data_upstfifochk(9 downto 8) = "10" then
- state_upstfifochk <= st_start;
- end if;
- when st_start =>
- if data_upstfifochk(9 downto 8) = "01" then
- state_upstfifochk <= st_idl;
- count_upstfifochk <= (others => '0');
- else
- state_upstfifochk <= st_count;
- count_upstfifochk <= count_upstfifochk + 1;
- end if;
- when st_count =>
- if data_upstfifochk(9 downto 8) = "01" then
- state_upstfifochk <= st_idl;
- count_upstfifochk <= (others => '0');
- elsif data_upstfifochk(9 downto 8) = "00" then
- state_upstfifochk <= st_count;
- count_upstfifochk <= count_upstfifochk + 1;
- else
- state_upstfifochk <= st_idl;
- err_upstfifochk <= '1';
- count_upstfifochk <= (others => '0');
- end if;
- end case fifo_checker;
- end if;
- end if;
- end process;
-
- elink_data_out <= efifoDout_8b10b when (emu_control.data_format = '1') else EDATA_OUT;
-
- enc8b10bx : entity work.enc8b10_wrap
- port map (
- clk => clk240,
- rst => elink_tx_rst,
- dataCode => EDATA_OUT(9 downto 8), -- 00"data, 01"eop, 10"sop, 11"comma
- dataIN => EDATA_OUT(7 downto 0),
- dataINrdy => efifoDoutRdy,
--- Xoff_Set_Rdy => '0',
--- Xoff_Clear_Rdy => '0',
- encDataOut => enc10bit,
- encDataOutrdy => enc10bitRdy
- );
-
--- efifoDout_8b10b <= enc10bit(9) & enc10bit(8) & enc10bit(7) & enc10bit(6) & enc10bit(5) & enc10bit(4) & enc10bit(3) & enc10bit(2) & enc10bit(1) & enc10bit(0);
--- efifoDout_8b10b <= enc10bit(0) & enc10bit(1) & enc10bit(2) & enc10bit(3) & enc10bit(4) & enc10bit(5) & enc10bit(6) & enc10bit(7) & enc10bit(8) & enc10bit(9);
-
--- Swap MSB LSB added SS
- efifoDout_8b10b <= enc10bit(0) & enc10bit(1) & enc10bit(2) & enc10bit(3) & enc10bit(4) & enc10bit(5) & enc10bit(6) & enc10bit(7) & enc10bit(8) & enc10bit(9);
- --when (fhCR_REVERSE_10B = '0') -- LSB First when '0' controlled by register CR_REVERSE_10B.FROMHOST --SS
- --else -- MSB First when '1'
- --enc10bit(9) & enc10bit(8) & enc10bit(7) & enc10bit(6) & enc10bit(5) & enc10bit(4) & enc10bit(3) & enc10bit(2) & enc10bit(1) & enc10bit(0);
-
- --MT checker 2
- --SOP/EOP=K28.1/K28.6=3c/dc (centralrouter_package) are encoded as in https://en.wikipedia.org/wiki/8b/10b_encoding
- --SOP/EOP after the encoding can assume two numbers, depending on
- --current parity (estimated from previous packet)
- rst_chk2 <= emu_control.reset;
- data_chk2 <= efifoDout_8b10b;
- valid_chk2 <= enc10bitRdy;
- --isEOP_chk2 <= '0';
- --! FS: From centralRouter_package.vhd: let's use thes instead of X"0F9" etc. X"0F9" represents a 12-bit number,
- --! FS: officcially the comparisons should always be false. Vivado seems to swallow it though
- --! FS: constant EOCp : std_logic_vector (9 downto 0) := "0011110110"; -- -K.28.6
- --! FS: constant EOCn : std_logic_vector (9 downto 0) := "1100001001"; -- +K.28.6
- --! FS: constant SOCp : std_logic_vector (9 downto 0) := "0011111001"; -- -K.28.1
- --! FS: constant SOCn : std_logic_vector (9 downto 0) := "1100000110"; -- +K.28.1
- checker2: process (clk240, rst_chk2)
- begin
- if rst_chk2 = '1' then
- state_chk2 <= st_idl;
- count_chk2 <= (others => '0');
- err_chk2 <= '0';
- elsif clk240'event and clk240='1' then
- if valid_chk2 = '1' then
- sm_checker2: case state_chk2 is
- when st_idl =>
- count_chk2 <= (others => '0');
- err_chk2 <= '0';
- isEOP_chk2 <= '0';
- if data_chk2 = SOCn or data_chk2 = SOCp then --SOP
- state_chk2 <= st_start;
- end if;
- when st_start =>
- if data_chk2 = EOCp or data_chk2 = EOCn then --EOP
- state_chk2 <= st_idl;
- count_chk2 <= (others => '0');
- isEOP_chk2 <= '1';
- else
- state_chk2 <= st_count;
- count_chk2 <= count_chk2 + 1;
- isEOP_chk2 <= '0';
- end if;
- when st_count =>
- if data_chk2 = EOCp or data_chk2 = EOCn then --EOP
- state_chk2 <= st_idl;
- count_chk2 <= (others => '0');
- isEOP_chk2 <= '1';
- else
- state_chk2 <= st_count;
- count_chk2 <= count_chk2 + 1;
- isEOP_chk2 <= '0';
- --else
- -- state_chk2 <= st_idl;
- -- err_chk2 <= '1';
- -- count_chk2 <= (others => '0');
- -- isEOP_chk2 <= '0';
- end if;
- end case sm_checker2;
- end if;
- end if;
- end process;
-
- flag_data_gen <= isEOP_chk2; --RL
-
- rst0: entity work.CRresetManager
- port map (
- clk40 => clk240,
- rst => emu_control.reset,
- cr_rst => elink_tx_rst,
- cr_fifo_flush => fifo_flush
- );
-
-end Behavioral;
-
+--==============================================================================
+--
+-- Argonne National Laboratory
+-- High Energy Physics
+-- Electronics Group
+--
+-- Engineer: John Anderson, Soo Ryu
+-- Modified By: Michael Oberling
+--
+-- Design Name: elink_data_emulator_lightweight
+-- Version: 1.0
+-- Date: 9/13/2017
+--
+-- Description: Coming soon.
+--
+-- Change Log: V1.0 -
+--
+--==============================================================================
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--MT
+use IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+--
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+use work.type_lib.ALL;
+
+use work.centralRouter_package.all;
+
+--Frans 1
+use work.pcie_package.all;
+entity elink_data_emulator is
+generic (
+ epath : std_logic_vector (4 downto 0);
+ egroup : std_logic_vector (2 downto 0);
+ --Frans 2
+ LANE_ID : integer := 0
+
+);
+port (
+ clk40 : in STD_LOGIC;
+ clk240 : in STD_LOGIC;
+ emu_control : in lane_emulator_control;
+ elink_data_out : out STD_LOGIC_VECTOR (9 downto 0);
+ elink_data_re : in std_logic;
+ l1a_trig : in STD_LOGIC;
+ l1a_id : in STD_LOGIC_VECTOR (15 downto 0);
+ flag_data_gen : out std_logic; --RL added to be used to sync the read enables
+ SELECT_RANDOM : in std_logic_vector(0 downto 0);
+ chunk_length_out : out std_logic_vector(11 downto 0) ;
+ --MT 2 (Fran 2)
+ FMEMU_RANDOM_RAM_ADDR : in std_logic_vector(9 downto 0); -- Controls the address of the ramblock for the random number generator
+ FMEMU_RANDOM_RAM : in bitfield_fmemu_random_ram_t_type;
+ FMEMU_RANDOM_CONTROL : in bitfield_fmemu_random_control_w_type--;
+ --SS (SWAP LSB MSB)
+ --fhCR_REVERSE_10B : in std_logic
+);
+end entity elink_data_emulator;
+
+architecture Behavioral of elink_data_emulator is
+
+ signal elinkdata_o : std_logic_vector(17 downto 0); -- 18 bit input to the elinkinterface
+ signal elinkdata_rdy_o : std_logic;
+
+ signal elink_tx_rst : std_logic;
+ signal fifo_flush : std_logic;
+ signal efifoPfull : std_logic;
+
+ signal efifoDoutRdy, efifoFull, efifoEmpty : std_logic := '0';
+ signal EDATA_OUT : std_logic_vector(9 downto 0) := (others => '0');
+ signal efifoDout_8b10b: std_logic_vector(9 downto 0) := (others => '0');
+ signal enc10bit : std_logic_vector (9 downto 0);
+ signal enc10bitRdy : std_logic;
+
+ --Frans 1
+ signal chunk_length : std_logic_vector(11 downto 0);
+
+ --Frans 2
+ signal chunk_length_trig: std_logic;
+ signal random_chunk_length : std_logic_vector(15 downto 0);
+
+
+ --MT checker
+ signal rst_chk : std_logic:= '0';
+ signal datacode_chk : std_logic_vector(1 downto 0) := (others => '0');
+ signal data_chk : std_logic_vector(15 downto 0) := (others => '0');
+ signal valid_chk : std_logic := '0';
+ signal count_chk : std_logic_vector(10 downto 0) := (others => '0');
+ type STCHK is (st_idl, st_start, st_count) ;
+ signal state_chk : STCHK := st_idl;
+ signal err_chk : std_logic := '0';
+
+ --upstreamEpathFifoWrap
+ signal count_fifochk : std_logic_vector(15 downto 0) := (others => '0');
+
+ --MT checker upstream fifo
+ signal data_upstfifochk : std_logic_vector(9 downto 0) := (others => '0');
+ signal valid_upstfifochk : std_logic := '0';
+ signal count_upstfifochk : std_logic_vector(10 downto 0) := (others => '0');
+ signal state_upstfifochk : STCHK := st_idl;
+ signal err_upstfifochk : std_logic := '0';
+
+ --MT checker2
+ signal rst_chk2 : std_logic:= '0';
+ signal data_chk2 : std_logic_vector(9 downto 0) := (others => '0');
+ signal count_chk2 : std_logic_vector(10 downto 0) := (others => '0');
+ signal state_chk2 : STCHK := st_idl;
+ signal err_chk2 : std_logic := '0';
+ signal isEOP_chk2 : std_logic := '0';
+ signal valid_chk2 : std_logic := '0';
+
+begin
+
+ data_gen : entity work.elink_packet_generator
+ generic map (
+ epath => epath,
+ egroup => egroup
+ )
+ port map (
+ clk_i => clk240,
+ rst_i => emu_control.reset,
+ ewidth => emu_control.output_width,
+ pattern_sel_i => emu_control.pattern_select,
+ userdata_i => emu_control.userdata,
+ chunk_length_i => chunk_length, --Frans 1 emu_control.chunk_length(11 downto 0), -- length of packet in bytes, 12bits = 4kBytes
+ sw_busy_i => emu_control.sw_busy,
+ elinkdata_o => elinkdata_o, -- 18bit = 2bit datacode & 16bit data
+ l1trigger_i => l1a_trig, -- L1 trigger
+ l1a_id => l1a_id,
+ elinkdata_rdy_o => elinkdata_rdy_o,
+ --Frans 2
+ chunk_length_trig_o => chunk_length_trig
+ );
+
+--Frans 1
+
+ --chunkLengthSel: process(register_map_control_40xtal, emu_control) --, random_chunk_length)
+ --begin
+ -- if register_map_control_40xtal.FMEMU_RANDOM_CONTROL.SELECT_RANDOM = "0" then
+ -- chunk_length <= emu_control.chunk_length(11 downto 0);
+ -- else
+ -- chunk_length <= X"01A"; --random_chunk_length(11 downto 0);
+ -- end if;
+ --end process;
+--
+-- chunk_length <= emu_control.chunk_length(11 downto 0) when (SELECT_RANDOM = "0") else
+-- X"01A";
+
+ chunk_length_out <= chunk_length;
+
+--Frans 2
+ chunk_length <= emu_control.chunk_length(11 downto 0) when (SELECT_RANDOM = "0") else
+ random_chunk_length(11 downto 0);
+
+
+ random_gen0: entity work.Random_gen
+ generic map(
+ LANE_ID => LANE_ID
+ )
+ port map(
+ rst => elink_tx_rst,--: in std_logic;
+ clk40 => clk40,--: in std_logic;
+ clk240 => clk240,--: in std_logic;
+-- register_map_control => register_map_control_40xtal,--: in register_map_control_type;
+ rg_rst => elink_tx_rst,--: in std_logic;
+ rg_enb => chunk_length_trig,--: in std_logic;
+ rg_doutb => random_chunk_length, --: out std_logic_vector(15 downto 0)
+ --MT 2 (Fran 2)
+ FMEMU_RANDOM_RAM_ADDR => FMEMU_RANDOM_RAM_ADDR ,
+ FMEMU_RANDOM_RAM => FMEMU_RANDOM_RAM ,
+ FMEMU_RANDOM_CONTROL => FMEMU_RANDOM_CONTROL
+ );
+--
+
+
+ --MT checker
+--datacode: elinkdata_o(17 downto 16)
+--data: elinkdata_o(15 downto 0)
+--valid elinkdata_rdy_o
+ rst_chk <= emu_control.reset;
+ datacode_chk <= elinkdata_o(17 downto 16);
+ data_chk <= elinkdata_o(15 downto 0);
+ valid_chk <= elinkdata_rdy_o;
+ checker: process (clk240, rst_chk)
+ begin
+ if rst_chk = '1' then
+ state_chk <= st_idl;
+ count_chk <= (others => '0');
+ err_chk <= '0';
+ elsif clk240'event and clk240='1' then
+ if valid_chk = '1' then
+ sm_checker: case state_chk is
+ when st_idl =>
+ count_chk <= (others => '0');
+ err_chk <= '0';
+-- if data_chk = X"AA00" and datacode_chk = "10" then
+ if datacode_chk = "10" then
+ state_chk <= st_start;
+ end if;
+ when st_start =>
+-- if data_chk = X"0000" and datacode_chk = "01" then
+ if datacode_chk = "01" then
+ state_chk <= st_idl;
+ count_chk <= (others => '0');
+ else
+ state_chk <= st_count;
+ count_chk <= count_chk + 1;
+ end if;
+ when st_count =>
+ if datacode_chk = "01" then
+ state_chk <= st_idl;
+ count_chk <= (others => '0');
+ elsif datacode_chk = "00" then
+ state_chk <= st_count;
+ count_chk <= count_chk + 1;
+ else
+ state_chk <= st_idl;
+ err_chk <= '1';
+ count_chk <= (others => '0');
+ end if;
+ end case sm_checker;
+ end if;
+ end if;
+ end process;
+
+ ------------------------------------------------------------
+ -- EPATH_FIFO
+ ------------------------------------------------------------
+ UEF_IN : entity work.upstreamEpathFifoWrap
+ port map(
+ bitCLK => '0',
+ rst => elink_tx_rst,
+ fifoFLUSH => fifo_flush,
+ clk => clk240,
+ ---
+ wr_en => elinkdata_rdy_o,
+ din => elinkdata_o,
+ ---
+ rd_en => elink_data_re,
+ dout => EDATA_OUT,
+ doutRdy => efifoDoutRdy,
+ ---
+ full => efifoFull,
+ empty => efifoEmpty,
+ prog_full => efifoPfull
+ );
+
+
+ --MT count data in the fifo
+ fifochk: process (clk240, elink_tx_rst, fifo_flush)
+ begin
+ if elink_tx_rst = '1' or fifo_flush = '1' then
+ count_fifochk <= (others => '0');
+ elsif clk240'event and clk240='1' then
+ if elinkdata_rdy_o = '1' and elink_data_re = '1' then
+ count_fifochk <= count_fifochk; --+1 -1
+ elsif elinkdata_rdy_o = '1' and elink_data_re = '0' then
+ count_fifochk <= count_fifochk + 1; --+1
+ elsif elinkdata_rdy_o = '0' and elink_data_re = '1' and count_fifochk /= X"0000" then
+ count_fifochk <= count_fifochk - 1; ---1
+ else
+ count_fifochk <= count_fifochk; --0
+ end if;
+ end if;
+ end process;
+ --
+
+ --MT
+ --MT checker upstream fifo
+ data_upstfifochk <= EDATA_OUT;
+ valid_upstfifochk <= efifoDoutRdy;
+ checker_upstfifo: process (clk240, elink_tx_rst, fifo_flush)
+ begin
+ if elink_tx_rst = '1' or fifo_flush = '1' then
+ count_upstfifochk <= (others => '0');
+ err_upstfifochk <= '0';
+ elsif clk240'event and clk240='1' then
+ if valid_upstfifochk = '1' then
+ fifo_checker: case state_upstfifochk is
+ when st_idl =>
+ count_upstfifochk <= (others => '0');
+ err_upstfifochk <= '0';
+ if data_upstfifochk(9 downto 8) = "10" then
+ state_upstfifochk <= st_start;
+ end if;
+ when st_start =>
+ if data_upstfifochk(9 downto 8) = "01" then
+ state_upstfifochk <= st_idl;
+ count_upstfifochk <= (others => '0');
+ else
+ state_upstfifochk <= st_count;
+ count_upstfifochk <= count_upstfifochk + 1;
+ end if;
+ when st_count =>
+ if data_upstfifochk(9 downto 8) = "01" then
+ state_upstfifochk <= st_idl;
+ count_upstfifochk <= (others => '0');
+ elsif data_upstfifochk(9 downto 8) = "00" then
+ state_upstfifochk <= st_count;
+ count_upstfifochk <= count_upstfifochk + 1;
+ else
+ state_upstfifochk <= st_idl;
+ err_upstfifochk <= '1';
+ count_upstfifochk <= (others => '0');
+ end if;
+ end case fifo_checker;
+ end if;
+ end if;
+ end process;
+
+ elink_data_out <= efifoDout_8b10b when (emu_control.data_format = '1') else EDATA_OUT;
+
+ enc8b10bx : entity work.enc8b10_wrap
+ port map (
+ clk => clk240,
+ rst => elink_tx_rst,
+ dataCode => EDATA_OUT(9 downto 8), -- 00"data, 01"eop, 10"sop, 11"comma
+ dataIN => EDATA_OUT(7 downto 0),
+ dataINrdy => efifoDoutRdy,
+-- Xoff_Set_Rdy => '0',
+-- Xoff_Clear_Rdy => '0',
+ encDataOut => enc10bit,
+ encDataOutrdy => enc10bitRdy
+ );
+
+-- efifoDout_8b10b <= enc10bit(9) & enc10bit(8) & enc10bit(7) & enc10bit(6) & enc10bit(5) & enc10bit(4) & enc10bit(3) & enc10bit(2) & enc10bit(1) & enc10bit(0);
+-- efifoDout_8b10b <= enc10bit(0) & enc10bit(1) & enc10bit(2) & enc10bit(3) & enc10bit(4) & enc10bit(5) & enc10bit(6) & enc10bit(7) & enc10bit(8) & enc10bit(9);
+
+-- Swap MSB LSB added SS
+ efifoDout_8b10b <= enc10bit(0) & enc10bit(1) & enc10bit(2) & enc10bit(3) & enc10bit(4) & enc10bit(5) & enc10bit(6) & enc10bit(7) & enc10bit(8) & enc10bit(9);
+ --when (fhCR_REVERSE_10B = '0') -- LSB First when '0' controlled by register CR_REVERSE_10B.FROMHOST --SS
+ --else -- MSB First when '1'
+ --enc10bit(9) & enc10bit(8) & enc10bit(7) & enc10bit(6) & enc10bit(5) & enc10bit(4) & enc10bit(3) & enc10bit(2) & enc10bit(1) & enc10bit(0);
+
+ --MT checker 2
+ --SOP/EOP=K28.1/K28.6=3c/dc (centralrouter_package) are encoded as in https://en.wikipedia.org/wiki/8b/10b_encoding
+ --SOP/EOP after the encoding can assume two numbers, depending on
+ --current parity (estimated from previous packet)
+ rst_chk2 <= emu_control.reset;
+ data_chk2 <= efifoDout_8b10b;
+ valid_chk2 <= enc10bitRdy;
+ --isEOP_chk2 <= '0';
+ --! FS: From centralRouter_package.vhd: let's use thes instead of X"0F9" etc. X"0F9" represents a 12-bit number,
+ --! FS: officcially the comparisons should always be false. Vivado seems to swallow it though
+ --! FS: constant EOCp : std_logic_vector (9 downto 0) := "0011110110"; -- -K.28.6
+ --! FS: constant EOCn : std_logic_vector (9 downto 0) := "1100001001"; -- +K.28.6
+ --! FS: constant SOCp : std_logic_vector (9 downto 0) := "0011111001"; -- -K.28.1
+ --! FS: constant SOCn : std_logic_vector (9 downto 0) := "1100000110"; -- +K.28.1
+ checker2: process (clk240, rst_chk2)
+ begin
+ if rst_chk2 = '1' then
+ state_chk2 <= st_idl;
+ count_chk2 <= (others => '0');
+ err_chk2 <= '0';
+ elsif clk240'event and clk240='1' then
+ if valid_chk2 = '1' then
+ sm_checker2: case state_chk2 is
+ when st_idl =>
+ count_chk2 <= (others => '0');
+ err_chk2 <= '0';
+ isEOP_chk2 <= '0';
+ if data_chk2 = SOCn or data_chk2 = SOCp then --SOP
+ state_chk2 <= st_start;
+ end if;
+ when st_start =>
+ if data_chk2 = EOCp or data_chk2 = EOCn then --EOP
+ state_chk2 <= st_idl;
+ count_chk2 <= (others => '0');
+ isEOP_chk2 <= '1';
+ else
+ state_chk2 <= st_count;
+ count_chk2 <= count_chk2 + 1;
+ isEOP_chk2 <= '0';
+ end if;
+ when st_count =>
+ if data_chk2 = EOCp or data_chk2 = EOCn then --EOP
+ state_chk2 <= st_idl;
+ count_chk2 <= (others => '0');
+ isEOP_chk2 <= '1';
+ else
+ state_chk2 <= st_count;
+ count_chk2 <= count_chk2 + 1;
+ isEOP_chk2 <= '0';
+ --else
+ -- state_chk2 <= st_idl;
+ -- err_chk2 <= '1';
+ -- count_chk2 <= (others => '0');
+ -- isEOP_chk2 <= '0';
+ end if;
+ end case sm_checker2;
+ end if;
+ end if;
+ end process;
+
+ flag_data_gen <= isEOP_chk2; --RL
+
+ rst0: entity work.CRresetManager
+ port map (
+ clk40 => clk40,
+ clk80 => '0',
+ clk160 => '0',
+ clk240 => clk240,
+ rst => emu_control.reset,
+ cr_rst_40 => open,
+ cr_rst_80 => open,
+ cr_rst_160 => open,
+ cr_rst_240 => elink_tx_rst,
+ cr_fifo_flush_40 => open,
+ cr_fifo_flush_80 => open,
+ cr_fifo_flush_160 => open,
+ cr_fifo_flush_240 => fifo_flush
+ );
+
+end Behavioral;
+
diff --git a/sources/ip_cores/kintexUltrascale/Distr_LUT.xci b/sources/ip_cores/kintexUltrascale/Distr_LUT.xci
index 17f54872c947fb4743fb51a2cfa7723dd7277bbe..7efe54e3411815cb564986336bd5a4777570a043 100644
--- a/sources/ip_cores/kintexUltrascale/Distr_LUT.xci
+++ b/sources/ip_cores/kintexUltrascale/Distr_LUT.xci
@@ -113,7 +113,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP : 2.810143 mW</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP : 3.107037 mW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintexu</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
@@ -148,7 +148,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
@@ -160,7 +160,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">1024</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">NO_CHANGE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">READ_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">16</spirit:configurableElementValue>
@@ -173,8 +173,8 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">gaus_m30_s9.coe</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">gausjv.coe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">Distr_LUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
@@ -193,7 +193,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Simple_Dual_Port_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">NO_CHANGE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">READ_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">WRITE_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
@@ -297,6 +297,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Collision_Warnings" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
@@ -304,6 +305,7 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Write_Rate" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>