diff --git a/.gitignore b/.gitignore
index c06aa8e5216ea042be44e7bab0fc42ddc5736f9d..b8631ee5e8a1bf40facae30e3366ae7e56e3875e 100644
--- a/.gitignore
+++ b/.gitignore
@@ -41,3 +41,6 @@ simulation/UVVMtests/_Alert.txt
simulation/UVVMtests/_Log.txt
simulation/UVVMtests/vsim.wlf
simulation/samples/
+
+# python venv
+scripts/helper/.venv
diff --git a/.gitmodules b/.gitmodules
index c8ed106d77618189204caca01d235d24e56db5ba..69e03336c99fadc3386fdba2718561de78d60ad6 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -24,3 +24,6 @@
[submodule "simulation/VUnit/xpm_vhdl"]
path = simulation/VUnit/xpm_vhdl
url = https://github.com/fransschreuder/xpm_vhdl.git
+[submodule "sources/templates/yaml/regmap"]
+ path = sources/templates/yaml/regmap
+ url = ../regmap.git
diff --git a/scripts/FELIX_top/FELIX_import_sigasi.tcl b/scripts/FELIX_top/FELIX_import_sigasi.tcl
index 728a594383a3211590e672f7a21273d7cfa3fbb8..575b05164f6936a1d38a192f0188f84d51380c52 100755
--- a/scripts/FELIX_top/FELIX_import_sigasi.tcl
+++ b/scripts/FELIX_top/FELIX_import_sigasi.tcl
@@ -53,8 +53,10 @@ source ../filesets/64b66b_fileset.tcl
source ../filesets/core1990_interlaken_fileset.tcl
source ../filesets/itk_strips_fileset.tcl
source ../filesets/bcm_fileset.tcl
-#source ../filesets/fmemu_fileset.tcl
-#source ../filesets/fmemu_top_fileset.tcl
+source ../filesets/fmemu_fileset.tcl
+source ../filesets/fmemu_top_fileset.tcl
+source ../filesets/felig_fileset.tcl
+source ../filesets/lpgbt_fe_core_fileset.tcl
#Actually execute all the filesets
source ../helper/sigasi_import_generic.tcl
diff --git a/scripts/filesets/felig_fileset.tcl b/scripts/filesets/felig_fileset.tcl
index 210e3a2994e9e4a4036ce3a6073e9b2dace64c46..e85054bba048a2aacbb96fedd546462fd3179d0e 100644
--- a/scripts/filesets/felig_fileset.tcl
+++ b/scripts/filesets/felig_fileset.tcl
@@ -37,10 +37,10 @@ set VHDL_FILES [concat $VHDL_FILES \
FELIG/packages/type_lib.vhd \
FELIG/templates/LaneRegisterRemapper.vhd \
FELIG/checkers/gbtword_checker.vhd \
- FELIG/felix_modified/ttc/ttc_decoder/ttc_decoder_core.vhd \
- FELIG/felix_modified/ttc/ttc_decoder/ttc_decode_wrapper.vhd \
+ FELIG/felix_modified/ttc/ttc_decoder/ttc_decoder_core_felig.vhd \
+ FELIG/felix_modified/ttc/ttc_decoder/ttc_decode_wrapper_felig.vhd \
FELIG/PRandomDGen/randomd_gen.vhd \
- FELIG/felix_modified/centralRouter/upstreamEpathFifoWrap.vhd \
+ FELIG/felix_modified/centralRouter/upstreamEpathFifoWrap_felig.vhd \
ttc/ttc_decoder/TTC_hamming_decoder_alme.vhd \
FELIG/housekeeping/housekeeping_module_FELIG.vhd \
FELIG/data_generator/elink_printer_v2.vhd \
@@ -114,16 +114,15 @@ set XCI_FILES_KU [concat $XCI_FILES_KU \
Distr_LUT_felig.xci \
fifo_GBT2CR.xci \
fifo_generator_fe.xci \
- rxclkgen.xci \
- ila_0.xci \
- ila_link_frame.xci \
- ila_downlink.xci \
- ila_header.xci \
- ila_lmk_signals.xci \
- ila_signals_to_LMK.xci \
- ila_tx128.xci \
- ila_SM_LMK.xci \
- ]
+ rxclkgen.xci]
+ #ila_link_frame.xci \
+ #ila_downlink.xci \
+ #ila_header.xci \
+ #ila_lmk_signals.xci \
+ #ila_signals_to_LMK.xci \
+ #ila_tx128.xci \
+ #ila_SM_LMK.xci \
+ #]
set XDC_FILES_BNL712 [concat $XDC_FILES_BNL712 \
felix_top_BNL712.xdc \
diff --git a/scripts/filesets/fmemu_fileset.tcl b/scripts/filesets/fmemu_fileset.tcl
index 711d0a7223cdaf63738aa40a6cf35219916d5df0..1377ec1e648cd9bb64fa8e1fb050607f46a95573 100644
--- a/scripts/filesets/fmemu_fileset.tcl
+++ b/scripts/filesets/fmemu_fileset.tcl
@@ -31,9 +31,9 @@ set VHDL_FILES [concat $VHDL_FILES \
CRC32/CRC32_v2.vhd \
CRC20/crc.vhd \
FullModeTransmitter/FMchannelTXctrl_emu.vhd \
- PRandomDGen/randomd_gen.vhd \
- Xoff_decoder/8b10_dec.vhd \
- Xoff_decoder/8b10_dec_wrap.vhd \
+ PRandomDGen/randomd_gen_fmemu.vhd \
+ Xoff_decoder/8b10_dec_fmemu.vhd \
+ Xoff_decoder/8b10_dec_wrap_fmemu.vhd \
Xoff_decoder/InputShifterNb.vhd \
GBT/gbt_code/FELIX_gbt_wrapper_no_gth.vhd \
felixUserSupport/packages/FMTransceiverPackage.vhd \
diff --git a/scripts/filesets/housekeeping_felig_fileset.tcl b/scripts/filesets/housekeeping_felig_fileset.tcl
deleted file mode 100644
index d50313e729f66cf75fea1fcb39c1dd678f9ffd0f..0000000000000000000000000000000000000000
--- a/scripts/filesets/housekeeping_felig_fileset.tcl
+++ /dev/null
@@ -1,67 +0,0 @@
-
-# This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
-# Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
-# Authors:
-# mtrovato
-# Frans Schreuder
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
-set VHDL_FILES [concat $VHDL_FILES \
- shared/card_type_specific_ios.vhd \
- shared/xadc_drp.vhd \
- shared/dna.vhd \
- housekeeping/housekeeping_module.vhd \
- housekeeping/i2c_interface.vhd \
- housekeeping/clock_and_reset.vhd \
- housekeeping/debug_port_module.vhd \
- housekeeping/GenericConstantsToRegs.vhd \
- housekeeping/gc_multichannel_frequency_meter.vhd \
- housekeeping/gc_pulse_synchronizer.vhd \
- housekeeping/gc_pulse_synchronizer2.vhd \
- housekeeping/gc_sync_ffs.vhd \
- i2c_master/i2c.vhd]
-
-set VHDL_FILES_V7 [concat $VHDL_FILES_V7 \
- flash/flash_wrapper_stub.vhd]
-
-set VHDL_FILES_KU [concat $VHDL_FILES_KU \
- i2c_master/I2C_Master_PEX.vhd \
- FELIG/felix_modified/spi/LMK03200_spi.vhd \
- FELIG/felix_modified/spi/LMK03200_wrapper.vhd \
- shared/pex_init.vhd \
- flash/flash_wrapper.vhd \
- flash/flash_ipcore_bnl.vhd]
-
-set XCI_FILES [concat $XCI_FILES \
- I2C_RDFifo.xci \
- I2C_WRFifo.xci \
- clk_wiz_40_0.xci \
- clk_wiz_200_0.xci \
- clk_wiz_156_0.xci \
- clk_wiz_100_0.xci \
- clk_wiz_250.xci]
-
-#Kintex ultrascale only
-set XCI_FILES_KU [concat $XCI_FILES_KU \
- system_management_wiz_0.xci]
-
-set VHDL_FILES_KU [concat $VHDL_FILES_KU \
- ip_cores/kintexUltrascale/xadc_wiz_0_stub.vhdl]
-
-#Virtex 7 only
-set XCI_FILES_V7 [concat $XCI_FILES_V7 \
- xadc_wiz_0.xci]
-
-set VHDL_FILES_V7 [concat $VHDL_FILES_V7 \
- ip_cores/virtex7/system_management_wiz_0_stub.vhdl]
diff --git a/scripts/helper/do_implementation_finish.tcl b/scripts/helper/do_implementation_finish.tcl
index 8d9e69a17edb961f4ef60ca3362316d0f80dd650..bbcb970ea881c45266c31bc3012b6cc762aa606a 100644
--- a/scripts/helper/do_implementation_finish.tcl
+++ b/scripts/helper/do_implementation_finish.tcl
@@ -169,7 +169,13 @@ cd $HDLDIR/output/
set pass [expr {[get_property SLACK [get_timing_paths -delay_type min_max]] >= 0}]
set report [report_timing -slack_lesser_than 0 -return_string -nworst 10]
set check_timing_report [check_timing -return_string]
-report_utilization -name ${FileName} -spreadsheet_table "Hierarchy" -spreadsheet_file ${HDLDIR}/output/${FileName}.xlsx -spreadsheet_depth 8
+# report_utilization -name ${FileName} -spreadsheet_table "Hierarchy" -spreadsheet_file ${HDLDIR}/output/${FileName}.xlsx -spreadsheet_depth 8
+report_utilization -hierarchical -hierarchical_depth 8 -file ${HDLDIR}/output/${FileName}_util.txt
+if {[catch {exec $scriptdir/../helper/generate_util_xlsx_wrapper.sh ${HDLDIR}/output/${FileName}_util.txt}] != 0} {
+ puts "Error generating Excel utilization report. Keeping the text report."
+} else {
+ file delete ${HDLDIR}/output/${FileName}_util.txt
+}
set util [report_utilization -return_string]
set power [report_power -return_string]
set slack [get_property SLACK [get_timing_paths -delay_type min_max]]
diff --git a/scripts/helper/do_implementation_pre.tcl b/scripts/helper/do_implementation_pre.tcl
index 2983476f5382319fdbba1cbc2ba827160cde2bc3..4938b119e2e7fa9f31cec9e0e4685189aa25dd75 100644
--- a/scripts/helper/do_implementation_pre.tcl
+++ b/scripts/helper/do_implementation_pre.tcl
@@ -6,6 +6,7 @@
# Elena Zhivun
# Thei Wijnen
# Frans Schreuder
+# Marius Wensing
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -36,8 +37,6 @@ if { [file exists ../../.git/hooks] == 1 } {
puts "no git hooks directory found, omitting creation of symbolic link"
}
-
-
set FIRMWARE_MODE_GBT 0
set FIRMWARE_MODE_FULL 1
set FIRMWARE_MODE_LTDB 2
diff --git a/scripts/helper/generate_util_xlsx.py b/scripts/helper/generate_util_xlsx.py
new file mode 100644
index 0000000000000000000000000000000000000000..df4a12e581bd5068ea653f51bdf6970f4c40a609
--- /dev/null
+++ b/scripts/helper/generate_util_xlsx.py
@@ -0,0 +1,99 @@
+# This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+# Copyright (C) 2001-2024 CERN for the benefit of the ATLAS collaboration.
+# Authors:
+# Marius Wensing
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import sys
+import xlsxwriter
+import itertools
+import os
+
+def usage():
+ print("usage:")
+ print(" generate_util_xlsx.py <filename>")
+ print()
+ print(" <filename> is the path to the Vivado utilization report")
+ print(" (generated with generate_utilization -hierarchical -hierarchical_depth 8 -file <filename>)")
+
+def main(argv):
+ # check if no argument has been supplied
+ if len(argv) == 0:
+ usage()
+ return 1
+
+ # check for --help/-h
+ if any(arg in argv[0] for arg in ["-h", "-help"]):
+ usage()
+ return 0
+
+ # get the filenames
+ txtfilename = argv[0]
+ xlsxfilename = os.path.splitext(txtfilename)[0] + ".xlsx"
+
+ with open(txtfilename, "r") as f:
+ workbook = xlsxwriter.Workbook(xlsxfilename)
+ worksheet = workbook.add_worksheet("Utilization")
+ worksheet.outline_settings(True, False, False, False)
+
+ # read line by line
+ skip = 2
+ row = 0
+ while True:
+ line = f.readline()
+
+ if not line:
+ break
+
+ # scan for beginning of table
+ if line.startswith('+'):
+ skip = skip - 1
+
+ # skip header lines or lines without pipe (|)
+ if (skip > 1) or not ('|' in line):
+ continue
+
+ fields = line.split('|')[1:-1]
+
+ if skip == 1:
+ bold = workbook.add_format({"bold": 1})
+
+ # we have the header row here
+ for (col, field) in enumerate(fields):
+ worksheet.write(row, col, field.strip(), bold)
+ else:
+ # we have a regular row here
+ # let's try to find out our hierarchy level
+ hier_level = int((sum(1 for _ in itertools.takewhile(str.isspace, fields[0]))-1) / 2)
+ hidden = hier_level > 1
+ for (col, field) in enumerate(fields):
+ indent = workbook.add_format({"indent": hier_level})
+ if col == 0:
+ worksheet.write(row, col, field.strip(), indent)
+ else:
+ worksheet.write(row, col, field.strip())
+
+ #worksheet.set_row(row, None, None, {"level": hier_level, "collapsed": True, "hidden": hidden})
+ worksheet.set_row(row, None, None, {"level": hier_level, "hidden": hidden})
+
+ # next row
+ row = row + 1
+
+ worksheet.autofit()
+ workbook.close()
+
+ return 0
+
+if __name__ == "__main__":
+ sys.exit(main(sys.argv[1:]))
diff --git a/scripts/helper/generate_util_xlsx_wrapper.sh b/scripts/helper/generate_util_xlsx_wrapper.sh
new file mode 100755
index 0000000000000000000000000000000000000000..161d14934f9e8e17b1a25b963228fae2913448d7
--- /dev/null
+++ b/scripts/helper/generate_util_xlsx_wrapper.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+# get script directory
+SCRIPT_DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )"
+
+# use virtual environment
+VENV_DIR=${SCRIPT_DIR}/.venv
+
+# check if virtual environment exists
+if ! [ -d ${VENV_DIR} ]; then
+ python -m venv ${VENV_DIR}
+fi
+
+# activate virtual environment
+source ${VENV_DIR}/bin/activate
+
+# install xlsxwriter
+pip install xlsxwriter
+
+# run the python script
+python ${SCRIPT_DIR}/generate_util_xlsx.py $*
diff --git a/simulation/FELIG/felig_sim_64b66b_decoding.vhd b/simulation/FELIG/felig_sim_64b66b_decoding.vhd
index 96d2bbfd7a281a6adb22dfe5ad4e9ce1f4c521fa..256dcbf622fa50af396a23cda77c30b557ddfd5e 100644
--- a/simulation/FELIG/felig_sim_64b66b_decoding.vhd
+++ b/simulation/FELIG/felig_sim_64b66b_decoding.vhd
@@ -41,13 +41,13 @@ architecture Behavioral of felig_sim_64b66b_decoding is
signal clk40 : std_logic:= '0'; --input
signal reset : std_logic_vector(4 downto 0) := (others => '0'); --input
- signal lpGBT_UPLINK_USER_DATA_FOSEL : txrx224b_type(0 to 0); --input
- signal LinkAligned_FOSEL : std_logic_vector(0 downto 0); --input
- signal DecoderAligned : std_logic_vector(STREAMS_TOHOST-3 downto 0); --out
- signal m_axis : axis_32_array_type(0 to STREAMS_TOHOST-1); --out
- signal m_axis_tready : axis_tready_array_type(0 to STREAMS_TOHOST-1); --input
+ signal lpGBT_UPLINK_USER_DATA_FOSEL : txrx224b_type(0 to 1); --input
+ signal LinkAligned_FOSEL : std_logic_vector(0 to 1); --input
+ signal DecoderAligned : std_logic_vector(2*STREAMS_TOHOST-4-1 downto 0); --out -- @suppress "signal DecoderAligned is never read"
+ signal m_axis : axis_32_2d_array_type(0 to 1, 0 to STREAMS_TOHOST-3); --out
+ signal m_axis_tready : axis_tready_2d_array_type(0 to 1, 0 to STREAMS_TOHOST-3); --input
signal aclk : std_logic:= '0'; --input
- signal m_axis_prog_empty : axis_tready_array_type(0 to STREAMS_TOHOST-1); --out
+ signal m_axis_prog_empty : axis_tready_2d_array_type(0 to 1, 0 to STREAMS_TOHOST-3); --out
signal register_map_control : register_map_control_type; --input
-- signal PCIE_ENDPOINT : integer := 0;
@@ -137,7 +137,7 @@ begin
--clock
clk40 <= clk40_in;
- aclk_tmp_b <= not aclk_tmp_b after 3.125ns;
+ aclk_tmp_b <= not aclk_tmp_b after 3.125 ns;
aclk <= aclk_tmp;
rst_proc: process(clk40)
@@ -254,43 +254,49 @@ begin
BLOCKSIZE => 1024,
SIMU => 1,
STREAMS_TOHOST => STREAMS_TOHOST,
- Link => LINK
+ Link => (LINK, LINK),
+ VERSAL => false
)
port map(
clk40 => clk40,--: in std_logic; --BC clock for DataIn
- reset => '0',--reset(4),--: in std_logic; --Acitve high reset
+ --reset => '0',--reset(4),--: in std_logic; --Acitve high reset
MsbFirst => MSB,--: in std_logic; --Default 1, make 0 to reverse the bit order
- LinkData => lpGBT_UPLINK_USER_DATA_FOSEL(0), --LinkData, --to create 223 downto 0
- LinkAligned => LinkAligned_FOSEL(0), --1 --LinkAligned,
+ LinkData => lpGBT_UPLINK_USER_DATA_FOSEL(0 to 1), --LinkData, --to create 223 downto 0
+ LinkAligned => LinkAligned_FOSEL(0) & LinkAligned_FOSEL(1), --1 --LinkAligned,
DecoderAligned_out => DecoderAligned,
- m_axis => m_axis(0 to STREAMS_TOHOST-3),--: out axis_32_type; --FIFO read port (axi stream)
- m_axis_tready => m_axis_tready(0 to STREAMS_TOHOST-3), --x"FE00000",--: in std_logic; --FIFO read tready (axi stream)
+ m_axis => m_axis,--: out axis_32_type; --FIFO read port (axi stream)
+ m_axis_tready => m_axis_tready, --x"FE00000",--: in std_logic; --FIFO read tready (axi stream)
m_axis_aclk => aclk,--: in std_logic; --FIFO read clock (axi stream)
- m_axis_prog_empty => m_axis_prog_empty(0 to STREAMS_TOHOST-3), --: out std_logic
- register_map_control => register_map_control
+ m_axis_prog_empty => m_axis_prog_empty, --: out std_logic
+ register_map_control => register_map_control,
+ clk160 => aclk,
+ daq_reset => '0',
+ daq_fifo_flush => '0',
+ rx_soft_err_rst => "00"
);
--axis stuff
- m_axis(STREAMS_TOHOST-2).tvalid <= '0';
- m_axis(STREAMS_TOHOST-2).tdata <= (others => '0');
- m_axis(STREAMS_TOHOST-2).tlast <= '0';
- m_axis(STREAMS_TOHOST-2).tkeep <= (others => '0');
- m_axis(STREAMS_TOHOST-2).tuser <= (others => '0');
- m_axis_prog_empty(STREAMS_TOHOST-2) <= '1';
- m_axis(STREAMS_TOHOST-1).tvalid <= '0';
- m_axis(STREAMS_TOHOST-1).tdata <= (others => '0');
- m_axis(STREAMS_TOHOST-1).tlast <= '0';
- m_axis(STREAMS_TOHOST-1).tkeep <= (others => '0');
- m_axis(STREAMS_TOHOST-1).tuser <= (others => '0');
- m_axis_prog_empty(STREAMS_TOHOST-1) <= '1';
-
- s_axis <= m_axis;
- m_axis_tready <= s_axis_tready;
- s_axis_prog_empty <= m_axis_prog_empty;
+ m_axis(0,STREAMS_TOHOST-2).tvalid <= '0';
+ m_axis(0,STREAMS_TOHOST-2).tdata <= (others => '0');
+ m_axis(0,STREAMS_TOHOST-2).tlast <= '0';
+ m_axis(0,STREAMS_TOHOST-2).tkeep <= (others => '0');
+ m_axis(0,STREAMS_TOHOST-2).tuser <= (others => '0');
+ m_axis_prog_empty(0,STREAMS_TOHOST-2) <= '1';
+ m_axis(0,STREAMS_TOHOST-1).tvalid <= '0';
+ m_axis(0,STREAMS_TOHOST-1).tdata <= (others => '0');
+ m_axis(0,STREAMS_TOHOST-1).tlast <= '0';
+ m_axis(0,STREAMS_TOHOST-1).tkeep <= (others => '0');
+ m_axis(0,STREAMS_TOHOST-1).tuser <= (others => '0');
+ m_axis_prog_empty(0,STREAMS_TOHOST-1) <= '1';
+ g_axis_connect: for i in 0 to STREAMS_TOHOST-3 generate
+ s_axis(i) <= m_axis(0,i);
+ m_axis_tready(0,i) <= s_axis_tready(i);
+ s_axis_prog_empty(i) <= m_axis_prog_empty(0,i);
+ end generate;
aresetn <= not reset(4);
chStreamController: entity work.ToHostAxiStreamController
@@ -298,19 +304,22 @@ begin
FMCHid => LINK,
toHostTimeoutBitn => toHostTimeoutBitn,
BLOCKSIZE => 1024, --BLOCKSIZE,
- CHUNK_TRAILER_32B => false,--;CHUNK_TRAILER_32B,
- STREAMS_TOHOST => STREAMS_TOHOST
+ --CHUNK_TRAILER_32B => false,--;CHUNK_TRAILER_32B,
+ STREAMS_TOHOST => STREAMS_TOHOST,
+ ACLK_FREQ => 160
--debug
-- PCIE_ENDPOINT => PCIE_ENDPOINT
)
port map (
aclk => aclk,
- aresetn => aresetn,
+ daq_reset => reset(4),
+ --aresetn => aresetn,
s_axis_in => s_axis,
s_axis_tready_out => s_axis_tready,
s_axis_prog_empty_in => s_axis_prog_empty,
timeOutEna_i => timeCnt_ena,
timeCnt_max => timeCnt_max,
+ instant_timeout_enable => (others => '0'),
prog_full_in => '0', --ch_prog_full, -- in, downstream wm fifo is full or main , can't happen in normal operation
word32out => chFIFO_din32, -- to chFIFO
word32out_valid => chFIFO_din32_valid -- to chFIFO
diff --git a/simulation/ItkStrip/tb_playback_controller.do b/simulation/ItkStrip/tb_playback_controller.do
new file mode 100644
index 0000000000000000000000000000000000000000..bc69a9411d29ba81113f7ef67ec5b384d2e40ead
--- /dev/null
+++ b/simulation/ItkStrip/tb_playback_controller.do
@@ -0,0 +1,71 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/clk
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/rst
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/readout_active_o
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/data_i
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/valid_i
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/ready_o
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/set_write_addr_pulse_i
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/write_addr_start_i
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/read_addr_start_i
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/data_o
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/valid_o
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/wea
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/readout_active_reg
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/ready_i
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/valid_reg
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/ready_reg
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/data_reg
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/state
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/start_pulse_i
+add wave -noupdate -radix unsigned /tb_playback_controller_vunit/uut_tb/DUT/addra
+add wave -noupdate -radix unsigned /tb_playback_controller_vunit/uut_tb/DUT/read_addr_stop_i
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/loop_active
+add wave -noupdate -radix unsigned /tb_playback_controller_vunit/uut_tb/DUT/loop_counter
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/DUT/trickle_loops_i
+add wave -noupdate -divider {New Divider}
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/uvvm_completed
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/trickle_loops
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/clk
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/rst
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/start_pulse_i
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/readout_active_o
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/set_write_addr_pulse_i
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/write_addr_start_i
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/read_addr_start_i
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/read_addr_stop_i
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/data_o
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/valid_o
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/ready_i
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/data_in
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/verify_data_en
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/verify_data_done
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/verify_data_ack
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/valid_word_count
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/valid_word_count_rst
+add wave -noupdate -divider {New Divider}
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/data_checker/data_expected_count
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/data_checker/loops_hack
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/data_checker/read_delay_clk_cycles
+add wave -noupdate -radix unsigned /tb_playback_controller_vunit/uut_tb/data_checker/i
+add wave -noupdate /tb_playback_controller_vunit/uut_tb/data_checker/loopy
+add wave -noupdate -divider {New Divider}
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1163323 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 210
+configure wave -valuecolwidth 181
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {1220625 ps}
diff --git a/simulation/ItkStrip/tb_playback_controller.vhd b/simulation/ItkStrip/tb_playback_controller.vhd
index 92a64ea613189aca285e6e6754703e1071a0d244..74b8e670db5a46201e1ce76c6dcd9abb65c4cda6 100644
--- a/simulation/ItkStrip/tb_playback_controller.vhd
+++ b/simulation/ItkStrip/tb_playback_controller.vhd
@@ -36,20 +36,20 @@ library bitvis_vip_clock_generator;
entity tb_playback_controller is
generic(
- use_vunit: boolean := false -- @suppress "Unused generic: use_vunit is not used in work.tb_playback_controller(RTL)"
+ use_vunit : boolean := false -- @suppress "Unused generic: use_vunit is not used in work.tb_playback_controller(RTL)"
);
port(
- uvvm_completed: out std_logic := '0'
+ uvvm_completed : out std_logic := '0'
);
end entity tb_playback_controller;
architecture RTL of tb_playback_controller is
- signal clk : std_logic; -- 40 MHz BC clock
+ signal clk : std_logic; -- 40 MHz BC clock
signal rst : std_logic;
- signal start_pulse_i : std_logic := '0'; -- toggle this input to initiate the readout
- signal readout_active_o : std_logic; -- '1' when the readout is in progress
+ signal start_pulse_i : std_logic := '0'; -- toggle this input to initiate the readout
+ signal readout_active_o : std_logic; -- '1' when the readout is in progress
- subtype t_data is std_logic_vector(playback_controller_data'range); -- 8 bit wide
+ subtype t_data is std_logic_vector(playback_controller_data'range); -- 8 bit wide
subtype t_addr is std_logic_vector(playback_controller_address'range);
type t_data_array is array (natural range <>) of t_data;
@@ -68,29 +68,29 @@ architecture RTL of tb_playback_controller is
signal read_addr_stop_i : t_addr := (others => '0');
-- output interface
- signal data_o : std_logic_vector(playback_controller_data'range); -- data read out from BRAM
- signal valid_o : std_logic; -- indicates data_o is valid this clk cycle
- signal ready_i : std_logic := '0'; -- the receiving side indicates it's ready for more data
+ signal data_o : std_logic_vector(playback_controller_data'range); -- data read out from BRAM
+ signal valid_o : std_logic; -- indicates data_o is valid this clk cycle
+ signal ready_i : std_logic := '0'; -- the receiving side indicates it's ready for more data
- constant C_CLK_PERIOD : time := 25 ns;
- constant C_CYCLES_RST : integer := 3;
+ constant C_CLK_PERIOD : time := 25 ns;
+ constant C_CYCLES_RST : integer := 3;
--constant C_STABLE_PERIODS : integer := 10;
--constant C_MAX_CYCLES_PER_BYTE : integer := 4;
- constant C_USER_WIDTH : integer := 1;
- constant C_ID_WIDTH : integer := 1;
- constant C_DEST_WIDTH : integer := 1;
- constant C_DATA_WIDTH : integer := playback_controller_data'length;
+ constant C_USER_WIDTH : integer := 1;
+ constant C_ID_WIDTH : integer := 1;
+ constant C_DEST_WIDTH : integer := 1;
+ constant C_DATA_WIDTH : integer := playback_controller_data'length;
--constant C_FRAME_WIDTH : integer := 16;
-- input interface
- signal data_in : t_axistream_if(tdata(C_DATA_WIDTH - 1 downto 0),--@suppress
- tkeep((C_DATA_WIDTH / 8) - 1 downto 0),
- tuser(C_USER_WIDTH - 1 downto 0),
- tstrb((C_DATA_WIDTH / 8) - 1 downto 0),
- tid(C_ID_WIDTH - 1 downto 0),
- tdest(C_DEST_WIDTH - 1 downto 0)
- );
+ signal data_in : t_axistream_if(tdata(C_DATA_WIDTH - 1 downto 0), --@suppress
+ tkeep((C_DATA_WIDTH / 8) - 1 downto 0),
+ tuser(C_USER_WIDTH - 1 downto 0),
+ tstrb((C_DATA_WIDTH / 8) - 1 downto 0),
+ tid(C_ID_WIDTH - 1 downto 0),
+ tdest(C_DEST_WIDTH - 1 downto 0)
+ );
constant max_data_legth : natural := 256;
@@ -98,16 +98,18 @@ architecture RTL of tb_playback_controller is
constant zero_data : t_data := (others => '0');
-- shared variables to control readout verification
- shared variable data_expected : t_data_array(0 to 1024) := (others => zero_data);
- shared variable data_expected_count : natural := 0;
- shared variable read_delay_clk_cycles : natural := 0;
+ shared variable data_expected : t_data_array(0 to 1024) := (others => zero_data);
+ shared variable data_expected_count : natural := 0;
+ shared variable read_delay_clk_cycles : natural := 0;
signal verify_data_en, verify_data_done : boolean := false;
- signal verify_data_ack : std_logic := '0';
+ signal verify_data_ack : std_logic := '0';
-- count number of valid words presented by the FIFO
- signal valid_word_count : natural := 0;
+ signal valid_word_count : natural := 0;
signal valid_word_count_rst : std_logic := '0';
+ signal playback_loops_i : std_logic_vector(15 downto 0) := x"0000";
+ shared variable loops_prime : natural := 0;
begin
@@ -145,8 +147,8 @@ begin
verify_data_en <= true;
start_readout;
await_value(verify_data_done, true, 0 ns,
- (3 + delay_clk_cycles) * data_expected_count * C_CLK_PERIOD,
- ERROR, "Waiting for the data verification to complete");
+ (3 + delay_clk_cycles) * data_expected_count * C_CLK_PERIOD * loops_prime,
+ ERROR, "Waiting for the data verification to complete");
verify_data_en <= false;
verify_data_ack <= '1';
@@ -165,6 +167,15 @@ begin
wait_num_rising_edge(clk, duration);
end;
+ -- set loop counter
+ procedure set_loop_counter(
+ loops : natural
+ ) is
+ begin
+ playback_loops_i <= std_logic_vector(to_unsigned(loops, 16));
+ loops_prime := 1 when (loops = 0) else loops;
+ end;
+
-- moves the BRAM write pointer to addr
procedure set_write_pointer(
addr : t_addr
@@ -185,12 +196,12 @@ begin
) is
variable delay : time;
begin
- axistream_transmit(AXISTREAM_VVCT, 2, std_logic_vector'(data),--@suppress
- "Writing " & to_hstring(data));
+ axistream_transmit(AXISTREAM_VVCT, 2, std_logic_vector'(data), --@suppress
+ "Writing " & to_hstring(data));
if delay_clk_cycles > 0 then
delay := delay_clk_cycles * C_CLK_PERIOD;
- insert_delay(AXISTREAM_VVCT, 2, delay, "Inserting " &--@suppress
- to_string(delay) & " delay", C_SCOPE);
+ insert_delay(AXISTREAM_VVCT, 2, delay, "Inserting " & --@suppress
+ to_string(delay) & " delay", C_SCOPE);
end if;
end;
@@ -230,8 +241,8 @@ begin
make_random_data(byte_count);
data := random_data(0 to byte_count - 1);
write_array(data => data, delay_clk_cycles => write_delay_clk_cycles);
- await_completion(AXISTREAM_VVCT, 2, byte_count * (5 + write_delay_clk_cycles ) * C_CLK_PERIOD,--@suppress
- "Waiting for the transmission to finish");
+ await_completion(AXISTREAM_VVCT, 2, byte_count * (5 + write_delay_clk_cycles) * C_CLK_PERIOD, --@suppress
+ "Waiting for the transmission to finish");
verify_data(data_exp => data, delay_clk_cycles => read_delay_clk_cycles);
end;
@@ -240,13 +251,13 @@ begin
------------------------------------------------
begin
await_uvvm_initialization(VOID);
- start_clock(CLOCK_GENERATOR_VVCT, 1, "Start clock generator");--@suppress
+ start_clock(CLOCK_GENERATOR_VVCT, 1, "Start clock generator"); --@suppress
disable_log_msg(ALL_MESSAGES);
enable_log_msg(ID_LOG_HDR);
enable_log_msg(ID_SEQUENCER);
- disable_log_msg(CLOCK_GENERATOR_VVCT, 1, ALL_MESSAGES);--@suppress
- disable_log_msg(AXISTREAM_VVCT, 2, ALL_MESSAGES);--@suppress
+ disable_log_msg(CLOCK_GENERATOR_VVCT, 1, ALL_MESSAGES); --@suppress
+ disable_log_msg(AXISTREAM_VVCT, 2, ALL_MESSAGES); --@suppress
log(ID_LOG_HDR, "Checking behavior when rst = 1", C_SCOPE);
set_rst('1');
@@ -256,25 +267,52 @@ begin
check_value(data_in.tready, '1', ERROR, "tready = 1 when rst = 1");
set_rst('0');
- log(ID_LOG_HDR, "Writing some data to trickle configuration (fast) and reading it back (fast)", C_SCOPE);
+ set_loop_counter(0); -- Note 0 is translated to 1 to allow resetting reg to zero
+ log(ID_LOG_HDR, "Writing some data to trickle configuration (fast) and reading it back (fast), 0 loops", C_SCOPE);
+ write_and_verify(write_delay_clk_cycles => 0, read_delay_clk_cycles => 0);
+
+ log(ID_LOG_HDR, "Writing some data to trickle configuration (slow) and reading it back (fast), 0 loops", C_SCOPE);
+ write_and_verify(write_delay_clk_cycles => 10, read_delay_clk_cycles => 0);
+
+ log(ID_LOG_HDR, "Writing some data to trickle configuration (fast) and reading it back (slow), 0 loops", C_SCOPE);
+ write_and_verify(write_delay_clk_cycles => 0, read_delay_clk_cycles => 10);
+
+ log(ID_LOG_HDR, "Writing some data to trickle configuration (slow) and reading it back (slow), 0 loops", C_SCOPE);
+ write_and_verify(write_delay_clk_cycles => 10, read_delay_clk_cycles => 10);
+
+ set_loop_counter(1);
+ log(ID_LOG_HDR, "Writing some data to trickle configuration (fast) and reading it back (fast), 1 loops", C_SCOPE);
+ write_and_verify(write_delay_clk_cycles => 0, read_delay_clk_cycles => 0);
+
+ log(ID_LOG_HDR, "Writing some data to trickle configuration (slow) and reading it back (fast), 1 loops", C_SCOPE);
+ write_and_verify(write_delay_clk_cycles => 10, read_delay_clk_cycles => 0);
+
+ log(ID_LOG_HDR, "Writing some data to trickle configuration (fast) and reading it back (slow), 1 loops", C_SCOPE);
+ write_and_verify(write_delay_clk_cycles => 0, read_delay_clk_cycles => 10);
+
+ log(ID_LOG_HDR, "Writing some data to trickle configuration (slow) and reading it back (slow), 1 loops", C_SCOPE);
+ write_and_verify(write_delay_clk_cycles => 10, read_delay_clk_cycles => 10);
+
+ set_loop_counter(10);
+ log(ID_LOG_HDR, "Writing some data to trickle configuration (fast) and reading it back (fast), 10 loops", C_SCOPE);
write_and_verify(write_delay_clk_cycles => 0, read_delay_clk_cycles => 0);
- log(ID_LOG_HDR, "Writing some data to trickle configuration (slow) and reading it back (fast)", C_SCOPE);
+ log(ID_LOG_HDR, "Writing some data to trickle configuration (slow) and reading it back (fast), 10 loops", C_SCOPE);
write_and_verify(write_delay_clk_cycles => 10, read_delay_clk_cycles => 0);
- log(ID_LOG_HDR, "Writing some data to trickle configuration (fast) and reading it back (slow)", C_SCOPE);
+ log(ID_LOG_HDR, "Writing some data to trickle configuration (fast) and reading it back (slow), 10 loops", C_SCOPE);
write_and_verify(write_delay_clk_cycles => 0, read_delay_clk_cycles => 10);
- log(ID_LOG_HDR, "Writing some data to trickle configuration (slow) and reading it back (slow)", C_SCOPE);
+ log(ID_LOG_HDR, "Writing some data to trickle configuration (slow) and reading it back (slow), 10 loops", C_SCOPE);
write_and_verify(write_delay_clk_cycles => 10, read_delay_clk_cycles => 10);
-- Finish the simulation
- wait for 1000 ns; -- to allow some time for completion
- report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
+ wait for 1000 ns; -- to allow some time for completion
+ report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
uvvm_completed <= '1';
wait for 1 us;
- stop_clock(CLOCK_GENERATOR_VVCT, 1, "Stop clock generator");--@suppress
- wait; -- to stop completely
+ stop_clock(CLOCK_GENERATOR_VVCT, 1, "Stop clock generator"); --@suppress
+ wait; -- to stop completely
end process;
@@ -283,16 +321,17 @@ begin
-----------------------------------------------------------------------------
DUT : entity work.playback_controller
generic map(
- USE_ULTRARAM => false
+ USE_ULTRARAM => false
)
port map(
clk => clk,
rst => rst,
start_pulse_i => start_pulse_i,
readout_active_o => readout_active_o,
- data_i => data_in.tdata,--@suppress
- valid_i => data_in.tvalid,--@suppress
- ready_o => data_in.tready,--@suppress
+ playback_loops_i => playback_loops_i,
+ data_i => data_in.tdata, --@suppress
+ valid_i => data_in.tvalid, --@suppress
+ ready_o => data_in.tready, --@suppress
set_write_addr_pulse_i => set_write_addr_pulse_i,
write_addr_start_i => write_addr_start_i,
read_addr_start_i => read_addr_start_i,
@@ -305,7 +344,7 @@ begin
i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
i_clock_generator_vvc : entity bitvis_vip_clock_generator.clock_generator_vvc
- generic map( -- @suppress "Generic map uses default values. Missing optional actuals: GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY, GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY"
+ generic map( -- @suppress "Generic map uses default values. Missing optional actuals: GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY, GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY"
GC_INSTANCE_IDX => 1,
GC_CLOCK_NAME => "Clock",
GC_CLOCK_PERIOD => C_CLK_PERIOD,
@@ -316,7 +355,7 @@ begin
);
i_axistream_vvc_master : entity bitvis_vip_axistream.axistream_vvc
- generic map( -- @suppress "Generic map uses default values. Missing optional actuals: GC_PACKETINFO_QUEUE_COUNT_MAX, GC_AXISTREAM_BFM_CONFIG, GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY, GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY"
+ generic map( -- @suppress "Generic map uses default values. Missing optional actuals: GC_PACKETINFO_QUEUE_COUNT_MAX, GC_AXISTREAM_BFM_CONFIG, GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY, GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY"
GC_VVC_IS_MASTER => true,
GC_DATA_WIDTH => C_DATA_WIDTH,
GC_USER_WIDTH => C_USER_WIDTH,
@@ -325,42 +364,47 @@ begin
GC_INSTANCE_IDX => 2)
port map(
clk => clk,
- axistream_vvc_if => data_in);--@suppress
+ axistream_vvc_if => data_in); --@suppress
data_checker : process is
- variable i : integer := 0;
+ variable i : integer := 0;
+ variable loop_counter : integer := 0;
begin
if verify_data_en then
- i := 0;
+ loop_counter := loops_prime;
valid_word_count_rst <= '1';
wait until rising_edge(clk);
valid_word_count_rst <= '0';
wait until rising_edge(clk);
log(ID_SEQUENCER_SUB, "Data checker is waiting for data");
- while (i < data_expected_count) loop
- await_value(valid_o, '1', 0 ns, C_CLK_PERIOD * 10, ERROR, "Waiting for playback controller data to become valid");
- ready_i <= '1';
- wait for C_CLK_PERIOD / 2;
- if ?? valid_o then
- check_value(readout_active_o, '1', ERROR, "Readout active flag is 1");
- check_value(data_o, data_expected(i), ERROR, "Value read from playback controller matches the expected value");
- wait until rising_edge(clk);
- i := i + 1;
- if read_delay_clk_cycles > 0 then
- ready_i <= '0';
- wait_num_rising_edge(clk, read_delay_clk_cycles);
- ready_i <= '1';
+ while (loop_counter > 0) loop
+ i := 0;
+ while (i < data_expected_count) loop
+ await_value(valid_o, '1', 0 ns, C_CLK_PERIOD * 10, ERROR, "Waiting for playback controller data to become valid");
+ ready_i <= '1';
+ wait for C_CLK_PERIOD / 2;
+ if ?? valid_o then
+ check_value(readout_active_o, '1', ERROR, "Readout active flag is 1");
+ check_value(data_o, data_expected(i), ERROR, "Value read from playback controller matches the expected value");
+ wait until rising_edge(clk);
+ if read_delay_clk_cycles > 0 then
+ ready_i <= '0';
+ wait_num_rising_edge(clk, read_delay_clk_cycles);
+ end if;
+ i := i + 1;
+ else
+ wait until rising_edge(clk);
end if;
- else
- wait until rising_edge(clk);
- end if;
+ end loop;
+ loop_counter := loop_counter - 1;
+ wait until rising_edge(clk);
end loop;
wait until rising_edge(clk);
check_value(valid_o, '0', ERROR, "The playback controller FIFO is empty");
- check_value(valid_word_count, data_expected_count, ERROR, "The number of words read out from playback controller was correct");
+ check_value(valid_word_count, data_expected_count * loops_prime, ERROR, "The number of words read out from playback controller was correct");
wait_num_rising_edge(clk, 2);
- ready_i <= '0';
+ ready_i <= '0';
wait_num_rising_edge(clk, 2);
verify_data_done <= true;
wait until rising_edge(verify_data_ack);
@@ -378,7 +422,7 @@ begin
if ?? valid_word_count_rst then
valid_word_count <= 0;
else
- valid_word_count <= valid_word_count + 1 when (?? valid_o) and (?? ready_i);
+ valid_word_count <= valid_word_count + 1 when ( ?? valid_o) and ( ?? ready_i);
end if;
end if;
end process;
diff --git a/simulation/UVVMtests/tb/ByteToAxiStream_tb.vhd b/simulation/UVVMtests/tb/ByteToAxiStream_tb.vhd
index d65b97ab5cca10338343431e207dd8f8145268e3..be52189f4a20bef4b0b9c3556e3f75dc24938229 100644
--- a/simulation/UVVMtests/tb/ByteToAxiStream_tb.vhd
+++ b/simulation/UVVMtests/tb/ByteToAxiStream_tb.vhd
@@ -412,6 +412,7 @@ begin
EOB => EOB1b,
TruncateIn => TruncateIn1b,
CodingErrorIn => '0',
+ FramingErrorIn => '0',
m_axis => m_axis1b,
m_axis_tready => m_axis_tready_1b,
m_axis_aclk => clk160,
@@ -439,6 +440,7 @@ begin
EOB => EOB2b,
TruncateIn => TruncateIn2b,
CodingErrorIn => '0',
+ FramingErrorIn => '0',
m_axis => m_axis2b,
m_axis_tready => m_axis_tready_2b,
m_axis_aclk => clk160,
@@ -466,6 +468,7 @@ begin
EOB => EOB4b,
TruncateIn => TruncateIn4b,
CodingErrorIn => '0',
+ FramingErrorIn => '0',
m_axis => m_axis4b,
m_axis_tready => m_axis_tready_4b,
m_axis_aclk => clk160,
diff --git a/simulation/UVVMtests/tb/GBTLinkToHost_tb.vhd b/simulation/UVVMtests/tb/GBTLinkToHost_tb.vhd
index 1503b30bdddcdfbed577cf7416b2ca1b886ac8bc..d0beb30bddfba773fad1cdd143ab4cda6f2abbca 100644
--- a/simulation/UVVMtests/tb/GBTLinkToHost_tb.vhd
+++ b/simulation/UVVMtests/tb/GBTLinkToHost_tb.vhd
@@ -66,10 +66,10 @@ architecture arch of GBTLinkToHost_tb is
constant FIRMWARE_MODE : integer := FIRMWARE_MODE_GBT;
constant NUMBER_OF_DESCRIPTORS : integer := 2;
constant STREAMS_TOHOST: integer := STREAMS_TOHOST_MODE(FIRMWARE_MODE);
- constant BLOCKSIZE : integer :=1024;
+ constant BLOCKSIZE : integer := 1024;
constant LOCK_PERIOD : integer := 640;
constant DATA_WIDTH : integer := 256;
- constant SIM_NUMBER_OF_BLOCKS : integer := 500;
+ constant SIM_NUMBER_OF_BLOCKS : integer := 500; -- 5000; --500;
constant pcie_endpoint: integer := 0;
@@ -173,6 +173,7 @@ begin
GEN_SCF_LINKS: for i in 0 to 11 generate
register_map_40_control.SUPER_CHUNK_FACTOR_LINK(i) <= x"01";
register_map_40_control.CRTOHOST_INSTANT_TIMEOUT_ENA(i) <= "000000000000000000000000000000000000000001";
+ --register_map_40_control.CRTOHOST_INSTANT_TIMEOUT_ENA(i) <= "000000000000000000000000000000000000000000"; --No instant timeout
end generate;
diff --git a/simulation/VUnit/tcl/source_sim_filesets.tcl b/simulation/VUnit/tcl/source_sim_filesets.tcl
index bf6e0fffd0d55546784fcdae41f948946ae70d97..83aec0d5cc64b4fbc9e35ac551f15770034de2ce 100644
--- a/simulation/VUnit/tcl/source_sim_filesets.tcl
+++ b/simulation/VUnit/tcl/source_sim_filesets.tcl
@@ -27,6 +27,11 @@ source $PROJECT_ROOT/scripts/filesets/ttc_decoder_fileset.tcl
source $PROJECT_ROOT/scripts/filesets/ttc_emulator_fileset.tcl
source $PROJECT_ROOT/scripts/filesets/wupper_fileset.tcl
source $PROJECT_ROOT/scripts/filesets/bcm_fileset.tcl
+source $PROJECT_ROOT/scripts/filesets/felig_fileset.tcl
+source $PROJECT_ROOT/scripts/filesets/fmemu_fileset.tcl
+source $PROJECT_ROOT/scripts/filesets/fmemu_top_fileset.tcl
+source $PROJECT_ROOT/scripts/filesets/lpgbt_fe_core_fileset.tcl
+
set SIM_ARCH "KU"
if { $SIM_ARCH == "V7" } {
set XCI_FILES [concat $XCI_FILES $XCI_FILES_V7]
diff --git a/sources/AxisUtils/Axis32Fifo.vhd b/sources/AxisUtils/Axis32Fifo.vhd
index 78f3f779112ff29c59faef8722ce1fc19eed287e..9e4943af87259cf461314c68a8da6e109a06c07c 100644
--- a/sources/AxisUtils/Axis32Fifo.vhd
+++ b/sources/AxisUtils/Axis32Fifo.vhd
@@ -77,6 +77,7 @@ architecture rtl of Axis32Fifo is
signal busy_sync: std_logic;
signal trunc_sync: std_logic;
+ signal framing_error_sync: std_logic;
signal s_axis_tready_s : std_logic;
signal s_axis_tuser: std_logic_vector(2 downto 0);
signal s_axis_tvalid : std_logic;
@@ -86,7 +87,7 @@ architecture rtl of Axis32Fifo is
signal m_axis_tvalid : std_logic;
signal m_axis_tdata : std_logic_vector(31 downto 0);
signal m_axis_tlast : std_logic;
- signal s_axis_tuser_2, s_axis_tuser_3: std_logic; --for xpm cdc sync
+ signal s_axis_tuser_2, s_axis_tuser_3, s_axis_tuser_1: std_logic; --for xpm cdc sync
signal m_axis_aresetn: std_logic;
begin
@@ -165,6 +166,20 @@ begin
dest_out => s_axis_tuser_2 -- 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
);
+ xpm_cdc_err : xpm_cdc_single
+ generic map (
+ DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
+ INIT_SYNC_FF => 0, -- DECIMAL; integer; 0=disable simulation init values, 1=enable simulation init values
+ SIM_ASSERT_CHK => 0, -- DECIMAL; integer; 0=disable simulation messages, 1=enable simulation messages
+ SRC_INPUT_REG => 1 -- DECIMAL; integer; 0=do not register input, 1=register input
+ )
+ port map (
+ src_clk => s_axis_aclk, -- 1-bit input: optional; required when SRC_INPUT_REG = 1
+ src_in => s_axis.tuser(1), -- 1-bit input: Input signal to be synchronized to dest_clk domain.
+ dest_clk => m_axis_aclk, -- 1-bit input: Clock signal for the destination clock domain.
+ dest_out => s_axis_tuser_1 -- 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
+ );
+
sync_s_axis_aresetn : xpm_cdc_sync_rst
generic map (
DEST_SYNC_FF => 2,
@@ -182,7 +197,10 @@ begin
variable busy_sync_v: std_logic;
variable trunc_sync_v: std_logic;
variable trunc_sync_p1: std_logic;
- variable trunc_cnt: integer range 0 to 3; --count truncations in FIFO, max 3
+ variable framing_error_sync_v: std_logic;
+ variable framing_error_sync_p1: std_logic;
+ constant max_trunc_cnt: integer := 15;
+ variable trunc_cnt: integer range 0 to 15; --count truncations in FIFO
begin
if m_axis_aresetn = '0' then
trunc_cnt := 0;
@@ -190,30 +208,36 @@ begin
trunc_sync <= '0';
trunc_sync_p1 := '0';
trunc_sync_v := '0';
+ framing_error_sync <= '0';
+ framing_error_sync_p1 := '0';
+ framing_error_sync_v := '0';
busy_sync_v := '0';
elsif rising_edge(m_axis_aclk) then
busy_sync <= busy_sync_v;
busy_sync_v := s_axis_tuser_2;
--Truncate flag does not go through FIFO to save resources, use error flag instead and replace if after fifo.
trunc_sync_v := s_axis_tuser_3;
- if trunc_sync_v = '1' and trunc_sync_p1 = '0' then --Before FIFO truncation was asserted, count up to maximum 3
+ framing_error_sync_v := s_axis_tuser_3 and s_axis_tuser_1; --Both T and E were set at the same time
+ if trunc_sync_v = '1' and trunc_sync_p1 = '0' then --Before FIFO truncation was asserted, count up to maximum max_trunc_cnt
trunc_sync <= '1';
- if trunc_cnt /= 3 then
+ if trunc_cnt /= max_trunc_cnt then
trunc_cnt := trunc_cnt + 1;
end if;
end if;
+ if framing_error_sync_v = '1' and framing_error_sync_p1 = '0' then --Before FIFO truncation was asserted, count counter is already done with trunc_sync
+ framing_error_sync <= '1';
+ end if;
if m_axis_tuser(2) = '1' and m_axis_tready = '1' and m_axis_tlast = '1' then --Truncation handled by m_axis, decrement counter
- trunc_sync <= '0';
if trunc_cnt /= 0 then
trunc_cnt := trunc_cnt - 1;
end if;
end if;
- if trunc_cnt /= 0 then --Counter not zero, tell m_axis_tuser to set trunc flag instead of chunk error.
- trunc_sync <= '1';
- else
+ if trunc_cnt = 0 then --Counter not zero, tell m_axis_tuser to set trunc flag instead of chunk error.
trunc_sync <= '0';
+ framing_error_sync <= '0';
end if;
trunc_sync_p1 := trunc_sync_v; --pipeline.
+ framing_error_sync_p1 := framing_error_sync_v; --pipeline.
end if;
end process;
@@ -329,7 +353,7 @@ begin
begin
m_axis.tuser(3) <= m_axis_tuser(2) and trunc_sync; --Error bit used as truncation bit
m_axis.tuser(2) <= busy_sync;
- m_axis.tuser(1) <= m_axis_tuser(2) and not trunc_sync; --Error bit
+ m_axis.tuser(1) <= m_axis_tuser(2) and ((not trunc_sync) or framing_error_sync); --Error bit, in case of Framing error, we set T+E flags
m_axis.tuser(0) <= '0'; --Unused in GBT mode where we use the builtin fifo.
m_axis.tvalid <= m_axis_tvalid;
m_axis.tdata <= m_axis_tdata;
diff --git a/sources/FELIG/aurora_will/aurora_64b66b_1TXch_tx_lane_init_sm_simplex.v b/sources/FELIG/aurora_will/aurora_64b66b_1TXch_tx_lane_init_sm_simplex.v
index ebf7ae6f7badac898b29c600c474e8ff90b7aeb2..52cbd1193b70c7454d8aaedb2409c4364e2686a8 100644
--- a/sources/FELIG/aurora_will/aurora_64b66b_1TXch_tx_lane_init_sm_simplex.v
+++ b/sources/FELIG/aurora_will/aurora_64b66b_1TXch_tx_lane_init_sm_simplex.v
@@ -170,7 +170,7 @@ assign tx_resetdone_in_sync3 = 1;//WB remove u_rst_sync_tx_resetdone
assign count_done_for_lane_ready = (counter2_r == 24'd0);
// LANE_UP is asserted when in the READY state.
- FDR lane_up_flop_i
+ FDR lane_up_flop_i //@suppress
(
.D(count_done_for_lane_ready),
.C(USER_CLK),
diff --git a/sources/FELIG/data_generator/elink_data_emulator.vhd b/sources/FELIG/data_generator/elink_data_emulator.vhd
index ba392a62519f82fd5fb4aa137507deae69241f45..5bea4d80b0e37ccaac284248edc016e961aa9736 100644
--- a/sources/FELIG/data_generator/elink_data_emulator.vhd
+++ b/sources/FELIG/data_generator/elink_data_emulator.vhd
@@ -349,7 +349,7 @@ begin
------------------------------------------------------------
-- EPATH_FIFO
------------------------------------------------------------
- UEF_IN : entity work.upstreamEpathFifoWrap
+ UEF_IN : entity work.upstreamEpathFifoWrap_felig
port map(
bitCLK => '0',
rst => elink_tx_rst,
@@ -534,6 +534,7 @@ begin
-- clk40 => clk240,
clk40 => clk,
rst => emu_control.reset,
+ clk40_stable => '1',
cr_rst => elink_tx_rst,
cr_fifo_flush => fifo_flush
);
diff --git a/sources/FELIG/emulator/Emulator.vhd b/sources/FELIG/emulator/Emulator.vhd
index 64e2e8c50c69135df117a662d9d6e6169a3cb7fa..29931ba4d053cbcf8511346429718fd72309df48 100644
--- a/sources/FELIG/emulator/Emulator.vhd
+++ b/sources/FELIG/emulator/Emulator.vhd
@@ -1005,7 +1005,7 @@ begin
-- gen_ttc_wrapper_comp : if sim_emulator = false generate
- ttc_wrapper_comp : entity work.ttc_wrapper
+ ttc_wrapper_comp : entity work.ttc_wrapper_felig
port map (
a_data_in => gbt_extractedl1a,
b_data_in => gbt_extracted_bchan,
diff --git a/sources/FELIG/emulator/mux_128_sync.vhd b/sources/FELIG/emulator/mux_128_sync.vhd
index 58a5ade50b3855825a0ffb4e08fa8dd2f823a315..7846abe5b5229157bc3ab15635627f6351778114 100644
--- a/sources/FELIG/emulator/mux_128_sync.vhd
+++ b/sources/FELIG/emulator/mux_128_sync.vhd
@@ -42,7 +42,7 @@ library ieee;
library UNISIM;
use UNISIM.Vcomponents.ALL;
-Library XilinxCoreLib;
+--Library XilinxCoreLib;
entity mux_128_sync is
port (
diff --git a/sources/FELIG/emulator/mux_16.vhd b/sources/FELIG/emulator/mux_16.vhd
index 96a89f4b0dbd068c1fbb46357341661d832c4c00..ff7525aa4329ea895d0dd315a0a22c844e58a049 100644
--- a/sources/FELIG/emulator/mux_16.vhd
+++ b/sources/FELIG/emulator/mux_16.vhd
@@ -42,7 +42,7 @@ library ieee;
library UNISIM;
use UNISIM.Vcomponents.ALL;
-Library XilinxCoreLib;
+--Library XilinxCoreLib;
entity mux_16 is
port (
@@ -68,7 +68,7 @@ begin
);
end generate gen_mux_8;
- MUXF8_comp : MUXF8_D
+ MUXF8_comp : MUXF8_D --@suppress
port map (
LO => bit_output_local, -- Ouptut of MUX to local routing
O => bit_output, -- Output of MUX to general routing
diff --git a/sources/FELIG/emulator/mux_8.vhd b/sources/FELIG/emulator/mux_8.vhd
index 44e51c488eb310536a431e84942d2e0d211128b7..7bcf68eb456afe32b2343b96b42cc8332fd3f549 100644
--- a/sources/FELIG/emulator/mux_8.vhd
+++ b/sources/FELIG/emulator/mux_8.vhd
@@ -42,7 +42,7 @@ library ieee;
library UNISIM;
use UNISIM.Vcomponents.ALL;
-Library XilinxCoreLib;
+--Library XilinxCoreLib;
entity mux_8 is
port (
@@ -66,7 +66,7 @@ begin
'0';
end generate gen_mux_4;
- MUXF7_comp : MUXF7_D
+ MUXF7_comp : MUXF7_D --@suppress
port map (
LO => bit_output_local, -- Ouptut of MUX to local routing
O => bit_output, -- Output of MUX to general routing
diff --git a/sources/FELIG/felix_modified/centralRouter/upstreamEpathFifoWrap.vhd b/sources/FELIG/felix_modified/centralRouter/upstreamEpathFifoWrap_felig.vhd
similarity index 98%
rename from sources/FELIG/felix_modified/centralRouter/upstreamEpathFifoWrap.vhd
rename to sources/FELIG/felix_modified/centralRouter/upstreamEpathFifoWrap_felig.vhd
index e204c7bd3e588f14fe18b3861971300af96614ec..377b3241972897fe9c78e26441d9556652120a5d 100644
--- a/sources/FELIG/felix_modified/centralRouter/upstreamEpathFifoWrap.vhd
+++ b/sources/FELIG/felix_modified/centralRouter/upstreamEpathFifoWrap_felig.vhd
@@ -56,7 +56,7 @@ library ieee,work;
use work.ip_lib.ALL;
--! EPATH FIFO 18 bit wide, 2K deep
-entity upstreamEpathFifoWrap is
+entity upstreamEpathFifoWrap_felig is
port (
bitCLK : in std_logic; --IG: add clock 40 to extract ready signal in 40 MHz
rst : in std_logic;
@@ -83,9 +83,9 @@ entity upstreamEpathFifoWrap is
ila_rd_en_pipe_0 : out std_logic;
ila_rd_en_pipe_1 : out std_logic
);
-end upstreamEpathFifoWrap;
+end upstreamEpathFifoWrap_felig;
-architecture Behavioral of upstreamEpathFifoWrap is
+architecture Behavioral of upstreamEpathFifoWrap_felig is
signal rd_en_s, empty_efifo, prog_full_s : std_logic := '0';
diff --git a/sources/FELIG/felix_modified/ttc/ttc_decoder/ttc_decode_wrapper.vhd b/sources/FELIG/felix_modified/ttc/ttc_decoder/ttc_decode_wrapper_felig.vhd
similarity index 99%
rename from sources/FELIG/felix_modified/ttc/ttc_decoder/ttc_decode_wrapper.vhd
rename to sources/FELIG/felix_modified/ttc/ttc_decoder/ttc_decode_wrapper_felig.vhd
index 759dcd1ee75ffbf82b5de404c7fbc894452f6f6b..d9604f7c25cb0c786460133d917e27d2cc9bd242 100644
--- a/sources/FELIG/felix_modified/ttc/ttc_decoder/ttc_decode_wrapper.vhd
+++ b/sources/FELIG/felix_modified/ttc/ttc_decoder/ttc_decode_wrapper_felig.vhd
@@ -52,7 +52,7 @@ library UNISIM;
--=================================================================================================--
--======================================= Module Body =============================================--
--=================================================================================================--
-entity ttc_wrapper is
+entity ttc_wrapper_felig is
port (
--== ttc fmc interface ==--
a_data_in : in std_logic;
@@ -89,11 +89,11 @@ entity ttc_wrapper is
TTC_ToHost_Data_out : out TTC_ToHost_data_type
);
-end ttc_wrapper;
+end ttc_wrapper_felig;
-architecture top of ttc_wrapper is
+architecture top of ttc_wrapper_felig is
--signal RESET : std_logic;
--========================= Signal Declarations ==========================--
--signal cdrbad : std_logic;
@@ -498,7 +498,7 @@ begin
--=====================================--
- ttc_dec: entity work.ttc_decoder_core
+ ttc_dec: entity work.ttc_decoder_core_felig
--=====================================--
port map
(
diff --git a/sources/FELIG/felix_modified/ttc/ttc_decoder/ttc_decoder_core.vhd b/sources/FELIG/felix_modified/ttc/ttc_decoder/ttc_decoder_core_felig.vhd
similarity index 99%
rename from sources/FELIG/felix_modified/ttc/ttc_decoder/ttc_decoder_core.vhd
rename to sources/FELIG/felix_modified/ttc/ttc_decoder/ttc_decoder_core_felig.vhd
index 238181012e93d5cae8394a78c111e56dbf3e05b5..3fc740a8f7f5e9370cda3824979ae7f49f93f6d9 100644
--- a/sources/FELIG/felix_modified/ttc/ttc_decoder/ttc_decoder_core.vhd
+++ b/sources/FELIG/felix_modified/ttc/ttc_decoder/ttc_decoder_core_felig.vhd
@@ -129,7 +129,7 @@ library ieee;
--=================================================================================================--
--======================================= Module Body =============================================--
--=================================================================================================--
-entity ttc_decoder_core is
+entity ttc_decoder_core_felig is
port
(
--== cdr interface ==--
@@ -157,9 +157,9 @@ entity ttc_decoder_core is
add_d8 : out std_logic_vector(7 downto 0)
);
-end ttc_decoder_core;
+end ttc_decoder_core_felig;
-architecture core of ttc_decoder_core is
+architecture core of ttc_decoder_core_felig is
diff --git a/sources/FELIG/housekeeping/housekeeping_module_FELIG.vhd b/sources/FELIG/housekeeping/housekeeping_module_FELIG.vhd
index e687e3b74fe6e6fdf36467a0c0ffe7ea7038b40d..0fe527f06d233ea03f15a0565e19407d55099624 100644
--- a/sources/FELIG/housekeeping/housekeeping_module_FELIG.vhd
+++ b/sources/FELIG/housekeeping/housekeeping_module_FELIG.vhd
@@ -91,6 +91,7 @@ entity housekeeping_module_FELIG is
PORT_GOOD : in std_logic_vector(7 downto 0);
SHPC_INT : out std_logic;
lnk_up : in std_logic_vector(1 downto 0);
+ select_bifurcation : in std_logic_vector(NUM_BIFURCATION_SELECT(CARD_TYPE)-1 downto 0);
RXUSRCLK_IN : in std_logic_vector((GBT_NUM*ENDPOINTS)-1 downto 0);
versal_sys_reset_n_out : out std_logic
);
@@ -394,6 +395,7 @@ begin
generic map(
CARD_TYPE => CARD_TYPE)
port map(
+ select_bifurcation => select_bifurcation,
I2C_SMB => I2C_SMB,
I2C_SMBUS_CFG_nEN => I2C_SMBUS_CFG_nEN,
MGMT_PORT_EN => MGMT_PORT_EN,
diff --git a/sources/FelixTop/felig_top_bnl712.vhd b/sources/FelixTop/felig_top_bnl712.vhd
index 369c6d50940289673c5554b52a05a63f68c5e695..ff1e2e2b6b9d096186e06e83a38fa84939cdcdb9 100644
--- a/sources/FelixTop/felig_top_bnl712.vhd
+++ b/sources/FelixTop/felig_top_bnl712.vhd
@@ -149,6 +149,7 @@ entity felig_top_bnl712 is
PEX_PERSTn : out std_logic_vector(NUM_PEX(CARD_TYPE)-1 downto 0);
PEX_SCL : out std_logic_vector(NUM_PEX(CARD_TYPE)-1 downto 0);
PEX_SDA : inout std_logic_vector(NUM_PEX(CARD_TYPE)-1 downto 0);
+ select_bifurcation : in std_logic_vector(NUM_BIFURCATION_SELECT(CARD_TYPE)-1 downto 0);
PORT_GOOD : in std_logic_vector(NUM_PEX(CARD_TYPE)*8-1 downto 0);
Perstn_open : in std_logic_vector(NUM_PEX(CARD_TYPE)*2-1 downto 0); -- @suppress "Unused port: Perstn_open is not used in work.felix_top(structure)"
GTREFCLK_N_IN : in std_logic_vector(GTREFCLKS-1 downto 0);
@@ -311,6 +312,7 @@ architecture structure of felig_top_bnl712 is
signal CLK40_FPGA2LMK_P_link : std_logic;
signal CLK40_FPGA2LMK_N_hk : std_logic;
signal CLK40_FPGA2LMK_P_hk : std_logic;
+ signal leds8 : std_logic_vector(7 downto 0);
COMPONENT ila_downlink IS
PORT (
@@ -624,6 +626,8 @@ begin
signal clk250_out_pcie : std_logic;
signal CPMToWupper : CPMToWupper_type;
signal WupperToCPM : WupperToCPM_type;
+ signal daq_reset: std_logic;
+ signal daq_fifo_flush: std_logic;
begin
g_assign_endpoint0: if pcie_endpoint = 0 generate
@@ -635,6 +639,8 @@ begin
end generate;
aresetn <= not(rst_hw or rst_soft_40);
+ daq_reset <= rst_hw or rst_soft_40;
+ daq_fifo_flush <= rst_soft_40;
pcie0: entity work.wupper
generic map(
@@ -691,7 +697,7 @@ begin
reset_hard => open,
reset_soft => open,
reset_soft_appreg_clk => reset_soft_appreg_clk,
- reset_hw_in => rst_hw,
+ --reset_hw_in => rst_hw,
sys_clk_n => sys_clk_n(pcie_endpoint),
sys_clk_p => sys_clk_p(pcie_endpoint),
sys_reset_n => sys_reset_n,
@@ -773,7 +779,8 @@ begin
clk40 => clk40,
clk365 => '0', --
aclk_out => decoding_aclk,
- aresetn => aresetn,
+ daq_reset => daq_reset, --aresetn => aresetn,
+ daq_fifo_flush => daq_fifo_flush,
m_axis => decoding_axis,
m_axis_tready => decoding_axis_tready,
m_axis_prog_empty => decoding_axis_prog_empty,
@@ -790,6 +797,7 @@ begin
m_axis_aux_tready => decoding_axis_aux_tready,
register_map_control => register_map_40_control,
register_map_decoding_monitor => register_map_decoding_monitor,
+ TTCin => TTC_zero,
--RL added july2023
Interlaken_RX_Data_In => Interlaken_RX_Data(pcie_endpoint*(GBT_NUM/ENDPOINTS) to ((pcie_endpoint+1)*(GBT_NUM/ENDPOINTS))-1),
@@ -887,8 +895,7 @@ begin
clk40_rxusrclk => clk40_rxusrclk,--not in master
RESET_TO_LMK => RESET_TO_LMK_i,--not in master
--
- leds(6 downto 0) => leds,
- leds(7) => open,
+ leds => leds8,
opto_inhibit => opto_inhibit,
--opto_los => OPTO_LOS,--commented in master
register_map_control => global_register_map_control_appreg_clk,
@@ -916,9 +923,10 @@ begin
PORT_GOOD => PORT_GOOD,
SHPC_INT => SHPC_INT(0),
lnk_up => lnk_up,
+ select_bifurcation => select_bifurcation,
RXUSRCLK_IN => RXUSRCLK);
-
+ leds <= leds8(NUM_LEDS(CARD_TYPE)-1 downto 0);
end architecture structure ; -- of felig_top_bnl712
diff --git a/sources/FelixTop/felix_top.vhd b/sources/FelixTop/felix_top.vhd
index 7e4facff6be54c074c8ca16116227ff77a961547..5c5d139181cdf0b378ce5ca0f10fc14495e42b76 100644
--- a/sources/FelixTop/felix_top.vhd
+++ b/sources/FelixTop/felix_top.vhd
@@ -158,7 +158,7 @@ entity felix_top is
PEX_PERSTn : out std_logic_vector(NUM_PEX(CARD_TYPE)-1 downto 0);
PEX_SCL : inout std_logic_vector(NUM_PEX(CARD_TYPE)-1 downto 0);
PEX_SDA : inout std_logic_vector(NUM_PEX(CARD_TYPE)-1 downto 0);
- select_bifurcation : in std_logic_vector(NUM_BIFURCATION_SELECT(CARD_TYPE)-1 downto 0);
+ select_bifurcation : in std_logic_vector(NUM_BIFURCATION_SELECT(CARD_TYPE)-1 downto 0);
PORT_GOOD : in std_logic_vector(NUM_PEX(CARD_TYPE)*8-1 downto 0);
Perstn_open : in std_logic_vector(NUM_PEX(CARD_TYPE)*2-1 downto 0); -- @suppress "Unused port: Perstn_open is not used in work.felix_top(structure)"
GTREFCLK_N_IN : in std_logic_vector(GTREFCLKS-1 downto 0);
diff --git a/sources/FullModeEmulator/FMEmu_FSM_mealy.vhd b/sources/FullModeEmulator/FMEmu_FSM_mealy.vhd
index e2125da867beb6c1cdf398b470094fdaa478bb32..753525ef8b2c39b078ec91ff420c952911c870a5 100644
--- a/sources/FullModeEmulator/FMEmu_FSM_mealy.vhd
+++ b/sources/FullModeEmulator/FMEmu_FSM_mealy.vhd
@@ -222,7 +222,7 @@ begin
RST_RAM <= RST240 or RST_RAM_FSM;
- u7: entity work.Random_gen
+ u7: entity work.Random_gen_fmemu
generic map (
LANE_ID => 1)
port map(
diff --git a/sources/FullModeEmulator/FMEmu_top.vhd b/sources/FullModeEmulator/FMEmu_top.vhd
index 8d61a93076c72274326326f87a78bf0d062a69fd..d7b803a7c7824b82aa9b22ae3387a75ac2ffc56a 100644
--- a/sources/FullModeEmulator/FMEmu_top.vhd
+++ b/sources/FullModeEmulator/FMEmu_top.vhd
@@ -412,7 +412,7 @@ begin
reset_hard => open,
reset_soft => rst_soft_40,
reset_soft_appreg_clk => reset_soft_appreg_clk,
- reset_hw_in => rst_hw,
+ --reset_hw_in => rst_hw,
sys_clk_n => sys_clk_n(pcie_endpoint),
sys_clk_p => sys_clk_p(pcie_endpoint),
sys_reset_n => PCIE_PERSTn,
diff --git a/sources/ItkStrip/lcb_regmap_package.vhd b/sources/ItkStrip/lcb_regmap_package.vhd
index bb2083e84ed32ee0c85387644ef6733f14642a2f..47d4c77382b334033576d2636c3866728248a521 100644
--- a/sources/ItkStrip/lcb_regmap_package.vhd
+++ b/sources/ItkStrip/lcb_regmap_package.vhd
@@ -59,7 +59,8 @@ package lcb_regmap_package is
ABC_MASK_C, -- 0x1B (16 bit)
ABC_MASK_D, -- 0x1C (16 bit)
ABC_MASK_E, -- 0x1D (16 bit)
- ABC_MASK_F -- 0x1E (16 bit)
+ ABC_MASK_F, -- 0x1E (16 bit)
+ PLAYBACK_LOOPS -- 0x1F (16 bit) -- Number of times to loop over trickle mem (0=1=once)
);
@@ -118,6 +119,7 @@ package body lcb_regmap_package is
when ABC_MASK_D => return string'("ABC_MASK_D");
when ABC_MASK_E => return string'("ABC_MASK_E");
when ABC_MASK_F => return string'("ABC_MASK_F");
+ when PLAYBACK_LOOPS => return string'("PLAYBACK_LOOPS");
when others =>
report "Unknown LCB register is referenced" severity FAILURE;
diff --git a/sources/ItkStrip/lcb_wrapper.vhd b/sources/ItkStrip/lcb_wrapper.vhd
index 48ce9a0f072698e2a9687dcb7ab92d94e8bf73c0..7f46db481d01beca556cf5bb71ea26bba094587d 100644
--- a/sources/ItkStrip/lcb_wrapper.vhd
+++ b/sources/ItkStrip/lcb_wrapper.vhd
@@ -266,6 +266,7 @@ begin
rst => rst,
start_pulse_i => trickle_trigger_start,
readout_active_o => open,
+ playback_loops_i => regmap(PLAYBACK_LOOPS),
data_i => trickle_data_i,
valid_i => trickle_valid_i,
ready_o => trickle_ready_o,
diff --git a/sources/ItkStrip/playback_controller.vhd b/sources/ItkStrip/playback_controller.vhd
index 5ac52e97d4da07174cf4d81ec977e45fa73a2eb9..4eea2b758c4ea40473a5b965d400ceb9b094c490 100644
--- a/sources/ItkStrip/playback_controller.vhd
+++ b/sources/ItkStrip/playback_controller.vhd
@@ -46,27 +46,28 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-Library xpm;
+library xpm;
use xpm.vcomponents.all;
use work.strips_package.all;
entity playback_controller is
generic(
- USE_ULTRARAM : boolean
+ USE_ULTRARAM : boolean
);
port(
- clk : in std_logic; -- 40 MHz BC clock
- rst : in std_logic;
- start_pulse_i : in std_logic; -- toggle this input to initiate the readout
- readout_active_o : out std_logic; -- '1' when the readout is in progress
+ clk : in std_logic; -- 40 MHz BC clock
+ rst : in std_logic;
+ start_pulse_i : in std_logic; -- toggle this input to initiate the readout
+ readout_active_o : out std_logic; -- '1' when the readout is in progress
+ playback_loops_i : in std_logic_vector(15 downto 0);
-- trickle memory write interface
-- input data to be saved to the BRAM
data_i : in std_logic_vector(playback_controller_data'range);
- valid_i : in std_logic; -- indicates data_i is valid this clk cycle
- ready_o : out std_logic; -- this module is ready for more data
+ valid_i : in std_logic; -- indicates data_i is valid this clk cycle
+ ready_o : out std_logic; -- this module is ready for more data
-- pulse this signal to load the write_addr of bram from write_addr_start_i
set_write_addr_pulse_i : in std_logic;
-- the memory address that write_ptr of the BRAM will be placed to
@@ -80,28 +81,28 @@ entity playback_controller is
-- trickle configuration memory read interface
-- outputs data read out from BRAM
- data_o : out std_logic_vector(playback_controller_data'range);
+ data_o : out std_logic_vector(playback_controller_data'range);
-- indicates data_o is valid this clk cycle
- valid_o : out std_logic; -- indicates data_o is valid this clk cycle
+ valid_o : out std_logic; -- indicates data_o is valid this clk cycle
-- the receiving side indicates it's ready for more data
- ready_i : in std_logic
+ ready_i : in std_logic
);
end entity playback_controller;
architecture RTL of playback_controller is
-- BRAM signals
- signal wea : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ signal wea : std_logic_vector(0 downto 0);
signal addra : std_logic_vector(playback_controller_address'range);
-- output register buffers
signal readout_active_reg, valid_reg, ready_reg : std_logic;
- signal data_reg : std_logic_vector(playback_controller_data'range);
+ signal data_reg : std_logic_vector(playback_controller_data'range);
-- FIFO mode state
type t_state is (s_init_readout, s_fetch_next, s_wait, s_readout_complete, s_bram_update);
signal state : t_state := s_bram_update;
- function f_mem_type(uram: boolean) return string is
+ function f_mem_type(uram : boolean) return string is
begin
if uram then
return "ultra";
@@ -110,49 +111,80 @@ architecture RTL of playback_controller is
end if;
end function;
+ signal loop_counter : unsigned(15 downto 0) := x"0000";
+ signal loop_active : std_logic;
+ signal loops_prime : unsigned(15 downto 0);
+
begin
data_o <= data_reg;
valid_o <= valid_reg;
readout_active_o <= readout_active_reg;
- ready_o <= ready_reg;
+ ready_o <= ready_reg;
wea <= (others => '1') when (ready_reg = '1' and valid_i = '1' and state = s_bram_update) else (others => '0');
- fsm_state_update : process(clk) is
+
+ loop_active <= '0' when (loop_counter = x"0000") else '1';
+ loops_prime <= x"0001" when (playback_loops_i = x"0000") else unsigned(playback_loops_i);
+
+
+ fsm_state_var_update : process(clk) is
begin
if rising_edge(clk) then
if (rst = '1') then
state <= s_bram_update;
+
+ --wea <= (others => '0');
+ addra <= (others => '0');
+ readout_active_reg <= '0';
+ valid_reg <= '0';
+ ready_reg <= '1';
+ loop_counter <= x"0000";
+
+
else
case state is
when s_init_readout =>
-- prepare to read out data from BRAM addresses
-- read_addr_start_i to read_addr_stop_i (inclusive)
+ state <= s_wait;
if ready_i = '1' then
if read_addr_start_i = read_addr_stop_i then
state <= s_readout_complete;
- else
- state <= s_fetch_next;
end if;
- else
- state <= s_wait;
end if;
+ valid_reg <= '1';
+ readout_active_reg <= '1';
+ ready_reg <= '0';
+
when s_fetch_next =>
+ ready_reg <= '0';
-- fetch the next byte from BRAM
if addra = read_addr_stop_i then
state <= s_readout_complete;
else
if ready_i = '1' and valid_reg = '1' then
+ --if (ready_i = '1') then -- MRMW valid should not control flow IMHO
+ addra <= std_logic_vector(unsigned(addra) + to_unsigned(1, addra'length));
state <= s_fetch_next;
else
state <= s_wait;
end if;
end if;
+ valid_reg <= '1';
+ if addra = read_addr_stop_i then
+ valid_reg <= '0';
+ end if;
+
when s_wait =>
-- wait for the receiving FSM to become ready
+ ready_reg <= '0';
if ready_i = '1' then
+ valid_reg <= '0'; --MRMW: Fix this! valid should not need dropping
+ --to regulate flow, this should be done by ready_i.
+ addra <= std_logic_vector(unsigned(addra) + to_unsigned(1, addra'length));
if addra = read_addr_stop_i then
state <= s_readout_complete;
else
@@ -162,132 +194,98 @@ begin
state <= s_wait;
end if;
+
when s_readout_complete =>
-- BRAM readout is finished
state <= s_bram_update;
+ ready_reg <= '0';
+ valid_reg <= '0';
+ readout_active_reg <= '0';
+ if (loop_active = '1') then
+ loop_counter <= loop_counter - 1;
+ readout_active_reg <= '1';
+ end if;
+
when s_bram_update =>
-- wait for the commands to update BRAM contents
-- (or for another readout to be initiated)
- if start_pulse_i = '1' then
+ if (start_pulse_i = '1') or (loop_active = '1') then
state <= s_init_readout;
else
state <= s_bram_update;
end if;
- when others =>
- report "Invalid FSM state of playback_controller" severity failure;
- end case;
- end if;
- end if;
- end process;
-
- fsm_variable_update : process(clk) is
- begin
- if rising_edge(clk) then
- if (rst = '1') then
- --wea <= (others => '0');
- addra <= (others => '0');
- readout_active_reg <= '0';
- valid_reg <= '0';
- ready_reg <= '1';
- else
- case state is
- when s_init_readout =>
- if ready_i = '1' then
- addra <= std_logic_vector(unsigned(addra) + to_unsigned(1, addra'length));
- end if;
- valid_reg <= '1';
- readout_active_reg <= '1';
- ready_reg <= '0';
-
- when s_fetch_next =>
- ready_reg <= '0';
- if ready_i = '1' and valid_reg = '1' then
- addra <= std_logic_vector(unsigned(addra) + to_unsigned(1, addra'length));
- end if;
- if addra = read_addr_stop_i then
- valid_reg <= '0';
- else
- valid_reg <= '1';
- end if;
-
- when s_wait =>
- ready_reg <= '0';
- if ready_i = '1' then
- valid_reg <= '0';
- addra <= std_logic_vector(unsigned(addra) + to_unsigned(1, addra'length));
- end if;
-
- when s_readout_complete =>
- ready_reg <= '0';
- valid_reg <= '0';
- readout_active_reg <= '0';
-
- when s_bram_update =>
readout_active_reg <= '0';
- ready_reg <= '1';
-
- if set_write_addr_pulse_i = '1' then
- -- move the write pointer
- addra <= write_addr_start_i;
- end if;
-
- if valid_i = '1' then
- -- advance the write pointer
- addra <= std_logic_vector(unsigned(addra) + to_unsigned(1, addra'length));
+ ready_reg <= '1';
+ if (loop_active = '0') then
+ if set_write_addr_pulse_i = '1' then
+ -- move the write pointer
+ addra <= write_addr_start_i;
+ end if;
+ if valid_i = '1' then
+ -- advance the write pointer
+ addra <= std_logic_vector(unsigned(addra) + to_unsigned(1, addra'length));
+ end if;
+ if start_pulse_i = '1' then
+ loop_counter <= loops_prime;
+ addra <= read_addr_start_i;
+ ready_reg <= '0';
+ end if;
+ else -- if (loop_active = '1') then
+ ready_reg <= '0';
+ addra <= read_addr_start_i;
+ readout_active_reg <= '1';
end if;
- if start_pulse_i = '1' then
- addra <= read_addr_start_i;
- ready_reg <= '0';
- end if;
when others =>
report "Invalid FSM state of playback_controller" severity failure;
+
end case;
end if;
end if;
end process;
+
-- BRAM instantiation for FLX712
-- TODO: Versal should use UltraRam with 16 bit address, with 64*8*1024 bits of memory
xpm_memory_spram_inst : xpm_memory_spram
generic map ( -- @suppress "Generic map uses default values. Missing optional actuals: USE_MEM_INIT_MMI, CASCADE_HEIGHT, SIM_ASSERT_CHK, WRITE_PROTECT"
- ADDR_WIDTH_A => playback_controller_address'length, -- DECIMAL
- AUTO_SLEEP_TIME => 0, -- DECIMAL
- BYTE_WRITE_WIDTH_A => 8, -- DECIMAL
- ECC_MODE => "no_ecc", -- String
- MEMORY_INIT_FILE => "none", -- String
- MEMORY_INIT_PARAM => "0", -- String
- MEMORY_OPTIMIZATION => "true", -- String
- MEMORY_PRIMITIVE => f_mem_type(USE_ULTRARAM), -- String
- MEMORY_SIZE => (2**playback_controller_address'length) * 8, -- Number of bits
- MESSAGE_CONTROL => 0, -- DECIMAL
- READ_DATA_WIDTH_A => 8, -- DECIMAL
- READ_LATENCY_A => 1, -- DECIMAL
- READ_RESET_VALUE_A => "0", -- String
- RST_MODE_A => "SYNC", -- String
- USE_MEM_INIT => 1, -- DECIMAL
- WAKEUP_TIME => "disable_sleep", -- String
- WRITE_DATA_WIDTH_A => 8, -- DECIMAL
- WRITE_MODE_A => "write_first" -- String
+ ADDR_WIDTH_A => playback_controller_address'length, -- DECIMAL
+ AUTO_SLEEP_TIME => 0, -- DECIMAL
+ BYTE_WRITE_WIDTH_A => 8, -- DECIMAL
+ ECC_MODE => "no_ecc", -- String
+ MEMORY_INIT_FILE => "none", -- String
+ MEMORY_INIT_PARAM => "0", -- String
+ MEMORY_OPTIMIZATION => "true", -- String
+ MEMORY_PRIMITIVE => f_mem_type(USE_ULTRARAM), -- String
+ MEMORY_SIZE => (2**playback_controller_address'length) * 8, -- Number of bits
+ MESSAGE_CONTROL => 0, -- DECIMAL
+ READ_DATA_WIDTH_A => 8, -- DECIMAL
+ READ_LATENCY_A => 1, -- DECIMAL
+ READ_RESET_VALUE_A => "0", -- String
+ RST_MODE_A => "SYNC", -- String
+ USE_MEM_INIT => 1, -- DECIMAL
+ WAKEUP_TIME => "disable_sleep", -- String
+ WRITE_DATA_WIDTH_A => 8, -- DECIMAL
+ WRITE_MODE_A => "write_first" -- String
)
port map (
- sleep => '0', -- 1-bit input: sleep signal to enable the dynamic power saving feature.
- clka => clk, -- 1-bit input: Clock signal for port A.
- rsta => '0', -- 1-bit input: Reset signal for the final port A output register
- ena => '1', -- 1-bit input: Memory enable signal for port A. Must be high on clock-- cycles when read or write operations are initiated. Pipelined-- internally.
- regcea => '1', -- 1-bit input: Clock Enable for the last register stage on the output
- wea => wea, -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector-- for port A input data port dina. 1 bit wide when word-wide writes-- are used. In byte-wide write configurations, each bit controls the-- writing one byte of dina to address addra. For example, to-- synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A-- is 32, wea would be 4'b0010.
- addra => addra, -- ADDR_WIDTH_A-bit input: Address for port A write and read operations.
- dina => data_i, -- WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
- injectsbiterra => '0', -- 1-bit input: Controls single bit error injection on input data when
- injectdbiterra => '0', -- 1-bit input: Controls double bit error injection on input data when
- douta => data_reg, -- READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
- sbiterra => open, -- 1-bit output: Status signal to indicate single bit error occurrence
- dbiterra => open -- 1-bit output: Status signal to indicate double bit error occurrence
+ sleep => '0', -- 1-bit input: sleep signal to enable the dynamic power saving feature.
+ clka => clk, -- 1-bit input: Clock signal for port A.
+ rsta => '0', -- 1-bit input: Reset signal for the final port A output register
+ ena => '1', -- 1-bit input: Memory enable signal for port A. Must be high on clock-- cycles when read or write operations are initiated. Pipelined-- internally.
+ regcea => '1', -- 1-bit input: Clock Enable for the last register stage on the output
+ wea => wea, -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector-- for port A input data port dina. 1 bit wide when word-wide writes-- are used. In byte-wide write configurations, each bit controls the-- writing one byte of dina to address addra. For example, to-- synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A-- is 32, wea would be 4'b0010.
+ addra => addra, -- ADDR_WIDTH_A-bit input: Address for port A write and read operations.
+ dina => data_i, -- WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
+ injectsbiterra => '0', -- 1-bit input: Controls single bit error injection on input data when
+ injectdbiterra => '0', -- 1-bit input: Controls double bit error injection on input data when
+ douta => data_reg, -- READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
+ sbiterra => open, -- 1-bit output: Status signal to indicate single bit error occurrence
+ dbiterra => open -- 1-bit output: Status signal to indicate double bit error occurrence
);
diff --git a/sources/ItkStrip/strips_package.vhd b/sources/ItkStrip/strips_package.vhd
index 054bc1a0f5a80f792da45aabf75470a25c231db6..8774e400d6d541da9a9b8d354a6b644cfc978d11 100644
--- a/sources/ItkStrip/strips_package.vhd
+++ b/sources/ItkStrip/strips_package.vhd
@@ -53,7 +53,8 @@ package strips_package is
constant L0tag_bits : std_logic_vector(6 downto 0) := (others => '0');
-- playback controller address and data width
- constant playback_controller_address : std_logic_vector(12 downto 0) := (others => '0'); --8 kB of trickle memory
+ constant playback_controller_address : std_logic_vector(11 downto 0) := (others => '0'); --4 kB of trickle memory
+ --constant playback_controller_address : std_logic_vector(12 downto 0) := (others => '0'); --8 kB of trickle memory
--constant playback_controller_address : std_logic_vector(13 downto 0) := (others => '0'); --16 kB of trickle memory
constant playback_controller_data : std_logic_vector(7 downto 0) := (others => '0');
diff --git a/sources/PRandomDGen/randomd_gen.vhd b/sources/PRandomDGen/randomd_gen_fmemu.vhd
similarity index 98%
rename from sources/PRandomDGen/randomd_gen.vhd
rename to sources/PRandomDGen/randomd_gen_fmemu.vhd
index 75fa4ca47ef7678d6bed3ea2ad7970369b50398c..00a18187836d6bf8193990bf4077e871e1fdea22 100644
--- a/sources/PRandomDGen/randomd_gen.vhd
+++ b/sources/PRandomDGen/randomd_gen_fmemu.vhd
@@ -33,7 +33,7 @@ library ieee, UNISIM;
use ieee.std_logic_1164.all;
use work.pcie_package.all;
-entity Random_gen is
+entity Random_gen_fmemu is
generic (
LANE_ID : integer := 0
);
@@ -46,9 +46,9 @@ entity Random_gen is
rg_enb : in std_logic; -- Active high generate one random value per pulse(clk240 clock used).
rg_doutb : out std_logic_vector(15 downto 0) -- RDG output(clk240)
);
-end entity Random_gen;
+end entity Random_gen_fmemu;
-architecture rtl of Random_gen is
+architecture rtl of Random_gen_fmemu is
constant wd : integer := 10;
signal rg_temp : std_logic_vector(wd - 1 downto 0):= (wd - 1 => '1', others => '0');
diff --git a/sources/Xoff_decoder/8b10_dec.vhd b/sources/Xoff_decoder/8b10_dec_fmemu.vhd
similarity index 98%
rename from sources/Xoff_decoder/8b10_dec.vhd
rename to sources/Xoff_decoder/8b10_dec_fmemu.vhd
index 01223be6f6a3fe0a4011f2033f50433e1bec7f90..f26c27ca908acc3ca0b6e3e5dc2fbaf38469da42 100644
--- a/sources/Xoff_decoder/8b10_dec.vhd
+++ b/sources/Xoff_decoder/8b10_dec_fmemu.vhd
@@ -73,7 +73,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
--! 8b/10b Decoder by Critia Computer, Inc.
-entity xoff_dec_8b10b is
+entity xoff_dec_8b10b_fmemu is
port(
RESET : in std_logic ; -- Global asynchronous reset (AH) -- syncronous now (13 JUL 2015)
RBYTECLK : in std_logic ; -- Master synchronous receive byte clock
@@ -82,9 +82,9 @@ entity xoff_dec_8b10b is
KO : out std_logic ; -- Control (K) character indicator (AH)
HO, GO, FO, EO, DO, CO, BO, AO : out std_logic -- Decoded out (MS..LS)
);
-end xoff_dec_8b10b;
+end xoff_dec_8b10b_fmemu;
-architecture behavioral of xoff_dec_8b10b is
+architecture behavioral of xoff_dec_8b10b_fmemu is
-- Signals to tie things together
signal ANEB, CNED, EEI, P13, P22, P31 : std_logic := '0'; -- Figure 10 Signals
diff --git a/sources/Xoff_decoder/8b10_dec_wrap.vhd b/sources/Xoff_decoder/8b10_dec_wrap_fmemu.vhd
similarity index 86%
rename from sources/Xoff_decoder/8b10_dec_wrap.vhd
rename to sources/Xoff_decoder/8b10_dec_wrap_fmemu.vhd
index eb174df9f45a3f429217fa67d2a936123fd3ec45..271e61b9e949efb54f05b0359f5093a879ffa32e 100644
--- a/sources/Xoff_decoder/8b10_dec_wrap.vhd
+++ b/sources/Xoff_decoder/8b10_dec_wrap_fmemu.vhd
@@ -32,7 +32,7 @@ library IEEE;
use work.centralRouter_package.all;
--! a wrap for 8b10b decoder
-entity dec_8b10_wrap is
+entity dec_8b10_wrap_fmemu is
port (
RESET : in std_logic;
RBYTECLK : in std_logic;
@@ -41,37 +41,13 @@ entity dec_8b10_wrap is
ISK : out std_logic_vector (1 downto 0);
BUSY : out std_logic
);
-end dec_8b10_wrap;
+end dec_8b10_wrap_fmemu;
-architecture Behavioral of dec_8b10_wrap is
+architecture Behavioral of dec_8b10_wrap_fmemu is
----------------------------------
----------------------------------
- COMPONENT xoff_dec_8b10b
- PORT(
- RESET : IN std_logic;
- RBYTECLK : IN std_logic;
- AI : IN std_logic;
- BI : IN std_logic;
- CI : IN std_logic;
- DI : IN std_logic;
- EI : IN std_logic;
- II : IN std_logic;
- FI : IN std_logic;
- GI : IN std_logic;
- HI : IN std_logic;
- JI : IN std_logic;
- KO : OUT std_logic;
- HO : OUT std_logic;
- GO : OUT std_logic;
- FO : OUT std_logic;
- EO : OUT std_logic;
- DO : OUT std_logic;
- CO : OUT std_logic;
- BO : OUT std_logic;
- AO : OUT std_logic
- );
- END COMPONENT;
+
----------------------------------
----------------------------------
@@ -90,7 +66,7 @@ architecture Behavioral of dec_8b10_wrap is
begin
-- 8b10b decoder
- dec_8b10b_INST: xoff_dec_8b10b
+ dec_8b10b_INST: entity work.xoff_dec_8b10b_fmemu
PORT MAP(
RESET => RESET,
RBYTECLK => RBYTECLK,
diff --git a/sources/Xoff_decoder/Xoff_decoder_top.vhd b/sources/Xoff_decoder/Xoff_decoder_top.vhd
index a400ef8fa7103fb00a5e4c4261d37a37a4d89db4..b0a8d7047af0594825e1282ba004dca06c043116 100644
--- a/sources/Xoff_decoder/Xoff_decoder_top.vhd
+++ b/sources/Xoff_decoder/Xoff_decoder_top.vhd
@@ -103,7 +103,7 @@ begin
end if;
end process;
- dec_8b10: entity work.dec_8b10_wrap
+ dec_8b10: entity work.dec_8b10_wrap_fmemu
port map(
RESET => Reset,
RBYTECLK => Clk,
diff --git a/sources/decoding/ByteToAxiStream.vhd b/sources/decoding/ByteToAxiStream.vhd
index 7dc0f71f1324649a35644c46a03d2ad233909d1f..caa2031cefa2056572f99dc5c039fa950476b3fa 100644
--- a/sources/decoding/ByteToAxiStream.vhd
+++ b/sources/decoding/ByteToAxiStream.vhd
@@ -76,6 +76,7 @@ entity ByteToAxiStream is
EOB : in std_logic_vector(BYTES-1 downto 0); --Add to tuser
TruncateIn : in std_logic_vector(BYTES-1 downto 0); --Add to tuser
CodingErrorIn : in std_logic;
+ FramingErrorIn : in std_logic;
m_axis : out axis_32_type; --FIFO read port (axi stream)
m_axis_tready : in std_logic; --FIFO read tready (axi stream)
m_axis_aclk : in std_logic; --FIFO read clock (axi stream)
@@ -90,6 +91,7 @@ architecture Behavioral of ByteToAxiStream is
signal s_axis_tready: std_logic;
signal Truncate: std_logic;
+ signal FramingError: std_logic;
--signal ByteIndex: integer range 0 to 3;
signal EnableIn_aclk: std_logic;
@@ -99,102 +101,6 @@ architecture Behavioral of ByteToAxiStream is
begin
- --g_onebyte: if BYTES = 1 generate
- -- signal DataInValid_p1: std_logic;
- -- signal DataIn_p1: std_logic_vector(7 downto 0);
- --begin
- --toaxis_proc: process(s_axis_aresetn, clk40)
- -- variable ElinkBusy_v: std_logic;
- -- variable ClearElinkBusy_v: std_logic;
- -- variable FramingError_v : std_logic;
- -- variable TruncateHandled : std_logic;
- --begin
- -- if s_axis_aresetn = '0' then
- -- s_axis.tdata <= (others => '0');
- -- s_axis.tvalid <= '0';
- -- s_axis.tlast <= '0';
- -- s_axis.tkeep <= "0000";
- -- s_axis.tuser <= "0000";
- -- Truncate <= '0';
- -- ByteIndex <= 0;
- -- TruncateHandled := '0';
- -- ElinkBusy_v := '0';
- -- FramingError_v := '0';
- -- DataInValid_p1 <= '0';
- -- ChunkContainsData <= '0';
- -- elsif rising_edge(clk40) then
- -- if TruncateIn(0) = '1' then
- -- Truncate <= '1';
- -- end if;
- -- if SOB(0) = '1' then
- -- ElinkBusy_v := '1';
- -- end if;
- -- if EOB(0) = '1' then
- -- ClearElinkBusy_v := '1';
- -- end if;
- -- if CodingErrorIn = '1' then
- -- FramingError_v := '1';
- -- end if;
- -- if s_axis_tready = '1' then
- -- s_axis.tvalid <= '0';
- -- if GearboxValid = '1' then
- -- s_axis.tlast <= '0';
- -- s_axis.tkeep <= "1111";
- -- s_axis.tuser <= "0000";
- -- s_axis.tdata(ByteIndex*8+7 downto ByteIndex*8) <= DataIn(7 downto 0);
- -- if DataInValid(0) = '1' then
- -- ChunkContainsData <= '1';
- -- if ByteIndex < 3 then
- -- ByteIndex <= ByteIndex + 1;
- -- else
- -- ByteIndex <= 0;
- -- s_axis.tvalid <= '1';
- -- end if;
- -- end if;
- --
- -- if (EOP(0) = '1' or Truncate = '1') and ChunkContainsData = '1' then
- -- ChunkContainsData <= '0';
- -- if Truncate = '1' then
- -- if TruncateHandled = '0' then
- -- TruncateHandled := '1';
- -- s_axis.tvalid <= '1';
- -- else
- -- s_axis.tvalid <= '0';
- -- end if;
- -- if EOP(0) = '1' then
- -- Truncate <= '0';
- -- TruncateHandled := '0';
- -- end if;
- -- elsif EOP(0) = '1' then
- -- s_axis.tvalid <= '1';
- -- end if;
- -- s_axis.tlast <= '1';
- -- s_axis.tuser(3) <= Truncate;
- -- s_axis.tuser(2) <= ElinkBusy_v;
- -- s_axis.tuser(1) <= FramingError_v;
- -- s_axis.tuser(0) <= '0'; --CRC not used in this mode.
- -- s_axis.tkeep <= (others => '0');
- -- for i in 0 to 3 loop
- -- if i < ByteIndex or ByteIndex = 0 then
- -- s_axis.tkeep(i) <= '1';
- -- end if;
- -- end loop;
- -- if ClearElinkBusy_v = '1' then
- -- ElinkBusy_v := '0';
- -- ClearElinkBusy_v := '0';
- -- end if;
- -- FramingError_v := '0';
- -- ByteIndex <= 0; --Start a fresh 32b word for the next packet.
- -- end if;
- -- end if;
- -- else --tready = 0
- -- if DataInValid(0) = '1' then
- -- Truncate <= '1';
- -- end if;
- -- end if;
- -- end if;
- --end process;
- --end generate;
g_multibyte: if BYTES >= 1 generate
@@ -220,7 +126,7 @@ begin
variable shiftKeep_v : std_logic_vector(3 downto 0);
variable ElinkBusy_v: std_logic;
variable ClearElinkBusy_v: std_logic;
- variable FramingError_v : std_logic;
+ variable CodingError_v : std_logic;
variable outputNow, outputNext : std_logic;
variable maxBytes: integer range 0 to BYTES-1;
variable ChunkContainsData_v : std_logic;
@@ -230,7 +136,7 @@ begin
shiftData_v := (others => '0');
ElinkBusy_v := '0';
ClearElinkBusy_v := '0';
- FramingError_v := '0';
+ CodingError_v := '0';
s_axis_p0.tdata <= x"00000000";
s_axis_p0.tkeep <= x"0";
s_axis_p0.tuser <= x"0";
@@ -248,6 +154,7 @@ begin
s_axis_p2.tvalid <= '0';
Truncate <= '0';
+ FramingError <= '0';
ChunkContainsData_v := '0';
TruncateHandled <= '0';
outputNow := '0';
@@ -272,9 +179,12 @@ begin
if Truncate = '0' then
for i in 0 to BYTES-1 loop
- if TruncateIn(i) = '1' then
+ if (TruncateIn(i) = '1' OR FramingErrorIn = '1') then
Truncate <= '1';
TruncateHandled <= '0';
+ if FramingErrorIn = '1' then
+ FramingError <= '1';
+ end if;
end if;
outputNow := '0';
outputNext := '0';
@@ -284,8 +194,8 @@ begin
if EOB(i) = '1' then
ClearElinkBusy_v := '1';
end if;
- if CodingErrorIn = '1' then
- FramingError_v := '1';
+ if (CodingErrorIn = '1') then
+ CodingError_v := '1';
end if;
if DataInValid(i) = '1' then
shiftData_v(23 downto 0) := shiftData_v(31 downto 8); --Shift 1 byte
@@ -337,10 +247,10 @@ begin
s_axis_p1.tvalid <= '1';
s_axis_p1.tkeep <= shiftKeep_v;
s_axis_p1.tdata <= shiftData_v;
- s_axis_p1.tuser <= Truncate & ElinkBusy_v & FramingError_v & '0';
+ s_axis_p1.tuser <= Truncate & ElinkBusy_v & (CodingError_v or FramingError) & '0';
shiftKeep_v := "0000";
shiftData_v := x"00000000";
- FramingError_v := '0';
+ CodingError_v := '0';
end if;
if shiftKeep_v(0) = '1' and i = maxBytes then --If we have our shift register filled somehwere in the middle, output immediately.
outputNext := '1';
@@ -349,23 +259,24 @@ begin
s_axis_p0.tvalid <= '1';
s_axis_p0.tkeep <= shiftKeep_v;
s_axis_p0.tdata <= shiftData_v;
- s_axis_p0.tuser <= Truncate & ElinkBusy_v & FramingError_v & '0';
+ s_axis_p0.tuser <= Truncate & ElinkBusy_v & (CodingError_v or FramingError) & '0';
shiftKeep_v := "0000";
shiftData_v := x"00000000";
if ClearElinkBusy_v = '1' then
ElinkBusy_v := '0';
end if;
- FramingError_v := '0';
+ CodingError_v := '0';
end if;
end loop;
else --Truncate = '1'
s_axis_p1.tdata <= shiftData_v;
s_axis_p1.tvalid <= (not TruncateHandled);
s_axis_p1.tlast <= '1';
- s_axis_p1.tuser <= Truncate & ElinkBusy_v & FramingError_v & '0';
+ s_axis_p1.tuser <= Truncate & ElinkBusy_v & (CodingError_v or FramingError) & '0';
TruncateHandled <= '1';
if (DataInValid = (DataInValid'range => '0')) and (TruncateHandled = '1') then --If no data is coming in, we can safely go back to normal operation, and we are sure we are not in the middle of a chunk.
Truncate <= '0';
+ FramingError <= '0';
TruncateHandled <= '0';
shiftKeep_v := "0000";
shiftData_v := x"00000000";
diff --git a/sources/decoding/DecEgroup_8b10b.vhd b/sources/decoding/DecEgroup_8b10b.vhd
index 5450c835aabbdff08faabfc48cec0b96fb03ce90..c03ffe8742fb735e1028bd1a281156cc243ad496 100644
--- a/sources/decoding/DecEgroup_8b10b.vhd
+++ b/sources/decoding/DecEgroup_8b10b.vhd
@@ -65,6 +65,7 @@ architecture struct of DecEgroup_8b10b is
signal Enable : std_logic_vector(3 downto 0);
signal DataGB : std_logic_vector(39 downto 0);
signal DataGBValid : std_logic_vector( 3 downto 0);
+ signal DataGBValid_p1 : std_logic_vector( 3 downto 0);
signal DataGB_32b : std_logic_vector(39 downto 0);
signal DataGB_32bValid : std_logic;
@@ -124,7 +125,9 @@ architecture struct of DecEgroup_8b10b is
signal ElinkAligned_s : std_logic_vector(3 downto 0);
signal CodingError : std_logic_vector(3 downto 0);
signal DisparityError : std_logic_vector(3 downto 0); -- @suppress "signal DisparityError is never read"
+ signal FramingError : std_logic_vector(3 downto 0);
signal CodingError_0, CodingError_1, CodingError_2, CodingError_3: std_logic;
+ signal FramingError_0, FramingError_1, FramingError_2, FramingError_3: std_logic;
signal ByteToAxiStreamGearboxValid : std_logic_vector(3 downto 0);
@@ -138,6 +141,7 @@ architecture struct of DecEgroup_8b10b is
signal DecoderAligned8b10b_out : std_logic_vector(3 downto 0);
signal CodingError8b10b : std_logic_vector(3 downto 0);
signal DisparityError8b10b : std_logic_vector(3 downto 0);
+ signal FramingError8b10b : std_logic_vector(3 downto 0);
signal ISK_SOC_in : std_logic_vector(3 downto 0);
signal ISK_SOC_out : std_logic_vector(3 downto 0);
signal ISK_SOC_out_p1 : std_logic_vector(3 downto 0);
@@ -223,8 +227,9 @@ begin
DecoderLinkSharing_proc: process( clk40 )
begin
if rising_edge( clk40 ) then
+ DataGBValid_p1 <= DataGBValid;
for i in 0 to 3 loop
- if DataGBValid(i) = '1' then
+ if DataGBValid_p1(i) = '1' then --Gearbox valid, but 1 clock later because the data passes through the decoder.
ISK_SOC_out_p1(i) <= ISK_SOC_out(i);
ISK_EOC_out_p1(i) <= ISK_EOC_out(i);
ISK_DelimiterB_out_p1(i) <= ISK_DelimiterB_out(i); -- the 16 and 8 bit decoders need 1 cycle delay on the second character on the (max. length 3) of the delimiter
@@ -493,12 +498,13 @@ begin
DecoderAligned_in => DecoderAligned8b10b_in(i),
CodingError => CodingError8b10b(i),
DisparityError => DisparityError8b10b(i),
+ FramingError => FramingError8b10b(i),
dispout => dispout(i),
dispin => dispin(i),
- ISK_SOC_in => ISK_SOC_in(i),
- ISK_SOC_out => ISK_SOC_out(i),
- ISK_EOC_in => ISK_EOC_in(i),
- ISK_EOC_out => ISK_EOC_out(i),
+ Char_SOC_in => ISK_SOC_in(i),
+ Char_SOC_out => ISK_SOC_out(i),
+ Char_EOC_in => ISK_EOC_in(i),
+ Char_EOC_out => ISK_EOC_out(i),
ISK_DelimiterA_in => ISK_DelimiterA_in(i),
ISK_DelimiterB_in => ISK_DelimiterB_in(i),
ISK_DelimiterA_out => ISK_DelimiterA_out(i),
@@ -518,16 +524,16 @@ begin
elsif rising_edge(clk40) then
--rigorous error counting
errs := DecodingErrors_s;
- if(errs /= x"FFFF_FFFF" AND (CodingError8b10b(0) = '1' OR DisparityError8b10b(0) = '1')) then
+ if(errs /= x"FFFF_FFFF" AND (CodingError8b10b(0) = '1' OR DisparityError8b10b(0) = '1' OR FramingError8b10b(0) = '1')) then
errs := errs + x"1";
end if;
- if(errs /= x"FFFF_FFFF" AND (CodingError8b10b(1) = '1' OR DisparityError8b10b(1) = '1')) then
+ if(errs /= x"FFFF_FFFF" AND (CodingError8b10b(1) = '1' OR DisparityError8b10b(1) = '1' OR FramingError8b10b(1) = '1')) then
errs := errs + x"1";
end if;
- if(errs /= x"FFFF_FFFF" AND (CodingError8b10b(2) = '1' OR DisparityError8b10b(2) = '1')) then
+ if(errs /= x"FFFF_FFFF" AND (CodingError8b10b(2) = '1' OR DisparityError8b10b(2) = '1' OR FramingError8b10b(2) = '1')) then
errs := errs + x"1";
end if;
- if(errs /= x"FFFF_FFFF" AND (CodingError8b10b(3) = '1' OR DisparityError8b10b(3) = '1')) then
+ if(errs /= x"FFFF_FFFF" AND (CodingError8b10b(3) = '1' OR DisparityError8b10b(3) = '1' OR FramingError8b10b(3) = '1')) then
errs := errs + x"1";
end if;
DecodingErrors_s <= errs;
@@ -543,7 +549,7 @@ begin
encodingmux: process(DataOut8b10b, DataOutValid8b10b, EOP8b10b,
ElinkSOB8b10b, ElinkEOB8b10b, DecoderAligned8b10b_out,
- CodingError8b10b, DisparityError8b10b,
+ CodingError8b10b, DisparityError8b10b, FramingError8b10b,
DataIn, LinkAligned,
PathEncoding, ElinkWidth, EnableIn,
DataGB_32bValid_p1, DataGB_16bValid_p1, DataGB_8b1Valid_p1, DataGB_8b2Valid_p1, DataValid, DataValid(0))
@@ -576,6 +582,7 @@ begin
DecoderAligned(i) <= '0';
CodingError(i) <= '0';
DisparityError(i) <= '0';
+ FramingError(i) <= '0';
ByteToAxiStreamGearboxValid(i) <= '0';
if ME(i*4+3 downto i*4) = "0000" then --No Encoding / Direct mode, take data directly from Egroup input bits
if ElinkWidth = "100" then --32-bit E-Links, use Enable bit 0
@@ -595,6 +602,7 @@ begin
DecoderAligned(i) <= LinkAligned;
CodingError(i) <= '0';
DisparityError(i) <= '0';
+ FramingError(i) <= '0';
end if;
if ME(i*4+3 downto i*4) = "0001" then --8b10b encoding, take data from decoders
Data(8*i+7 downto 8*i) <= DataOut8b10b(8*i+7 downto 8*i);
@@ -605,6 +613,7 @@ begin
DecoderAligned(i) <= DecoderAligned8b10b_out(i);
CodingError(i) <= CodingError8b10b(i);
DisparityError(i) <= DisparityError8b10b(i);
+ FramingError(i) <= FramingError8b10b(i);
case ElinkWidth is
when "010" => --8 bit E-Link
ByteToAxiStreamGearboxValid(0) <= DataGB_32bValid_p1;
@@ -631,7 +640,7 @@ begin
end loop;
end process;
- datamux: process(ElinkWidth, Data, DataValid, EOP, ElinkEOB, ElinkSOB, DecoderAligned, CodingError)
+ datamux: process(ElinkWidth, Data, DataValid, EOP, ElinkEOB, ElinkSOB, DecoderAligned, CodingError, FramingError)
begin
case ElinkWidth is
when "010" => --8 bit E-Link
@@ -656,10 +665,14 @@ begin
DataValid_2 <= "0" & DataValid(2);
DataValid_3 <= DataValid(3 downto 3);
ElinkAligned_s <= DecoderAligned;
- CodingError_0 <= CodingError(0) or CodingError(1);
+ CodingError_0 <= CodingError(0) or CodingError(1);
CodingError_1 <= '0';
CodingError_2 <= CodingError(2) or CodingError(3);
CodingError_3 <= '0';
+ FramingError_0 <= FramingError(0) or FramingError(1);
+ FramingError_1 <= '0';
+ FramingError_2 <= FramingError(2) or FramingError(3);
+ FramingError_3 <= '0';
when "011" =>
Data_0 <= x"0000" & Data(15 downto 0);
Data_1 <= x"00";
@@ -686,6 +699,11 @@ begin
CodingError_1 <= CodingError(1);
CodingError_2 <= CodingError(2);
CodingError_3 <= CodingError(3);
+
+ FramingError_0 <= FramingError(0);
+ FramingError_1 <= FramingError(1);
+ FramingError_2 <= FramingError(2);
+ FramingError_3 <= FramingError(3);
when "100" =>
Data_0 <= Data(31 downto 0);
Data_1 <= x"00";
@@ -715,6 +733,11 @@ begin
CodingError_1 <= '0';
CodingError_2 <= '0';
CodingError_3 <= '0';
+
+ FramingError_0 <= FramingError(0) or FramingError(1) or FramingError(2) or FramingError(3);
+ FramingError_1 <= '0';
+ FramingError_2 <= '0';
+ FramingError_3 <= '0';
when others =>
Data_0 <= (others => '0');
Data_1 <= (others => '0');
@@ -737,10 +760,15 @@ begin
DataValid_2 <= "00";
DataValid_3 <= "0";
ElinkAligned_s <= "0000";
- CodingError_0 <= '0';
- CodingError_1 <= '0';
- CodingError_2 <= '0';
- CodingError_3 <= '0';
+ CodingError_0 <= '0';
+ CodingError_1 <= '0';
+ CodingError_2 <= '0';
+ CodingError_3 <= '0';
+
+ FramingError_0 <= '0';
+ FramingError_1 <= '0';
+ FramingError_2 <= '0';
+ FramingError_3 <= '0';
end case;
end process;
@@ -790,6 +818,7 @@ begin
EOB => EOB_0,
TruncateIn => Truncate,
CodingErrorIn => CodingError_0,
+ FramingErrorIn => FramingError_0,
m_axis => m_axis(0),
m_axis_tready => m_axis_tready(0),
m_axis_aclk => m_axis_aclk,
@@ -821,6 +850,7 @@ begin
EOB => EOB_1,
TruncateIn => Truncate(1 downto 1),
CodingErrorIn => CodingError_1,
+ FramingErrorIn => FramingError_1,
m_axis => m_axis(1),
m_axis_tready => m_axis_tready(1),
m_axis_aclk => m_axis_aclk,
@@ -853,6 +883,7 @@ begin
EOB => EOB_2,
TruncateIn => Truncate(3 downto 2),
CodingErrorIn => CodingError_2,
+ FramingErrorIn => FramingError_2,
m_axis => m_axis(2),
m_axis_tready => m_axis_tready(2),
m_axis_aclk => m_axis_aclk,
@@ -885,6 +916,7 @@ begin
EOB => EOB_3,
TruncateIn => Truncate(3 downto 3),
CodingErrorIn => CodingError_3,
+ FramingErrorIn => FramingError_3,
m_axis => m_axis(3),
m_axis_tready => m_axis_tready(3),
m_axis_aclk => m_axis_aclk,
diff --git a/sources/decoding/Decoder8b10b.vhd b/sources/decoding/Decoder8b10b.vhd
index 32432715c0cd4426cdbcd52ab831f0d47598c0cf..172bd6c9998d9b367787c3dc376d86e63fcaf73f 100644
--- a/sources/decoding/Decoder8b10b.vhd
+++ b/sources/decoding/Decoder8b10b.vhd
@@ -58,13 +58,14 @@ entity Decoder8b10b is
DecoderAligned_out : out std_logic; --Indicator that the 8b10b decoder was successfully aligned.
DecoderAligned_in : in std_logic; -- Indicated that one of the other linked decoders has successfully aligned
CodingError : out std_logic;
+ FramingError : out std_logic; -- signals a missing end of chunk charcater or start of chunk character or both
DisparityError : out std_logic;
dispout : out std_logic; --Disparity in/out: Loop back through register to same decoder, or to the next when using parallel decoders
dispin : in std_logic; --Disparity in/out: Loop back through register to same decoder, or to the next when using parallel decoders
- ISK_SOC_in : in std_logic; --Handshake lines to parallel decoders
- ISK_SOC_out : out std_logic; --Handshake lines to parallel decoders
- ISK_EOC_in : in std_logic; --Handshake lines to parallel decoders
- ISK_EOC_out : out std_logic; --Handshake lines to parallel decoders
+ Char_SOC_in : in std_logic; --Handshake lines to parallel decoders
+ Char_SOC_out : out std_logic; --Handshake lines to parallel decoders
+ Char_EOC_in : in std_logic; --Handshake lines to parallel decoders
+ Char_EOC_out : out std_logic; --Handshake lines to parallel decoders
ISK_DelimiterA_in : in std_logic; --Handshake lines to parallel decoders
ISK_DelimiterB_in : in std_logic; --Handshake lines to parallel decoders
ISK_DelimiterA_out : out std_logic; --Handshake lines to parallel decoders
@@ -76,16 +77,13 @@ entity Decoder8b10b is
end Decoder8b10b;
architecture Behavioral of Decoder8b10b is
-
signal DecoderAligned_s: std_logic;
-
-
signal decoder_out : std_logic_vector(7 downto 0) := (others => '0');--Output of 8b10b decoder
--Second pipeline to align EOP with last output of chunk
signal CharIsK : std_logic; --Output of 8b10b decoder
signal ISK_comma : std_logic;
signal ISK_SOC, ISK_EOC: std_logic; -- FIXME why CHAR_EOC and not ISK_EOC?
- signal Char_EOC, Char_SOB, Char_EOB: std_logic;
+ signal Char_SOC, Char_EOC, Char_SOB, Char_EOB: std_logic;
--signal DataInValid_p1 : std_logic; --One pipeline delayed synchronous with 8b10b decoder.
signal decoder_out_valid : std_logic; --One pipeline delayed synchronous with 8b10b decoder.
signal decoder_out_valid_no_ReceivingState : std_logic; --One pipeline delayed synchronous with 8b10b decoder.
@@ -95,6 +93,8 @@ architecture Behavioral of Decoder8b10b is
signal disp_err, code_err: std_logic;
signal DecoderAligned_4s: std_logic;
signal DecoderAligned_pipe: std_logic_vector(4 downto 0);
+
+
begin
GBT_mode: if (GENERATE_FEI4B = false and GENERATE_LCB_ENC = false) generate
@@ -102,35 +102,35 @@ begin
begin
if HGTD_ALTIROC_DECODING = '0' then --NSW-like
ISK_comma <= '1' when (DataIn = COMMAp or DataIn = COMMAn) else '0';
- ISK_SOC <= '1' when (DataIn = SOCp or DataIn = SOCn) else '0';
+ --ISK_SOC <= '1' when (DataIn = SOCp or DataIn = SOCn) else '0';
ISK_EOC <= '1' when (DataIn = EOCp or DataIn = EOCn) else '0';
--Char_comma <= '1' when (decoder_out = Kchar_comma and CharIsK = '1' and decoder_out_valid = '1') else '0';
- --Char_SOC <= '1' when (decoder_out = Kchar_sop and CharIsK = '1' and decoder_out_valid = '1') else '0';
- Char_EOC <= '1' when (decoder_out = Kchar_eop and CharIsK = '1' and decoder_out_valid = '1') else '0';
+ Char_SOC <= '1' when (decoder_out = Kchar_sop and CharIsK = '1' and decoder_out_valid_no_ReceivingState = '1') else '0';
+ Char_EOC <= '1' when (decoder_out = Kchar_eop and CharIsK = '1' and decoder_out_valid_no_ReceivingState = '1') else '0';
Char_SOB <= '1' when (decoder_out = Kchar_sob and CharIsK = '1' and decoder_out_valid_no_ReceivingState = '1') else '0';
Char_EOB <= '1' when (decoder_out = Kchar_eob and CharIsK = '1' and decoder_out_valid_no_ReceivingState = '1') else '0';
else --HGTD Altiroc
-- DataIn = 10 bits, use both positive and negative options; note that decoder_out is delayed by 1 cycle (with DataValid active) from DataIn
-- K.28.5 188 BC 1011 1100 10bN 00 1111 1010 10bP 11 0000 0101
-- K.28.7 252 FC 1111 1100 10bN 00 1111 1000 10bP 11 0000 0111
- ISK_comma <= '1' when (DataIn = HGTD_COMMAn or DataIn = HGTD_COMMAp) else '0';
- ISK_SOC <= '1' when ( CharIsK_in = '1' and not ( ISK_comma = '1' or ISK_EOC = '1' ) ) else '0';
- ISK_EOC <= '1' when ((DataIn = HGTD_EOPn or DataIn = HGTD_EOPp)) else '0';
- Char_EOC <= '1' when (decoder_out = HGTD_Kchar_eop) and (CharIsK = '1') and (CharIsK_in = '0') else '0';
- --Char_SOC <= '0';
- Char_SOB <= '0';
- Char_EOB <= '0';
+ ISK_comma <= '1' when (DataIn = HGTD_COMMAn or DataIn = HGTD_COMMAp) else '0';
+ ISK_SOC <= '1' when ( CharIsK_in = '1' and not ( ISK_comma = '1' or ISK_EOC = '1' ) ) else '0';
+ ISK_EOC <= '1' when ((DataIn = HGTD_EOPn or DataIn = HGTD_EOPp)) else '0';
+ Char_EOC <= '1' when (decoder_out = HGTD_Kchar_eop) and (CharIsK = '1') and (CharIsK_in = '0') else '0';
+ Char_SOC <= '0';
+ Char_SOB <= '0';
+ Char_EOB <= '0';
end if;
end process;
end generate GBT_mode;
FEI4B: if (GENERATE_FEI4B) generate
ISK_comma <= '1' when (DataIn = FEI4B_COMMAp or DataIn = FEI4B_COMMAn) else '0';
- ISK_SOC <= '1' when (DataIn = FEI4B_SOCp or DataIn = FEI4B_SOCn) else '0';
+ --ISK_SOC <= '1' when (DataIn = FEI4B_SOCp or DataIn = FEI4B_SOCn) else '0';
--Char_comma <= '1' when (decoder_out = FEI4B_Kchar_comma and CharIsK = '1' and decoder_out_valid = '1') else '0';
- --Char_SOC <= '1' when (decoder_out = FEI4B_Kchar_sop and CharIsK = '1' and decoder_out_valid = '1') else '0';
- Char_EOC <= '1' when (decoder_out = FEI4B_Kchar_eop and CharIsK = '1' and decoder_out_valid = '1') else '0';
+ Char_SOC <= '1' when (decoder_out = FEI4B_Kchar_sop and CharIsK = '1' and decoder_out_valid_no_ReceivingState = '1') else '0';
+ Char_EOC <= '1' when (decoder_out = FEI4B_Kchar_eop and CharIsK = '1' and decoder_out_valid_no_ReceivingState = '1') else '0';
Char_SOB <= '0';
Char_EOB <= '0';
end generate FEI4B;
@@ -146,8 +146,8 @@ begin
Char_EOB <= '0';
end generate LCB;
- ISK_SOC_out <= ISK_SOC;
- ISK_EOC_out <= ISK_EOC;
+ Char_SOC_out <= Char_SOC;
+ Char_EOC_out <= Char_EOC;
ISK_DelimiterA_out <= ISK_EOC;
ISK_DelimiterB_out <= ISK_comma;
ISK_DelimiterC <= ISK_comma;
@@ -158,6 +158,7 @@ begin
variable AlignmentPulse: std_logic;
variable DecoderAligned_4v: std_logic;
variable ReceivingState: std_logic;
+ variable FirstSOCSeen: std_logic;
begin
if reset = '1' then
AlignmentCounter <= 3;
@@ -173,6 +174,8 @@ begin
RealignmentEvent <= '0';
decoder_out_valid <= '0';
decoder_out_valid_no_receivingState <= '0';
+ FramingError <= '0';
+ FirstSOCSeen := '0'; --The first framing error as a result of missing SOC due to the decoder just aligning should be ignored.
elsif rising_edge(clk40) then
if DecoderAligned_s = '1' then
AlignmentPulse := AlignmentPulseDeAlign;
@@ -203,12 +206,38 @@ begin
DecoderAligned_s <= '0';
end if;
end if;
- if (Char_EOC = '1' or ISK_EOC_in = '1' ) then
+ --Treat inputs for EOC and SOC from other (parallel) decoders first, so ReceivingState is set prior to handling SOC/EOC from this decoder
+ if (Char_EOC_in = '1' and decoder_out_valid_no_ReceivingState = '1') then
+ FramingError <= '0';
+ if (ReceivingState = '0' and FirstSOCSeen = '1' and HGTD_ALTIROC_DECODING = '0') then
+ FramingError <= '1'; --HGTD doesn't use framing, so don't assert FramingError
+ end if;
ReceivingState := '0';
end if;
- if ((ISK_SOC = '1' or ISK_SOC_in = '1' ) and DecoderAligned_4v = '1') or not AWAIT_SOP then
+ if (Char_SOC_in = '1' and decoder_out_valid_no_ReceivingState = '1') or not AWAIT_SOP then
+ FirstSOCSeen := '1'; --First SOC occured, start recording Framing errors
+ if (ReceivingState = '1' and HGTD_ALTIROC_DECODING = '0') then
+ FramingError <= '1' ; --HGTD doesn't use framing, so don't assert FramingError
+ end if;
+ ReceivingState := '1';
+ end if;
+ if (Char_SOC = '1' and decoder_out_valid_no_ReceivingState = '1') or not AWAIT_SOP then
+ FirstSOCSeen := '1'; --First SOC occured, start recording Framing errors
+ if (ReceivingState = '1' and HGTD_ALTIROC_DECODING = '0') then
+ FramingError <= '1' ; --HGTD doesn't use framing, so don't assert FramingError
+ end if;
ReceivingState := '1';
end if;
+ if (Char_EOC = '1' and decoder_out_valid_no_ReceivingState = '1') then
+ FramingError <= '0';
+ if (ReceivingState = '0' and FirstSOCSeen = '1' and HGTD_ALTIROC_DECODING = '0') then
+ FramingError <= '1'; --HGTD doesn't use framing, so don't assert FramingError
+ end if;
+ ReceivingState := '0';
+ end if;
+ if CharIsK = '0' and decoder_out_valid_no_ReceivingState = '1' and ReceivingState = '0' and FirstSOCSeen = '1' and HGTD_ALTIROC_DECODING = '0'then
+ FramingError <= '1';
+ end if;
CodingError <= '0';
RealignmentEvent <= '0';
if ((code_err = '1') and (DecoderAligned_s = '1')) and AutoRealign = '1' then
@@ -237,7 +266,6 @@ begin
end if;
end if;
-
DecoderAligned_4s <= DecoderAligned_4v;
--DataInValid_p1 <= DataInValid and DecoderAligned_4v; --Only validate signal when Elink is aligned for more than 4 clocks.
--! Ignore RecievingState for HGTD_ALTIROC_DECODING
@@ -267,9 +295,9 @@ begin
ElinkSOB <= Char_SOB;
ElinkEOB <= Char_EOB;
- EOP <= Char_EOC;
+ EOP <= Char_EOC and decoder_out_valid;
DataOut <= decoder_out;
- DataOutValid <= not CharIsK and decoder_out_valid;
+ DataOutValid <= (not CharIsK and decoder_out_valid) or (Char_SOC_in and decoder_out_valid_no_ReceivingState and not HGTD_ALTIROC_DECODING);
CharIsK_out <= '1' when ISK_comma = '1' or ISK_EOC = '1' else '0';
diff --git a/sources/decoding/DecodingEpathGBT.vhd b/sources/decoding/DecodingEpathGBT.vhd
index 80e53ff3d0ae22414e126e7f526aac740b7f38da..9c9d16f3341b81c306ebca49dfb18daeb601cead 100644
--- a/sources/decoding/DecodingEpathGBT.vhd
+++ b/sources/decoding/DecodingEpathGBT.vhd
@@ -112,6 +112,7 @@ architecture Behavioral of DecodingEpathGBT is
signal Decoder8b10bSOB : std_logic_vector(NUM_DECODERS(INCLUDE_16b)-1 downto 0);
signal Decoder8b10bEOB : std_logic_vector(NUM_DECODERS(INCLUDE_16b)-1 downto 0);
signal Decoder8b10bCodingError: std_logic_vector(NUM_DECODERS(INCLUDE_16b)-1 downto 0);
+ signal Decoder8b10bFramingError: std_logic_vector(NUM_DECODERS(INCLUDE_16b)-1 downto 0);
signal DecoderHDLCAligned : std_logic;
signal DecoderHDLCDataOut : std_logic_vector(7 downto 0);
@@ -128,6 +129,7 @@ architecture Behavioral of DecodingEpathGBT is
signal ByteToAxiStreamEOB : std_logic_vector(NUM_DECODERS(INCLUDE_16b)-1 downto 0);
signal ByteToAxiStreamTruncate : std_logic;
signal ByteToAxiStreamCodingError: std_logic;
+ signal ByteToAxiStreamFramingError: std_logic;
signal ElinkData_s: std_logic_vector(MAX_INPUT-1 downto 0);
signal GearBoxDataOutValid_p1 : std_logic;
@@ -294,12 +296,13 @@ begin
DecoderAligned_in => DecoderAligned8b10b_in(0),
CodingError => Decoder8b10bCodingError(0),
DisparityError => open,
+ FramingError => Decoder8b10bFramingError(0),
dispout => dispout(0),
dispin => dispin(0),
- ISK_SOC_in => ISK_SOC_in(0),
- ISK_SOC_out => ISK_SOC_out(0),
- ISK_EOC_in => ISK_EOC_in(0),
- ISK_EOC_out => ISK_EOC_out(0),
+ Char_SOC_in => ISK_SOC_in(0),
+ Char_SOC_out => ISK_SOC_out(0),
+ Char_EOC_in => ISK_EOC_in(0),
+ Char_EOC_out => ISK_EOC_out(0),
ISK_DelimiterA_in => '1',
ISK_DelimiterB_in => ISK_DelimiterB_in(0),
ISK_DelimiterA_out => open,
@@ -336,12 +339,13 @@ begin
DecoderAligned_in => DecoderAligned8b10b_in(1),
CodingError => Decoder8b10bCodingError(1),
DisparityError => open,
+ FramingError => Decoder8b10bFramingError(1),
dispout => dispout(1),
dispin => dispin(1),
- ISK_SOC_in => ISK_SOC_in(1),
- ISK_SOC_out => ISK_SOC_out(1),
- ISK_EOC_in => ISK_EOC_in(1),
- ISK_EOC_out => ISK_EOC_out(1),
+ Char_SOC_in => ISK_SOC_in(1),
+ Char_SOC_out => ISK_SOC_out(1),
+ Char_EOC_in => ISK_EOC_in(1),
+ Char_EOC_out => ISK_EOC_out(1),
ISK_DelimiterA_in => '1',
ISK_DelimiterB_in => ISK_DelimiterB_in(1),
ISK_DelimiterA_out => open,
@@ -393,6 +397,7 @@ begin
ByteToAxiStreamEOB <= (others => '0');
ByteToAxiStreamTruncate <= '0';
ByteToAxiStreamCodingError <= '0';
+ ByteToAxiStreamFramingError <= '0';
ByteToAxiStreamGearboxValid <= '0';
GearBoxDataOutValid_p1 <= GearBoxDataOutValid;
@@ -414,11 +419,13 @@ begin
ByteToAxiStreamDataOut <= Decoder8b10bDataOut(7 downto 0) & Decoder8b10bDataOut(15 downto 8); --swap the 2 bytes
ByteToAxiStreamAligned <= and DecoderAligned8b10b_out;
ByteToAxiStreamCodingError <= or Decoder8b10bCodingError;
+ ByteToAxiStreamFramingError <= or Decoder8b10bFramingError;
ByteToAxiStreamDataOutValid <= Decoder8b10bDataOutValid(0) & Decoder8b10bDataOutValid(1);
ByteToAxiStreamEOP <= Decoder8b10bEOP(0) & Decoder8b10bEOP(1);
else
ByteToAxiStreamAligned <= DecoderAligned8b10b_out(0);
ByteToAxiStreamCodingError <= Decoder8b10bCodingError(0);
+ ByteToAxiStreamFramingError <= Decoder8b10bFramingError(0);
end if;
end if;
@@ -458,6 +465,7 @@ begin
EOB => ByteToAxiStreamEOB,
TruncateIn => (others => ByteToAxiStreamTruncate),
CodingErrorIn => ByteToAxiStreamCodingError,
+ FramingErrorIn => ByteToAxiStreamFramingError,
m_axis => m_axis,
m_axis_tready => m_axis_tready,
m_axis_aclk => m_axis_aclk,
diff --git a/sources/ip_cores/kintexUltrascale/KCU_NORXBUF_PCS_CPLL_1CH.xci b/sources/ip_cores/kintexUltrascale/KCU_NORXBUF_PCS_CPLL_1CH.xci
index 55929c81eeb1835f6a2fc335f7bd9cdfc9eea464..e9e3195d641fcf31e0907f65f9eedd2eec14f794 100644
--- a/sources/ip_cores/kintexUltrascale/KCU_NORXBUF_PCS_CPLL_1CH.xci
+++ b/sources/ip_cores/kintexUltrascale/KCU_NORXBUF_PCS_CPLL_1CH.xci
@@ -1372,7 +1372,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/KCU_NORXBUF_PCS_CPLL_1CH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/KCU_PMA_QPLL_4CH_LPGBT.xci b/sources/ip_cores/kintexUltrascale/KCU_PMA_QPLL_4CH_LPGBT.xci
index e855fd9d0da07cee49ad4b42b1f580d7a539de74..335f7734af039e68999d3b588a64501574f3106f 100644
--- a/sources/ip_cores/kintexUltrascale/KCU_PMA_QPLL_4CH_LPGBT.xci
+++ b/sources/ip_cores/kintexUltrascale/KCU_PMA_QPLL_4CH_LPGBT.xci
@@ -1372,7 +1372,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/KCU_PMA_QPLL_4CH_LPGBT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH.xci b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH.xci
index 9844cb263f475895efbffe68c9490f4f81ebdefe..a0c132f37dfa49089e2151a567785ef580976fad 100644
--- a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH.xci
+++ b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH.xci
@@ -1372,7 +1372,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/KCU_RXBUF_PMA_CPLL_1CH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH_LPGBT.xci b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH_LPGBT.xci
index 2f06f67ae411104a2f0ff78b2d65e51e36862e98..3600b7090b8847fa23778c28ce9c36a1504daa68 100644
--- a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH_LPGBT.xci
+++ b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH_LPGBT.xci
@@ -1372,7 +1372,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/KCU_RXBUF_PMA_CPLL_1CH_LPGBT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_4CH.xci b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_4CH.xci
index 2abbf397bd1c38e0e26de8c9e35bbd4f2d2b0e68..28e2e4a41085a4c94d757d917f7db1ae50858d0a 100644
--- a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_4CH.xci
+++ b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_4CH.xci
@@ -1372,7 +1372,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/KCU_RXBUF_PMA_QPLL_4CH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT.xci b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT.xci
index ef2e15e2e53148b73334002e55f805ae5932d1fe..0b3956b07385a25ef699b174c1fc923e2a7bac8e 100644
--- a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT.xci
+++ b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT.xci
@@ -1372,7 +1372,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/axi8_fifo_bif.xci b/sources/ip_cores/kintexUltrascale/axi8_fifo_bif.xci
index efe289b606879ecc6fc9547185d00b6ef365ebed..681239fd8ac6ac3dcd90b2f5da1233ff2f7c911d 100644
--- a/sources/ip_cores/kintexUltrascale/axi8_fifo_bif.xci
+++ b/sources/ip_cores/kintexUltrascale/axi8_fifo_bif.xci
@@ -524,7 +524,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/axi8_fifo_bif</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/axi8_fifo_bram.xci b/sources/ip_cores/kintexUltrascale/axi8_fifo_bram.xci
index 3ce57224203e3fdca22e829827ea83d9e069eedf..4e2c0e966a5877bc135bc11a834232ea263099e5 100644
--- a/sources/ip_cores/kintexUltrascale/axi8_fifo_bram.xci
+++ b/sources/ip_cores/kintexUltrascale/axi8_fifo_bram.xci
@@ -524,7 +524,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/axi8_fifo_bram</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/axis32_fifo_bif.xci b/sources/ip_cores/kintexUltrascale/axis32_fifo_bif.xci
index 6d641ca93bf809b05aeb4d27e45fd3166eb96d71..418dabbdabe932cc698c0979a8a8941918a5a5b9 100644
--- a/sources/ip_cores/kintexUltrascale/axis32_fifo_bif.xci
+++ b/sources/ip_cores/kintexUltrascale/axis32_fifo_bif.xci
@@ -524,7 +524,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/axis32_fifo_bif</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/clk_wiz_100_0.xci b/sources/ip_cores/kintexUltrascale/clk_wiz_100_0.xci
index 3707518910717fa8fa67b8e81d75c098bb12d802..b76461ee58faf6284f93c0fe7e4da1ab552d3cfb 100644
--- a/sources/ip_cores/kintexUltrascale/clk_wiz_100_0.xci
+++ b/sources/ip_cores/kintexUltrascale/clk_wiz_100_0.xci
@@ -674,7 +674,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/clk_wiz_100_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/clk_wiz_156_0.xci b/sources/ip_cores/kintexUltrascale/clk_wiz_156_0.xci
index b7da4993fa631e3e4c29192aa0c820afb44ad547..7d076d92e32b0624da60b0c196613e5f3533e928 100644
--- a/sources/ip_cores/kintexUltrascale/clk_wiz_156_0.xci
+++ b/sources/ip_cores/kintexUltrascale/clk_wiz_156_0.xci
@@ -674,7 +674,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/clk_wiz_156_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/clk_wiz_200_0.xci b/sources/ip_cores/kintexUltrascale/clk_wiz_200_0.xci
index fb698e4a8eb9247e2da3749f24dcda8726e49aab..aceddd1be8202d516f97828bce48d53982d042d7 100644
--- a/sources/ip_cores/kintexUltrascale/clk_wiz_200_0.xci
+++ b/sources/ip_cores/kintexUltrascale/clk_wiz_200_0.xci
@@ -674,7 +674,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/clk_wiz_200_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/clk_wiz_250.xci b/sources/ip_cores/kintexUltrascale/clk_wiz_250.xci
index f18bad9f9139feea1970aa8864efdc1f54e23388..00205a943b25531fcddc8cd3d0a0d4e79dd69899 100644
--- a/sources/ip_cores/kintexUltrascale/clk_wiz_250.xci
+++ b/sources/ip_cores/kintexUltrascale/clk_wiz_250.xci
@@ -690,7 +690,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/clk_wiz_250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/clk_wiz_40_0.xci b/sources/ip_cores/kintexUltrascale/clk_wiz_40_0.xci
index 47b80fe5ff103c47a612b47b493e64ce79323b16..9f1a4584cf4e9185fbff0471e7a6834982b6f8e9 100644
--- a/sources/ip_cores/kintexUltrascale/clk_wiz_40_0.xci
+++ b/sources/ip_cores/kintexUltrascale/clk_wiz_40_0.xci
@@ -722,7 +722,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/clk_wiz_40_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/clk_wiz_regmap.xci b/sources/ip_cores/kintexUltrascale/clk_wiz_regmap.xci
index bb992d7bc0b1dbb5aeea8f77e8d0c76a84b61260..1a7f5600d78336b792013a69df7ac1b1d9c59108 100644
--- a/sources/ip_cores/kintexUltrascale/clk_wiz_regmap.xci
+++ b/sources/ip_cores/kintexUltrascale/clk_wiz_regmap.xci
@@ -674,7 +674,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/clk_wiz_regmap</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/debug_bridge_0.xci b/sources/ip_cores/kintexUltrascale/debug_bridge_0.xci
index f00d22b08322eb78b7770317335783fa7f93f345..c915a6cad180fcee57c16a5158f92c30b93c8f3a 100644
--- a/sources/ip_cores/kintexUltrascale/debug_bridge_0.xci
+++ b/sources/ip_cores/kintexUltrascale/debug_bridge_0.xci
@@ -78,7 +78,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/debug_bridge_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/dsp_counter.xci b/sources/ip_cores/kintexUltrascale/dsp_counter.xci
index 8d8a4e7d21eb3a0193596b2a2478bdb7fa166740..9f9c08ff43538bfd4884b8a1a4c4173d8d0a440f 100644
--- a/sources/ip_cores/kintexUltrascale/dsp_counter.xci
+++ b/sources/ip_cores/kintexUltrascale/dsp_counter.xci
@@ -87,7 +87,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/dsp_counter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_48g_ku.xci b/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_48g_ku.xci
index 72ce385cc5575f6111d616d2bdd0f8df38b5dfb2..d40e9e4df2a7d70fb5a172b07ffaf2b6d78c43df 100644
--- a/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_48g_ku.xci
+++ b/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_48g_ku.xci
@@ -1372,7 +1372,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/gtwizard_fullmode_cpll_48g_ku</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_ku.xci b/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_ku.xci
index 213596b37a83fab213a74a64bac651b13500fb31..9281f5460c35a5969eccf740ff1f29f8fa6113a1 100644
--- a/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_ku.xci
+++ b/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_ku.xci
@@ -1372,7 +1372,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/gtwizard_fullmode_cpll_ku</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/gtwizard_ttc_rxcpll.xci b/sources/ip_cores/kintexUltrascale/gtwizard_ttc_rxcpll.xci
index 2ae6c5d533c90069ba456d0840a07c4d23f0e621..e94d1e7f9953217f00aaad508668e001a18c4cec 100644
--- a/sources/ip_cores/kintexUltrascale/gtwizard_ttc_rxcpll.xci
+++ b/sources/ip_cores/kintexUltrascale/gtwizard_ttc_rxcpll.xci
@@ -11,7 +11,7 @@
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHANNEL_ENABLE">"000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_SCALING_FACTOR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CPLL_VCO_FREQUENCY">2578.125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CPLL_VCO_FREQUENCY">2404.74</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_COMMON_USRCLK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FORCE_COMMONS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FREERUN_FREQUENCY">40.079</spirit:configurableElementValue>
@@ -32,7 +32,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_SEQUENCE_INTERVAL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_BUFFBYPASS_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_BUFFER_BYPASS_INSTANCE_CTRL">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_BUFFER_MODE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_BUFFER_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_CB_DISP">"00000000"</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_CB_K">"00000000"</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_CB_LEN_SEQ">1</spirit:configurableElementValue>
@@ -77,7 +77,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TOTAL_NUM_COMMONS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TOTAL_NUM_COMMONS_EXAMPLE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TXPROGDIV_FREQ_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TXPROGDIV_FREQ_SOURCE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TXPROGDIV_FREQ_SOURCE">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TXPROGDIV_FREQ_VAL">240.474</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_BUFFBYPASS_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_BUFFER_BYPASS_INSTANCE_CTRL">0</spirit:configurableElementValue>
@@ -90,7 +90,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_OUTCLK_BUFG_GT_DIV">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_OUTCLK_FREQUENCY">240.4740000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_OUTCLK_SOURCE">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_PLL_TYPE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_PLL_TYPE">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_REFCLK_FREQUENCY">240.474</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_USER_CLOCKING_CONTENTS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_USER_CLOCKING_INSTANCE_CTRL">0</spirit:configurableElementValue>
@@ -113,7 +113,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_CPLL_CAL">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INS_LOSS_NYQ">20</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_CHANNEL_COLUMN_LOC_MAX">96</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_CHANNEL_SITES_UPDATED">36</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_CHANNEL_SITES_UPDATED">37</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_GT_PRIM_TYPE">gthe3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_NUM_COMMONS_CORE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_NUM_COMMONS_EXAMPLE">0</spirit:configurableElementValue>
@@ -138,7 +138,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLLOCKDETCLK_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLLOCKEN_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLLOCK_OUT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLPD_IN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLPD_IN">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLREFCLKLOST_OUT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLREFCLKSEL_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_CPLLRESET_IN">0</spirit:configurableElementValue>
@@ -190,7 +190,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTPOWERGOOD_OUT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK00_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK01_IN">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK0_IN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK0_IN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK10_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK11_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTREFCLK1_IN">0</spirit:configurableElementValue>
@@ -207,10 +207,10 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTSOUTHREFCLK1_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTTXRESETSEL_IN">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTTXRESET_IN">-1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT">-1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT">-1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN">-1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN">-1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN">1</spirit:configurableElementValue>
@@ -417,11 +417,11 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEVPOVRDEN_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEVSEN_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDFEXYDEN_IN">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYBYPASS_IN">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYEN_IN">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYOVRDEN_IN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYBYPASS_IN">-1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYEN_IN">-1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYOVRDEN_IN">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYSRESETDONE_OUT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYSRESET_IN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXDLYSRESET_IN">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXELECIDLEMODE_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXELECIDLE_OUT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXEQTRAINING_IN">-1</spirit:configurableElementValue>
@@ -466,12 +466,12 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPCSRESET_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPD_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHALIGNDONE_OUT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHALIGNEN_IN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHALIGNEN_IN">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHALIGNERR_OUT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHALIGN_IN">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHDLYPD_IN">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHDLYRESET_IN">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHOVRDEN_IN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHALIGN_IN">-1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHDLYPD_IN">-1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHDLYRESET_IN">-1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPHOVRDEN_IN">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPLLCLKSEL_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPMARESETDONE_OUT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXPMARESET_IN">0</spirit:configurableElementValue>
@@ -503,10 +503,10 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSLIPPMA_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSTARTOFSEQ_OUT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSTATUS_OUT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCALLIN_IN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCALLIN_IN">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCDONE_OUT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCIN_IN">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCMODE_IN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCIN_IN">-1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCMODE_IN">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYNCOUT_OUT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXSYSCLKSEL_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_RXTERMINATION_IN">-1</spirit:configurableElementValue>
@@ -651,7 +651,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMTDO_OUT">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBRSVDOUT_OUT">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBTXUART_OUT">-1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLEMENT_UPDATED">149</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLEMENT_UPDATED">159</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_USAGE_UPDATED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PRESET">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_RX_COMMA_PRESET_UPDATE">11</spirit:configurableElementValue>
@@ -659,7 +659,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_TOTAL_NUM_CHANNELS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_TOTAL_NUM_COMMONS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_TX_USRCLK_FREQUENCY">240.4740000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_UPDATE_IP_SYMBOL_drpclk_in">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_UPDATE_IP_SYMBOL_drpclk_in">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCATE_COMMON">CORE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCATE_IN_SYSTEM_IBERT_CORE">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCATE_RESET_CONTROLLER">CORE</spirit:configurableElementValue>
@@ -678,7 +678,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRESET">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_SEQUENCE_INTERVAL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_BUFFER_BYPASS_MODE">MULTI</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_BUFFER_MODE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_BUFFER_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_BUFFER_RESET_ON_CB_CHANGE">ENABLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_BUFFER_RESET_ON_COMMAALIGN">DISABLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_BUFFER_RESET_ON_RATE_CHANGE">ENABLE</spirit:configurableElementValue>
@@ -802,7 +802,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_QPLL_REFCLK_FREQUENCY">257.8125</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SIM_CPLL_CAL_BYPASS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TXPROGDIV_FREQ_ENABLE">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TXPROGDIV_FREQ_SOURCE">QPLL1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TXPROGDIV_FREQ_SOURCE">CPLL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TXPROGDIV_FREQ_VAL">240.474</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_BUFFER_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_BUFFER_RESET_ON_RATE_CHANGE">ENABLE</spirit:configurableElementValue>
@@ -813,10 +813,10 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_LINE_RATE">4.80948</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_MASTER_CHANNEL">X1Y28</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_OUTCLK_SOURCE">TXPROGDIVCLK</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_PLL_TYPE">QPLL1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_PLL_TYPE">CPLL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_QPLL_FRACN_NUMERATOR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_REFCLK_FREQUENCY">240.474</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_REFCLK_SOURCE">X1Y28 clk1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_REFCLK_SOURCE"/>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_USER_DATA_WIDTH">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USB_ENABLE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_GTPOWERGOOD_DELAY_EN">1</spirit:configurableElementValue>
@@ -892,7 +892,7 @@
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtpowergood_out">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrefclk00_in">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrefclk01_in">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrefclk0_in">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrefclk0_in">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrefclk10_in">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrefclk11_in">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtrefclk1_in">false</spirit:configurableElementValue>
@@ -909,10 +909,10 @@
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtsouthrefclk1_in">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gttxreset_in">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gttxresetsel_in">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_rx_done_out">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_rx_error_out">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_rx_reset_in">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_rx_start_user_in">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_rx_done_out">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_rx_error_out">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_rx_reset_in">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_rx_start_user_in">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_tx_done_out">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_tx_error_out">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.gtwiz_buffbypass_tx_reset_in">true</spirit:configurableElementValue>
@@ -1417,13 +1417,14 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TX_USER_DATA_WIDTH" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
<xilinx:boundaryDescriptionInfo>
- <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"cpllfbclklost_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"cplllock_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"cplllockdetclk_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"cpllreset_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gthrxn_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gthrxp_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gthtxn_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gthtxp_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtpowergood_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtrefclk01_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwi
-z_buffbypass_tx_done_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_buffbypass_tx_error_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_buffbypass_tx_reset_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_buffbypass_tx_start_user_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_all_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_clk_freerun_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_rx_cdr_stable_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_rx_datapath_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_rx_done_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtw
-iz_reset_rx_pll_and_datapath_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_tx_datapath_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_tx_done_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_tx_pll_and_datapath_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_rx_active_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_rx_reset_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_rx_srcclk_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_rx_usrclk2_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_rx_usrclk_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":
-"true"}],"gtwiz_userclk_tx_active_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_tx_reset_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_tx_srcclk_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_tx_usrclk2_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_tx_usrclk_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userdata_rx_out":[{"direction":"out","physical_left":"31","physical_right":"0","is_vector":"true"}],"gtwiz_userdata_tx_in":[{"direction":"in","physical_left":"15","physical_right":"0","is_vector":"true"}],"loopback_in":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"qpll1fbclklost_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"qpll1lock_out":[{"dir
-ection":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"qpll1outclk_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"qpll1outrefclk_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"qpll1refclklost_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"rx8b10ben_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxbyteisaligned_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxbyterealign_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxcdrlock_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxcommadet_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxcommadeten_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxctrl0_out":[{"d
-irection":"out","physical_left":"15","physical_right":"0","is_vector":"true"}],"rxctrl1_out":[{"direction":"out","physical_left":"15","physical_right":"0","is_vector":"true"}],"rxctrl2_out":[{"direction":"out","physical_left":"7","physical_right":"0","is_vector":"true"}],"rxctrl3_out":[{"direction":"out","physical_left":"7","physical_right":"0","is_vector":"true"}],"rxmcommaalignen_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxpcommaalignen_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxpmaresetdone_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxresetdone_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"tx8b10ben_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"txctrl0_in":[{"direction":"in","physical_left":"15","physical_right":"0","is_vector":"true"}],"txctrl1_in":[{"direction":"in","
-physical_left":"15","physical_right":"0","is_vector":"true"}],"txctrl2_in":[{"direction":"in","physical_left":"7","physical_right":"0","is_vector":"true"}],"txpmaresetdone_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"txprgdivresetdone_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"txresetdone_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}]},"interfaces":{}}}"/>
+ <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"cpllfbclklost_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"cplllock_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"cplllockdetclk_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"cpllreset_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"drpclk_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gthrxn_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gthrxp_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gthtxn_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gthtxp_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtpowergood_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtrefclk
+01_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtrefclk0_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_buffbypass_rx_done_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_buffbypass_rx_error_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_buffbypass_rx_reset_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_buffbypass_rx_start_user_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_buffbypass_tx_done_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_buffbypass_tx_error_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_buffbypass_tx_reset_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_buffbypass_tx
+_start_user_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_all_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_clk_freerun_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_rx_cdr_stable_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_rx_datapath_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_rx_done_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_rx_pll_and_datapath_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_tx_datapath_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_tx_done_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_reset_tx_pll_an
+d_datapath_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_rx_active_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_rx_reset_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_rx_srcclk_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_rx_usrclk2_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_rx_usrclk_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_tx_active_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_tx_reset_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_tx_srcclk_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userc
+lk_tx_usrclk2_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userclk_tx_usrclk_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"gtwiz_userdata_rx_out":[{"direction":"out","physical_left":"31","physical_right":"0","is_vector":"true"}],"gtwiz_userdata_tx_in":[{"direction":"in","physical_left":"15","physical_right":"0","is_vector":"true"}],"loopback_in":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"qpll1fbclklost_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"qpll1lock_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"qpll1outclk_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"qpll1outrefclk_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"qpll1refclklost_out":[{"direction":"out","physical_left":"0","physical_rig
+ht":"0","is_vector":"true"}],"rx8b10ben_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxbyteisaligned_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxbyterealign_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxcdrlock_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxcommadet_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxcommadeten_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxctrl0_out":[{"direction":"out","physical_left":"15","physical_right":"0","is_vector":"true"}],"rxctrl1_out":[{"direction":"out","physical_left":"15","physical_right":"0","is_vector":"true"}],"rxctrl2_out":[{"direction":"out","physical_left":"7","physical_right":"0","is_vector":"true"}],"rxctrl3_out":[{"direction":"out","physical_left":"7","physical_right":"0","is_vec
+tor":"true"}],"rxmcommaalignen_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxpcommaalignen_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxpmaresetdone_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"rxresetdone_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"tx8b10ben_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"txctrl0_in":[{"direction":"in","physical_left":"15","physical_right":"0","is_vector":"true"}],"txctrl1_in":[{"direction":"in","physical_left":"15","physical_right":"0","is_vector":"true"}],"txctrl2_in":[{"direction":"in","physical_left":"7","physical_right":"0","is_vector":"true"}],"txpmaresetdone_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"txprgdivresetdone_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector
+":"true"}],"txresetdone_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}]},"interfaces":{}}}"/>
</xilinx:boundaryDescriptionInfo>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7038.xci b/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7038.xci
index ae80ce7d15591a9ae5a6870e239c5ac2404848af..70f4ffd9e3e27b076b61960e6234d2e613f3a0ac 100644
--- a/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7038.xci
+++ b/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7038.xci
@@ -831,7 +831,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/pcie3_ultrascale_7038</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7039.xci b/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7039.xci
index 7f22c43310b481a61950decb8dabe41b2b0115de..0016c5c5e0c20273bb1fb05b3f984ba66124d8c7 100644
--- a/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7039.xci
+++ b/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7039.xci
@@ -831,7 +831,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/pcie3_ultrascale_7039</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/system_management_wiz_0.xci b/sources/ip_cores/kintexUltrascale/system_management_wiz_0.xci
index dcaed14c92c0f9fa81d8a52475b04f5555cc7348..66c19efae8c105d0ccd78ce3a591c91781c34f86 100644
--- a/sources/ip_cores/kintexUltrascale/system_management_wiz_0.xci
+++ b/sources/ip_cores/kintexUltrascale/system_management_wiz_0.xci
@@ -948,7 +948,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/system_management_wiz_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/kintexUltrascale/wavegen_dsp_counter.xci b/sources/ip_cores/kintexUltrascale/wavegen_dsp_counter.xci
index fbcb8c1bd2a928088718d89425295b9919214329..a5cce3677b5cfc100818cf1509b07ba2e4529e2e 100644
--- a/sources/ip_cores/kintexUltrascale/wavegen_dsp_counter.xci
+++ b/sources/ip_cores/kintexUltrascale/wavegen_dsp_counter.xci
@@ -87,7 +87,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/wavegen_dsp_counter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
diff --git a/sources/ip_cores/sim/DPram_32b_sim_netlist.vhdl b/sources/ip_cores/sim/DPram_32b_sim_netlist.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..b20b60a72d1601fa6fae28ef6dae788828b2d308
--- /dev/null
+++ b/sources/ip_cores/sim/DPram_32b_sim_netlist.vhdl
@@ -0,0 +1,1106 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Wed Jun 12 16:30:35 2024
+-- Host : lbp001app.nikhef.nl running 64-bit unknown
+-- Command : write_vhdl -force -mode funcsim
+-- /localstore/et/franss/felix/firmware/Projects/FLX712_FMEMU/FLX712_FMEMU.gen/sources_1/ip/DPram_32b/DPram_32b_sim_netlist.vhdl
+-- Design : DPram_32b
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xcku115-flvf1924-2-e
+-- --------------------------------------------------------------------------------
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+rO7Os08DxfK9MhlLA4TgOkHnmL0XxSg=
+`protect end_protected
+library IEEE;
+ use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+ use UNISIM.VCOMPONENTS.ALL;
+entity DPram_32b is
+ port (
+ clka : in STD_LOGIC;
+ wea : in STD_LOGIC_VECTOR ( 0 to 0 );
+ addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ clkb : in STD_LOGIC;
+ web : in STD_LOGIC_VECTOR ( 0 to 0 );
+ addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of DPram_32b : entity is true;
+ attribute CHECK_LICENSE_TYPE : string;
+ attribute CHECK_LICENSE_TYPE of DPram_32b : entity is "DPram_32b,blk_mem_gen_v8_4_8,{}";
+ attribute downgradeipidentifiedwarnings : string;
+ attribute downgradeipidentifiedwarnings of DPram_32b : entity is "yes";
+ attribute x_core_info : string;
+ attribute x_core_info of DPram_32b : entity is "blk_mem_gen_v8_4_8,Vivado 2024.1";
+end DPram_32b;
+
+architecture STRUCTURE of DPram_32b is
+ signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ attribute C_ADDRA_WIDTH : integer;
+ attribute C_ADDRA_WIDTH of U0 : label is 10;
+ attribute C_ADDRB_WIDTH : integer;
+ attribute C_ADDRB_WIDTH of U0 : label is 10;
+ attribute C_ALGORITHM : integer;
+ attribute C_ALGORITHM of U0 : label is 1;
+ attribute C_AXI_ID_WIDTH : integer;
+ attribute C_AXI_ID_WIDTH of U0 : label is 4;
+ attribute C_AXI_SLAVE_TYPE : integer;
+ attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
+ attribute C_AXI_TYPE : integer;
+ attribute C_AXI_TYPE of U0 : label is 1;
+ attribute C_BYTE_SIZE : integer;
+ attribute C_BYTE_SIZE of U0 : label is 9;
+ attribute C_COMMON_CLK : integer;
+ attribute C_COMMON_CLK of U0 : label is 0;
+ attribute C_COUNT_18K_BRAM : string;
+ attribute C_COUNT_18K_BRAM of U0 : label is "0";
+ attribute C_COUNT_36K_BRAM : string;
+ attribute C_COUNT_36K_BRAM of U0 : label is "1";
+ attribute C_CTRL_ECC_ALGO : string;
+ attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
+ attribute C_DEFAULT_DATA : string;
+ attribute C_DEFAULT_DATA of U0 : label is "0";
+ attribute C_DISABLE_WARN_BHV_COLL : integer;
+ attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
+ attribute C_DISABLE_WARN_BHV_RANGE : integer;
+ attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
+ attribute C_ELABORATION_DIR : string;
+ attribute C_ELABORATION_DIR of U0 : label is "./";
+ attribute C_ENABLE_32BIT_ADDRESS : integer;
+ attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
+ attribute C_EN_DEEPSLEEP_PIN : integer;
+ attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
+ attribute C_EN_ECC_PIPE : integer;
+ attribute C_EN_ECC_PIPE of U0 : label is 0;
+ attribute C_EN_RDADDRA_CHG : integer;
+ attribute C_EN_RDADDRA_CHG of U0 : label is 0;
+ attribute C_EN_RDADDRB_CHG : integer;
+ attribute C_EN_RDADDRB_CHG of U0 : label is 0;
+ attribute C_EN_SAFETY_CKT : integer;
+ attribute C_EN_SAFETY_CKT of U0 : label is 0;
+ attribute C_EN_SHUTDOWN_PIN : integer;
+ attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
+ attribute C_EN_SLEEP_PIN : integer;
+ attribute C_EN_SLEEP_PIN of U0 : label is 0;
+ attribute C_EST_POWER_SUMMARY : string;
+ attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 6.12234 mW";
+ attribute C_FAMILY : string;
+ attribute C_FAMILY of U0 : label is "kintexu";
+ attribute C_HAS_AXI_ID : integer;
+ attribute C_HAS_AXI_ID of U0 : label is 0;
+ attribute C_HAS_ENA : integer;
+ attribute C_HAS_ENA of U0 : label is 0;
+ attribute C_HAS_ENB : integer;
+ attribute C_HAS_ENB of U0 : label is 0;
+ attribute C_HAS_INJECTERR : integer;
+ attribute C_HAS_INJECTERR of U0 : label is 0;
+ attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
+ attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
+ attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
+ attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
+ attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
+ attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
+ attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
+ attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
+ attribute C_HAS_REGCEA : integer;
+ attribute C_HAS_REGCEA of U0 : label is 0;
+ attribute C_HAS_REGCEB : integer;
+ attribute C_HAS_REGCEB of U0 : label is 0;
+ attribute C_HAS_RSTA : integer;
+ attribute C_HAS_RSTA of U0 : label is 0;
+ attribute C_HAS_RSTB : integer;
+ attribute C_HAS_RSTB of U0 : label is 0;
+ attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
+ attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
+ attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
+ attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
+ attribute C_INITA_VAL : integer;
+ attribute C_INITA_VAL of U0 : label is 0;
+ attribute C_INITB_VAL : integer;
+ attribute C_INITB_VAL of U0 : label is 0;
+ attribute C_INIT_FILE : string;
+ attribute C_INIT_FILE of U0 : label is "DPram_32b.mem";
+ attribute C_INIT_FILE_NAME : string;
+ attribute C_INIT_FILE_NAME of U0 : label is "DPram_32b.mif";
+ attribute C_INTERFACE_TYPE : integer;
+ attribute C_INTERFACE_TYPE of U0 : label is 0;
+ attribute C_LOAD_INIT_FILE : integer;
+ attribute C_LOAD_INIT_FILE of U0 : label is 1;
+ attribute C_MEM_TYPE : integer;
+ attribute C_MEM_TYPE of U0 : label is 2;
+ attribute C_MUX_PIPELINE_STAGES : integer;
+ attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
+ attribute C_PRIM_TYPE : integer;
+ attribute C_PRIM_TYPE of U0 : label is 1;
+ attribute C_READ_DEPTH_A : integer;
+ attribute C_READ_DEPTH_A of U0 : label is 1024;
+ attribute C_READ_DEPTH_B : integer;
+ attribute C_READ_DEPTH_B of U0 : label is 1024;
+ attribute C_READ_LATENCY_A : integer;
+ attribute C_READ_LATENCY_A of U0 : label is 1;
+ attribute C_READ_LATENCY_B : integer;
+ attribute C_READ_LATENCY_B of U0 : label is 1;
+ attribute C_READ_WIDTH_A : integer;
+ attribute C_READ_WIDTH_A of U0 : label is 32;
+ attribute C_READ_WIDTH_B : integer;
+ attribute C_READ_WIDTH_B of U0 : label is 32;
+ attribute C_RSTRAM_A : integer;
+ attribute C_RSTRAM_A of U0 : label is 0;
+ attribute C_RSTRAM_B : integer;
+ attribute C_RSTRAM_B of U0 : label is 0;
+ attribute C_RST_PRIORITY_A : string;
+ attribute C_RST_PRIORITY_A of U0 : label is "CE";
+ attribute C_RST_PRIORITY_B : string;
+ attribute C_RST_PRIORITY_B of U0 : label is "CE";
+ attribute C_SIM_COLLISION_CHECK : string;
+ attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
+ attribute C_USE_BRAM_BLOCK : integer;
+ attribute C_USE_BRAM_BLOCK of U0 : label is 0;
+ attribute C_USE_BYTE_WEA : integer;
+ attribute C_USE_BYTE_WEA of U0 : label is 0;
+ attribute C_USE_BYTE_WEB : integer;
+ attribute C_USE_BYTE_WEB of U0 : label is 0;
+ attribute C_USE_DEFAULT_DATA : integer;
+ attribute C_USE_DEFAULT_DATA of U0 : label is 0;
+ attribute C_USE_ECC : integer;
+ attribute C_USE_ECC of U0 : label is 0;
+ attribute C_USE_SOFTECC : integer;
+ attribute C_USE_SOFTECC of U0 : label is 0;
+ attribute C_USE_URAM : integer;
+ attribute C_USE_URAM of U0 : label is 0;
+ attribute C_WEA_WIDTH : integer;
+ attribute C_WEA_WIDTH of U0 : label is 1;
+ attribute C_WEB_WIDTH : integer;
+ attribute C_WEB_WIDTH of U0 : label is 1;
+ attribute C_WRITE_DEPTH_A : integer;
+ attribute C_WRITE_DEPTH_A of U0 : label is 1024;
+ attribute C_WRITE_DEPTH_B : integer;
+ attribute C_WRITE_DEPTH_B of U0 : label is 1024;
+ attribute C_WRITE_MODE_A : string;
+ attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
+ attribute C_WRITE_MODE_B : string;
+ attribute C_WRITE_MODE_B of U0 : label is "READ_FIRST";
+ attribute C_WRITE_WIDTH_A : integer;
+ attribute C_WRITE_WIDTH_A of U0 : label is 32;
+ attribute C_WRITE_WIDTH_B : integer;
+ attribute C_WRITE_WIDTH_B of U0 : label is 32;
+ attribute C_XDEVICEFAMILY : string;
+ attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
+ attribute downgradeipidentifiedwarnings of U0 : label is "yes";
+ attribute is_du_within_envelope : string;
+ attribute is_du_within_envelope of U0 : label is "true";
+ attribute x_interface_info : string;
+ attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
+ attribute x_interface_parameter : string;
+ attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
+ attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
+ attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
+ attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
+ attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
+ attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
+ attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
+ attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
+ attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
+ attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
+ attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
+begin
+ U0: entity work.DPram_32b_blk_mem_gen_v8_4_8
+ port map (
+ addra(9 downto 0) => addra(9 downto 0),
+ addrb(9 downto 0) => addrb(9 downto 0),
+ clka => clka,
+ clkb => clkb,
+ dbiterr => NLW_U0_dbiterr_UNCONNECTED,
+ deepsleep => '0',
+ dina(31 downto 0) => dina(31 downto 0),
+ dinb(31 downto 0) => dinb(31 downto 0),
+ douta(31 downto 0) => douta(31 downto 0),
+ doutb(31 downto 0) => doutb(31 downto 0),
+ eccpipece => '0',
+ ena => '0',
+ enb => '0',
+ injectdbiterr => '0',
+ injectsbiterr => '0',
+ rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
+ regcea => '1',
+ regceb => '1',
+ rsta => '0',
+ rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
+ rstb => '0',
+ rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
+ s_aclk => '0',
+ s_aresetn => '0',
+ s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
+ s_axi_arburst(1 downto 0) => B"00",
+ s_axi_arid(3 downto 0) => B"0000",
+ s_axi_arlen(7 downto 0) => B"00000000",
+ s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
+ s_axi_arsize(2 downto 0) => B"000",
+ s_axi_arvalid => '0',
+ s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
+ s_axi_awburst(1 downto 0) => B"00",
+ s_axi_awid(3 downto 0) => B"0000",
+ s_axi_awlen(7 downto 0) => B"00000000",
+ s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
+ s_axi_awsize(2 downto 0) => B"000",
+ s_axi_awvalid => '0',
+ s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
+ s_axi_bready => '0',
+ s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
+ s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
+ s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
+ s_axi_injectdbiterr => '0',
+ s_axi_injectsbiterr => '0',
+ s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
+ s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
+ s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
+ s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
+ s_axi_rready => '0',
+ s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
+ s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
+ s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
+ s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
+ s_axi_wlast => '0',
+ s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
+ s_axi_wstrb(0) => '0',
+ s_axi_wvalid => '0',
+ sbiterr => NLW_U0_sbiterr_UNCONNECTED,
+ shutdown => '0',
+ sleep => '0',
+ wea(0) => wea(0),
+ web(0) => web(0)
+ );
+end STRUCTURE;
diff --git a/sources/ip_cores/sim/Distr_LUT_sim_netlist.vhdl b/sources/ip_cores/sim/Distr_LUT_sim_netlist.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..e7ec8dcf33044e81707f6c9d5d9fe1f186b02d25
--- /dev/null
+++ b/sources/ip_cores/sim/Distr_LUT_sim_netlist.vhdl
@@ -0,0 +1,932 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Wed Jun 12 16:30:34 2024
+-- Host : lbp001app.nikhef.nl running 64-bit unknown
+-- Command : write_vhdl -force -mode funcsim
+-- /localstore/et/franss/felix/firmware/Projects/FLX712_FMEMU/FLX712_FMEMU.gen/sources_1/ip/Distr_LUT/Distr_LUT_sim_netlist.vhdl
+-- Design : Distr_LUT
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xcku115-flvf1924-2-e
+-- --------------------------------------------------------------------------------
+`protect begin_protected
+`protect version = 1
+`protect encrypt_agent = "XILINX"
+`protect encrypt_agent_info = "Xilinx Encryption Tool 2024.1"
+`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
+`protect key_block
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++I3G9t9tJuWUIWKjI+I=
+
+`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
+`protect key_block
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+
+`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect key_keyowner="Xilinx", key_keyname="xilinxt_2023_11", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=384)
+`protect key_block
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+`protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect data_method = "AES128-CBC"
+`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30448)
+`protect data_block
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+`protect end_protected
+library IEEE;
+ use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+ use UNISIM.VCOMPONENTS.ALL;
+entity Distr_LUT is
+ port (
+ clka : in STD_LOGIC;
+ wea : in STD_LOGIC_VECTOR ( 0 to 0 );
+ addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ clkb : in STD_LOGIC;
+ enb : in STD_LOGIC;
+ addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ doutb : out STD_LOGIC_VECTOR ( 15 downto 0 )
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of Distr_LUT : entity is true;
+ attribute CHECK_LICENSE_TYPE : string;
+ attribute CHECK_LICENSE_TYPE of Distr_LUT : entity is "Distr_LUT,blk_mem_gen_v8_4_8,{}";
+ attribute downgradeipidentifiedwarnings : string;
+ attribute downgradeipidentifiedwarnings of Distr_LUT : entity is "yes";
+ attribute x_core_info : string;
+ attribute x_core_info of Distr_LUT : entity is "blk_mem_gen_v8_4_8,Vivado 2024.1";
+end Distr_LUT;
+
+architecture STRUCTURE of Distr_LUT is
+ signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+ signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+ signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ attribute C_ADDRA_WIDTH : integer;
+ attribute C_ADDRA_WIDTH of U0 : label is 10;
+ attribute C_ADDRB_WIDTH : integer;
+ attribute C_ADDRB_WIDTH of U0 : label is 10;
+ attribute C_ALGORITHM : integer;
+ attribute C_ALGORITHM of U0 : label is 1;
+ attribute C_AXI_ID_WIDTH : integer;
+ attribute C_AXI_ID_WIDTH of U0 : label is 4;
+ attribute C_AXI_SLAVE_TYPE : integer;
+ attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
+ attribute C_AXI_TYPE : integer;
+ attribute C_AXI_TYPE of U0 : label is 1;
+ attribute C_BYTE_SIZE : integer;
+ attribute C_BYTE_SIZE of U0 : label is 9;
+ attribute C_COMMON_CLK : integer;
+ attribute C_COMMON_CLK of U0 : label is 0;
+ attribute C_COUNT_18K_BRAM : string;
+ attribute C_COUNT_18K_BRAM of U0 : label is "1";
+ attribute C_COUNT_36K_BRAM : string;
+ attribute C_COUNT_36K_BRAM of U0 : label is "0";
+ attribute C_CTRL_ECC_ALGO : string;
+ attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
+ attribute C_DEFAULT_DATA : string;
+ attribute C_DEFAULT_DATA of U0 : label is "0";
+ attribute C_DISABLE_WARN_BHV_COLL : integer;
+ attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
+ attribute C_DISABLE_WARN_BHV_RANGE : integer;
+ attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
+ attribute C_ELABORATION_DIR : string;
+ attribute C_ELABORATION_DIR of U0 : label is "./";
+ attribute C_ENABLE_32BIT_ADDRESS : integer;
+ attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
+ attribute C_EN_DEEPSLEEP_PIN : integer;
+ attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
+ attribute C_EN_ECC_PIPE : integer;
+ attribute C_EN_ECC_PIPE of U0 : label is 0;
+ attribute C_EN_RDADDRA_CHG : integer;
+ attribute C_EN_RDADDRA_CHG of U0 : label is 0;
+ attribute C_EN_RDADDRB_CHG : integer;
+ attribute C_EN_RDADDRB_CHG of U0 : label is 0;
+ attribute C_EN_SAFETY_CKT : integer;
+ attribute C_EN_SAFETY_CKT of U0 : label is 0;
+ attribute C_EN_SHUTDOWN_PIN : integer;
+ attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
+ attribute C_EN_SLEEP_PIN : integer;
+ attribute C_EN_SLEEP_PIN of U0 : label is 0;
+ attribute C_EST_POWER_SUMMARY : string;
+ attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.107037 mW";
+ attribute C_FAMILY : string;
+ attribute C_FAMILY of U0 : label is "kintexu";
+ attribute C_HAS_AXI_ID : integer;
+ attribute C_HAS_AXI_ID of U0 : label is 0;
+ attribute C_HAS_ENA : integer;
+ attribute C_HAS_ENA of U0 : label is 0;
+ attribute C_HAS_ENB : integer;
+ attribute C_HAS_ENB of U0 : label is 1;
+ attribute C_HAS_INJECTERR : integer;
+ attribute C_HAS_INJECTERR of U0 : label is 0;
+ attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
+ attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
+ attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
+ attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
+ attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
+ attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
+ attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
+ attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
+ attribute C_HAS_REGCEA : integer;
+ attribute C_HAS_REGCEA of U0 : label is 0;
+ attribute C_HAS_REGCEB : integer;
+ attribute C_HAS_REGCEB of U0 : label is 0;
+ attribute C_HAS_RSTA : integer;
+ attribute C_HAS_RSTA of U0 : label is 0;
+ attribute C_HAS_RSTB : integer;
+ attribute C_HAS_RSTB of U0 : label is 0;
+ attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
+ attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
+ attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
+ attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
+ attribute C_INITA_VAL : string;
+ attribute C_INITA_VAL of U0 : label is "0";
+ attribute C_INITB_VAL : string;
+ attribute C_INITB_VAL of U0 : label is "0";
+ attribute C_INIT_FILE : string;
+ attribute C_INIT_FILE of U0 : label is "Distr_LUT.mem";
+ attribute C_INIT_FILE_NAME : string;
+ attribute C_INIT_FILE_NAME of U0 : label is "Distr_LUT.mif";
+ attribute C_INTERFACE_TYPE : integer;
+ attribute C_INTERFACE_TYPE of U0 : label is 0;
+ attribute C_LOAD_INIT_FILE : integer;
+ attribute C_LOAD_INIT_FILE of U0 : label is 1;
+ attribute C_MEM_TYPE : integer;
+ attribute C_MEM_TYPE of U0 : label is 1;
+ attribute C_MUX_PIPELINE_STAGES : integer;
+ attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
+ attribute C_PRIM_TYPE : integer;
+ attribute C_PRIM_TYPE of U0 : label is 1;
+ attribute C_READ_DEPTH_A : integer;
+ attribute C_READ_DEPTH_A of U0 : label is 1024;
+ attribute C_READ_DEPTH_B : integer;
+ attribute C_READ_DEPTH_B of U0 : label is 1024;
+ attribute C_READ_LATENCY_A : integer;
+ attribute C_READ_LATENCY_A of U0 : label is 1;
+ attribute C_READ_LATENCY_B : integer;
+ attribute C_READ_LATENCY_B of U0 : label is 1;
+ attribute C_READ_WIDTH_A : integer;
+ attribute C_READ_WIDTH_A of U0 : label is 16;
+ attribute C_READ_WIDTH_B : integer;
+ attribute C_READ_WIDTH_B of U0 : label is 16;
+ attribute C_RSTRAM_A : integer;
+ attribute C_RSTRAM_A of U0 : label is 0;
+ attribute C_RSTRAM_B : integer;
+ attribute C_RSTRAM_B of U0 : label is 0;
+ attribute C_RST_PRIORITY_A : string;
+ attribute C_RST_PRIORITY_A of U0 : label is "CE";
+ attribute C_RST_PRIORITY_B : string;
+ attribute C_RST_PRIORITY_B of U0 : label is "CE";
+ attribute C_SIM_COLLISION_CHECK : string;
+ attribute C_SIM_COLLISION_CHECK of U0 : label is "NONE";
+ attribute C_USE_BRAM_BLOCK : integer;
+ attribute C_USE_BRAM_BLOCK of U0 : label is 0;
+ attribute C_USE_BYTE_WEA : integer;
+ attribute C_USE_BYTE_WEA of U0 : label is 0;
+ attribute C_USE_BYTE_WEB : integer;
+ attribute C_USE_BYTE_WEB of U0 : label is 0;
+ attribute C_USE_DEFAULT_DATA : integer;
+ attribute C_USE_DEFAULT_DATA of U0 : label is 0;
+ attribute C_USE_ECC : integer;
+ attribute C_USE_ECC of U0 : label is 0;
+ attribute C_USE_SOFTECC : integer;
+ attribute C_USE_SOFTECC of U0 : label is 0;
+ attribute C_USE_URAM : integer;
+ attribute C_USE_URAM of U0 : label is 0;
+ attribute C_WEA_WIDTH : integer;
+ attribute C_WEA_WIDTH of U0 : label is 1;
+ attribute C_WEB_WIDTH : integer;
+ attribute C_WEB_WIDTH of U0 : label is 1;
+ attribute C_WRITE_DEPTH_A : integer;
+ attribute C_WRITE_DEPTH_A of U0 : label is 1024;
+ attribute C_WRITE_DEPTH_B : integer;
+ attribute C_WRITE_DEPTH_B of U0 : label is 1024;
+ attribute C_WRITE_MODE_A : string;
+ attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST";
+ attribute C_WRITE_MODE_B : string;
+ attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
+ attribute C_WRITE_WIDTH_A : integer;
+ attribute C_WRITE_WIDTH_A of U0 : label is 16;
+ attribute C_WRITE_WIDTH_B : integer;
+ attribute C_WRITE_WIDTH_B of U0 : label is 16;
+ attribute C_XDEVICEFAMILY : string;
+ attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
+ attribute downgradeipidentifiedwarnings of U0 : label is "yes";
+ attribute is_du_within_envelope : string;
+ attribute is_du_within_envelope of U0 : label is "true";
+ attribute x_interface_info : string;
+ attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
+ attribute x_interface_parameter : string;
+ attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
+ attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
+ attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
+ attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
+ attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
+ attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
+ attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
+ attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
+ attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
+begin
+ U0: entity work.Distr_LUT_blk_mem_gen_v8_4_8
+ port map (
+ addra(9 downto 0) => addra(9 downto 0),
+ addrb(9 downto 0) => addrb(9 downto 0),
+ clka => clka,
+ clkb => clkb,
+ dbiterr => NLW_U0_dbiterr_UNCONNECTED,
+ deepsleep => '0',
+ dina(15 downto 0) => dina(15 downto 0),
+ dinb(15 downto 0) => B"0000000000000000",
+ douta(15 downto 0) => NLW_U0_douta_UNCONNECTED(15 downto 0),
+ doutb(15 downto 0) => doutb(15 downto 0),
+ eccpipece => '0',
+ ena => '0',
+ enb => enb,
+ injectdbiterr => '0',
+ injectsbiterr => '0',
+ rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
+ regcea => '1',
+ regceb => '1',
+ rsta => '0',
+ rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
+ rstb => '0',
+ rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
+ s_aclk => '0',
+ s_aresetn => '0',
+ s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
+ s_axi_arburst(1 downto 0) => B"00",
+ s_axi_arid(3 downto 0) => B"0000",
+ s_axi_arlen(7 downto 0) => B"00000000",
+ s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
+ s_axi_arsize(2 downto 0) => B"000",
+ s_axi_arvalid => '0',
+ s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
+ s_axi_awburst(1 downto 0) => B"00",
+ s_axi_awid(3 downto 0) => B"0000",
+ s_axi_awlen(7 downto 0) => B"00000000",
+ s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
+ s_axi_awsize(2 downto 0) => B"000",
+ s_axi_awvalid => '0',
+ s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
+ s_axi_bready => '0',
+ s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
+ s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
+ s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
+ s_axi_injectdbiterr => '0',
+ s_axi_injectsbiterr => '0',
+ s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
+ s_axi_rdata(15 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(15 downto 0),
+ s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
+ s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
+ s_axi_rready => '0',
+ s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
+ s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
+ s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
+ s_axi_wdata(15 downto 0) => B"0000000000000000",
+ s_axi_wlast => '0',
+ s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
+ s_axi_wstrb(0) => '0',
+ s_axi_wvalid => '0',
+ sbiterr => NLW_U0_sbiterr_UNCONNECTED,
+ shutdown => '0',
+ sleep => '0',
+ wea(0) => wea(0),
+ web(0) => '0'
+ );
+end STRUCTURE;
diff --git a/sources/ip_cores/sim/KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_sim_netlist.vhdl b/sources/ip_cores/sim/KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_sim_netlist.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..430d6e615295dd4116e8e2fb713864af6450c954
--- /dev/null
+++ b/sources/ip_cores/sim/KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_sim_netlist.vhdl
@@ -0,0 +1,15241 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Fri Jun 14 11:28:31 2024
+-- Host : lbp001app.nikhef.nl running 64-bit unknown
+-- Command : write_vhdl -force -mode funcsim
+-- /localstore/et/franss/felix/firmware/Projects/FLX712_FELIG/FLX712_FELIG.gen/sources_1/ip/KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0/KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_sim_netlist.vhdl
+-- Design : KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xcku115-flvf1924-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rxresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_0 is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ txresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_0 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_0;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_0 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => txresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_1 is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_1 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_1;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_1 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rxresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_10 is
+ port (
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ in0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \FSM_sequential_sm_reset_rx_reg[0]\ : in STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[0]_0\ : in STD_LOGIC;
+ gtwiz_reset_rx_pll_and_datapath_dly : in STD_LOGIC;
+ sm_reset_rx_pll_timer_sat : in STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[0]_1\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_10 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_10;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_10 is
+ signal \FSM_sequential_sm_reset_rx[2]_i_3_n_0\ : STD_LOGIC;
+ signal gtwiz_reset_rx_datapath_dly : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+\FSM_sequential_sm_reset_rx[2]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFE400E4"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => \FSM_sequential_sm_reset_rx[2]_i_3_n_0\,
+ I2 => \FSM_sequential_sm_reset_rx_reg[0]\,
+ I3 => Q(2),
+ I4 => \FSM_sequential_sm_reset_rx_reg[0]_0\,
+ O => E(0)
+ );
+\FSM_sequential_sm_reset_rx[2]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0E0EFE0E"
+ )
+ port map (
+ I0 => gtwiz_reset_rx_datapath_dly,
+ I1 => gtwiz_reset_rx_pll_and_datapath_dly,
+ I2 => Q(0),
+ I3 => sm_reset_rx_pll_timer_sat,
+ I4 => \FSM_sequential_sm_reset_rx_reg[0]_1\,
+ O => \FSM_sequential_sm_reset_rx[2]_i_3_n_0\
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => in0,
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => gtwiz_reset_rx_datapath_dly,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_11 is
+ port (
+ gtwiz_reset_rx_pll_and_datapath_dly : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ in0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \p_0_in11_out__0\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_11 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_11;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_11 is
+ signal \^gtwiz_reset_rx_pll_and_datapath_dly\ : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_rx[0]_i_1\ : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_rx[1]_i_1\ : label is "soft_lutpair0";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+ gtwiz_reset_rx_pll_and_datapath_dly <= \^gtwiz_reset_rx_pll_and_datapath_dly\;
+\FSM_sequential_sm_reset_rx[0]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"F5A55E5E"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => \^gtwiz_reset_rx_pll_and_datapath_dly\,
+ I2 => Q(1),
+ I3 => \p_0_in11_out__0\,
+ I4 => Q(2),
+ O => D(0)
+ );
+\FSM_sequential_sm_reset_rx[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00FFF511"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => \^gtwiz_reset_rx_pll_and_datapath_dly\,
+ I2 => \p_0_in11_out__0\,
+ I3 => Q(1),
+ I4 => Q(0),
+ O => D(1)
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => in0,
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \^gtwiz_reset_rx_pll_and_datapath_dly\,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_12 is
+ port (
+ i_in_out_reg_0 : out STD_LOGIC;
+ in0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_pll_and_datapath_dly : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sm_reset_tx_pll_timer_sat : in STD_LOGIC;
+ \FSM_sequential_sm_reset_tx[2]_i_5\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_12 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_12;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_12 is
+ signal gtwiz_reset_tx_datapath_dly : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+\FSM_sequential_sm_reset_tx[2]_i_6\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0E0EFE0E"
+ )
+ port map (
+ I0 => gtwiz_reset_tx_datapath_dly,
+ I1 => gtwiz_reset_tx_pll_and_datapath_dly,
+ I2 => Q(0),
+ I3 => sm_reset_tx_pll_timer_sat,
+ I4 => \FSM_sequential_sm_reset_tx[2]_i_5\,
+ O => i_in_out_reg_0
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => in0,
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => gtwiz_reset_tx_datapath_dly,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_13 is
+ port (
+ gtwiz_reset_tx_pll_and_datapath_dly : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ in0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_13 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_13;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_13 is
+ signal \^gtwiz_reset_tx_pll_and_datapath_dly\ : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[0]_i_1\ : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[1]_i_1\ : label is "soft_lutpair1";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+ gtwiz_reset_tx_pll_and_datapath_dly <= \^gtwiz_reset_tx_pll_and_datapath_dly\;
+\FSM_sequential_sm_reset_tx[0]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0F3E"
+ )
+ port map (
+ I0 => \^gtwiz_reset_tx_pll_and_datapath_dly\,
+ I1 => Q(2),
+ I2 => Q(0),
+ I3 => Q(1),
+ O => D(0)
+ );
+\FSM_sequential_sm_reset_tx[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0FF1"
+ )
+ port map (
+ I0 => \^gtwiz_reset_tx_pll_and_datapath_dly\,
+ I1 => Q(2),
+ I2 => Q(1),
+ I3 => Q(0),
+ O => D(1)
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => in0,
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \^gtwiz_reset_tx_pll_and_datapath_dly\,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_14 is
+ port (
+ \sm_reset_rx_timer_clr0__0\ : out STD_LOGIC;
+ gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxuserrdy_out_reg : in STD_LOGIC;
+ sm_reset_rx_timer_sat : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_14 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_14;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_14 is
+ signal gtwiz_reset_userclk_rx_active_sync : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => gtwiz_userclk_rx_active_in(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => gtwiz_reset_userclk_rx_active_sync,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+sm_reset_rx_timer_clr_i_3: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"40"
+ )
+ port map (
+ I0 => rxuserrdy_out_reg,
+ I1 => sm_reset_rx_timer_sat,
+ I2 => gtwiz_reset_userclk_rx_active_sync,
+ O => \sm_reset_rx_timer_clr0__0\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_15 is
+ port (
+ \FSM_sequential_sm_reset_tx_reg[1]\ : out STD_LOGIC;
+ \sm_reset_tx_timer_clr0__0\ : out STD_LOGIC;
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ gtwiz_reset_tx_any_sync : in STD_LOGIC;
+ GTHE3_CHANNEL_TXUSERRDY : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \gtwiz_reset_tx_done_int0__0\ : in STD_LOGIC;
+ \FSM_sequential_sm_reset_tx_reg[0]\ : in STD_LOGIC;
+ txuserrdy_out_reg : in STD_LOGIC;
+ sm_reset_tx_timer_sat : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_15 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_15;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_15 is
+ signal gtwiz_reset_userclk_tx_active_sync : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ signal \^sm_reset_tx_timer_clr0__0\ : STD_LOGIC;
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+ \sm_reset_tx_timer_clr0__0\ <= \^sm_reset_tx_timer_clr0__0\;
+\FSM_sequential_sm_reset_tx[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000F0CCF0AAF0"
+ )
+ port map (
+ I0 => \^sm_reset_tx_timer_clr0__0\,
+ I1 => \gtwiz_reset_tx_done_int0__0\,
+ I2 => \FSM_sequential_sm_reset_tx_reg[0]\,
+ I3 => Q(2),
+ I4 => Q(0),
+ I5 => Q(1),
+ O => E(0)
+ );
+\FSM_sequential_sm_reset_tx[2]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"40"
+ )
+ port map (
+ I0 => txuserrdy_out_reg,
+ I1 => sm_reset_tx_timer_sat,
+ I2 => gtwiz_reset_userclk_tx_active_sync,
+ O => \^sm_reset_tx_timer_clr0__0\
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => gtwiz_userclk_tx_active_in(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => gtwiz_reset_userclk_tx_active_sync,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+txuserrdy_out_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF9F900001000"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => Q(0),
+ I2 => Q(2),
+ I3 => \^sm_reset_tx_timer_clr0__0\,
+ I4 => gtwiz_reset_tx_any_sync,
+ I5 => GTHE3_CHANNEL_TXUSERRDY(0),
+ O => \FSM_sequential_sm_reset_tx_reg[1]\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_16 is
+ port (
+ i_in_out_reg_0 : out STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[0]\ : out STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[2]\ : out STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[2]_0\ : out STD_LOGIC;
+ i_in_out_reg_1 : out STD_LOGIC;
+ i_in_meta_reg_0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \p_0_in11_out__0\ : in STD_LOGIC;
+ gtwiz_reset_rx_done_int_reg : in STD_LOGIC;
+ \sm_reset_rx_timer_clr0__0\ : in STD_LOGIC;
+ sm_reset_rx_timer_clr_reg : in STD_LOGIC;
+ sm_reset_rx_cdr_to_clr_reg : in STD_LOGIC;
+ sm_reset_rx_cdr_to_clr : in STD_LOGIC;
+ gtwiz_reset_rx_any_sync : in STD_LOGIC;
+ GTHE3_CHANNEL_GTRXRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \sm_reset_rx_timer_clr010_out__0\ : in STD_LOGIC;
+ sm_reset_rx_timer_sat : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_16 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_16;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_16 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ signal plllock_rx_sync : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_clr_i_2_n_0 : STD_LOGIC;
+ signal sm_reset_rx_timer_clr_i_2_n_0 : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_rx[2]_i_4\ : label is "soft_lutpair2";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+ attribute SOFT_HLUTNM of sm_reset_rx_cdr_to_clr_i_2 : label is "soft_lutpair2";
+begin
+\FSM_sequential_sm_reset_rx[2]_i_4\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00B0"
+ )
+ port map (
+ I0 => plllock_rx_sync,
+ I1 => Q(0),
+ I2 => sm_reset_rx_timer_sat,
+ I3 => sm_reset_rx_timer_clr_reg,
+ O => i_in_out_reg_1
+ );
+gtrxreset_out_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFBFFF00001514"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => Q(1),
+ I2 => Q(0),
+ I3 => sm_reset_rx_cdr_to_clr_i_2_n_0,
+ I4 => gtwiz_reset_rx_any_sync,
+ I5 => GTHE3_CHANNEL_GTRXRESET(0),
+ O => \FSM_sequential_sm_reset_rx_reg[2]_0\
+ );
+gtwiz_reset_rx_done_int_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"BFBFFFFF0C000000"
+ )
+ port map (
+ I0 => plllock_rx_sync,
+ I1 => Q(1),
+ I2 => Q(0),
+ I3 => \p_0_in11_out__0\,
+ I4 => Q(2),
+ I5 => gtwiz_reset_rx_done_int_reg,
+ O => i_in_out_reg_0
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta_reg_0,
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => plllock_rx_sync,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+sm_reset_rx_cdr_to_clr_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FBFFFFFF0000040F"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => sm_reset_rx_cdr_to_clr_i_2_n_0,
+ I2 => sm_reset_rx_cdr_to_clr_reg,
+ I3 => Q(0),
+ I4 => Q(1),
+ I5 => sm_reset_rx_cdr_to_clr,
+ O => \FSM_sequential_sm_reset_rx_reg[2]\
+ );
+sm_reset_rx_cdr_to_clr_i_2: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0800"
+ )
+ port map (
+ I0 => plllock_rx_sync,
+ I1 => Q(1),
+ I2 => sm_reset_rx_timer_clr_reg,
+ I3 => sm_reset_rx_timer_sat,
+ O => sm_reset_rx_cdr_to_clr_i_2_n_0
+ );
+sm_reset_rx_timer_clr_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAEFAAFF0AE0AA0F"
+ )
+ port map (
+ I0 => sm_reset_rx_timer_clr_i_2_n_0,
+ I1 => \sm_reset_rx_timer_clr0__0\,
+ I2 => Q(0),
+ I3 => Q(1),
+ I4 => Q(2),
+ I5 => sm_reset_rx_timer_clr_reg,
+ O => \FSM_sequential_sm_reset_rx_reg[0]\
+ );
+sm_reset_rx_timer_clr_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8F808F8F80808080"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => \p_0_in11_out__0\,
+ I2 => Q(2),
+ I3 => plllock_rx_sync,
+ I4 => Q(0),
+ I5 => \sm_reset_rx_timer_clr010_out__0\,
+ O => sm_reset_rx_timer_clr_i_2_n_0
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_17 is
+ port (
+ i_in_out_reg_0 : out STD_LOGIC;
+ \FSM_sequential_sm_reset_tx_reg[2]\ : out STD_LOGIC;
+ \FSM_sequential_sm_reset_tx_reg[0]\ : out STD_LOGIC;
+ i_in_out_reg_1 : out STD_LOGIC;
+ qpll1lock_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sm_reset_tx_timer_sat : in STD_LOGIC;
+ sm_reset_tx_timer_clr_reg : in STD_LOGIC;
+ \gtwiz_reset_tx_done_int0__0\ : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ gtwiz_reset_tx_done_int_reg : in STD_LOGIC;
+ \sm_reset_tx_timer_clr0__0\ : in STD_LOGIC;
+ gtwiz_reset_tx_any_sync : in STD_LOGIC;
+ GTHE3_CHANNEL_GTTXRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \FSM_sequential_sm_reset_tx_reg[0]_0\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_17 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_17;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_17 is
+ signal gttxreset_out_i_2_n_0 : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ signal plllock_tx_sync : STD_LOGIC;
+ signal sm_reset_tx_timer_clr_i_2_n_0 : STD_LOGIC;
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+\FSM_sequential_sm_reset_tx[2]_i_5\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00B0FFFF00B00000"
+ )
+ port map (
+ I0 => plllock_tx_sync,
+ I1 => Q(0),
+ I2 => sm_reset_tx_timer_sat,
+ I3 => sm_reset_tx_timer_clr_reg,
+ I4 => Q(1),
+ I5 => \FSM_sequential_sm_reset_tx_reg[0]_0\,
+ O => i_in_out_reg_1
+ );
+gttxreset_out_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"7F7F7F7F2A2A2A3E"
+ )
+ port map (
+ I0 => gttxreset_out_i_2_n_0,
+ I1 => Q(0),
+ I2 => Q(1),
+ I3 => gtwiz_reset_tx_any_sync,
+ I4 => Q(2),
+ I5 => GTHE3_CHANNEL_GTTXRESET(0),
+ O => \FSM_sequential_sm_reset_tx_reg[0]\
+ );
+gttxreset_out_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000002000000000"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_sat,
+ I1 => sm_reset_tx_timer_clr_reg,
+ I2 => plllock_tx_sync,
+ I3 => gtwiz_reset_tx_any_sync,
+ I4 => Q(2),
+ I5 => Q(1),
+ O => gttxreset_out_i_2_n_0
+ );
+gtwiz_reset_tx_done_int_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAFFFFFF0000C000"
+ )
+ port map (
+ I0 => plllock_tx_sync,
+ I1 => \gtwiz_reset_tx_done_int0__0\,
+ I2 => Q(0),
+ I3 => Q(2),
+ I4 => Q(1),
+ I5 => gtwiz_reset_tx_done_int_reg,
+ O => i_in_out_reg_0
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => qpll1lock_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => plllock_tx_sync,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+sm_reset_tx_timer_clr_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAAFFAEF0AA00AEF"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_clr_i_2_n_0,
+ I1 => \sm_reset_tx_timer_clr0__0\,
+ I2 => Q(2),
+ I3 => Q(1),
+ I4 => Q(0),
+ I5 => sm_reset_tx_timer_clr_reg,
+ O => \FSM_sequential_sm_reset_tx_reg[2]\
+ );
+sm_reset_tx_timer_clr_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F022F00000220022"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_sat,
+ I1 => sm_reset_tx_timer_clr_reg,
+ I2 => \gtwiz_reset_tx_done_int0__0\,
+ I3 => Q(2),
+ I4 => plllock_tx_sync,
+ I5 => Q(0),
+ O => sm_reset_tx_timer_clr_i_2_n_0
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_18 is
+ port (
+ i_in_out_reg_0 : out STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[2]\ : out STD_LOGIC;
+ i_in_out_reg_1 : out STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[2]_0\ : out STD_LOGIC;
+ i_in_meta_reg_0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ gtwiz_reset_rx_any_sync : in STD_LOGIC;
+ GTHE3_CHANNEL_RXPROGDIVRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sm_reset_rx_cdr_to_sat : in STD_LOGIC;
+ \sm_reset_rx_timer_clr0__0\ : in STD_LOGIC;
+ \p_0_in11_out__0\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_18 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_18;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_18 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal \^i_in_out_reg_0\ : STD_LOGIC;
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ signal \sm_reset_rx_cdr_to_clr0__0\ : STD_LOGIC;
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of rxprogdivreset_out_i_2 : label is "soft_lutpair3";
+ attribute SOFT_HLUTNM of sm_reset_rx_cdr_to_clr_i_3 : label is "soft_lutpair3";
+begin
+ i_in_out_reg_0 <= \^i_in_out_reg_0\;
+\FSM_sequential_sm_reset_rx[2]_i_5\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000F0F0FF00EEEE"
+ )
+ port map (
+ I0 => \^i_in_out_reg_0\,
+ I1 => sm_reset_rx_cdr_to_sat,
+ I2 => \sm_reset_rx_timer_clr0__0\,
+ I3 => \p_0_in11_out__0\,
+ I4 => Q(1),
+ I5 => Q(0),
+ O => i_in_out_reg_1
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta_reg_0,
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \^i_in_out_reg_0\,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+rxprogdivreset_out_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFDFF00001414"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => Q(1),
+ I2 => Q(0),
+ I3 => \sm_reset_rx_cdr_to_clr0__0\,
+ I4 => gtwiz_reset_rx_any_sync,
+ I5 => GTHE3_CHANNEL_RXPROGDIVRESET(0),
+ O => \FSM_sequential_sm_reset_rx_reg[2]\
+ );
+rxprogdivreset_out_i_2: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_sat,
+ I1 => \^i_in_out_reg_0\,
+ O => \sm_reset_rx_cdr_to_clr0__0\
+ );
+sm_reset_rx_cdr_to_clr_i_3: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"02"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => \^i_in_out_reg_0\,
+ I2 => sm_reset_rx_cdr_to_sat,
+ O => \FSM_sequential_sm_reset_rx_reg[2]_0\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_2 is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ txresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_2 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_2;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_2 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => txresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_3 is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_3 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_3;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_3 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rxresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_4 is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ txresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_4 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_4;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_4 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => txresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_5 is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_5 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_5;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_5 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rxresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_6 is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ txresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_6 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_6;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_6 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => txresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_7 is
+ port (
+ \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[1]\ : out STD_LOGIC;
+ GTHE3_CHANNEL_TXPHALIGNDONE : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_7 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_7;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_7 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_out : STD_LOGIC;
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_error_out_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => i_in_out,
+ O => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[1]\
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => GTHE3_CHANNEL_TXPHALIGNDONE(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => i_in_out,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_8 is
+ port (
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\ : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ GTHE3_CHANNEL_TXSYNCDONE : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_8 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_8;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_8 is
+ signal \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\ : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx[0]_i_1\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx[1]_i_2\ : label is "soft_lutpair20";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\ <= \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\;
+\FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx[0]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0455"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\,
+ I2 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\,
+ I3 => Q(1),
+ O => D(0)
+ );
+\FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx[1]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"2622"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => Q(1),
+ I2 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\,
+ I3 => \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\,
+ O => D(1)
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => GTHE3_CHANNEL_TXSYNCDONE(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_9 is
+ port (
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ in0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \FSM_sequential_sm_reset_all_reg[0]\ : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \FSM_sequential_sm_reset_all_reg[0]_0\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_9 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_9;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_9 is
+ signal gtpowergood_sync : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+\FSM_sequential_sm_reset_all[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AF0FAF00CFFFCFFF"
+ )
+ port map (
+ I0 => gtpowergood_sync,
+ I1 => \FSM_sequential_sm_reset_all_reg[0]\,
+ I2 => Q(2),
+ I3 => Q(0),
+ I4 => \FSM_sequential_sm_reset_all_reg[0]_0\,
+ I5 => Q(1),
+ O => E(0)
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => in0,
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => gtpowergood_sync,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gthe3_channel is
+ port (
+ cplllock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxn_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxp_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtpowergood_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrlock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXPHALIGNDONE : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXSYNCDONE : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 79 downto 0 );
+ GTHE3_CHANNEL_CPLLPD : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxn_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxp_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_GTRXRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_GTTXRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outrefclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outrefclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxcdrhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_RXPROGDIVRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxslide_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_RXUSERRDY : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXDLYSRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXPROGDIVRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXSYNCALLIN : in STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXUSERRDY : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 79 downto 0 );
+ loopback_in : in STD_LOGIC_VECTOR ( 11 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gthe3_channel : entity is "gtwizard_ultrascale_v1_7_18_gthe3_channel";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gthe3_channel;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gthe3_channel is
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_0\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_10\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_100\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_101\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_102\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_103\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_104\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_105\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_106\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_107\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_108\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_109\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_11\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_110\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_111\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_112\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_113\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_114\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_115\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_116\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_117\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_118\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_119\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_12\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_120\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_121\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_122\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_123\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_124\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_125\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_126\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_127\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_128\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_129\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_13\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_130\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_131\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_132\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_133\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_134\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_135\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_136\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_137\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_138\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_139\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_14\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_140\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_141\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_142\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_143\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_144\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_145\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_146\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_147\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_148\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_149\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_15\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_150\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_151\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_152\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_153\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_154\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_155\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_156\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_157\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_158\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_159\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_16\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_160\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_161\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_162\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_163\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_164\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_165\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_166\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_167\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_168\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_169\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_17\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_170\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_171\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_172\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_173\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_174\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_175\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_176\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_177\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_178\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_179\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_18\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_180\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_181\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_182\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_183\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_184\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_185\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_186\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_187\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_188\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_189\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_190\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_191\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_192\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_193\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_2\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_20\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_21\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_210\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_211\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_212\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_213\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_214\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_215\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_216\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_217\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_218\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_219\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_22\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_220\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_221\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_222\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_223\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_224\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_225\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_226\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_227\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_228\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_229\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_23\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_230\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_231\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_232\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_233\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_234\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_235\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_236\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_237\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_238\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_239\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_24\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_242\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_243\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_244\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_245\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_246\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_247\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_248\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_249\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_25\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_250\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_251\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_252\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_253\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_254\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_255\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_258\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_259\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_26\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_260\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_261\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_262\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_263\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_264\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_265\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_266\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_267\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_268\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_269\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_27\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_270\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_271\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_272\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_273\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_274\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_275\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_276\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_277\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_278\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_279\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_28\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_280\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_281\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_282\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_283\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_284\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_285\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_286\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_287\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_288\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_289\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_29\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_290\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_291\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_292\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_293\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_294\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_295\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_296\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_297\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_298\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_299\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_3\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_30\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_300\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_301\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_302\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_303\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_304\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_305\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_306\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_307\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_308\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_309\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_31\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_310\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_311\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_312\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_313\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_314\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_315\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_316\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_317\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_318\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_319\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_32\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_320\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_321\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_322\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_323\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_324\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_325\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_326\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_327\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_328\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_329\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_33\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_330\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_331\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_332\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_333\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_334\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_335\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_336\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_337\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_338\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_339\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_340\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_341\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_342\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_343\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_344\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_345\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_346\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_347\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_348\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_349\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_35\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_350\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_351\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_352\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_353\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_354\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_355\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_356\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_357\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_358\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_359\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_36\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_360\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_361\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_362\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_363\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_364\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_365\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_37\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_38\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_4\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_40\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_41\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_42\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_43\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_44\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_45\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_46\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_48\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_49\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_50\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_51\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_52\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_53\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_54\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_55\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_56\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_58\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_59\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_61\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_63\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_64\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_65\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_66\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_70\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_71\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_72\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_73\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_74\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_75\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_76\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_77\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_78\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_79\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_8\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_80\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_81\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_82\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_83\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_84\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_85\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_86\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_87\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_88\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_89\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_9\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_90\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_91\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_92\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_93\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_94\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_95\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_96\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_97\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_98\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_99\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_0\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_10\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_100\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_101\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_102\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_103\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_104\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_105\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_106\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_107\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_108\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_109\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_11\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_110\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_111\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_112\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_113\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_114\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_115\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_116\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_117\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_118\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_119\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_12\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_120\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_121\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_122\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_123\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_124\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_125\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_126\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_127\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_128\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_129\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_13\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_130\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_131\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_132\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_133\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_134\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_135\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_136\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_137\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_138\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_139\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_14\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_140\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_141\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_142\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_143\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_144\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_145\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_146\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_147\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_148\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_149\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_15\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_150\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_151\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_152\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_153\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_154\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_155\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_156\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_157\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_158\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_159\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_16\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_160\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_161\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_162\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_163\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_164\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_165\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_166\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_167\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_168\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_169\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_17\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_170\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_171\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_172\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_173\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_174\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_175\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_176\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_177\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_178\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_179\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_18\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_180\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_181\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_182\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_183\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_184\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_185\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_186\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_187\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_188\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_189\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_190\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_191\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_192\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_193\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_2\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_20\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_21\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_210\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_211\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_212\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_213\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_214\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_215\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_216\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_217\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_218\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_219\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_22\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_220\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_221\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_222\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_223\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_224\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_225\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_226\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_227\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_228\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_229\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_23\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_230\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_231\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_232\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_233\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_234\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_235\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_236\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_237\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_238\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_239\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_24\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_242\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_243\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_244\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_245\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_246\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_247\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_248\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_249\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_25\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_250\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_251\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_252\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_253\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_254\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_255\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_258\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_259\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_26\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_260\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_261\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_262\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_263\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_264\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_265\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_266\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_267\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_268\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_269\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_27\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_270\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_271\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_272\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_273\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_274\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_275\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_276\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_277\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_278\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_279\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_28\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_280\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_281\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_282\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_283\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_284\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_285\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_286\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_287\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_288\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_289\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_29\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_290\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_291\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_292\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_293\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_294\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_295\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_296\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_297\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_298\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_299\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_3\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_30\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_300\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_301\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_302\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_303\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_304\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_305\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_306\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_307\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_308\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_309\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_31\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_310\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_311\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_312\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_313\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_314\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_315\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_316\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_317\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_318\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_319\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_32\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_320\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_321\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_322\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_323\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_324\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_325\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_326\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_327\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_328\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_329\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_33\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_330\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_331\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_332\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_333\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_334\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_335\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_336\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_337\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_338\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_339\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_340\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_341\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_342\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_343\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_344\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_345\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_346\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_347\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_348\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_349\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_35\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_350\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_351\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_352\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_353\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_354\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_355\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_356\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_357\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_358\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_359\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_36\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_360\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_361\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_362\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_363\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_364\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_365\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_37\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_38\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_4\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_40\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_41\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_42\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_43\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_44\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_45\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_46\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_48\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_49\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_50\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_51\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_52\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_53\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_54\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_55\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_56\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_58\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_59\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_61\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_63\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_64\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_65\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_66\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_68\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_69\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_70\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_71\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_72\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_73\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_74\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_75\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_76\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_77\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_78\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_79\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_8\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_80\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_81\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_82\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_83\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_84\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_85\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_86\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_87\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_88\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_89\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_9\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_90\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_91\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_92\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_93\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_94\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_95\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_96\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_97\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_98\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_99\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_0\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_10\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_100\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_101\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_102\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_103\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_104\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_105\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_106\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_107\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_108\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_109\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_11\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_110\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_111\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_112\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_113\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_114\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_115\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_116\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_117\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_118\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_119\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_12\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_120\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_121\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_122\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_123\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_124\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_125\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_126\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_127\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_128\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_129\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_13\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_130\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_131\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_132\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_133\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_134\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_135\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_136\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_137\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_138\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_139\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_14\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_140\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_141\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_142\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_143\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_144\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_145\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_146\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_147\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_148\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_149\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_15\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_150\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_151\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_152\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_153\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_154\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_155\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_156\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_157\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_158\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_159\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_16\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_160\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_161\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_162\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_163\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_164\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_165\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_166\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_167\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_168\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_169\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_17\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_170\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_171\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_172\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_173\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_174\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_175\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_176\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_177\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_178\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_179\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_18\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_180\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_181\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_182\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_183\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_184\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_185\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_186\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_187\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_188\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_189\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_190\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_191\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_192\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_193\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_2\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_20\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_21\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_210\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_211\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_212\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_213\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_214\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_215\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_216\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_217\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_218\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_219\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_22\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_220\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_221\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_222\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_223\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_224\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_225\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_226\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_227\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_228\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_229\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_23\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_230\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_231\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_232\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_233\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_234\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_235\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_236\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_237\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_238\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_239\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_24\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_242\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_243\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_244\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_245\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_246\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_247\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_248\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_249\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_25\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_250\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_251\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_252\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_253\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_254\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_255\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_258\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_259\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_26\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_260\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_261\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_262\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_263\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_264\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_265\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_266\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_267\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_268\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_269\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_27\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_270\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_271\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_272\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_273\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_274\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_275\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_276\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_277\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_278\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_279\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_28\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_280\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_281\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_282\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_283\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_284\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_285\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_286\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_287\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_288\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_289\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_29\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_290\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_291\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_292\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_293\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_294\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_295\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_296\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_297\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_298\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_299\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_3\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_30\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_300\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_301\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_302\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_303\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_304\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_305\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_306\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_307\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_308\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_309\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_31\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_310\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_311\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_312\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_313\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_314\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_315\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_316\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_317\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_318\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_319\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_32\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_320\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_321\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_322\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_323\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_324\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_325\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_326\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_327\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_328\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_329\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_33\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_330\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_331\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_332\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_333\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_334\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_335\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_336\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_337\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_338\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_339\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_340\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_341\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_342\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_343\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_344\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_345\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_346\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_347\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_348\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_349\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_35\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_350\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_351\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_352\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_353\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_354\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_355\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_356\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_357\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_358\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_359\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_36\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_360\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_361\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_362\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_363\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_364\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_365\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_37\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_38\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_4\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_40\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_41\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_42\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_43\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_44\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_45\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_46\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_48\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_49\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_50\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_51\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_52\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_53\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_54\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_55\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_56\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_58\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_59\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_61\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_63\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_64\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_65\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_66\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_68\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_69\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_70\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_71\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_72\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_73\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_74\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_75\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_76\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_77\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_78\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_79\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_8\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_80\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_81\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_82\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_83\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_84\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_85\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_86\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_87\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_88\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_89\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_9\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_90\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_91\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_92\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_93\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_94\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_95\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_96\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_97\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_98\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_99\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_0\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_10\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_100\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_101\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_102\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_103\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_104\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_105\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_106\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_107\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_108\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_109\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_11\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_110\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_111\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_112\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_113\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_114\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_115\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_116\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_117\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_118\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_119\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_12\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_120\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_121\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_122\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_123\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_124\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_125\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_126\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_127\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_128\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_129\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_13\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_130\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_131\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_132\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_133\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_134\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_135\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_136\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_137\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_138\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_139\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_14\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_140\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_141\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_142\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_143\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_144\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_145\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_146\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_147\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_148\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_149\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_15\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_150\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_151\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_152\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_153\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_154\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_155\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_156\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_157\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_158\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_159\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_16\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_160\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_161\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_162\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_163\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_164\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_165\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_166\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_167\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_168\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_169\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_17\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_170\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_171\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_172\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_173\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_174\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_175\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_176\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_177\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_178\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_179\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_18\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_180\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_181\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_182\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_183\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_184\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_185\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_186\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_187\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_188\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_189\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_190\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_191\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_192\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_193\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_2\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_20\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_21\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_210\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_211\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_212\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_213\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_214\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_215\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_216\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_217\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_218\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_219\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_22\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_220\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_221\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_222\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_223\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_224\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_225\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_226\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_227\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_228\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_229\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_23\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_230\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_231\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_232\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_233\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_234\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_235\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_236\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_237\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_238\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_239\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_24\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_242\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_243\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_244\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_245\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_246\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_247\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_248\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_249\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_25\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_250\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_251\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_252\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_253\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_254\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_255\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_258\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_259\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_26\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_260\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_261\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_262\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_263\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_264\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_265\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_266\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_267\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_268\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_269\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_27\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_270\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_271\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_272\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_273\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_274\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_275\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_276\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_277\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_278\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_279\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_28\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_280\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_281\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_282\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_283\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_284\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_285\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_286\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_287\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_288\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_289\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_29\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_290\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_291\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_292\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_293\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_294\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_295\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_296\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_297\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_298\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_299\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_3\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_30\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_300\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_301\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_302\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_303\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_304\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_305\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_306\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_307\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_308\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_309\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_31\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_310\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_311\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_312\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_313\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_314\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_315\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_316\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_317\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_318\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_319\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_32\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_320\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_321\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_322\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_323\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_324\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_325\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_326\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_327\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_328\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_329\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_33\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_330\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_331\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_332\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_333\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_334\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_335\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_336\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_337\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_338\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_339\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_340\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_341\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_342\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_343\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_344\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_345\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_346\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_347\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_348\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_349\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_35\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_350\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_351\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_352\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_353\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_354\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_355\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_356\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_357\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_358\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_359\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_36\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_360\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_361\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_362\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_363\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_364\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_365\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_37\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_38\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_4\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_40\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_41\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_42\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_43\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_44\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_45\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_46\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_48\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_49\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_50\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_51\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_52\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_53\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_54\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_55\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_56\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_58\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_59\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_61\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_63\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_64\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_65\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_66\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_68\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_69\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_70\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_71\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_72\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_73\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_74\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_75\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_76\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_77\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_78\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_79\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_8\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_80\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_81\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_82\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_83\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_84\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_85\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_86\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_87\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_88\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_89\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_9\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_90\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_91\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_92\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_93\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_94\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_95\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_96\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_97\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_98\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_99\ : STD_LOGIC;
+ attribute BOX_TYPE : string;
+ attribute BOX_TYPE of \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST\ : label is "PRIMITIVE";
+begin
+\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST\: unisim.vcomponents.GTHE3_CHANNEL
+ generic map(
+ ACJTAG_DEBUG_MODE => '0',
+ ACJTAG_MODE => '0',
+ ACJTAG_RESET => '0',
+ ADAPT_CFG0 => X"F800",
+ ADAPT_CFG1 => X"0000",
+ ALIGN_COMMA_DOUBLE => "FALSE",
+ ALIGN_COMMA_ENABLE => B"0000000000",
+ ALIGN_COMMA_WORD => 1,
+ ALIGN_MCOMMA_DET => "FALSE",
+ ALIGN_MCOMMA_VALUE => B"1010000011",
+ ALIGN_PCOMMA_DET => "FALSE",
+ ALIGN_PCOMMA_VALUE => B"0101111100",
+ A_RXOSCALRESET => '0',
+ A_RXPROGDIVRESET => '0',
+ A_TXPROGDIVRESET => '0',
+ CBCC_DATA_SOURCE_SEL => "ENCODED",
+ CDR_SWAP_MODE_EN => '0',
+ CHAN_BOND_KEEP_ALIGN => "FALSE",
+ CHAN_BOND_MAX_SKEW => 1,
+ CHAN_BOND_SEQ_1_1 => B"0000000000",
+ CHAN_BOND_SEQ_1_2 => B"0000000000",
+ CHAN_BOND_SEQ_1_3 => B"0000000000",
+ CHAN_BOND_SEQ_1_4 => B"0000000000",
+ CHAN_BOND_SEQ_1_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_1 => B"0000000000",
+ CHAN_BOND_SEQ_2_2 => B"0000000000",
+ CHAN_BOND_SEQ_2_3 => B"0000000000",
+ CHAN_BOND_SEQ_2_4 => B"0000000000",
+ CHAN_BOND_SEQ_2_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_USE => "FALSE",
+ CHAN_BOND_SEQ_LEN => 1,
+ CLK_CORRECT_USE => "FALSE",
+ CLK_COR_KEEP_IDLE => "FALSE",
+ CLK_COR_MAX_LAT => 6,
+ CLK_COR_MIN_LAT => 4,
+ CLK_COR_PRECEDENCE => "TRUE",
+ CLK_COR_REPEAT_WAIT => 0,
+ CLK_COR_SEQ_1_1 => B"0000000000",
+ CLK_COR_SEQ_1_2 => B"0000000000",
+ CLK_COR_SEQ_1_3 => B"0000000000",
+ CLK_COR_SEQ_1_4 => B"0000000000",
+ CLK_COR_SEQ_1_ENABLE => B"1111",
+ CLK_COR_SEQ_2_1 => B"0000000000",
+ CLK_COR_SEQ_2_2 => B"0000000000",
+ CLK_COR_SEQ_2_3 => B"0000000000",
+ CLK_COR_SEQ_2_4 => B"0000000000",
+ CLK_COR_SEQ_2_ENABLE => B"1111",
+ CLK_COR_SEQ_2_USE => "FALSE",
+ CLK_COR_SEQ_LEN => 1,
+ CPLL_CFG0 => X"67F8",
+ CPLL_CFG1 => X"A4AC",
+ CPLL_CFG2 => X"5007",
+ CPLL_CFG3 => B"00" & X"0",
+ CPLL_FBDIV => 2,
+ CPLL_FBDIV_45 => 5,
+ CPLL_INIT_CFG0 => X"02B2",
+ CPLL_INIT_CFG1 => X"00",
+ CPLL_LOCK_CFG => X"01E8",
+ CPLL_REFCLK_DIV => 1,
+ DDI_CTRL => B"00",
+ DDI_REALIGN_WAIT => 15,
+ DEC_MCOMMA_DETECT => "FALSE",
+ DEC_PCOMMA_DETECT => "FALSE",
+ DEC_VALID_COMMA_ONLY => "FALSE",
+ DFE_D_X_REL_POS => '0',
+ DFE_VCM_COMP_EN => '0',
+ DMONITOR_CFG0 => B"00" & X"00",
+ DMONITOR_CFG1 => X"00",
+ ES_CLK_PHASE_SEL => '0',
+ ES_CONTROL => B"000000",
+ ES_ERRDET_EN => "FALSE",
+ ES_EYE_SCAN_EN => "FALSE",
+ ES_HORZ_OFFSET => X"000",
+ ES_PMA_CFG => B"0000000000",
+ ES_PRESCALE => B"00000",
+ ES_QUALIFIER0 => X"0000",
+ ES_QUALIFIER1 => X"0000",
+ ES_QUALIFIER2 => X"0000",
+ ES_QUALIFIER3 => X"0000",
+ ES_QUALIFIER4 => X"0000",
+ ES_QUAL_MASK0 => X"0000",
+ ES_QUAL_MASK1 => X"0000",
+ ES_QUAL_MASK2 => X"0000",
+ ES_QUAL_MASK3 => X"0000",
+ ES_QUAL_MASK4 => X"0000",
+ ES_SDATA_MASK0 => X"0000",
+ ES_SDATA_MASK1 => X"0000",
+ ES_SDATA_MASK2 => X"0000",
+ ES_SDATA_MASK3 => X"0000",
+ ES_SDATA_MASK4 => X"0000",
+ EVODD_PHI_CFG => B"00000000000",
+ EYE_SCAN_SWAP_EN => '0',
+ FTS_DESKEW_SEQ_ENABLE => B"1111",
+ FTS_LANE_DESKEW_CFG => B"1111",
+ FTS_LANE_DESKEW_EN => "FALSE",
+ GEARBOX_MODE => B"00000",
+ GM_BIAS_SELECT => '0',
+ LOCAL_MASTER => '1',
+ OOBDIVCTL => B"00",
+ OOB_PWRUP => '0',
+ PCI3_AUTO_REALIGN => "OVR_1K_BLK",
+ PCI3_PIPE_RX_ELECIDLE => '0',
+ PCI3_RX_ASYNC_EBUF_BYPASS => B"00",
+ PCI3_RX_ELECIDLE_EI2_ENABLE => '0',
+ PCI3_RX_ELECIDLE_H2L_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_H2L_DISABLE => B"000",
+ PCI3_RX_ELECIDLE_HI_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_LP4_DISABLE => '0',
+ PCI3_RX_FIFO_DISABLE => '0',
+ PCIE_BUFG_DIV_CTRL => X"1000",
+ PCIE_RXPCS_CFG_GEN3 => X"02A4",
+ PCIE_RXPMA_CFG => X"000A",
+ PCIE_TXPCS_CFG_GEN3 => X"24A4",
+ PCIE_TXPMA_CFG => X"000A",
+ PCS_PCIE_EN => "FALSE",
+ PCS_RSVD0 => B"0000000000000000",
+ PCS_RSVD1 => B"000",
+ PD_TRANS_TIME_FROM_P2 => X"03C",
+ PD_TRANS_TIME_NONE_P2 => X"19",
+ PD_TRANS_TIME_TO_P2 => X"64",
+ PLL_SEL_MODE_GEN12 => B"00",
+ PLL_SEL_MODE_GEN3 => B"11",
+ PMA_RSV1 => X"F000",
+ PROCESS_PAR => B"010",
+ RATE_SW_USE_DRP => '1',
+ RESET_POWERSAVE_DISABLE => '0',
+ RXBUFRESET_TIME => B"00011",
+ RXBUF_ADDR_MODE => "FAST",
+ RXBUF_EIDLE_HI_CNT => B"1000",
+ RXBUF_EIDLE_LO_CNT => B"0000",
+ RXBUF_EN => "TRUE",
+ RXBUF_RESET_ON_CB_CHANGE => "TRUE",
+ RXBUF_RESET_ON_COMMAALIGN => "FALSE",
+ RXBUF_RESET_ON_EIDLE => "FALSE",
+ RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ RXBUF_THRESH_OVFLW => 61,
+ RXBUF_THRESH_OVRD => "TRUE",
+ RXBUF_THRESH_UNDFLW => 1,
+ RXCDRFREQRESET_TIME => B"00001",
+ RXCDRPHRESET_TIME => B"00001",
+ RXCDR_CFG0 => X"0000",
+ RXCDR_CFG0_GEN3 => X"0000",
+ RXCDR_CFG1 => X"0000",
+ RXCDR_CFG1_GEN3 => X"0000",
+ RXCDR_CFG2 => X"07E6",
+ RXCDR_CFG2_GEN3 => X"07E6",
+ RXCDR_CFG3 => X"0000",
+ RXCDR_CFG3_GEN3 => X"0000",
+ RXCDR_CFG4 => X"0000",
+ RXCDR_CFG4_GEN3 => X"0000",
+ RXCDR_CFG5 => X"0000",
+ RXCDR_CFG5_GEN3 => X"0000",
+ RXCDR_FR_RESET_ON_EIDLE => '0',
+ RXCDR_HOLD_DURING_EIDLE => '0',
+ RXCDR_LOCK_CFG0 => X"4480",
+ RXCDR_LOCK_CFG1 => X"5FFF",
+ RXCDR_LOCK_CFG2 => X"77C3",
+ RXCDR_PH_RESET_ON_EIDLE => '0',
+ RXCFOK_CFG0 => X"4000",
+ RXCFOK_CFG1 => X"0065",
+ RXCFOK_CFG2 => X"002E",
+ RXDFELPMRESET_TIME => B"0001111",
+ RXDFELPM_KL_CFG0 => X"0000",
+ RXDFELPM_KL_CFG1 => X"0002",
+ RXDFELPM_KL_CFG2 => X"0000",
+ RXDFE_CFG0 => X"0A00",
+ RXDFE_CFG1 => X"0000",
+ RXDFE_GC_CFG0 => X"0000",
+ RXDFE_GC_CFG1 => X"7870",
+ RXDFE_GC_CFG2 => X"0000",
+ RXDFE_H2_CFG0 => X"0000",
+ RXDFE_H2_CFG1 => X"0000",
+ RXDFE_H3_CFG0 => X"4000",
+ RXDFE_H3_CFG1 => X"0000",
+ RXDFE_H4_CFG0 => X"2000",
+ RXDFE_H4_CFG1 => X"0003",
+ RXDFE_H5_CFG0 => X"2000",
+ RXDFE_H5_CFG1 => X"0003",
+ RXDFE_H6_CFG0 => X"2000",
+ RXDFE_H6_CFG1 => X"0000",
+ RXDFE_H7_CFG0 => X"2000",
+ RXDFE_H7_CFG1 => X"0000",
+ RXDFE_H8_CFG0 => X"2000",
+ RXDFE_H8_CFG1 => X"0000",
+ RXDFE_H9_CFG0 => X"2000",
+ RXDFE_H9_CFG1 => X"0000",
+ RXDFE_HA_CFG0 => X"2000",
+ RXDFE_HA_CFG1 => X"0000",
+ RXDFE_HB_CFG0 => X"2000",
+ RXDFE_HB_CFG1 => X"0000",
+ RXDFE_HC_CFG0 => X"0000",
+ RXDFE_HC_CFG1 => X"0000",
+ RXDFE_HD_CFG0 => X"0000",
+ RXDFE_HD_CFG1 => X"0000",
+ RXDFE_HE_CFG0 => X"0000",
+ RXDFE_HE_CFG1 => X"0000",
+ RXDFE_HF_CFG0 => X"0000",
+ RXDFE_HF_CFG1 => X"0000",
+ RXDFE_OS_CFG0 => X"8000",
+ RXDFE_OS_CFG1 => X"0000",
+ RXDFE_UT_CFG0 => X"8000",
+ RXDFE_UT_CFG1 => X"0003",
+ RXDFE_VP_CFG0 => X"AA00",
+ RXDFE_VP_CFG1 => X"0033",
+ RXDLY_CFG => X"001F",
+ RXDLY_LCFG => X"0030",
+ RXELECIDLE_CFG => "Sigcfg_4",
+ RXGBOX_FIFO_INIT_RD_ADDR => 4,
+ RXGEARBOX_EN => "FALSE",
+ RXISCANRESET_TIME => B"00001",
+ RXLPM_CFG => X"0000",
+ RXLPM_GC_CFG => X"1000",
+ RXLPM_KH_CFG0 => X"0000",
+ RXLPM_KH_CFG1 => X"0002",
+ RXLPM_OS_CFG0 => X"8000",
+ RXLPM_OS_CFG1 => X"0002",
+ RXOOB_CFG => B"000000110",
+ RXOOB_CLK_CFG => "PMA",
+ RXOSCALRESET_TIME => B"00011",
+ RXOUT_DIV => 1,
+ RXPCSRESET_TIME => B"00011",
+ RXPHBEACON_CFG => X"0000",
+ RXPHDLY_CFG => X"2020",
+ RXPHSAMP_CFG => X"2100",
+ RXPHSLIP_CFG => X"6622",
+ RXPH_MONITOR_SEL => B"00000",
+ RXPI_CFG0 => B"00",
+ RXPI_CFG1 => B"00",
+ RXPI_CFG2 => B"00",
+ RXPI_CFG3 => B"00",
+ RXPI_CFG4 => '1',
+ RXPI_CFG5 => '1',
+ RXPI_CFG6 => B"011",
+ RXPI_LPM => '0',
+ RXPI_VREFSEL => '0',
+ RXPMACLK_SEL => "DATA",
+ RXPMARESET_TIME => B"00011",
+ RXPRBS_ERR_LOOPBACK => '0',
+ RXPRBS_LINKACQ_CNT => 15,
+ RXSLIDE_AUTO_WAIT => 7,
+ RXSLIDE_MODE => "PMA",
+ RXSYNC_MULTILANE => '1',
+ RXSYNC_OVRD => '0',
+ RXSYNC_SKIP_DA => '0',
+ RX_AFE_CM_EN => '0',
+ RX_BIAS_CFG0 => X"0AB4",
+ RX_BUFFER_CFG => B"000000",
+ RX_CAPFF_SARC_ENB => '0',
+ RX_CLK25_DIV => 10,
+ RX_CLKMUX_EN => '1',
+ RX_CLK_SLIP_OVRD => B"00000",
+ RX_CM_BUF_CFG => B"1010",
+ RX_CM_BUF_PD => '0',
+ RX_CM_SEL => B"11",
+ RX_CM_TRIM => B"1010",
+ RX_CTLE3_LPF => B"00000001",
+ RX_DATA_WIDTH => 20,
+ RX_DDI_SEL => B"000000",
+ RX_DEFER_RESET_BUF_EN => "TRUE",
+ RX_DFELPM_CFG0 => B"0110",
+ RX_DFELPM_CFG1 => '1',
+ RX_DFELPM_KLKH_AGC_STUP_EN => '1',
+ RX_DFE_AGC_CFG0 => B"10",
+ RX_DFE_AGC_CFG1 => B"100",
+ RX_DFE_KL_LPM_KH_CFG0 => B"01",
+ RX_DFE_KL_LPM_KH_CFG1 => B"100",
+ RX_DFE_KL_LPM_KL_CFG0 => B"01",
+ RX_DFE_KL_LPM_KL_CFG1 => B"100",
+ RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
+ RX_DISPERR_SEQ_MATCH => "TRUE",
+ RX_DIVRESET_TIME => B"00001",
+ RX_EN_HI_LR => '0',
+ RX_EYESCAN_VS_CODE => B"0000000",
+ RX_EYESCAN_VS_NEG_DIR => '0',
+ RX_EYESCAN_VS_RANGE => B"00",
+ RX_EYESCAN_VS_UT_SIGN => '0',
+ RX_FABINT_USRCLK_FLOP => '0',
+ RX_INT_DATAWIDTH => 0,
+ RX_PMA_POWER_SAVE => '0',
+ RX_PROGDIV_CFG => 0.000000,
+ RX_SAMPLE_PERIOD => B"111",
+ RX_SIG_VALID_DLY => 11,
+ RX_SUM_DFETAPREP_EN => '0',
+ RX_SUM_IREF_TUNE => B"0000",
+ RX_SUM_RES_CTRL => B"00",
+ RX_SUM_VCMTUNE => B"0000",
+ RX_SUM_VCM_OVWR => '0',
+ RX_SUM_VREF_TUNE => B"000",
+ RX_TUNE_AFE_OS => B"10",
+ RX_WIDEMODE_CDR => '0',
+ RX_XCLK_SEL => "RXDES",
+ SAS_MAX_COM => 64,
+ SAS_MIN_COM => 36,
+ SATA_BURST_SEQ_LEN => B"1110",
+ SATA_BURST_VAL => B"100",
+ SATA_CPLL_CFG => "VCO_3000MHZ",
+ SATA_EIDLE_VAL => B"100",
+ SATA_MAX_BURST => 8,
+ SATA_MAX_INIT => 21,
+ SATA_MAX_WAKE => 7,
+ SATA_MIN_BURST => 4,
+ SATA_MIN_INIT => 12,
+ SATA_MIN_WAKE => 4,
+ SHOW_REALIGN_COMMA => "FALSE",
+ SIM_MODE => "FAST",
+ SIM_RECEIVER_DETECT_PASS => "TRUE",
+ SIM_RESET_SPEEDUP => "TRUE",
+ SIM_TX_EIDLE_DRIVE_LEVEL => '0',
+ SIM_VERSION => 2,
+ TAPDLY_SET_TX => B"00",
+ TEMPERATUR_PAR => B"0010",
+ TERM_RCAL_CFG => B"100001000010000",
+ TERM_RCAL_OVRD => B"000",
+ TRANS_TIME_RATE => X"0E",
+ TST_RSV0 => X"00",
+ TST_RSV1 => X"00",
+ TXBUF_EN => "FALSE",
+ TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ TXDLY_CFG => X"0009",
+ TXDLY_LCFG => X"0050",
+ TXDRVBIAS_N => B"1010",
+ TXDRVBIAS_P => B"1010",
+ TXFIFO_ADDR_CFG => "LOW",
+ TXGBOX_FIFO_INIT_RD_ADDR => 4,
+ TXGEARBOX_EN => "FALSE",
+ TXOUT_DIV => 2,
+ TXPCSRESET_TIME => B"00011",
+ TXPHDLY_CFG0 => X"2020",
+ TXPHDLY_CFG1 => X"0075",
+ TXPH_CFG => X"0980",
+ TXPH_MONITOR_SEL => B"00000",
+ TXPI_CFG0 => B"00",
+ TXPI_CFG1 => B"00",
+ TXPI_CFG2 => B"00",
+ TXPI_CFG3 => '1',
+ TXPI_CFG4 => '1',
+ TXPI_CFG5 => B"000",
+ TXPI_GRAY_SEL => '0',
+ TXPI_INVSTROBE_SEL => '1',
+ TXPI_LPM => '0',
+ TXPI_PPMCLK_SEL => "TXUSRCLK2",
+ TXPI_PPM_CFG => B"00000000",
+ TXPI_SYNFREQ_PPM => B"001",
+ TXPI_VREFSEL => '0',
+ TXPMARESET_TIME => B"00011",
+ TXSYNC_MULTILANE => '1',
+ TXSYNC_OVRD => '0',
+ TXSYNC_SKIP_DA => '0',
+ TX_CLK25_DIV => 10,
+ TX_CLKMUX_EN => '1',
+ TX_DATA_WIDTH => 20,
+ TX_DCD_CFG => B"000010",
+ TX_DCD_EN => '0',
+ TX_DEEMPH0 => B"000000",
+ TX_DEEMPH1 => B"000000",
+ TX_DIVRESET_TIME => B"00001",
+ TX_DRIVE_MODE => "DIRECT",
+ TX_EIDLE_ASSERT_DELAY => B"100",
+ TX_EIDLE_DEASSERT_DELAY => B"011",
+ TX_EML_PHI_TUNE => '0',
+ TX_FABINT_USRCLK_FLOP => '0',
+ TX_IDLE_DATA_ZERO => '0',
+ TX_INT_DATAWIDTH => 0,
+ TX_LOOPBACK_DRIVE_HIZ => "FALSE",
+ TX_MAINCURSOR_SEL => '0',
+ TX_MARGIN_FULL_0 => B"1001111",
+ TX_MARGIN_FULL_1 => B"1001110",
+ TX_MARGIN_FULL_2 => B"1001100",
+ TX_MARGIN_FULL_3 => B"1001010",
+ TX_MARGIN_FULL_4 => B"1001000",
+ TX_MARGIN_LOW_0 => B"1000110",
+ TX_MARGIN_LOW_1 => B"1000101",
+ TX_MARGIN_LOW_2 => B"1000011",
+ TX_MARGIN_LOW_3 => B"1000010",
+ TX_MARGIN_LOW_4 => B"1000000",
+ TX_MODE_SEL => B"000",
+ TX_PMADATA_OPT => '0',
+ TX_PMA_POWER_SAVE => '0',
+ TX_PROGCLK_SEL => "PREPI",
+ TX_PROGDIV_CFG => 0.000000,
+ TX_QPI_STATUS_EN => '0',
+ TX_RXDETECT_CFG => B"00" & X"032",
+ TX_RXDETECT_REF => B"100",
+ TX_SAMPLE_PERIOD => B"111",
+ TX_SARC_LPBK_ENB => '0',
+ TX_XCLK_SEL => "TXUSR",
+ USE_PCS_CLK_PHASE_SEL => '0',
+ WB_MODE => B"00"
+ )
+ port map (
+ BUFGTCE(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_289\,
+ BUFGTCE(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_290\,
+ BUFGTCE(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_291\,
+ BUFGTCEMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_292\,
+ BUFGTCEMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_293\,
+ BUFGTCEMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_294\,
+ BUFGTDIV(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_357\,
+ BUFGTDIV(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_358\,
+ BUFGTDIV(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_359\,
+ BUFGTDIV(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_360\,
+ BUFGTDIV(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_361\,
+ BUFGTDIV(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_362\,
+ BUFGTDIV(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_363\,
+ BUFGTDIV(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_364\,
+ BUFGTDIV(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_365\,
+ BUFGTRESET(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_295\,
+ BUFGTRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_296\,
+ BUFGTRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_297\,
+ BUFGTRSTMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_298\,
+ BUFGTRSTMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_299\,
+ BUFGTRSTMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_300\,
+ CFGRESET => '0',
+ CLKRSVD0 => '0',
+ CLKRSVD1 => '0',
+ CPLLFBCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_0\,
+ CPLLLOCK => cplllock_out(0),
+ CPLLLOCKDETCLK => '0',
+ CPLLLOCKEN => '1',
+ CPLLPD => GTHE3_CHANNEL_CPLLPD(0),
+ CPLLREFCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_2\,
+ CPLLREFCLKSEL(2 downto 0) => B"001",
+ CPLLRESET => '0',
+ DMONFIFORESET => '0',
+ DMONITORCLK => '0',
+ DMONITOROUT(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_258\,
+ DMONITOROUT(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_259\,
+ DMONITOROUT(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_260\,
+ DMONITOROUT(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_261\,
+ DMONITOROUT(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_262\,
+ DMONITOROUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_263\,
+ DMONITOROUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_264\,
+ DMONITOROUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_265\,
+ DMONITOROUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_266\,
+ DMONITOROUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_267\,
+ DMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_268\,
+ DMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_269\,
+ DMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_270\,
+ DMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_271\,
+ DMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_272\,
+ DMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_273\,
+ DMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_274\,
+ DRPADDR(8 downto 0) => B"000000000",
+ DRPCLK => drpclk_in(0),
+ DRPDI(15 downto 0) => B"0000000000000000",
+ DRPDO(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_210\,
+ DRPDO(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_211\,
+ DRPDO(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_212\,
+ DRPDO(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_213\,
+ DRPDO(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_214\,
+ DRPDO(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_215\,
+ DRPDO(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_216\,
+ DRPDO(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_217\,
+ DRPDO(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_218\,
+ DRPDO(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_219\,
+ DRPDO(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_220\,
+ DRPDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_221\,
+ DRPDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_222\,
+ DRPDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_223\,
+ DRPDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_224\,
+ DRPDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_225\,
+ DRPEN => '0',
+ DRPRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_3\,
+ DRPWE => '0',
+ EVODDPHICALDONE => '0',
+ EVODDPHICALSTART => '0',
+ EVODDPHIDRDEN => '0',
+ EVODDPHIDWREN => '0',
+ EVODDPHIXRDEN => '0',
+ EVODDPHIXWREN => '0',
+ EYESCANDATAERROR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_4\,
+ EYESCANMODE => '0',
+ EYESCANRESET => '0',
+ EYESCANTRIGGER => '0',
+ GTGREFCLK => '0',
+ GTHRXN => gthrxn_in(0),
+ GTHRXP => gthrxp_in(0),
+ GTHTXN => gthtxn_out(0),
+ GTHTXP => gthtxp_out(0),
+ GTNORTHREFCLK0 => '0',
+ GTNORTHREFCLK1 => '0',
+ GTPOWERGOOD => gtpowergood_out(0),
+ GTREFCLK0 => gtrefclk0_in(0),
+ GTREFCLK1 => '0',
+ GTREFCLKMONITOR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_8\,
+ GTRESETSEL => '0',
+ GTRSVD(15 downto 0) => B"0000000000000000",
+ GTRXRESET => GTHE3_CHANNEL_GTRXRESET(0),
+ GTSOUTHREFCLK0 => '0',
+ GTSOUTHREFCLK1 => '0',
+ GTTXRESET => GTHE3_CHANNEL_GTTXRESET(0),
+ LOOPBACK(2 downto 0) => loopback_in(2 downto 0),
+ LPBKRXTXSEREN => '0',
+ LPBKTXRXSEREN => '0',
+ PCIEEQRXEQADAPTDONE => '0',
+ PCIERATEGEN3 => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_9\,
+ PCIERATEIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_10\,
+ PCIERATEQPLLPD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_275\,
+ PCIERATEQPLLPD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_276\,
+ PCIERATEQPLLRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_277\,
+ PCIERATEQPLLRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_278\,
+ PCIERSTIDLE => '0',
+ PCIERSTTXSYNCSTART => '0',
+ PCIESYNCTXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_11\,
+ PCIEUSERGEN3RDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_12\,
+ PCIEUSERPHYSTATUSRST => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_13\,
+ PCIEUSERRATEDONE => '0',
+ PCIEUSERRATESTART => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_14\,
+ PCSRSVDIN(15 downto 0) => B"0000000000000000",
+ PCSRSVDIN2(4 downto 0) => B"00000",
+ PCSRSVDOUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_70\,
+ PCSRSVDOUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_71\,
+ PCSRSVDOUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_72\,
+ PCSRSVDOUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_73\,
+ PCSRSVDOUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_74\,
+ PCSRSVDOUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_75\,
+ PCSRSVDOUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_76\,
+ PCSRSVDOUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_77\,
+ PCSRSVDOUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_78\,
+ PCSRSVDOUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_79\,
+ PCSRSVDOUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_80\,
+ PCSRSVDOUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_81\,
+ PHYSTATUS => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_15\,
+ PINRSRVDAS(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_325\,
+ PINRSRVDAS(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_326\,
+ PINRSRVDAS(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_327\,
+ PINRSRVDAS(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_328\,
+ PINRSRVDAS(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_329\,
+ PINRSRVDAS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_330\,
+ PINRSRVDAS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_331\,
+ PINRSRVDAS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_332\,
+ PMARSVDIN(4 downto 0) => B"00000",
+ QPLL0CLK => qpll0outclk_out(0),
+ QPLL0REFCLK => qpll0outrefclk_out(0),
+ QPLL1CLK => qpll1outclk_out(0),
+ QPLL1REFCLK => qpll1outrefclk_out(0),
+ RESETEXCEPTION => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_16\,
+ RESETOVRD => '0',
+ RSTCLKENTX => '0',
+ RX8B10BEN => '0',
+ RXBUFRESET => '0',
+ RXBUFSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_301\,
+ RXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_302\,
+ RXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_303\,
+ RXBYTEISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_17\,
+ RXBYTEREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_18\,
+ RXCDRFREQRESET => '0',
+ RXCDRHOLD => rxcdrhold_in(0),
+ RXCDRLOCK => rxcdrlock_out(0),
+ RXCDROVRDEN => '0',
+ RXCDRPHDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_20\,
+ RXCDRRESET => '0',
+ RXCDRRESETRSV => '0',
+ RXCHANBONDSEQ => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_21\,
+ RXCHANISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_22\,
+ RXCHANREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_23\,
+ RXCHBONDEN => '0',
+ RXCHBONDI(4 downto 0) => B"00000",
+ RXCHBONDLEVEL(2 downto 0) => B"000",
+ RXCHBONDMASTER => '0',
+ RXCHBONDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_307\,
+ RXCHBONDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_308\,
+ RXCHBONDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_309\,
+ RXCHBONDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_310\,
+ RXCHBONDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_311\,
+ RXCHBONDSLAVE => '0',
+ RXCLKCORCNT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_279\,
+ RXCLKCORCNT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_280\,
+ RXCOMINITDET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_24\,
+ RXCOMMADET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_25\,
+ RXCOMMADETEN => '1',
+ RXCOMSASDET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_26\,
+ RXCOMWAKEDET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_27\,
+ RXCTRL0(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_226\,
+ RXCTRL0(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_227\,
+ RXCTRL0(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_228\,
+ RXCTRL0(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_229\,
+ RXCTRL0(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_230\,
+ RXCTRL0(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_231\,
+ RXCTRL0(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_232\,
+ RXCTRL0(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_233\,
+ RXCTRL0(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_234\,
+ RXCTRL0(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_235\,
+ RXCTRL0(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_236\,
+ RXCTRL0(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_237\,
+ RXCTRL0(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_238\,
+ RXCTRL0(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_239\,
+ RXCTRL0(1) => gtwiz_userdata_rx_out(18),
+ RXCTRL0(0) => gtwiz_userdata_rx_out(8),
+ RXCTRL1(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_242\,
+ RXCTRL1(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_243\,
+ RXCTRL1(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_244\,
+ RXCTRL1(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_245\,
+ RXCTRL1(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_246\,
+ RXCTRL1(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_247\,
+ RXCTRL1(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_248\,
+ RXCTRL1(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_249\,
+ RXCTRL1(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_250\,
+ RXCTRL1(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_251\,
+ RXCTRL1(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_252\,
+ RXCTRL1(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_253\,
+ RXCTRL1(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_254\,
+ RXCTRL1(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_255\,
+ RXCTRL1(1) => gtwiz_userdata_rx_out(19),
+ RXCTRL1(0) => gtwiz_userdata_rx_out(9),
+ RXCTRL2(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_333\,
+ RXCTRL2(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_334\,
+ RXCTRL2(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_335\,
+ RXCTRL2(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_336\,
+ RXCTRL2(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_337\,
+ RXCTRL2(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_338\,
+ RXCTRL2(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_339\,
+ RXCTRL2(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_340\,
+ RXCTRL3(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_341\,
+ RXCTRL3(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_342\,
+ RXCTRL3(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_343\,
+ RXCTRL3(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_344\,
+ RXCTRL3(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_345\,
+ RXCTRL3(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_346\,
+ RXCTRL3(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_347\,
+ RXCTRL3(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_348\,
+ RXDATA(127) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_82\,
+ RXDATA(126) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_83\,
+ RXDATA(125) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_84\,
+ RXDATA(124) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_85\,
+ RXDATA(123) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_86\,
+ RXDATA(122) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_87\,
+ RXDATA(121) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_88\,
+ RXDATA(120) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_89\,
+ RXDATA(119) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_90\,
+ RXDATA(118) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_91\,
+ RXDATA(117) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_92\,
+ RXDATA(116) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_93\,
+ RXDATA(115) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_94\,
+ RXDATA(114) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_95\,
+ RXDATA(113) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_96\,
+ RXDATA(112) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_97\,
+ RXDATA(111) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_98\,
+ RXDATA(110) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_99\,
+ RXDATA(109) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_100\,
+ RXDATA(108) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_101\,
+ RXDATA(107) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_102\,
+ RXDATA(106) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_103\,
+ RXDATA(105) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_104\,
+ RXDATA(104) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_105\,
+ RXDATA(103) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_106\,
+ RXDATA(102) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_107\,
+ RXDATA(101) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_108\,
+ RXDATA(100) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_109\,
+ RXDATA(99) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_110\,
+ RXDATA(98) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_111\,
+ RXDATA(97) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_112\,
+ RXDATA(96) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_113\,
+ RXDATA(95) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_114\,
+ RXDATA(94) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_115\,
+ RXDATA(93) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_116\,
+ RXDATA(92) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_117\,
+ RXDATA(91) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_118\,
+ RXDATA(90) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_119\,
+ RXDATA(89) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_120\,
+ RXDATA(88) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_121\,
+ RXDATA(87) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_122\,
+ RXDATA(86) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_123\,
+ RXDATA(85) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_124\,
+ RXDATA(84) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_125\,
+ RXDATA(83) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_126\,
+ RXDATA(82) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_127\,
+ RXDATA(81) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_128\,
+ RXDATA(80) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_129\,
+ RXDATA(79) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_130\,
+ RXDATA(78) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_131\,
+ RXDATA(77) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_132\,
+ RXDATA(76) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_133\,
+ RXDATA(75) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_134\,
+ RXDATA(74) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_135\,
+ RXDATA(73) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_136\,
+ RXDATA(72) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_137\,
+ RXDATA(71) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_138\,
+ RXDATA(70) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_139\,
+ RXDATA(69) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_140\,
+ RXDATA(68) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_141\,
+ RXDATA(67) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_142\,
+ RXDATA(66) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_143\,
+ RXDATA(65) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_144\,
+ RXDATA(64) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_145\,
+ RXDATA(63) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_146\,
+ RXDATA(62) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_147\,
+ RXDATA(61) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_148\,
+ RXDATA(60) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_149\,
+ RXDATA(59) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_150\,
+ RXDATA(58) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_151\,
+ RXDATA(57) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_152\,
+ RXDATA(56) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_153\,
+ RXDATA(55) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_154\,
+ RXDATA(54) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_155\,
+ RXDATA(53) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_156\,
+ RXDATA(52) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_157\,
+ RXDATA(51) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_158\,
+ RXDATA(50) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_159\,
+ RXDATA(49) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_160\,
+ RXDATA(48) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_161\,
+ RXDATA(47) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_162\,
+ RXDATA(46) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_163\,
+ RXDATA(45) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_164\,
+ RXDATA(44) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_165\,
+ RXDATA(43) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_166\,
+ RXDATA(42) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_167\,
+ RXDATA(41) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_168\,
+ RXDATA(40) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_169\,
+ RXDATA(39) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_170\,
+ RXDATA(38) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_171\,
+ RXDATA(37) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_172\,
+ RXDATA(36) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_173\,
+ RXDATA(35) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_174\,
+ RXDATA(34) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_175\,
+ RXDATA(33) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_176\,
+ RXDATA(32) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_177\,
+ RXDATA(31) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_178\,
+ RXDATA(30) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_179\,
+ RXDATA(29) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_180\,
+ RXDATA(28) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_181\,
+ RXDATA(27) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_182\,
+ RXDATA(26) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_183\,
+ RXDATA(25) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_184\,
+ RXDATA(24) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_185\,
+ RXDATA(23) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_186\,
+ RXDATA(22) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_187\,
+ RXDATA(21) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_188\,
+ RXDATA(20) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_189\,
+ RXDATA(19) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_190\,
+ RXDATA(18) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_191\,
+ RXDATA(17) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_192\,
+ RXDATA(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_193\,
+ RXDATA(15 downto 8) => gtwiz_userdata_rx_out(17 downto 10),
+ RXDATA(7 downto 0) => gtwiz_userdata_rx_out(7 downto 0),
+ RXDATAEXTENDRSVD(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_349\,
+ RXDATAEXTENDRSVD(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_350\,
+ RXDATAEXTENDRSVD(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_351\,
+ RXDATAEXTENDRSVD(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_352\,
+ RXDATAEXTENDRSVD(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_353\,
+ RXDATAEXTENDRSVD(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_354\,
+ RXDATAEXTENDRSVD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_355\,
+ RXDATAEXTENDRSVD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_356\,
+ RXDATAVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_281\,
+ RXDATAVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_282\,
+ RXDFEAGCCTRL(1 downto 0) => B"01",
+ RXDFEAGCHOLD => '0',
+ RXDFEAGCOVRDEN => '0',
+ RXDFELFHOLD => '0',
+ RXDFELFOVRDEN => '0',
+ RXDFELPMRESET => '0',
+ RXDFETAP10HOLD => '0',
+ RXDFETAP10OVRDEN => '0',
+ RXDFETAP11HOLD => '0',
+ RXDFETAP11OVRDEN => '0',
+ RXDFETAP12HOLD => '0',
+ RXDFETAP12OVRDEN => '0',
+ RXDFETAP13HOLD => '0',
+ RXDFETAP13OVRDEN => '0',
+ RXDFETAP14HOLD => '0',
+ RXDFETAP14OVRDEN => '0',
+ RXDFETAP15HOLD => '0',
+ RXDFETAP15OVRDEN => '0',
+ RXDFETAP2HOLD => '0',
+ RXDFETAP2OVRDEN => '0',
+ RXDFETAP3HOLD => '0',
+ RXDFETAP3OVRDEN => '0',
+ RXDFETAP4HOLD => '0',
+ RXDFETAP4OVRDEN => '0',
+ RXDFETAP5HOLD => '0',
+ RXDFETAP5OVRDEN => '0',
+ RXDFETAP6HOLD => '0',
+ RXDFETAP6OVRDEN => '0',
+ RXDFETAP7HOLD => '0',
+ RXDFETAP7OVRDEN => '0',
+ RXDFETAP8HOLD => '0',
+ RXDFETAP8OVRDEN => '0',
+ RXDFETAP9HOLD => '0',
+ RXDFETAP9OVRDEN => '0',
+ RXDFEUTHOLD => '0',
+ RXDFEUTOVRDEN => '0',
+ RXDFEVPHOLD => '0',
+ RXDFEVPOVRDEN => '0',
+ RXDFEVSEN => '0',
+ RXDFEXYDEN => '1',
+ RXDLYBYPASS => '1',
+ RXDLYEN => '0',
+ RXDLYOVRDEN => '0',
+ RXDLYSRESET => '0',
+ RXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_28\,
+ RXELECIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_29\,
+ RXELECIDLEMODE(1 downto 0) => B"11",
+ RXGEARBOXSLIP => '0',
+ RXHEADER(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_312\,
+ RXHEADER(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_313\,
+ RXHEADER(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_314\,
+ RXHEADER(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_315\,
+ RXHEADER(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_316\,
+ RXHEADER(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_317\,
+ RXHEADERVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_283\,
+ RXHEADERVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_284\,
+ RXLATCLK => '0',
+ RXLPMEN => '0',
+ RXLPMGCHOLD => '0',
+ RXLPMGCOVRDEN => '0',
+ RXLPMHFHOLD => '0',
+ RXLPMHFOVRDEN => '0',
+ RXLPMLFHOLD => '0',
+ RXLPMLFKLOVRDEN => '0',
+ RXLPMOSHOLD => '0',
+ RXLPMOSOVRDEN => '0',
+ RXMCOMMAALIGNEN => '0',
+ RXMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_318\,
+ RXMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_319\,
+ RXMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_320\,
+ RXMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_321\,
+ RXMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_322\,
+ RXMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_323\,
+ RXMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_324\,
+ RXMONITORSEL(1 downto 0) => B"00",
+ RXOOBRESET => '0',
+ RXOSCALRESET => '0',
+ RXOSHOLD => '0',
+ RXOSINTCFG(3 downto 0) => B"1101",
+ RXOSINTDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_30\,
+ RXOSINTEN => '1',
+ RXOSINTHOLD => '0',
+ RXOSINTOVRDEN => '0',
+ RXOSINTSTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_31\,
+ RXOSINTSTROBE => '0',
+ RXOSINTSTROBEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_32\,
+ RXOSINTSTROBESTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_33\,
+ RXOSINTTESTOVRDEN => '0',
+ RXOSOVRDEN => '0',
+ RXOUTCLK => rxoutclk_out(0),
+ RXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_35\,
+ RXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_36\,
+ RXOUTCLKSEL(2 downto 0) => B"010",
+ RXPCOMMAALIGNEN => '0',
+ RXPCSRESET => '0',
+ RXPD(1 downto 0) => B"00",
+ RXPHALIGN => '0',
+ RXPHALIGNDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_37\,
+ RXPHALIGNEN => '0',
+ RXPHALIGNERR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_38\,
+ RXPHDLYPD => '0',
+ RXPHDLYRESET => '0',
+ RXPHOVRDEN => '0',
+ RXPLLCLKSEL(1 downto 0) => B"00",
+ RXPMARESET => '0',
+ RXPMARESETDONE => rxpmaresetdone_out(0),
+ RXPOLARITY => rxpolarity_in(0),
+ RXPRBSCNTRESET => '0',
+ RXPRBSERR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_40\,
+ RXPRBSLOCKED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_41\,
+ RXPRBSSEL(3 downto 0) => B"0000",
+ RXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_42\,
+ RXPROGDIVRESET => GTHE3_CHANNEL_RXPROGDIVRESET(0),
+ RXQPIEN => '0',
+ RXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_43\,
+ RXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_44\,
+ RXRATE(2 downto 0) => B"000",
+ RXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_45\,
+ RXRATEMODE => '0',
+ RXRECCLKOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_46\,
+ RXRESETDONE => rxresetdone_out(0),
+ RXSLIDE => rxslide_in(0),
+ RXSLIDERDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_48\,
+ RXSLIPDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_49\,
+ RXSLIPOUTCLK => '0',
+ RXSLIPOUTCLKRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_50\,
+ RXSLIPPMA => '0',
+ RXSLIPPMARDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_51\,
+ RXSTARTOFSEQ(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_285\,
+ RXSTARTOFSEQ(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_286\,
+ RXSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_304\,
+ RXSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_305\,
+ RXSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_306\,
+ RXSYNCALLIN => '0',
+ RXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_52\,
+ RXSYNCIN => '0',
+ RXSYNCMODE => '0',
+ RXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_53\,
+ RXSYSCLKSEL(1 downto 0) => B"00",
+ RXUSERRDY => GTHE3_CHANNEL_RXUSERRDY(0),
+ RXUSRCLK => rxusrclk_in(0),
+ RXUSRCLK2 => rxusrclk2_in(0),
+ RXVALID => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_54\,
+ SIGVALIDCLK => '0',
+ TSTIN(19 downto 0) => B"00000000000000000000",
+ TX8B10BBYPASS(7 downto 0) => B"00000000",
+ TX8B10BEN => '0',
+ TXBUFDIFFCTRL(2 downto 0) => B"000",
+ TXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_287\,
+ TXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_288\,
+ TXCOMFINISH => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_55\,
+ TXCOMINIT => '0',
+ TXCOMSAS => '0',
+ TXCOMWAKE => '0',
+ TXCTRL0(15 downto 2) => B"00000000000000",
+ TXCTRL0(1) => gtwiz_userdata_tx_in(18),
+ TXCTRL0(0) => gtwiz_userdata_tx_in(8),
+ TXCTRL1(15 downto 2) => B"00000000000000",
+ TXCTRL1(1) => gtwiz_userdata_tx_in(19),
+ TXCTRL1(0) => gtwiz_userdata_tx_in(9),
+ TXCTRL2(7 downto 0) => B"00000000",
+ TXDATA(127 downto 16) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ TXDATA(15 downto 8) => gtwiz_userdata_tx_in(17 downto 10),
+ TXDATA(7 downto 0) => gtwiz_userdata_tx_in(7 downto 0),
+ TXDATAEXTENDRSVD(7 downto 0) => B"00000000",
+ TXDEEMPH => '0',
+ TXDETECTRX => '0',
+ TXDIFFCTRL(3 downto 0) => B"1100",
+ TXDIFFPD => '0',
+ TXDLYBYPASS => '0',
+ TXDLYEN => '0',
+ TXDLYHOLD => '0',
+ TXDLYOVRDEN => '0',
+ TXDLYSRESET => GTHE3_CHANNEL_TXDLYSRESET(0),
+ TXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_56\,
+ TXDLYUPDOWN => '0',
+ TXELECIDLE => '0',
+ TXHEADER(5 downto 0) => B"000000",
+ TXINHIBIT => '0',
+ TXLATCLK => '0',
+ TXMAINCURSOR(6 downto 0) => B"1000000",
+ TXMARGIN(2 downto 0) => B"000",
+ TXOUTCLK => txoutclk_out(0),
+ TXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_58\,
+ TXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_59\,
+ TXOUTCLKSEL(2 downto 0) => B"011",
+ TXPCSRESET => '0',
+ TXPD(1 downto 0) => B"00",
+ TXPDELECIDLEMODE => '0',
+ TXPHALIGN => '0',
+ TXPHALIGNDONE => GTHE3_CHANNEL_TXPHALIGNDONE(0),
+ TXPHALIGNEN => '0',
+ TXPHDLYPD => '0',
+ TXPHDLYRESET => '0',
+ TXPHDLYTSTCLK => '0',
+ TXPHINIT => '0',
+ TXPHINITDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_61\,
+ TXPHOVRDEN => '0',
+ TXPIPPMEN => '0',
+ TXPIPPMOVRDEN => '0',
+ TXPIPPMPD => '0',
+ TXPIPPMSEL => '0',
+ TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
+ TXPISOPD => '0',
+ TXPLLCLKSEL(1 downto 0) => B"10",
+ TXPMARESET => '0',
+ TXPMARESETDONE => txpmaresetdone_out(0),
+ TXPOLARITY => txpolarity_in(0),
+ TXPOSTCURSOR(4 downto 0) => B"00000",
+ TXPOSTCURSORINV => '0',
+ TXPRBSFORCEERR => '0',
+ TXPRBSSEL(3 downto 0) => B"0000",
+ TXPRECURSOR(4 downto 0) => B"00000",
+ TXPRECURSORINV => '0',
+ TXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_63\,
+ TXPROGDIVRESET => GTHE3_CHANNEL_TXPROGDIVRESET(0),
+ TXQPIBIASEN => '0',
+ TXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_64\,
+ TXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_65\,
+ TXQPISTRONGPDOWN => '0',
+ TXQPIWEAKPUP => '0',
+ TXRATE(2 downto 0) => B"000",
+ TXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_66\,
+ TXRATEMODE => '0',
+ TXRESETDONE => txresetdone_out(0),
+ TXSEQUENCE(6 downto 0) => B"0000000",
+ TXSWING => '0',
+ TXSYNCALLIN => GTHE3_CHANNEL_TXSYNCALLIN(0),
+ TXSYNCDONE => GTHE3_CHANNEL_TXSYNCDONE(0),
+ TXSYNCIN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYNCMODE => '1',
+ TXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYSCLKSEL(1 downto 0) => B"11",
+ TXUSERRDY => GTHE3_CHANNEL_TXUSERRDY(0),
+ TXUSRCLK => txusrclk_in(0),
+ TXUSRCLK2 => txusrclk2_in(0)
+ );
+\gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST\: unisim.vcomponents.GTHE3_CHANNEL
+ generic map(
+ ACJTAG_DEBUG_MODE => '0',
+ ACJTAG_MODE => '0',
+ ACJTAG_RESET => '0',
+ ADAPT_CFG0 => X"F800",
+ ADAPT_CFG1 => X"0000",
+ ALIGN_COMMA_DOUBLE => "FALSE",
+ ALIGN_COMMA_ENABLE => B"0000000000",
+ ALIGN_COMMA_WORD => 1,
+ ALIGN_MCOMMA_DET => "FALSE",
+ ALIGN_MCOMMA_VALUE => B"1010000011",
+ ALIGN_PCOMMA_DET => "FALSE",
+ ALIGN_PCOMMA_VALUE => B"0101111100",
+ A_RXOSCALRESET => '0',
+ A_RXPROGDIVRESET => '0',
+ A_TXPROGDIVRESET => '0',
+ CBCC_DATA_SOURCE_SEL => "ENCODED",
+ CDR_SWAP_MODE_EN => '0',
+ CHAN_BOND_KEEP_ALIGN => "FALSE",
+ CHAN_BOND_MAX_SKEW => 1,
+ CHAN_BOND_SEQ_1_1 => B"0000000000",
+ CHAN_BOND_SEQ_1_2 => B"0000000000",
+ CHAN_BOND_SEQ_1_3 => B"0000000000",
+ CHAN_BOND_SEQ_1_4 => B"0000000000",
+ CHAN_BOND_SEQ_1_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_1 => B"0000000000",
+ CHAN_BOND_SEQ_2_2 => B"0000000000",
+ CHAN_BOND_SEQ_2_3 => B"0000000000",
+ CHAN_BOND_SEQ_2_4 => B"0000000000",
+ CHAN_BOND_SEQ_2_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_USE => "FALSE",
+ CHAN_BOND_SEQ_LEN => 1,
+ CLK_CORRECT_USE => "FALSE",
+ CLK_COR_KEEP_IDLE => "FALSE",
+ CLK_COR_MAX_LAT => 6,
+ CLK_COR_MIN_LAT => 4,
+ CLK_COR_PRECEDENCE => "TRUE",
+ CLK_COR_REPEAT_WAIT => 0,
+ CLK_COR_SEQ_1_1 => B"0000000000",
+ CLK_COR_SEQ_1_2 => B"0000000000",
+ CLK_COR_SEQ_1_3 => B"0000000000",
+ CLK_COR_SEQ_1_4 => B"0000000000",
+ CLK_COR_SEQ_1_ENABLE => B"1111",
+ CLK_COR_SEQ_2_1 => B"0000000000",
+ CLK_COR_SEQ_2_2 => B"0000000000",
+ CLK_COR_SEQ_2_3 => B"0000000000",
+ CLK_COR_SEQ_2_4 => B"0000000000",
+ CLK_COR_SEQ_2_ENABLE => B"1111",
+ CLK_COR_SEQ_2_USE => "FALSE",
+ CLK_COR_SEQ_LEN => 1,
+ CPLL_CFG0 => X"67F8",
+ CPLL_CFG1 => X"A4AC",
+ CPLL_CFG2 => X"5007",
+ CPLL_CFG3 => B"00" & X"0",
+ CPLL_FBDIV => 2,
+ CPLL_FBDIV_45 => 5,
+ CPLL_INIT_CFG0 => X"02B2",
+ CPLL_INIT_CFG1 => X"00",
+ CPLL_LOCK_CFG => X"01E8",
+ CPLL_REFCLK_DIV => 1,
+ DDI_CTRL => B"00",
+ DDI_REALIGN_WAIT => 15,
+ DEC_MCOMMA_DETECT => "FALSE",
+ DEC_PCOMMA_DETECT => "FALSE",
+ DEC_VALID_COMMA_ONLY => "FALSE",
+ DFE_D_X_REL_POS => '0',
+ DFE_VCM_COMP_EN => '0',
+ DMONITOR_CFG0 => B"00" & X"00",
+ DMONITOR_CFG1 => X"00",
+ ES_CLK_PHASE_SEL => '0',
+ ES_CONTROL => B"000000",
+ ES_ERRDET_EN => "FALSE",
+ ES_EYE_SCAN_EN => "FALSE",
+ ES_HORZ_OFFSET => X"000",
+ ES_PMA_CFG => B"0000000000",
+ ES_PRESCALE => B"00000",
+ ES_QUALIFIER0 => X"0000",
+ ES_QUALIFIER1 => X"0000",
+ ES_QUALIFIER2 => X"0000",
+ ES_QUALIFIER3 => X"0000",
+ ES_QUALIFIER4 => X"0000",
+ ES_QUAL_MASK0 => X"0000",
+ ES_QUAL_MASK1 => X"0000",
+ ES_QUAL_MASK2 => X"0000",
+ ES_QUAL_MASK3 => X"0000",
+ ES_QUAL_MASK4 => X"0000",
+ ES_SDATA_MASK0 => X"0000",
+ ES_SDATA_MASK1 => X"0000",
+ ES_SDATA_MASK2 => X"0000",
+ ES_SDATA_MASK3 => X"0000",
+ ES_SDATA_MASK4 => X"0000",
+ EVODD_PHI_CFG => B"00000000000",
+ EYE_SCAN_SWAP_EN => '0',
+ FTS_DESKEW_SEQ_ENABLE => B"1111",
+ FTS_LANE_DESKEW_CFG => B"1111",
+ FTS_LANE_DESKEW_EN => "FALSE",
+ GEARBOX_MODE => B"00000",
+ GM_BIAS_SELECT => '0',
+ LOCAL_MASTER => '1',
+ OOBDIVCTL => B"00",
+ OOB_PWRUP => '0',
+ PCI3_AUTO_REALIGN => "OVR_1K_BLK",
+ PCI3_PIPE_RX_ELECIDLE => '0',
+ PCI3_RX_ASYNC_EBUF_BYPASS => B"00",
+ PCI3_RX_ELECIDLE_EI2_ENABLE => '0',
+ PCI3_RX_ELECIDLE_H2L_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_H2L_DISABLE => B"000",
+ PCI3_RX_ELECIDLE_HI_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_LP4_DISABLE => '0',
+ PCI3_RX_FIFO_DISABLE => '0',
+ PCIE_BUFG_DIV_CTRL => X"1000",
+ PCIE_RXPCS_CFG_GEN3 => X"02A4",
+ PCIE_RXPMA_CFG => X"000A",
+ PCIE_TXPCS_CFG_GEN3 => X"24A4",
+ PCIE_TXPMA_CFG => X"000A",
+ PCS_PCIE_EN => "FALSE",
+ PCS_RSVD0 => B"0000000000000000",
+ PCS_RSVD1 => B"000",
+ PD_TRANS_TIME_FROM_P2 => X"03C",
+ PD_TRANS_TIME_NONE_P2 => X"19",
+ PD_TRANS_TIME_TO_P2 => X"64",
+ PLL_SEL_MODE_GEN12 => B"00",
+ PLL_SEL_MODE_GEN3 => B"11",
+ PMA_RSV1 => X"F000",
+ PROCESS_PAR => B"010",
+ RATE_SW_USE_DRP => '1',
+ RESET_POWERSAVE_DISABLE => '0',
+ RXBUFRESET_TIME => B"00011",
+ RXBUF_ADDR_MODE => "FAST",
+ RXBUF_EIDLE_HI_CNT => B"1000",
+ RXBUF_EIDLE_LO_CNT => B"0000",
+ RXBUF_EN => "TRUE",
+ RXBUF_RESET_ON_CB_CHANGE => "TRUE",
+ RXBUF_RESET_ON_COMMAALIGN => "FALSE",
+ RXBUF_RESET_ON_EIDLE => "FALSE",
+ RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ RXBUF_THRESH_OVFLW => 61,
+ RXBUF_THRESH_OVRD => "TRUE",
+ RXBUF_THRESH_UNDFLW => 1,
+ RXCDRFREQRESET_TIME => B"00001",
+ RXCDRPHRESET_TIME => B"00001",
+ RXCDR_CFG0 => X"0000",
+ RXCDR_CFG0_GEN3 => X"0000",
+ RXCDR_CFG1 => X"0000",
+ RXCDR_CFG1_GEN3 => X"0000",
+ RXCDR_CFG2 => X"07E6",
+ RXCDR_CFG2_GEN3 => X"07E6",
+ RXCDR_CFG3 => X"0000",
+ RXCDR_CFG3_GEN3 => X"0000",
+ RXCDR_CFG4 => X"0000",
+ RXCDR_CFG4_GEN3 => X"0000",
+ RXCDR_CFG5 => X"0000",
+ RXCDR_CFG5_GEN3 => X"0000",
+ RXCDR_FR_RESET_ON_EIDLE => '0',
+ RXCDR_HOLD_DURING_EIDLE => '0',
+ RXCDR_LOCK_CFG0 => X"4480",
+ RXCDR_LOCK_CFG1 => X"5FFF",
+ RXCDR_LOCK_CFG2 => X"77C3",
+ RXCDR_PH_RESET_ON_EIDLE => '0',
+ RXCFOK_CFG0 => X"4000",
+ RXCFOK_CFG1 => X"0065",
+ RXCFOK_CFG2 => X"002E",
+ RXDFELPMRESET_TIME => B"0001111",
+ RXDFELPM_KL_CFG0 => X"0000",
+ RXDFELPM_KL_CFG1 => X"0002",
+ RXDFELPM_KL_CFG2 => X"0000",
+ RXDFE_CFG0 => X"0A00",
+ RXDFE_CFG1 => X"0000",
+ RXDFE_GC_CFG0 => X"0000",
+ RXDFE_GC_CFG1 => X"7870",
+ RXDFE_GC_CFG2 => X"0000",
+ RXDFE_H2_CFG0 => X"0000",
+ RXDFE_H2_CFG1 => X"0000",
+ RXDFE_H3_CFG0 => X"4000",
+ RXDFE_H3_CFG1 => X"0000",
+ RXDFE_H4_CFG0 => X"2000",
+ RXDFE_H4_CFG1 => X"0003",
+ RXDFE_H5_CFG0 => X"2000",
+ RXDFE_H5_CFG1 => X"0003",
+ RXDFE_H6_CFG0 => X"2000",
+ RXDFE_H6_CFG1 => X"0000",
+ RXDFE_H7_CFG0 => X"2000",
+ RXDFE_H7_CFG1 => X"0000",
+ RXDFE_H8_CFG0 => X"2000",
+ RXDFE_H8_CFG1 => X"0000",
+ RXDFE_H9_CFG0 => X"2000",
+ RXDFE_H9_CFG1 => X"0000",
+ RXDFE_HA_CFG0 => X"2000",
+ RXDFE_HA_CFG1 => X"0000",
+ RXDFE_HB_CFG0 => X"2000",
+ RXDFE_HB_CFG1 => X"0000",
+ RXDFE_HC_CFG0 => X"0000",
+ RXDFE_HC_CFG1 => X"0000",
+ RXDFE_HD_CFG0 => X"0000",
+ RXDFE_HD_CFG1 => X"0000",
+ RXDFE_HE_CFG0 => X"0000",
+ RXDFE_HE_CFG1 => X"0000",
+ RXDFE_HF_CFG0 => X"0000",
+ RXDFE_HF_CFG1 => X"0000",
+ RXDFE_OS_CFG0 => X"8000",
+ RXDFE_OS_CFG1 => X"0000",
+ RXDFE_UT_CFG0 => X"8000",
+ RXDFE_UT_CFG1 => X"0003",
+ RXDFE_VP_CFG0 => X"AA00",
+ RXDFE_VP_CFG1 => X"0033",
+ RXDLY_CFG => X"001F",
+ RXDLY_LCFG => X"0030",
+ RXELECIDLE_CFG => "Sigcfg_4",
+ RXGBOX_FIFO_INIT_RD_ADDR => 4,
+ RXGEARBOX_EN => "FALSE",
+ RXISCANRESET_TIME => B"00001",
+ RXLPM_CFG => X"0000",
+ RXLPM_GC_CFG => X"1000",
+ RXLPM_KH_CFG0 => X"0000",
+ RXLPM_KH_CFG1 => X"0002",
+ RXLPM_OS_CFG0 => X"8000",
+ RXLPM_OS_CFG1 => X"0002",
+ RXOOB_CFG => B"000000110",
+ RXOOB_CLK_CFG => "PMA",
+ RXOSCALRESET_TIME => B"00011",
+ RXOUT_DIV => 1,
+ RXPCSRESET_TIME => B"00011",
+ RXPHBEACON_CFG => X"0000",
+ RXPHDLY_CFG => X"2020",
+ RXPHSAMP_CFG => X"2100",
+ RXPHSLIP_CFG => X"6622",
+ RXPH_MONITOR_SEL => B"00000",
+ RXPI_CFG0 => B"00",
+ RXPI_CFG1 => B"00",
+ RXPI_CFG2 => B"00",
+ RXPI_CFG3 => B"00",
+ RXPI_CFG4 => '1',
+ RXPI_CFG5 => '1',
+ RXPI_CFG6 => B"011",
+ RXPI_LPM => '0',
+ RXPI_VREFSEL => '0',
+ RXPMACLK_SEL => "DATA",
+ RXPMARESET_TIME => B"00011",
+ RXPRBS_ERR_LOOPBACK => '0',
+ RXPRBS_LINKACQ_CNT => 15,
+ RXSLIDE_AUTO_WAIT => 7,
+ RXSLIDE_MODE => "PMA",
+ RXSYNC_MULTILANE => '1',
+ RXSYNC_OVRD => '0',
+ RXSYNC_SKIP_DA => '0',
+ RX_AFE_CM_EN => '0',
+ RX_BIAS_CFG0 => X"0AB4",
+ RX_BUFFER_CFG => B"000000",
+ RX_CAPFF_SARC_ENB => '0',
+ RX_CLK25_DIV => 10,
+ RX_CLKMUX_EN => '1',
+ RX_CLK_SLIP_OVRD => B"00000",
+ RX_CM_BUF_CFG => B"1010",
+ RX_CM_BUF_PD => '0',
+ RX_CM_SEL => B"11",
+ RX_CM_TRIM => B"1010",
+ RX_CTLE3_LPF => B"00000001",
+ RX_DATA_WIDTH => 20,
+ RX_DDI_SEL => B"000000",
+ RX_DEFER_RESET_BUF_EN => "TRUE",
+ RX_DFELPM_CFG0 => B"0110",
+ RX_DFELPM_CFG1 => '1',
+ RX_DFELPM_KLKH_AGC_STUP_EN => '1',
+ RX_DFE_AGC_CFG0 => B"10",
+ RX_DFE_AGC_CFG1 => B"100",
+ RX_DFE_KL_LPM_KH_CFG0 => B"01",
+ RX_DFE_KL_LPM_KH_CFG1 => B"100",
+ RX_DFE_KL_LPM_KL_CFG0 => B"01",
+ RX_DFE_KL_LPM_KL_CFG1 => B"100",
+ RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
+ RX_DISPERR_SEQ_MATCH => "TRUE",
+ RX_DIVRESET_TIME => B"00001",
+ RX_EN_HI_LR => '0',
+ RX_EYESCAN_VS_CODE => B"0000000",
+ RX_EYESCAN_VS_NEG_DIR => '0',
+ RX_EYESCAN_VS_RANGE => B"00",
+ RX_EYESCAN_VS_UT_SIGN => '0',
+ RX_FABINT_USRCLK_FLOP => '0',
+ RX_INT_DATAWIDTH => 0,
+ RX_PMA_POWER_SAVE => '0',
+ RX_PROGDIV_CFG => 0.000000,
+ RX_SAMPLE_PERIOD => B"111",
+ RX_SIG_VALID_DLY => 11,
+ RX_SUM_DFETAPREP_EN => '0',
+ RX_SUM_IREF_TUNE => B"0000",
+ RX_SUM_RES_CTRL => B"00",
+ RX_SUM_VCMTUNE => B"0000",
+ RX_SUM_VCM_OVWR => '0',
+ RX_SUM_VREF_TUNE => B"000",
+ RX_TUNE_AFE_OS => B"10",
+ RX_WIDEMODE_CDR => '0',
+ RX_XCLK_SEL => "RXDES",
+ SAS_MAX_COM => 64,
+ SAS_MIN_COM => 36,
+ SATA_BURST_SEQ_LEN => B"1110",
+ SATA_BURST_VAL => B"100",
+ SATA_CPLL_CFG => "VCO_3000MHZ",
+ SATA_EIDLE_VAL => B"100",
+ SATA_MAX_BURST => 8,
+ SATA_MAX_INIT => 21,
+ SATA_MAX_WAKE => 7,
+ SATA_MIN_BURST => 4,
+ SATA_MIN_INIT => 12,
+ SATA_MIN_WAKE => 4,
+ SHOW_REALIGN_COMMA => "FALSE",
+ SIM_MODE => "FAST",
+ SIM_RECEIVER_DETECT_PASS => "TRUE",
+ SIM_RESET_SPEEDUP => "TRUE",
+ SIM_TX_EIDLE_DRIVE_LEVEL => '0',
+ SIM_VERSION => 2,
+ TAPDLY_SET_TX => B"00",
+ TEMPERATUR_PAR => B"0010",
+ TERM_RCAL_CFG => B"100001000010000",
+ TERM_RCAL_OVRD => B"000",
+ TRANS_TIME_RATE => X"0E",
+ TST_RSV0 => X"00",
+ TST_RSV1 => X"00",
+ TXBUF_EN => "FALSE",
+ TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ TXDLY_CFG => X"0009",
+ TXDLY_LCFG => X"0050",
+ TXDRVBIAS_N => B"1010",
+ TXDRVBIAS_P => B"1010",
+ TXFIFO_ADDR_CFG => "LOW",
+ TXGBOX_FIFO_INIT_RD_ADDR => 4,
+ TXGEARBOX_EN => "FALSE",
+ TXOUT_DIV => 2,
+ TXPCSRESET_TIME => B"00011",
+ TXPHDLY_CFG0 => X"2020",
+ TXPHDLY_CFG1 => X"0075",
+ TXPH_CFG => X"0980",
+ TXPH_MONITOR_SEL => B"00000",
+ TXPI_CFG0 => B"00",
+ TXPI_CFG1 => B"00",
+ TXPI_CFG2 => B"00",
+ TXPI_CFG3 => '1',
+ TXPI_CFG4 => '1',
+ TXPI_CFG5 => B"000",
+ TXPI_GRAY_SEL => '0',
+ TXPI_INVSTROBE_SEL => '1',
+ TXPI_LPM => '0',
+ TXPI_PPMCLK_SEL => "TXUSRCLK2",
+ TXPI_PPM_CFG => B"00000000",
+ TXPI_SYNFREQ_PPM => B"001",
+ TXPI_VREFSEL => '0',
+ TXPMARESET_TIME => B"00011",
+ TXSYNC_MULTILANE => '1',
+ TXSYNC_OVRD => '0',
+ TXSYNC_SKIP_DA => '0',
+ TX_CLK25_DIV => 10,
+ TX_CLKMUX_EN => '1',
+ TX_DATA_WIDTH => 20,
+ TX_DCD_CFG => B"000010",
+ TX_DCD_EN => '0',
+ TX_DEEMPH0 => B"000000",
+ TX_DEEMPH1 => B"000000",
+ TX_DIVRESET_TIME => B"00001",
+ TX_DRIVE_MODE => "DIRECT",
+ TX_EIDLE_ASSERT_DELAY => B"100",
+ TX_EIDLE_DEASSERT_DELAY => B"011",
+ TX_EML_PHI_TUNE => '0',
+ TX_FABINT_USRCLK_FLOP => '0',
+ TX_IDLE_DATA_ZERO => '0',
+ TX_INT_DATAWIDTH => 0,
+ TX_LOOPBACK_DRIVE_HIZ => "FALSE",
+ TX_MAINCURSOR_SEL => '0',
+ TX_MARGIN_FULL_0 => B"1001111",
+ TX_MARGIN_FULL_1 => B"1001110",
+ TX_MARGIN_FULL_2 => B"1001100",
+ TX_MARGIN_FULL_3 => B"1001010",
+ TX_MARGIN_FULL_4 => B"1001000",
+ TX_MARGIN_LOW_0 => B"1000110",
+ TX_MARGIN_LOW_1 => B"1000101",
+ TX_MARGIN_LOW_2 => B"1000011",
+ TX_MARGIN_LOW_3 => B"1000010",
+ TX_MARGIN_LOW_4 => B"1000000",
+ TX_MODE_SEL => B"000",
+ TX_PMADATA_OPT => '0',
+ TX_PMA_POWER_SAVE => '0',
+ TX_PROGCLK_SEL => "PREPI",
+ TX_PROGDIV_CFG => 0.000000,
+ TX_QPI_STATUS_EN => '0',
+ TX_RXDETECT_CFG => B"00" & X"032",
+ TX_RXDETECT_REF => B"100",
+ TX_SAMPLE_PERIOD => B"111",
+ TX_SARC_LPBK_ENB => '0',
+ TX_XCLK_SEL => "TXUSR",
+ USE_PCS_CLK_PHASE_SEL => '0',
+ WB_MODE => B"00"
+ )
+ port map (
+ BUFGTCE(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_289\,
+ BUFGTCE(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_290\,
+ BUFGTCE(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_291\,
+ BUFGTCEMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_292\,
+ BUFGTCEMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_293\,
+ BUFGTCEMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_294\,
+ BUFGTDIV(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_357\,
+ BUFGTDIV(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_358\,
+ BUFGTDIV(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_359\,
+ BUFGTDIV(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_360\,
+ BUFGTDIV(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_361\,
+ BUFGTDIV(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_362\,
+ BUFGTDIV(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_363\,
+ BUFGTDIV(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_364\,
+ BUFGTDIV(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_365\,
+ BUFGTRESET(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_295\,
+ BUFGTRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_296\,
+ BUFGTRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_297\,
+ BUFGTRSTMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_298\,
+ BUFGTRSTMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_299\,
+ BUFGTRSTMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_300\,
+ CFGRESET => '0',
+ CLKRSVD0 => '0',
+ CLKRSVD1 => '0',
+ CPLLFBCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_0\,
+ CPLLLOCK => cplllock_out(1),
+ CPLLLOCKDETCLK => '0',
+ CPLLLOCKEN => '1',
+ CPLLPD => GTHE3_CHANNEL_CPLLPD(0),
+ CPLLREFCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_2\,
+ CPLLREFCLKSEL(2 downto 0) => B"001",
+ CPLLRESET => '0',
+ DMONFIFORESET => '0',
+ DMONITORCLK => '0',
+ DMONITOROUT(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_258\,
+ DMONITOROUT(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_259\,
+ DMONITOROUT(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_260\,
+ DMONITOROUT(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_261\,
+ DMONITOROUT(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_262\,
+ DMONITOROUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_263\,
+ DMONITOROUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_264\,
+ DMONITOROUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_265\,
+ DMONITOROUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_266\,
+ DMONITOROUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_267\,
+ DMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_268\,
+ DMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_269\,
+ DMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_270\,
+ DMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_271\,
+ DMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_272\,
+ DMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_273\,
+ DMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_274\,
+ DRPADDR(8 downto 0) => B"000000000",
+ DRPCLK => drpclk_in(1),
+ DRPDI(15 downto 0) => B"0000000000000000",
+ DRPDO(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_210\,
+ DRPDO(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_211\,
+ DRPDO(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_212\,
+ DRPDO(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_213\,
+ DRPDO(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_214\,
+ DRPDO(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_215\,
+ DRPDO(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_216\,
+ DRPDO(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_217\,
+ DRPDO(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_218\,
+ DRPDO(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_219\,
+ DRPDO(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_220\,
+ DRPDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_221\,
+ DRPDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_222\,
+ DRPDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_223\,
+ DRPDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_224\,
+ DRPDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_225\,
+ DRPEN => '0',
+ DRPRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_3\,
+ DRPWE => '0',
+ EVODDPHICALDONE => '0',
+ EVODDPHICALSTART => '0',
+ EVODDPHIDRDEN => '0',
+ EVODDPHIDWREN => '0',
+ EVODDPHIXRDEN => '0',
+ EVODDPHIXWREN => '0',
+ EYESCANDATAERROR => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_4\,
+ EYESCANMODE => '0',
+ EYESCANRESET => '0',
+ EYESCANTRIGGER => '0',
+ GTGREFCLK => '0',
+ GTHRXN => gthrxn_in(1),
+ GTHRXP => gthrxp_in(1),
+ GTHTXN => gthtxn_out(1),
+ GTHTXP => gthtxp_out(1),
+ GTNORTHREFCLK0 => '0',
+ GTNORTHREFCLK1 => '0',
+ GTPOWERGOOD => gtpowergood_out(1),
+ GTREFCLK0 => gtrefclk0_in(1),
+ GTREFCLK1 => '0',
+ GTREFCLKMONITOR => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_8\,
+ GTRESETSEL => '0',
+ GTRSVD(15 downto 0) => B"0000000000000000",
+ GTRXRESET => GTHE3_CHANNEL_GTRXRESET(0),
+ GTSOUTHREFCLK0 => '0',
+ GTSOUTHREFCLK1 => '0',
+ GTTXRESET => GTHE3_CHANNEL_GTTXRESET(0),
+ LOOPBACK(2 downto 0) => loopback_in(5 downto 3),
+ LPBKRXTXSEREN => '0',
+ LPBKTXRXSEREN => '0',
+ PCIEEQRXEQADAPTDONE => '0',
+ PCIERATEGEN3 => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_9\,
+ PCIERATEIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_10\,
+ PCIERATEQPLLPD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_275\,
+ PCIERATEQPLLPD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_276\,
+ PCIERATEQPLLRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_277\,
+ PCIERATEQPLLRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_278\,
+ PCIERSTIDLE => '0',
+ PCIERSTTXSYNCSTART => '0',
+ PCIESYNCTXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_11\,
+ PCIEUSERGEN3RDY => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_12\,
+ PCIEUSERPHYSTATUSRST => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_13\,
+ PCIEUSERRATEDONE => '0',
+ PCIEUSERRATESTART => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_14\,
+ PCSRSVDIN(15 downto 0) => B"0000000000000000",
+ PCSRSVDIN2(4 downto 0) => B"00000",
+ PCSRSVDOUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_70\,
+ PCSRSVDOUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_71\,
+ PCSRSVDOUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_72\,
+ PCSRSVDOUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_73\,
+ PCSRSVDOUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_74\,
+ PCSRSVDOUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_75\,
+ PCSRSVDOUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_76\,
+ PCSRSVDOUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_77\,
+ PCSRSVDOUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_78\,
+ PCSRSVDOUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_79\,
+ PCSRSVDOUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_80\,
+ PCSRSVDOUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_81\,
+ PHYSTATUS => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_15\,
+ PINRSRVDAS(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_325\,
+ PINRSRVDAS(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_326\,
+ PINRSRVDAS(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_327\,
+ PINRSRVDAS(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_328\,
+ PINRSRVDAS(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_329\,
+ PINRSRVDAS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_330\,
+ PINRSRVDAS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_331\,
+ PINRSRVDAS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_332\,
+ PMARSVDIN(4 downto 0) => B"00000",
+ QPLL0CLK => qpll0outclk_out(0),
+ QPLL0REFCLK => qpll0outrefclk_out(0),
+ QPLL1CLK => qpll1outclk_out(0),
+ QPLL1REFCLK => qpll1outrefclk_out(0),
+ RESETEXCEPTION => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_16\,
+ RESETOVRD => '0',
+ RSTCLKENTX => '0',
+ RX8B10BEN => '0',
+ RXBUFRESET => '0',
+ RXBUFSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_301\,
+ RXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_302\,
+ RXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_303\,
+ RXBYTEISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_17\,
+ RXBYTEREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_18\,
+ RXCDRFREQRESET => '0',
+ RXCDRHOLD => rxcdrhold_in(1),
+ RXCDRLOCK => rxcdrlock_out(1),
+ RXCDROVRDEN => '0',
+ RXCDRPHDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_20\,
+ RXCDRRESET => '0',
+ RXCDRRESETRSV => '0',
+ RXCHANBONDSEQ => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_21\,
+ RXCHANISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_22\,
+ RXCHANREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_23\,
+ RXCHBONDEN => '0',
+ RXCHBONDI(4 downto 0) => B"00000",
+ RXCHBONDLEVEL(2 downto 0) => B"000",
+ RXCHBONDMASTER => '0',
+ RXCHBONDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_307\,
+ RXCHBONDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_308\,
+ RXCHBONDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_309\,
+ RXCHBONDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_310\,
+ RXCHBONDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_311\,
+ RXCHBONDSLAVE => '0',
+ RXCLKCORCNT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_279\,
+ RXCLKCORCNT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_280\,
+ RXCOMINITDET => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_24\,
+ RXCOMMADET => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_25\,
+ RXCOMMADETEN => '1',
+ RXCOMSASDET => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_26\,
+ RXCOMWAKEDET => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_27\,
+ RXCTRL0(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_226\,
+ RXCTRL0(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_227\,
+ RXCTRL0(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_228\,
+ RXCTRL0(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_229\,
+ RXCTRL0(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_230\,
+ RXCTRL0(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_231\,
+ RXCTRL0(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_232\,
+ RXCTRL0(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_233\,
+ RXCTRL0(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_234\,
+ RXCTRL0(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_235\,
+ RXCTRL0(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_236\,
+ RXCTRL0(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_237\,
+ RXCTRL0(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_238\,
+ RXCTRL0(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_239\,
+ RXCTRL0(1) => gtwiz_userdata_rx_out(38),
+ RXCTRL0(0) => gtwiz_userdata_rx_out(28),
+ RXCTRL1(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_242\,
+ RXCTRL1(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_243\,
+ RXCTRL1(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_244\,
+ RXCTRL1(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_245\,
+ RXCTRL1(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_246\,
+ RXCTRL1(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_247\,
+ RXCTRL1(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_248\,
+ RXCTRL1(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_249\,
+ RXCTRL1(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_250\,
+ RXCTRL1(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_251\,
+ RXCTRL1(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_252\,
+ RXCTRL1(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_253\,
+ RXCTRL1(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_254\,
+ RXCTRL1(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_255\,
+ RXCTRL1(1) => gtwiz_userdata_rx_out(39),
+ RXCTRL1(0) => gtwiz_userdata_rx_out(29),
+ RXCTRL2(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_333\,
+ RXCTRL2(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_334\,
+ RXCTRL2(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_335\,
+ RXCTRL2(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_336\,
+ RXCTRL2(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_337\,
+ RXCTRL2(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_338\,
+ RXCTRL2(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_339\,
+ RXCTRL2(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_340\,
+ RXCTRL3(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_341\,
+ RXCTRL3(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_342\,
+ RXCTRL3(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_343\,
+ RXCTRL3(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_344\,
+ RXCTRL3(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_345\,
+ RXCTRL3(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_346\,
+ RXCTRL3(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_347\,
+ RXCTRL3(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_348\,
+ RXDATA(127) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_82\,
+ RXDATA(126) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_83\,
+ RXDATA(125) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_84\,
+ RXDATA(124) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_85\,
+ RXDATA(123) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_86\,
+ RXDATA(122) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_87\,
+ RXDATA(121) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_88\,
+ RXDATA(120) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_89\,
+ RXDATA(119) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_90\,
+ RXDATA(118) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_91\,
+ RXDATA(117) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_92\,
+ RXDATA(116) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_93\,
+ RXDATA(115) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_94\,
+ RXDATA(114) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_95\,
+ RXDATA(113) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_96\,
+ RXDATA(112) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_97\,
+ RXDATA(111) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_98\,
+ RXDATA(110) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_99\,
+ RXDATA(109) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_100\,
+ RXDATA(108) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_101\,
+ RXDATA(107) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_102\,
+ RXDATA(106) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_103\,
+ RXDATA(105) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_104\,
+ RXDATA(104) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_105\,
+ RXDATA(103) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_106\,
+ RXDATA(102) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_107\,
+ RXDATA(101) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_108\,
+ RXDATA(100) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_109\,
+ RXDATA(99) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_110\,
+ RXDATA(98) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_111\,
+ RXDATA(97) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_112\,
+ RXDATA(96) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_113\,
+ RXDATA(95) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_114\,
+ RXDATA(94) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_115\,
+ RXDATA(93) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_116\,
+ RXDATA(92) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_117\,
+ RXDATA(91) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_118\,
+ RXDATA(90) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_119\,
+ RXDATA(89) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_120\,
+ RXDATA(88) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_121\,
+ RXDATA(87) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_122\,
+ RXDATA(86) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_123\,
+ RXDATA(85) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_124\,
+ RXDATA(84) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_125\,
+ RXDATA(83) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_126\,
+ RXDATA(82) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_127\,
+ RXDATA(81) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_128\,
+ RXDATA(80) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_129\,
+ RXDATA(79) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_130\,
+ RXDATA(78) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_131\,
+ RXDATA(77) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_132\,
+ RXDATA(76) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_133\,
+ RXDATA(75) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_134\,
+ RXDATA(74) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_135\,
+ RXDATA(73) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_136\,
+ RXDATA(72) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_137\,
+ RXDATA(71) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_138\,
+ RXDATA(70) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_139\,
+ RXDATA(69) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_140\,
+ RXDATA(68) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_141\,
+ RXDATA(67) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_142\,
+ RXDATA(66) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_143\,
+ RXDATA(65) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_144\,
+ RXDATA(64) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_145\,
+ RXDATA(63) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_146\,
+ RXDATA(62) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_147\,
+ RXDATA(61) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_148\,
+ RXDATA(60) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_149\,
+ RXDATA(59) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_150\,
+ RXDATA(58) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_151\,
+ RXDATA(57) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_152\,
+ RXDATA(56) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_153\,
+ RXDATA(55) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_154\,
+ RXDATA(54) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_155\,
+ RXDATA(53) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_156\,
+ RXDATA(52) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_157\,
+ RXDATA(51) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_158\,
+ RXDATA(50) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_159\,
+ RXDATA(49) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_160\,
+ RXDATA(48) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_161\,
+ RXDATA(47) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_162\,
+ RXDATA(46) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_163\,
+ RXDATA(45) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_164\,
+ RXDATA(44) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_165\,
+ RXDATA(43) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_166\,
+ RXDATA(42) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_167\,
+ RXDATA(41) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_168\,
+ RXDATA(40) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_169\,
+ RXDATA(39) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_170\,
+ RXDATA(38) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_171\,
+ RXDATA(37) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_172\,
+ RXDATA(36) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_173\,
+ RXDATA(35) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_174\,
+ RXDATA(34) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_175\,
+ RXDATA(33) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_176\,
+ RXDATA(32) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_177\,
+ RXDATA(31) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_178\,
+ RXDATA(30) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_179\,
+ RXDATA(29) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_180\,
+ RXDATA(28) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_181\,
+ RXDATA(27) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_182\,
+ RXDATA(26) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_183\,
+ RXDATA(25) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_184\,
+ RXDATA(24) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_185\,
+ RXDATA(23) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_186\,
+ RXDATA(22) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_187\,
+ RXDATA(21) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_188\,
+ RXDATA(20) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_189\,
+ RXDATA(19) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_190\,
+ RXDATA(18) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_191\,
+ RXDATA(17) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_192\,
+ RXDATA(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_193\,
+ RXDATA(15 downto 8) => gtwiz_userdata_rx_out(37 downto 30),
+ RXDATA(7 downto 0) => gtwiz_userdata_rx_out(27 downto 20),
+ RXDATAEXTENDRSVD(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_349\,
+ RXDATAEXTENDRSVD(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_350\,
+ RXDATAEXTENDRSVD(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_351\,
+ RXDATAEXTENDRSVD(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_352\,
+ RXDATAEXTENDRSVD(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_353\,
+ RXDATAEXTENDRSVD(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_354\,
+ RXDATAEXTENDRSVD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_355\,
+ RXDATAEXTENDRSVD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_356\,
+ RXDATAVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_281\,
+ RXDATAVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_282\,
+ RXDFEAGCCTRL(1 downto 0) => B"01",
+ RXDFEAGCHOLD => '0',
+ RXDFEAGCOVRDEN => '0',
+ RXDFELFHOLD => '0',
+ RXDFELFOVRDEN => '0',
+ RXDFELPMRESET => '0',
+ RXDFETAP10HOLD => '0',
+ RXDFETAP10OVRDEN => '0',
+ RXDFETAP11HOLD => '0',
+ RXDFETAP11OVRDEN => '0',
+ RXDFETAP12HOLD => '0',
+ RXDFETAP12OVRDEN => '0',
+ RXDFETAP13HOLD => '0',
+ RXDFETAP13OVRDEN => '0',
+ RXDFETAP14HOLD => '0',
+ RXDFETAP14OVRDEN => '0',
+ RXDFETAP15HOLD => '0',
+ RXDFETAP15OVRDEN => '0',
+ RXDFETAP2HOLD => '0',
+ RXDFETAP2OVRDEN => '0',
+ RXDFETAP3HOLD => '0',
+ RXDFETAP3OVRDEN => '0',
+ RXDFETAP4HOLD => '0',
+ RXDFETAP4OVRDEN => '0',
+ RXDFETAP5HOLD => '0',
+ RXDFETAP5OVRDEN => '0',
+ RXDFETAP6HOLD => '0',
+ RXDFETAP6OVRDEN => '0',
+ RXDFETAP7HOLD => '0',
+ RXDFETAP7OVRDEN => '0',
+ RXDFETAP8HOLD => '0',
+ RXDFETAP8OVRDEN => '0',
+ RXDFETAP9HOLD => '0',
+ RXDFETAP9OVRDEN => '0',
+ RXDFEUTHOLD => '0',
+ RXDFEUTOVRDEN => '0',
+ RXDFEVPHOLD => '0',
+ RXDFEVPOVRDEN => '0',
+ RXDFEVSEN => '0',
+ RXDFEXYDEN => '1',
+ RXDLYBYPASS => '1',
+ RXDLYEN => '0',
+ RXDLYOVRDEN => '0',
+ RXDLYSRESET => '0',
+ RXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_28\,
+ RXELECIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_29\,
+ RXELECIDLEMODE(1 downto 0) => B"11",
+ RXGEARBOXSLIP => '0',
+ RXHEADER(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_312\,
+ RXHEADER(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_313\,
+ RXHEADER(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_314\,
+ RXHEADER(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_315\,
+ RXHEADER(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_316\,
+ RXHEADER(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_317\,
+ RXHEADERVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_283\,
+ RXHEADERVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_284\,
+ RXLATCLK => '0',
+ RXLPMEN => '0',
+ RXLPMGCHOLD => '0',
+ RXLPMGCOVRDEN => '0',
+ RXLPMHFHOLD => '0',
+ RXLPMHFOVRDEN => '0',
+ RXLPMLFHOLD => '0',
+ RXLPMLFKLOVRDEN => '0',
+ RXLPMOSHOLD => '0',
+ RXLPMOSOVRDEN => '0',
+ RXMCOMMAALIGNEN => '0',
+ RXMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_318\,
+ RXMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_319\,
+ RXMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_320\,
+ RXMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_321\,
+ RXMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_322\,
+ RXMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_323\,
+ RXMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_324\,
+ RXMONITORSEL(1 downto 0) => B"00",
+ RXOOBRESET => '0',
+ RXOSCALRESET => '0',
+ RXOSHOLD => '0',
+ RXOSINTCFG(3 downto 0) => B"1101",
+ RXOSINTDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_30\,
+ RXOSINTEN => '1',
+ RXOSINTHOLD => '0',
+ RXOSINTOVRDEN => '0',
+ RXOSINTSTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_31\,
+ RXOSINTSTROBE => '0',
+ RXOSINTSTROBEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_32\,
+ RXOSINTSTROBESTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_33\,
+ RXOSINTTESTOVRDEN => '0',
+ RXOSOVRDEN => '0',
+ RXOUTCLK => rxoutclk_out(1),
+ RXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_35\,
+ RXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_36\,
+ RXOUTCLKSEL(2 downto 0) => B"010",
+ RXPCOMMAALIGNEN => '0',
+ RXPCSRESET => '0',
+ RXPD(1 downto 0) => B"00",
+ RXPHALIGN => '0',
+ RXPHALIGNDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_37\,
+ RXPHALIGNEN => '0',
+ RXPHALIGNERR => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_38\,
+ RXPHDLYPD => '0',
+ RXPHDLYRESET => '0',
+ RXPHOVRDEN => '0',
+ RXPLLCLKSEL(1 downto 0) => B"00",
+ RXPMARESET => '0',
+ RXPMARESETDONE => rxpmaresetdone_out(1),
+ RXPOLARITY => rxpolarity_in(1),
+ RXPRBSCNTRESET => '0',
+ RXPRBSERR => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_40\,
+ RXPRBSLOCKED => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_41\,
+ RXPRBSSEL(3 downto 0) => B"0000",
+ RXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_42\,
+ RXPROGDIVRESET => GTHE3_CHANNEL_RXPROGDIVRESET(0),
+ RXQPIEN => '0',
+ RXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_43\,
+ RXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_44\,
+ RXRATE(2 downto 0) => B"000",
+ RXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_45\,
+ RXRATEMODE => '0',
+ RXRECCLKOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_46\,
+ RXRESETDONE => rxresetdone_out(1),
+ RXSLIDE => rxslide_in(1),
+ RXSLIDERDY => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_48\,
+ RXSLIPDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_49\,
+ RXSLIPOUTCLK => '0',
+ RXSLIPOUTCLKRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_50\,
+ RXSLIPPMA => '0',
+ RXSLIPPMARDY => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_51\,
+ RXSTARTOFSEQ(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_285\,
+ RXSTARTOFSEQ(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_286\,
+ RXSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_304\,
+ RXSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_305\,
+ RXSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_306\,
+ RXSYNCALLIN => '0',
+ RXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_52\,
+ RXSYNCIN => '0',
+ RXSYNCMODE => '0',
+ RXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_53\,
+ RXSYSCLKSEL(1 downto 0) => B"00",
+ RXUSERRDY => GTHE3_CHANNEL_RXUSERRDY(0),
+ RXUSRCLK => rxusrclk_in(1),
+ RXUSRCLK2 => rxusrclk2_in(1),
+ RXVALID => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_54\,
+ SIGVALIDCLK => '0',
+ TSTIN(19 downto 0) => B"00000000000000000000",
+ TX8B10BBYPASS(7 downto 0) => B"00000000",
+ TX8B10BEN => '0',
+ TXBUFDIFFCTRL(2 downto 0) => B"000",
+ TXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_287\,
+ TXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_288\,
+ TXCOMFINISH => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_55\,
+ TXCOMINIT => '0',
+ TXCOMSAS => '0',
+ TXCOMWAKE => '0',
+ TXCTRL0(15 downto 2) => B"00000000000000",
+ TXCTRL0(1) => gtwiz_userdata_tx_in(38),
+ TXCTRL0(0) => gtwiz_userdata_tx_in(28),
+ TXCTRL1(15 downto 2) => B"00000000000000",
+ TXCTRL1(1) => gtwiz_userdata_tx_in(39),
+ TXCTRL1(0) => gtwiz_userdata_tx_in(29),
+ TXCTRL2(7 downto 0) => B"00000000",
+ TXDATA(127 downto 16) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ TXDATA(15 downto 8) => gtwiz_userdata_tx_in(37 downto 30),
+ TXDATA(7 downto 0) => gtwiz_userdata_tx_in(27 downto 20),
+ TXDATAEXTENDRSVD(7 downto 0) => B"00000000",
+ TXDEEMPH => '0',
+ TXDETECTRX => '0',
+ TXDIFFCTRL(3 downto 0) => B"1100",
+ TXDIFFPD => '0',
+ TXDLYBYPASS => '0',
+ TXDLYEN => '0',
+ TXDLYHOLD => '0',
+ TXDLYOVRDEN => '0',
+ TXDLYSRESET => GTHE3_CHANNEL_TXDLYSRESET(0),
+ TXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_56\,
+ TXDLYUPDOWN => '0',
+ TXELECIDLE => '0',
+ TXHEADER(5 downto 0) => B"000000",
+ TXINHIBIT => '0',
+ TXLATCLK => '0',
+ TXMAINCURSOR(6 downto 0) => B"1000000",
+ TXMARGIN(2 downto 0) => B"000",
+ TXOUTCLK => txoutclk_out(1),
+ TXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_58\,
+ TXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_59\,
+ TXOUTCLKSEL(2 downto 0) => B"011",
+ TXPCSRESET => '0',
+ TXPD(1 downto 0) => B"00",
+ TXPDELECIDLEMODE => '0',
+ TXPHALIGN => '0',
+ TXPHALIGNDONE => GTHE3_CHANNEL_TXPHALIGNDONE(1),
+ TXPHALIGNEN => '0',
+ TXPHDLYPD => '0',
+ TXPHDLYRESET => '0',
+ TXPHDLYTSTCLK => '0',
+ TXPHINIT => '0',
+ TXPHINITDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_61\,
+ TXPHOVRDEN => '0',
+ TXPIPPMEN => '0',
+ TXPIPPMOVRDEN => '0',
+ TXPIPPMPD => '0',
+ TXPIPPMSEL => '0',
+ TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
+ TXPISOPD => '0',
+ TXPLLCLKSEL(1 downto 0) => B"10",
+ TXPMARESET => '0',
+ TXPMARESETDONE => txpmaresetdone_out(1),
+ TXPOLARITY => txpolarity_in(1),
+ TXPOSTCURSOR(4 downto 0) => B"00000",
+ TXPOSTCURSORINV => '0',
+ TXPRBSFORCEERR => '0',
+ TXPRBSSEL(3 downto 0) => B"0000",
+ TXPRECURSOR(4 downto 0) => B"00000",
+ TXPRECURSORINV => '0',
+ TXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_63\,
+ TXPROGDIVRESET => GTHE3_CHANNEL_TXPROGDIVRESET(0),
+ TXQPIBIASEN => '0',
+ TXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_64\,
+ TXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_65\,
+ TXQPISTRONGPDOWN => '0',
+ TXQPIWEAKPUP => '0',
+ TXRATE(2 downto 0) => B"000",
+ TXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_66\,
+ TXRATEMODE => '0',
+ TXRESETDONE => txresetdone_out(1),
+ TXSEQUENCE(6 downto 0) => B"0000000",
+ TXSWING => '0',
+ TXSYNCALLIN => GTHE3_CHANNEL_TXSYNCALLIN(0),
+ TXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_68\,
+ TXSYNCIN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYNCMODE => '0',
+ TXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYSCLKSEL(1 downto 0) => B"11",
+ TXUSERRDY => GTHE3_CHANNEL_TXUSERRDY(0),
+ TXUSRCLK => txusrclk_in(1),
+ TXUSRCLK2 => txusrclk2_in(1)
+ );
+\gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST\: unisim.vcomponents.GTHE3_CHANNEL
+ generic map(
+ ACJTAG_DEBUG_MODE => '0',
+ ACJTAG_MODE => '0',
+ ACJTAG_RESET => '0',
+ ADAPT_CFG0 => X"F800",
+ ADAPT_CFG1 => X"0000",
+ ALIGN_COMMA_DOUBLE => "FALSE",
+ ALIGN_COMMA_ENABLE => B"0000000000",
+ ALIGN_COMMA_WORD => 1,
+ ALIGN_MCOMMA_DET => "FALSE",
+ ALIGN_MCOMMA_VALUE => B"1010000011",
+ ALIGN_PCOMMA_DET => "FALSE",
+ ALIGN_PCOMMA_VALUE => B"0101111100",
+ A_RXOSCALRESET => '0',
+ A_RXPROGDIVRESET => '0',
+ A_TXPROGDIVRESET => '0',
+ CBCC_DATA_SOURCE_SEL => "ENCODED",
+ CDR_SWAP_MODE_EN => '0',
+ CHAN_BOND_KEEP_ALIGN => "FALSE",
+ CHAN_BOND_MAX_SKEW => 1,
+ CHAN_BOND_SEQ_1_1 => B"0000000000",
+ CHAN_BOND_SEQ_1_2 => B"0000000000",
+ CHAN_BOND_SEQ_1_3 => B"0000000000",
+ CHAN_BOND_SEQ_1_4 => B"0000000000",
+ CHAN_BOND_SEQ_1_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_1 => B"0000000000",
+ CHAN_BOND_SEQ_2_2 => B"0000000000",
+ CHAN_BOND_SEQ_2_3 => B"0000000000",
+ CHAN_BOND_SEQ_2_4 => B"0000000000",
+ CHAN_BOND_SEQ_2_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_USE => "FALSE",
+ CHAN_BOND_SEQ_LEN => 1,
+ CLK_CORRECT_USE => "FALSE",
+ CLK_COR_KEEP_IDLE => "FALSE",
+ CLK_COR_MAX_LAT => 6,
+ CLK_COR_MIN_LAT => 4,
+ CLK_COR_PRECEDENCE => "TRUE",
+ CLK_COR_REPEAT_WAIT => 0,
+ CLK_COR_SEQ_1_1 => B"0000000000",
+ CLK_COR_SEQ_1_2 => B"0000000000",
+ CLK_COR_SEQ_1_3 => B"0000000000",
+ CLK_COR_SEQ_1_4 => B"0000000000",
+ CLK_COR_SEQ_1_ENABLE => B"1111",
+ CLK_COR_SEQ_2_1 => B"0000000000",
+ CLK_COR_SEQ_2_2 => B"0000000000",
+ CLK_COR_SEQ_2_3 => B"0000000000",
+ CLK_COR_SEQ_2_4 => B"0000000000",
+ CLK_COR_SEQ_2_ENABLE => B"1111",
+ CLK_COR_SEQ_2_USE => "FALSE",
+ CLK_COR_SEQ_LEN => 1,
+ CPLL_CFG0 => X"67F8",
+ CPLL_CFG1 => X"A4AC",
+ CPLL_CFG2 => X"5007",
+ CPLL_CFG3 => B"00" & X"0",
+ CPLL_FBDIV => 2,
+ CPLL_FBDIV_45 => 5,
+ CPLL_INIT_CFG0 => X"02B2",
+ CPLL_INIT_CFG1 => X"00",
+ CPLL_LOCK_CFG => X"01E8",
+ CPLL_REFCLK_DIV => 1,
+ DDI_CTRL => B"00",
+ DDI_REALIGN_WAIT => 15,
+ DEC_MCOMMA_DETECT => "FALSE",
+ DEC_PCOMMA_DETECT => "FALSE",
+ DEC_VALID_COMMA_ONLY => "FALSE",
+ DFE_D_X_REL_POS => '0',
+ DFE_VCM_COMP_EN => '0',
+ DMONITOR_CFG0 => B"00" & X"00",
+ DMONITOR_CFG1 => X"00",
+ ES_CLK_PHASE_SEL => '0',
+ ES_CONTROL => B"000000",
+ ES_ERRDET_EN => "FALSE",
+ ES_EYE_SCAN_EN => "FALSE",
+ ES_HORZ_OFFSET => X"000",
+ ES_PMA_CFG => B"0000000000",
+ ES_PRESCALE => B"00000",
+ ES_QUALIFIER0 => X"0000",
+ ES_QUALIFIER1 => X"0000",
+ ES_QUALIFIER2 => X"0000",
+ ES_QUALIFIER3 => X"0000",
+ ES_QUALIFIER4 => X"0000",
+ ES_QUAL_MASK0 => X"0000",
+ ES_QUAL_MASK1 => X"0000",
+ ES_QUAL_MASK2 => X"0000",
+ ES_QUAL_MASK3 => X"0000",
+ ES_QUAL_MASK4 => X"0000",
+ ES_SDATA_MASK0 => X"0000",
+ ES_SDATA_MASK1 => X"0000",
+ ES_SDATA_MASK2 => X"0000",
+ ES_SDATA_MASK3 => X"0000",
+ ES_SDATA_MASK4 => X"0000",
+ EVODD_PHI_CFG => B"00000000000",
+ EYE_SCAN_SWAP_EN => '0',
+ FTS_DESKEW_SEQ_ENABLE => B"1111",
+ FTS_LANE_DESKEW_CFG => B"1111",
+ FTS_LANE_DESKEW_EN => "FALSE",
+ GEARBOX_MODE => B"00000",
+ GM_BIAS_SELECT => '0',
+ LOCAL_MASTER => '1',
+ OOBDIVCTL => B"00",
+ OOB_PWRUP => '0',
+ PCI3_AUTO_REALIGN => "OVR_1K_BLK",
+ PCI3_PIPE_RX_ELECIDLE => '0',
+ PCI3_RX_ASYNC_EBUF_BYPASS => B"00",
+ PCI3_RX_ELECIDLE_EI2_ENABLE => '0',
+ PCI3_RX_ELECIDLE_H2L_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_H2L_DISABLE => B"000",
+ PCI3_RX_ELECIDLE_HI_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_LP4_DISABLE => '0',
+ PCI3_RX_FIFO_DISABLE => '0',
+ PCIE_BUFG_DIV_CTRL => X"1000",
+ PCIE_RXPCS_CFG_GEN3 => X"02A4",
+ PCIE_RXPMA_CFG => X"000A",
+ PCIE_TXPCS_CFG_GEN3 => X"24A4",
+ PCIE_TXPMA_CFG => X"000A",
+ PCS_PCIE_EN => "FALSE",
+ PCS_RSVD0 => B"0000000000000000",
+ PCS_RSVD1 => B"000",
+ PD_TRANS_TIME_FROM_P2 => X"03C",
+ PD_TRANS_TIME_NONE_P2 => X"19",
+ PD_TRANS_TIME_TO_P2 => X"64",
+ PLL_SEL_MODE_GEN12 => B"00",
+ PLL_SEL_MODE_GEN3 => B"11",
+ PMA_RSV1 => X"F000",
+ PROCESS_PAR => B"010",
+ RATE_SW_USE_DRP => '1',
+ RESET_POWERSAVE_DISABLE => '0',
+ RXBUFRESET_TIME => B"00011",
+ RXBUF_ADDR_MODE => "FAST",
+ RXBUF_EIDLE_HI_CNT => B"1000",
+ RXBUF_EIDLE_LO_CNT => B"0000",
+ RXBUF_EN => "TRUE",
+ RXBUF_RESET_ON_CB_CHANGE => "TRUE",
+ RXBUF_RESET_ON_COMMAALIGN => "FALSE",
+ RXBUF_RESET_ON_EIDLE => "FALSE",
+ RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ RXBUF_THRESH_OVFLW => 61,
+ RXBUF_THRESH_OVRD => "TRUE",
+ RXBUF_THRESH_UNDFLW => 1,
+ RXCDRFREQRESET_TIME => B"00001",
+ RXCDRPHRESET_TIME => B"00001",
+ RXCDR_CFG0 => X"0000",
+ RXCDR_CFG0_GEN3 => X"0000",
+ RXCDR_CFG1 => X"0000",
+ RXCDR_CFG1_GEN3 => X"0000",
+ RXCDR_CFG2 => X"07E6",
+ RXCDR_CFG2_GEN3 => X"07E6",
+ RXCDR_CFG3 => X"0000",
+ RXCDR_CFG3_GEN3 => X"0000",
+ RXCDR_CFG4 => X"0000",
+ RXCDR_CFG4_GEN3 => X"0000",
+ RXCDR_CFG5 => X"0000",
+ RXCDR_CFG5_GEN3 => X"0000",
+ RXCDR_FR_RESET_ON_EIDLE => '0',
+ RXCDR_HOLD_DURING_EIDLE => '0',
+ RXCDR_LOCK_CFG0 => X"4480",
+ RXCDR_LOCK_CFG1 => X"5FFF",
+ RXCDR_LOCK_CFG2 => X"77C3",
+ RXCDR_PH_RESET_ON_EIDLE => '0',
+ RXCFOK_CFG0 => X"4000",
+ RXCFOK_CFG1 => X"0065",
+ RXCFOK_CFG2 => X"002E",
+ RXDFELPMRESET_TIME => B"0001111",
+ RXDFELPM_KL_CFG0 => X"0000",
+ RXDFELPM_KL_CFG1 => X"0002",
+ RXDFELPM_KL_CFG2 => X"0000",
+ RXDFE_CFG0 => X"0A00",
+ RXDFE_CFG1 => X"0000",
+ RXDFE_GC_CFG0 => X"0000",
+ RXDFE_GC_CFG1 => X"7870",
+ RXDFE_GC_CFG2 => X"0000",
+ RXDFE_H2_CFG0 => X"0000",
+ RXDFE_H2_CFG1 => X"0000",
+ RXDFE_H3_CFG0 => X"4000",
+ RXDFE_H3_CFG1 => X"0000",
+ RXDFE_H4_CFG0 => X"2000",
+ RXDFE_H4_CFG1 => X"0003",
+ RXDFE_H5_CFG0 => X"2000",
+ RXDFE_H5_CFG1 => X"0003",
+ RXDFE_H6_CFG0 => X"2000",
+ RXDFE_H6_CFG1 => X"0000",
+ RXDFE_H7_CFG0 => X"2000",
+ RXDFE_H7_CFG1 => X"0000",
+ RXDFE_H8_CFG0 => X"2000",
+ RXDFE_H8_CFG1 => X"0000",
+ RXDFE_H9_CFG0 => X"2000",
+ RXDFE_H9_CFG1 => X"0000",
+ RXDFE_HA_CFG0 => X"2000",
+ RXDFE_HA_CFG1 => X"0000",
+ RXDFE_HB_CFG0 => X"2000",
+ RXDFE_HB_CFG1 => X"0000",
+ RXDFE_HC_CFG0 => X"0000",
+ RXDFE_HC_CFG1 => X"0000",
+ RXDFE_HD_CFG0 => X"0000",
+ RXDFE_HD_CFG1 => X"0000",
+ RXDFE_HE_CFG0 => X"0000",
+ RXDFE_HE_CFG1 => X"0000",
+ RXDFE_HF_CFG0 => X"0000",
+ RXDFE_HF_CFG1 => X"0000",
+ RXDFE_OS_CFG0 => X"8000",
+ RXDFE_OS_CFG1 => X"0000",
+ RXDFE_UT_CFG0 => X"8000",
+ RXDFE_UT_CFG1 => X"0003",
+ RXDFE_VP_CFG0 => X"AA00",
+ RXDFE_VP_CFG1 => X"0033",
+ RXDLY_CFG => X"001F",
+ RXDLY_LCFG => X"0030",
+ RXELECIDLE_CFG => "Sigcfg_4",
+ RXGBOX_FIFO_INIT_RD_ADDR => 4,
+ RXGEARBOX_EN => "FALSE",
+ RXISCANRESET_TIME => B"00001",
+ RXLPM_CFG => X"0000",
+ RXLPM_GC_CFG => X"1000",
+ RXLPM_KH_CFG0 => X"0000",
+ RXLPM_KH_CFG1 => X"0002",
+ RXLPM_OS_CFG0 => X"8000",
+ RXLPM_OS_CFG1 => X"0002",
+ RXOOB_CFG => B"000000110",
+ RXOOB_CLK_CFG => "PMA",
+ RXOSCALRESET_TIME => B"00011",
+ RXOUT_DIV => 1,
+ RXPCSRESET_TIME => B"00011",
+ RXPHBEACON_CFG => X"0000",
+ RXPHDLY_CFG => X"2020",
+ RXPHSAMP_CFG => X"2100",
+ RXPHSLIP_CFG => X"6622",
+ RXPH_MONITOR_SEL => B"00000",
+ RXPI_CFG0 => B"00",
+ RXPI_CFG1 => B"00",
+ RXPI_CFG2 => B"00",
+ RXPI_CFG3 => B"00",
+ RXPI_CFG4 => '1',
+ RXPI_CFG5 => '1',
+ RXPI_CFG6 => B"011",
+ RXPI_LPM => '0',
+ RXPI_VREFSEL => '0',
+ RXPMACLK_SEL => "DATA",
+ RXPMARESET_TIME => B"00011",
+ RXPRBS_ERR_LOOPBACK => '0',
+ RXPRBS_LINKACQ_CNT => 15,
+ RXSLIDE_AUTO_WAIT => 7,
+ RXSLIDE_MODE => "PMA",
+ RXSYNC_MULTILANE => '1',
+ RXSYNC_OVRD => '0',
+ RXSYNC_SKIP_DA => '0',
+ RX_AFE_CM_EN => '0',
+ RX_BIAS_CFG0 => X"0AB4",
+ RX_BUFFER_CFG => B"000000",
+ RX_CAPFF_SARC_ENB => '0',
+ RX_CLK25_DIV => 10,
+ RX_CLKMUX_EN => '1',
+ RX_CLK_SLIP_OVRD => B"00000",
+ RX_CM_BUF_CFG => B"1010",
+ RX_CM_BUF_PD => '0',
+ RX_CM_SEL => B"11",
+ RX_CM_TRIM => B"1010",
+ RX_CTLE3_LPF => B"00000001",
+ RX_DATA_WIDTH => 20,
+ RX_DDI_SEL => B"000000",
+ RX_DEFER_RESET_BUF_EN => "TRUE",
+ RX_DFELPM_CFG0 => B"0110",
+ RX_DFELPM_CFG1 => '1',
+ RX_DFELPM_KLKH_AGC_STUP_EN => '1',
+ RX_DFE_AGC_CFG0 => B"10",
+ RX_DFE_AGC_CFG1 => B"100",
+ RX_DFE_KL_LPM_KH_CFG0 => B"01",
+ RX_DFE_KL_LPM_KH_CFG1 => B"100",
+ RX_DFE_KL_LPM_KL_CFG0 => B"01",
+ RX_DFE_KL_LPM_KL_CFG1 => B"100",
+ RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
+ RX_DISPERR_SEQ_MATCH => "TRUE",
+ RX_DIVRESET_TIME => B"00001",
+ RX_EN_HI_LR => '0',
+ RX_EYESCAN_VS_CODE => B"0000000",
+ RX_EYESCAN_VS_NEG_DIR => '0',
+ RX_EYESCAN_VS_RANGE => B"00",
+ RX_EYESCAN_VS_UT_SIGN => '0',
+ RX_FABINT_USRCLK_FLOP => '0',
+ RX_INT_DATAWIDTH => 0,
+ RX_PMA_POWER_SAVE => '0',
+ RX_PROGDIV_CFG => 0.000000,
+ RX_SAMPLE_PERIOD => B"111",
+ RX_SIG_VALID_DLY => 11,
+ RX_SUM_DFETAPREP_EN => '0',
+ RX_SUM_IREF_TUNE => B"0000",
+ RX_SUM_RES_CTRL => B"00",
+ RX_SUM_VCMTUNE => B"0000",
+ RX_SUM_VCM_OVWR => '0',
+ RX_SUM_VREF_TUNE => B"000",
+ RX_TUNE_AFE_OS => B"10",
+ RX_WIDEMODE_CDR => '0',
+ RX_XCLK_SEL => "RXDES",
+ SAS_MAX_COM => 64,
+ SAS_MIN_COM => 36,
+ SATA_BURST_SEQ_LEN => B"1110",
+ SATA_BURST_VAL => B"100",
+ SATA_CPLL_CFG => "VCO_3000MHZ",
+ SATA_EIDLE_VAL => B"100",
+ SATA_MAX_BURST => 8,
+ SATA_MAX_INIT => 21,
+ SATA_MAX_WAKE => 7,
+ SATA_MIN_BURST => 4,
+ SATA_MIN_INIT => 12,
+ SATA_MIN_WAKE => 4,
+ SHOW_REALIGN_COMMA => "FALSE",
+ SIM_MODE => "FAST",
+ SIM_RECEIVER_DETECT_PASS => "TRUE",
+ SIM_RESET_SPEEDUP => "TRUE",
+ SIM_TX_EIDLE_DRIVE_LEVEL => '0',
+ SIM_VERSION => 2,
+ TAPDLY_SET_TX => B"00",
+ TEMPERATUR_PAR => B"0010",
+ TERM_RCAL_CFG => B"100001000010000",
+ TERM_RCAL_OVRD => B"000",
+ TRANS_TIME_RATE => X"0E",
+ TST_RSV0 => X"00",
+ TST_RSV1 => X"00",
+ TXBUF_EN => "FALSE",
+ TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ TXDLY_CFG => X"0009",
+ TXDLY_LCFG => X"0050",
+ TXDRVBIAS_N => B"1010",
+ TXDRVBIAS_P => B"1010",
+ TXFIFO_ADDR_CFG => "LOW",
+ TXGBOX_FIFO_INIT_RD_ADDR => 4,
+ TXGEARBOX_EN => "FALSE",
+ TXOUT_DIV => 2,
+ TXPCSRESET_TIME => B"00011",
+ TXPHDLY_CFG0 => X"2020",
+ TXPHDLY_CFG1 => X"0075",
+ TXPH_CFG => X"0980",
+ TXPH_MONITOR_SEL => B"00000",
+ TXPI_CFG0 => B"00",
+ TXPI_CFG1 => B"00",
+ TXPI_CFG2 => B"00",
+ TXPI_CFG3 => '1',
+ TXPI_CFG4 => '1',
+ TXPI_CFG5 => B"000",
+ TXPI_GRAY_SEL => '0',
+ TXPI_INVSTROBE_SEL => '1',
+ TXPI_LPM => '0',
+ TXPI_PPMCLK_SEL => "TXUSRCLK2",
+ TXPI_PPM_CFG => B"00000000",
+ TXPI_SYNFREQ_PPM => B"001",
+ TXPI_VREFSEL => '0',
+ TXPMARESET_TIME => B"00011",
+ TXSYNC_MULTILANE => '1',
+ TXSYNC_OVRD => '0',
+ TXSYNC_SKIP_DA => '0',
+ TX_CLK25_DIV => 10,
+ TX_CLKMUX_EN => '1',
+ TX_DATA_WIDTH => 20,
+ TX_DCD_CFG => B"000010",
+ TX_DCD_EN => '0',
+ TX_DEEMPH0 => B"000000",
+ TX_DEEMPH1 => B"000000",
+ TX_DIVRESET_TIME => B"00001",
+ TX_DRIVE_MODE => "DIRECT",
+ TX_EIDLE_ASSERT_DELAY => B"100",
+ TX_EIDLE_DEASSERT_DELAY => B"011",
+ TX_EML_PHI_TUNE => '0',
+ TX_FABINT_USRCLK_FLOP => '0',
+ TX_IDLE_DATA_ZERO => '0',
+ TX_INT_DATAWIDTH => 0,
+ TX_LOOPBACK_DRIVE_HIZ => "FALSE",
+ TX_MAINCURSOR_SEL => '0',
+ TX_MARGIN_FULL_0 => B"1001111",
+ TX_MARGIN_FULL_1 => B"1001110",
+ TX_MARGIN_FULL_2 => B"1001100",
+ TX_MARGIN_FULL_3 => B"1001010",
+ TX_MARGIN_FULL_4 => B"1001000",
+ TX_MARGIN_LOW_0 => B"1000110",
+ TX_MARGIN_LOW_1 => B"1000101",
+ TX_MARGIN_LOW_2 => B"1000011",
+ TX_MARGIN_LOW_3 => B"1000010",
+ TX_MARGIN_LOW_4 => B"1000000",
+ TX_MODE_SEL => B"000",
+ TX_PMADATA_OPT => '0',
+ TX_PMA_POWER_SAVE => '0',
+ TX_PROGCLK_SEL => "PREPI",
+ TX_PROGDIV_CFG => 0.000000,
+ TX_QPI_STATUS_EN => '0',
+ TX_RXDETECT_CFG => B"00" & X"032",
+ TX_RXDETECT_REF => B"100",
+ TX_SAMPLE_PERIOD => B"111",
+ TX_SARC_LPBK_ENB => '0',
+ TX_XCLK_SEL => "TXUSR",
+ USE_PCS_CLK_PHASE_SEL => '0',
+ WB_MODE => B"00"
+ )
+ port map (
+ BUFGTCE(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_289\,
+ BUFGTCE(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_290\,
+ BUFGTCE(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_291\,
+ BUFGTCEMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_292\,
+ BUFGTCEMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_293\,
+ BUFGTCEMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_294\,
+ BUFGTDIV(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_357\,
+ BUFGTDIV(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_358\,
+ BUFGTDIV(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_359\,
+ BUFGTDIV(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_360\,
+ BUFGTDIV(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_361\,
+ BUFGTDIV(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_362\,
+ BUFGTDIV(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_363\,
+ BUFGTDIV(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_364\,
+ BUFGTDIV(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_365\,
+ BUFGTRESET(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_295\,
+ BUFGTRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_296\,
+ BUFGTRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_297\,
+ BUFGTRSTMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_298\,
+ BUFGTRSTMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_299\,
+ BUFGTRSTMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_300\,
+ CFGRESET => '0',
+ CLKRSVD0 => '0',
+ CLKRSVD1 => '0',
+ CPLLFBCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_0\,
+ CPLLLOCK => cplllock_out(2),
+ CPLLLOCKDETCLK => '0',
+ CPLLLOCKEN => '1',
+ CPLLPD => GTHE3_CHANNEL_CPLLPD(0),
+ CPLLREFCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_2\,
+ CPLLREFCLKSEL(2 downto 0) => B"001",
+ CPLLRESET => '0',
+ DMONFIFORESET => '0',
+ DMONITORCLK => '0',
+ DMONITOROUT(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_258\,
+ DMONITOROUT(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_259\,
+ DMONITOROUT(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_260\,
+ DMONITOROUT(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_261\,
+ DMONITOROUT(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_262\,
+ DMONITOROUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_263\,
+ DMONITOROUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_264\,
+ DMONITOROUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_265\,
+ DMONITOROUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_266\,
+ DMONITOROUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_267\,
+ DMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_268\,
+ DMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_269\,
+ DMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_270\,
+ DMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_271\,
+ DMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_272\,
+ DMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_273\,
+ DMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_274\,
+ DRPADDR(8 downto 0) => B"000000000",
+ DRPCLK => drpclk_in(2),
+ DRPDI(15 downto 0) => B"0000000000000000",
+ DRPDO(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_210\,
+ DRPDO(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_211\,
+ DRPDO(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_212\,
+ DRPDO(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_213\,
+ DRPDO(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_214\,
+ DRPDO(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_215\,
+ DRPDO(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_216\,
+ DRPDO(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_217\,
+ DRPDO(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_218\,
+ DRPDO(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_219\,
+ DRPDO(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_220\,
+ DRPDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_221\,
+ DRPDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_222\,
+ DRPDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_223\,
+ DRPDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_224\,
+ DRPDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_225\,
+ DRPEN => '0',
+ DRPRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_3\,
+ DRPWE => '0',
+ EVODDPHICALDONE => '0',
+ EVODDPHICALSTART => '0',
+ EVODDPHIDRDEN => '0',
+ EVODDPHIDWREN => '0',
+ EVODDPHIXRDEN => '0',
+ EVODDPHIXWREN => '0',
+ EYESCANDATAERROR => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_4\,
+ EYESCANMODE => '0',
+ EYESCANRESET => '0',
+ EYESCANTRIGGER => '0',
+ GTGREFCLK => '0',
+ GTHRXN => gthrxn_in(2),
+ GTHRXP => gthrxp_in(2),
+ GTHTXN => gthtxn_out(2),
+ GTHTXP => gthtxp_out(2),
+ GTNORTHREFCLK0 => '0',
+ GTNORTHREFCLK1 => '0',
+ GTPOWERGOOD => gtpowergood_out(2),
+ GTREFCLK0 => gtrefclk0_in(2),
+ GTREFCLK1 => '0',
+ GTREFCLKMONITOR => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_8\,
+ GTRESETSEL => '0',
+ GTRSVD(15 downto 0) => B"0000000000000000",
+ GTRXRESET => GTHE3_CHANNEL_GTRXRESET(0),
+ GTSOUTHREFCLK0 => '0',
+ GTSOUTHREFCLK1 => '0',
+ GTTXRESET => GTHE3_CHANNEL_GTTXRESET(0),
+ LOOPBACK(2 downto 0) => loopback_in(8 downto 6),
+ LPBKRXTXSEREN => '0',
+ LPBKTXRXSEREN => '0',
+ PCIEEQRXEQADAPTDONE => '0',
+ PCIERATEGEN3 => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_9\,
+ PCIERATEIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_10\,
+ PCIERATEQPLLPD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_275\,
+ PCIERATEQPLLPD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_276\,
+ PCIERATEQPLLRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_277\,
+ PCIERATEQPLLRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_278\,
+ PCIERSTIDLE => '0',
+ PCIERSTTXSYNCSTART => '0',
+ PCIESYNCTXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_11\,
+ PCIEUSERGEN3RDY => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_12\,
+ PCIEUSERPHYSTATUSRST => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_13\,
+ PCIEUSERRATEDONE => '0',
+ PCIEUSERRATESTART => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_14\,
+ PCSRSVDIN(15 downto 0) => B"0000000000000000",
+ PCSRSVDIN2(4 downto 0) => B"00000",
+ PCSRSVDOUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_70\,
+ PCSRSVDOUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_71\,
+ PCSRSVDOUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_72\,
+ PCSRSVDOUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_73\,
+ PCSRSVDOUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_74\,
+ PCSRSVDOUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_75\,
+ PCSRSVDOUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_76\,
+ PCSRSVDOUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_77\,
+ PCSRSVDOUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_78\,
+ PCSRSVDOUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_79\,
+ PCSRSVDOUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_80\,
+ PCSRSVDOUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_81\,
+ PHYSTATUS => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_15\,
+ PINRSRVDAS(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_325\,
+ PINRSRVDAS(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_326\,
+ PINRSRVDAS(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_327\,
+ PINRSRVDAS(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_328\,
+ PINRSRVDAS(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_329\,
+ PINRSRVDAS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_330\,
+ PINRSRVDAS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_331\,
+ PINRSRVDAS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_332\,
+ PMARSVDIN(4 downto 0) => B"00000",
+ QPLL0CLK => qpll0outclk_out(0),
+ QPLL0REFCLK => qpll0outrefclk_out(0),
+ QPLL1CLK => qpll1outclk_out(0),
+ QPLL1REFCLK => qpll1outrefclk_out(0),
+ RESETEXCEPTION => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_16\,
+ RESETOVRD => '0',
+ RSTCLKENTX => '0',
+ RX8B10BEN => '0',
+ RXBUFRESET => '0',
+ RXBUFSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_301\,
+ RXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_302\,
+ RXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_303\,
+ RXBYTEISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_17\,
+ RXBYTEREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_18\,
+ RXCDRFREQRESET => '0',
+ RXCDRHOLD => rxcdrhold_in(2),
+ RXCDRLOCK => rxcdrlock_out(2),
+ RXCDROVRDEN => '0',
+ RXCDRPHDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_20\,
+ RXCDRRESET => '0',
+ RXCDRRESETRSV => '0',
+ RXCHANBONDSEQ => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_21\,
+ RXCHANISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_22\,
+ RXCHANREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_23\,
+ RXCHBONDEN => '0',
+ RXCHBONDI(4 downto 0) => B"00000",
+ RXCHBONDLEVEL(2 downto 0) => B"000",
+ RXCHBONDMASTER => '0',
+ RXCHBONDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_307\,
+ RXCHBONDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_308\,
+ RXCHBONDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_309\,
+ RXCHBONDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_310\,
+ RXCHBONDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_311\,
+ RXCHBONDSLAVE => '0',
+ RXCLKCORCNT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_279\,
+ RXCLKCORCNT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_280\,
+ RXCOMINITDET => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_24\,
+ RXCOMMADET => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_25\,
+ RXCOMMADETEN => '1',
+ RXCOMSASDET => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_26\,
+ RXCOMWAKEDET => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_27\,
+ RXCTRL0(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_226\,
+ RXCTRL0(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_227\,
+ RXCTRL0(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_228\,
+ RXCTRL0(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_229\,
+ RXCTRL0(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_230\,
+ RXCTRL0(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_231\,
+ RXCTRL0(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_232\,
+ RXCTRL0(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_233\,
+ RXCTRL0(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_234\,
+ RXCTRL0(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_235\,
+ RXCTRL0(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_236\,
+ RXCTRL0(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_237\,
+ RXCTRL0(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_238\,
+ RXCTRL0(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_239\,
+ RXCTRL0(1) => gtwiz_userdata_rx_out(58),
+ RXCTRL0(0) => gtwiz_userdata_rx_out(48),
+ RXCTRL1(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_242\,
+ RXCTRL1(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_243\,
+ RXCTRL1(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_244\,
+ RXCTRL1(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_245\,
+ RXCTRL1(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_246\,
+ RXCTRL1(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_247\,
+ RXCTRL1(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_248\,
+ RXCTRL1(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_249\,
+ RXCTRL1(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_250\,
+ RXCTRL1(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_251\,
+ RXCTRL1(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_252\,
+ RXCTRL1(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_253\,
+ RXCTRL1(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_254\,
+ RXCTRL1(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_255\,
+ RXCTRL1(1) => gtwiz_userdata_rx_out(59),
+ RXCTRL1(0) => gtwiz_userdata_rx_out(49),
+ RXCTRL2(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_333\,
+ RXCTRL2(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_334\,
+ RXCTRL2(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_335\,
+ RXCTRL2(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_336\,
+ RXCTRL2(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_337\,
+ RXCTRL2(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_338\,
+ RXCTRL2(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_339\,
+ RXCTRL2(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_340\,
+ RXCTRL3(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_341\,
+ RXCTRL3(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_342\,
+ RXCTRL3(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_343\,
+ RXCTRL3(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_344\,
+ RXCTRL3(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_345\,
+ RXCTRL3(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_346\,
+ RXCTRL3(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_347\,
+ RXCTRL3(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_348\,
+ RXDATA(127) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_82\,
+ RXDATA(126) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_83\,
+ RXDATA(125) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_84\,
+ RXDATA(124) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_85\,
+ RXDATA(123) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_86\,
+ RXDATA(122) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_87\,
+ RXDATA(121) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_88\,
+ RXDATA(120) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_89\,
+ RXDATA(119) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_90\,
+ RXDATA(118) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_91\,
+ RXDATA(117) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_92\,
+ RXDATA(116) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_93\,
+ RXDATA(115) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_94\,
+ RXDATA(114) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_95\,
+ RXDATA(113) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_96\,
+ RXDATA(112) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_97\,
+ RXDATA(111) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_98\,
+ RXDATA(110) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_99\,
+ RXDATA(109) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_100\,
+ RXDATA(108) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_101\,
+ RXDATA(107) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_102\,
+ RXDATA(106) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_103\,
+ RXDATA(105) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_104\,
+ RXDATA(104) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_105\,
+ RXDATA(103) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_106\,
+ RXDATA(102) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_107\,
+ RXDATA(101) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_108\,
+ RXDATA(100) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_109\,
+ RXDATA(99) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_110\,
+ RXDATA(98) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_111\,
+ RXDATA(97) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_112\,
+ RXDATA(96) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_113\,
+ RXDATA(95) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_114\,
+ RXDATA(94) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_115\,
+ RXDATA(93) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_116\,
+ RXDATA(92) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_117\,
+ RXDATA(91) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_118\,
+ RXDATA(90) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_119\,
+ RXDATA(89) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_120\,
+ RXDATA(88) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_121\,
+ RXDATA(87) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_122\,
+ RXDATA(86) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_123\,
+ RXDATA(85) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_124\,
+ RXDATA(84) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_125\,
+ RXDATA(83) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_126\,
+ RXDATA(82) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_127\,
+ RXDATA(81) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_128\,
+ RXDATA(80) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_129\,
+ RXDATA(79) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_130\,
+ RXDATA(78) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_131\,
+ RXDATA(77) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_132\,
+ RXDATA(76) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_133\,
+ RXDATA(75) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_134\,
+ RXDATA(74) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_135\,
+ RXDATA(73) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_136\,
+ RXDATA(72) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_137\,
+ RXDATA(71) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_138\,
+ RXDATA(70) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_139\,
+ RXDATA(69) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_140\,
+ RXDATA(68) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_141\,
+ RXDATA(67) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_142\,
+ RXDATA(66) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_143\,
+ RXDATA(65) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_144\,
+ RXDATA(64) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_145\,
+ RXDATA(63) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_146\,
+ RXDATA(62) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_147\,
+ RXDATA(61) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_148\,
+ RXDATA(60) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_149\,
+ RXDATA(59) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_150\,
+ RXDATA(58) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_151\,
+ RXDATA(57) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_152\,
+ RXDATA(56) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_153\,
+ RXDATA(55) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_154\,
+ RXDATA(54) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_155\,
+ RXDATA(53) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_156\,
+ RXDATA(52) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_157\,
+ RXDATA(51) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_158\,
+ RXDATA(50) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_159\,
+ RXDATA(49) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_160\,
+ RXDATA(48) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_161\,
+ RXDATA(47) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_162\,
+ RXDATA(46) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_163\,
+ RXDATA(45) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_164\,
+ RXDATA(44) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_165\,
+ RXDATA(43) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_166\,
+ RXDATA(42) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_167\,
+ RXDATA(41) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_168\,
+ RXDATA(40) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_169\,
+ RXDATA(39) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_170\,
+ RXDATA(38) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_171\,
+ RXDATA(37) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_172\,
+ RXDATA(36) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_173\,
+ RXDATA(35) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_174\,
+ RXDATA(34) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_175\,
+ RXDATA(33) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_176\,
+ RXDATA(32) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_177\,
+ RXDATA(31) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_178\,
+ RXDATA(30) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_179\,
+ RXDATA(29) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_180\,
+ RXDATA(28) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_181\,
+ RXDATA(27) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_182\,
+ RXDATA(26) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_183\,
+ RXDATA(25) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_184\,
+ RXDATA(24) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_185\,
+ RXDATA(23) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_186\,
+ RXDATA(22) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_187\,
+ RXDATA(21) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_188\,
+ RXDATA(20) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_189\,
+ RXDATA(19) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_190\,
+ RXDATA(18) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_191\,
+ RXDATA(17) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_192\,
+ RXDATA(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_193\,
+ RXDATA(15 downto 8) => gtwiz_userdata_rx_out(57 downto 50),
+ RXDATA(7 downto 0) => gtwiz_userdata_rx_out(47 downto 40),
+ RXDATAEXTENDRSVD(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_349\,
+ RXDATAEXTENDRSVD(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_350\,
+ RXDATAEXTENDRSVD(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_351\,
+ RXDATAEXTENDRSVD(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_352\,
+ RXDATAEXTENDRSVD(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_353\,
+ RXDATAEXTENDRSVD(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_354\,
+ RXDATAEXTENDRSVD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_355\,
+ RXDATAEXTENDRSVD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_356\,
+ RXDATAVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_281\,
+ RXDATAVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_282\,
+ RXDFEAGCCTRL(1 downto 0) => B"01",
+ RXDFEAGCHOLD => '0',
+ RXDFEAGCOVRDEN => '0',
+ RXDFELFHOLD => '0',
+ RXDFELFOVRDEN => '0',
+ RXDFELPMRESET => '0',
+ RXDFETAP10HOLD => '0',
+ RXDFETAP10OVRDEN => '0',
+ RXDFETAP11HOLD => '0',
+ RXDFETAP11OVRDEN => '0',
+ RXDFETAP12HOLD => '0',
+ RXDFETAP12OVRDEN => '0',
+ RXDFETAP13HOLD => '0',
+ RXDFETAP13OVRDEN => '0',
+ RXDFETAP14HOLD => '0',
+ RXDFETAP14OVRDEN => '0',
+ RXDFETAP15HOLD => '0',
+ RXDFETAP15OVRDEN => '0',
+ RXDFETAP2HOLD => '0',
+ RXDFETAP2OVRDEN => '0',
+ RXDFETAP3HOLD => '0',
+ RXDFETAP3OVRDEN => '0',
+ RXDFETAP4HOLD => '0',
+ RXDFETAP4OVRDEN => '0',
+ RXDFETAP5HOLD => '0',
+ RXDFETAP5OVRDEN => '0',
+ RXDFETAP6HOLD => '0',
+ RXDFETAP6OVRDEN => '0',
+ RXDFETAP7HOLD => '0',
+ RXDFETAP7OVRDEN => '0',
+ RXDFETAP8HOLD => '0',
+ RXDFETAP8OVRDEN => '0',
+ RXDFETAP9HOLD => '0',
+ RXDFETAP9OVRDEN => '0',
+ RXDFEUTHOLD => '0',
+ RXDFEUTOVRDEN => '0',
+ RXDFEVPHOLD => '0',
+ RXDFEVPOVRDEN => '0',
+ RXDFEVSEN => '0',
+ RXDFEXYDEN => '1',
+ RXDLYBYPASS => '1',
+ RXDLYEN => '0',
+ RXDLYOVRDEN => '0',
+ RXDLYSRESET => '0',
+ RXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_28\,
+ RXELECIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_29\,
+ RXELECIDLEMODE(1 downto 0) => B"11",
+ RXGEARBOXSLIP => '0',
+ RXHEADER(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_312\,
+ RXHEADER(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_313\,
+ RXHEADER(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_314\,
+ RXHEADER(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_315\,
+ RXHEADER(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_316\,
+ RXHEADER(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_317\,
+ RXHEADERVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_283\,
+ RXHEADERVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_284\,
+ RXLATCLK => '0',
+ RXLPMEN => '0',
+ RXLPMGCHOLD => '0',
+ RXLPMGCOVRDEN => '0',
+ RXLPMHFHOLD => '0',
+ RXLPMHFOVRDEN => '0',
+ RXLPMLFHOLD => '0',
+ RXLPMLFKLOVRDEN => '0',
+ RXLPMOSHOLD => '0',
+ RXLPMOSOVRDEN => '0',
+ RXMCOMMAALIGNEN => '0',
+ RXMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_318\,
+ RXMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_319\,
+ RXMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_320\,
+ RXMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_321\,
+ RXMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_322\,
+ RXMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_323\,
+ RXMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_324\,
+ RXMONITORSEL(1 downto 0) => B"00",
+ RXOOBRESET => '0',
+ RXOSCALRESET => '0',
+ RXOSHOLD => '0',
+ RXOSINTCFG(3 downto 0) => B"1101",
+ RXOSINTDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_30\,
+ RXOSINTEN => '1',
+ RXOSINTHOLD => '0',
+ RXOSINTOVRDEN => '0',
+ RXOSINTSTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_31\,
+ RXOSINTSTROBE => '0',
+ RXOSINTSTROBEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_32\,
+ RXOSINTSTROBESTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_33\,
+ RXOSINTTESTOVRDEN => '0',
+ RXOSOVRDEN => '0',
+ RXOUTCLK => rxoutclk_out(2),
+ RXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_35\,
+ RXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_36\,
+ RXOUTCLKSEL(2 downto 0) => B"010",
+ RXPCOMMAALIGNEN => '0',
+ RXPCSRESET => '0',
+ RXPD(1 downto 0) => B"00",
+ RXPHALIGN => '0',
+ RXPHALIGNDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_37\,
+ RXPHALIGNEN => '0',
+ RXPHALIGNERR => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_38\,
+ RXPHDLYPD => '0',
+ RXPHDLYRESET => '0',
+ RXPHOVRDEN => '0',
+ RXPLLCLKSEL(1 downto 0) => B"00",
+ RXPMARESET => '0',
+ RXPMARESETDONE => rxpmaresetdone_out(2),
+ RXPOLARITY => rxpolarity_in(2),
+ RXPRBSCNTRESET => '0',
+ RXPRBSERR => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_40\,
+ RXPRBSLOCKED => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_41\,
+ RXPRBSSEL(3 downto 0) => B"0000",
+ RXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_42\,
+ RXPROGDIVRESET => GTHE3_CHANNEL_RXPROGDIVRESET(0),
+ RXQPIEN => '0',
+ RXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_43\,
+ RXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_44\,
+ RXRATE(2 downto 0) => B"000",
+ RXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_45\,
+ RXRATEMODE => '0',
+ RXRECCLKOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_46\,
+ RXRESETDONE => rxresetdone_out(2),
+ RXSLIDE => rxslide_in(2),
+ RXSLIDERDY => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_48\,
+ RXSLIPDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_49\,
+ RXSLIPOUTCLK => '0',
+ RXSLIPOUTCLKRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_50\,
+ RXSLIPPMA => '0',
+ RXSLIPPMARDY => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_51\,
+ RXSTARTOFSEQ(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_285\,
+ RXSTARTOFSEQ(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_286\,
+ RXSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_304\,
+ RXSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_305\,
+ RXSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_306\,
+ RXSYNCALLIN => '0',
+ RXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_52\,
+ RXSYNCIN => '0',
+ RXSYNCMODE => '0',
+ RXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_53\,
+ RXSYSCLKSEL(1 downto 0) => B"00",
+ RXUSERRDY => GTHE3_CHANNEL_RXUSERRDY(0),
+ RXUSRCLK => rxusrclk_in(2),
+ RXUSRCLK2 => rxusrclk2_in(2),
+ RXVALID => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_54\,
+ SIGVALIDCLK => '0',
+ TSTIN(19 downto 0) => B"00000000000000000000",
+ TX8B10BBYPASS(7 downto 0) => B"00000000",
+ TX8B10BEN => '0',
+ TXBUFDIFFCTRL(2 downto 0) => B"000",
+ TXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_287\,
+ TXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_288\,
+ TXCOMFINISH => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_55\,
+ TXCOMINIT => '0',
+ TXCOMSAS => '0',
+ TXCOMWAKE => '0',
+ TXCTRL0(15 downto 2) => B"00000000000000",
+ TXCTRL0(1) => gtwiz_userdata_tx_in(58),
+ TXCTRL0(0) => gtwiz_userdata_tx_in(48),
+ TXCTRL1(15 downto 2) => B"00000000000000",
+ TXCTRL1(1) => gtwiz_userdata_tx_in(59),
+ TXCTRL1(0) => gtwiz_userdata_tx_in(49),
+ TXCTRL2(7 downto 0) => B"00000000",
+ TXDATA(127 downto 16) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ TXDATA(15 downto 8) => gtwiz_userdata_tx_in(57 downto 50),
+ TXDATA(7 downto 0) => gtwiz_userdata_tx_in(47 downto 40),
+ TXDATAEXTENDRSVD(7 downto 0) => B"00000000",
+ TXDEEMPH => '0',
+ TXDETECTRX => '0',
+ TXDIFFCTRL(3 downto 0) => B"1100",
+ TXDIFFPD => '0',
+ TXDLYBYPASS => '0',
+ TXDLYEN => '0',
+ TXDLYHOLD => '0',
+ TXDLYOVRDEN => '0',
+ TXDLYSRESET => GTHE3_CHANNEL_TXDLYSRESET(0),
+ TXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_56\,
+ TXDLYUPDOWN => '0',
+ TXELECIDLE => '0',
+ TXHEADER(5 downto 0) => B"000000",
+ TXINHIBIT => '0',
+ TXLATCLK => '0',
+ TXMAINCURSOR(6 downto 0) => B"1000000",
+ TXMARGIN(2 downto 0) => B"000",
+ TXOUTCLK => txoutclk_out(2),
+ TXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_58\,
+ TXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_59\,
+ TXOUTCLKSEL(2 downto 0) => B"011",
+ TXPCSRESET => '0',
+ TXPD(1 downto 0) => B"00",
+ TXPDELECIDLEMODE => '0',
+ TXPHALIGN => '0',
+ TXPHALIGNDONE => GTHE3_CHANNEL_TXPHALIGNDONE(2),
+ TXPHALIGNEN => '0',
+ TXPHDLYPD => '0',
+ TXPHDLYRESET => '0',
+ TXPHDLYTSTCLK => '0',
+ TXPHINIT => '0',
+ TXPHINITDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_61\,
+ TXPHOVRDEN => '0',
+ TXPIPPMEN => '0',
+ TXPIPPMOVRDEN => '0',
+ TXPIPPMPD => '0',
+ TXPIPPMSEL => '0',
+ TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
+ TXPISOPD => '0',
+ TXPLLCLKSEL(1 downto 0) => B"10",
+ TXPMARESET => '0',
+ TXPMARESETDONE => txpmaresetdone_out(2),
+ TXPOLARITY => txpolarity_in(2),
+ TXPOSTCURSOR(4 downto 0) => B"00000",
+ TXPOSTCURSORINV => '0',
+ TXPRBSFORCEERR => '0',
+ TXPRBSSEL(3 downto 0) => B"0000",
+ TXPRECURSOR(4 downto 0) => B"00000",
+ TXPRECURSORINV => '0',
+ TXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_63\,
+ TXPROGDIVRESET => GTHE3_CHANNEL_TXPROGDIVRESET(0),
+ TXQPIBIASEN => '0',
+ TXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_64\,
+ TXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_65\,
+ TXQPISTRONGPDOWN => '0',
+ TXQPIWEAKPUP => '0',
+ TXRATE(2 downto 0) => B"000",
+ TXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_66\,
+ TXRATEMODE => '0',
+ TXRESETDONE => txresetdone_out(2),
+ TXSEQUENCE(6 downto 0) => B"0000000",
+ TXSWING => '0',
+ TXSYNCALLIN => GTHE3_CHANNEL_TXSYNCALLIN(0),
+ TXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_68\,
+ TXSYNCIN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYNCMODE => '0',
+ TXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYSCLKSEL(1 downto 0) => B"11",
+ TXUSERRDY => GTHE3_CHANNEL_TXUSERRDY(0),
+ TXUSRCLK => txusrclk_in(2),
+ TXUSRCLK2 => txusrclk2_in(2)
+ );
+\gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST\: unisim.vcomponents.GTHE3_CHANNEL
+ generic map(
+ ACJTAG_DEBUG_MODE => '0',
+ ACJTAG_MODE => '0',
+ ACJTAG_RESET => '0',
+ ADAPT_CFG0 => X"F800",
+ ADAPT_CFG1 => X"0000",
+ ALIGN_COMMA_DOUBLE => "FALSE",
+ ALIGN_COMMA_ENABLE => B"0000000000",
+ ALIGN_COMMA_WORD => 1,
+ ALIGN_MCOMMA_DET => "FALSE",
+ ALIGN_MCOMMA_VALUE => B"1010000011",
+ ALIGN_PCOMMA_DET => "FALSE",
+ ALIGN_PCOMMA_VALUE => B"0101111100",
+ A_RXOSCALRESET => '0',
+ A_RXPROGDIVRESET => '0',
+ A_TXPROGDIVRESET => '0',
+ CBCC_DATA_SOURCE_SEL => "ENCODED",
+ CDR_SWAP_MODE_EN => '0',
+ CHAN_BOND_KEEP_ALIGN => "FALSE",
+ CHAN_BOND_MAX_SKEW => 1,
+ CHAN_BOND_SEQ_1_1 => B"0000000000",
+ CHAN_BOND_SEQ_1_2 => B"0000000000",
+ CHAN_BOND_SEQ_1_3 => B"0000000000",
+ CHAN_BOND_SEQ_1_4 => B"0000000000",
+ CHAN_BOND_SEQ_1_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_1 => B"0000000000",
+ CHAN_BOND_SEQ_2_2 => B"0000000000",
+ CHAN_BOND_SEQ_2_3 => B"0000000000",
+ CHAN_BOND_SEQ_2_4 => B"0000000000",
+ CHAN_BOND_SEQ_2_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_USE => "FALSE",
+ CHAN_BOND_SEQ_LEN => 1,
+ CLK_CORRECT_USE => "FALSE",
+ CLK_COR_KEEP_IDLE => "FALSE",
+ CLK_COR_MAX_LAT => 6,
+ CLK_COR_MIN_LAT => 4,
+ CLK_COR_PRECEDENCE => "TRUE",
+ CLK_COR_REPEAT_WAIT => 0,
+ CLK_COR_SEQ_1_1 => B"0000000000",
+ CLK_COR_SEQ_1_2 => B"0000000000",
+ CLK_COR_SEQ_1_3 => B"0000000000",
+ CLK_COR_SEQ_1_4 => B"0000000000",
+ CLK_COR_SEQ_1_ENABLE => B"1111",
+ CLK_COR_SEQ_2_1 => B"0000000000",
+ CLK_COR_SEQ_2_2 => B"0000000000",
+ CLK_COR_SEQ_2_3 => B"0000000000",
+ CLK_COR_SEQ_2_4 => B"0000000000",
+ CLK_COR_SEQ_2_ENABLE => B"1111",
+ CLK_COR_SEQ_2_USE => "FALSE",
+ CLK_COR_SEQ_LEN => 1,
+ CPLL_CFG0 => X"67F8",
+ CPLL_CFG1 => X"A4AC",
+ CPLL_CFG2 => X"5007",
+ CPLL_CFG3 => B"00" & X"0",
+ CPLL_FBDIV => 2,
+ CPLL_FBDIV_45 => 5,
+ CPLL_INIT_CFG0 => X"02B2",
+ CPLL_INIT_CFG1 => X"00",
+ CPLL_LOCK_CFG => X"01E8",
+ CPLL_REFCLK_DIV => 1,
+ DDI_CTRL => B"00",
+ DDI_REALIGN_WAIT => 15,
+ DEC_MCOMMA_DETECT => "FALSE",
+ DEC_PCOMMA_DETECT => "FALSE",
+ DEC_VALID_COMMA_ONLY => "FALSE",
+ DFE_D_X_REL_POS => '0',
+ DFE_VCM_COMP_EN => '0',
+ DMONITOR_CFG0 => B"00" & X"00",
+ DMONITOR_CFG1 => X"00",
+ ES_CLK_PHASE_SEL => '0',
+ ES_CONTROL => B"000000",
+ ES_ERRDET_EN => "FALSE",
+ ES_EYE_SCAN_EN => "FALSE",
+ ES_HORZ_OFFSET => X"000",
+ ES_PMA_CFG => B"0000000000",
+ ES_PRESCALE => B"00000",
+ ES_QUALIFIER0 => X"0000",
+ ES_QUALIFIER1 => X"0000",
+ ES_QUALIFIER2 => X"0000",
+ ES_QUALIFIER3 => X"0000",
+ ES_QUALIFIER4 => X"0000",
+ ES_QUAL_MASK0 => X"0000",
+ ES_QUAL_MASK1 => X"0000",
+ ES_QUAL_MASK2 => X"0000",
+ ES_QUAL_MASK3 => X"0000",
+ ES_QUAL_MASK4 => X"0000",
+ ES_SDATA_MASK0 => X"0000",
+ ES_SDATA_MASK1 => X"0000",
+ ES_SDATA_MASK2 => X"0000",
+ ES_SDATA_MASK3 => X"0000",
+ ES_SDATA_MASK4 => X"0000",
+ EVODD_PHI_CFG => B"00000000000",
+ EYE_SCAN_SWAP_EN => '0',
+ FTS_DESKEW_SEQ_ENABLE => B"1111",
+ FTS_LANE_DESKEW_CFG => B"1111",
+ FTS_LANE_DESKEW_EN => "FALSE",
+ GEARBOX_MODE => B"00000",
+ GM_BIAS_SELECT => '0',
+ LOCAL_MASTER => '1',
+ OOBDIVCTL => B"00",
+ OOB_PWRUP => '0',
+ PCI3_AUTO_REALIGN => "OVR_1K_BLK",
+ PCI3_PIPE_RX_ELECIDLE => '0',
+ PCI3_RX_ASYNC_EBUF_BYPASS => B"00",
+ PCI3_RX_ELECIDLE_EI2_ENABLE => '0',
+ PCI3_RX_ELECIDLE_H2L_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_H2L_DISABLE => B"000",
+ PCI3_RX_ELECIDLE_HI_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_LP4_DISABLE => '0',
+ PCI3_RX_FIFO_DISABLE => '0',
+ PCIE_BUFG_DIV_CTRL => X"1000",
+ PCIE_RXPCS_CFG_GEN3 => X"02A4",
+ PCIE_RXPMA_CFG => X"000A",
+ PCIE_TXPCS_CFG_GEN3 => X"24A4",
+ PCIE_TXPMA_CFG => X"000A",
+ PCS_PCIE_EN => "FALSE",
+ PCS_RSVD0 => B"0000000000000000",
+ PCS_RSVD1 => B"000",
+ PD_TRANS_TIME_FROM_P2 => X"03C",
+ PD_TRANS_TIME_NONE_P2 => X"19",
+ PD_TRANS_TIME_TO_P2 => X"64",
+ PLL_SEL_MODE_GEN12 => B"00",
+ PLL_SEL_MODE_GEN3 => B"11",
+ PMA_RSV1 => X"F000",
+ PROCESS_PAR => B"010",
+ RATE_SW_USE_DRP => '1',
+ RESET_POWERSAVE_DISABLE => '0',
+ RXBUFRESET_TIME => B"00011",
+ RXBUF_ADDR_MODE => "FAST",
+ RXBUF_EIDLE_HI_CNT => B"1000",
+ RXBUF_EIDLE_LO_CNT => B"0000",
+ RXBUF_EN => "TRUE",
+ RXBUF_RESET_ON_CB_CHANGE => "TRUE",
+ RXBUF_RESET_ON_COMMAALIGN => "FALSE",
+ RXBUF_RESET_ON_EIDLE => "FALSE",
+ RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ RXBUF_THRESH_OVFLW => 61,
+ RXBUF_THRESH_OVRD => "TRUE",
+ RXBUF_THRESH_UNDFLW => 1,
+ RXCDRFREQRESET_TIME => B"00001",
+ RXCDRPHRESET_TIME => B"00001",
+ RXCDR_CFG0 => X"0000",
+ RXCDR_CFG0_GEN3 => X"0000",
+ RXCDR_CFG1 => X"0000",
+ RXCDR_CFG1_GEN3 => X"0000",
+ RXCDR_CFG2 => X"07E6",
+ RXCDR_CFG2_GEN3 => X"07E6",
+ RXCDR_CFG3 => X"0000",
+ RXCDR_CFG3_GEN3 => X"0000",
+ RXCDR_CFG4 => X"0000",
+ RXCDR_CFG4_GEN3 => X"0000",
+ RXCDR_CFG5 => X"0000",
+ RXCDR_CFG5_GEN3 => X"0000",
+ RXCDR_FR_RESET_ON_EIDLE => '0',
+ RXCDR_HOLD_DURING_EIDLE => '0',
+ RXCDR_LOCK_CFG0 => X"4480",
+ RXCDR_LOCK_CFG1 => X"5FFF",
+ RXCDR_LOCK_CFG2 => X"77C3",
+ RXCDR_PH_RESET_ON_EIDLE => '0',
+ RXCFOK_CFG0 => X"4000",
+ RXCFOK_CFG1 => X"0065",
+ RXCFOK_CFG2 => X"002E",
+ RXDFELPMRESET_TIME => B"0001111",
+ RXDFELPM_KL_CFG0 => X"0000",
+ RXDFELPM_KL_CFG1 => X"0002",
+ RXDFELPM_KL_CFG2 => X"0000",
+ RXDFE_CFG0 => X"0A00",
+ RXDFE_CFG1 => X"0000",
+ RXDFE_GC_CFG0 => X"0000",
+ RXDFE_GC_CFG1 => X"7870",
+ RXDFE_GC_CFG2 => X"0000",
+ RXDFE_H2_CFG0 => X"0000",
+ RXDFE_H2_CFG1 => X"0000",
+ RXDFE_H3_CFG0 => X"4000",
+ RXDFE_H3_CFG1 => X"0000",
+ RXDFE_H4_CFG0 => X"2000",
+ RXDFE_H4_CFG1 => X"0003",
+ RXDFE_H5_CFG0 => X"2000",
+ RXDFE_H5_CFG1 => X"0003",
+ RXDFE_H6_CFG0 => X"2000",
+ RXDFE_H6_CFG1 => X"0000",
+ RXDFE_H7_CFG0 => X"2000",
+ RXDFE_H7_CFG1 => X"0000",
+ RXDFE_H8_CFG0 => X"2000",
+ RXDFE_H8_CFG1 => X"0000",
+ RXDFE_H9_CFG0 => X"2000",
+ RXDFE_H9_CFG1 => X"0000",
+ RXDFE_HA_CFG0 => X"2000",
+ RXDFE_HA_CFG1 => X"0000",
+ RXDFE_HB_CFG0 => X"2000",
+ RXDFE_HB_CFG1 => X"0000",
+ RXDFE_HC_CFG0 => X"0000",
+ RXDFE_HC_CFG1 => X"0000",
+ RXDFE_HD_CFG0 => X"0000",
+ RXDFE_HD_CFG1 => X"0000",
+ RXDFE_HE_CFG0 => X"0000",
+ RXDFE_HE_CFG1 => X"0000",
+ RXDFE_HF_CFG0 => X"0000",
+ RXDFE_HF_CFG1 => X"0000",
+ RXDFE_OS_CFG0 => X"8000",
+ RXDFE_OS_CFG1 => X"0000",
+ RXDFE_UT_CFG0 => X"8000",
+ RXDFE_UT_CFG1 => X"0003",
+ RXDFE_VP_CFG0 => X"AA00",
+ RXDFE_VP_CFG1 => X"0033",
+ RXDLY_CFG => X"001F",
+ RXDLY_LCFG => X"0030",
+ RXELECIDLE_CFG => "Sigcfg_4",
+ RXGBOX_FIFO_INIT_RD_ADDR => 4,
+ RXGEARBOX_EN => "FALSE",
+ RXISCANRESET_TIME => B"00001",
+ RXLPM_CFG => X"0000",
+ RXLPM_GC_CFG => X"1000",
+ RXLPM_KH_CFG0 => X"0000",
+ RXLPM_KH_CFG1 => X"0002",
+ RXLPM_OS_CFG0 => X"8000",
+ RXLPM_OS_CFG1 => X"0002",
+ RXOOB_CFG => B"000000110",
+ RXOOB_CLK_CFG => "PMA",
+ RXOSCALRESET_TIME => B"00011",
+ RXOUT_DIV => 1,
+ RXPCSRESET_TIME => B"00011",
+ RXPHBEACON_CFG => X"0000",
+ RXPHDLY_CFG => X"2020",
+ RXPHSAMP_CFG => X"2100",
+ RXPHSLIP_CFG => X"6622",
+ RXPH_MONITOR_SEL => B"00000",
+ RXPI_CFG0 => B"00",
+ RXPI_CFG1 => B"00",
+ RXPI_CFG2 => B"00",
+ RXPI_CFG3 => B"00",
+ RXPI_CFG4 => '1',
+ RXPI_CFG5 => '1',
+ RXPI_CFG6 => B"011",
+ RXPI_LPM => '0',
+ RXPI_VREFSEL => '0',
+ RXPMACLK_SEL => "DATA",
+ RXPMARESET_TIME => B"00011",
+ RXPRBS_ERR_LOOPBACK => '0',
+ RXPRBS_LINKACQ_CNT => 15,
+ RXSLIDE_AUTO_WAIT => 7,
+ RXSLIDE_MODE => "PMA",
+ RXSYNC_MULTILANE => '1',
+ RXSYNC_OVRD => '0',
+ RXSYNC_SKIP_DA => '0',
+ RX_AFE_CM_EN => '0',
+ RX_BIAS_CFG0 => X"0AB4",
+ RX_BUFFER_CFG => B"000000",
+ RX_CAPFF_SARC_ENB => '0',
+ RX_CLK25_DIV => 10,
+ RX_CLKMUX_EN => '1',
+ RX_CLK_SLIP_OVRD => B"00000",
+ RX_CM_BUF_CFG => B"1010",
+ RX_CM_BUF_PD => '0',
+ RX_CM_SEL => B"11",
+ RX_CM_TRIM => B"1010",
+ RX_CTLE3_LPF => B"00000001",
+ RX_DATA_WIDTH => 20,
+ RX_DDI_SEL => B"000000",
+ RX_DEFER_RESET_BUF_EN => "TRUE",
+ RX_DFELPM_CFG0 => B"0110",
+ RX_DFELPM_CFG1 => '1',
+ RX_DFELPM_KLKH_AGC_STUP_EN => '1',
+ RX_DFE_AGC_CFG0 => B"10",
+ RX_DFE_AGC_CFG1 => B"100",
+ RX_DFE_KL_LPM_KH_CFG0 => B"01",
+ RX_DFE_KL_LPM_KH_CFG1 => B"100",
+ RX_DFE_KL_LPM_KL_CFG0 => B"01",
+ RX_DFE_KL_LPM_KL_CFG1 => B"100",
+ RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
+ RX_DISPERR_SEQ_MATCH => "TRUE",
+ RX_DIVRESET_TIME => B"00001",
+ RX_EN_HI_LR => '0',
+ RX_EYESCAN_VS_CODE => B"0000000",
+ RX_EYESCAN_VS_NEG_DIR => '0',
+ RX_EYESCAN_VS_RANGE => B"00",
+ RX_EYESCAN_VS_UT_SIGN => '0',
+ RX_FABINT_USRCLK_FLOP => '0',
+ RX_INT_DATAWIDTH => 0,
+ RX_PMA_POWER_SAVE => '0',
+ RX_PROGDIV_CFG => 0.000000,
+ RX_SAMPLE_PERIOD => B"111",
+ RX_SIG_VALID_DLY => 11,
+ RX_SUM_DFETAPREP_EN => '0',
+ RX_SUM_IREF_TUNE => B"0000",
+ RX_SUM_RES_CTRL => B"00",
+ RX_SUM_VCMTUNE => B"0000",
+ RX_SUM_VCM_OVWR => '0',
+ RX_SUM_VREF_TUNE => B"000",
+ RX_TUNE_AFE_OS => B"10",
+ RX_WIDEMODE_CDR => '0',
+ RX_XCLK_SEL => "RXDES",
+ SAS_MAX_COM => 64,
+ SAS_MIN_COM => 36,
+ SATA_BURST_SEQ_LEN => B"1110",
+ SATA_BURST_VAL => B"100",
+ SATA_CPLL_CFG => "VCO_3000MHZ",
+ SATA_EIDLE_VAL => B"100",
+ SATA_MAX_BURST => 8,
+ SATA_MAX_INIT => 21,
+ SATA_MAX_WAKE => 7,
+ SATA_MIN_BURST => 4,
+ SATA_MIN_INIT => 12,
+ SATA_MIN_WAKE => 4,
+ SHOW_REALIGN_COMMA => "FALSE",
+ SIM_MODE => "FAST",
+ SIM_RECEIVER_DETECT_PASS => "TRUE",
+ SIM_RESET_SPEEDUP => "TRUE",
+ SIM_TX_EIDLE_DRIVE_LEVEL => '0',
+ SIM_VERSION => 2,
+ TAPDLY_SET_TX => B"00",
+ TEMPERATUR_PAR => B"0010",
+ TERM_RCAL_CFG => B"100001000010000",
+ TERM_RCAL_OVRD => B"000",
+ TRANS_TIME_RATE => X"0E",
+ TST_RSV0 => X"00",
+ TST_RSV1 => X"00",
+ TXBUF_EN => "FALSE",
+ TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ TXDLY_CFG => X"0009",
+ TXDLY_LCFG => X"0050",
+ TXDRVBIAS_N => B"1010",
+ TXDRVBIAS_P => B"1010",
+ TXFIFO_ADDR_CFG => "LOW",
+ TXGBOX_FIFO_INIT_RD_ADDR => 4,
+ TXGEARBOX_EN => "FALSE",
+ TXOUT_DIV => 2,
+ TXPCSRESET_TIME => B"00011",
+ TXPHDLY_CFG0 => X"2020",
+ TXPHDLY_CFG1 => X"0075",
+ TXPH_CFG => X"0980",
+ TXPH_MONITOR_SEL => B"00000",
+ TXPI_CFG0 => B"00",
+ TXPI_CFG1 => B"00",
+ TXPI_CFG2 => B"00",
+ TXPI_CFG3 => '1',
+ TXPI_CFG4 => '1',
+ TXPI_CFG5 => B"000",
+ TXPI_GRAY_SEL => '0',
+ TXPI_INVSTROBE_SEL => '1',
+ TXPI_LPM => '0',
+ TXPI_PPMCLK_SEL => "TXUSRCLK2",
+ TXPI_PPM_CFG => B"00000000",
+ TXPI_SYNFREQ_PPM => B"001",
+ TXPI_VREFSEL => '0',
+ TXPMARESET_TIME => B"00011",
+ TXSYNC_MULTILANE => '1',
+ TXSYNC_OVRD => '0',
+ TXSYNC_SKIP_DA => '0',
+ TX_CLK25_DIV => 10,
+ TX_CLKMUX_EN => '1',
+ TX_DATA_WIDTH => 20,
+ TX_DCD_CFG => B"000010",
+ TX_DCD_EN => '0',
+ TX_DEEMPH0 => B"000000",
+ TX_DEEMPH1 => B"000000",
+ TX_DIVRESET_TIME => B"00001",
+ TX_DRIVE_MODE => "DIRECT",
+ TX_EIDLE_ASSERT_DELAY => B"100",
+ TX_EIDLE_DEASSERT_DELAY => B"011",
+ TX_EML_PHI_TUNE => '0',
+ TX_FABINT_USRCLK_FLOP => '0',
+ TX_IDLE_DATA_ZERO => '0',
+ TX_INT_DATAWIDTH => 0,
+ TX_LOOPBACK_DRIVE_HIZ => "FALSE",
+ TX_MAINCURSOR_SEL => '0',
+ TX_MARGIN_FULL_0 => B"1001111",
+ TX_MARGIN_FULL_1 => B"1001110",
+ TX_MARGIN_FULL_2 => B"1001100",
+ TX_MARGIN_FULL_3 => B"1001010",
+ TX_MARGIN_FULL_4 => B"1001000",
+ TX_MARGIN_LOW_0 => B"1000110",
+ TX_MARGIN_LOW_1 => B"1000101",
+ TX_MARGIN_LOW_2 => B"1000011",
+ TX_MARGIN_LOW_3 => B"1000010",
+ TX_MARGIN_LOW_4 => B"1000000",
+ TX_MODE_SEL => B"000",
+ TX_PMADATA_OPT => '0',
+ TX_PMA_POWER_SAVE => '0',
+ TX_PROGCLK_SEL => "PREPI",
+ TX_PROGDIV_CFG => 0.000000,
+ TX_QPI_STATUS_EN => '0',
+ TX_RXDETECT_CFG => B"00" & X"032",
+ TX_RXDETECT_REF => B"100",
+ TX_SAMPLE_PERIOD => B"111",
+ TX_SARC_LPBK_ENB => '0',
+ TX_XCLK_SEL => "TXUSR",
+ USE_PCS_CLK_PHASE_SEL => '0',
+ WB_MODE => B"00"
+ )
+ port map (
+ BUFGTCE(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_289\,
+ BUFGTCE(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_290\,
+ BUFGTCE(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_291\,
+ BUFGTCEMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_292\,
+ BUFGTCEMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_293\,
+ BUFGTCEMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_294\,
+ BUFGTDIV(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_357\,
+ BUFGTDIV(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_358\,
+ BUFGTDIV(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_359\,
+ BUFGTDIV(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_360\,
+ BUFGTDIV(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_361\,
+ BUFGTDIV(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_362\,
+ BUFGTDIV(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_363\,
+ BUFGTDIV(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_364\,
+ BUFGTDIV(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_365\,
+ BUFGTRESET(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_295\,
+ BUFGTRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_296\,
+ BUFGTRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_297\,
+ BUFGTRSTMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_298\,
+ BUFGTRSTMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_299\,
+ BUFGTRSTMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_300\,
+ CFGRESET => '0',
+ CLKRSVD0 => '0',
+ CLKRSVD1 => '0',
+ CPLLFBCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_0\,
+ CPLLLOCK => cplllock_out(3),
+ CPLLLOCKDETCLK => '0',
+ CPLLLOCKEN => '1',
+ CPLLPD => GTHE3_CHANNEL_CPLLPD(0),
+ CPLLREFCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_2\,
+ CPLLREFCLKSEL(2 downto 0) => B"001",
+ CPLLRESET => '0',
+ DMONFIFORESET => '0',
+ DMONITORCLK => '0',
+ DMONITOROUT(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_258\,
+ DMONITOROUT(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_259\,
+ DMONITOROUT(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_260\,
+ DMONITOROUT(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_261\,
+ DMONITOROUT(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_262\,
+ DMONITOROUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_263\,
+ DMONITOROUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_264\,
+ DMONITOROUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_265\,
+ DMONITOROUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_266\,
+ DMONITOROUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_267\,
+ DMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_268\,
+ DMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_269\,
+ DMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_270\,
+ DMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_271\,
+ DMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_272\,
+ DMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_273\,
+ DMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_274\,
+ DRPADDR(8 downto 0) => B"000000000",
+ DRPCLK => drpclk_in(3),
+ DRPDI(15 downto 0) => B"0000000000000000",
+ DRPDO(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_210\,
+ DRPDO(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_211\,
+ DRPDO(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_212\,
+ DRPDO(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_213\,
+ DRPDO(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_214\,
+ DRPDO(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_215\,
+ DRPDO(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_216\,
+ DRPDO(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_217\,
+ DRPDO(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_218\,
+ DRPDO(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_219\,
+ DRPDO(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_220\,
+ DRPDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_221\,
+ DRPDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_222\,
+ DRPDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_223\,
+ DRPDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_224\,
+ DRPDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_225\,
+ DRPEN => '0',
+ DRPRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_3\,
+ DRPWE => '0',
+ EVODDPHICALDONE => '0',
+ EVODDPHICALSTART => '0',
+ EVODDPHIDRDEN => '0',
+ EVODDPHIDWREN => '0',
+ EVODDPHIXRDEN => '0',
+ EVODDPHIXWREN => '0',
+ EYESCANDATAERROR => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_4\,
+ EYESCANMODE => '0',
+ EYESCANRESET => '0',
+ EYESCANTRIGGER => '0',
+ GTGREFCLK => '0',
+ GTHRXN => gthrxn_in(3),
+ GTHRXP => gthrxp_in(3),
+ GTHTXN => gthtxn_out(3),
+ GTHTXP => gthtxp_out(3),
+ GTNORTHREFCLK0 => '0',
+ GTNORTHREFCLK1 => '0',
+ GTPOWERGOOD => gtpowergood_out(3),
+ GTREFCLK0 => gtrefclk0_in(3),
+ GTREFCLK1 => '0',
+ GTREFCLKMONITOR => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_8\,
+ GTRESETSEL => '0',
+ GTRSVD(15 downto 0) => B"0000000000000000",
+ GTRXRESET => GTHE3_CHANNEL_GTRXRESET(0),
+ GTSOUTHREFCLK0 => '0',
+ GTSOUTHREFCLK1 => '0',
+ GTTXRESET => GTHE3_CHANNEL_GTTXRESET(0),
+ LOOPBACK(2 downto 0) => loopback_in(11 downto 9),
+ LPBKRXTXSEREN => '0',
+ LPBKTXRXSEREN => '0',
+ PCIEEQRXEQADAPTDONE => '0',
+ PCIERATEGEN3 => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_9\,
+ PCIERATEIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_10\,
+ PCIERATEQPLLPD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_275\,
+ PCIERATEQPLLPD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_276\,
+ PCIERATEQPLLRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_277\,
+ PCIERATEQPLLRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_278\,
+ PCIERSTIDLE => '0',
+ PCIERSTTXSYNCSTART => '0',
+ PCIESYNCTXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_11\,
+ PCIEUSERGEN3RDY => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_12\,
+ PCIEUSERPHYSTATUSRST => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_13\,
+ PCIEUSERRATEDONE => '0',
+ PCIEUSERRATESTART => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_14\,
+ PCSRSVDIN(15 downto 0) => B"0000000000000000",
+ PCSRSVDIN2(4 downto 0) => B"00000",
+ PCSRSVDOUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_70\,
+ PCSRSVDOUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_71\,
+ PCSRSVDOUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_72\,
+ PCSRSVDOUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_73\,
+ PCSRSVDOUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_74\,
+ PCSRSVDOUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_75\,
+ PCSRSVDOUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_76\,
+ PCSRSVDOUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_77\,
+ PCSRSVDOUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_78\,
+ PCSRSVDOUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_79\,
+ PCSRSVDOUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_80\,
+ PCSRSVDOUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_81\,
+ PHYSTATUS => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_15\,
+ PINRSRVDAS(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_325\,
+ PINRSRVDAS(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_326\,
+ PINRSRVDAS(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_327\,
+ PINRSRVDAS(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_328\,
+ PINRSRVDAS(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_329\,
+ PINRSRVDAS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_330\,
+ PINRSRVDAS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_331\,
+ PINRSRVDAS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_332\,
+ PMARSVDIN(4 downto 0) => B"00000",
+ QPLL0CLK => qpll0outclk_out(0),
+ QPLL0REFCLK => qpll0outrefclk_out(0),
+ QPLL1CLK => qpll1outclk_out(0),
+ QPLL1REFCLK => qpll1outrefclk_out(0),
+ RESETEXCEPTION => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_16\,
+ RESETOVRD => '0',
+ RSTCLKENTX => '0',
+ RX8B10BEN => '0',
+ RXBUFRESET => '0',
+ RXBUFSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_301\,
+ RXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_302\,
+ RXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_303\,
+ RXBYTEISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_17\,
+ RXBYTEREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_18\,
+ RXCDRFREQRESET => '0',
+ RXCDRHOLD => rxcdrhold_in(3),
+ RXCDRLOCK => rxcdrlock_out(3),
+ RXCDROVRDEN => '0',
+ RXCDRPHDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_20\,
+ RXCDRRESET => '0',
+ RXCDRRESETRSV => '0',
+ RXCHANBONDSEQ => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_21\,
+ RXCHANISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_22\,
+ RXCHANREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_23\,
+ RXCHBONDEN => '0',
+ RXCHBONDI(4 downto 0) => B"00000",
+ RXCHBONDLEVEL(2 downto 0) => B"000",
+ RXCHBONDMASTER => '0',
+ RXCHBONDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_307\,
+ RXCHBONDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_308\,
+ RXCHBONDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_309\,
+ RXCHBONDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_310\,
+ RXCHBONDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_311\,
+ RXCHBONDSLAVE => '0',
+ RXCLKCORCNT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_279\,
+ RXCLKCORCNT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_280\,
+ RXCOMINITDET => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_24\,
+ RXCOMMADET => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_25\,
+ RXCOMMADETEN => '1',
+ RXCOMSASDET => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_26\,
+ RXCOMWAKEDET => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_27\,
+ RXCTRL0(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_226\,
+ RXCTRL0(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_227\,
+ RXCTRL0(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_228\,
+ RXCTRL0(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_229\,
+ RXCTRL0(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_230\,
+ RXCTRL0(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_231\,
+ RXCTRL0(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_232\,
+ RXCTRL0(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_233\,
+ RXCTRL0(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_234\,
+ RXCTRL0(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_235\,
+ RXCTRL0(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_236\,
+ RXCTRL0(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_237\,
+ RXCTRL0(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_238\,
+ RXCTRL0(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_239\,
+ RXCTRL0(1) => gtwiz_userdata_rx_out(78),
+ RXCTRL0(0) => gtwiz_userdata_rx_out(68),
+ RXCTRL1(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_242\,
+ RXCTRL1(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_243\,
+ RXCTRL1(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_244\,
+ RXCTRL1(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_245\,
+ RXCTRL1(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_246\,
+ RXCTRL1(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_247\,
+ RXCTRL1(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_248\,
+ RXCTRL1(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_249\,
+ RXCTRL1(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_250\,
+ RXCTRL1(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_251\,
+ RXCTRL1(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_252\,
+ RXCTRL1(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_253\,
+ RXCTRL1(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_254\,
+ RXCTRL1(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_255\,
+ RXCTRL1(1) => gtwiz_userdata_rx_out(79),
+ RXCTRL1(0) => gtwiz_userdata_rx_out(69),
+ RXCTRL2(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_333\,
+ RXCTRL2(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_334\,
+ RXCTRL2(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_335\,
+ RXCTRL2(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_336\,
+ RXCTRL2(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_337\,
+ RXCTRL2(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_338\,
+ RXCTRL2(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_339\,
+ RXCTRL2(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_340\,
+ RXCTRL3(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_341\,
+ RXCTRL3(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_342\,
+ RXCTRL3(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_343\,
+ RXCTRL3(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_344\,
+ RXCTRL3(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_345\,
+ RXCTRL3(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_346\,
+ RXCTRL3(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_347\,
+ RXCTRL3(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_348\,
+ RXDATA(127) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_82\,
+ RXDATA(126) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_83\,
+ RXDATA(125) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_84\,
+ RXDATA(124) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_85\,
+ RXDATA(123) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_86\,
+ RXDATA(122) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_87\,
+ RXDATA(121) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_88\,
+ RXDATA(120) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_89\,
+ RXDATA(119) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_90\,
+ RXDATA(118) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_91\,
+ RXDATA(117) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_92\,
+ RXDATA(116) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_93\,
+ RXDATA(115) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_94\,
+ RXDATA(114) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_95\,
+ RXDATA(113) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_96\,
+ RXDATA(112) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_97\,
+ RXDATA(111) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_98\,
+ RXDATA(110) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_99\,
+ RXDATA(109) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_100\,
+ RXDATA(108) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_101\,
+ RXDATA(107) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_102\,
+ RXDATA(106) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_103\,
+ RXDATA(105) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_104\,
+ RXDATA(104) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_105\,
+ RXDATA(103) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_106\,
+ RXDATA(102) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_107\,
+ RXDATA(101) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_108\,
+ RXDATA(100) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_109\,
+ RXDATA(99) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_110\,
+ RXDATA(98) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_111\,
+ RXDATA(97) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_112\,
+ RXDATA(96) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_113\,
+ RXDATA(95) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_114\,
+ RXDATA(94) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_115\,
+ RXDATA(93) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_116\,
+ RXDATA(92) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_117\,
+ RXDATA(91) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_118\,
+ RXDATA(90) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_119\,
+ RXDATA(89) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_120\,
+ RXDATA(88) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_121\,
+ RXDATA(87) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_122\,
+ RXDATA(86) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_123\,
+ RXDATA(85) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_124\,
+ RXDATA(84) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_125\,
+ RXDATA(83) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_126\,
+ RXDATA(82) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_127\,
+ RXDATA(81) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_128\,
+ RXDATA(80) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_129\,
+ RXDATA(79) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_130\,
+ RXDATA(78) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_131\,
+ RXDATA(77) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_132\,
+ RXDATA(76) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_133\,
+ RXDATA(75) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_134\,
+ RXDATA(74) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_135\,
+ RXDATA(73) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_136\,
+ RXDATA(72) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_137\,
+ RXDATA(71) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_138\,
+ RXDATA(70) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_139\,
+ RXDATA(69) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_140\,
+ RXDATA(68) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_141\,
+ RXDATA(67) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_142\,
+ RXDATA(66) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_143\,
+ RXDATA(65) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_144\,
+ RXDATA(64) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_145\,
+ RXDATA(63) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_146\,
+ RXDATA(62) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_147\,
+ RXDATA(61) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_148\,
+ RXDATA(60) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_149\,
+ RXDATA(59) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_150\,
+ RXDATA(58) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_151\,
+ RXDATA(57) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_152\,
+ RXDATA(56) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_153\,
+ RXDATA(55) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_154\,
+ RXDATA(54) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_155\,
+ RXDATA(53) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_156\,
+ RXDATA(52) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_157\,
+ RXDATA(51) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_158\,
+ RXDATA(50) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_159\,
+ RXDATA(49) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_160\,
+ RXDATA(48) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_161\,
+ RXDATA(47) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_162\,
+ RXDATA(46) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_163\,
+ RXDATA(45) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_164\,
+ RXDATA(44) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_165\,
+ RXDATA(43) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_166\,
+ RXDATA(42) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_167\,
+ RXDATA(41) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_168\,
+ RXDATA(40) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_169\,
+ RXDATA(39) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_170\,
+ RXDATA(38) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_171\,
+ RXDATA(37) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_172\,
+ RXDATA(36) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_173\,
+ RXDATA(35) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_174\,
+ RXDATA(34) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_175\,
+ RXDATA(33) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_176\,
+ RXDATA(32) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_177\,
+ RXDATA(31) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_178\,
+ RXDATA(30) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_179\,
+ RXDATA(29) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_180\,
+ RXDATA(28) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_181\,
+ RXDATA(27) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_182\,
+ RXDATA(26) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_183\,
+ RXDATA(25) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_184\,
+ RXDATA(24) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_185\,
+ RXDATA(23) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_186\,
+ RXDATA(22) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_187\,
+ RXDATA(21) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_188\,
+ RXDATA(20) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_189\,
+ RXDATA(19) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_190\,
+ RXDATA(18) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_191\,
+ RXDATA(17) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_192\,
+ RXDATA(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_193\,
+ RXDATA(15 downto 8) => gtwiz_userdata_rx_out(77 downto 70),
+ RXDATA(7 downto 0) => gtwiz_userdata_rx_out(67 downto 60),
+ RXDATAEXTENDRSVD(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_349\,
+ RXDATAEXTENDRSVD(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_350\,
+ RXDATAEXTENDRSVD(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_351\,
+ RXDATAEXTENDRSVD(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_352\,
+ RXDATAEXTENDRSVD(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_353\,
+ RXDATAEXTENDRSVD(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_354\,
+ RXDATAEXTENDRSVD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_355\,
+ RXDATAEXTENDRSVD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_356\,
+ RXDATAVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_281\,
+ RXDATAVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_282\,
+ RXDFEAGCCTRL(1 downto 0) => B"01",
+ RXDFEAGCHOLD => '0',
+ RXDFEAGCOVRDEN => '0',
+ RXDFELFHOLD => '0',
+ RXDFELFOVRDEN => '0',
+ RXDFELPMRESET => '0',
+ RXDFETAP10HOLD => '0',
+ RXDFETAP10OVRDEN => '0',
+ RXDFETAP11HOLD => '0',
+ RXDFETAP11OVRDEN => '0',
+ RXDFETAP12HOLD => '0',
+ RXDFETAP12OVRDEN => '0',
+ RXDFETAP13HOLD => '0',
+ RXDFETAP13OVRDEN => '0',
+ RXDFETAP14HOLD => '0',
+ RXDFETAP14OVRDEN => '0',
+ RXDFETAP15HOLD => '0',
+ RXDFETAP15OVRDEN => '0',
+ RXDFETAP2HOLD => '0',
+ RXDFETAP2OVRDEN => '0',
+ RXDFETAP3HOLD => '0',
+ RXDFETAP3OVRDEN => '0',
+ RXDFETAP4HOLD => '0',
+ RXDFETAP4OVRDEN => '0',
+ RXDFETAP5HOLD => '0',
+ RXDFETAP5OVRDEN => '0',
+ RXDFETAP6HOLD => '0',
+ RXDFETAP6OVRDEN => '0',
+ RXDFETAP7HOLD => '0',
+ RXDFETAP7OVRDEN => '0',
+ RXDFETAP8HOLD => '0',
+ RXDFETAP8OVRDEN => '0',
+ RXDFETAP9HOLD => '0',
+ RXDFETAP9OVRDEN => '0',
+ RXDFEUTHOLD => '0',
+ RXDFEUTOVRDEN => '0',
+ RXDFEVPHOLD => '0',
+ RXDFEVPOVRDEN => '0',
+ RXDFEVSEN => '0',
+ RXDFEXYDEN => '1',
+ RXDLYBYPASS => '1',
+ RXDLYEN => '0',
+ RXDLYOVRDEN => '0',
+ RXDLYSRESET => '0',
+ RXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_28\,
+ RXELECIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_29\,
+ RXELECIDLEMODE(1 downto 0) => B"11",
+ RXGEARBOXSLIP => '0',
+ RXHEADER(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_312\,
+ RXHEADER(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_313\,
+ RXHEADER(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_314\,
+ RXHEADER(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_315\,
+ RXHEADER(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_316\,
+ RXHEADER(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_317\,
+ RXHEADERVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_283\,
+ RXHEADERVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_284\,
+ RXLATCLK => '0',
+ RXLPMEN => '0',
+ RXLPMGCHOLD => '0',
+ RXLPMGCOVRDEN => '0',
+ RXLPMHFHOLD => '0',
+ RXLPMHFOVRDEN => '0',
+ RXLPMLFHOLD => '0',
+ RXLPMLFKLOVRDEN => '0',
+ RXLPMOSHOLD => '0',
+ RXLPMOSOVRDEN => '0',
+ RXMCOMMAALIGNEN => '0',
+ RXMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_318\,
+ RXMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_319\,
+ RXMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_320\,
+ RXMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_321\,
+ RXMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_322\,
+ RXMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_323\,
+ RXMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_324\,
+ RXMONITORSEL(1 downto 0) => B"00",
+ RXOOBRESET => '0',
+ RXOSCALRESET => '0',
+ RXOSHOLD => '0',
+ RXOSINTCFG(3 downto 0) => B"1101",
+ RXOSINTDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_30\,
+ RXOSINTEN => '1',
+ RXOSINTHOLD => '0',
+ RXOSINTOVRDEN => '0',
+ RXOSINTSTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_31\,
+ RXOSINTSTROBE => '0',
+ RXOSINTSTROBEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_32\,
+ RXOSINTSTROBESTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_33\,
+ RXOSINTTESTOVRDEN => '0',
+ RXOSOVRDEN => '0',
+ RXOUTCLK => rxoutclk_out(3),
+ RXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_35\,
+ RXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_36\,
+ RXOUTCLKSEL(2 downto 0) => B"010",
+ RXPCOMMAALIGNEN => '0',
+ RXPCSRESET => '0',
+ RXPD(1 downto 0) => B"00",
+ RXPHALIGN => '0',
+ RXPHALIGNDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_37\,
+ RXPHALIGNEN => '0',
+ RXPHALIGNERR => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_38\,
+ RXPHDLYPD => '0',
+ RXPHDLYRESET => '0',
+ RXPHOVRDEN => '0',
+ RXPLLCLKSEL(1 downto 0) => B"00",
+ RXPMARESET => '0',
+ RXPMARESETDONE => rxpmaresetdone_out(3),
+ RXPOLARITY => rxpolarity_in(3),
+ RXPRBSCNTRESET => '0',
+ RXPRBSERR => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_40\,
+ RXPRBSLOCKED => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_41\,
+ RXPRBSSEL(3 downto 0) => B"0000",
+ RXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_42\,
+ RXPROGDIVRESET => GTHE3_CHANNEL_RXPROGDIVRESET(0),
+ RXQPIEN => '0',
+ RXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_43\,
+ RXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_44\,
+ RXRATE(2 downto 0) => B"000",
+ RXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_45\,
+ RXRATEMODE => '0',
+ RXRECCLKOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_46\,
+ RXRESETDONE => rxresetdone_out(3),
+ RXSLIDE => rxslide_in(3),
+ RXSLIDERDY => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_48\,
+ RXSLIPDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_49\,
+ RXSLIPOUTCLK => '0',
+ RXSLIPOUTCLKRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_50\,
+ RXSLIPPMA => '0',
+ RXSLIPPMARDY => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_51\,
+ RXSTARTOFSEQ(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_285\,
+ RXSTARTOFSEQ(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_286\,
+ RXSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_304\,
+ RXSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_305\,
+ RXSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_306\,
+ RXSYNCALLIN => '0',
+ RXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_52\,
+ RXSYNCIN => '0',
+ RXSYNCMODE => '0',
+ RXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_53\,
+ RXSYSCLKSEL(1 downto 0) => B"00",
+ RXUSERRDY => GTHE3_CHANNEL_RXUSERRDY(0),
+ RXUSRCLK => rxusrclk_in(3),
+ RXUSRCLK2 => rxusrclk2_in(3),
+ RXVALID => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_54\,
+ SIGVALIDCLK => '0',
+ TSTIN(19 downto 0) => B"00000000000000000000",
+ TX8B10BBYPASS(7 downto 0) => B"00000000",
+ TX8B10BEN => '0',
+ TXBUFDIFFCTRL(2 downto 0) => B"000",
+ TXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_287\,
+ TXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_288\,
+ TXCOMFINISH => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_55\,
+ TXCOMINIT => '0',
+ TXCOMSAS => '0',
+ TXCOMWAKE => '0',
+ TXCTRL0(15 downto 2) => B"00000000000000",
+ TXCTRL0(1) => gtwiz_userdata_tx_in(78),
+ TXCTRL0(0) => gtwiz_userdata_tx_in(68),
+ TXCTRL1(15 downto 2) => B"00000000000000",
+ TXCTRL1(1) => gtwiz_userdata_tx_in(79),
+ TXCTRL1(0) => gtwiz_userdata_tx_in(69),
+ TXCTRL2(7 downto 0) => B"00000000",
+ TXDATA(127 downto 16) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ TXDATA(15 downto 8) => gtwiz_userdata_tx_in(77 downto 70),
+ TXDATA(7 downto 0) => gtwiz_userdata_tx_in(67 downto 60),
+ TXDATAEXTENDRSVD(7 downto 0) => B"00000000",
+ TXDEEMPH => '0',
+ TXDETECTRX => '0',
+ TXDIFFCTRL(3 downto 0) => B"1100",
+ TXDIFFPD => '0',
+ TXDLYBYPASS => '0',
+ TXDLYEN => '0',
+ TXDLYHOLD => '0',
+ TXDLYOVRDEN => '0',
+ TXDLYSRESET => GTHE3_CHANNEL_TXDLYSRESET(0),
+ TXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_56\,
+ TXDLYUPDOWN => '0',
+ TXELECIDLE => '0',
+ TXHEADER(5 downto 0) => B"000000",
+ TXINHIBIT => '0',
+ TXLATCLK => '0',
+ TXMAINCURSOR(6 downto 0) => B"1000000",
+ TXMARGIN(2 downto 0) => B"000",
+ TXOUTCLK => txoutclk_out(3),
+ TXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_58\,
+ TXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_59\,
+ TXOUTCLKSEL(2 downto 0) => B"011",
+ TXPCSRESET => '0',
+ TXPD(1 downto 0) => B"00",
+ TXPDELECIDLEMODE => '0',
+ TXPHALIGN => '0',
+ TXPHALIGNDONE => GTHE3_CHANNEL_TXPHALIGNDONE(3),
+ TXPHALIGNEN => '0',
+ TXPHDLYPD => '0',
+ TXPHDLYRESET => '0',
+ TXPHDLYTSTCLK => '0',
+ TXPHINIT => '0',
+ TXPHINITDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_61\,
+ TXPHOVRDEN => '0',
+ TXPIPPMEN => '0',
+ TXPIPPMOVRDEN => '0',
+ TXPIPPMPD => '0',
+ TXPIPPMSEL => '0',
+ TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
+ TXPISOPD => '0',
+ TXPLLCLKSEL(1 downto 0) => B"10",
+ TXPMARESET => '0',
+ TXPMARESETDONE => txpmaresetdone_out(3),
+ TXPOLARITY => txpolarity_in(3),
+ TXPOSTCURSOR(4 downto 0) => B"00000",
+ TXPOSTCURSORINV => '0',
+ TXPRBSFORCEERR => '0',
+ TXPRBSSEL(3 downto 0) => B"0000",
+ TXPRECURSOR(4 downto 0) => B"00000",
+ TXPRECURSORINV => '0',
+ TXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_63\,
+ TXPROGDIVRESET => GTHE3_CHANNEL_TXPROGDIVRESET(0),
+ TXQPIBIASEN => '0',
+ TXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_64\,
+ TXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_65\,
+ TXQPISTRONGPDOWN => '0',
+ TXQPIWEAKPUP => '0',
+ TXRATE(2 downto 0) => B"000",
+ TXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_66\,
+ TXRATEMODE => '0',
+ TXRESETDONE => txresetdone_out(3),
+ TXSEQUENCE(6 downto 0) => B"0000000",
+ TXSWING => '0',
+ TXSYNCALLIN => GTHE3_CHANNEL_TXSYNCALLIN(0),
+ TXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_68\,
+ TXSYNCIN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYNCMODE => '0',
+ TXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYSCLKSEL(1 downto 0) => B"11",
+ TXUSERRDY => GTHE3_CHANNEL_TXUSERRDY(0),
+ TXUSRCLK => txusrclk_in(3),
+ TXUSRCLK2 => txusrclk2_in(3)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gthe3_common is
+ port (
+ qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in0 : out STD_LOGIC;
+ gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_0\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gthe3_common : entity is "gtwizard_ultrascale_v1_7_18_gthe3_common";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gthe3_common;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gthe3_common is
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_0\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_10\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_11\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_12\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_13\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_14\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_15\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_16\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_17\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_18\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_19\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_20\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_21\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_22\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_23\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_24\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_25\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_26\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_27\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_28\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_29\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_30\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_31\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_32\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_33\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_34\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_35\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_36\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_37\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_38\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_39\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_40\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_41\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_42\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_43\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_44\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_45\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_46\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_47\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_48\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_49\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_5\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_50\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_51\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_52\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_53\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_54\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_55\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_56\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_57\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_58\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_59\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_60\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_61\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_62\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_63\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_64\ : STD_LOGIC;
+ signal \^qpll1lock_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ attribute BOX_TYPE : string;
+ attribute BOX_TYPE of \gthe3_common_gen.GTHE3_COMMON_PRIM_INST\ : label is "PRIMITIVE";
+begin
+ qpll1lock_out(0) <= \^qpll1lock_out\(0);
+\gthe3_common_gen.GTHE3_COMMON_PRIM_INST\: unisim.vcomponents.GTHE3_COMMON
+ generic map(
+ BIAS_CFG0 => X"0000",
+ BIAS_CFG1 => X"0000",
+ BIAS_CFG2 => X"0000",
+ BIAS_CFG3 => X"0040",
+ BIAS_CFG4 => X"0000",
+ BIAS_CFG_RSVD => B"0000000000",
+ COMMON_CFG0 => X"0000",
+ COMMON_CFG1 => X"0000",
+ POR_CFG => X"0004",
+ QPLL0_CFG0 => X"321C",
+ QPLL0_CFG1 => X"1018",
+ QPLL0_CFG1_G3 => X"1018",
+ QPLL0_CFG2 => X"0048",
+ QPLL0_CFG2_G3 => X"0048",
+ QPLL0_CFG3 => X"0120",
+ QPLL0_CFG4 => X"0009",
+ QPLL0_CP => B"0000011111",
+ QPLL0_CP_G3 => B"1111111111",
+ QPLL0_FBDIV => 66,
+ QPLL0_FBDIV_G3 => 80,
+ QPLL0_INIT_CFG0 => X"02B2",
+ QPLL0_INIT_CFG1 => X"00",
+ QPLL0_LOCK_CFG => X"21E8",
+ QPLL0_LOCK_CFG_G3 => X"21E8",
+ QPLL0_LPF => B"1111111100",
+ QPLL0_LPF_G3 => B"0000010101",
+ QPLL0_REFCLK_DIV => 1,
+ QPLL0_SDM_CFG0 => B"0000000000000000",
+ QPLL0_SDM_CFG1 => B"0000000000000000",
+ QPLL0_SDM_CFG2 => B"0000000000000000",
+ QPLL1_CFG0 => X"321C",
+ QPLL1_CFG1 => X"1018",
+ QPLL1_CFG1_G3 => X"1018",
+ QPLL1_CFG2 => X"0040",
+ QPLL1_CFG2_G3 => X"0040",
+ QPLL1_CFG3 => X"0120",
+ QPLL1_CFG4 => X"0000",
+ QPLL1_CP => B"0000011111",
+ QPLL1_CP_G3 => B"1111111111",
+ QPLL1_FBDIV => 40,
+ QPLL1_FBDIV_G3 => 80,
+ QPLL1_INIT_CFG0 => X"02B2",
+ QPLL1_INIT_CFG1 => X"00",
+ QPLL1_LOCK_CFG => X"21E8",
+ QPLL1_LOCK_CFG_G3 => X"21E8",
+ QPLL1_LPF => B"1111111110",
+ QPLL1_LPF_G3 => B"0000010101",
+ QPLL1_REFCLK_DIV => 1,
+ QPLL1_SDM_CFG0 => B"0000000000000000",
+ QPLL1_SDM_CFG1 => B"0000000000000000",
+ QPLL1_SDM_CFG2 => B"0000000000000000",
+ RSVD_ATTR0 => X"0000",
+ RSVD_ATTR1 => X"0000",
+ RSVD_ATTR2 => X"0000",
+ RSVD_ATTR3 => X"0000",
+ RXRECCLKOUT0_SEL => B"00",
+ RXRECCLKOUT1_SEL => B"00",
+ SARC_EN => '1',
+ SARC_SEL => '0',
+ SDM0DATA1_0 => B"0000000000000000",
+ SDM0DATA1_1 => B"000000000",
+ SDM0INITSEED0_0 => B"0000000000000000",
+ SDM0INITSEED0_1 => B"000000000",
+ SDM0_DATA_PIN_SEL => '0',
+ SDM0_WIDTH_PIN_SEL => '0',
+ SDM1DATA1_0 => B"0000000000000000",
+ SDM1DATA1_1 => B"000000000",
+ SDM1INITSEED0_0 => B"0000000000000000",
+ SDM1INITSEED0_1 => B"000000000",
+ SDM1_DATA_PIN_SEL => '0',
+ SDM1_WIDTH_PIN_SEL => '0',
+ SIM_MODE => "FAST",
+ SIM_RESET_SPEEDUP => "TRUE",
+ SIM_VERSION => 2
+ )
+ port map (
+ BGBYPASSB => '1',
+ BGMONITORENB => '1',
+ BGPDB => '1',
+ BGRCALOVRD(4 downto 0) => B"11111",
+ BGRCALOVRDENB => '1',
+ DRPADDR(8 downto 0) => B"000000000",
+ DRPCLK => '0',
+ DRPDI(15 downto 0) => B"0000000000000000",
+ DRPDO(15) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_13\,
+ DRPDO(14) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_14\,
+ DRPDO(13) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_15\,
+ DRPDO(12) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_16\,
+ DRPDO(11) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_17\,
+ DRPDO(10) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_18\,
+ DRPDO(9) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_19\,
+ DRPDO(8) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_20\,
+ DRPDO(7) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_21\,
+ DRPDO(6) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_22\,
+ DRPDO(5) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_23\,
+ DRPDO(4) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_24\,
+ DRPDO(3) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_25\,
+ DRPDO(2) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_26\,
+ DRPDO(1) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_27\,
+ DRPDO(0) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_28\,
+ DRPEN => '0',
+ DRPRDY => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_0\,
+ DRPWE => '0',
+ GTGREFCLK0 => '0',
+ GTGREFCLK1 => '0',
+ GTNORTHREFCLK00 => '0',
+ GTNORTHREFCLK01 => '0',
+ GTNORTHREFCLK10 => '0',
+ GTNORTHREFCLK11 => '0',
+ GTREFCLK00 => '0',
+ GTREFCLK01 => gtrefclk01_in(0),
+ GTREFCLK10 => '0',
+ GTREFCLK11 => '0',
+ GTSOUTHREFCLK00 => '0',
+ GTSOUTHREFCLK01 => '0',
+ GTSOUTHREFCLK10 => '0',
+ GTSOUTHREFCLK11 => '0',
+ PMARSVD0(7 downto 0) => B"00000000",
+ PMARSVD1(7 downto 0) => B"00000000",
+ PMARSVDOUT0(7) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_33\,
+ PMARSVDOUT0(6) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_34\,
+ PMARSVDOUT0(5) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_35\,
+ PMARSVDOUT0(4) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_36\,
+ PMARSVDOUT0(3) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_37\,
+ PMARSVDOUT0(2) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_38\,
+ PMARSVDOUT0(1) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_39\,
+ PMARSVDOUT0(0) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_40\,
+ PMARSVDOUT1(7) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_41\,
+ PMARSVDOUT1(6) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_42\,
+ PMARSVDOUT1(5) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_43\,
+ PMARSVDOUT1(4) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_44\,
+ PMARSVDOUT1(3) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_45\,
+ PMARSVDOUT1(2) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_46\,
+ PMARSVDOUT1(1) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_47\,
+ PMARSVDOUT1(0) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_48\,
+ QPLL0CLKRSVD0 => '0',
+ QPLL0CLKRSVD1 => '0',
+ QPLL0FBCLKLOST => qpll0fbclklost_out(0),
+ QPLL0LOCK => qpll0lock_out(0),
+ QPLL0LOCKDETCLK => '0',
+ QPLL0LOCKEN => '0',
+ QPLL0OUTCLK => qpll0outclk_out(0),
+ QPLL0OUTREFCLK => qpll0outrefclk_out(0),
+ QPLL0PD => '1',
+ QPLL0REFCLKLOST => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_5\,
+ QPLL0REFCLKSEL(2 downto 0) => B"001",
+ QPLL0RESET => '1',
+ QPLL1CLKRSVD0 => '0',
+ QPLL1CLKRSVD1 => '0',
+ QPLL1FBCLKLOST => qpll1fbclklost_out(0),
+ QPLL1LOCK => \^qpll1lock_out\(0),
+ QPLL1LOCKDETCLK => '0',
+ QPLL1LOCKEN => '1',
+ QPLL1OUTCLK => qpll1outclk_out(0),
+ QPLL1OUTREFCLK => qpll1outrefclk_out(0),
+ QPLL1PD => '0',
+ QPLL1REFCLKLOST => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_10\,
+ QPLL1REFCLKSEL(2 downto 0) => B"001",
+ QPLL1RESET => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_0\,
+ QPLLDMONITOR0(7) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_49\,
+ QPLLDMONITOR0(6) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_50\,
+ QPLLDMONITOR0(5) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_51\,
+ QPLLDMONITOR0(4) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_52\,
+ QPLLDMONITOR0(3) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_53\,
+ QPLLDMONITOR0(2) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_54\,
+ QPLLDMONITOR0(1) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_55\,
+ QPLLDMONITOR0(0) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_56\,
+ QPLLDMONITOR1(7) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_57\,
+ QPLLDMONITOR1(6) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_58\,
+ QPLLDMONITOR1(5) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_59\,
+ QPLLDMONITOR1(4) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_60\,
+ QPLLDMONITOR1(3) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_61\,
+ QPLLDMONITOR1(2) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_62\,
+ QPLLDMONITOR1(1) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_63\,
+ QPLLDMONITOR1(0) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_64\,
+ QPLLRSVD1(7 downto 0) => B"00000000",
+ QPLLRSVD2(4 downto 0) => B"00000",
+ QPLLRSVD3(4 downto 0) => B"00000",
+ QPLLRSVD4(7 downto 0) => B"00000000",
+ RCALENB => '1',
+ REFCLKOUTMONITOR0 => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_11\,
+ REFCLKOUTMONITOR1 => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_12\,
+ RXRECCLK0_SEL(1) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_29\,
+ RXRECCLK0_SEL(0) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_30\,
+ RXRECCLK1_SEL(1) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_31\,
+ RXRECCLK1_SEL(0) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_32\
+ );
+\rst_in_meta_i_1__3\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^qpll1lock_out\(0),
+ O => rst_in0
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer is
+ port (
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\ : out STD_LOGIC;
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[0]\ : out STD_LOGIC;
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_sync2_reg_0 : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\ : in STD_LOGIC;
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\ : in STD_LOGIC;
+ gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer : entity is "gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer is
+ signal \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\ : STD_LOGIC;
+ signal p_0_in : STD_LOGIC;
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx[1]_i_3\ : label is "soft_lutpair21";
+ attribute SOFT_HLUTNM of \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_done_out_i_1\ : label is "soft_lutpair21";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\ <= \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\;
+\FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AEFEAEAE"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => p_0_in,
+ I2 => Q(1),
+ I3 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\,
+ I4 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\,
+ O => E(0)
+ );
+\FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx[1]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"F4"
+ )
+ port map (
+ I0 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\,
+ I1 => \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\,
+ I2 => gtwiz_buffbypass_tx_start_user_in(0),
+ O => p_0_in
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_done_out_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AAAA4454"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => gtwiz_buffbypass_tx_start_user_in(0),
+ I2 => \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\,
+ I3 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\,
+ I4 => Q(1),
+ O => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[0]\
+ );
+rst_in_meta_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => rst_in_sync2_reg_0,
+ D => '1',
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => rst_in_sync2_reg_0,
+ D => rst_in_sync3,
+ Q => \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => rst_in_sync2_reg_0,
+ D => rst_in_meta,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => rst_in_sync2_reg_0,
+ D => rst_in_sync1,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => rst_in_sync2_reg_0,
+ D => rst_in_sync2,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_25 is
+ port (
+ gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_sync2_reg_0 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_25 : entity is "gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_25;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_25 is
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal \rst_in_out_i_1__1_n_0\ : STD_LOGIC;
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+rst_in_meta_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => rxusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__1_n_0\,
+ D => '1',
+ Q => rst_in_meta
+ );
+\rst_in_out_i_1__1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => rst_in_sync2_reg_0,
+ O => \rst_in_out_i_1__1_n_0\
+ );
+rst_in_out_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => rxusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__1_n_0\,
+ D => rst_in_sync3,
+ Q => gtwiz_reset_rx_done_out(0)
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => rxusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__1_n_0\,
+ D => rst_in_meta,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => rxusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__1_n_0\,
+ D => rst_in_sync1,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => rxusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__1_n_0\,
+ D => rst_in_sync2,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_26 is
+ port (
+ gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_out_reg_0 : out STD_LOGIC;
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_sync3_reg_0 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_26 : entity is "gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_26;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_26 is
+ signal \^gtwiz_reset_tx_done_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal \rst_in_out_i_1__0_n_0\ : STD_LOGIC;
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+ gtwiz_reset_tx_done_out(0) <= \^gtwiz_reset_tx_done_out\(0);
+\rst_in_meta_i_1__4\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^gtwiz_reset_tx_done_out\(0),
+ O => rst_in_out_reg_0
+ );
+rst_in_meta_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__0_n_0\,
+ D => '1',
+ Q => rst_in_meta
+ );
+\rst_in_out_i_1__0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => rst_in_sync3_reg_0,
+ O => \rst_in_out_i_1__0_n_0\
+ );
+rst_in_out_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__0_n_0\,
+ D => rst_in_sync3,
+ Q => \^gtwiz_reset_tx_done_out\(0)
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__0_n_0\,
+ D => rst_in_meta,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__0_n_0\,
+ D => rst_in_sync1,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__0_n_0\,
+ D => rst_in_sync2,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer is
+ port (
+ gtwiz_reset_all_sync : out STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer is
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => gtwiz_reset_all_in(0),
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => gtwiz_reset_all_in(0),
+ Q => gtwiz_reset_all_sync
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => gtwiz_reset_all_in(0),
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => gtwiz_reset_all_in(0),
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => gtwiz_reset_all_in(0),
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_19 is
+ port (
+ gtwiz_reset_rx_any_sync : out STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[1]\ : out STD_LOGIC;
+ rst_in_out_reg_0 : out STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ GTHE3_CHANNEL_CPLLPD : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \sm_reset_rx_timer_clr0__0\ : in STD_LOGIC;
+ GTHE3_CHANNEL_RXUSERRDY : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_out_reg_1 : in STD_LOGIC;
+ gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_out_reg_2 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_19 : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_19;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_19 is
+ signal gtwiz_reset_rx_any : STD_LOGIC;
+ signal \^gtwiz_reset_rx_any_sync\ : STD_LOGIC;
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+ gtwiz_reset_rx_any_sync <= \^gtwiz_reset_rx_any_sync\;
+pllreset_rx_out_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFDF0010"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => Q(2),
+ I2 => Q(0),
+ I3 => \^gtwiz_reset_rx_any_sync\,
+ I4 => GTHE3_CHANNEL_CPLLPD(0),
+ O => \FSM_sequential_sm_reset_rx_reg[1]\
+ );
+\rst_in_meta_i_1__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => rst_in_out_reg_1,
+ I1 => gtwiz_reset_rx_datapath_in(0),
+ I2 => gtwiz_reset_rx_pll_and_datapath_in(0),
+ I3 => rst_in_out_reg_2,
+ O => gtwiz_reset_rx_any
+ );
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => gtwiz_reset_rx_any,
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => gtwiz_reset_rx_any,
+ Q => \^gtwiz_reset_rx_any_sync\
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => gtwiz_reset_rx_any,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => gtwiz_reset_rx_any,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => gtwiz_reset_rx_any,
+ Q => rst_in_sync3
+ );
+rxuserrdy_out_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFAAF00400000"
+ )
+ port map (
+ I0 => \^gtwiz_reset_rx_any_sync\,
+ I1 => \sm_reset_rx_timer_clr0__0\,
+ I2 => Q(0),
+ I3 => Q(1),
+ I4 => Q(2),
+ I5 => GTHE3_CHANNEL_RXUSERRDY(0),
+ O => rst_in_out_reg_0
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_20 is
+ port (
+ in0 : out STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_out_reg_0 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_20 : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_20;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_20 is
+ signal rst_in0_2 : STD_LOGIC;
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+\rst_in_meta_i_1__2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => gtwiz_reset_rx_datapath_in(0),
+ I1 => rst_in_out_reg_0,
+ O => rst_in0_2
+ );
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => rst_in0_2,
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => rst_in0_2,
+ Q => in0
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => rst_in0_2,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => rst_in0_2,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => rst_in0_2,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_21 is
+ port (
+ in0 : out STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_out_reg_0 : in STD_LOGIC;
+ gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_21 : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_21;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_21 is
+ signal p_0_in_1 : STD_LOGIC;
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+\rst_in_meta_i_1__1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => rst_in_out_reg_0,
+ I1 => gtwiz_reset_rx_pll_and_datapath_in(0),
+ O => p_0_in_1
+ );
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => p_0_in_1,
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => p_0_in_1,
+ Q => in0
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => p_0_in_1,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => p_0_in_1,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => p_0_in_1,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_22 is
+ port (
+ gtwiz_reset_tx_any_sync : out STD_LOGIC;
+ \FSM_sequential_sm_reset_tx_reg[1]\ : out STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ pllreset_tx_out_reg : in STD_LOGIC;
+ gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_sync3_reg_0 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_22 : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_22;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_22 is
+ signal gtwiz_reset_tx_any : STD_LOGIC;
+ signal \^gtwiz_reset_tx_any_sync\ : STD_LOGIC;
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+ gtwiz_reset_tx_any_sync <= \^gtwiz_reset_tx_any_sync\;
+pllreset_tx_out_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFDF0010"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => Q(2),
+ I2 => Q(0),
+ I3 => \^gtwiz_reset_tx_any_sync\,
+ I4 => pllreset_tx_out_reg,
+ O => \FSM_sequential_sm_reset_tx_reg[1]\
+ );
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => gtwiz_reset_tx_any,
+ Q => rst_in_meta
+ );
+rst_in_out_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"FE"
+ )
+ port map (
+ I0 => gtwiz_reset_tx_datapath_in(0),
+ I1 => gtwiz_reset_tx_pll_and_datapath_in(0),
+ I2 => rst_in_sync3_reg_0,
+ O => gtwiz_reset_tx_any
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => gtwiz_reset_tx_any,
+ Q => \^gtwiz_reset_tx_any_sync\
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => gtwiz_reset_tx_any,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => gtwiz_reset_tx_any,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => gtwiz_reset_tx_any,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_23 is
+ port (
+ in0 : out STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_23 : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_23;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_23 is
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => gtwiz_reset_tx_datapath_in(0),
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => gtwiz_reset_tx_datapath_in(0),
+ Q => in0
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => gtwiz_reset_tx_datapath_in(0),
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => gtwiz_reset_tx_datapath_in(0),
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => gtwiz_reset_tx_datapath_in(0),
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_24 is
+ port (
+ in0 : out STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_out_reg_0 : in STD_LOGIC;
+ gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_24 : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_24;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_24 is
+ signal p_1_in_0 : STD_LOGIC;
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+rst_in_meta_i_1: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => rst_in_out_reg_0,
+ I1 => gtwiz_reset_tx_pll_and_datapath_in(0),
+ O => p_1_in_0
+ );
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => p_1_in_0,
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => p_1_in_0,
+ Q => in0
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => p_1_in_0,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => p_1_in_0,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => p_1_in_0,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_27 is
+ port (
+ GTHE3_CHANNEL_TXPROGDIVRESET : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in0 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_27 : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_27;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_27 is
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => rst_in0,
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => rst_in0,
+ Q => GTHE3_CHANNEL_TXPROGDIVRESET(0)
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => rst_in0,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => rst_in0,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => rst_in0,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gthe3_channel_wrapper is
+ port (
+ cplllock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxn_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxp_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtpowergood_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrlock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXPHALIGNDONE : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXSYNCDONE : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 79 downto 0 );
+ GTHE3_CHANNEL_CPLLPD : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxn_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxp_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_GTRXRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_GTTXRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outrefclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outrefclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxcdrhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_RXPROGDIVRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxslide_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_RXUSERRDY : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXDLYSRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXPROGDIVRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXSYNCALLIN : in STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXUSERRDY : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 79 downto 0 );
+ loopback_in : in STD_LOGIC_VECTOR ( 11 downto 0 )
+ );
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gthe3_channel_wrapper;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gthe3_channel_wrapper is
+begin
+channel_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gthe3_channel
+ port map (
+ GTHE3_CHANNEL_CPLLPD(0) => GTHE3_CHANNEL_CPLLPD(0),
+ GTHE3_CHANNEL_GTRXRESET(0) => GTHE3_CHANNEL_GTRXRESET(0),
+ GTHE3_CHANNEL_GTTXRESET(0) => GTHE3_CHANNEL_GTTXRESET(0),
+ GTHE3_CHANNEL_RXPROGDIVRESET(0) => GTHE3_CHANNEL_RXPROGDIVRESET(0),
+ GTHE3_CHANNEL_RXUSERRDY(0) => GTHE3_CHANNEL_RXUSERRDY(0),
+ GTHE3_CHANNEL_TXDLYSRESET(0) => GTHE3_CHANNEL_TXDLYSRESET(0),
+ GTHE3_CHANNEL_TXPHALIGNDONE(3 downto 0) => GTHE3_CHANNEL_TXPHALIGNDONE(3 downto 0),
+ GTHE3_CHANNEL_TXPROGDIVRESET(0) => GTHE3_CHANNEL_TXPROGDIVRESET(0),
+ GTHE3_CHANNEL_TXSYNCALLIN(0) => GTHE3_CHANNEL_TXSYNCALLIN(0),
+ GTHE3_CHANNEL_TXSYNCDONE(0) => GTHE3_CHANNEL_TXSYNCDONE(0),
+ GTHE3_CHANNEL_TXUSERRDY(0) => GTHE3_CHANNEL_TXUSERRDY(0),
+ cplllock_out(3 downto 0) => cplllock_out(3 downto 0),
+ drpclk_in(3 downto 0) => drpclk_in(3 downto 0),
+ gthrxn_in(3 downto 0) => gthrxn_in(3 downto 0),
+ gthrxp_in(3 downto 0) => gthrxp_in(3 downto 0),
+ gthtxn_out(3 downto 0) => gthtxn_out(3 downto 0),
+ gthtxp_out(3 downto 0) => gthtxp_out(3 downto 0),
+ gtpowergood_out(3 downto 0) => gtpowergood_out(3 downto 0),
+ gtrefclk0_in(3 downto 0) => gtrefclk0_in(3 downto 0),
+ gtwiz_userdata_rx_out(79 downto 0) => gtwiz_userdata_rx_out(79 downto 0),
+ gtwiz_userdata_tx_in(79 downto 0) => gtwiz_userdata_tx_in(79 downto 0),
+ loopback_in(11 downto 0) => loopback_in(11 downto 0),
+ qpll0outclk_out(0) => qpll0outclk_out(0),
+ qpll0outrefclk_out(0) => qpll0outrefclk_out(0),
+ qpll1outclk_out(0) => qpll1outclk_out(0),
+ qpll1outrefclk_out(0) => qpll1outrefclk_out(0),
+ rxcdrhold_in(3 downto 0) => rxcdrhold_in(3 downto 0),
+ rxcdrlock_out(3 downto 0) => rxcdrlock_out(3 downto 0),
+ rxoutclk_out(3 downto 0) => rxoutclk_out(3 downto 0),
+ rxpmaresetdone_out(3 downto 0) => rxpmaresetdone_out(3 downto 0),
+ rxpolarity_in(3 downto 0) => rxpolarity_in(3 downto 0),
+ rxresetdone_out(3 downto 0) => rxresetdone_out(3 downto 0),
+ rxslide_in(3 downto 0) => rxslide_in(3 downto 0),
+ rxusrclk2_in(3 downto 0) => rxusrclk2_in(3 downto 0),
+ rxusrclk_in(3 downto 0) => rxusrclk_in(3 downto 0),
+ txoutclk_out(3 downto 0) => txoutclk_out(3 downto 0),
+ txpmaresetdone_out(3 downto 0) => txpmaresetdone_out(3 downto 0),
+ txpolarity_in(3 downto 0) => txpolarity_in(3 downto 0),
+ txresetdone_out(3 downto 0) => txresetdone_out(3 downto 0),
+ txusrclk2_in(3 downto 0) => txusrclk2_in(3 downto 0),
+ txusrclk_in(3 downto 0) => txusrclk_in(3 downto 0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gthe3_common_wrapper is
+ port (
+ qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in0 : out STD_LOGIC;
+ gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \gthe3_common_gen.GTHE3_COMMON_PRIM_INST\ : in STD_LOGIC
+ );
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gthe3_common_wrapper;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gthe3_common_wrapper is
+begin
+common_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gthe3_common
+ port map (
+ \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_0\ => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST\,
+ gtrefclk01_in(0) => gtrefclk01_in(0),
+ qpll0fbclklost_out(0) => qpll0fbclklost_out(0),
+ qpll0lock_out(0) => qpll0lock_out(0),
+ qpll0outclk_out(0) => qpll0outclk_out(0),
+ qpll0outrefclk_out(0) => qpll0outrefclk_out(0),
+ qpll1fbclklost_out(0) => qpll1fbclklost_out(0),
+ qpll1lock_out(0) => qpll1lock_out(0),
+ qpll1outclk_out(0) => qpll1outclk_out(0),
+ qpll1outrefclk_out(0) => qpll1outrefclk_out(0),
+ rst_in0 => rst_in0
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gtwiz_buffbypass_tx is
+ port (
+ gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXSYNCALLIN : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXDLYSRESET : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXSYNCDONE : in STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXPHALIGNDONE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_sync2_reg : in STD_LOGIC;
+ gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gtwiz_buffbypass_tx : entity is "gtwizard_ultrascale_v1_7_18_gtwiz_buffbypass_tx";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gtwiz_buffbypass_tx;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gtwiz_buffbypass_tx is
+ signal \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg_n_0_[1]\ : STD_LOGIC;
+ signal \^gthe3_channel_txdlysreset\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.bit_synchronizer_master_phaligndone_inst_n_0\ : STD_LOGIC;
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\ : STD_LOGIC;
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\ : STD_LOGIC;
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\ : STD_LOGIC;
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\ : STD_LOGIC;
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_1\ : STD_LOGIC;
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_2\ : STD_LOGIC;
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.txdlysreset_out[3]_i_1_n_0\ : STD_LOGIC;
+ attribute FSM_ENCODED_STATES : string;
+ attribute FSM_ENCODED_STATES of \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[0]\ : label is "ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET:01,ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE:10,iSTATE:00,ST_BUFFBYPASS_TX_DONE:11";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[1]\ : label is "ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET:01,ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE:10,iSTATE:00,ST_BUFFBYPASS_TX_DONE:11";
+begin
+ GTHE3_CHANNEL_TXDLYSRESET(0) <= \^gthe3_channel_txdlysreset\(0);
+\FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_1\,
+ D => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx\(0),
+ Q => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx__0\(0),
+ R => gtwiz_buffbypass_tx_reset_in(0)
+ );
+\FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_1\,
+ D => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx\(1),
+ Q => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg_n_0_[1]\,
+ R => gtwiz_buffbypass_tx_reset_in(0)
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.bit_synchronizer_master_phaligndone_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_7
+ port map (
+ \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[1]\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.bit_synchronizer_master_phaligndone_inst_n_0\,
+ GTHE3_CHANNEL_TXPHALIGNDONE(0) => GTHE3_CHANNEL_TXPHALIGNDONE(0),
+ Q(0) => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg_n_0_[1]\,
+ txusrclk2_in(0) => txusrclk2_in(0)
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.bit_synchronizer_master_syncdone_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_8
+ port map (
+ D(1 downto 0) => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx\(1 downto 0),
+ GTHE3_CHANNEL_TXSYNCDONE(0) => GTHE3_CHANNEL_TXSYNCDONE(0),
+ Q(1) => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg_n_0_[1]\,
+ Q(0) => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx__0\(0),
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\,
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\,
+ txusrclk2_in(0) => txusrclk2_in(0)
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_done_out_reg\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_2\,
+ D => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg_n_0_[1]\,
+ Q => gtwiz_buffbypass_tx_done_out(0),
+ R => gtwiz_buffbypass_tx_reset_in(0)
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_error_out_reg\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_2\,
+ D => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.bit_synchronizer_master_phaligndone_inst_n_0\,
+ Q => gtwiz_buffbypass_tx_error_out(0),
+ R => gtwiz_buffbypass_tx_reset_in(0)
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg_reg\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\,
+ Q => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\,
+ R => '0'
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg_reg\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\,
+ Q => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\,
+ R => gtwiz_buffbypass_tx_reset_in(0)
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer
+ port map (
+ E(0) => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_1\,
+ \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[0]\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_2\,
+ Q(1) => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg_n_0_[1]\,
+ Q(0) => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx__0\(0),
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\,
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\,
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\,
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\,
+ gtwiz_buffbypass_tx_start_user_in(0) => gtwiz_buffbypass_tx_start_user_in(0),
+ rst_in_sync2_reg_0 => rst_in_sync2_reg,
+ txusrclk2_in(0) => txusrclk2_in(0)
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.txdlysreset_out[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AAAAFFFF00005510"
+ )
+ port map (
+ I0 => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg_n_0_[1]\,
+ I1 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\,
+ I2 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\,
+ I3 => gtwiz_buffbypass_tx_start_user_in(0),
+ I4 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx__0\(0),
+ I5 => \^gthe3_channel_txdlysreset\(0),
+ O => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.txdlysreset_out[3]_i_1_n_0\
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.txdlysreset_out_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.txdlysreset_out[3]_i_1_n_0\,
+ Q => \^gthe3_channel_txdlysreset\(0),
+ R => gtwiz_buffbypass_tx_reset_in(0)
+ );
+txsyncallin_out0: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => GTHE3_CHANNEL_TXPHALIGNDONE(1),
+ I1 => GTHE3_CHANNEL_TXPHALIGNDONE(0),
+ I2 => GTHE3_CHANNEL_TXPHALIGNDONE(3),
+ I3 => GTHE3_CHANNEL_TXPHALIGNDONE(2),
+ O => GTHE3_CHANNEL_TXSYNCALLIN(0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gtwiz_reset is
+ port (
+ gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXPROGDIVRESET : out STD_LOGIC_VECTOR ( 0 to 0 );
+ i_in_out_reg : out STD_LOGIC;
+ gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ pllreset_tx_out_reg_0 : out STD_LOGIC;
+ GTHE3_CHANNEL_GTTXRESET : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXUSERRDY : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_CPLLPD : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_RXPROGDIVRESET : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_GTRXRESET : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_RXUSERRDY : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_out_reg : out STD_LOGIC;
+ in0 : in STD_LOGIC;
+ gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1lock_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ i_in_meta_reg : in STD_LOGIC;
+ i_in_meta_reg_0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in0 : in STD_LOGIC;
+ rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gtwiz_reset : entity is "gtwizard_ultrascale_v1_7_18_gtwiz_reset";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gtwiz_reset;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gtwiz_reset is
+ signal \FSM_sequential_sm_reset_all[2]_i_3_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_sm_reset_all[2]_i_4_n_0\ : STD_LOGIC;
+ signal \^gthe3_channel_cpllpd\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^gthe3_channel_gtrxreset\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^gthe3_channel_gttxreset\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^gthe3_channel_rxprogdivreset\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^gthe3_channel_rxuserrdy\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^gthe3_channel_txuserrdy\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal bit_synchronizer_gtpowergood_inst_n_0 : STD_LOGIC;
+ signal bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst_n_0 : STD_LOGIC;
+ signal bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0 : STD_LOGIC;
+ signal bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_0 : STD_LOGIC;
+ signal bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2 : STD_LOGIC;
+ signal bit_synchronizer_plllock_rx_inst_n_0 : STD_LOGIC;
+ signal bit_synchronizer_plllock_rx_inst_n_1 : STD_LOGIC;
+ signal bit_synchronizer_plllock_rx_inst_n_2 : STD_LOGIC;
+ signal bit_synchronizer_plllock_rx_inst_n_3 : STD_LOGIC;
+ signal bit_synchronizer_plllock_rx_inst_n_4 : STD_LOGIC;
+ signal bit_synchronizer_plllock_tx_inst_n_0 : STD_LOGIC;
+ signal bit_synchronizer_plllock_tx_inst_n_1 : STD_LOGIC;
+ signal bit_synchronizer_plllock_tx_inst_n_2 : STD_LOGIC;
+ signal bit_synchronizer_plllock_tx_inst_n_3 : STD_LOGIC;
+ signal bit_synchronizer_rxcdrlock_inst_n_1 : STD_LOGIC;
+ signal bit_synchronizer_rxcdrlock_inst_n_2 : STD_LOGIC;
+ signal bit_synchronizer_rxcdrlock_inst_n_3 : STD_LOGIC;
+ signal gtwiz_reset_all_sync : STD_LOGIC;
+ signal gtwiz_reset_rx_any_sync : STD_LOGIC;
+ signal gtwiz_reset_rx_datapath_int_i_1_n_0 : STD_LOGIC;
+ signal gtwiz_reset_rx_datapath_int_reg_n_0 : STD_LOGIC;
+ signal gtwiz_reset_rx_datapath_sync : STD_LOGIC;
+ signal gtwiz_reset_rx_done_int_reg_n_0 : STD_LOGIC;
+ signal gtwiz_reset_rx_pll_and_datapath_dly : STD_LOGIC;
+ signal gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0 : STD_LOGIC;
+ signal gtwiz_reset_rx_pll_and_datapath_int_reg_n_0 : STD_LOGIC;
+ signal gtwiz_reset_rx_pll_and_datapath_sync : STD_LOGIC;
+ signal gtwiz_reset_tx_any_sync : STD_LOGIC;
+ signal gtwiz_reset_tx_datapath_sync : STD_LOGIC;
+ signal \gtwiz_reset_tx_done_int0__0\ : STD_LOGIC;
+ signal gtwiz_reset_tx_done_int_reg_n_0 : STD_LOGIC;
+ signal gtwiz_reset_tx_pll_and_datapath_dly : STD_LOGIC;
+ signal gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0 : STD_LOGIC;
+ signal gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 : STD_LOGIC;
+ signal gtwiz_reset_tx_pll_and_datapath_sync : STD_LOGIC;
+ signal p_0_in : STD_LOGIC;
+ signal \p_0_in11_out__0\ : STD_LOGIC;
+ signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal p_1_in : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \^pllreset_tx_out_reg_0\ : STD_LOGIC;
+ signal reset_synchronizer_gtwiz_reset_rx_any_inst_n_1 : STD_LOGIC;
+ signal reset_synchronizer_gtwiz_reset_rx_any_inst_n_2 : STD_LOGIC;
+ signal reset_synchronizer_gtwiz_reset_tx_any_inst_n_1 : STD_LOGIC;
+ signal sel : STD_LOGIC;
+ signal sm_reset_all : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \sm_reset_all__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal sm_reset_all_timer_clr_i_1_n_0 : STD_LOGIC;
+ signal sm_reset_all_timer_clr_i_2_n_0 : STD_LOGIC;
+ signal sm_reset_all_timer_clr_reg_n_0 : STD_LOGIC;
+ signal sm_reset_all_timer_ctr : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \sm_reset_all_timer_ctr0_inferred__0/i__n_0\ : STD_LOGIC;
+ signal \sm_reset_all_timer_ctr[0]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_all_timer_ctr[1]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_all_timer_ctr[2]_i_1_n_0\ : STD_LOGIC;
+ signal sm_reset_all_timer_sat : STD_LOGIC;
+ signal sm_reset_all_timer_sat_i_1_n_0 : STD_LOGIC;
+ signal sm_reset_rx : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \sm_reset_rx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal sm_reset_rx_cdr_to_clr : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0\ : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_ctr_reg : STD_LOGIC_VECTOR ( 25 downto 0 );
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9\ : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat_i_1_n_0 : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat_i_2_n_0 : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat_i_3_n_0 : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat_i_4_n_0 : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat_i_5_n_0 : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat_i_6_n_0 : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat_i_7_n_0 : STD_LOGIC;
+ signal sm_reset_rx_pll_timer_clr_i_1_n_0 : STD_LOGIC;
+ signal sm_reset_rx_pll_timer_clr_reg_n_0 : STD_LOGIC;
+ signal \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\ : STD_LOGIC;
+ signal sm_reset_rx_pll_timer_ctr_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal sm_reset_rx_pll_timer_sat : STD_LOGIC;
+ signal sm_reset_rx_pll_timer_sat_i_1_n_0 : STD_LOGIC;
+ signal \sm_reset_rx_timer_clr010_out__0\ : STD_LOGIC;
+ signal \sm_reset_rx_timer_clr0__0\ : STD_LOGIC;
+ signal sm_reset_rx_timer_clr_reg_n_0 : STD_LOGIC;
+ signal sm_reset_rx_timer_ctr : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \sm_reset_rx_timer_ctr0_inferred__0/i__n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_timer_ctr[0]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_timer_ctr[1]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_timer_ctr[2]_i_1_n_0\ : STD_LOGIC;
+ signal sm_reset_rx_timer_sat : STD_LOGIC;
+ signal sm_reset_rx_timer_sat_i_1_n_0 : STD_LOGIC;
+ signal sm_reset_tx : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \sm_reset_tx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal sm_reset_tx_pll_timer_clr_i_1_n_0 : STD_LOGIC;
+ signal sm_reset_tx_pll_timer_clr_reg_n_0 : STD_LOGIC;
+ signal \sm_reset_tx_pll_timer_ctr[2]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_tx_pll_timer_ctr[6]_i_2_n_0\ : STD_LOGIC;
+ signal \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0\ : STD_LOGIC;
+ signal \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\ : STD_LOGIC;
+ signal sm_reset_tx_pll_timer_ctr_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal sm_reset_tx_pll_timer_sat : STD_LOGIC;
+ signal sm_reset_tx_pll_timer_sat_i_1_n_0 : STD_LOGIC;
+ signal \sm_reset_tx_timer_clr0__0\ : STD_LOGIC;
+ signal sm_reset_tx_timer_clr_reg_n_0 : STD_LOGIC;
+ signal sm_reset_tx_timer_ctr : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal sm_reset_tx_timer_sat : STD_LOGIC;
+ signal sm_reset_tx_timer_sat_i_1_n_0 : STD_LOGIC;
+ signal \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
+ signal \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[1]_i_1\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[2]_i_2\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[2]_i_3\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[2]_i_4\ : label is "soft_lutpair11";
+ attribute FSM_ENCODED_STATES : string;
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_all_reg[0]\ : label is "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_all_reg[1]\ : label is "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_all_reg[2]\ : label is "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_rx_reg[0]\ : label is "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_rx_reg[1]\ : label is "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_rx_reg[2]\ : label is "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_tx_reg[0]\ : label is "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_tx_reg[1]\ : label is "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_tx_reg[2]\ : label is "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001";
+ attribute SOFT_HLUTNM of gtwiz_reset_rx_datapath_int_i_1 : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of gtwiz_reset_tx_pll_and_datapath_int_i_1 : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \sm_reset_all_timer_ctr[1]_i_1\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \sm_reset_all_timer_ctr[2]_i_1\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \sm_reset_rx_cdr_to_ctr[0]_i_3\ : label is "soft_lutpair4";
+ attribute ADDER_THRESHOLD : integer;
+ attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[0]_i_2\ : label is 16;
+ attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[16]_i_1\ : label is 16;
+ attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[24]_i_1\ : label is 16;
+ attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[8]_i_1\ : label is 16;
+ attribute SOFT_HLUTNM of sm_reset_rx_cdr_to_sat_i_5 : label is "soft_lutpair4";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[1]_i_1\ : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[2]_i_1\ : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[3]_i_1\ : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[4]_i_1\ : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[6]_i_1\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[7]_i_1\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[8]_i_1\ : label is "soft_lutpair6";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[9]_i_2\ : label is "soft_lutpair6";
+ attribute SOFT_HLUTNM of sm_reset_rx_timer_clr_i_4 : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \sm_reset_rx_timer_ctr[1]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \sm_reset_rx_timer_ctr[2]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of sm_reset_rx_timer_sat_i_1 : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[0]_i_1\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[1]_i_1\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[2]_i_1\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[3]_i_1\ : label is "soft_lutpair7";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[4]_i_1\ : label is "soft_lutpair7";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[6]_i_2\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[8]_i_1\ : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[9]_i_2\ : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of \sm_reset_tx_timer_ctr[1]_i_1\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \sm_reset_tx_timer_ctr[2]_i_1\ : label is "soft_lutpair15";
+begin
+ GTHE3_CHANNEL_CPLLPD(0) <= \^gthe3_channel_cpllpd\(0);
+ GTHE3_CHANNEL_GTRXRESET(0) <= \^gthe3_channel_gtrxreset\(0);
+ GTHE3_CHANNEL_GTTXRESET(0) <= \^gthe3_channel_gttxreset\(0);
+ GTHE3_CHANNEL_RXPROGDIVRESET(0) <= \^gthe3_channel_rxprogdivreset\(0);
+ GTHE3_CHANNEL_RXUSERRDY(0) <= \^gthe3_channel_rxuserrdy\(0);
+ GTHE3_CHANNEL_TXUSERRDY(0) <= \^gthe3_channel_txuserrdy\(0);
+ pllreset_tx_out_reg_0 <= \^pllreset_tx_out_reg_0\;
+\FSM_sequential_sm_reset_all[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00FFF7000000FFFF"
+ )
+ port map (
+ I0 => gtwiz_reset_rx_done_int_reg_n_0,
+ I1 => sm_reset_all_timer_sat,
+ I2 => sm_reset_all_timer_clr_reg_n_0,
+ I3 => sm_reset_all(2),
+ I4 => sm_reset_all(1),
+ I5 => sm_reset_all(0),
+ O => \sm_reset_all__0\(0)
+ );
+\FSM_sequential_sm_reset_all[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => sm_reset_all(0),
+ I1 => sm_reset_all(1),
+ O => \sm_reset_all__0\(1)
+ );
+\FSM_sequential_sm_reset_all[2]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => sm_reset_all(2),
+ I1 => sm_reset_all(1),
+ O => \sm_reset_all__0\(2)
+ );
+\FSM_sequential_sm_reset_all[2]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => sm_reset_all_timer_sat,
+ I1 => gtwiz_reset_rx_done_int_reg_n_0,
+ I2 => sm_reset_all_timer_clr_reg_n_0,
+ O => \FSM_sequential_sm_reset_all[2]_i_3_n_0\
+ );
+\FSM_sequential_sm_reset_all[2]_i_4\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"40"
+ )
+ port map (
+ I0 => sm_reset_all_timer_clr_reg_n_0,
+ I1 => sm_reset_all_timer_sat,
+ I2 => gtwiz_reset_tx_done_int_reg_n_0,
+ O => \FSM_sequential_sm_reset_all[2]_i_4_n_0\
+ );
+\FSM_sequential_sm_reset_all_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtpowergood_inst_n_0,
+ D => \sm_reset_all__0\(0),
+ Q => sm_reset_all(0),
+ R => gtwiz_reset_all_sync
+ );
+\FSM_sequential_sm_reset_all_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtpowergood_inst_n_0,
+ D => \sm_reset_all__0\(1),
+ Q => sm_reset_all(1),
+ R => gtwiz_reset_all_sync
+ );
+\FSM_sequential_sm_reset_all_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtpowergood_inst_n_0,
+ D => \sm_reset_all__0\(2),
+ Q => sm_reset_all(2),
+ R => gtwiz_reset_all_sync
+ );
+\FSM_sequential_sm_reset_rx[2]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"F8B8"
+ )
+ port map (
+ I0 => sm_reset_rx(0),
+ I1 => sm_reset_rx(1),
+ I2 => sm_reset_rx(2),
+ I3 => \p_0_in11_out__0\,
+ O => \sm_reset_rx__0\(2)
+ );
+\FSM_sequential_sm_reset_rx[2]_i_6\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000800000000000"
+ )
+ port map (
+ I0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(2),
+ I1 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(3),
+ I2 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0),
+ I3 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(1),
+ I4 => sm_reset_rx_timer_clr_reg_n_0,
+ I5 => sm_reset_rx_timer_sat,
+ O => \p_0_in11_out__0\
+ );
+\FSM_sequential_sm_reset_rx_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst_n_0,
+ D => \sm_reset_rx__0\(0),
+ Q => sm_reset_rx(0),
+ R => gtwiz_reset_rx_any_sync
+ );
+\FSM_sequential_sm_reset_rx_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst_n_0,
+ D => \sm_reset_rx__0\(1),
+ Q => sm_reset_rx(1),
+ R => gtwiz_reset_rx_any_sync
+ );
+\FSM_sequential_sm_reset_rx_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst_n_0,
+ D => \sm_reset_rx__0\(2),
+ Q => sm_reset_rx(2),
+ R => gtwiz_reset_rx_any_sync
+ );
+\FSM_sequential_sm_reset_tx[2]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"2C"
+ )
+ port map (
+ I0 => sm_reset_tx(0),
+ I1 => sm_reset_tx(2),
+ I2 => sm_reset_tx(1),
+ O => \sm_reset_tx__0\(2)
+ );
+\FSM_sequential_sm_reset_tx[2]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000800000000000"
+ )
+ port map (
+ I0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(2),
+ I1 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(3),
+ I2 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0),
+ I3 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(1),
+ I4 => sm_reset_tx_timer_clr_reg_n_0,
+ I5 => sm_reset_tx_timer_sat,
+ O => \gtwiz_reset_tx_done_int0__0\
+ );
+\FSM_sequential_sm_reset_tx_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2,
+ D => \sm_reset_tx__0\(0),
+ Q => sm_reset_tx(0),
+ R => gtwiz_reset_tx_any_sync
+ );
+\FSM_sequential_sm_reset_tx_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2,
+ D => \sm_reset_tx__0\(1),
+ Q => sm_reset_tx(1),
+ R => gtwiz_reset_tx_any_sync
+ );
+\FSM_sequential_sm_reset_tx_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2,
+ D => \sm_reset_tx__0\(2),
+ Q => sm_reset_tx(2),
+ R => gtwiz_reset_tx_any_sync
+ );
+bit_synchronizer_gtpowergood_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_9
+ port map (
+ E(0) => bit_synchronizer_gtpowergood_inst_n_0,
+ \FSM_sequential_sm_reset_all_reg[0]\ => \FSM_sequential_sm_reset_all[2]_i_3_n_0\,
+ \FSM_sequential_sm_reset_all_reg[0]_0\ => \FSM_sequential_sm_reset_all[2]_i_4_n_0\,
+ Q(2 downto 0) => sm_reset_all(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ in0 => in0
+ );
+bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_10
+ port map (
+ E(0) => bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst_n_0,
+ \FSM_sequential_sm_reset_rx_reg[0]\ => bit_synchronizer_plllock_rx_inst_n_4,
+ \FSM_sequential_sm_reset_rx_reg[0]_0\ => bit_synchronizer_rxcdrlock_inst_n_2,
+ \FSM_sequential_sm_reset_rx_reg[0]_1\ => sm_reset_rx_pll_timer_clr_reg_n_0,
+ Q(2 downto 0) => sm_reset_rx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_pll_and_datapath_dly => gtwiz_reset_rx_pll_and_datapath_dly,
+ in0 => gtwiz_reset_rx_datapath_sync,
+ sm_reset_rx_pll_timer_sat => sm_reset_rx_pll_timer_sat
+ );
+bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_11
+ port map (
+ D(1 downto 0) => \sm_reset_rx__0\(1 downto 0),
+ Q(2 downto 0) => sm_reset_rx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_pll_and_datapath_dly => gtwiz_reset_rx_pll_and_datapath_dly,
+ in0 => gtwiz_reset_rx_pll_and_datapath_sync,
+ \p_0_in11_out__0\ => \p_0_in11_out__0\
+ );
+bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_12
+ port map (
+ \FSM_sequential_sm_reset_tx[2]_i_5\ => sm_reset_tx_pll_timer_clr_reg_n_0,
+ Q(0) => sm_reset_tx(0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_tx_pll_and_datapath_dly => gtwiz_reset_tx_pll_and_datapath_dly,
+ i_in_out_reg_0 => bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0,
+ in0 => gtwiz_reset_tx_datapath_sync,
+ sm_reset_tx_pll_timer_sat => sm_reset_tx_pll_timer_sat
+ );
+bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_13
+ port map (
+ D(1 downto 0) => \sm_reset_tx__0\(1 downto 0),
+ Q(2 downto 0) => sm_reset_tx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_tx_pll_and_datapath_dly => gtwiz_reset_tx_pll_and_datapath_dly,
+ in0 => gtwiz_reset_tx_pll_and_datapath_sync
+ );
+bit_synchronizer_gtwiz_reset_userclk_rx_active_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_14
+ port map (
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_userclk_rx_active_in(0) => gtwiz_userclk_rx_active_in(0),
+ rxuserrdy_out_reg => sm_reset_rx_timer_clr_reg_n_0,
+ \sm_reset_rx_timer_clr0__0\ => \sm_reset_rx_timer_clr0__0\,
+ sm_reset_rx_timer_sat => sm_reset_rx_timer_sat
+ );
+bit_synchronizer_gtwiz_reset_userclk_tx_active_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_15
+ port map (
+ E(0) => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2,
+ \FSM_sequential_sm_reset_tx_reg[0]\ => bit_synchronizer_plllock_tx_inst_n_3,
+ \FSM_sequential_sm_reset_tx_reg[1]\ => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_0,
+ GTHE3_CHANNEL_TXUSERRDY(0) => \^gthe3_channel_txuserrdy\(0),
+ Q(2 downto 0) => sm_reset_tx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_tx_any_sync => gtwiz_reset_tx_any_sync,
+ \gtwiz_reset_tx_done_int0__0\ => \gtwiz_reset_tx_done_int0__0\,
+ gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0),
+ \sm_reset_tx_timer_clr0__0\ => \sm_reset_tx_timer_clr0__0\,
+ sm_reset_tx_timer_sat => sm_reset_tx_timer_sat,
+ txuserrdy_out_reg => sm_reset_tx_timer_clr_reg_n_0
+ );
+bit_synchronizer_plllock_rx_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_16
+ port map (
+ \FSM_sequential_sm_reset_rx_reg[0]\ => bit_synchronizer_plllock_rx_inst_n_1,
+ \FSM_sequential_sm_reset_rx_reg[2]\ => bit_synchronizer_plllock_rx_inst_n_2,
+ \FSM_sequential_sm_reset_rx_reg[2]_0\ => bit_synchronizer_plllock_rx_inst_n_3,
+ GTHE3_CHANNEL_GTRXRESET(0) => \^gthe3_channel_gtrxreset\(0),
+ Q(2 downto 0) => sm_reset_rx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_any_sync => gtwiz_reset_rx_any_sync,
+ gtwiz_reset_rx_done_int_reg => gtwiz_reset_rx_done_int_reg_n_0,
+ i_in_meta_reg_0 => i_in_meta_reg,
+ i_in_out_reg_0 => bit_synchronizer_plllock_rx_inst_n_0,
+ i_in_out_reg_1 => bit_synchronizer_plllock_rx_inst_n_4,
+ \p_0_in11_out__0\ => \p_0_in11_out__0\,
+ sm_reset_rx_cdr_to_clr => sm_reset_rx_cdr_to_clr,
+ sm_reset_rx_cdr_to_clr_reg => bit_synchronizer_rxcdrlock_inst_n_3,
+ \sm_reset_rx_timer_clr010_out__0\ => \sm_reset_rx_timer_clr010_out__0\,
+ \sm_reset_rx_timer_clr0__0\ => \sm_reset_rx_timer_clr0__0\,
+ sm_reset_rx_timer_clr_reg => sm_reset_rx_timer_clr_reg_n_0,
+ sm_reset_rx_timer_sat => sm_reset_rx_timer_sat
+ );
+bit_synchronizer_plllock_tx_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_17
+ port map (
+ \FSM_sequential_sm_reset_tx_reg[0]\ => bit_synchronizer_plllock_tx_inst_n_2,
+ \FSM_sequential_sm_reset_tx_reg[0]_0\ => bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0,
+ \FSM_sequential_sm_reset_tx_reg[2]\ => bit_synchronizer_plllock_tx_inst_n_1,
+ GTHE3_CHANNEL_GTTXRESET(0) => \^gthe3_channel_gttxreset\(0),
+ Q(2 downto 0) => sm_reset_tx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_tx_any_sync => gtwiz_reset_tx_any_sync,
+ \gtwiz_reset_tx_done_int0__0\ => \gtwiz_reset_tx_done_int0__0\,
+ gtwiz_reset_tx_done_int_reg => gtwiz_reset_tx_done_int_reg_n_0,
+ i_in_out_reg_0 => bit_synchronizer_plllock_tx_inst_n_0,
+ i_in_out_reg_1 => bit_synchronizer_plllock_tx_inst_n_3,
+ qpll1lock_out(0) => qpll1lock_out(0),
+ \sm_reset_tx_timer_clr0__0\ => \sm_reset_tx_timer_clr0__0\,
+ sm_reset_tx_timer_clr_reg => sm_reset_tx_timer_clr_reg_n_0,
+ sm_reset_tx_timer_sat => sm_reset_tx_timer_sat
+ );
+bit_synchronizer_rxcdrlock_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_18
+ port map (
+ \FSM_sequential_sm_reset_rx_reg[2]\ => bit_synchronizer_rxcdrlock_inst_n_1,
+ \FSM_sequential_sm_reset_rx_reg[2]_0\ => bit_synchronizer_rxcdrlock_inst_n_3,
+ GTHE3_CHANNEL_RXPROGDIVRESET(0) => \^gthe3_channel_rxprogdivreset\(0),
+ Q(2 downto 0) => sm_reset_rx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_any_sync => gtwiz_reset_rx_any_sync,
+ i_in_meta_reg_0 => i_in_meta_reg_0,
+ i_in_out_reg_0 => i_in_out_reg,
+ i_in_out_reg_1 => bit_synchronizer_rxcdrlock_inst_n_2,
+ \p_0_in11_out__0\ => \p_0_in11_out__0\,
+ sm_reset_rx_cdr_to_sat => sm_reset_rx_cdr_to_sat,
+ \sm_reset_rx_timer_clr0__0\ => \sm_reset_rx_timer_clr0__0\
+ );
+gtrxreset_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_plllock_rx_inst_n_3,
+ Q => \^gthe3_channel_gtrxreset\(0),
+ R => '0'
+ );
+gttxreset_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_plllock_tx_inst_n_2,
+ Q => \^gthe3_channel_gttxreset\(0),
+ R => '0'
+ );
+gtwiz_reset_rx_datapath_int_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"F740"
+ )
+ port map (
+ I0 => sm_reset_all(2),
+ I1 => sm_reset_all(0),
+ I2 => sm_reset_all(1),
+ I3 => gtwiz_reset_rx_datapath_int_reg_n_0,
+ O => gtwiz_reset_rx_datapath_int_i_1_n_0
+ );
+gtwiz_reset_rx_datapath_int_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => gtwiz_reset_rx_datapath_int_i_1_n_0,
+ Q => gtwiz_reset_rx_datapath_int_reg_n_0,
+ R => gtwiz_reset_all_sync
+ );
+gtwiz_reset_rx_done_int_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_plllock_rx_inst_n_0,
+ Q => gtwiz_reset_rx_done_int_reg_n_0,
+ R => gtwiz_reset_rx_any_sync
+ );
+gtwiz_reset_rx_pll_and_datapath_int_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"F704"
+ )
+ port map (
+ I0 => sm_reset_all(0),
+ I1 => sm_reset_all(2),
+ I2 => sm_reset_all(1),
+ I3 => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0,
+ O => gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0
+ );
+gtwiz_reset_rx_pll_and_datapath_int_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0,
+ Q => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0,
+ R => gtwiz_reset_all_sync
+ );
+gtwiz_reset_tx_done_int_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_plllock_tx_inst_n_0,
+ Q => gtwiz_reset_tx_done_int_reg_n_0,
+ R => gtwiz_reset_tx_any_sync
+ );
+gtwiz_reset_tx_pll_and_datapath_int_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FB02"
+ )
+ port map (
+ I0 => sm_reset_all(0),
+ I1 => sm_reset_all(1),
+ I2 => sm_reset_all(2),
+ I3 => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0,
+ O => gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0
+ );
+gtwiz_reset_tx_pll_and_datapath_int_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0,
+ Q => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0,
+ R => gtwiz_reset_all_sync
+ );
+pllreset_rx_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => reset_synchronizer_gtwiz_reset_rx_any_inst_n_1,
+ Q => \^gthe3_channel_cpllpd\(0),
+ R => '0'
+ );
+pllreset_tx_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => reset_synchronizer_gtwiz_reset_tx_any_inst_n_1,
+ Q => \^pllreset_tx_out_reg_0\,
+ R => '0'
+ );
+reset_synchronizer_gtwiz_reset_all_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer
+ port map (
+ gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0),
+ gtwiz_reset_all_sync => gtwiz_reset_all_sync,
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0)
+ );
+reset_synchronizer_gtwiz_reset_rx_any_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_19
+ port map (
+ \FSM_sequential_sm_reset_rx_reg[1]\ => reset_synchronizer_gtwiz_reset_rx_any_inst_n_1,
+ GTHE3_CHANNEL_CPLLPD(0) => \^gthe3_channel_cpllpd\(0),
+ GTHE3_CHANNEL_RXUSERRDY(0) => \^gthe3_channel_rxuserrdy\(0),
+ Q(2 downto 0) => sm_reset_rx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_any_sync => gtwiz_reset_rx_any_sync,
+ gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0),
+ gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0),
+ rst_in_out_reg_0 => reset_synchronizer_gtwiz_reset_rx_any_inst_n_2,
+ rst_in_out_reg_1 => gtwiz_reset_rx_datapath_int_reg_n_0,
+ rst_in_out_reg_2 => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0,
+ \sm_reset_rx_timer_clr0__0\ => \sm_reset_rx_timer_clr0__0\
+ );
+reset_synchronizer_gtwiz_reset_rx_datapath_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_20
+ port map (
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0),
+ in0 => gtwiz_reset_rx_datapath_sync,
+ rst_in_out_reg_0 => gtwiz_reset_rx_datapath_int_reg_n_0
+ );
+reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_21
+ port map (
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0),
+ in0 => gtwiz_reset_rx_pll_and_datapath_sync,
+ rst_in_out_reg_0 => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0
+ );
+reset_synchronizer_gtwiz_reset_tx_any_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_22
+ port map (
+ \FSM_sequential_sm_reset_tx_reg[1]\ => reset_synchronizer_gtwiz_reset_tx_any_inst_n_1,
+ Q(2 downto 0) => sm_reset_tx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_tx_any_sync => gtwiz_reset_tx_any_sync,
+ gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0),
+ gtwiz_reset_tx_pll_and_datapath_in(0) => gtwiz_reset_tx_pll_and_datapath_in(0),
+ pllreset_tx_out_reg => \^pllreset_tx_out_reg_0\,
+ rst_in_sync3_reg_0 => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0
+ );
+reset_synchronizer_gtwiz_reset_tx_datapath_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_23
+ port map (
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0),
+ in0 => gtwiz_reset_tx_datapath_sync
+ );
+reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_24
+ port map (
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_tx_pll_and_datapath_in(0) => gtwiz_reset_tx_pll_and_datapath_in(0),
+ in0 => gtwiz_reset_tx_pll_and_datapath_sync,
+ rst_in_out_reg_0 => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0
+ );
+reset_synchronizer_rx_done_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_25
+ port map (
+ gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0),
+ rst_in_sync2_reg_0 => gtwiz_reset_rx_done_int_reg_n_0,
+ rxusrclk2_in(0) => rxusrclk2_in(0)
+ );
+reset_synchronizer_tx_done_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_26
+ port map (
+ gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0),
+ rst_in_out_reg_0 => rst_in_out_reg,
+ rst_in_sync3_reg_0 => gtwiz_reset_tx_done_int_reg_n_0,
+ txusrclk2_in(0) => txusrclk2_in(0)
+ );
+reset_synchronizer_txprogdivreset_inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_reset_synchronizer_27
+ port map (
+ GTHE3_CHANNEL_TXPROGDIVRESET(0) => GTHE3_CHANNEL_TXPROGDIVRESET(0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ rst_in0 => rst_in0
+ );
+rxprogdivreset_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_rxcdrlock_inst_n_1,
+ Q => \^gthe3_channel_rxprogdivreset\(0),
+ R => '0'
+ );
+rxuserrdy_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => reset_synchronizer_gtwiz_reset_rx_any_inst_n_2,
+ Q => \^gthe3_channel_rxuserrdy\(0),
+ R => '0'
+ );
+sm_reset_all_timer_clr_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"EFFA200A"
+ )
+ port map (
+ I0 => sm_reset_all_timer_clr_i_2_n_0,
+ I1 => sm_reset_all(1),
+ I2 => sm_reset_all(2),
+ I3 => sm_reset_all(0),
+ I4 => sm_reset_all_timer_clr_reg_n_0,
+ O => sm_reset_all_timer_clr_i_1_n_0
+ );
+sm_reset_all_timer_clr_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000B0003333BB33"
+ )
+ port map (
+ I0 => gtwiz_reset_rx_done_int_reg_n_0,
+ I1 => sm_reset_all(2),
+ I2 => gtwiz_reset_tx_done_int_reg_n_0,
+ I3 => sm_reset_all_timer_sat,
+ I4 => sm_reset_all_timer_clr_reg_n_0,
+ I5 => sm_reset_all(1),
+ O => sm_reset_all_timer_clr_i_2_n_0
+ );
+sm_reset_all_timer_clr_reg: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_all_timer_clr_i_1_n_0,
+ Q => sm_reset_all_timer_clr_reg_n_0,
+ S => gtwiz_reset_all_sync
+ );
+\sm_reset_all_timer_ctr0_inferred__0/i_\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"7F"
+ )
+ port map (
+ I0 => sm_reset_all_timer_ctr(2),
+ I1 => sm_reset_all_timer_ctr(0),
+ I2 => sm_reset_all_timer_ctr(1),
+ O => \sm_reset_all_timer_ctr0_inferred__0/i__n_0\
+ );
+\sm_reset_all_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => sm_reset_all_timer_ctr(0),
+ O => \sm_reset_all_timer_ctr[0]_i_1_n_0\
+ );
+\sm_reset_all_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => sm_reset_all_timer_ctr(0),
+ I1 => sm_reset_all_timer_ctr(1),
+ O => \sm_reset_all_timer_ctr[1]_i_1_n_0\
+ );
+\sm_reset_all_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => sm_reset_all_timer_ctr(0),
+ I1 => sm_reset_all_timer_ctr(1),
+ I2 => sm_reset_all_timer_ctr(2),
+ O => \sm_reset_all_timer_ctr[2]_i_1_n_0\
+ );
+\sm_reset_all_timer_ctr_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_all_timer_ctr0_inferred__0/i__n_0\,
+ D => \sm_reset_all_timer_ctr[0]_i_1_n_0\,
+ Q => sm_reset_all_timer_ctr(0),
+ R => sm_reset_all_timer_clr_reg_n_0
+ );
+\sm_reset_all_timer_ctr_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_all_timer_ctr0_inferred__0/i__n_0\,
+ D => \sm_reset_all_timer_ctr[1]_i_1_n_0\,
+ Q => sm_reset_all_timer_ctr(1),
+ R => sm_reset_all_timer_clr_reg_n_0
+ );
+\sm_reset_all_timer_ctr_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_all_timer_ctr0_inferred__0/i__n_0\,
+ D => \sm_reset_all_timer_ctr[2]_i_1_n_0\,
+ Q => sm_reset_all_timer_ctr(2),
+ R => sm_reset_all_timer_clr_reg_n_0
+ );
+sm_reset_all_timer_sat_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0000FF80"
+ )
+ port map (
+ I0 => sm_reset_all_timer_ctr(2),
+ I1 => sm_reset_all_timer_ctr(0),
+ I2 => sm_reset_all_timer_ctr(1),
+ I3 => sm_reset_all_timer_sat,
+ I4 => sm_reset_all_timer_clr_reg_n_0,
+ O => sm_reset_all_timer_sat_i_1_n_0
+ );
+sm_reset_all_timer_sat_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_all_timer_sat_i_1_n_0,
+ Q => sm_reset_all_timer_sat,
+ R => '0'
+ );
+sm_reset_rx_cdr_to_clr_reg: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_plllock_rx_inst_n_2,
+ Q => sm_reset_rx_cdr_to_clr,
+ S => gtwiz_reset_rx_any_sync
+ );
+\sm_reset_rx_cdr_to_ctr[0]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFFFFEF"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_ctr_reg(24),
+ I1 => sm_reset_rx_cdr_to_ctr_reg(21),
+ I2 => \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0\,
+ I3 => \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\,
+ I4 => sm_reset_rx_cdr_to_sat_i_3_n_0,
+ O => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\
+ );
+\sm_reset_rx_cdr_to_ctr[0]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"20000000"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_sat_i_4_n_0,
+ I1 => sm_reset_rx_cdr_to_ctr_reg(1),
+ I2 => sm_reset_rx_cdr_to_ctr_reg(2),
+ I3 => sm_reset_rx_cdr_to_ctr_reg(0),
+ I4 => sm_reset_rx_cdr_to_sat_i_6_n_0,
+ O => \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0\
+ );
+\sm_reset_rx_cdr_to_ctr[0]_i_4\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_ctr_reg(17),
+ I1 => sm_reset_rx_cdr_to_ctr_reg(16),
+ I2 => sm_reset_rx_cdr_to_ctr_reg(9),
+ I3 => sm_reset_rx_cdr_to_ctr_reg(8),
+ O => \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\
+ );
+\sm_reset_rx_cdr_to_ctr[0]_i_5\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_ctr_reg(0),
+ O => \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0\
+ );
+\sm_reset_rx_cdr_to_ctr_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(0),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[0]_i_2\: unisim.vcomponents.CARRY8
+ port map (
+ CI => '0',
+ CI_TOP => '0',
+ CO(7) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0\,
+ CO(6) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1\,
+ CO(5) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2\,
+ CO(4) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3\,
+ CO(3) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4\,
+ CO(2) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5\,
+ CO(1) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6\,
+ CO(0) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7\,
+ DI(7 downto 0) => B"00000001",
+ O(7) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8\,
+ O(6) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9\,
+ O(5) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10\,
+ O(4) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11\,
+ O(3) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12\,
+ O(2) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13\,
+ O(1) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14\,
+ O(0) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15\,
+ S(7 downto 1) => sm_reset_rx_cdr_to_ctr_reg(7 downto 1),
+ S(0) => \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0\
+ );
+\sm_reset_rx_cdr_to_ctr_reg[10]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(10),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[11]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(11),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[12]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(12),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[13]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(13),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[14]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(14),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[15]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(15),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[16]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(16),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[16]_i_1\: unisim.vcomponents.CARRY8
+ port map (
+ CI => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0\,
+ CI_TOP => '0',
+ CO(7) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0\,
+ CO(6) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1\,
+ CO(5) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2\,
+ CO(4) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3\,
+ CO(3) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4\,
+ CO(2) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5\,
+ CO(1) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6\,
+ CO(0) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7\,
+ DI(7 downto 0) => B"00000000",
+ O(7) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8\,
+ O(6) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9\,
+ O(5) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10\,
+ O(4) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11\,
+ O(3) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12\,
+ O(2) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13\,
+ O(1) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14\,
+ O(0) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15\,
+ S(7 downto 0) => sm_reset_rx_cdr_to_ctr_reg(23 downto 16)
+ );
+\sm_reset_rx_cdr_to_ctr_reg[17]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(17),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[18]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(18),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[19]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(19),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(1),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[20]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(20),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[21]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(21),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[22]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(22),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[23]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(23),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[24]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(24),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[24]_i_1\: unisim.vcomponents.CARRY8
+ port map (
+ CI => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0\,
+ CI_TOP => '0',
+ CO(7 downto 1) => \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED\(7 downto 1),
+ CO(0) => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7\,
+ DI(7 downto 0) => B"00000000",
+ O(7 downto 2) => \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED\(7 downto 2),
+ O(1) => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14\,
+ O(0) => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15\,
+ S(7 downto 2) => B"000000",
+ S(1 downto 0) => sm_reset_rx_cdr_to_ctr_reg(25 downto 24)
+ );
+\sm_reset_rx_cdr_to_ctr_reg[25]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(25),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(2),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(3),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(4),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(5),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[6]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(6),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[7]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(7),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[8]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(8),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[8]_i_1\: unisim.vcomponents.CARRY8
+ port map (
+ CI => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0\,
+ CI_TOP => '0',
+ CO(7) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0\,
+ CO(6) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1\,
+ CO(5) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2\,
+ CO(4) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3\,
+ CO(3) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4\,
+ CO(2) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5\,
+ CO(1) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6\,
+ CO(0) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7\,
+ DI(7 downto 0) => B"00000000",
+ O(7) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8\,
+ O(6) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9\,
+ O(5) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10\,
+ O(4) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11\,
+ O(3) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12\,
+ O(2) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13\,
+ O(1) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14\,
+ O(0) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15\,
+ S(7 downto 0) => sm_reset_rx_cdr_to_ctr_reg(15 downto 8)
+ );
+\sm_reset_rx_cdr_to_ctr_reg[9]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(9),
+ R => sm_reset_rx_cdr_to_clr
+ );
+sm_reset_rx_cdr_to_sat_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00F1"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_sat_i_2_n_0,
+ I1 => sm_reset_rx_cdr_to_sat_i_3_n_0,
+ I2 => sm_reset_rx_cdr_to_sat,
+ I3 => sm_reset_rx_cdr_to_clr,
+ O => sm_reset_rx_cdr_to_sat_i_1_n_0
+ );
+sm_reset_rx_cdr_to_sat_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFBFFF"
+ )
+ port map (
+ I0 => \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\,
+ I1 => sm_reset_rx_cdr_to_sat_i_4_n_0,
+ I2 => sm_reset_rx_cdr_to_sat_i_5_n_0,
+ I3 => sm_reset_rx_cdr_to_sat_i_6_n_0,
+ I4 => sm_reset_rx_cdr_to_ctr_reg(21),
+ I5 => sm_reset_rx_cdr_to_ctr_reg(24),
+ O => sm_reset_rx_cdr_to_sat_i_2_n_0
+ );
+sm_reset_rx_cdr_to_sat_i_3: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_sat_i_7_n_0,
+ I1 => sm_reset_rx_cdr_to_ctr_reg(19),
+ I2 => sm_reset_rx_cdr_to_ctr_reg(23),
+ I3 => sm_reset_rx_cdr_to_ctr_reg(25),
+ O => sm_reset_rx_cdr_to_sat_i_3_n_0
+ );
+sm_reset_rx_cdr_to_sat_i_4: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0800"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_ctr_reg(6),
+ I1 => sm_reset_rx_cdr_to_ctr_reg(5),
+ I2 => sm_reset_rx_cdr_to_ctr_reg(4),
+ I3 => sm_reset_rx_cdr_to_ctr_reg(3),
+ O => sm_reset_rx_cdr_to_sat_i_4_n_0
+ );
+sm_reset_rx_cdr_to_sat_i_5: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"40"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_ctr_reg(1),
+ I1 => sm_reset_rx_cdr_to_ctr_reg(2),
+ I2 => sm_reset_rx_cdr_to_ctr_reg(0),
+ O => sm_reset_rx_cdr_to_sat_i_5_n_0
+ );
+sm_reset_rx_cdr_to_sat_i_6: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"2000000000000000"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_ctr_reg(10),
+ I1 => sm_reset_rx_cdr_to_ctr_reg(7),
+ I2 => sm_reset_rx_cdr_to_ctr_reg(12),
+ I3 => sm_reset_rx_cdr_to_ctr_reg(13),
+ I4 => sm_reset_rx_cdr_to_ctr_reg(18),
+ I5 => sm_reset_rx_cdr_to_ctr_reg(15),
+ O => sm_reset_rx_cdr_to_sat_i_6_n_0
+ );
+sm_reset_rx_cdr_to_sat_i_7: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_ctr_reg(14),
+ I1 => sm_reset_rx_cdr_to_ctr_reg(11),
+ I2 => sm_reset_rx_cdr_to_ctr_reg(20),
+ I3 => sm_reset_rx_cdr_to_ctr_reg(22),
+ O => sm_reset_rx_cdr_to_sat_i_7_n_0
+ );
+sm_reset_rx_cdr_to_sat_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_rx_cdr_to_sat_i_1_n_0,
+ Q => sm_reset_rx_cdr_to_sat,
+ R => '0'
+ );
+sm_reset_rx_pll_timer_clr_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFF3000B"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_sat,
+ I1 => sm_reset_rx(0),
+ I2 => sm_reset_rx(1),
+ I3 => sm_reset_rx(2),
+ I4 => sm_reset_rx_pll_timer_clr_reg_n_0,
+ O => sm_reset_rx_pll_timer_clr_i_1_n_0
+ );
+sm_reset_rx_pll_timer_clr_reg: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_rx_pll_timer_clr_i_1_n_0,
+ Q => sm_reset_rx_pll_timer_clr_reg_n_0,
+ S => gtwiz_reset_rx_any_sync
+ );
+\sm_reset_rx_pll_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(0),
+ O => \p_0_in__1\(0)
+ );
+\sm_reset_rx_pll_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(0),
+ I1 => sm_reset_rx_pll_timer_ctr_reg(1),
+ O => \p_0_in__1\(1)
+ );
+\sm_reset_rx_pll_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(0),
+ I1 => sm_reset_rx_pll_timer_ctr_reg(1),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(2),
+ O => \p_0_in__1\(2)
+ );
+\sm_reset_rx_pll_timer_ctr[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"7F80"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(1),
+ I1 => sm_reset_rx_pll_timer_ctr_reg(0),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(2),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(3),
+ O => \p_0_in__1\(3)
+ );
+\sm_reset_rx_pll_timer_ctr[4]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"7FFF8000"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(2),
+ I1 => sm_reset_rx_pll_timer_ctr_reg(0),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(1),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(3),
+ I4 => sm_reset_rx_pll_timer_ctr_reg(4),
+ O => \p_0_in__1\(4)
+ );
+\sm_reset_rx_pll_timer_ctr[5]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"7FFFFFFF80000000"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(3),
+ I1 => sm_reset_rx_pll_timer_ctr_reg(1),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(0),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(2),
+ I4 => sm_reset_rx_pll_timer_ctr_reg(4),
+ I5 => sm_reset_rx_pll_timer_ctr_reg(5),
+ O => \p_0_in__1\(5)
+ );
+\sm_reset_rx_pll_timer_ctr[6]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\,
+ I1 => sm_reset_rx_pll_timer_ctr_reg(6),
+ O => \p_0_in__1\(6)
+ );
+\sm_reset_rx_pll_timer_ctr[7]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\,
+ I1 => sm_reset_rx_pll_timer_ctr_reg(6),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(7),
+ O => \p_0_in__1\(7)
+ );
+\sm_reset_rx_pll_timer_ctr[8]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"7F80"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(6),
+ I1 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\,
+ I2 => sm_reset_rx_pll_timer_ctr_reg(7),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(8),
+ O => \p_0_in__1\(8)
+ );
+\sm_reset_rx_pll_timer_ctr[9]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFFFFEF"
+ )
+ port map (
+ I0 => \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0\,
+ I1 => sm_reset_rx_pll_timer_ctr_reg(8),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(6),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(5),
+ I4 => sm_reset_rx_pll_timer_ctr_reg(9),
+ O => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\
+ );
+\sm_reset_rx_pll_timer_ctr[9]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"7FFF8000"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(7),
+ I1 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\,
+ I2 => sm_reset_rx_pll_timer_ctr_reg(6),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(8),
+ I4 => sm_reset_rx_pll_timer_ctr_reg(9),
+ O => \p_0_in__1\(9)
+ );
+\sm_reset_rx_pll_timer_ctr[9]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFEFFF"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(0),
+ I1 => sm_reset_rx_pll_timer_ctr_reg(2),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(1),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(4),
+ I4 => sm_reset_rx_pll_timer_ctr_reg(3),
+ I5 => sm_reset_rx_pll_timer_ctr_reg(7),
+ O => \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0\
+ );
+\sm_reset_rx_pll_timer_ctr[9]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8000000000000000"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(5),
+ I1 => sm_reset_rx_pll_timer_ctr_reg(3),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(1),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(0),
+ I4 => sm_reset_rx_pll_timer_ctr_reg(2),
+ I5 => sm_reset_rx_pll_timer_ctr_reg(4),
+ O => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\
+ );
+\sm_reset_rx_pll_timer_ctr_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(0),
+ Q => sm_reset_rx_pll_timer_ctr_reg(0),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(1),
+ Q => sm_reset_rx_pll_timer_ctr_reg(1),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(2),
+ Q => sm_reset_rx_pll_timer_ctr_reg(2),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(3),
+ Q => sm_reset_rx_pll_timer_ctr_reg(3),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(4),
+ Q => sm_reset_rx_pll_timer_ctr_reg(4),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(5),
+ Q => sm_reset_rx_pll_timer_ctr_reg(5),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[6]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(6),
+ Q => sm_reset_rx_pll_timer_ctr_reg(6),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[7]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(7),
+ Q => sm_reset_rx_pll_timer_ctr_reg(7),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[8]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(8),
+ Q => sm_reset_rx_pll_timer_ctr_reg(8),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[9]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(9),
+ Q => sm_reset_rx_pll_timer_ctr_reg(9),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+sm_reset_rx_pll_timer_sat_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"0D"
+ )
+ port map (
+ I0 => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ I1 => sm_reset_rx_pll_timer_sat,
+ I2 => sm_reset_rx_pll_timer_clr_reg_n_0,
+ O => sm_reset_rx_pll_timer_sat_i_1_n_0
+ );
+sm_reset_rx_pll_timer_sat_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_rx_pll_timer_sat_i_1_n_0,
+ Q => sm_reset_rx_pll_timer_sat,
+ R => '0'
+ );
+sm_reset_rx_timer_clr_i_4: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => sm_reset_rx_timer_sat,
+ I1 => sm_reset_rx_timer_clr_reg_n_0,
+ O => \sm_reset_rx_timer_clr010_out__0\
+ );
+sm_reset_rx_timer_clr_reg: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_plllock_rx_inst_n_1,
+ Q => sm_reset_rx_timer_clr_reg_n_0,
+ S => gtwiz_reset_rx_any_sync
+ );
+\sm_reset_rx_timer_ctr0_inferred__0/i_\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"7F"
+ )
+ port map (
+ I0 => sm_reset_rx_timer_ctr(2),
+ I1 => sm_reset_rx_timer_ctr(0),
+ I2 => sm_reset_rx_timer_ctr(1),
+ O => \sm_reset_rx_timer_ctr0_inferred__0/i__n_0\
+ );
+\sm_reset_rx_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => sm_reset_rx_timer_ctr(0),
+ O => \sm_reset_rx_timer_ctr[0]_i_1_n_0\
+ );
+\sm_reset_rx_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => sm_reset_rx_timer_ctr(0),
+ I1 => sm_reset_rx_timer_ctr(1),
+ O => \sm_reset_rx_timer_ctr[1]_i_1_n_0\
+ );
+\sm_reset_rx_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => sm_reset_rx_timer_ctr(0),
+ I1 => sm_reset_rx_timer_ctr(1),
+ I2 => sm_reset_rx_timer_ctr(2),
+ O => \sm_reset_rx_timer_ctr[2]_i_1_n_0\
+ );
+\sm_reset_rx_timer_ctr_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_timer_ctr0_inferred__0/i__n_0\,
+ D => \sm_reset_rx_timer_ctr[0]_i_1_n_0\,
+ Q => sm_reset_rx_timer_ctr(0),
+ R => sm_reset_rx_timer_clr_reg_n_0
+ );
+\sm_reset_rx_timer_ctr_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_timer_ctr0_inferred__0/i__n_0\,
+ D => \sm_reset_rx_timer_ctr[1]_i_1_n_0\,
+ Q => sm_reset_rx_timer_ctr(1),
+ R => sm_reset_rx_timer_clr_reg_n_0
+ );
+\sm_reset_rx_timer_ctr_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_timer_ctr0_inferred__0/i__n_0\,
+ D => \sm_reset_rx_timer_ctr[2]_i_1_n_0\,
+ Q => sm_reset_rx_timer_ctr(2),
+ R => sm_reset_rx_timer_clr_reg_n_0
+ );
+sm_reset_rx_timer_sat_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0000FF80"
+ )
+ port map (
+ I0 => sm_reset_rx_timer_ctr(2),
+ I1 => sm_reset_rx_timer_ctr(0),
+ I2 => sm_reset_rx_timer_ctr(1),
+ I3 => sm_reset_rx_timer_sat,
+ I4 => sm_reset_rx_timer_clr_reg_n_0,
+ O => sm_reset_rx_timer_sat_i_1_n_0
+ );
+sm_reset_rx_timer_sat_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_rx_timer_sat_i_1_n_0,
+ Q => sm_reset_rx_timer_sat,
+ R => '0'
+ );
+sm_reset_tx_pll_timer_clr_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFF3000B"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_sat,
+ I1 => sm_reset_tx(0),
+ I2 => sm_reset_tx(1),
+ I3 => sm_reset_tx(2),
+ I4 => sm_reset_tx_pll_timer_clr_reg_n_0,
+ O => sm_reset_tx_pll_timer_clr_i_1_n_0
+ );
+sm_reset_tx_pll_timer_clr_reg: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_tx_pll_timer_clr_i_1_n_0,
+ Q => sm_reset_tx_pll_timer_clr_reg_n_0,
+ S => gtwiz_reset_tx_any_sync
+ );
+\sm_reset_tx_pll_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(0),
+ O => \p_0_in__0\(0)
+ );
+\sm_reset_tx_pll_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(1),
+ O => \p_0_in__0\(1)
+ );
+\sm_reset_tx_pll_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(1),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(2),
+ O => \sm_reset_tx_pll_timer_ctr[2]_i_1_n_0\
+ );
+\sm_reset_tx_pll_timer_ctr[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"7F80"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(1),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(2),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(3),
+ O => \p_0_in__0\(3)
+ );
+\sm_reset_tx_pll_timer_ctr[4]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"7FFF8000"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(2),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(1),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(3),
+ I4 => sm_reset_tx_pll_timer_ctr_reg(4),
+ O => \p_0_in__0\(4)
+ );
+\sm_reset_tx_pll_timer_ctr[5]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"7FFFFFFF80000000"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(3),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(1),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(2),
+ I4 => sm_reset_tx_pll_timer_ctr_reg(4),
+ I5 => sm_reset_tx_pll_timer_ctr_reg(5),
+ O => \p_0_in__0\(5)
+ );
+\sm_reset_tx_pll_timer_ctr[6]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F7FFFFFF08000000"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(4),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(2),
+ I2 => \sm_reset_tx_pll_timer_ctr[6]_i_2_n_0\,
+ I3 => sm_reset_tx_pll_timer_ctr_reg(3),
+ I4 => sm_reset_tx_pll_timer_ctr_reg(5),
+ I5 => sm_reset_tx_pll_timer_ctr_reg(6),
+ O => \p_0_in__0\(6)
+ );
+\sm_reset_tx_pll_timer_ctr[6]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"7"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(1),
+ O => \sm_reset_tx_pll_timer_ctr[6]_i_2_n_0\
+ );
+\sm_reset_tx_pll_timer_ctr[7]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\,
+ I1 => sm_reset_tx_pll_timer_ctr_reg(6),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(7),
+ O => \p_0_in__0\(7)
+ );
+\sm_reset_tx_pll_timer_ctr[8]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"7F80"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(6),
+ I1 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\,
+ I2 => sm_reset_tx_pll_timer_ctr_reg(7),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(8),
+ O => \p_0_in__0\(8)
+ );
+\sm_reset_tx_pll_timer_ctr[9]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFFFFEF"
+ )
+ port map (
+ I0 => \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0\,
+ I1 => sm_reset_tx_pll_timer_ctr_reg(8),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(2),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(6),
+ I4 => sm_reset_tx_pll_timer_ctr_reg(9),
+ O => sel
+ );
+\sm_reset_tx_pll_timer_ctr[9]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"7FFF8000"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(7),
+ I1 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\,
+ I2 => sm_reset_tx_pll_timer_ctr_reg(6),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(8),
+ I4 => sm_reset_tx_pll_timer_ctr_reg(9),
+ O => \p_0_in__0\(9)
+ );
+\sm_reset_tx_pll_timer_ctr[9]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFEFFF"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(3),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(4),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(1),
+ I4 => sm_reset_tx_pll_timer_ctr_reg(5),
+ I5 => sm_reset_tx_pll_timer_ctr_reg(7),
+ O => \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0\
+ );
+\sm_reset_tx_pll_timer_ctr[9]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8000000000000000"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(5),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(3),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(1),
+ I4 => sm_reset_tx_pll_timer_ctr_reg(2),
+ I5 => sm_reset_tx_pll_timer_ctr_reg(4),
+ O => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\
+ );
+\sm_reset_tx_pll_timer_ctr_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(0),
+ Q => sm_reset_tx_pll_timer_ctr_reg(0),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(1),
+ Q => sm_reset_tx_pll_timer_ctr_reg(1),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \sm_reset_tx_pll_timer_ctr[2]_i_1_n_0\,
+ Q => sm_reset_tx_pll_timer_ctr_reg(2),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(3),
+ Q => sm_reset_tx_pll_timer_ctr_reg(3),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(4),
+ Q => sm_reset_tx_pll_timer_ctr_reg(4),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(5),
+ Q => sm_reset_tx_pll_timer_ctr_reg(5),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[6]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(6),
+ Q => sm_reset_tx_pll_timer_ctr_reg(6),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[7]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(7),
+ Q => sm_reset_tx_pll_timer_ctr_reg(7),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[8]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(8),
+ Q => sm_reset_tx_pll_timer_ctr_reg(8),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[9]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(9),
+ Q => sm_reset_tx_pll_timer_ctr_reg(9),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+sm_reset_tx_pll_timer_sat_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"0D"
+ )
+ port map (
+ I0 => sel,
+ I1 => sm_reset_tx_pll_timer_sat,
+ I2 => sm_reset_tx_pll_timer_clr_reg_n_0,
+ O => sm_reset_tx_pll_timer_sat_i_1_n_0
+ );
+sm_reset_tx_pll_timer_sat_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_tx_pll_timer_sat_i_1_n_0,
+ Q => sm_reset_tx_pll_timer_sat,
+ R => '0'
+ );
+sm_reset_tx_timer_clr_reg: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_plllock_tx_inst_n_1,
+ Q => sm_reset_tx_timer_clr_reg_n_0,
+ S => gtwiz_reset_tx_any_sync
+ );
+\sm_reset_tx_timer_ctr0_inferred__0/i_\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"7F"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_ctr(2),
+ I1 => sm_reset_tx_timer_ctr(0),
+ I2 => sm_reset_tx_timer_ctr(1),
+ O => p_0_in
+ );
+\sm_reset_tx_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_ctr(0),
+ O => p_1_in(0)
+ );
+\sm_reset_tx_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_ctr(0),
+ I1 => sm_reset_tx_timer_ctr(1),
+ O => p_1_in(1)
+ );
+\sm_reset_tx_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_ctr(0),
+ I1 => sm_reset_tx_timer_ctr(1),
+ I2 => sm_reset_tx_timer_ctr(2),
+ O => p_1_in(2)
+ );
+\sm_reset_tx_timer_ctr_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => p_0_in,
+ D => p_1_in(0),
+ Q => sm_reset_tx_timer_ctr(0),
+ R => sm_reset_tx_timer_clr_reg_n_0
+ );
+\sm_reset_tx_timer_ctr_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => p_0_in,
+ D => p_1_in(1),
+ Q => sm_reset_tx_timer_ctr(1),
+ R => sm_reset_tx_timer_clr_reg_n_0
+ );
+\sm_reset_tx_timer_ctr_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => p_0_in,
+ D => p_1_in(2),
+ Q => sm_reset_tx_timer_ctr(2),
+ R => sm_reset_tx_timer_clr_reg_n_0
+ );
+sm_reset_tx_timer_sat_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0000FF80"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_ctr(2),
+ I1 => sm_reset_tx_timer_ctr(0),
+ I2 => sm_reset_tx_timer_ctr(1),
+ I3 => sm_reset_tx_timer_sat,
+ I4 => sm_reset_tx_timer_clr_reg_n_0,
+ O => sm_reset_tx_timer_sat_i_1_n_0
+ );
+sm_reset_tx_timer_sat_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_tx_timer_sat_i_1_n_0,
+ Q => sm_reset_tx_timer_sat,
+ R => '0'
+ );
+txuserrdy_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_0,
+ Q => \^gthe3_channel_txuserrdy\(0),
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_gthe3 is
+ port (
+ qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ cplllock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxn_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxp_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtpowergood_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrlock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 79 downto 0 );
+ gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxn_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxp_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslide_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 79 downto 0 );
+ loopback_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_gthe3;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_gthe3 is
+ signal \^cplllock_out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_36\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_37\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_38\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_39\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_48\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_common.gen_common_container[2].gen_enabled_common.gthe3_common_wrapper_inst_n_2\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_common.gen_common_container[2].gen_enabled_common.gthe3_common_wrapper_inst_n_3\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gtpowergood_int__0\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gtrxreset_int\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gttxreset_int\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst_n_11\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst_n_4\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_plllock_rx_int__0\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxcdrlock_int__0\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxprogdivreset_int\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxuserrdy_int\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_txprogdivreset_int\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_txuserrdy_int\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \gen_gtwizard_gthe3.txdlysreset_int\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal \gen_gtwizard_gthe3.txsyncallin_int\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^gtpowergood_out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \^qpll1lock_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^qpll1outclk_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^qpll1outrefclk_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal rst_in0 : STD_LOGIC;
+ signal \^rxcdrlock_out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \^rxresetdone_out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \^txresetdone_out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+begin
+ cplllock_out(3 downto 0) <= \^cplllock_out\(3 downto 0);
+ gtpowergood_out(3 downto 0) <= \^gtpowergood_out\(3 downto 0);
+ qpll1lock_out(0) <= \^qpll1lock_out\(0);
+ qpll1outclk_out(0) <= \^qpll1outclk_out\(0);
+ qpll1outrefclk_out(0) <= \^qpll1outrefclk_out\(0);
+ rxcdrlock_out(3 downto 0) <= \^rxcdrlock_out\(3 downto 0);
+ rxresetdone_out(3 downto 0) <= \^rxresetdone_out\(3 downto 0);
+ txresetdone_out(3 downto 0) <= \^txresetdone_out\(3 downto 0);
+\gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gthe3_channel_wrapper
+ port map (
+ GTHE3_CHANNEL_CPLLPD(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\,
+ GTHE3_CHANNEL_GTRXRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gtrxreset_int\,
+ GTHE3_CHANNEL_GTTXRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gttxreset_int\,
+ GTHE3_CHANNEL_RXPROGDIVRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxprogdivreset_int\,
+ GTHE3_CHANNEL_RXUSERRDY(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxuserrdy_int\,
+ GTHE3_CHANNEL_TXDLYSRESET(0) => \gen_gtwizard_gthe3.txdlysreset_int\(3),
+ GTHE3_CHANNEL_TXPHALIGNDONE(3) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_36\,
+ GTHE3_CHANNEL_TXPHALIGNDONE(2) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_37\,
+ GTHE3_CHANNEL_TXPHALIGNDONE(1) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_38\,
+ GTHE3_CHANNEL_TXPHALIGNDONE(0) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_39\,
+ GTHE3_CHANNEL_TXPROGDIVRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_txprogdivreset_int\,
+ GTHE3_CHANNEL_TXSYNCALLIN(0) => \gen_gtwizard_gthe3.txsyncallin_int\(0),
+ GTHE3_CHANNEL_TXSYNCDONE(0) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_48\,
+ GTHE3_CHANNEL_TXUSERRDY(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_txuserrdy_int\,
+ cplllock_out(3 downto 0) => \^cplllock_out\(3 downto 0),
+ drpclk_in(3 downto 0) => drpclk_in(3 downto 0),
+ gthrxn_in(3 downto 0) => gthrxn_in(3 downto 0),
+ gthrxp_in(3 downto 0) => gthrxp_in(3 downto 0),
+ gthtxn_out(3 downto 0) => gthtxn_out(3 downto 0),
+ gthtxp_out(3 downto 0) => gthtxp_out(3 downto 0),
+ gtpowergood_out(3 downto 0) => \^gtpowergood_out\(3 downto 0),
+ gtrefclk0_in(3 downto 0) => gtrefclk0_in(3 downto 0),
+ gtwiz_userdata_rx_out(79 downto 0) => gtwiz_userdata_rx_out(79 downto 0),
+ gtwiz_userdata_tx_in(79 downto 0) => gtwiz_userdata_tx_in(79 downto 0),
+ loopback_in(11 downto 0) => loopback_in(11 downto 0),
+ qpll0outclk_out(0) => \gen_gtwizard_gthe3.gen_common.gen_common_container[2].gen_enabled_common.gthe3_common_wrapper_inst_n_2\,
+ qpll0outrefclk_out(0) => \gen_gtwizard_gthe3.gen_common.gen_common_container[2].gen_enabled_common.gthe3_common_wrapper_inst_n_3\,
+ qpll1outclk_out(0) => \^qpll1outclk_out\(0),
+ qpll1outrefclk_out(0) => \^qpll1outrefclk_out\(0),
+ rxcdrhold_in(3 downto 0) => rxcdrhold_in(3 downto 0),
+ rxcdrlock_out(3 downto 0) => \^rxcdrlock_out\(3 downto 0),
+ rxoutclk_out(3 downto 0) => rxoutclk_out(3 downto 0),
+ rxpmaresetdone_out(3 downto 0) => rxpmaresetdone_out(3 downto 0),
+ rxpolarity_in(3 downto 0) => rxpolarity_in(3 downto 0),
+ rxresetdone_out(3 downto 0) => \^rxresetdone_out\(3 downto 0),
+ rxslide_in(3 downto 0) => rxslide_in(3 downto 0),
+ rxusrclk2_in(3 downto 0) => rxusrclk2_in(3 downto 0),
+ rxusrclk_in(3 downto 0) => rxusrclk_in(3 downto 0),
+ txoutclk_out(3 downto 0) => txoutclk_out(3 downto 0),
+ txpmaresetdone_out(3 downto 0) => txpmaresetdone_out(3 downto 0),
+ txpolarity_in(3 downto 0) => txpolarity_in(3 downto 0),
+ txresetdone_out(3 downto 0) => \^txresetdone_out\(3 downto 0),
+ txusrclk2_in(3 downto 0) => txusrclk2_in(3 downto 0),
+ txusrclk_in(3 downto 0) => txusrclk_in(3 downto 0)
+ );
+\gen_gtwizard_gthe3.gen_common.gen_common_container[2].gen_enabled_common.gthe3_common_wrapper_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gthe3_common_wrapper
+ port map (
+ \gthe3_common_gen.GTHE3_COMMON_PRIM_INST\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst_n_4\,
+ gtrefclk01_in(0) => gtrefclk01_in(0),
+ qpll0fbclklost_out(0) => qpll0fbclklost_out(0),
+ qpll0lock_out(0) => qpll0lock_out(0),
+ qpll0outclk_out(0) => \gen_gtwizard_gthe3.gen_common.gen_common_container[2].gen_enabled_common.gthe3_common_wrapper_inst_n_2\,
+ qpll0outrefclk_out(0) => \gen_gtwizard_gthe3.gen_common.gen_common_container[2].gen_enabled_common.gthe3_common_wrapper_inst_n_3\,
+ qpll1fbclklost_out(0) => qpll1fbclklost_out(0),
+ qpll1lock_out(0) => \^qpll1lock_out\(0),
+ qpll1outclk_out(0) => \^qpll1outclk_out\(0),
+ qpll1outrefclk_out(0) => \^qpll1outrefclk_out\(0),
+ rst_in0 => rst_in0
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_rxresetdone_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ rxresetdone_out(0) => \^rxresetdone_out\(0)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_txresetdone_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_0
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ txresetdone_out(0) => \^txresetdone_out\(0)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[1].bit_synchronizer_rxresetdone_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_1
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(1),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ rxresetdone_out(0) => \^rxresetdone_out\(1)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[1].bit_synchronizer_txresetdone_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_2
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(1),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ txresetdone_out(0) => \^txresetdone_out\(1)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[2].bit_synchronizer_rxresetdone_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_3
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(2),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ rxresetdone_out(0) => \^rxresetdone_out\(2)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[2].bit_synchronizer_txresetdone_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_4
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(2),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ txresetdone_out(0) => \^txresetdone_out\(2)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[3].bit_synchronizer_rxresetdone_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_5
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(3),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ rxresetdone_out(0) => \^rxresetdone_out\(3)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[3].bit_synchronizer_txresetdone_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_bit_synchronizer_6
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(3),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ txresetdone_out(0) => \^txresetdone_out\(3)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gtpowergood_int\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => \^gtpowergood_out\(1),
+ I1 => \^gtpowergood_out\(0),
+ I2 => \^gtpowergood_out\(3),
+ I3 => \^gtpowergood_out\(2),
+ O => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gtpowergood_int__0\
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gtwiz_reset
+ port map (
+ GTHE3_CHANNEL_CPLLPD(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\,
+ GTHE3_CHANNEL_GTRXRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gtrxreset_int\,
+ GTHE3_CHANNEL_GTTXRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gttxreset_int\,
+ GTHE3_CHANNEL_RXPROGDIVRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxprogdivreset_int\,
+ GTHE3_CHANNEL_RXUSERRDY(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxuserrdy_int\,
+ GTHE3_CHANNEL_TXPROGDIVRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_txprogdivreset_int\,
+ GTHE3_CHANNEL_TXUSERRDY(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_txuserrdy_int\,
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(3 downto 0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(3 downto 0),
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(3 downto 0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(3 downto 0),
+ gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0),
+ gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0),
+ gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0),
+ gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0),
+ gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0),
+ gtwiz_reset_tx_pll_and_datapath_in(0) => gtwiz_reset_tx_pll_and_datapath_in(0),
+ gtwiz_userclk_rx_active_in(0) => gtwiz_userclk_rx_active_in(0),
+ gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0),
+ i_in_meta_reg => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_plllock_rx_int__0\,
+ i_in_meta_reg_0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxcdrlock_int__0\,
+ i_in_out_reg => gtwiz_reset_rx_cdr_stable_out(0),
+ in0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gtpowergood_int__0\,
+ pllreset_tx_out_reg_0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst_n_4\,
+ qpll1lock_out(0) => \^qpll1lock_out\(0),
+ rst_in0 => rst_in0,
+ rst_in_out_reg => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst_n_11\,
+ rxusrclk2_in(0) => rxusrclk2_in(0),
+ txusrclk2_in(0) => txusrclk2_in(0)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_plllock_rx_int\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => \^cplllock_out\(1),
+ I1 => \^cplllock_out\(0),
+ I2 => \^cplllock_out\(3),
+ I3 => \^cplllock_out\(2),
+ O => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_plllock_rx_int__0\
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxcdrlock_int\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => \^rxcdrlock_out\(1),
+ I1 => \^rxcdrlock_out\(0),
+ I2 => \^rxcdrlock_out\(3),
+ I3 => \^rxcdrlock_out\(2),
+ O => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxcdrlock_int__0\
+ );
+\gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_ultrascale_v1_7_18_gtwiz_buffbypass_tx
+ port map (
+ GTHE3_CHANNEL_TXDLYSRESET(0) => \gen_gtwizard_gthe3.txdlysreset_int\(3),
+ GTHE3_CHANNEL_TXPHALIGNDONE(3) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_36\,
+ GTHE3_CHANNEL_TXPHALIGNDONE(2) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_37\,
+ GTHE3_CHANNEL_TXPHALIGNDONE(1) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_38\,
+ GTHE3_CHANNEL_TXPHALIGNDONE(0) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_39\,
+ GTHE3_CHANNEL_TXSYNCALLIN(0) => \gen_gtwizard_gthe3.txsyncallin_int\(0),
+ GTHE3_CHANNEL_TXSYNCDONE(0) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_48\,
+ gtwiz_buffbypass_tx_done_out(0) => gtwiz_buffbypass_tx_done_out(0),
+ gtwiz_buffbypass_tx_error_out(0) => gtwiz_buffbypass_tx_error_out(0),
+ gtwiz_buffbypass_tx_reset_in(0) => gtwiz_buffbypass_tx_reset_in(0),
+ gtwiz_buffbypass_tx_start_user_in(0) => gtwiz_buffbypass_tx_start_user_in(0),
+ rst_in_sync2_reg => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst_n_11\,
+ txusrclk2_in(0) => txusrclk2_in(0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top is
+ port (
+ gtwiz_userclk_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_tx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_tx_usrclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_tx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_tx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_usrclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_rx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_rx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_rx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_done_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_done_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_qpll0lock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_qpll1lock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_qpll0reset_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_qpll1reset_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_gthe3_cpll_cal_txoutclk_period_in : in STD_LOGIC_VECTOR ( 71 downto 0 );
+ gtwiz_gthe3_cpll_cal_cnt_tol_in : in STD_LOGIC_VECTOR ( 71 downto 0 );
+ gtwiz_gthe3_cpll_cal_bufg_ce_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtwiz_gthe4_cpll_cal_txoutclk_period_in : in STD_LOGIC_VECTOR ( 71 downto 0 );
+ gtwiz_gthe4_cpll_cal_cnt_tol_in : in STD_LOGIC_VECTOR ( 71 downto 0 );
+ gtwiz_gthe4_cpll_cal_bufg_ce_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtwiz_gtye4_cpll_cal_txoutclk_period_in : in STD_LOGIC_VECTOR ( 71 downto 0 );
+ gtwiz_gtye4_cpll_cal_cnt_tol_in : in STD_LOGIC_VECTOR ( 71 downto 0 );
+ gtwiz_gtye4_cpll_cal_bufg_ce_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 79 downto 0 );
+ gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 79 downto 0 );
+ bgbypassb_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ bgmonitorenb_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ bgpdb_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ bgrcalovrd_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ bgrcalovrdenb_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpaddr_common_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ drpclk_common_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpdi_common_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ drpen_common_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpwe_common_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtgrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtgrefclk1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtnorthrefclk00_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtnorthrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtnorthrefclk10_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtnorthrefclk11_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtrefclk00_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtrefclk10_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtrefclk11_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtsouthrefclk00_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtsouthrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtsouthrefclk10_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtsouthrefclk11_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ pcierateqpll0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ pcierateqpll1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ pmarsvd0_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ pmarsvd1_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ qpll0clkrsvd0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0clkrsvd1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0fbdiv_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0lockdetclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0locken_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0pd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0refclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ qpll0reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1clkrsvd0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1clkrsvd1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1fbdiv_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1lockdetclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1locken_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1pd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1refclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ qpll1reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpllrsvd1_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ qpllrsvd2_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ qpllrsvd3_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ qpllrsvd4_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ rcalenb_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm0data_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm0reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm0toggle_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm0width_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm1data_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm1reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm1toggle_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm1width_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ tcongpi_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ tconpowerup_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ tconreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ tconrsvdin1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubcfgstreamen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubdo_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubdrdy_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubenable_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubgpi_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubintr_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubiolmbrst_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmbrst_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmcapture_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmdbgrst_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmdbgupdate_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmregen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmshift_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmsysrst_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmtck_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmtdi_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpdo_common_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
+ drprdy_common_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ pmarsvdout0_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ pmarsvdout1_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0refclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1refclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qplldmonitor0_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ qplldmonitor1_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ refclkoutmonitor0_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ refclkoutmonitor1_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxrecclk0_sel_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ rxrecclk1_sel_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ rxrecclk0sel_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxrecclk1sel_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm0finalout_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm0testdata_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm1finalout_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm1testdata_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ tcongpo_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ tconrsvdout0_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ ubdaddr_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ ubden_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ ubdi_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ ubdwe_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmtdo_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ ubrsvdout_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ ubtxuart_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ cdrstepdir_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ cdrstepsq_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ cdrstepsx_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ cfgreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ clkrsvd0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ clkrsvd1_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ cpllfreqlock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ cplllockdetclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ cplllocken_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ cpllpd_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ cpllrefclksel_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ cpllreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ dmonfiforeset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ dmonitorclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ drpaddr_in : in STD_LOGIC_VECTOR ( 35 downto 0 );
+ drpclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ drpdi_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ drpen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ drprst_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpwe_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ elpcaldvorwren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ elpcalpaorwren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ evoddphicaldone_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ evoddphicalstart_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ evoddphidrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ evoddphidwren_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ evoddphixrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ evoddphixwren_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ eyescanmode_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ eyescanreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ eyescantrigger_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ freqos_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtgrefclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxn_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxp_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtnorthrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtnorthrefclk1_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrefclk1_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtresetsel_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrsvd_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ gtrxreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrxresetsel_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtsouthrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtsouthrefclk1_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gttxreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gttxresetsel_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ incpctrl_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtyrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtyrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ loopback_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ looprsvd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ lpbkrxtxseren_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ lpbktxrxseren_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcieeqrxeqadaptdone_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcierstidle_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ pciersttxsyncstart_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcieuserratedone_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcsrsvdin_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ pcsrsvdin2_in : in STD_LOGIC_VECTOR ( 19 downto 0 );
+ pmarsvdin_in : in STD_LOGIC_VECTOR ( 19 downto 0 );
+ qpll0clk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ qpll0freqlock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0refclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ qpll1clk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ qpll1freqlock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1refclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ resetovrd_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rstclkentx_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rx8b10ben_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxafecfoken_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxbufreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrfreqreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrresetrsv_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxchbonden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxchbondi_in : in STD_LOGIC_VECTOR ( 19 downto 0 );
+ rxchbondlevel_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ rxchbondmaster_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxchbondslave_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxckcalreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxckcalstart_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxcommadeten_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfeagcctrl_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxdccforcestart_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfeagchold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfeagcovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfecfokfcnum_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfecfokfen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfecfokfpulse_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfecfokhold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfecfokovren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfekhhold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfekhovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfelfhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfelfovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfelpmreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap10hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap10ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap11hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap11ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap12hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap12ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap13hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap13ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap14hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap14ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap15hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap15ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap2hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap2ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap3hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap3ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap4hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap4ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap5hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap5ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap6hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap6ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap7hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap7ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap8hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap8ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap9hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap9ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfeuthold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfeutovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfevphold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfevpovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfevsen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfexyden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdlybypass_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdlyen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdlyovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdlysreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxelecidlemode_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxeqtraining_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxgearboxslip_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlatclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmgchold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmgcovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmhfhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmhfovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmlfhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmlfklovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmoshold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmosovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxmcommaalignen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxmonitorsel_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxoobreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoscalreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoshold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosintcfg_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ rxosinten_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosinthold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosintovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosintstrobe_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosinttestovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclksel_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ rxpcommaalignen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpcsreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpd_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxphalign_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxphalignen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxphdlypd_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxphdlyreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxphovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpllclksel_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxpmareset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxprbscntreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxprbssel_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ rxprogdivreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxqpien_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxrate_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ rxratemode_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslide_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslipoutclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslippma_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxsyncallin_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxsyncin_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxsyncmode_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxsysclksel_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxtermination_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxuserrdy_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ sigvalidclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ tstin_in : in STD_LOGIC_VECTOR ( 79 downto 0 );
+ tx8b10bbypass_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ tx8b10ben_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txbufdiffctrl_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ txcominit_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txcomsas_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txcomwake_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txctrl0_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ txctrl1_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ txctrl2_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ txdata_in : in STD_LOGIC_VECTOR ( 511 downto 0 );
+ txdataextendrsvd_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ txdccforcestart_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txdccreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txdeemph_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdetectrx_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdiffctrl_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ txdiffpd_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdlybypass_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdlyen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdlyhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdlyovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdlysreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdlyupdown_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txelecidle_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txelforcestart_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txheader_in : in STD_LOGIC_VECTOR ( 23 downto 0 );
+ txinhibit_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txlatclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txlfpstreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txlfpsu2lpexit_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txlfpsu3wake_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txmaincursor_in : in STD_LOGIC_VECTOR ( 27 downto 0 );
+ txmargin_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ txmuxdcdexhold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txmuxdcdorwren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txoneszeros_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txoutclksel_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ txpcsreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpd_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ txpdelecidlemode_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphalign_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphalignen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphdlypd_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphdlyreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphdlytstclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphinit_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpippmen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpippmovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpippmpd_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpippmsel_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpippmstepsize_in : in STD_LOGIC_VECTOR ( 19 downto 0 );
+ txpisopd_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpllclksel_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ txpmareset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpostcursor_in : in STD_LOGIC_VECTOR ( 19 downto 0 );
+ txpostcursorinv_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txprbsforceerr_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txprbssel_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ txprecursor_in : in STD_LOGIC_VECTOR ( 19 downto 0 );
+ txprecursorinv_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txprogdivreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txqpibiasen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txqpistrongpdown_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txqpiweakpup_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txrate_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ txratemode_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txsequence_in : in STD_LOGIC_VECTOR ( 27 downto 0 );
+ txswing_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txsyncallin_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txsyncin_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txsyncmode_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txsysclksel_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ txuserrdy_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ bufgtce_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ bufgtcemask_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ bufgtdiv_out : out STD_LOGIC_VECTOR ( 35 downto 0 );
+ bufgtreset_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ bufgtrstmask_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ cpllfbclklost_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ cplllock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ cpllrefclklost_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ dmonitorout_out : out STD_LOGIC_VECTOR ( 67 downto 0 );
+ dmonitoroutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ drpdo_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ drprdy_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ eyescandataerror_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxn_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxp_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtpowergood_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrefclkmonitor_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtytxn_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtytxp_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ pcierategen3_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcierateidle_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcierateqpllpd_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ pcierateqpllreset_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ pciesynctxsyncdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcieusergen3rdy_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcieuserphystatusrst_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcieuserratestart_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcsrsvdout_out : out STD_LOGIC_VECTOR ( 47 downto 0 );
+ phystatus_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ pinrsrvdas_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ powerpresent_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ resetexception_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxbufstatus_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ rxbyteisaligned_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxbyterealign_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrlock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrphdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxchanbondseq_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxchanisaligned_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxchanrealign_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxchbondo_out : out STD_LOGIC_VECTOR ( 19 downto 0 );
+ rxckcaldone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxclkcorcnt_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxcominitdet_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcommadet_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcomsasdet_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcomwakedet_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxctrl0_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ rxctrl1_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ rxctrl2_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ rxctrl3_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ rxdata_out : out STD_LOGIC_VECTOR ( 511 downto 0 );
+ rxdataextendrsvd_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ rxdatavalid_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxdlysresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxelecidle_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxheader_out : out STD_LOGIC_VECTOR ( 23 downto 0 );
+ rxheadervalid_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxlfpstresetdet_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxlfpsu2lpexitdet_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxlfpsu3wakedet_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxmonitorout_out : out STD_LOGIC_VECTOR ( 27 downto 0 );
+ rxosintdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosintstarted_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosintstrobedone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosintstrobestarted_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclkfabric_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclkpcs_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxphaligndone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxphalignerr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxprbserr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxprbslocked_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxprgdivresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxqpisenn_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxqpisenp_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxratedone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxrecclkout_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxsliderdy_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslipdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslipoutclkrdy_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslippmardy_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxstartofseq_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxstatus_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ rxsyncdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxsyncout_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxvalid_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txbufstatus_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ txcomfinish_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdccdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ txdlysresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txoutclkfabric_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txoutclkpcs_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphaligndone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphinitdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txprgdivresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txqpisenn_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txqpisenp_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txratedone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txsyncdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txsyncout_out : out STD_LOGIC_VECTOR ( 3 downto 0 )
+ );
+ attribute C_CHANNEL_ENABLE : string;
+ attribute C_CHANNEL_ENABLE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100000000";
+ attribute C_COMMON_SCALING_FACTOR : integer;
+ attribute C_COMMON_SCALING_FACTOR of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_CPLL_VCO_FREQUENCY : string;
+ attribute C_CPLL_VCO_FREQUENCY of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "2400.000000";
+ attribute C_ENABLE_COMMON_USRCLK : integer;
+ attribute C_ENABLE_COMMON_USRCLK of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_FORCE_COMMONS : integer;
+ attribute C_FORCE_COMMONS of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_FREERUN_FREQUENCY : string;
+ attribute C_FREERUN_FREQUENCY of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "40.000000";
+ attribute C_GT_REV : integer;
+ attribute C_GT_REV of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 17;
+ attribute C_GT_TYPE : integer;
+ attribute C_GT_TYPE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_INCLUDE_CPLL_CAL : integer;
+ attribute C_INCLUDE_CPLL_CAL of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 2;
+ attribute C_LOCATE_COMMON : integer;
+ attribute C_LOCATE_COMMON of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_LOCATE_IN_SYSTEM_IBERT_CORE : integer;
+ attribute C_LOCATE_IN_SYSTEM_IBERT_CORE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 2;
+ attribute C_LOCATE_RESET_CONTROLLER : integer;
+ attribute C_LOCATE_RESET_CONTROLLER of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER : integer;
+ attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_LOCATE_RX_USER_CLOCKING : integer;
+ attribute C_LOCATE_RX_USER_CLOCKING of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER : integer;
+ attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_LOCATE_TX_USER_CLOCKING : integer;
+ attribute C_LOCATE_TX_USER_CLOCKING of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_LOCATE_USER_DATA_WIDTH_SIZING : integer;
+ attribute C_LOCATE_USER_DATA_WIDTH_SIZING of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_PCIE_CORECLK_FREQ : integer;
+ attribute C_PCIE_CORECLK_FREQ of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 250;
+ attribute C_PCIE_ENABLE : integer;
+ attribute C_PCIE_ENABLE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_RESET_CONTROLLER_INSTANCE_CTRL : integer;
+ attribute C_RESET_CONTROLLER_INSTANCE_CTRL of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_RESET_SEQUENCE_INTERVAL : integer;
+ attribute C_RESET_SEQUENCE_INTERVAL of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_RX_BUFFBYPASS_MODE : integer;
+ attribute C_RX_BUFFBYPASS_MODE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL : integer;
+ attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_RX_BUFFER_MODE : integer;
+ attribute C_RX_BUFFER_MODE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_RX_CB_DISP : string;
+ attribute C_RX_CB_DISP of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "8'b00000000";
+ attribute C_RX_CB_K : string;
+ attribute C_RX_CB_K of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "8'b00000000";
+ attribute C_RX_CB_LEN_SEQ : integer;
+ attribute C_RX_CB_LEN_SEQ of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_RX_CB_MAX_LEVEL : integer;
+ attribute C_RX_CB_MAX_LEVEL of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 2;
+ attribute C_RX_CB_NUM_SEQ : integer;
+ attribute C_RX_CB_NUM_SEQ of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_RX_CB_VAL : string;
+ attribute C_RX_CB_VAL of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_RX_CC_DISP : string;
+ attribute C_RX_CC_DISP of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "8'b00000000";
+ attribute C_RX_CC_ENABLE : integer;
+ attribute C_RX_CC_ENABLE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_RX_CC_K : string;
+ attribute C_RX_CC_K of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "8'b00000000";
+ attribute C_RX_CC_LEN_SEQ : integer;
+ attribute C_RX_CC_LEN_SEQ of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_RX_CC_NUM_SEQ : integer;
+ attribute C_RX_CC_NUM_SEQ of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_RX_CC_PERIODICITY : integer;
+ attribute C_RX_CC_PERIODICITY of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 5000;
+ attribute C_RX_CC_VAL : string;
+ attribute C_RX_CC_VAL of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_RX_COMMA_M_ENABLE : integer;
+ attribute C_RX_COMMA_M_ENABLE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_RX_COMMA_M_VAL : string;
+ attribute C_RX_COMMA_M_VAL of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "10'b1010000011";
+ attribute C_RX_COMMA_P_ENABLE : integer;
+ attribute C_RX_COMMA_P_ENABLE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_RX_COMMA_P_VAL : string;
+ attribute C_RX_COMMA_P_VAL of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "10'b0101111100";
+ attribute C_RX_DATA_DECODING : integer;
+ attribute C_RX_DATA_DECODING of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_RX_ENABLE : integer;
+ attribute C_RX_ENABLE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_RX_INT_DATA_WIDTH : integer;
+ attribute C_RX_INT_DATA_WIDTH of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 20;
+ attribute C_RX_LINE_RATE : string;
+ attribute C_RX_LINE_RATE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "4.800000";
+ attribute C_RX_MASTER_CHANNEL_IDX : integer;
+ attribute C_RX_MASTER_CHANNEL_IDX of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 8;
+ attribute C_RX_OUTCLK_BUFG_GT_DIV : integer;
+ attribute C_RX_OUTCLK_BUFG_GT_DIV of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_RX_OUTCLK_FREQUENCY : string;
+ attribute C_RX_OUTCLK_FREQUENCY of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "240.000000";
+ attribute C_RX_OUTCLK_SOURCE : integer;
+ attribute C_RX_OUTCLK_SOURCE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_RX_PLL_TYPE : integer;
+ attribute C_RX_PLL_TYPE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 2;
+ attribute C_RX_RECCLK_OUTPUT : string;
+ attribute C_RX_RECCLK_OUTPUT of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_RX_REFCLK_FREQUENCY : string;
+ attribute C_RX_REFCLK_FREQUENCY of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "240.000000";
+ attribute C_RX_SLIDE_MODE : integer;
+ attribute C_RX_SLIDE_MODE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 2;
+ attribute C_RX_USER_CLOCKING_CONTENTS : integer;
+ attribute C_RX_USER_CLOCKING_CONTENTS of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_RX_USER_CLOCKING_INSTANCE_CTRL : integer;
+ attribute C_RX_USER_CLOCKING_INSTANCE_CTRL of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer;
+ attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer;
+ attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_RX_USER_CLOCKING_SOURCE : integer;
+ attribute C_RX_USER_CLOCKING_SOURCE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_RX_USER_DATA_WIDTH : integer;
+ attribute C_RX_USER_DATA_WIDTH of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 20;
+ attribute C_RX_USRCLK2_FREQUENCY : string;
+ attribute C_RX_USRCLK2_FREQUENCY of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "240.000000";
+ attribute C_RX_USRCLK_FREQUENCY : string;
+ attribute C_RX_USRCLK_FREQUENCY of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "240.000000";
+ attribute C_SECONDARY_QPLL_ENABLE : integer;
+ attribute C_SECONDARY_QPLL_ENABLE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY : string;
+ attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "257.812500";
+ attribute C_SIM_CPLL_CAL_BYPASS : integer;
+ attribute C_SIM_CPLL_CAL_BYPASS of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_TOTAL_NUM_CHANNELS : integer;
+ attribute C_TOTAL_NUM_CHANNELS of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 4;
+ attribute C_TOTAL_NUM_COMMONS : integer;
+ attribute C_TOTAL_NUM_COMMONS of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_TOTAL_NUM_COMMONS_EXAMPLE : integer;
+ attribute C_TOTAL_NUM_COMMONS_EXAMPLE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_TXPROGDIV_FREQ_ENABLE : integer;
+ attribute C_TXPROGDIV_FREQ_ENABLE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_TXPROGDIV_FREQ_SOURCE : integer;
+ attribute C_TXPROGDIV_FREQ_SOURCE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_TXPROGDIV_FREQ_VAL : string;
+ attribute C_TXPROGDIV_FREQ_VAL of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "240.000000";
+ attribute C_TX_BUFFBYPASS_MODE : integer;
+ attribute C_TX_BUFFBYPASS_MODE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL : integer;
+ attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_TX_BUFFER_MODE : integer;
+ attribute C_TX_BUFFER_MODE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_TX_DATA_ENCODING : integer;
+ attribute C_TX_DATA_ENCODING of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_TX_ENABLE : integer;
+ attribute C_TX_ENABLE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_TX_INT_DATA_WIDTH : integer;
+ attribute C_TX_INT_DATA_WIDTH of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 20;
+ attribute C_TX_LINE_RATE : string;
+ attribute C_TX_LINE_RATE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "4.800000";
+ attribute C_TX_MASTER_CHANNEL_IDX : integer;
+ attribute C_TX_MASTER_CHANNEL_IDX of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 8;
+ attribute C_TX_OUTCLK_BUFG_GT_DIV : integer;
+ attribute C_TX_OUTCLK_BUFG_GT_DIV of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_TX_OUTCLK_FREQUENCY : string;
+ attribute C_TX_OUTCLK_FREQUENCY of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "240.000000";
+ attribute C_TX_OUTCLK_SOURCE : integer;
+ attribute C_TX_OUTCLK_SOURCE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 2;
+ attribute C_TX_PLL_TYPE : integer;
+ attribute C_TX_PLL_TYPE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_TX_REFCLK_FREQUENCY : string;
+ attribute C_TX_REFCLK_FREQUENCY of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "240.000000";
+ attribute C_TX_USER_CLOCKING_CONTENTS : integer;
+ attribute C_TX_USER_CLOCKING_CONTENTS of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_TX_USER_CLOCKING_INSTANCE_CTRL : integer;
+ attribute C_TX_USER_CLOCKING_INSTANCE_CTRL of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer;
+ attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer;
+ attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 1;
+ attribute C_TX_USER_CLOCKING_SOURCE : integer;
+ attribute C_TX_USER_CLOCKING_SOURCE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+ attribute C_TX_USER_DATA_WIDTH : integer;
+ attribute C_TX_USER_DATA_WIDTH of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 20;
+ attribute C_TX_USRCLK2_FREQUENCY : string;
+ attribute C_TX_USRCLK2_FREQUENCY of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "240.000000";
+ attribute C_TX_USRCLK_FREQUENCY : string;
+ attribute C_TX_USRCLK_FREQUENCY of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is "240.000000";
+ attribute C_USER_GTPOWERGOOD_DELAY_EN : integer;
+ attribute C_USER_GTPOWERGOOD_DELAY_EN of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top : entity is 0;
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top is
+ signal \<const0>\ : STD_LOGIC;
+begin
+ bufgtce_out(11) <= \<const0>\;
+ bufgtce_out(10) <= \<const0>\;
+ bufgtce_out(9) <= \<const0>\;
+ bufgtce_out(8) <= \<const0>\;
+ bufgtce_out(7) <= \<const0>\;
+ bufgtce_out(6) <= \<const0>\;
+ bufgtce_out(5) <= \<const0>\;
+ bufgtce_out(4) <= \<const0>\;
+ bufgtce_out(3) <= \<const0>\;
+ bufgtce_out(2) <= \<const0>\;
+ bufgtce_out(1) <= \<const0>\;
+ bufgtce_out(0) <= \<const0>\;
+ bufgtcemask_out(11) <= \<const0>\;
+ bufgtcemask_out(10) <= \<const0>\;
+ bufgtcemask_out(9) <= \<const0>\;
+ bufgtcemask_out(8) <= \<const0>\;
+ bufgtcemask_out(7) <= \<const0>\;
+ bufgtcemask_out(6) <= \<const0>\;
+ bufgtcemask_out(5) <= \<const0>\;
+ bufgtcemask_out(4) <= \<const0>\;
+ bufgtcemask_out(3) <= \<const0>\;
+ bufgtcemask_out(2) <= \<const0>\;
+ bufgtcemask_out(1) <= \<const0>\;
+ bufgtcemask_out(0) <= \<const0>\;
+ bufgtdiv_out(35) <= \<const0>\;
+ bufgtdiv_out(34) <= \<const0>\;
+ bufgtdiv_out(33) <= \<const0>\;
+ bufgtdiv_out(32) <= \<const0>\;
+ bufgtdiv_out(31) <= \<const0>\;
+ bufgtdiv_out(30) <= \<const0>\;
+ bufgtdiv_out(29) <= \<const0>\;
+ bufgtdiv_out(28) <= \<const0>\;
+ bufgtdiv_out(27) <= \<const0>\;
+ bufgtdiv_out(26) <= \<const0>\;
+ bufgtdiv_out(25) <= \<const0>\;
+ bufgtdiv_out(24) <= \<const0>\;
+ bufgtdiv_out(23) <= \<const0>\;
+ bufgtdiv_out(22) <= \<const0>\;
+ bufgtdiv_out(21) <= \<const0>\;
+ bufgtdiv_out(20) <= \<const0>\;
+ bufgtdiv_out(19) <= \<const0>\;
+ bufgtdiv_out(18) <= \<const0>\;
+ bufgtdiv_out(17) <= \<const0>\;
+ bufgtdiv_out(16) <= \<const0>\;
+ bufgtdiv_out(15) <= \<const0>\;
+ bufgtdiv_out(14) <= \<const0>\;
+ bufgtdiv_out(13) <= \<const0>\;
+ bufgtdiv_out(12) <= \<const0>\;
+ bufgtdiv_out(11) <= \<const0>\;
+ bufgtdiv_out(10) <= \<const0>\;
+ bufgtdiv_out(9) <= \<const0>\;
+ bufgtdiv_out(8) <= \<const0>\;
+ bufgtdiv_out(7) <= \<const0>\;
+ bufgtdiv_out(6) <= \<const0>\;
+ bufgtdiv_out(5) <= \<const0>\;
+ bufgtdiv_out(4) <= \<const0>\;
+ bufgtdiv_out(3) <= \<const0>\;
+ bufgtdiv_out(2) <= \<const0>\;
+ bufgtdiv_out(1) <= \<const0>\;
+ bufgtdiv_out(0) <= \<const0>\;
+ bufgtreset_out(11) <= \<const0>\;
+ bufgtreset_out(10) <= \<const0>\;
+ bufgtreset_out(9) <= \<const0>\;
+ bufgtreset_out(8) <= \<const0>\;
+ bufgtreset_out(7) <= \<const0>\;
+ bufgtreset_out(6) <= \<const0>\;
+ bufgtreset_out(5) <= \<const0>\;
+ bufgtreset_out(4) <= \<const0>\;
+ bufgtreset_out(3) <= \<const0>\;
+ bufgtreset_out(2) <= \<const0>\;
+ bufgtreset_out(1) <= \<const0>\;
+ bufgtreset_out(0) <= \<const0>\;
+ bufgtrstmask_out(11) <= \<const0>\;
+ bufgtrstmask_out(10) <= \<const0>\;
+ bufgtrstmask_out(9) <= \<const0>\;
+ bufgtrstmask_out(8) <= \<const0>\;
+ bufgtrstmask_out(7) <= \<const0>\;
+ bufgtrstmask_out(6) <= \<const0>\;
+ bufgtrstmask_out(5) <= \<const0>\;
+ bufgtrstmask_out(4) <= \<const0>\;
+ bufgtrstmask_out(3) <= \<const0>\;
+ bufgtrstmask_out(2) <= \<const0>\;
+ bufgtrstmask_out(1) <= \<const0>\;
+ bufgtrstmask_out(0) <= \<const0>\;
+ cpllfbclklost_out(3) <= \<const0>\;
+ cpllfbclklost_out(2) <= \<const0>\;
+ cpllfbclklost_out(1) <= \<const0>\;
+ cpllfbclklost_out(0) <= \<const0>\;
+ cpllrefclklost_out(3) <= \<const0>\;
+ cpllrefclklost_out(2) <= \<const0>\;
+ cpllrefclklost_out(1) <= \<const0>\;
+ cpllrefclklost_out(0) <= \<const0>\;
+ dmonitorout_out(67) <= \<const0>\;
+ dmonitorout_out(66) <= \<const0>\;
+ dmonitorout_out(65) <= \<const0>\;
+ dmonitorout_out(64) <= \<const0>\;
+ dmonitorout_out(63) <= \<const0>\;
+ dmonitorout_out(62) <= \<const0>\;
+ dmonitorout_out(61) <= \<const0>\;
+ dmonitorout_out(60) <= \<const0>\;
+ dmonitorout_out(59) <= \<const0>\;
+ dmonitorout_out(58) <= \<const0>\;
+ dmonitorout_out(57) <= \<const0>\;
+ dmonitorout_out(56) <= \<const0>\;
+ dmonitorout_out(55) <= \<const0>\;
+ dmonitorout_out(54) <= \<const0>\;
+ dmonitorout_out(53) <= \<const0>\;
+ dmonitorout_out(52) <= \<const0>\;
+ dmonitorout_out(51) <= \<const0>\;
+ dmonitorout_out(50) <= \<const0>\;
+ dmonitorout_out(49) <= \<const0>\;
+ dmonitorout_out(48) <= \<const0>\;
+ dmonitorout_out(47) <= \<const0>\;
+ dmonitorout_out(46) <= \<const0>\;
+ dmonitorout_out(45) <= \<const0>\;
+ dmonitorout_out(44) <= \<const0>\;
+ dmonitorout_out(43) <= \<const0>\;
+ dmonitorout_out(42) <= \<const0>\;
+ dmonitorout_out(41) <= \<const0>\;
+ dmonitorout_out(40) <= \<const0>\;
+ dmonitorout_out(39) <= \<const0>\;
+ dmonitorout_out(38) <= \<const0>\;
+ dmonitorout_out(37) <= \<const0>\;
+ dmonitorout_out(36) <= \<const0>\;
+ dmonitorout_out(35) <= \<const0>\;
+ dmonitorout_out(34) <= \<const0>\;
+ dmonitorout_out(33) <= \<const0>\;
+ dmonitorout_out(32) <= \<const0>\;
+ dmonitorout_out(31) <= \<const0>\;
+ dmonitorout_out(30) <= \<const0>\;
+ dmonitorout_out(29) <= \<const0>\;
+ dmonitorout_out(28) <= \<const0>\;
+ dmonitorout_out(27) <= \<const0>\;
+ dmonitorout_out(26) <= \<const0>\;
+ dmonitorout_out(25) <= \<const0>\;
+ dmonitorout_out(24) <= \<const0>\;
+ dmonitorout_out(23) <= \<const0>\;
+ dmonitorout_out(22) <= \<const0>\;
+ dmonitorout_out(21) <= \<const0>\;
+ dmonitorout_out(20) <= \<const0>\;
+ dmonitorout_out(19) <= \<const0>\;
+ dmonitorout_out(18) <= \<const0>\;
+ dmonitorout_out(17) <= \<const0>\;
+ dmonitorout_out(16) <= \<const0>\;
+ dmonitorout_out(15) <= \<const0>\;
+ dmonitorout_out(14) <= \<const0>\;
+ dmonitorout_out(13) <= \<const0>\;
+ dmonitorout_out(12) <= \<const0>\;
+ dmonitorout_out(11) <= \<const0>\;
+ dmonitorout_out(10) <= \<const0>\;
+ dmonitorout_out(9) <= \<const0>\;
+ dmonitorout_out(8) <= \<const0>\;
+ dmonitorout_out(7) <= \<const0>\;
+ dmonitorout_out(6) <= \<const0>\;
+ dmonitorout_out(5) <= \<const0>\;
+ dmonitorout_out(4) <= \<const0>\;
+ dmonitorout_out(3) <= \<const0>\;
+ dmonitorout_out(2) <= \<const0>\;
+ dmonitorout_out(1) <= \<const0>\;
+ dmonitorout_out(0) <= \<const0>\;
+ dmonitoroutclk_out(0) <= \<const0>\;
+ drpdo_common_out(15) <= \<const0>\;
+ drpdo_common_out(14) <= \<const0>\;
+ drpdo_common_out(13) <= \<const0>\;
+ drpdo_common_out(12) <= \<const0>\;
+ drpdo_common_out(11) <= \<const0>\;
+ drpdo_common_out(10) <= \<const0>\;
+ drpdo_common_out(9) <= \<const0>\;
+ drpdo_common_out(8) <= \<const0>\;
+ drpdo_common_out(7) <= \<const0>\;
+ drpdo_common_out(6) <= \<const0>\;
+ drpdo_common_out(5) <= \<const0>\;
+ drpdo_common_out(4) <= \<const0>\;
+ drpdo_common_out(3) <= \<const0>\;
+ drpdo_common_out(2) <= \<const0>\;
+ drpdo_common_out(1) <= \<const0>\;
+ drpdo_common_out(0) <= \<const0>\;
+ drpdo_out(63) <= \<const0>\;
+ drpdo_out(62) <= \<const0>\;
+ drpdo_out(61) <= \<const0>\;
+ drpdo_out(60) <= \<const0>\;
+ drpdo_out(59) <= \<const0>\;
+ drpdo_out(58) <= \<const0>\;
+ drpdo_out(57) <= \<const0>\;
+ drpdo_out(56) <= \<const0>\;
+ drpdo_out(55) <= \<const0>\;
+ drpdo_out(54) <= \<const0>\;
+ drpdo_out(53) <= \<const0>\;
+ drpdo_out(52) <= \<const0>\;
+ drpdo_out(51) <= \<const0>\;
+ drpdo_out(50) <= \<const0>\;
+ drpdo_out(49) <= \<const0>\;
+ drpdo_out(48) <= \<const0>\;
+ drpdo_out(47) <= \<const0>\;
+ drpdo_out(46) <= \<const0>\;
+ drpdo_out(45) <= \<const0>\;
+ drpdo_out(44) <= \<const0>\;
+ drpdo_out(43) <= \<const0>\;
+ drpdo_out(42) <= \<const0>\;
+ drpdo_out(41) <= \<const0>\;
+ drpdo_out(40) <= \<const0>\;
+ drpdo_out(39) <= \<const0>\;
+ drpdo_out(38) <= \<const0>\;
+ drpdo_out(37) <= \<const0>\;
+ drpdo_out(36) <= \<const0>\;
+ drpdo_out(35) <= \<const0>\;
+ drpdo_out(34) <= \<const0>\;
+ drpdo_out(33) <= \<const0>\;
+ drpdo_out(32) <= \<const0>\;
+ drpdo_out(31) <= \<const0>\;
+ drpdo_out(30) <= \<const0>\;
+ drpdo_out(29) <= \<const0>\;
+ drpdo_out(28) <= \<const0>\;
+ drpdo_out(27) <= \<const0>\;
+ drpdo_out(26) <= \<const0>\;
+ drpdo_out(25) <= \<const0>\;
+ drpdo_out(24) <= \<const0>\;
+ drpdo_out(23) <= \<const0>\;
+ drpdo_out(22) <= \<const0>\;
+ drpdo_out(21) <= \<const0>\;
+ drpdo_out(20) <= \<const0>\;
+ drpdo_out(19) <= \<const0>\;
+ drpdo_out(18) <= \<const0>\;
+ drpdo_out(17) <= \<const0>\;
+ drpdo_out(16) <= \<const0>\;
+ drpdo_out(15) <= \<const0>\;
+ drpdo_out(14) <= \<const0>\;
+ drpdo_out(13) <= \<const0>\;
+ drpdo_out(12) <= \<const0>\;
+ drpdo_out(11) <= \<const0>\;
+ drpdo_out(10) <= \<const0>\;
+ drpdo_out(9) <= \<const0>\;
+ drpdo_out(8) <= \<const0>\;
+ drpdo_out(7) <= \<const0>\;
+ drpdo_out(6) <= \<const0>\;
+ drpdo_out(5) <= \<const0>\;
+ drpdo_out(4) <= \<const0>\;
+ drpdo_out(3) <= \<const0>\;
+ drpdo_out(2) <= \<const0>\;
+ drpdo_out(1) <= \<const0>\;
+ drpdo_out(0) <= \<const0>\;
+ drprdy_common_out(0) <= \<const0>\;
+ drprdy_out(3) <= \<const0>\;
+ drprdy_out(2) <= \<const0>\;
+ drprdy_out(1) <= \<const0>\;
+ drprdy_out(0) <= \<const0>\;
+ eyescandataerror_out(3) <= \<const0>\;
+ eyescandataerror_out(2) <= \<const0>\;
+ eyescandataerror_out(1) <= \<const0>\;
+ eyescandataerror_out(0) <= \<const0>\;
+ gtrefclkmonitor_out(3) <= \<const0>\;
+ gtrefclkmonitor_out(2) <= \<const0>\;
+ gtrefclkmonitor_out(1) <= \<const0>\;
+ gtrefclkmonitor_out(0) <= \<const0>\;
+ gtwiz_buffbypass_rx_done_out(0) <= \<const0>\;
+ gtwiz_buffbypass_rx_error_out(0) <= \<const0>\;
+ gtwiz_reset_qpll0reset_out(0) <= \<const0>\;
+ gtwiz_reset_qpll1reset_out(0) <= \<const0>\;
+ gtwiz_userclk_rx_active_out(0) <= \<const0>\;
+ gtwiz_userclk_rx_srcclk_out(0) <= \<const0>\;
+ gtwiz_userclk_rx_usrclk2_out(0) <= \<const0>\;
+ gtwiz_userclk_rx_usrclk_out(0) <= \<const0>\;
+ gtwiz_userclk_tx_active_out(0) <= \<const0>\;
+ gtwiz_userclk_tx_srcclk_out(0) <= \<const0>\;
+ gtwiz_userclk_tx_usrclk2_out(0) <= \<const0>\;
+ gtwiz_userclk_tx_usrclk_out(0) <= \<const0>\;
+ gtytxn_out(0) <= \<const0>\;
+ gtytxp_out(0) <= \<const0>\;
+ pcierategen3_out(3) <= \<const0>\;
+ pcierategen3_out(2) <= \<const0>\;
+ pcierategen3_out(1) <= \<const0>\;
+ pcierategen3_out(0) <= \<const0>\;
+ pcierateidle_out(3) <= \<const0>\;
+ pcierateidle_out(2) <= \<const0>\;
+ pcierateidle_out(1) <= \<const0>\;
+ pcierateidle_out(0) <= \<const0>\;
+ pcierateqpllpd_out(7) <= \<const0>\;
+ pcierateqpllpd_out(6) <= \<const0>\;
+ pcierateqpllpd_out(5) <= \<const0>\;
+ pcierateqpllpd_out(4) <= \<const0>\;
+ pcierateqpllpd_out(3) <= \<const0>\;
+ pcierateqpllpd_out(2) <= \<const0>\;
+ pcierateqpllpd_out(1) <= \<const0>\;
+ pcierateqpllpd_out(0) <= \<const0>\;
+ pcierateqpllreset_out(7) <= \<const0>\;
+ pcierateqpllreset_out(6) <= \<const0>\;
+ pcierateqpllreset_out(5) <= \<const0>\;
+ pcierateqpllreset_out(4) <= \<const0>\;
+ pcierateqpllreset_out(3) <= \<const0>\;
+ pcierateqpllreset_out(2) <= \<const0>\;
+ pcierateqpllreset_out(1) <= \<const0>\;
+ pcierateqpllreset_out(0) <= \<const0>\;
+ pciesynctxsyncdone_out(3) <= \<const0>\;
+ pciesynctxsyncdone_out(2) <= \<const0>\;
+ pciesynctxsyncdone_out(1) <= \<const0>\;
+ pciesynctxsyncdone_out(0) <= \<const0>\;
+ pcieusergen3rdy_out(3) <= \<const0>\;
+ pcieusergen3rdy_out(2) <= \<const0>\;
+ pcieusergen3rdy_out(1) <= \<const0>\;
+ pcieusergen3rdy_out(0) <= \<const0>\;
+ pcieuserphystatusrst_out(3) <= \<const0>\;
+ pcieuserphystatusrst_out(2) <= \<const0>\;
+ pcieuserphystatusrst_out(1) <= \<const0>\;
+ pcieuserphystatusrst_out(0) <= \<const0>\;
+ pcieuserratestart_out(3) <= \<const0>\;
+ pcieuserratestart_out(2) <= \<const0>\;
+ pcieuserratestart_out(1) <= \<const0>\;
+ pcieuserratestart_out(0) <= \<const0>\;
+ pcsrsvdout_out(47) <= \<const0>\;
+ pcsrsvdout_out(46) <= \<const0>\;
+ pcsrsvdout_out(45) <= \<const0>\;
+ pcsrsvdout_out(44) <= \<const0>\;
+ pcsrsvdout_out(43) <= \<const0>\;
+ pcsrsvdout_out(42) <= \<const0>\;
+ pcsrsvdout_out(41) <= \<const0>\;
+ pcsrsvdout_out(40) <= \<const0>\;
+ pcsrsvdout_out(39) <= \<const0>\;
+ pcsrsvdout_out(38) <= \<const0>\;
+ pcsrsvdout_out(37) <= \<const0>\;
+ pcsrsvdout_out(36) <= \<const0>\;
+ pcsrsvdout_out(35) <= \<const0>\;
+ pcsrsvdout_out(34) <= \<const0>\;
+ pcsrsvdout_out(33) <= \<const0>\;
+ pcsrsvdout_out(32) <= \<const0>\;
+ pcsrsvdout_out(31) <= \<const0>\;
+ pcsrsvdout_out(30) <= \<const0>\;
+ pcsrsvdout_out(29) <= \<const0>\;
+ pcsrsvdout_out(28) <= \<const0>\;
+ pcsrsvdout_out(27) <= \<const0>\;
+ pcsrsvdout_out(26) <= \<const0>\;
+ pcsrsvdout_out(25) <= \<const0>\;
+ pcsrsvdout_out(24) <= \<const0>\;
+ pcsrsvdout_out(23) <= \<const0>\;
+ pcsrsvdout_out(22) <= \<const0>\;
+ pcsrsvdout_out(21) <= \<const0>\;
+ pcsrsvdout_out(20) <= \<const0>\;
+ pcsrsvdout_out(19) <= \<const0>\;
+ pcsrsvdout_out(18) <= \<const0>\;
+ pcsrsvdout_out(17) <= \<const0>\;
+ pcsrsvdout_out(16) <= \<const0>\;
+ pcsrsvdout_out(15) <= \<const0>\;
+ pcsrsvdout_out(14) <= \<const0>\;
+ pcsrsvdout_out(13) <= \<const0>\;
+ pcsrsvdout_out(12) <= \<const0>\;
+ pcsrsvdout_out(11) <= \<const0>\;
+ pcsrsvdout_out(10) <= \<const0>\;
+ pcsrsvdout_out(9) <= \<const0>\;
+ pcsrsvdout_out(8) <= \<const0>\;
+ pcsrsvdout_out(7) <= \<const0>\;
+ pcsrsvdout_out(6) <= \<const0>\;
+ pcsrsvdout_out(5) <= \<const0>\;
+ pcsrsvdout_out(4) <= \<const0>\;
+ pcsrsvdout_out(3) <= \<const0>\;
+ pcsrsvdout_out(2) <= \<const0>\;
+ pcsrsvdout_out(1) <= \<const0>\;
+ pcsrsvdout_out(0) <= \<const0>\;
+ phystatus_out(3) <= \<const0>\;
+ phystatus_out(2) <= \<const0>\;
+ phystatus_out(1) <= \<const0>\;
+ phystatus_out(0) <= \<const0>\;
+ pinrsrvdas_out(31) <= \<const0>\;
+ pinrsrvdas_out(30) <= \<const0>\;
+ pinrsrvdas_out(29) <= \<const0>\;
+ pinrsrvdas_out(28) <= \<const0>\;
+ pinrsrvdas_out(27) <= \<const0>\;
+ pinrsrvdas_out(26) <= \<const0>\;
+ pinrsrvdas_out(25) <= \<const0>\;
+ pinrsrvdas_out(24) <= \<const0>\;
+ pinrsrvdas_out(23) <= \<const0>\;
+ pinrsrvdas_out(22) <= \<const0>\;
+ pinrsrvdas_out(21) <= \<const0>\;
+ pinrsrvdas_out(20) <= \<const0>\;
+ pinrsrvdas_out(19) <= \<const0>\;
+ pinrsrvdas_out(18) <= \<const0>\;
+ pinrsrvdas_out(17) <= \<const0>\;
+ pinrsrvdas_out(16) <= \<const0>\;
+ pinrsrvdas_out(15) <= \<const0>\;
+ pinrsrvdas_out(14) <= \<const0>\;
+ pinrsrvdas_out(13) <= \<const0>\;
+ pinrsrvdas_out(12) <= \<const0>\;
+ pinrsrvdas_out(11) <= \<const0>\;
+ pinrsrvdas_out(10) <= \<const0>\;
+ pinrsrvdas_out(9) <= \<const0>\;
+ pinrsrvdas_out(8) <= \<const0>\;
+ pinrsrvdas_out(7) <= \<const0>\;
+ pinrsrvdas_out(6) <= \<const0>\;
+ pinrsrvdas_out(5) <= \<const0>\;
+ pinrsrvdas_out(4) <= \<const0>\;
+ pinrsrvdas_out(3) <= \<const0>\;
+ pinrsrvdas_out(2) <= \<const0>\;
+ pinrsrvdas_out(1) <= \<const0>\;
+ pinrsrvdas_out(0) <= \<const0>\;
+ pmarsvdout0_out(7) <= \<const0>\;
+ pmarsvdout0_out(6) <= \<const0>\;
+ pmarsvdout0_out(5) <= \<const0>\;
+ pmarsvdout0_out(4) <= \<const0>\;
+ pmarsvdout0_out(3) <= \<const0>\;
+ pmarsvdout0_out(2) <= \<const0>\;
+ pmarsvdout0_out(1) <= \<const0>\;
+ pmarsvdout0_out(0) <= \<const0>\;
+ pmarsvdout1_out(7) <= \<const0>\;
+ pmarsvdout1_out(6) <= \<const0>\;
+ pmarsvdout1_out(5) <= \<const0>\;
+ pmarsvdout1_out(4) <= \<const0>\;
+ pmarsvdout1_out(3) <= \<const0>\;
+ pmarsvdout1_out(2) <= \<const0>\;
+ pmarsvdout1_out(1) <= \<const0>\;
+ pmarsvdout1_out(0) <= \<const0>\;
+ powerpresent_out(0) <= \<const0>\;
+ qpll0outclk_out(0) <= \<const0>\;
+ qpll0outrefclk_out(0) <= \<const0>\;
+ qpll0refclklost_out(0) <= \<const0>\;
+ qpll1refclklost_out(0) <= \<const0>\;
+ qplldmonitor0_out(7) <= \<const0>\;
+ qplldmonitor0_out(6) <= \<const0>\;
+ qplldmonitor0_out(5) <= \<const0>\;
+ qplldmonitor0_out(4) <= \<const0>\;
+ qplldmonitor0_out(3) <= \<const0>\;
+ qplldmonitor0_out(2) <= \<const0>\;
+ qplldmonitor0_out(1) <= \<const0>\;
+ qplldmonitor0_out(0) <= \<const0>\;
+ qplldmonitor1_out(7) <= \<const0>\;
+ qplldmonitor1_out(6) <= \<const0>\;
+ qplldmonitor1_out(5) <= \<const0>\;
+ qplldmonitor1_out(4) <= \<const0>\;
+ qplldmonitor1_out(3) <= \<const0>\;
+ qplldmonitor1_out(2) <= \<const0>\;
+ qplldmonitor1_out(1) <= \<const0>\;
+ qplldmonitor1_out(0) <= \<const0>\;
+ refclkoutmonitor0_out(0) <= \<const0>\;
+ refclkoutmonitor1_out(0) <= \<const0>\;
+ resetexception_out(3) <= \<const0>\;
+ resetexception_out(2) <= \<const0>\;
+ resetexception_out(1) <= \<const0>\;
+ resetexception_out(0) <= \<const0>\;
+ rxbufstatus_out(11) <= \<const0>\;
+ rxbufstatus_out(10) <= \<const0>\;
+ rxbufstatus_out(9) <= \<const0>\;
+ rxbufstatus_out(8) <= \<const0>\;
+ rxbufstatus_out(7) <= \<const0>\;
+ rxbufstatus_out(6) <= \<const0>\;
+ rxbufstatus_out(5) <= \<const0>\;
+ rxbufstatus_out(4) <= \<const0>\;
+ rxbufstatus_out(3) <= \<const0>\;
+ rxbufstatus_out(2) <= \<const0>\;
+ rxbufstatus_out(1) <= \<const0>\;
+ rxbufstatus_out(0) <= \<const0>\;
+ rxbyteisaligned_out(3) <= \<const0>\;
+ rxbyteisaligned_out(2) <= \<const0>\;
+ rxbyteisaligned_out(1) <= \<const0>\;
+ rxbyteisaligned_out(0) <= \<const0>\;
+ rxbyterealign_out(3) <= \<const0>\;
+ rxbyterealign_out(2) <= \<const0>\;
+ rxbyterealign_out(1) <= \<const0>\;
+ rxbyterealign_out(0) <= \<const0>\;
+ rxcdrphdone_out(3) <= \<const0>\;
+ rxcdrphdone_out(2) <= \<const0>\;
+ rxcdrphdone_out(1) <= \<const0>\;
+ rxcdrphdone_out(0) <= \<const0>\;
+ rxchanbondseq_out(3) <= \<const0>\;
+ rxchanbondseq_out(2) <= \<const0>\;
+ rxchanbondseq_out(1) <= \<const0>\;
+ rxchanbondseq_out(0) <= \<const0>\;
+ rxchanisaligned_out(3) <= \<const0>\;
+ rxchanisaligned_out(2) <= \<const0>\;
+ rxchanisaligned_out(1) <= \<const0>\;
+ rxchanisaligned_out(0) <= \<const0>\;
+ rxchanrealign_out(3) <= \<const0>\;
+ rxchanrealign_out(2) <= \<const0>\;
+ rxchanrealign_out(1) <= \<const0>\;
+ rxchanrealign_out(0) <= \<const0>\;
+ rxchbondo_out(19) <= \<const0>\;
+ rxchbondo_out(18) <= \<const0>\;
+ rxchbondo_out(17) <= \<const0>\;
+ rxchbondo_out(16) <= \<const0>\;
+ rxchbondo_out(15) <= \<const0>\;
+ rxchbondo_out(14) <= \<const0>\;
+ rxchbondo_out(13) <= \<const0>\;
+ rxchbondo_out(12) <= \<const0>\;
+ rxchbondo_out(11) <= \<const0>\;
+ rxchbondo_out(10) <= \<const0>\;
+ rxchbondo_out(9) <= \<const0>\;
+ rxchbondo_out(8) <= \<const0>\;
+ rxchbondo_out(7) <= \<const0>\;
+ rxchbondo_out(6) <= \<const0>\;
+ rxchbondo_out(5) <= \<const0>\;
+ rxchbondo_out(4) <= \<const0>\;
+ rxchbondo_out(3) <= \<const0>\;
+ rxchbondo_out(2) <= \<const0>\;
+ rxchbondo_out(1) <= \<const0>\;
+ rxchbondo_out(0) <= \<const0>\;
+ rxckcaldone_out(0) <= \<const0>\;
+ rxclkcorcnt_out(7) <= \<const0>\;
+ rxclkcorcnt_out(6) <= \<const0>\;
+ rxclkcorcnt_out(5) <= \<const0>\;
+ rxclkcorcnt_out(4) <= \<const0>\;
+ rxclkcorcnt_out(3) <= \<const0>\;
+ rxclkcorcnt_out(2) <= \<const0>\;
+ rxclkcorcnt_out(1) <= \<const0>\;
+ rxclkcorcnt_out(0) <= \<const0>\;
+ rxcominitdet_out(3) <= \<const0>\;
+ rxcominitdet_out(2) <= \<const0>\;
+ rxcominitdet_out(1) <= \<const0>\;
+ rxcominitdet_out(0) <= \<const0>\;
+ rxcommadet_out(3) <= \<const0>\;
+ rxcommadet_out(2) <= \<const0>\;
+ rxcommadet_out(1) <= \<const0>\;
+ rxcommadet_out(0) <= \<const0>\;
+ rxcomsasdet_out(3) <= \<const0>\;
+ rxcomsasdet_out(2) <= \<const0>\;
+ rxcomsasdet_out(1) <= \<const0>\;
+ rxcomsasdet_out(0) <= \<const0>\;
+ rxcomwakedet_out(3) <= \<const0>\;
+ rxcomwakedet_out(2) <= \<const0>\;
+ rxcomwakedet_out(1) <= \<const0>\;
+ rxcomwakedet_out(0) <= \<const0>\;
+ rxctrl0_out(63) <= \<const0>\;
+ rxctrl0_out(62) <= \<const0>\;
+ rxctrl0_out(61) <= \<const0>\;
+ rxctrl0_out(60) <= \<const0>\;
+ rxctrl0_out(59) <= \<const0>\;
+ rxctrl0_out(58) <= \<const0>\;
+ rxctrl0_out(57) <= \<const0>\;
+ rxctrl0_out(56) <= \<const0>\;
+ rxctrl0_out(55) <= \<const0>\;
+ rxctrl0_out(54) <= \<const0>\;
+ rxctrl0_out(53) <= \<const0>\;
+ rxctrl0_out(52) <= \<const0>\;
+ rxctrl0_out(51) <= \<const0>\;
+ rxctrl0_out(50) <= \<const0>\;
+ rxctrl0_out(49) <= \<const0>\;
+ rxctrl0_out(48) <= \<const0>\;
+ rxctrl0_out(47) <= \<const0>\;
+ rxctrl0_out(46) <= \<const0>\;
+ rxctrl0_out(45) <= \<const0>\;
+ rxctrl0_out(44) <= \<const0>\;
+ rxctrl0_out(43) <= \<const0>\;
+ rxctrl0_out(42) <= \<const0>\;
+ rxctrl0_out(41) <= \<const0>\;
+ rxctrl0_out(40) <= \<const0>\;
+ rxctrl0_out(39) <= \<const0>\;
+ rxctrl0_out(38) <= \<const0>\;
+ rxctrl0_out(37) <= \<const0>\;
+ rxctrl0_out(36) <= \<const0>\;
+ rxctrl0_out(35) <= \<const0>\;
+ rxctrl0_out(34) <= \<const0>\;
+ rxctrl0_out(33) <= \<const0>\;
+ rxctrl0_out(32) <= \<const0>\;
+ rxctrl0_out(31) <= \<const0>\;
+ rxctrl0_out(30) <= \<const0>\;
+ rxctrl0_out(29) <= \<const0>\;
+ rxctrl0_out(28) <= \<const0>\;
+ rxctrl0_out(27) <= \<const0>\;
+ rxctrl0_out(26) <= \<const0>\;
+ rxctrl0_out(25) <= \<const0>\;
+ rxctrl0_out(24) <= \<const0>\;
+ rxctrl0_out(23) <= \<const0>\;
+ rxctrl0_out(22) <= \<const0>\;
+ rxctrl0_out(21) <= \<const0>\;
+ rxctrl0_out(20) <= \<const0>\;
+ rxctrl0_out(19) <= \<const0>\;
+ rxctrl0_out(18) <= \<const0>\;
+ rxctrl0_out(17) <= \<const0>\;
+ rxctrl0_out(16) <= \<const0>\;
+ rxctrl0_out(15) <= \<const0>\;
+ rxctrl0_out(14) <= \<const0>\;
+ rxctrl0_out(13) <= \<const0>\;
+ rxctrl0_out(12) <= \<const0>\;
+ rxctrl0_out(11) <= \<const0>\;
+ rxctrl0_out(10) <= \<const0>\;
+ rxctrl0_out(9) <= \<const0>\;
+ rxctrl0_out(8) <= \<const0>\;
+ rxctrl0_out(7) <= \<const0>\;
+ rxctrl0_out(6) <= \<const0>\;
+ rxctrl0_out(5) <= \<const0>\;
+ rxctrl0_out(4) <= \<const0>\;
+ rxctrl0_out(3) <= \<const0>\;
+ rxctrl0_out(2) <= \<const0>\;
+ rxctrl0_out(1) <= \<const0>\;
+ rxctrl0_out(0) <= \<const0>\;
+ rxctrl1_out(63) <= \<const0>\;
+ rxctrl1_out(62) <= \<const0>\;
+ rxctrl1_out(61) <= \<const0>\;
+ rxctrl1_out(60) <= \<const0>\;
+ rxctrl1_out(59) <= \<const0>\;
+ rxctrl1_out(58) <= \<const0>\;
+ rxctrl1_out(57) <= \<const0>\;
+ rxctrl1_out(56) <= \<const0>\;
+ rxctrl1_out(55) <= \<const0>\;
+ rxctrl1_out(54) <= \<const0>\;
+ rxctrl1_out(53) <= \<const0>\;
+ rxctrl1_out(52) <= \<const0>\;
+ rxctrl1_out(51) <= \<const0>\;
+ rxctrl1_out(50) <= \<const0>\;
+ rxctrl1_out(49) <= \<const0>\;
+ rxctrl1_out(48) <= \<const0>\;
+ rxctrl1_out(47) <= \<const0>\;
+ rxctrl1_out(46) <= \<const0>\;
+ rxctrl1_out(45) <= \<const0>\;
+ rxctrl1_out(44) <= \<const0>\;
+ rxctrl1_out(43) <= \<const0>\;
+ rxctrl1_out(42) <= \<const0>\;
+ rxctrl1_out(41) <= \<const0>\;
+ rxctrl1_out(40) <= \<const0>\;
+ rxctrl1_out(39) <= \<const0>\;
+ rxctrl1_out(38) <= \<const0>\;
+ rxctrl1_out(37) <= \<const0>\;
+ rxctrl1_out(36) <= \<const0>\;
+ rxctrl1_out(35) <= \<const0>\;
+ rxctrl1_out(34) <= \<const0>\;
+ rxctrl1_out(33) <= \<const0>\;
+ rxctrl1_out(32) <= \<const0>\;
+ rxctrl1_out(31) <= \<const0>\;
+ rxctrl1_out(30) <= \<const0>\;
+ rxctrl1_out(29) <= \<const0>\;
+ rxctrl1_out(28) <= \<const0>\;
+ rxctrl1_out(27) <= \<const0>\;
+ rxctrl1_out(26) <= \<const0>\;
+ rxctrl1_out(25) <= \<const0>\;
+ rxctrl1_out(24) <= \<const0>\;
+ rxctrl1_out(23) <= \<const0>\;
+ rxctrl1_out(22) <= \<const0>\;
+ rxctrl1_out(21) <= \<const0>\;
+ rxctrl1_out(20) <= \<const0>\;
+ rxctrl1_out(19) <= \<const0>\;
+ rxctrl1_out(18) <= \<const0>\;
+ rxctrl1_out(17) <= \<const0>\;
+ rxctrl1_out(16) <= \<const0>\;
+ rxctrl1_out(15) <= \<const0>\;
+ rxctrl1_out(14) <= \<const0>\;
+ rxctrl1_out(13) <= \<const0>\;
+ rxctrl1_out(12) <= \<const0>\;
+ rxctrl1_out(11) <= \<const0>\;
+ rxctrl1_out(10) <= \<const0>\;
+ rxctrl1_out(9) <= \<const0>\;
+ rxctrl1_out(8) <= \<const0>\;
+ rxctrl1_out(7) <= \<const0>\;
+ rxctrl1_out(6) <= \<const0>\;
+ rxctrl1_out(5) <= \<const0>\;
+ rxctrl1_out(4) <= \<const0>\;
+ rxctrl1_out(3) <= \<const0>\;
+ rxctrl1_out(2) <= \<const0>\;
+ rxctrl1_out(1) <= \<const0>\;
+ rxctrl1_out(0) <= \<const0>\;
+ rxctrl2_out(31) <= \<const0>\;
+ rxctrl2_out(30) <= \<const0>\;
+ rxctrl2_out(29) <= \<const0>\;
+ rxctrl2_out(28) <= \<const0>\;
+ rxctrl2_out(27) <= \<const0>\;
+ rxctrl2_out(26) <= \<const0>\;
+ rxctrl2_out(25) <= \<const0>\;
+ rxctrl2_out(24) <= \<const0>\;
+ rxctrl2_out(23) <= \<const0>\;
+ rxctrl2_out(22) <= \<const0>\;
+ rxctrl2_out(21) <= \<const0>\;
+ rxctrl2_out(20) <= \<const0>\;
+ rxctrl2_out(19) <= \<const0>\;
+ rxctrl2_out(18) <= \<const0>\;
+ rxctrl2_out(17) <= \<const0>\;
+ rxctrl2_out(16) <= \<const0>\;
+ rxctrl2_out(15) <= \<const0>\;
+ rxctrl2_out(14) <= \<const0>\;
+ rxctrl2_out(13) <= \<const0>\;
+ rxctrl2_out(12) <= \<const0>\;
+ rxctrl2_out(11) <= \<const0>\;
+ rxctrl2_out(10) <= \<const0>\;
+ rxctrl2_out(9) <= \<const0>\;
+ rxctrl2_out(8) <= \<const0>\;
+ rxctrl2_out(7) <= \<const0>\;
+ rxctrl2_out(6) <= \<const0>\;
+ rxctrl2_out(5) <= \<const0>\;
+ rxctrl2_out(4) <= \<const0>\;
+ rxctrl2_out(3) <= \<const0>\;
+ rxctrl2_out(2) <= \<const0>\;
+ rxctrl2_out(1) <= \<const0>\;
+ rxctrl2_out(0) <= \<const0>\;
+ rxctrl3_out(31) <= \<const0>\;
+ rxctrl3_out(30) <= \<const0>\;
+ rxctrl3_out(29) <= \<const0>\;
+ rxctrl3_out(28) <= \<const0>\;
+ rxctrl3_out(27) <= \<const0>\;
+ rxctrl3_out(26) <= \<const0>\;
+ rxctrl3_out(25) <= \<const0>\;
+ rxctrl3_out(24) <= \<const0>\;
+ rxctrl3_out(23) <= \<const0>\;
+ rxctrl3_out(22) <= \<const0>\;
+ rxctrl3_out(21) <= \<const0>\;
+ rxctrl3_out(20) <= \<const0>\;
+ rxctrl3_out(19) <= \<const0>\;
+ rxctrl3_out(18) <= \<const0>\;
+ rxctrl3_out(17) <= \<const0>\;
+ rxctrl3_out(16) <= \<const0>\;
+ rxctrl3_out(15) <= \<const0>\;
+ rxctrl3_out(14) <= \<const0>\;
+ rxctrl3_out(13) <= \<const0>\;
+ rxctrl3_out(12) <= \<const0>\;
+ rxctrl3_out(11) <= \<const0>\;
+ rxctrl3_out(10) <= \<const0>\;
+ rxctrl3_out(9) <= \<const0>\;
+ rxctrl3_out(8) <= \<const0>\;
+ rxctrl3_out(7) <= \<const0>\;
+ rxctrl3_out(6) <= \<const0>\;
+ rxctrl3_out(5) <= \<const0>\;
+ rxctrl3_out(4) <= \<const0>\;
+ rxctrl3_out(3) <= \<const0>\;
+ rxctrl3_out(2) <= \<const0>\;
+ rxctrl3_out(1) <= \<const0>\;
+ rxctrl3_out(0) <= \<const0>\;
+ rxdata_out(511) <= \<const0>\;
+ rxdata_out(510) <= \<const0>\;
+ rxdata_out(509) <= \<const0>\;
+ rxdata_out(508) <= \<const0>\;
+ rxdata_out(507) <= \<const0>\;
+ rxdata_out(506) <= \<const0>\;
+ rxdata_out(505) <= \<const0>\;
+ rxdata_out(504) <= \<const0>\;
+ rxdata_out(503) <= \<const0>\;
+ rxdata_out(502) <= \<const0>\;
+ rxdata_out(501) <= \<const0>\;
+ rxdata_out(500) <= \<const0>\;
+ rxdata_out(499) <= \<const0>\;
+ rxdata_out(498) <= \<const0>\;
+ rxdata_out(497) <= \<const0>\;
+ rxdata_out(496) <= \<const0>\;
+ rxdata_out(495) <= \<const0>\;
+ rxdata_out(494) <= \<const0>\;
+ rxdata_out(493) <= \<const0>\;
+ rxdata_out(492) <= \<const0>\;
+ rxdata_out(491) <= \<const0>\;
+ rxdata_out(490) <= \<const0>\;
+ rxdata_out(489) <= \<const0>\;
+ rxdata_out(488) <= \<const0>\;
+ rxdata_out(487) <= \<const0>\;
+ rxdata_out(486) <= \<const0>\;
+ rxdata_out(485) <= \<const0>\;
+ rxdata_out(484) <= \<const0>\;
+ rxdata_out(483) <= \<const0>\;
+ rxdata_out(482) <= \<const0>\;
+ rxdata_out(481) <= \<const0>\;
+ rxdata_out(480) <= \<const0>\;
+ rxdata_out(479) <= \<const0>\;
+ rxdata_out(478) <= \<const0>\;
+ rxdata_out(477) <= \<const0>\;
+ rxdata_out(476) <= \<const0>\;
+ rxdata_out(475) <= \<const0>\;
+ rxdata_out(474) <= \<const0>\;
+ rxdata_out(473) <= \<const0>\;
+ rxdata_out(472) <= \<const0>\;
+ rxdata_out(471) <= \<const0>\;
+ rxdata_out(470) <= \<const0>\;
+ rxdata_out(469) <= \<const0>\;
+ rxdata_out(468) <= \<const0>\;
+ rxdata_out(467) <= \<const0>\;
+ rxdata_out(466) <= \<const0>\;
+ rxdata_out(465) <= \<const0>\;
+ rxdata_out(464) <= \<const0>\;
+ rxdata_out(463) <= \<const0>\;
+ rxdata_out(462) <= \<const0>\;
+ rxdata_out(461) <= \<const0>\;
+ rxdata_out(460) <= \<const0>\;
+ rxdata_out(459) <= \<const0>\;
+ rxdata_out(458) <= \<const0>\;
+ rxdata_out(457) <= \<const0>\;
+ rxdata_out(456) <= \<const0>\;
+ rxdata_out(455) <= \<const0>\;
+ rxdata_out(454) <= \<const0>\;
+ rxdata_out(453) <= \<const0>\;
+ rxdata_out(452) <= \<const0>\;
+ rxdata_out(451) <= \<const0>\;
+ rxdata_out(450) <= \<const0>\;
+ rxdata_out(449) <= \<const0>\;
+ rxdata_out(448) <= \<const0>\;
+ rxdata_out(447) <= \<const0>\;
+ rxdata_out(446) <= \<const0>\;
+ rxdata_out(445) <= \<const0>\;
+ rxdata_out(444) <= \<const0>\;
+ rxdata_out(443) <= \<const0>\;
+ rxdata_out(442) <= \<const0>\;
+ rxdata_out(441) <= \<const0>\;
+ rxdata_out(440) <= \<const0>\;
+ rxdata_out(439) <= \<const0>\;
+ rxdata_out(438) <= \<const0>\;
+ rxdata_out(437) <= \<const0>\;
+ rxdata_out(436) <= \<const0>\;
+ rxdata_out(435) <= \<const0>\;
+ rxdata_out(434) <= \<const0>\;
+ rxdata_out(433) <= \<const0>\;
+ rxdata_out(432) <= \<const0>\;
+ rxdata_out(431) <= \<const0>\;
+ rxdata_out(430) <= \<const0>\;
+ rxdata_out(429) <= \<const0>\;
+ rxdata_out(428) <= \<const0>\;
+ rxdata_out(427) <= \<const0>\;
+ rxdata_out(426) <= \<const0>\;
+ rxdata_out(425) <= \<const0>\;
+ rxdata_out(424) <= \<const0>\;
+ rxdata_out(423) <= \<const0>\;
+ rxdata_out(422) <= \<const0>\;
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+ rxdata_out(420) <= \<const0>\;
+ rxdata_out(419) <= \<const0>\;
+ rxdata_out(418) <= \<const0>\;
+ rxdata_out(417) <= \<const0>\;
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+ rxdata_out(415) <= \<const0>\;
+ rxdata_out(414) <= \<const0>\;
+ rxdata_out(413) <= \<const0>\;
+ rxdata_out(412) <= \<const0>\;
+ rxdata_out(411) <= \<const0>\;
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+ rxdata_out(408) <= \<const0>\;
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+ rxdata_out(406) <= \<const0>\;
+ rxdata_out(405) <= \<const0>\;
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+ rxdata_out(403) <= \<const0>\;
+ rxdata_out(402) <= \<const0>\;
+ rxdata_out(401) <= \<const0>\;
+ rxdata_out(400) <= \<const0>\;
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+ rxdata_out(397) <= \<const0>\;
+ rxdata_out(396) <= \<const0>\;
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+ rxdata_out(394) <= \<const0>\;
+ rxdata_out(393) <= \<const0>\;
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+ rxdata_out(390) <= \<const0>\;
+ rxdata_out(389) <= \<const0>\;
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+ rxdata_out(386) <= \<const0>\;
+ rxdata_out(385) <= \<const0>\;
+ rxdata_out(384) <= \<const0>\;
+ rxdata_out(383) <= \<const0>\;
+ rxdata_out(382) <= \<const0>\;
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+ rxdata_out(380) <= \<const0>\;
+ rxdata_out(379) <= \<const0>\;
+ rxdata_out(378) <= \<const0>\;
+ rxdata_out(377) <= \<const0>\;
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+ rxdata_out(374) <= \<const0>\;
+ rxdata_out(373) <= \<const0>\;
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+ rxdata_out(368) <= \<const0>\;
+ rxdata_out(367) <= \<const0>\;
+ rxdata_out(366) <= \<const0>\;
+ rxdata_out(365) <= \<const0>\;
+ rxdata_out(364) <= \<const0>\;
+ rxdata_out(363) <= \<const0>\;
+ rxdata_out(362) <= \<const0>\;
+ rxdata_out(361) <= \<const0>\;
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+ rxdata_out(358) <= \<const0>\;
+ rxdata_out(357) <= \<const0>\;
+ rxdata_out(356) <= \<const0>\;
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+ rxdata_out(352) <= \<const0>\;
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+ rxdata_out(350) <= \<const0>\;
+ rxdata_out(349) <= \<const0>\;
+ rxdata_out(348) <= \<const0>\;
+ rxdata_out(347) <= \<const0>\;
+ rxdata_out(346) <= \<const0>\;
+ rxdata_out(345) <= \<const0>\;
+ rxdata_out(344) <= \<const0>\;
+ rxdata_out(343) <= \<const0>\;
+ rxdata_out(342) <= \<const0>\;
+ rxdata_out(341) <= \<const0>\;
+ rxdata_out(340) <= \<const0>\;
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+ rxdata_out(338) <= \<const0>\;
+ rxdata_out(337) <= \<const0>\;
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+ rxdata_out(335) <= \<const0>\;
+ rxdata_out(334) <= \<const0>\;
+ rxdata_out(333) <= \<const0>\;
+ rxdata_out(332) <= \<const0>\;
+ rxdata_out(331) <= \<const0>\;
+ rxdata_out(330) <= \<const0>\;
+ rxdata_out(329) <= \<const0>\;
+ rxdata_out(328) <= \<const0>\;
+ rxdata_out(327) <= \<const0>\;
+ rxdata_out(326) <= \<const0>\;
+ rxdata_out(325) <= \<const0>\;
+ rxdata_out(324) <= \<const0>\;
+ rxdata_out(323) <= \<const0>\;
+ rxdata_out(322) <= \<const0>\;
+ rxdata_out(321) <= \<const0>\;
+ rxdata_out(320) <= \<const0>\;
+ rxdata_out(319) <= \<const0>\;
+ rxdata_out(318) <= \<const0>\;
+ rxdata_out(317) <= \<const0>\;
+ rxdata_out(316) <= \<const0>\;
+ rxdata_out(315) <= \<const0>\;
+ rxdata_out(314) <= \<const0>\;
+ rxdata_out(313) <= \<const0>\;
+ rxdata_out(312) <= \<const0>\;
+ rxdata_out(311) <= \<const0>\;
+ rxdata_out(310) <= \<const0>\;
+ rxdata_out(309) <= \<const0>\;
+ rxdata_out(308) <= \<const0>\;
+ rxdata_out(307) <= \<const0>\;
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+ rxdata_out(305) <= \<const0>\;
+ rxdata_out(304) <= \<const0>\;
+ rxdata_out(303) <= \<const0>\;
+ rxdata_out(302) <= \<const0>\;
+ rxdata_out(301) <= \<const0>\;
+ rxdata_out(300) <= \<const0>\;
+ rxdata_out(299) <= \<const0>\;
+ rxdata_out(298) <= \<const0>\;
+ rxdata_out(297) <= \<const0>\;
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+ rxdata_out(294) <= \<const0>\;
+ rxdata_out(293) <= \<const0>\;
+ rxdata_out(292) <= \<const0>\;
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+ rxdata_out(286) <= \<const0>\;
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+ rxdata_out(269) <= \<const0>\;
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+ rxdata_out(264) <= \<const0>\;
+ rxdata_out(263) <= \<const0>\;
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+ rxdata_out(259) <= \<const0>\;
+ rxdata_out(258) <= \<const0>\;
+ rxdata_out(257) <= \<const0>\;
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+ rxdata_out(254) <= \<const0>\;
+ rxdata_out(253) <= \<const0>\;
+ rxdata_out(252) <= \<const0>\;
+ rxdata_out(251) <= \<const0>\;
+ rxdata_out(250) <= \<const0>\;
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+ rxdata_out(248) <= \<const0>\;
+ rxdata_out(247) <= \<const0>\;
+ rxdata_out(246) <= \<const0>\;
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+ rxdata_out(243) <= \<const0>\;
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+ rxdata_out(237) <= \<const0>\;
+ rxdata_out(236) <= \<const0>\;
+ rxdata_out(235) <= \<const0>\;
+ rxdata_out(234) <= \<const0>\;
+ rxdata_out(233) <= \<const0>\;
+ rxdata_out(232) <= \<const0>\;
+ rxdata_out(231) <= \<const0>\;
+ rxdata_out(230) <= \<const0>\;
+ rxdata_out(229) <= \<const0>\;
+ rxdata_out(228) <= \<const0>\;
+ rxdata_out(227) <= \<const0>\;
+ rxdata_out(226) <= \<const0>\;
+ rxdata_out(225) <= \<const0>\;
+ rxdata_out(224) <= \<const0>\;
+ rxdata_out(223) <= \<const0>\;
+ rxdata_out(222) <= \<const0>\;
+ rxdata_out(221) <= \<const0>\;
+ rxdata_out(220) <= \<const0>\;
+ rxdata_out(219) <= \<const0>\;
+ rxdata_out(218) <= \<const0>\;
+ rxdata_out(217) <= \<const0>\;
+ rxdata_out(216) <= \<const0>\;
+ rxdata_out(215) <= \<const0>\;
+ rxdata_out(214) <= \<const0>\;
+ rxdata_out(213) <= \<const0>\;
+ rxdata_out(212) <= \<const0>\;
+ rxdata_out(211) <= \<const0>\;
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+ rxdata_out(34) <= \<const0>\;
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+ rxdata_out(30) <= \<const0>\;
+ rxdata_out(29) <= \<const0>\;
+ rxdata_out(28) <= \<const0>\;
+ rxdata_out(27) <= \<const0>\;
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+ rxdata_out(25) <= \<const0>\;
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+ rxdata_out(23) <= \<const0>\;
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+ rxdata_out(18) <= \<const0>\;
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+ rxdata_out(16) <= \<const0>\;
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+ rxdata_out(14) <= \<const0>\;
+ rxdata_out(13) <= \<const0>\;
+ rxdata_out(12) <= \<const0>\;
+ rxdata_out(11) <= \<const0>\;
+ rxdata_out(10) <= \<const0>\;
+ rxdata_out(9) <= \<const0>\;
+ rxdata_out(8) <= \<const0>\;
+ rxdata_out(7) <= \<const0>\;
+ rxdata_out(6) <= \<const0>\;
+ rxdata_out(5) <= \<const0>\;
+ rxdata_out(4) <= \<const0>\;
+ rxdata_out(3) <= \<const0>\;
+ rxdata_out(2) <= \<const0>\;
+ rxdata_out(1) <= \<const0>\;
+ rxdata_out(0) <= \<const0>\;
+ rxdataextendrsvd_out(31) <= \<const0>\;
+ rxdataextendrsvd_out(30) <= \<const0>\;
+ rxdataextendrsvd_out(29) <= \<const0>\;
+ rxdataextendrsvd_out(28) <= \<const0>\;
+ rxdataextendrsvd_out(27) <= \<const0>\;
+ rxdataextendrsvd_out(26) <= \<const0>\;
+ rxdataextendrsvd_out(25) <= \<const0>\;
+ rxdataextendrsvd_out(24) <= \<const0>\;
+ rxdataextendrsvd_out(23) <= \<const0>\;
+ rxdataextendrsvd_out(22) <= \<const0>\;
+ rxdataextendrsvd_out(21) <= \<const0>\;
+ rxdataextendrsvd_out(20) <= \<const0>\;
+ rxdataextendrsvd_out(19) <= \<const0>\;
+ rxdataextendrsvd_out(18) <= \<const0>\;
+ rxdataextendrsvd_out(17) <= \<const0>\;
+ rxdataextendrsvd_out(16) <= \<const0>\;
+ rxdataextendrsvd_out(15) <= \<const0>\;
+ rxdataextendrsvd_out(14) <= \<const0>\;
+ rxdataextendrsvd_out(13) <= \<const0>\;
+ rxdataextendrsvd_out(12) <= \<const0>\;
+ rxdataextendrsvd_out(11) <= \<const0>\;
+ rxdataextendrsvd_out(10) <= \<const0>\;
+ rxdataextendrsvd_out(9) <= \<const0>\;
+ rxdataextendrsvd_out(8) <= \<const0>\;
+ rxdataextendrsvd_out(7) <= \<const0>\;
+ rxdataextendrsvd_out(6) <= \<const0>\;
+ rxdataextendrsvd_out(5) <= \<const0>\;
+ rxdataextendrsvd_out(4) <= \<const0>\;
+ rxdataextendrsvd_out(3) <= \<const0>\;
+ rxdataextendrsvd_out(2) <= \<const0>\;
+ rxdataextendrsvd_out(1) <= \<const0>\;
+ rxdataextendrsvd_out(0) <= \<const0>\;
+ rxdatavalid_out(7) <= \<const0>\;
+ rxdatavalid_out(6) <= \<const0>\;
+ rxdatavalid_out(5) <= \<const0>\;
+ rxdatavalid_out(4) <= \<const0>\;
+ rxdatavalid_out(3) <= \<const0>\;
+ rxdatavalid_out(2) <= \<const0>\;
+ rxdatavalid_out(1) <= \<const0>\;
+ rxdatavalid_out(0) <= \<const0>\;
+ rxdlysresetdone_out(3) <= \<const0>\;
+ rxdlysresetdone_out(2) <= \<const0>\;
+ rxdlysresetdone_out(1) <= \<const0>\;
+ rxdlysresetdone_out(0) <= \<const0>\;
+ rxelecidle_out(3) <= \<const0>\;
+ rxelecidle_out(2) <= \<const0>\;
+ rxelecidle_out(1) <= \<const0>\;
+ rxelecidle_out(0) <= \<const0>\;
+ rxheader_out(23) <= \<const0>\;
+ rxheader_out(22) <= \<const0>\;
+ rxheader_out(21) <= \<const0>\;
+ rxheader_out(20) <= \<const0>\;
+ rxheader_out(19) <= \<const0>\;
+ rxheader_out(18) <= \<const0>\;
+ rxheader_out(17) <= \<const0>\;
+ rxheader_out(16) <= \<const0>\;
+ rxheader_out(15) <= \<const0>\;
+ rxheader_out(14) <= \<const0>\;
+ rxheader_out(13) <= \<const0>\;
+ rxheader_out(12) <= \<const0>\;
+ rxheader_out(11) <= \<const0>\;
+ rxheader_out(10) <= \<const0>\;
+ rxheader_out(9) <= \<const0>\;
+ rxheader_out(8) <= \<const0>\;
+ rxheader_out(7) <= \<const0>\;
+ rxheader_out(6) <= \<const0>\;
+ rxheader_out(5) <= \<const0>\;
+ rxheader_out(4) <= \<const0>\;
+ rxheader_out(3) <= \<const0>\;
+ rxheader_out(2) <= \<const0>\;
+ rxheader_out(1) <= \<const0>\;
+ rxheader_out(0) <= \<const0>\;
+ rxheadervalid_out(7) <= \<const0>\;
+ rxheadervalid_out(6) <= \<const0>\;
+ rxheadervalid_out(5) <= \<const0>\;
+ rxheadervalid_out(4) <= \<const0>\;
+ rxheadervalid_out(3) <= \<const0>\;
+ rxheadervalid_out(2) <= \<const0>\;
+ rxheadervalid_out(1) <= \<const0>\;
+ rxheadervalid_out(0) <= \<const0>\;
+ rxlfpstresetdet_out(0) <= \<const0>\;
+ rxlfpsu2lpexitdet_out(0) <= \<const0>\;
+ rxlfpsu3wakedet_out(0) <= \<const0>\;
+ rxmonitorout_out(27) <= \<const0>\;
+ rxmonitorout_out(26) <= \<const0>\;
+ rxmonitorout_out(25) <= \<const0>\;
+ rxmonitorout_out(24) <= \<const0>\;
+ rxmonitorout_out(23) <= \<const0>\;
+ rxmonitorout_out(22) <= \<const0>\;
+ rxmonitorout_out(21) <= \<const0>\;
+ rxmonitorout_out(20) <= \<const0>\;
+ rxmonitorout_out(19) <= \<const0>\;
+ rxmonitorout_out(18) <= \<const0>\;
+ rxmonitorout_out(17) <= \<const0>\;
+ rxmonitorout_out(16) <= \<const0>\;
+ rxmonitorout_out(15) <= \<const0>\;
+ rxmonitorout_out(14) <= \<const0>\;
+ rxmonitorout_out(13) <= \<const0>\;
+ rxmonitorout_out(12) <= \<const0>\;
+ rxmonitorout_out(11) <= \<const0>\;
+ rxmonitorout_out(10) <= \<const0>\;
+ rxmonitorout_out(9) <= \<const0>\;
+ rxmonitorout_out(8) <= \<const0>\;
+ rxmonitorout_out(7) <= \<const0>\;
+ rxmonitorout_out(6) <= \<const0>\;
+ rxmonitorout_out(5) <= \<const0>\;
+ rxmonitorout_out(4) <= \<const0>\;
+ rxmonitorout_out(3) <= \<const0>\;
+ rxmonitorout_out(2) <= \<const0>\;
+ rxmonitorout_out(1) <= \<const0>\;
+ rxmonitorout_out(0) <= \<const0>\;
+ rxosintdone_out(3) <= \<const0>\;
+ rxosintdone_out(2) <= \<const0>\;
+ rxosintdone_out(1) <= \<const0>\;
+ rxosintdone_out(0) <= \<const0>\;
+ rxosintstarted_out(3) <= \<const0>\;
+ rxosintstarted_out(2) <= \<const0>\;
+ rxosintstarted_out(1) <= \<const0>\;
+ rxosintstarted_out(0) <= \<const0>\;
+ rxosintstrobedone_out(3) <= \<const0>\;
+ rxosintstrobedone_out(2) <= \<const0>\;
+ rxosintstrobedone_out(1) <= \<const0>\;
+ rxosintstrobedone_out(0) <= \<const0>\;
+ rxosintstrobestarted_out(3) <= \<const0>\;
+ rxosintstrobestarted_out(2) <= \<const0>\;
+ rxosintstrobestarted_out(1) <= \<const0>\;
+ rxosintstrobestarted_out(0) <= \<const0>\;
+ rxoutclkfabric_out(3) <= \<const0>\;
+ rxoutclkfabric_out(2) <= \<const0>\;
+ rxoutclkfabric_out(1) <= \<const0>\;
+ rxoutclkfabric_out(0) <= \<const0>\;
+ rxoutclkpcs_out(3) <= \<const0>\;
+ rxoutclkpcs_out(2) <= \<const0>\;
+ rxoutclkpcs_out(1) <= \<const0>\;
+ rxoutclkpcs_out(0) <= \<const0>\;
+ rxphaligndone_out(3) <= \<const0>\;
+ rxphaligndone_out(2) <= \<const0>\;
+ rxphaligndone_out(1) <= \<const0>\;
+ rxphaligndone_out(0) <= \<const0>\;
+ rxphalignerr_out(3) <= \<const0>\;
+ rxphalignerr_out(2) <= \<const0>\;
+ rxphalignerr_out(1) <= \<const0>\;
+ rxphalignerr_out(0) <= \<const0>\;
+ rxprbserr_out(3) <= \<const0>\;
+ rxprbserr_out(2) <= \<const0>\;
+ rxprbserr_out(1) <= \<const0>\;
+ rxprbserr_out(0) <= \<const0>\;
+ rxprbslocked_out(3) <= \<const0>\;
+ rxprbslocked_out(2) <= \<const0>\;
+ rxprbslocked_out(1) <= \<const0>\;
+ rxprbslocked_out(0) <= \<const0>\;
+ rxprgdivresetdone_out(3) <= \<const0>\;
+ rxprgdivresetdone_out(2) <= \<const0>\;
+ rxprgdivresetdone_out(1) <= \<const0>\;
+ rxprgdivresetdone_out(0) <= \<const0>\;
+ rxqpisenn_out(3) <= \<const0>\;
+ rxqpisenn_out(2) <= \<const0>\;
+ rxqpisenn_out(1) <= \<const0>\;
+ rxqpisenn_out(0) <= \<const0>\;
+ rxqpisenp_out(3) <= \<const0>\;
+ rxqpisenp_out(2) <= \<const0>\;
+ rxqpisenp_out(1) <= \<const0>\;
+ rxqpisenp_out(0) <= \<const0>\;
+ rxratedone_out(3) <= \<const0>\;
+ rxratedone_out(2) <= \<const0>\;
+ rxratedone_out(1) <= \<const0>\;
+ rxratedone_out(0) <= \<const0>\;
+ rxrecclk0_sel_out(1) <= \<const0>\;
+ rxrecclk0_sel_out(0) <= \<const0>\;
+ rxrecclk0sel_out(0) <= \<const0>\;
+ rxrecclk1_sel_out(1) <= \<const0>\;
+ rxrecclk1_sel_out(0) <= \<const0>\;
+ rxrecclk1sel_out(0) <= \<const0>\;
+ rxrecclkout_out(3) <= \<const0>\;
+ rxrecclkout_out(2) <= \<const0>\;
+ rxrecclkout_out(1) <= \<const0>\;
+ rxrecclkout_out(0) <= \<const0>\;
+ rxsliderdy_out(3) <= \<const0>\;
+ rxsliderdy_out(2) <= \<const0>\;
+ rxsliderdy_out(1) <= \<const0>\;
+ rxsliderdy_out(0) <= \<const0>\;
+ rxslipdone_out(3) <= \<const0>\;
+ rxslipdone_out(2) <= \<const0>\;
+ rxslipdone_out(1) <= \<const0>\;
+ rxslipdone_out(0) <= \<const0>\;
+ rxslipoutclkrdy_out(3) <= \<const0>\;
+ rxslipoutclkrdy_out(2) <= \<const0>\;
+ rxslipoutclkrdy_out(1) <= \<const0>\;
+ rxslipoutclkrdy_out(0) <= \<const0>\;
+ rxslippmardy_out(3) <= \<const0>\;
+ rxslippmardy_out(2) <= \<const0>\;
+ rxslippmardy_out(1) <= \<const0>\;
+ rxslippmardy_out(0) <= \<const0>\;
+ rxstartofseq_out(7) <= \<const0>\;
+ rxstartofseq_out(6) <= \<const0>\;
+ rxstartofseq_out(5) <= \<const0>\;
+ rxstartofseq_out(4) <= \<const0>\;
+ rxstartofseq_out(3) <= \<const0>\;
+ rxstartofseq_out(2) <= \<const0>\;
+ rxstartofseq_out(1) <= \<const0>\;
+ rxstartofseq_out(0) <= \<const0>\;
+ rxstatus_out(11) <= \<const0>\;
+ rxstatus_out(10) <= \<const0>\;
+ rxstatus_out(9) <= \<const0>\;
+ rxstatus_out(8) <= \<const0>\;
+ rxstatus_out(7) <= \<const0>\;
+ rxstatus_out(6) <= \<const0>\;
+ rxstatus_out(5) <= \<const0>\;
+ rxstatus_out(4) <= \<const0>\;
+ rxstatus_out(3) <= \<const0>\;
+ rxstatus_out(2) <= \<const0>\;
+ rxstatus_out(1) <= \<const0>\;
+ rxstatus_out(0) <= \<const0>\;
+ rxsyncdone_out(3) <= \<const0>\;
+ rxsyncdone_out(2) <= \<const0>\;
+ rxsyncdone_out(1) <= \<const0>\;
+ rxsyncdone_out(0) <= \<const0>\;
+ rxsyncout_out(3) <= \<const0>\;
+ rxsyncout_out(2) <= \<const0>\;
+ rxsyncout_out(1) <= \<const0>\;
+ rxsyncout_out(0) <= \<const0>\;
+ rxvalid_out(3) <= \<const0>\;
+ rxvalid_out(2) <= \<const0>\;
+ rxvalid_out(1) <= \<const0>\;
+ rxvalid_out(0) <= \<const0>\;
+ sdm0finalout_out(0) <= \<const0>\;
+ sdm0testdata_out(0) <= \<const0>\;
+ sdm1finalout_out(0) <= \<const0>\;
+ sdm1testdata_out(0) <= \<const0>\;
+ tcongpo_out(0) <= \<const0>\;
+ tconrsvdout0_out(0) <= \<const0>\;
+ txbufstatus_out(7) <= \<const0>\;
+ txbufstatus_out(6) <= \<const0>\;
+ txbufstatus_out(5) <= \<const0>\;
+ txbufstatus_out(4) <= \<const0>\;
+ txbufstatus_out(3) <= \<const0>\;
+ txbufstatus_out(2) <= \<const0>\;
+ txbufstatus_out(1) <= \<const0>\;
+ txbufstatus_out(0) <= \<const0>\;
+ txcomfinish_out(3) <= \<const0>\;
+ txcomfinish_out(2) <= \<const0>\;
+ txcomfinish_out(1) <= \<const0>\;
+ txcomfinish_out(0) <= \<const0>\;
+ txdccdone_out(0) <= \<const0>\;
+ txdlysresetdone_out(3) <= \<const0>\;
+ txdlysresetdone_out(2) <= \<const0>\;
+ txdlysresetdone_out(1) <= \<const0>\;
+ txdlysresetdone_out(0) <= \<const0>\;
+ txoutclkfabric_out(3) <= \<const0>\;
+ txoutclkfabric_out(2) <= \<const0>\;
+ txoutclkfabric_out(1) <= \<const0>\;
+ txoutclkfabric_out(0) <= \<const0>\;
+ txoutclkpcs_out(3) <= \<const0>\;
+ txoutclkpcs_out(2) <= \<const0>\;
+ txoutclkpcs_out(1) <= \<const0>\;
+ txoutclkpcs_out(0) <= \<const0>\;
+ txphaligndone_out(3) <= \<const0>\;
+ txphaligndone_out(2) <= \<const0>\;
+ txphaligndone_out(1) <= \<const0>\;
+ txphaligndone_out(0) <= \<const0>\;
+ txphinitdone_out(3) <= \<const0>\;
+ txphinitdone_out(2) <= \<const0>\;
+ txphinitdone_out(1) <= \<const0>\;
+ txphinitdone_out(0) <= \<const0>\;
+ txprgdivresetdone_out(3) <= \<const0>\;
+ txprgdivresetdone_out(2) <= \<const0>\;
+ txprgdivresetdone_out(1) <= \<const0>\;
+ txprgdivresetdone_out(0) <= \<const0>\;
+ txqpisenn_out(3) <= \<const0>\;
+ txqpisenn_out(2) <= \<const0>\;
+ txqpisenn_out(1) <= \<const0>\;
+ txqpisenn_out(0) <= \<const0>\;
+ txqpisenp_out(3) <= \<const0>\;
+ txqpisenp_out(2) <= \<const0>\;
+ txqpisenp_out(1) <= \<const0>\;
+ txqpisenp_out(0) <= \<const0>\;
+ txratedone_out(3) <= \<const0>\;
+ txratedone_out(2) <= \<const0>\;
+ txratedone_out(1) <= \<const0>\;
+ txratedone_out(0) <= \<const0>\;
+ txsyncdone_out(3) <= \<const0>\;
+ txsyncdone_out(2) <= \<const0>\;
+ txsyncdone_out(1) <= \<const0>\;
+ txsyncdone_out(0) <= \<const0>\;
+ txsyncout_out(3) <= \<const0>\;
+ txsyncout_out(2) <= \<const0>\;
+ txsyncout_out(1) <= \<const0>\;
+ txsyncout_out(0) <= \<const0>\;
+ ubdaddr_out(0) <= \<const0>\;
+ ubden_out(0) <= \<const0>\;
+ ubdi_out(0) <= \<const0>\;
+ ubdwe_out(0) <= \<const0>\;
+ ubmdmtdo_out(0) <= \<const0>\;
+ ubrsvdout_out(0) <= \<const0>\;
+ ubtxuart_out(0) <= \<const0>\;
+GND: unisim.vcomponents.GND
+ port map (
+ G => \<const0>\
+ );
+\gen_gtwizard_gthe3_top.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_gthe3_inst\: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_gthe3
+ port map (
+ cplllock_out(3 downto 0) => cplllock_out(3 downto 0),
+ drpclk_in(3 downto 0) => drpclk_in(3 downto 0),
+ gthrxn_in(3 downto 0) => gthrxn_in(3 downto 0),
+ gthrxp_in(3 downto 0) => gthrxp_in(3 downto 0),
+ gthtxn_out(3 downto 0) => gthtxn_out(3 downto 0),
+ gthtxp_out(3 downto 0) => gthtxp_out(3 downto 0),
+ gtpowergood_out(3 downto 0) => gtpowergood_out(3 downto 0),
+ gtrefclk01_in(0) => gtrefclk01_in(0),
+ gtrefclk0_in(3 downto 0) => gtrefclk0_in(3 downto 0),
+ gtwiz_buffbypass_tx_done_out(0) => gtwiz_buffbypass_tx_done_out(0),
+ gtwiz_buffbypass_tx_error_out(0) => gtwiz_buffbypass_tx_error_out(0),
+ gtwiz_buffbypass_tx_reset_in(0) => gtwiz_buffbypass_tx_reset_in(0),
+ gtwiz_buffbypass_tx_start_user_in(0) => gtwiz_buffbypass_tx_start_user_in(0),
+ gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_cdr_stable_out(0) => gtwiz_reset_rx_cdr_stable_out(0),
+ gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0),
+ gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0),
+ gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0),
+ gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0),
+ gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0),
+ gtwiz_reset_tx_pll_and_datapath_in(0) => gtwiz_reset_tx_pll_and_datapath_in(0),
+ gtwiz_userclk_rx_active_in(0) => gtwiz_userclk_rx_active_in(0),
+ gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0),
+ gtwiz_userdata_rx_out(79 downto 0) => gtwiz_userdata_rx_out(79 downto 0),
+ gtwiz_userdata_tx_in(79 downto 0) => gtwiz_userdata_tx_in(79 downto 0),
+ loopback_in(11 downto 0) => loopback_in(11 downto 0),
+ qpll0fbclklost_out(0) => qpll0fbclklost_out(0),
+ qpll0lock_out(0) => qpll0lock_out(0),
+ qpll1fbclklost_out(0) => qpll1fbclklost_out(0),
+ qpll1lock_out(0) => qpll1lock_out(0),
+ qpll1outclk_out(0) => qpll1outclk_out(0),
+ qpll1outrefclk_out(0) => qpll1outrefclk_out(0),
+ rxcdrhold_in(3 downto 0) => rxcdrhold_in(3 downto 0),
+ rxcdrlock_out(3 downto 0) => rxcdrlock_out(3 downto 0),
+ rxoutclk_out(3 downto 0) => rxoutclk_out(3 downto 0),
+ rxpmaresetdone_out(3 downto 0) => rxpmaresetdone_out(3 downto 0),
+ rxpolarity_in(3 downto 0) => rxpolarity_in(3 downto 0),
+ rxresetdone_out(3 downto 0) => rxresetdone_out(3 downto 0),
+ rxslide_in(3 downto 0) => rxslide_in(3 downto 0),
+ rxusrclk2_in(3 downto 0) => rxusrclk2_in(3 downto 0),
+ rxusrclk_in(3 downto 0) => rxusrclk_in(3 downto 0),
+ txoutclk_out(3 downto 0) => txoutclk_out(3 downto 0),
+ txpmaresetdone_out(3 downto 0) => txpmaresetdone_out(3 downto 0),
+ txpolarity_in(3 downto 0) => txpolarity_in(3 downto 0),
+ txresetdone_out(3 downto 0) => txresetdone_out(3 downto 0),
+ txusrclk2_in(3 downto 0) => txusrclk2_in(3 downto 0),
+ txusrclk_in(3 downto 0) => txusrclk_in(3 downto 0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0 is
+ port (
+ gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 79 downto 0 );
+ gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 79 downto 0 );
+ gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ drpclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxn_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxp_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ loopback_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ rxcdrhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslide_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ cplllock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxn_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxp_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtpowergood_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrlock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 )
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0 : entity is true;
+ attribute CHECK_LICENSE_TYPE : string;
+ attribute CHECK_LICENSE_TYPE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0 : entity is "KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0,KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top,{}";
+ attribute DowngradeIPIdentifiedWarnings : string;
+ attribute DowngradeIPIdentifiedWarnings of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0 : entity is "yes";
+ attribute X_CORE_INFO : string;
+ attribute X_CORE_INFO of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0 : entity is "KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top,Vivado 2024.1";
+end KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0;
+
+architecture STRUCTURE of KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0 is
+ signal NLW_inst_bufgtce_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_bufgtcemask_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_bufgtdiv_out_UNCONNECTED : STD_LOGIC_VECTOR ( 35 downto 0 );
+ signal NLW_inst_bufgtreset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_bufgtrstmask_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_cpllfbclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_cpllrefclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_dmonitorout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 67 downto 0 );
+ signal NLW_inst_dmonitoroutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_drpdo_common_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+ signal NLW_inst_drpdo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_inst_drprdy_common_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_drprdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_eyescandataerror_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_gtrefclkmonitor_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_reset_qpll0reset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_rx_active_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_rx_srcclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_rx_usrclk2_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_rx_usrclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_tx_active_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_tx_srcclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_tx_usrclk2_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_tx_usrclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtytxn_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtytxp_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_pcierategen3_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_pcierateidle_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_pcierateqpllpd_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_pcierateqpllreset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_pciesynctxsyncdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_pcieusergen3rdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_pcieuserphystatusrst_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_pcieuserratestart_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_pcsrsvdout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
+ signal NLW_inst_phystatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_pinrsrvdas_out_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_inst_pmarsvdout0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_pmarsvdout1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_powerpresent_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_qpll0outclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_qpll0outrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_qpll0refclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_qpll1refclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_qplldmonitor0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_qplldmonitor1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_refclkoutmonitor0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_refclkoutmonitor1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_resetexception_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxbufstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_rxbyteisaligned_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxbyterealign_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxcdrphdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxchanbondseq_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxchanisaligned_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxchanrealign_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxchbondo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
+ signal NLW_inst_rxckcaldone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_rxclkcorcnt_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_rxcominitdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxcommadet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxcomsasdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxcomwakedet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxctrl0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_inst_rxctrl1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_inst_rxctrl2_out_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_inst_rxctrl3_out_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_inst_rxdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 511 downto 0 );
+ signal NLW_inst_rxdataextendrsvd_out_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_inst_rxdatavalid_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_rxdlysresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxelecidle_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxheader_out_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
+ signal NLW_inst_rxheadervalid_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_rxlfpstresetdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_rxmonitorout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 27 downto 0 );
+ signal NLW_inst_rxosintdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxosintstarted_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxosintstrobedone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxosintstrobestarted_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxoutclkfabric_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxoutclkpcs_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxphaligndone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxphalignerr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxprbserr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxprbslocked_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxprgdivresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxqpisenn_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxqpisenp_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxratedone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxrecclk0_sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_rxrecclk0sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_rxrecclk1_sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_rxrecclk1sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_rxrecclkout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxsliderdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxslipdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxslipoutclkrdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxslippmardy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxstartofseq_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_rxstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_rxsyncdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxsyncout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxvalid_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_sdm0finalout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_sdm0testdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_sdm1finalout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_sdm1testdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_tcongpo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_tconrsvdout0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_txbufstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_txcomfinish_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txdccdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_txdlysresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txoutclkfabric_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txoutclkpcs_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txphaligndone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txphinitdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txprgdivresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txqpisenn_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txqpisenp_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txratedone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txsyncdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txsyncout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_ubdaddr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_ubden_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_ubdi_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_ubdwe_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_ubmdmtdo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_ubrsvdout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_ubtxuart_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ attribute C_CHANNEL_ENABLE : string;
+ attribute C_CHANNEL_ENABLE of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100000000";
+ attribute C_COMMON_SCALING_FACTOR : integer;
+ attribute C_COMMON_SCALING_FACTOR of inst : label is 1;
+ attribute C_CPLL_VCO_FREQUENCY : string;
+ attribute C_CPLL_VCO_FREQUENCY of inst : label is "2400.000000";
+ attribute C_ENABLE_COMMON_USRCLK : integer;
+ attribute C_ENABLE_COMMON_USRCLK of inst : label is 0;
+ attribute C_FORCE_COMMONS : integer;
+ attribute C_FORCE_COMMONS of inst : label is 0;
+ attribute C_FREERUN_FREQUENCY : string;
+ attribute C_FREERUN_FREQUENCY of inst : label is "40.000000";
+ attribute C_GT_REV : integer;
+ attribute C_GT_REV of inst : label is 17;
+ attribute C_GT_TYPE : integer;
+ attribute C_GT_TYPE of inst : label is 0;
+ attribute C_INCLUDE_CPLL_CAL : integer;
+ attribute C_INCLUDE_CPLL_CAL of inst : label is 2;
+ attribute C_LOCATE_COMMON : integer;
+ attribute C_LOCATE_COMMON of inst : label is 0;
+ attribute C_LOCATE_IN_SYSTEM_IBERT_CORE : integer;
+ attribute C_LOCATE_IN_SYSTEM_IBERT_CORE of inst : label is 2;
+ attribute C_LOCATE_RESET_CONTROLLER : integer;
+ attribute C_LOCATE_RESET_CONTROLLER of inst : label is 0;
+ attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER : integer;
+ attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER of inst : label is 0;
+ attribute C_LOCATE_RX_USER_CLOCKING : integer;
+ attribute C_LOCATE_RX_USER_CLOCKING of inst : label is 1;
+ attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER : integer;
+ attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER of inst : label is 0;
+ attribute C_LOCATE_TX_USER_CLOCKING : integer;
+ attribute C_LOCATE_TX_USER_CLOCKING of inst : label is 1;
+ attribute C_LOCATE_USER_DATA_WIDTH_SIZING : integer;
+ attribute C_LOCATE_USER_DATA_WIDTH_SIZING of inst : label is 0;
+ attribute C_PCIE_CORECLK_FREQ : integer;
+ attribute C_PCIE_CORECLK_FREQ of inst : label is 250;
+ attribute C_PCIE_ENABLE : integer;
+ attribute C_PCIE_ENABLE of inst : label is 0;
+ attribute C_RESET_CONTROLLER_INSTANCE_CTRL : integer;
+ attribute C_RESET_CONTROLLER_INSTANCE_CTRL of inst : label is 0;
+ attribute C_RESET_SEQUENCE_INTERVAL : integer;
+ attribute C_RESET_SEQUENCE_INTERVAL of inst : label is 0;
+ attribute C_RX_BUFFBYPASS_MODE : integer;
+ attribute C_RX_BUFFBYPASS_MODE of inst : label is 0;
+ attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL : integer;
+ attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL of inst : label is 0;
+ attribute C_RX_BUFFER_MODE : integer;
+ attribute C_RX_BUFFER_MODE of inst : label is 1;
+ attribute C_RX_CB_DISP : string;
+ attribute C_RX_CB_DISP of inst : label is "8'b00000000";
+ attribute C_RX_CB_K : string;
+ attribute C_RX_CB_K of inst : label is "8'b00000000";
+ attribute C_RX_CB_LEN_SEQ : integer;
+ attribute C_RX_CB_LEN_SEQ of inst : label is 1;
+ attribute C_RX_CB_MAX_LEVEL : integer;
+ attribute C_RX_CB_MAX_LEVEL of inst : label is 2;
+ attribute C_RX_CB_NUM_SEQ : integer;
+ attribute C_RX_CB_NUM_SEQ of inst : label is 0;
+ attribute C_RX_CB_VAL : string;
+ attribute C_RX_CB_VAL of inst : label is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_RX_CC_DISP : string;
+ attribute C_RX_CC_DISP of inst : label is "8'b00000000";
+ attribute C_RX_CC_ENABLE : integer;
+ attribute C_RX_CC_ENABLE of inst : label is 0;
+ attribute C_RX_CC_K : string;
+ attribute C_RX_CC_K of inst : label is "8'b00000000";
+ attribute C_RX_CC_LEN_SEQ : integer;
+ attribute C_RX_CC_LEN_SEQ of inst : label is 1;
+ attribute C_RX_CC_NUM_SEQ : integer;
+ attribute C_RX_CC_NUM_SEQ of inst : label is 0;
+ attribute C_RX_CC_PERIODICITY : integer;
+ attribute C_RX_CC_PERIODICITY of inst : label is 5000;
+ attribute C_RX_CC_VAL : string;
+ attribute C_RX_CC_VAL of inst : label is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_RX_COMMA_M_ENABLE : integer;
+ attribute C_RX_COMMA_M_ENABLE of inst : label is 0;
+ attribute C_RX_COMMA_M_VAL : string;
+ attribute C_RX_COMMA_M_VAL of inst : label is "10'b1010000011";
+ attribute C_RX_COMMA_P_ENABLE : integer;
+ attribute C_RX_COMMA_P_ENABLE of inst : label is 0;
+ attribute C_RX_COMMA_P_VAL : string;
+ attribute C_RX_COMMA_P_VAL of inst : label is "10'b0101111100";
+ attribute C_RX_DATA_DECODING : integer;
+ attribute C_RX_DATA_DECODING of inst : label is 0;
+ attribute C_RX_ENABLE : integer;
+ attribute C_RX_ENABLE of inst : label is 1;
+ attribute C_RX_INT_DATA_WIDTH : integer;
+ attribute C_RX_INT_DATA_WIDTH of inst : label is 20;
+ attribute C_RX_LINE_RATE : string;
+ attribute C_RX_LINE_RATE of inst : label is "4.800000";
+ attribute C_RX_MASTER_CHANNEL_IDX : integer;
+ attribute C_RX_MASTER_CHANNEL_IDX of inst : label is 8;
+ attribute C_RX_OUTCLK_BUFG_GT_DIV : integer;
+ attribute C_RX_OUTCLK_BUFG_GT_DIV of inst : label is 1;
+ attribute C_RX_OUTCLK_FREQUENCY : string;
+ attribute C_RX_OUTCLK_FREQUENCY of inst : label is "240.000000";
+ attribute C_RX_OUTCLK_SOURCE : integer;
+ attribute C_RX_OUTCLK_SOURCE of inst : label is 1;
+ attribute C_RX_PLL_TYPE : integer;
+ attribute C_RX_PLL_TYPE of inst : label is 2;
+ attribute C_RX_RECCLK_OUTPUT : string;
+ attribute C_RX_RECCLK_OUTPUT of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_RX_REFCLK_FREQUENCY : string;
+ attribute C_RX_REFCLK_FREQUENCY of inst : label is "240.000000";
+ attribute C_RX_SLIDE_MODE : integer;
+ attribute C_RX_SLIDE_MODE of inst : label is 2;
+ attribute C_RX_USER_CLOCKING_CONTENTS : integer;
+ attribute C_RX_USER_CLOCKING_CONTENTS of inst : label is 0;
+ attribute C_RX_USER_CLOCKING_INSTANCE_CTRL : integer;
+ attribute C_RX_USER_CLOCKING_INSTANCE_CTRL of inst : label is 0;
+ attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer;
+ attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of inst : label is 1;
+ attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer;
+ attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of inst : label is 1;
+ attribute C_RX_USER_CLOCKING_SOURCE : integer;
+ attribute C_RX_USER_CLOCKING_SOURCE of inst : label is 0;
+ attribute C_RX_USER_DATA_WIDTH : integer;
+ attribute C_RX_USER_DATA_WIDTH of inst : label is 20;
+ attribute C_RX_USRCLK2_FREQUENCY : string;
+ attribute C_RX_USRCLK2_FREQUENCY of inst : label is "240.000000";
+ attribute C_RX_USRCLK_FREQUENCY : string;
+ attribute C_RX_USRCLK_FREQUENCY of inst : label is "240.000000";
+ attribute C_SECONDARY_QPLL_ENABLE : integer;
+ attribute C_SECONDARY_QPLL_ENABLE of inst : label is 0;
+ attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY : string;
+ attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY of inst : label is "257.812500";
+ attribute C_SIM_CPLL_CAL_BYPASS : integer;
+ attribute C_SIM_CPLL_CAL_BYPASS of inst : label is 1;
+ attribute C_TOTAL_NUM_CHANNELS : integer;
+ attribute C_TOTAL_NUM_CHANNELS of inst : label is 4;
+ attribute C_TOTAL_NUM_COMMONS : integer;
+ attribute C_TOTAL_NUM_COMMONS of inst : label is 1;
+ attribute C_TOTAL_NUM_COMMONS_EXAMPLE : integer;
+ attribute C_TOTAL_NUM_COMMONS_EXAMPLE of inst : label is 0;
+ attribute C_TXPROGDIV_FREQ_ENABLE : integer;
+ attribute C_TXPROGDIV_FREQ_ENABLE of inst : label is 0;
+ attribute C_TXPROGDIV_FREQ_SOURCE : integer;
+ attribute C_TXPROGDIV_FREQ_SOURCE of inst : label is 1;
+ attribute C_TXPROGDIV_FREQ_VAL : string;
+ attribute C_TXPROGDIV_FREQ_VAL of inst : label is "240.000000";
+ attribute C_TX_BUFFBYPASS_MODE : integer;
+ attribute C_TX_BUFFBYPASS_MODE of inst : label is 0;
+ attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL : integer;
+ attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL of inst : label is 0;
+ attribute C_TX_BUFFER_MODE : integer;
+ attribute C_TX_BUFFER_MODE of inst : label is 0;
+ attribute C_TX_DATA_ENCODING : integer;
+ attribute C_TX_DATA_ENCODING of inst : label is 0;
+ attribute C_TX_ENABLE : integer;
+ attribute C_TX_ENABLE of inst : label is 1;
+ attribute C_TX_INT_DATA_WIDTH : integer;
+ attribute C_TX_INT_DATA_WIDTH of inst : label is 20;
+ attribute C_TX_LINE_RATE : string;
+ attribute C_TX_LINE_RATE of inst : label is "4.800000";
+ attribute C_TX_MASTER_CHANNEL_IDX : integer;
+ attribute C_TX_MASTER_CHANNEL_IDX of inst : label is 8;
+ attribute C_TX_OUTCLK_BUFG_GT_DIV : integer;
+ attribute C_TX_OUTCLK_BUFG_GT_DIV of inst : label is 1;
+ attribute C_TX_OUTCLK_FREQUENCY : string;
+ attribute C_TX_OUTCLK_FREQUENCY of inst : label is "240.000000";
+ attribute C_TX_OUTCLK_SOURCE : integer;
+ attribute C_TX_OUTCLK_SOURCE of inst : label is 2;
+ attribute C_TX_PLL_TYPE : integer;
+ attribute C_TX_PLL_TYPE of inst : label is 1;
+ attribute C_TX_REFCLK_FREQUENCY : string;
+ attribute C_TX_REFCLK_FREQUENCY of inst : label is "240.000000";
+ attribute C_TX_USER_CLOCKING_CONTENTS : integer;
+ attribute C_TX_USER_CLOCKING_CONTENTS of inst : label is 0;
+ attribute C_TX_USER_CLOCKING_INSTANCE_CTRL : integer;
+ attribute C_TX_USER_CLOCKING_INSTANCE_CTRL of inst : label is 0;
+ attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer;
+ attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of inst : label is 1;
+ attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer;
+ attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of inst : label is 1;
+ attribute C_TX_USER_CLOCKING_SOURCE : integer;
+ attribute C_TX_USER_CLOCKING_SOURCE of inst : label is 0;
+ attribute C_TX_USER_DATA_WIDTH : integer;
+ attribute C_TX_USER_DATA_WIDTH of inst : label is 20;
+ attribute C_TX_USRCLK2_FREQUENCY : string;
+ attribute C_TX_USRCLK2_FREQUENCY of inst : label is "240.000000";
+ attribute C_TX_USRCLK_FREQUENCY : string;
+ attribute C_TX_USRCLK_FREQUENCY of inst : label is "240.000000";
+ attribute C_USER_GTPOWERGOOD_DELAY_EN : integer;
+ attribute C_USER_GTPOWERGOOD_DELAY_EN of inst : label is 0;
+begin
+inst: entity work.KCU_RXBUF_PMA_QPLLTXGTREF1_CPLLRXGTREF0_gtwizard_top
+ port map (
+ bgbypassb_in(0) => '1',
+ bgmonitorenb_in(0) => '1',
+ bgpdb_in(0) => '1',
+ bgrcalovrd_in(4 downto 0) => B"11111",
+ bgrcalovrdenb_in(0) => '1',
+ bufgtce_out(11 downto 0) => NLW_inst_bufgtce_out_UNCONNECTED(11 downto 0),
+ bufgtcemask_out(11 downto 0) => NLW_inst_bufgtcemask_out_UNCONNECTED(11 downto 0),
+ bufgtdiv_out(35 downto 0) => NLW_inst_bufgtdiv_out_UNCONNECTED(35 downto 0),
+ bufgtreset_out(11 downto 0) => NLW_inst_bufgtreset_out_UNCONNECTED(11 downto 0),
+ bufgtrstmask_out(11 downto 0) => NLW_inst_bufgtrstmask_out_UNCONNECTED(11 downto 0),
+ cdrstepdir_in(0) => '0',
+ cdrstepsq_in(0) => '0',
+ cdrstepsx_in(0) => '0',
+ cfgreset_in(3 downto 0) => B"0000",
+ clkrsvd0_in(3 downto 0) => B"0000",
+ clkrsvd1_in(3 downto 0) => B"0000",
+ cpllfbclklost_out(3 downto 0) => NLW_inst_cpllfbclklost_out_UNCONNECTED(3 downto 0),
+ cpllfreqlock_in(0) => '0',
+ cplllock_out(3 downto 0) => cplllock_out(3 downto 0),
+ cplllockdetclk_in(3 downto 0) => B"0000",
+ cplllocken_in(3 downto 0) => B"1111",
+ cpllpd_in(3 downto 0) => B"0000",
+ cpllrefclklost_out(3 downto 0) => NLW_inst_cpllrefclklost_out_UNCONNECTED(3 downto 0),
+ cpllrefclksel_in(11 downto 0) => B"001001001001",
+ cpllreset_in(3 downto 0) => B"0000",
+ dmonfiforeset_in(3 downto 0) => B"0000",
+ dmonitorclk_in(3 downto 0) => B"0000",
+ dmonitorout_out(67 downto 0) => NLW_inst_dmonitorout_out_UNCONNECTED(67 downto 0),
+ dmonitoroutclk_out(0) => NLW_inst_dmonitoroutclk_out_UNCONNECTED(0),
+ drpaddr_common_in(8 downto 0) => B"000000000",
+ drpaddr_in(35 downto 0) => B"000000000000000000000000000000000000",
+ drpclk_common_in(0) => '0',
+ drpclk_in(3 downto 0) => drpclk_in(3 downto 0),
+ drpdi_common_in(15 downto 0) => B"0000000000000000",
+ drpdi_in(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ drpdo_common_out(15 downto 0) => NLW_inst_drpdo_common_out_UNCONNECTED(15 downto 0),
+ drpdo_out(63 downto 0) => NLW_inst_drpdo_out_UNCONNECTED(63 downto 0),
+ drpen_common_in(0) => '0',
+ drpen_in(3 downto 0) => B"0000",
+ drprdy_common_out(0) => NLW_inst_drprdy_common_out_UNCONNECTED(0),
+ drprdy_out(3 downto 0) => NLW_inst_drprdy_out_UNCONNECTED(3 downto 0),
+ drprst_in(0) => '0',
+ drpwe_common_in(0) => '0',
+ drpwe_in(3 downto 0) => B"0000",
+ elpcaldvorwren_in(0) => '0',
+ elpcalpaorwren_in(0) => '0',
+ evoddphicaldone_in(3 downto 0) => B"0000",
+ evoddphicalstart_in(3 downto 0) => B"0000",
+ evoddphidrden_in(3 downto 0) => B"0000",
+ evoddphidwren_in(3 downto 0) => B"0000",
+ evoddphixrden_in(3 downto 0) => B"0000",
+ evoddphixwren_in(3 downto 0) => B"0000",
+ eyescandataerror_out(3 downto 0) => NLW_inst_eyescandataerror_out_UNCONNECTED(3 downto 0),
+ eyescanmode_in(3 downto 0) => B"0000",
+ eyescanreset_in(3 downto 0) => B"0000",
+ eyescantrigger_in(3 downto 0) => B"0000",
+ freqos_in(0) => '0',
+ gtgrefclk0_in(0) => '0',
+ gtgrefclk1_in(0) => '0',
+ gtgrefclk_in(3 downto 0) => B"0000",
+ gthrxn_in(3 downto 0) => gthrxn_in(3 downto 0),
+ gthrxp_in(3 downto 0) => gthrxp_in(3 downto 0),
+ gthtxn_out(3 downto 0) => gthtxn_out(3 downto 0),
+ gthtxp_out(3 downto 0) => gthtxp_out(3 downto 0),
+ gtnorthrefclk00_in(0) => '0',
+ gtnorthrefclk01_in(0) => '0',
+ gtnorthrefclk0_in(3 downto 0) => B"0000",
+ gtnorthrefclk10_in(0) => '0',
+ gtnorthrefclk11_in(0) => '0',
+ gtnorthrefclk1_in(3 downto 0) => B"0000",
+ gtpowergood_out(3 downto 0) => gtpowergood_out(3 downto 0),
+ gtrefclk00_in(0) => '0',
+ gtrefclk01_in(0) => gtrefclk01_in(0),
+ gtrefclk0_in(3 downto 0) => gtrefclk0_in(3 downto 0),
+ gtrefclk10_in(0) => '0',
+ gtrefclk11_in(0) => '0',
+ gtrefclk1_in(3 downto 0) => B"0000",
+ gtrefclkmonitor_out(3 downto 0) => NLW_inst_gtrefclkmonitor_out_UNCONNECTED(3 downto 0),
+ gtresetsel_in(3 downto 0) => B"0000",
+ gtrsvd_in(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ gtrxreset_in(3 downto 0) => B"0000",
+ gtrxresetsel_in(0) => '0',
+ gtsouthrefclk00_in(0) => '0',
+ gtsouthrefclk01_in(0) => '0',
+ gtsouthrefclk0_in(3 downto 0) => B"0000",
+ gtsouthrefclk10_in(0) => '0',
+ gtsouthrefclk11_in(0) => '0',
+ gtsouthrefclk1_in(3 downto 0) => B"0000",
+ gttxreset_in(3 downto 0) => B"0000",
+ gttxresetsel_in(0) => '0',
+ gtwiz_buffbypass_rx_done_out(0) => NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED(0),
+ gtwiz_buffbypass_rx_error_out(0) => NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED(0),
+ gtwiz_buffbypass_rx_reset_in(0) => '0',
+ gtwiz_buffbypass_rx_start_user_in(0) => '0',
+ gtwiz_buffbypass_tx_done_out(0) => gtwiz_buffbypass_tx_done_out(0),
+ gtwiz_buffbypass_tx_error_out(0) => gtwiz_buffbypass_tx_error_out(0),
+ gtwiz_buffbypass_tx_reset_in(0) => gtwiz_buffbypass_tx_reset_in(0),
+ gtwiz_buffbypass_tx_start_user_in(0) => gtwiz_buffbypass_tx_start_user_in(0),
+ gtwiz_gthe3_cpll_cal_bufg_ce_in(3 downto 0) => B"0000",
+ gtwiz_gthe3_cpll_cal_cnt_tol_in(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
+ gtwiz_gthe3_cpll_cal_txoutclk_period_in(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
+ gtwiz_gthe4_cpll_cal_bufg_ce_in(3 downto 0) => B"0000",
+ gtwiz_gthe4_cpll_cal_cnt_tol_in(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
+ gtwiz_gthe4_cpll_cal_txoutclk_period_in(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
+ gtwiz_gtye4_cpll_cal_bufg_ce_in(3 downto 0) => B"0000",
+ gtwiz_gtye4_cpll_cal_cnt_tol_in(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
+ gtwiz_gtye4_cpll_cal_txoutclk_period_in(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
+ gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_qpll0lock_in(0) => '0',
+ gtwiz_reset_qpll0reset_out(0) => NLW_inst_gtwiz_reset_qpll0reset_out_UNCONNECTED(0),
+ gtwiz_reset_qpll1lock_in(0) => '0',
+ gtwiz_reset_qpll1reset_out(0) => NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED(0),
+ gtwiz_reset_rx_cdr_stable_out(0) => gtwiz_reset_rx_cdr_stable_out(0),
+ gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0),
+ gtwiz_reset_rx_done_in(0) => '0',
+ gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0),
+ gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0),
+ gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0),
+ gtwiz_reset_tx_done_in(0) => '0',
+ gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0),
+ gtwiz_reset_tx_pll_and_datapath_in(0) => gtwiz_reset_tx_pll_and_datapath_in(0),
+ gtwiz_userclk_rx_active_in(0) => gtwiz_userclk_rx_active_in(0),
+ gtwiz_userclk_rx_active_out(0) => NLW_inst_gtwiz_userclk_rx_active_out_UNCONNECTED(0),
+ gtwiz_userclk_rx_reset_in(0) => '0',
+ gtwiz_userclk_rx_srcclk_out(0) => NLW_inst_gtwiz_userclk_rx_srcclk_out_UNCONNECTED(0),
+ gtwiz_userclk_rx_usrclk2_out(0) => NLW_inst_gtwiz_userclk_rx_usrclk2_out_UNCONNECTED(0),
+ gtwiz_userclk_rx_usrclk_out(0) => NLW_inst_gtwiz_userclk_rx_usrclk_out_UNCONNECTED(0),
+ gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0),
+ gtwiz_userclk_tx_active_out(0) => NLW_inst_gtwiz_userclk_tx_active_out_UNCONNECTED(0),
+ gtwiz_userclk_tx_reset_in(0) => '0',
+ gtwiz_userclk_tx_srcclk_out(0) => NLW_inst_gtwiz_userclk_tx_srcclk_out_UNCONNECTED(0),
+ gtwiz_userclk_tx_usrclk2_out(0) => NLW_inst_gtwiz_userclk_tx_usrclk2_out_UNCONNECTED(0),
+ gtwiz_userclk_tx_usrclk_out(0) => NLW_inst_gtwiz_userclk_tx_usrclk_out_UNCONNECTED(0),
+ gtwiz_userdata_rx_out(79 downto 0) => gtwiz_userdata_rx_out(79 downto 0),
+ gtwiz_userdata_tx_in(79 downto 0) => gtwiz_userdata_tx_in(79 downto 0),
+ gtyrxn_in(0) => '0',
+ gtyrxp_in(0) => '0',
+ gtytxn_out(0) => NLW_inst_gtytxn_out_UNCONNECTED(0),
+ gtytxp_out(0) => NLW_inst_gtytxp_out_UNCONNECTED(0),
+ incpctrl_in(0) => '0',
+ loopback_in(11 downto 0) => loopback_in(11 downto 0),
+ looprsvd_in(0) => '0',
+ lpbkrxtxseren_in(3 downto 0) => B"0000",
+ lpbktxrxseren_in(3 downto 0) => B"0000",
+ pcieeqrxeqadaptdone_in(3 downto 0) => B"0000",
+ pcierategen3_out(3 downto 0) => NLW_inst_pcierategen3_out_UNCONNECTED(3 downto 0),
+ pcierateidle_out(3 downto 0) => NLW_inst_pcierateidle_out_UNCONNECTED(3 downto 0),
+ pcierateqpll0_in(0) => '0',
+ pcierateqpll1_in(0) => '0',
+ pcierateqpllpd_out(7 downto 0) => NLW_inst_pcierateqpllpd_out_UNCONNECTED(7 downto 0),
+ pcierateqpllreset_out(7 downto 0) => NLW_inst_pcierateqpllreset_out_UNCONNECTED(7 downto 0),
+ pcierstidle_in(3 downto 0) => B"0000",
+ pciersttxsyncstart_in(3 downto 0) => B"0000",
+ pciesynctxsyncdone_out(3 downto 0) => NLW_inst_pciesynctxsyncdone_out_UNCONNECTED(3 downto 0),
+ pcieusergen3rdy_out(3 downto 0) => NLW_inst_pcieusergen3rdy_out_UNCONNECTED(3 downto 0),
+ pcieuserphystatusrst_out(3 downto 0) => NLW_inst_pcieuserphystatusrst_out_UNCONNECTED(3 downto 0),
+ pcieuserratedone_in(3 downto 0) => B"0000",
+ pcieuserratestart_out(3 downto 0) => NLW_inst_pcieuserratestart_out_UNCONNECTED(3 downto 0),
+ pcsrsvdin2_in(19 downto 0) => B"00000000000000000000",
+ pcsrsvdin_in(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ pcsrsvdout_out(47 downto 0) => NLW_inst_pcsrsvdout_out_UNCONNECTED(47 downto 0),
+ phystatus_out(3 downto 0) => NLW_inst_phystatus_out_UNCONNECTED(3 downto 0),
+ pinrsrvdas_out(31 downto 0) => NLW_inst_pinrsrvdas_out_UNCONNECTED(31 downto 0),
+ pmarsvd0_in(7 downto 0) => B"00000000",
+ pmarsvd1_in(7 downto 0) => B"00000000",
+ pmarsvdin_in(19 downto 0) => B"00000000000000000000",
+ pmarsvdout0_out(7 downto 0) => NLW_inst_pmarsvdout0_out_UNCONNECTED(7 downto 0),
+ pmarsvdout1_out(7 downto 0) => NLW_inst_pmarsvdout1_out_UNCONNECTED(7 downto 0),
+ powerpresent_out(0) => NLW_inst_powerpresent_out_UNCONNECTED(0),
+ qpll0clk_in(3 downto 0) => B"0000",
+ qpll0clkrsvd0_in(0) => '0',
+ qpll0clkrsvd1_in(0) => '0',
+ qpll0fbclklost_out(0) => qpll0fbclklost_out(0),
+ qpll0fbdiv_in(0) => '0',
+ qpll0freqlock_in(0) => '0',
+ qpll0lock_out(0) => qpll0lock_out(0),
+ qpll0lockdetclk_in(0) => '0',
+ qpll0locken_in(0) => '0',
+ qpll0outclk_out(0) => NLW_inst_qpll0outclk_out_UNCONNECTED(0),
+ qpll0outrefclk_out(0) => NLW_inst_qpll0outrefclk_out_UNCONNECTED(0),
+ qpll0pd_in(0) => '1',
+ qpll0refclk_in(3 downto 0) => B"0000",
+ qpll0refclklost_out(0) => NLW_inst_qpll0refclklost_out_UNCONNECTED(0),
+ qpll0refclksel_in(2 downto 0) => B"001",
+ qpll0reset_in(0) => '1',
+ qpll1clk_in(3 downto 0) => B"0000",
+ qpll1clkrsvd0_in(0) => '0',
+ qpll1clkrsvd1_in(0) => '0',
+ qpll1fbclklost_out(0) => qpll1fbclklost_out(0),
+ qpll1fbdiv_in(0) => '0',
+ qpll1freqlock_in(0) => '0',
+ qpll1lock_out(0) => qpll1lock_out(0),
+ qpll1lockdetclk_in(0) => '0',
+ qpll1locken_in(0) => '1',
+ qpll1outclk_out(0) => qpll1outclk_out(0),
+ qpll1outrefclk_out(0) => qpll1outrefclk_out(0),
+ qpll1pd_in(0) => '0',
+ qpll1refclk_in(3 downto 0) => B"0000",
+ qpll1refclklost_out(0) => NLW_inst_qpll1refclklost_out_UNCONNECTED(0),
+ qpll1refclksel_in(2 downto 0) => B"001",
+ qpll1reset_in(0) => '0',
+ qplldmonitor0_out(7 downto 0) => NLW_inst_qplldmonitor0_out_UNCONNECTED(7 downto 0),
+ qplldmonitor1_out(7 downto 0) => NLW_inst_qplldmonitor1_out_UNCONNECTED(7 downto 0),
+ qpllrsvd1_in(7 downto 0) => B"00000000",
+ qpllrsvd2_in(4 downto 0) => B"00000",
+ qpllrsvd3_in(4 downto 0) => B"00000",
+ qpllrsvd4_in(7 downto 0) => B"00000000",
+ rcalenb_in(0) => '1',
+ refclkoutmonitor0_out(0) => NLW_inst_refclkoutmonitor0_out_UNCONNECTED(0),
+ refclkoutmonitor1_out(0) => NLW_inst_refclkoutmonitor1_out_UNCONNECTED(0),
+ resetexception_out(3 downto 0) => NLW_inst_resetexception_out_UNCONNECTED(3 downto 0),
+ resetovrd_in(3 downto 0) => B"0000",
+ rstclkentx_in(3 downto 0) => B"0000",
+ rx8b10ben_in(3 downto 0) => B"0000",
+ rxafecfoken_in(0) => '0',
+ rxbufreset_in(3 downto 0) => B"0000",
+ rxbufstatus_out(11 downto 0) => NLW_inst_rxbufstatus_out_UNCONNECTED(11 downto 0),
+ rxbyteisaligned_out(3 downto 0) => NLW_inst_rxbyteisaligned_out_UNCONNECTED(3 downto 0),
+ rxbyterealign_out(3 downto 0) => NLW_inst_rxbyterealign_out_UNCONNECTED(3 downto 0),
+ rxcdrfreqreset_in(3 downto 0) => B"0000",
+ rxcdrhold_in(3 downto 0) => rxcdrhold_in(3 downto 0),
+ rxcdrlock_out(3 downto 0) => rxcdrlock_out(3 downto 0),
+ rxcdrovrden_in(3 downto 0) => B"0000",
+ rxcdrphdone_out(3 downto 0) => NLW_inst_rxcdrphdone_out_UNCONNECTED(3 downto 0),
+ rxcdrreset_in(3 downto 0) => B"0000",
+ rxcdrresetrsv_in(3 downto 0) => B"0000",
+ rxchanbondseq_out(3 downto 0) => NLW_inst_rxchanbondseq_out_UNCONNECTED(3 downto 0),
+ rxchanisaligned_out(3 downto 0) => NLW_inst_rxchanisaligned_out_UNCONNECTED(3 downto 0),
+ rxchanrealign_out(3 downto 0) => NLW_inst_rxchanrealign_out_UNCONNECTED(3 downto 0),
+ rxchbonden_in(3 downto 0) => B"0000",
+ rxchbondi_in(19 downto 0) => B"00000000000000000000",
+ rxchbondlevel_in(11 downto 0) => B"000000000000",
+ rxchbondmaster_in(3 downto 0) => B"0000",
+ rxchbondo_out(19 downto 0) => NLW_inst_rxchbondo_out_UNCONNECTED(19 downto 0),
+ rxchbondslave_in(3 downto 0) => B"0000",
+ rxckcaldone_out(0) => NLW_inst_rxckcaldone_out_UNCONNECTED(0),
+ rxckcalreset_in(0) => '0',
+ rxckcalstart_in(0) => '0',
+ rxclkcorcnt_out(7 downto 0) => NLW_inst_rxclkcorcnt_out_UNCONNECTED(7 downto 0),
+ rxcominitdet_out(3 downto 0) => NLW_inst_rxcominitdet_out_UNCONNECTED(3 downto 0),
+ rxcommadet_out(3 downto 0) => NLW_inst_rxcommadet_out_UNCONNECTED(3 downto 0),
+ rxcommadeten_in(3 downto 0) => B"1111",
+ rxcomsasdet_out(3 downto 0) => NLW_inst_rxcomsasdet_out_UNCONNECTED(3 downto 0),
+ rxcomwakedet_out(3 downto 0) => NLW_inst_rxcomwakedet_out_UNCONNECTED(3 downto 0),
+ rxctrl0_out(63 downto 0) => NLW_inst_rxctrl0_out_UNCONNECTED(63 downto 0),
+ rxctrl1_out(63 downto 0) => NLW_inst_rxctrl1_out_UNCONNECTED(63 downto 0),
+ rxctrl2_out(31 downto 0) => NLW_inst_rxctrl2_out_UNCONNECTED(31 downto 0),
+ rxctrl3_out(31 downto 0) => NLW_inst_rxctrl3_out_UNCONNECTED(31 downto 0),
+ rxdata_out(511 downto 0) => NLW_inst_rxdata_out_UNCONNECTED(511 downto 0),
+ rxdataextendrsvd_out(31 downto 0) => NLW_inst_rxdataextendrsvd_out_UNCONNECTED(31 downto 0),
+ rxdatavalid_out(7 downto 0) => NLW_inst_rxdatavalid_out_UNCONNECTED(7 downto 0),
+ rxdccforcestart_in(0) => '0',
+ rxdfeagcctrl_in(7 downto 0) => B"01010101",
+ rxdfeagchold_in(3 downto 0) => B"0000",
+ rxdfeagcovrden_in(3 downto 0) => B"0000",
+ rxdfecfokfcnum_in(0) => '0',
+ rxdfecfokfen_in(0) => '0',
+ rxdfecfokfpulse_in(0) => '0',
+ rxdfecfokhold_in(0) => '0',
+ rxdfecfokovren_in(0) => '0',
+ rxdfekhhold_in(0) => '0',
+ rxdfekhovrden_in(0) => '0',
+ rxdfelfhold_in(3 downto 0) => B"0000",
+ rxdfelfovrden_in(3 downto 0) => B"0000",
+ rxdfelpmreset_in(3 downto 0) => B"0000",
+ rxdfetap10hold_in(3 downto 0) => B"0000",
+ rxdfetap10ovrden_in(3 downto 0) => B"0000",
+ rxdfetap11hold_in(3 downto 0) => B"0000",
+ rxdfetap11ovrden_in(3 downto 0) => B"0000",
+ rxdfetap12hold_in(3 downto 0) => B"0000",
+ rxdfetap12ovrden_in(3 downto 0) => B"0000",
+ rxdfetap13hold_in(3 downto 0) => B"0000",
+ rxdfetap13ovrden_in(3 downto 0) => B"0000",
+ rxdfetap14hold_in(3 downto 0) => B"0000",
+ rxdfetap14ovrden_in(3 downto 0) => B"0000",
+ rxdfetap15hold_in(3 downto 0) => B"0000",
+ rxdfetap15ovrden_in(3 downto 0) => B"0000",
+ rxdfetap2hold_in(3 downto 0) => B"0000",
+ rxdfetap2ovrden_in(3 downto 0) => B"0000",
+ rxdfetap3hold_in(3 downto 0) => B"0000",
+ rxdfetap3ovrden_in(3 downto 0) => B"0000",
+ rxdfetap4hold_in(3 downto 0) => B"0000",
+ rxdfetap4ovrden_in(3 downto 0) => B"0000",
+ rxdfetap5hold_in(3 downto 0) => B"0000",
+ rxdfetap5ovrden_in(3 downto 0) => B"0000",
+ rxdfetap6hold_in(3 downto 0) => B"0000",
+ rxdfetap6ovrden_in(3 downto 0) => B"0000",
+ rxdfetap7hold_in(3 downto 0) => B"0000",
+ rxdfetap7ovrden_in(3 downto 0) => B"0000",
+ rxdfetap8hold_in(3 downto 0) => B"0000",
+ rxdfetap8ovrden_in(3 downto 0) => B"0000",
+ rxdfetap9hold_in(3 downto 0) => B"0000",
+ rxdfetap9ovrden_in(3 downto 0) => B"0000",
+ rxdfeuthold_in(3 downto 0) => B"0000",
+ rxdfeutovrden_in(3 downto 0) => B"0000",
+ rxdfevphold_in(3 downto 0) => B"0000",
+ rxdfevpovrden_in(3 downto 0) => B"0000",
+ rxdfevsen_in(3 downto 0) => B"0000",
+ rxdfexyden_in(3 downto 0) => B"1111",
+ rxdlybypass_in(3 downto 0) => B"1111",
+ rxdlyen_in(3 downto 0) => B"0000",
+ rxdlyovrden_in(3 downto 0) => B"0000",
+ rxdlysreset_in(3 downto 0) => B"0000",
+ rxdlysresetdone_out(3 downto 0) => NLW_inst_rxdlysresetdone_out_UNCONNECTED(3 downto 0),
+ rxelecidle_out(3 downto 0) => NLW_inst_rxelecidle_out_UNCONNECTED(3 downto 0),
+ rxelecidlemode_in(7 downto 0) => B"11111111",
+ rxeqtraining_in(0) => '0',
+ rxgearboxslip_in(3 downto 0) => B"0000",
+ rxheader_out(23 downto 0) => NLW_inst_rxheader_out_UNCONNECTED(23 downto 0),
+ rxheadervalid_out(7 downto 0) => NLW_inst_rxheadervalid_out_UNCONNECTED(7 downto 0),
+ rxlatclk_in(3 downto 0) => B"0000",
+ rxlfpstresetdet_out(0) => NLW_inst_rxlfpstresetdet_out_UNCONNECTED(0),
+ rxlfpsu2lpexitdet_out(0) => NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED(0),
+ rxlfpsu3wakedet_out(0) => NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED(0),
+ rxlpmen_in(3 downto 0) => B"0000",
+ rxlpmgchold_in(3 downto 0) => B"0000",
+ rxlpmgcovrden_in(3 downto 0) => B"0000",
+ rxlpmhfhold_in(3 downto 0) => B"0000",
+ rxlpmhfovrden_in(3 downto 0) => B"0000",
+ rxlpmlfhold_in(3 downto 0) => B"0000",
+ rxlpmlfklovrden_in(3 downto 0) => B"0000",
+ rxlpmoshold_in(3 downto 0) => B"0000",
+ rxlpmosovrden_in(3 downto 0) => B"0000",
+ rxmcommaalignen_in(3 downto 0) => B"0000",
+ rxmonitorout_out(27 downto 0) => NLW_inst_rxmonitorout_out_UNCONNECTED(27 downto 0),
+ rxmonitorsel_in(7 downto 0) => B"00000000",
+ rxoobreset_in(3 downto 0) => B"0000",
+ rxoscalreset_in(3 downto 0) => B"0000",
+ rxoshold_in(3 downto 0) => B"0000",
+ rxosintcfg_in(15 downto 0) => B"1101110111011101",
+ rxosintdone_out(3 downto 0) => NLW_inst_rxosintdone_out_UNCONNECTED(3 downto 0),
+ rxosinten_in(3 downto 0) => B"1111",
+ rxosinthold_in(3 downto 0) => B"0000",
+ rxosintovrden_in(3 downto 0) => B"0000",
+ rxosintstarted_out(3 downto 0) => NLW_inst_rxosintstarted_out_UNCONNECTED(3 downto 0),
+ rxosintstrobe_in(3 downto 0) => B"0000",
+ rxosintstrobedone_out(3 downto 0) => NLW_inst_rxosintstrobedone_out_UNCONNECTED(3 downto 0),
+ rxosintstrobestarted_out(3 downto 0) => NLW_inst_rxosintstrobestarted_out_UNCONNECTED(3 downto 0),
+ rxosinttestovrden_in(3 downto 0) => B"0000",
+ rxosovrden_in(3 downto 0) => B"0000",
+ rxoutclk_out(3 downto 0) => rxoutclk_out(3 downto 0),
+ rxoutclkfabric_out(3 downto 0) => NLW_inst_rxoutclkfabric_out_UNCONNECTED(3 downto 0),
+ rxoutclkpcs_out(3 downto 0) => NLW_inst_rxoutclkpcs_out_UNCONNECTED(3 downto 0),
+ rxoutclksel_in(11 downto 0) => B"010010010010",
+ rxpcommaalignen_in(3 downto 0) => B"0000",
+ rxpcsreset_in(3 downto 0) => B"0000",
+ rxpd_in(7 downto 0) => B"00000000",
+ rxphalign_in(3 downto 0) => B"0000",
+ rxphaligndone_out(3 downto 0) => NLW_inst_rxphaligndone_out_UNCONNECTED(3 downto 0),
+ rxphalignen_in(3 downto 0) => B"0000",
+ rxphalignerr_out(3 downto 0) => NLW_inst_rxphalignerr_out_UNCONNECTED(3 downto 0),
+ rxphdlypd_in(3 downto 0) => B"0000",
+ rxphdlyreset_in(3 downto 0) => B"0000",
+ rxphovrden_in(3 downto 0) => B"0000",
+ rxpllclksel_in(7 downto 0) => B"00000000",
+ rxpmareset_in(3 downto 0) => B"0000",
+ rxpmaresetdone_out(3 downto 0) => rxpmaresetdone_out(3 downto 0),
+ rxpolarity_in(3 downto 0) => rxpolarity_in(3 downto 0),
+ rxprbscntreset_in(3 downto 0) => B"0000",
+ rxprbserr_out(3 downto 0) => NLW_inst_rxprbserr_out_UNCONNECTED(3 downto 0),
+ rxprbslocked_out(3 downto 0) => NLW_inst_rxprbslocked_out_UNCONNECTED(3 downto 0),
+ rxprbssel_in(15 downto 0) => B"0000000000000000",
+ rxprgdivresetdone_out(3 downto 0) => NLW_inst_rxprgdivresetdone_out_UNCONNECTED(3 downto 0),
+ rxprogdivreset_in(3 downto 0) => B"0000",
+ rxqpien_in(3 downto 0) => B"0000",
+ rxqpisenn_out(3 downto 0) => NLW_inst_rxqpisenn_out_UNCONNECTED(3 downto 0),
+ rxqpisenp_out(3 downto 0) => NLW_inst_rxqpisenp_out_UNCONNECTED(3 downto 0),
+ rxrate_in(11 downto 0) => B"000000000000",
+ rxratedone_out(3 downto 0) => NLW_inst_rxratedone_out_UNCONNECTED(3 downto 0),
+ rxratemode_in(3 downto 0) => B"0000",
+ rxrecclk0_sel_out(1 downto 0) => NLW_inst_rxrecclk0_sel_out_UNCONNECTED(1 downto 0),
+ rxrecclk0sel_out(0) => NLW_inst_rxrecclk0sel_out_UNCONNECTED(0),
+ rxrecclk1_sel_out(1 downto 0) => NLW_inst_rxrecclk1_sel_out_UNCONNECTED(1 downto 0),
+ rxrecclk1sel_out(0) => NLW_inst_rxrecclk1sel_out_UNCONNECTED(0),
+ rxrecclkout_out(3 downto 0) => NLW_inst_rxrecclkout_out_UNCONNECTED(3 downto 0),
+ rxresetdone_out(3 downto 0) => rxresetdone_out(3 downto 0),
+ rxslide_in(3 downto 0) => rxslide_in(3 downto 0),
+ rxsliderdy_out(3 downto 0) => NLW_inst_rxsliderdy_out_UNCONNECTED(3 downto 0),
+ rxslipdone_out(3 downto 0) => NLW_inst_rxslipdone_out_UNCONNECTED(3 downto 0),
+ rxslipoutclk_in(3 downto 0) => B"0000",
+ rxslipoutclkrdy_out(3 downto 0) => NLW_inst_rxslipoutclkrdy_out_UNCONNECTED(3 downto 0),
+ rxslippma_in(3 downto 0) => B"0000",
+ rxslippmardy_out(3 downto 0) => NLW_inst_rxslippmardy_out_UNCONNECTED(3 downto 0),
+ rxstartofseq_out(7 downto 0) => NLW_inst_rxstartofseq_out_UNCONNECTED(7 downto 0),
+ rxstatus_out(11 downto 0) => NLW_inst_rxstatus_out_UNCONNECTED(11 downto 0),
+ rxsyncallin_in(3 downto 0) => B"0000",
+ rxsyncdone_out(3 downto 0) => NLW_inst_rxsyncdone_out_UNCONNECTED(3 downto 0),
+ rxsyncin_in(3 downto 0) => B"0000",
+ rxsyncmode_in(3 downto 0) => B"0000",
+ rxsyncout_out(3 downto 0) => NLW_inst_rxsyncout_out_UNCONNECTED(3 downto 0),
+ rxsysclksel_in(7 downto 0) => B"00000000",
+ rxtermination_in(0) => '0',
+ rxuserrdy_in(3 downto 0) => B"1111",
+ rxusrclk2_in(3 downto 0) => rxusrclk2_in(3 downto 0),
+ rxusrclk_in(3 downto 0) => rxusrclk_in(3 downto 0),
+ rxvalid_out(3 downto 0) => NLW_inst_rxvalid_out_UNCONNECTED(3 downto 0),
+ sdm0data_in(0) => '0',
+ sdm0finalout_out(0) => NLW_inst_sdm0finalout_out_UNCONNECTED(0),
+ sdm0reset_in(0) => '0',
+ sdm0testdata_out(0) => NLW_inst_sdm0testdata_out_UNCONNECTED(0),
+ sdm0toggle_in(0) => '0',
+ sdm0width_in(0) => '0',
+ sdm1data_in(0) => '0',
+ sdm1finalout_out(0) => NLW_inst_sdm1finalout_out_UNCONNECTED(0),
+ sdm1reset_in(0) => '0',
+ sdm1testdata_out(0) => NLW_inst_sdm1testdata_out_UNCONNECTED(0),
+ sdm1toggle_in(0) => '0',
+ sdm1width_in(0) => '0',
+ sigvalidclk_in(3 downto 0) => B"0000",
+ tcongpi_in(0) => '0',
+ tcongpo_out(0) => NLW_inst_tcongpo_out_UNCONNECTED(0),
+ tconpowerup_in(0) => '0',
+ tconreset_in(0) => '0',
+ tconrsvdin1_in(0) => '0',
+ tconrsvdout0_out(0) => NLW_inst_tconrsvdout0_out_UNCONNECTED(0),
+ tstin_in(79 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ tx8b10bbypass_in(31 downto 0) => B"00000000000000000000000000000000",
+ tx8b10ben_in(3 downto 0) => B"0000",
+ txbufdiffctrl_in(11 downto 0) => B"000000000000",
+ txbufstatus_out(7 downto 0) => NLW_inst_txbufstatus_out_UNCONNECTED(7 downto 0),
+ txcomfinish_out(3 downto 0) => NLW_inst_txcomfinish_out_UNCONNECTED(3 downto 0),
+ txcominit_in(3 downto 0) => B"0000",
+ txcomsas_in(3 downto 0) => B"0000",
+ txcomwake_in(3 downto 0) => B"0000",
+ txctrl0_in(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ txctrl1_in(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ txctrl2_in(31 downto 0) => B"00000000000000000000000000000000",
+ txdata_in(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ txdataextendrsvd_in(31 downto 0) => B"00000000000000000000000000000000",
+ txdccdone_out(0) => NLW_inst_txdccdone_out_UNCONNECTED(0),
+ txdccforcestart_in(0) => '0',
+ txdccreset_in(0) => '0',
+ txdeemph_in(3 downto 0) => B"0000",
+ txdetectrx_in(3 downto 0) => B"0000",
+ txdiffctrl_in(15 downto 0) => B"1100110011001100",
+ txdiffpd_in(3 downto 0) => B"0000",
+ txdlybypass_in(3 downto 0) => B"0000",
+ txdlyen_in(3 downto 0) => B"0000",
+ txdlyhold_in(3 downto 0) => B"0000",
+ txdlyovrden_in(3 downto 0) => B"0000",
+ txdlysreset_in(3 downto 0) => B"0000",
+ txdlysresetdone_out(3 downto 0) => NLW_inst_txdlysresetdone_out_UNCONNECTED(3 downto 0),
+ txdlyupdown_in(3 downto 0) => B"0000",
+ txelecidle_in(3 downto 0) => B"0000",
+ txelforcestart_in(0) => '0',
+ txheader_in(23 downto 0) => B"000000000000000000000000",
+ txinhibit_in(3 downto 0) => B"0000",
+ txlatclk_in(3 downto 0) => B"0000",
+ txlfpstreset_in(0) => '0',
+ txlfpsu2lpexit_in(0) => '0',
+ txlfpsu3wake_in(0) => '0',
+ txmaincursor_in(27 downto 0) => B"1000000100000010000001000000",
+ txmargin_in(11 downto 0) => B"000000000000",
+ txmuxdcdexhold_in(0) => '0',
+ txmuxdcdorwren_in(0) => '0',
+ txoneszeros_in(0) => '0',
+ txoutclk_out(3 downto 0) => txoutclk_out(3 downto 0),
+ txoutclkfabric_out(3 downto 0) => NLW_inst_txoutclkfabric_out_UNCONNECTED(3 downto 0),
+ txoutclkpcs_out(3 downto 0) => NLW_inst_txoutclkpcs_out_UNCONNECTED(3 downto 0),
+ txoutclksel_in(11 downto 0) => B"011011011011",
+ txpcsreset_in(3 downto 0) => B"0000",
+ txpd_in(7 downto 0) => B"00000000",
+ txpdelecidlemode_in(3 downto 0) => B"0000",
+ txphalign_in(3 downto 0) => B"0000",
+ txphaligndone_out(3 downto 0) => NLW_inst_txphaligndone_out_UNCONNECTED(3 downto 0),
+ txphalignen_in(3 downto 0) => B"0000",
+ txphdlypd_in(3 downto 0) => B"0000",
+ txphdlyreset_in(3 downto 0) => B"0000",
+ txphdlytstclk_in(3 downto 0) => B"0000",
+ txphinit_in(3 downto 0) => B"0000",
+ txphinitdone_out(3 downto 0) => NLW_inst_txphinitdone_out_UNCONNECTED(3 downto 0),
+ txphovrden_in(3 downto 0) => B"0000",
+ txpippmen_in(3 downto 0) => B"0000",
+ txpippmovrden_in(3 downto 0) => B"0000",
+ txpippmpd_in(3 downto 0) => B"0000",
+ txpippmsel_in(3 downto 0) => B"0000",
+ txpippmstepsize_in(19 downto 0) => B"00000000000000000000",
+ txpisopd_in(3 downto 0) => B"0000",
+ txpllclksel_in(7 downto 0) => B"10101010",
+ txpmareset_in(3 downto 0) => B"0000",
+ txpmaresetdone_out(3 downto 0) => txpmaresetdone_out(3 downto 0),
+ txpolarity_in(3 downto 0) => txpolarity_in(3 downto 0),
+ txpostcursor_in(19 downto 0) => B"00000000000000000000",
+ txpostcursorinv_in(3 downto 0) => B"0000",
+ txprbsforceerr_in(3 downto 0) => B"0000",
+ txprbssel_in(15 downto 0) => B"0000000000000000",
+ txprecursor_in(19 downto 0) => B"00000000000000000000",
+ txprecursorinv_in(3 downto 0) => B"0000",
+ txprgdivresetdone_out(3 downto 0) => NLW_inst_txprgdivresetdone_out_UNCONNECTED(3 downto 0),
+ txprogdivreset_in(3 downto 0) => B"0000",
+ txqpibiasen_in(3 downto 0) => B"0000",
+ txqpisenn_out(3 downto 0) => NLW_inst_txqpisenn_out_UNCONNECTED(3 downto 0),
+ txqpisenp_out(3 downto 0) => NLW_inst_txqpisenp_out_UNCONNECTED(3 downto 0),
+ txqpistrongpdown_in(3 downto 0) => B"0000",
+ txqpiweakpup_in(3 downto 0) => B"0000",
+ txrate_in(11 downto 0) => B"000000000000",
+ txratedone_out(3 downto 0) => NLW_inst_txratedone_out_UNCONNECTED(3 downto 0),
+ txratemode_in(3 downto 0) => B"0000",
+ txresetdone_out(3 downto 0) => txresetdone_out(3 downto 0),
+ txsequence_in(27 downto 0) => B"0000000000000000000000000000",
+ txswing_in(3 downto 0) => B"0000",
+ txsyncallin_in(3 downto 0) => B"0000",
+ txsyncdone_out(3 downto 0) => NLW_inst_txsyncdone_out_UNCONNECTED(3 downto 0),
+ txsyncin_in(3 downto 0) => B"0000",
+ txsyncmode_in(3 downto 0) => B"0000",
+ txsyncout_out(3 downto 0) => NLW_inst_txsyncout_out_UNCONNECTED(3 downto 0),
+ txsysclksel_in(7 downto 0) => B"11111111",
+ txuserrdy_in(3 downto 0) => B"1111",
+ txusrclk2_in(3 downto 0) => txusrclk2_in(3 downto 0),
+ txusrclk_in(3 downto 0) => txusrclk_in(3 downto 0),
+ ubcfgstreamen_in(0) => '0',
+ ubdaddr_out(0) => NLW_inst_ubdaddr_out_UNCONNECTED(0),
+ ubden_out(0) => NLW_inst_ubden_out_UNCONNECTED(0),
+ ubdi_out(0) => NLW_inst_ubdi_out_UNCONNECTED(0),
+ ubdo_in(0) => '0',
+ ubdrdy_in(0) => '0',
+ ubdwe_out(0) => NLW_inst_ubdwe_out_UNCONNECTED(0),
+ ubenable_in(0) => '0',
+ ubgpi_in(0) => '0',
+ ubintr_in(0) => '0',
+ ubiolmbrst_in(0) => '0',
+ ubmbrst_in(0) => '0',
+ ubmdmcapture_in(0) => '0',
+ ubmdmdbgrst_in(0) => '0',
+ ubmdmdbgupdate_in(0) => '0',
+ ubmdmregen_in(0) => '0',
+ ubmdmshift_in(0) => '0',
+ ubmdmsysrst_in(0) => '0',
+ ubmdmtck_in(0) => '0',
+ ubmdmtdi_in(0) => '0',
+ ubmdmtdo_out(0) => NLW_inst_ubmdmtdo_out_UNCONNECTED(0),
+ ubrsvdout_out(0) => NLW_inst_ubrsvdout_out_UNCONNECTED(0),
+ ubtxuart_out(0) => NLW_inst_ubtxuart_out_UNCONNECTED(0)
+ );
+end STRUCTURE;
diff --git a/sources/ip_cores/sim/KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_sim_netlist.vhdl b/sources/ip_cores/sim/KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_sim_netlist.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..a6bac3c45ac7c42ce2e9cbc8247588943265f767
--- /dev/null
+++ b/sources/ip_cores/sim/KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_sim_netlist.vhdl
@@ -0,0 +1,15229 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Fri Jun 14 11:28:32 2024
+-- Host : lbp001app.nikhef.nl running 64-bit unknown
+-- Command : write_vhdl -force -mode funcsim
+-- /localstore/et/franss/felix/firmware/Projects/FLX712_FELIG/FLX712_FELIG.gen/sources_1/ip/KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH/KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_sim_netlist.vhdl
+-- Design : KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xcku115-flvf1924-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rxresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_0 is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ txresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_0 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_0;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_0 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => txresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_1 is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_1 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_1;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_1 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rxresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_10 is
+ port (
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ in0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \FSM_sequential_sm_reset_rx_reg[0]\ : in STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[0]_0\ : in STD_LOGIC;
+ gtwiz_reset_rx_pll_and_datapath_dly : in STD_LOGIC;
+ sm_reset_rx_pll_timer_sat : in STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[0]_1\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_10 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_10;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_10 is
+ signal \FSM_sequential_sm_reset_rx[2]_i_3_n_0\ : STD_LOGIC;
+ signal gtwiz_reset_rx_datapath_dly : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+\FSM_sequential_sm_reset_rx[2]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFE400E4"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => \FSM_sequential_sm_reset_rx[2]_i_3_n_0\,
+ I2 => \FSM_sequential_sm_reset_rx_reg[0]\,
+ I3 => Q(2),
+ I4 => \FSM_sequential_sm_reset_rx_reg[0]_0\,
+ O => E(0)
+ );
+\FSM_sequential_sm_reset_rx[2]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0E0EFE0E"
+ )
+ port map (
+ I0 => gtwiz_reset_rx_datapath_dly,
+ I1 => gtwiz_reset_rx_pll_and_datapath_dly,
+ I2 => Q(0),
+ I3 => sm_reset_rx_pll_timer_sat,
+ I4 => \FSM_sequential_sm_reset_rx_reg[0]_1\,
+ O => \FSM_sequential_sm_reset_rx[2]_i_3_n_0\
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => in0,
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => gtwiz_reset_rx_datapath_dly,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_11 is
+ port (
+ gtwiz_reset_rx_pll_and_datapath_dly : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ in0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \p_0_in11_out__0\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_11 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_11;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_11 is
+ signal \^gtwiz_reset_rx_pll_and_datapath_dly\ : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_rx[0]_i_1\ : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_rx[1]_i_1\ : label is "soft_lutpair0";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+ gtwiz_reset_rx_pll_and_datapath_dly <= \^gtwiz_reset_rx_pll_and_datapath_dly\;
+\FSM_sequential_sm_reset_rx[0]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"F5A55E5E"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => \^gtwiz_reset_rx_pll_and_datapath_dly\,
+ I2 => Q(1),
+ I3 => \p_0_in11_out__0\,
+ I4 => Q(2),
+ O => D(0)
+ );
+\FSM_sequential_sm_reset_rx[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00FFF511"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => \^gtwiz_reset_rx_pll_and_datapath_dly\,
+ I2 => \p_0_in11_out__0\,
+ I3 => Q(1),
+ I4 => Q(0),
+ O => D(1)
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => in0,
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \^gtwiz_reset_rx_pll_and_datapath_dly\,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_12 is
+ port (
+ i_in_out_reg_0 : out STD_LOGIC;
+ in0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_pll_and_datapath_dly : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sm_reset_tx_pll_timer_sat : in STD_LOGIC;
+ \FSM_sequential_sm_reset_tx[2]_i_5\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_12 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_12;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_12 is
+ signal gtwiz_reset_tx_datapath_dly : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+\FSM_sequential_sm_reset_tx[2]_i_6\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0E0EFE0E"
+ )
+ port map (
+ I0 => gtwiz_reset_tx_datapath_dly,
+ I1 => gtwiz_reset_tx_pll_and_datapath_dly,
+ I2 => Q(0),
+ I3 => sm_reset_tx_pll_timer_sat,
+ I4 => \FSM_sequential_sm_reset_tx[2]_i_5\,
+ O => i_in_out_reg_0
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => in0,
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => gtwiz_reset_tx_datapath_dly,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_13 is
+ port (
+ gtwiz_reset_tx_pll_and_datapath_dly : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ in0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_13 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_13;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_13 is
+ signal \^gtwiz_reset_tx_pll_and_datapath_dly\ : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[0]_i_1\ : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_tx[1]_i_1\ : label is "soft_lutpair1";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+ gtwiz_reset_tx_pll_and_datapath_dly <= \^gtwiz_reset_tx_pll_and_datapath_dly\;
+\FSM_sequential_sm_reset_tx[0]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0F3E"
+ )
+ port map (
+ I0 => \^gtwiz_reset_tx_pll_and_datapath_dly\,
+ I1 => Q(2),
+ I2 => Q(0),
+ I3 => Q(1),
+ O => D(0)
+ );
+\FSM_sequential_sm_reset_tx[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0FF1"
+ )
+ port map (
+ I0 => \^gtwiz_reset_tx_pll_and_datapath_dly\,
+ I1 => Q(2),
+ I2 => Q(1),
+ I3 => Q(0),
+ O => D(1)
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => in0,
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \^gtwiz_reset_tx_pll_and_datapath_dly\,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_14 is
+ port (
+ \sm_reset_rx_timer_clr0__0\ : out STD_LOGIC;
+ gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxuserrdy_out_reg : in STD_LOGIC;
+ sm_reset_rx_timer_sat : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_14 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_14;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_14 is
+ signal gtwiz_reset_userclk_rx_active_sync : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => gtwiz_userclk_rx_active_in(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => gtwiz_reset_userclk_rx_active_sync,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+sm_reset_rx_timer_clr_i_3: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"40"
+ )
+ port map (
+ I0 => rxuserrdy_out_reg,
+ I1 => sm_reset_rx_timer_sat,
+ I2 => gtwiz_reset_userclk_rx_active_sync,
+ O => \sm_reset_rx_timer_clr0__0\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_15 is
+ port (
+ \FSM_sequential_sm_reset_tx_reg[1]\ : out STD_LOGIC;
+ \sm_reset_tx_timer_clr0__0\ : out STD_LOGIC;
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ gtwiz_reset_tx_any_sync : in STD_LOGIC;
+ GTHE3_CHANNEL_TXUSERRDY : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \gtwiz_reset_tx_done_int0__0\ : in STD_LOGIC;
+ \FSM_sequential_sm_reset_tx_reg[0]\ : in STD_LOGIC;
+ txuserrdy_out_reg : in STD_LOGIC;
+ sm_reset_tx_timer_sat : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_15 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_15;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_15 is
+ signal gtwiz_reset_userclk_tx_active_sync : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ signal \^sm_reset_tx_timer_clr0__0\ : STD_LOGIC;
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+ \sm_reset_tx_timer_clr0__0\ <= \^sm_reset_tx_timer_clr0__0\;
+\FSM_sequential_sm_reset_tx[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000F0CCF0AAF0"
+ )
+ port map (
+ I0 => \^sm_reset_tx_timer_clr0__0\,
+ I1 => \gtwiz_reset_tx_done_int0__0\,
+ I2 => \FSM_sequential_sm_reset_tx_reg[0]\,
+ I3 => Q(2),
+ I4 => Q(0),
+ I5 => Q(1),
+ O => E(0)
+ );
+\FSM_sequential_sm_reset_tx[2]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"40"
+ )
+ port map (
+ I0 => txuserrdy_out_reg,
+ I1 => sm_reset_tx_timer_sat,
+ I2 => gtwiz_reset_userclk_tx_active_sync,
+ O => \^sm_reset_tx_timer_clr0__0\
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => gtwiz_userclk_tx_active_in(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => gtwiz_reset_userclk_tx_active_sync,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+txuserrdy_out_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFF9F900001000"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => Q(0),
+ I2 => Q(2),
+ I3 => \^sm_reset_tx_timer_clr0__0\,
+ I4 => gtwiz_reset_tx_any_sync,
+ I5 => GTHE3_CHANNEL_TXUSERRDY(0),
+ O => \FSM_sequential_sm_reset_tx_reg[1]\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_16 is
+ port (
+ i_in_out_reg_0 : out STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[0]\ : out STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[2]\ : out STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[2]_0\ : out STD_LOGIC;
+ i_in_out_reg_1 : out STD_LOGIC;
+ i_in_meta_reg_0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \p_0_in11_out__0\ : in STD_LOGIC;
+ gtwiz_reset_rx_done_int_reg : in STD_LOGIC;
+ \sm_reset_rx_timer_clr0__0\ : in STD_LOGIC;
+ sm_reset_rx_timer_clr_reg : in STD_LOGIC;
+ sm_reset_rx_cdr_to_clr_reg : in STD_LOGIC;
+ sm_reset_rx_cdr_to_clr : in STD_LOGIC;
+ gtwiz_reset_rx_any_sync : in STD_LOGIC;
+ GTHE3_CHANNEL_GTRXRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \sm_reset_rx_timer_clr010_out__0\ : in STD_LOGIC;
+ sm_reset_rx_timer_sat : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_16 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_16;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_16 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ signal plllock_rx_sync : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_clr_i_2_n_0 : STD_LOGIC;
+ signal sm_reset_rx_timer_clr_i_2_n_0 : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_rx[2]_i_4\ : label is "soft_lutpair2";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+ attribute SOFT_HLUTNM of sm_reset_rx_cdr_to_clr_i_2 : label is "soft_lutpair2";
+begin
+\FSM_sequential_sm_reset_rx[2]_i_4\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00B0"
+ )
+ port map (
+ I0 => plllock_rx_sync,
+ I1 => Q(0),
+ I2 => sm_reset_rx_timer_sat,
+ I3 => sm_reset_rx_timer_clr_reg,
+ O => i_in_out_reg_1
+ );
+gtrxreset_out_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFBFFF00001514"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => Q(1),
+ I2 => Q(0),
+ I3 => sm_reset_rx_cdr_to_clr_i_2_n_0,
+ I4 => gtwiz_reset_rx_any_sync,
+ I5 => GTHE3_CHANNEL_GTRXRESET(0),
+ O => \FSM_sequential_sm_reset_rx_reg[2]_0\
+ );
+gtwiz_reset_rx_done_int_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"BFBFFFFF0C000000"
+ )
+ port map (
+ I0 => plllock_rx_sync,
+ I1 => Q(1),
+ I2 => Q(0),
+ I3 => \p_0_in11_out__0\,
+ I4 => Q(2),
+ I5 => gtwiz_reset_rx_done_int_reg,
+ O => i_in_out_reg_0
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta_reg_0,
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => plllock_rx_sync,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+sm_reset_rx_cdr_to_clr_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FBFFFFFF0000040F"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => sm_reset_rx_cdr_to_clr_i_2_n_0,
+ I2 => sm_reset_rx_cdr_to_clr_reg,
+ I3 => Q(0),
+ I4 => Q(1),
+ I5 => sm_reset_rx_cdr_to_clr,
+ O => \FSM_sequential_sm_reset_rx_reg[2]\
+ );
+sm_reset_rx_cdr_to_clr_i_2: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0800"
+ )
+ port map (
+ I0 => plllock_rx_sync,
+ I1 => Q(1),
+ I2 => sm_reset_rx_timer_clr_reg,
+ I3 => sm_reset_rx_timer_sat,
+ O => sm_reset_rx_cdr_to_clr_i_2_n_0
+ );
+sm_reset_rx_timer_clr_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAEFAAFF0AE0AA0F"
+ )
+ port map (
+ I0 => sm_reset_rx_timer_clr_i_2_n_0,
+ I1 => \sm_reset_rx_timer_clr0__0\,
+ I2 => Q(0),
+ I3 => Q(1),
+ I4 => Q(2),
+ I5 => sm_reset_rx_timer_clr_reg,
+ O => \FSM_sequential_sm_reset_rx_reg[0]\
+ );
+sm_reset_rx_timer_clr_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8F808F8F80808080"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => \p_0_in11_out__0\,
+ I2 => Q(2),
+ I3 => plllock_rx_sync,
+ I4 => Q(0),
+ I5 => \sm_reset_rx_timer_clr010_out__0\,
+ O => sm_reset_rx_timer_clr_i_2_n_0
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_17 is
+ port (
+ i_in_out_reg_0 : out STD_LOGIC;
+ \FSM_sequential_sm_reset_tx_reg[2]\ : out STD_LOGIC;
+ \FSM_sequential_sm_reset_tx_reg[0]\ : out STD_LOGIC;
+ i_in_out_reg_1 : out STD_LOGIC;
+ qpll1lock_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sm_reset_tx_timer_sat : in STD_LOGIC;
+ sm_reset_tx_timer_clr_reg : in STD_LOGIC;
+ \gtwiz_reset_tx_done_int0__0\ : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ gtwiz_reset_tx_done_int_reg : in STD_LOGIC;
+ \sm_reset_tx_timer_clr0__0\ : in STD_LOGIC;
+ gtwiz_reset_tx_any_sync : in STD_LOGIC;
+ GTHE3_CHANNEL_GTTXRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \FSM_sequential_sm_reset_tx_reg[0]_0\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_17 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_17;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_17 is
+ signal gttxreset_out_i_2_n_0 : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ signal plllock_tx_sync : STD_LOGIC;
+ signal sm_reset_tx_timer_clr_i_2_n_0 : STD_LOGIC;
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+\FSM_sequential_sm_reset_tx[2]_i_5\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00B0FFFF00B00000"
+ )
+ port map (
+ I0 => plllock_tx_sync,
+ I1 => Q(0),
+ I2 => sm_reset_tx_timer_sat,
+ I3 => sm_reset_tx_timer_clr_reg,
+ I4 => Q(1),
+ I5 => \FSM_sequential_sm_reset_tx_reg[0]_0\,
+ O => i_in_out_reg_1
+ );
+gttxreset_out_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"7F7F7F7F2A2A2A3E"
+ )
+ port map (
+ I0 => gttxreset_out_i_2_n_0,
+ I1 => Q(0),
+ I2 => Q(1),
+ I3 => gtwiz_reset_tx_any_sync,
+ I4 => Q(2),
+ I5 => GTHE3_CHANNEL_GTTXRESET(0),
+ O => \FSM_sequential_sm_reset_tx_reg[0]\
+ );
+gttxreset_out_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000002000000000"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_sat,
+ I1 => sm_reset_tx_timer_clr_reg,
+ I2 => plllock_tx_sync,
+ I3 => gtwiz_reset_tx_any_sync,
+ I4 => Q(2),
+ I5 => Q(1),
+ O => gttxreset_out_i_2_n_0
+ );
+gtwiz_reset_tx_done_int_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAFFFFFF0000C000"
+ )
+ port map (
+ I0 => plllock_tx_sync,
+ I1 => \gtwiz_reset_tx_done_int0__0\,
+ I2 => Q(0),
+ I3 => Q(2),
+ I4 => Q(1),
+ I5 => gtwiz_reset_tx_done_int_reg,
+ O => i_in_out_reg_0
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => qpll1lock_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => plllock_tx_sync,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+sm_reset_tx_timer_clr_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAAFFAEF0AA00AEF"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_clr_i_2_n_0,
+ I1 => \sm_reset_tx_timer_clr0__0\,
+ I2 => Q(2),
+ I3 => Q(1),
+ I4 => Q(0),
+ I5 => sm_reset_tx_timer_clr_reg,
+ O => \FSM_sequential_sm_reset_tx_reg[2]\
+ );
+sm_reset_tx_timer_clr_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F022F00000220022"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_sat,
+ I1 => sm_reset_tx_timer_clr_reg,
+ I2 => \gtwiz_reset_tx_done_int0__0\,
+ I3 => Q(2),
+ I4 => plllock_tx_sync,
+ I5 => Q(0),
+ O => sm_reset_tx_timer_clr_i_2_n_0
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_18 is
+ port (
+ i_in_out_reg_0 : out STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[2]\ : out STD_LOGIC;
+ i_in_out_reg_1 : out STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[2]_0\ : out STD_LOGIC;
+ i_in_meta_reg_0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ gtwiz_reset_rx_any_sync : in STD_LOGIC;
+ GTHE3_CHANNEL_RXPROGDIVRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sm_reset_rx_cdr_to_sat : in STD_LOGIC;
+ \sm_reset_rx_timer_clr0__0\ : in STD_LOGIC;
+ \p_0_in11_out__0\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_18 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_18;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_18 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal \^i_in_out_reg_0\ : STD_LOGIC;
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ signal \sm_reset_rx_cdr_to_clr0__0\ : STD_LOGIC;
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of rxprogdivreset_out_i_2 : label is "soft_lutpair3";
+ attribute SOFT_HLUTNM of sm_reset_rx_cdr_to_clr_i_3 : label is "soft_lutpair3";
+begin
+ i_in_out_reg_0 <= \^i_in_out_reg_0\;
+\FSM_sequential_sm_reset_rx[2]_i_5\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000F0F0FF00EEEE"
+ )
+ port map (
+ I0 => \^i_in_out_reg_0\,
+ I1 => sm_reset_rx_cdr_to_sat,
+ I2 => \sm_reset_rx_timer_clr0__0\,
+ I3 => \p_0_in11_out__0\,
+ I4 => Q(1),
+ I5 => Q(0),
+ O => i_in_out_reg_1
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta_reg_0,
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \^i_in_out_reg_0\,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+rxprogdivreset_out_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFDFF00001414"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => Q(1),
+ I2 => Q(0),
+ I3 => \sm_reset_rx_cdr_to_clr0__0\,
+ I4 => gtwiz_reset_rx_any_sync,
+ I5 => GTHE3_CHANNEL_RXPROGDIVRESET(0),
+ O => \FSM_sequential_sm_reset_rx_reg[2]\
+ );
+rxprogdivreset_out_i_2: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_sat,
+ I1 => \^i_in_out_reg_0\,
+ O => \sm_reset_rx_cdr_to_clr0__0\
+ );
+sm_reset_rx_cdr_to_clr_i_3: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"02"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => \^i_in_out_reg_0\,
+ I2 => sm_reset_rx_cdr_to_sat,
+ O => \FSM_sequential_sm_reset_rx_reg[2]_0\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_2 is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ txresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_2 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_2;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_2 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => txresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_3 is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_3 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_3;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_3 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rxresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_4 is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ txresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_4 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_4;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_4 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => txresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_5 is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_5 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_5;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_5 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rxresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_6 is
+ port (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ txresetdone_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_6 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_6;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_6 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => txresetdone_out(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0),
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_7 is
+ port (
+ \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[1]\ : out STD_LOGIC;
+ GTHE3_CHANNEL_TXPHALIGNDONE : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_7 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_7;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_7 is
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_out : STD_LOGIC;
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_error_out_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => i_in_out,
+ O => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[1]\
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => GTHE3_CHANNEL_TXPHALIGNDONE(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => i_in_out,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_8 is
+ port (
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\ : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ GTHE3_CHANNEL_TXSYNCDONE : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_8 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_8;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_8 is
+ signal \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\ : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx[0]_i_1\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx[1]_i_2\ : label is "soft_lutpair20";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\ <= \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\;
+\FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx[0]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0455"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\,
+ I2 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\,
+ I3 => Q(1),
+ O => D(0)
+ );
+\FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx[1]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"2622"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => Q(1),
+ I2 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\,
+ I3 => \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\,
+ O => D(1)
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => GTHE3_CHANNEL_TXSYNCDONE(0),
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_9 is
+ port (
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ in0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \FSM_sequential_sm_reset_all_reg[0]\ : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \FSM_sequential_sm_reset_all_reg[0]_0\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_9 : entity is "gtwizard_ultrascale_v1_7_18_bit_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_9;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_9 is
+ signal gtpowergood_sync : STD_LOGIC;
+ signal i_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of i_in_meta : signal is "true";
+ signal i_in_sync1 : STD_LOGIC;
+ attribute async_reg of i_in_sync1 : signal is "true";
+ signal i_in_sync2 : STD_LOGIC;
+ attribute async_reg of i_in_sync2 : signal is "true";
+ signal i_in_sync3 : STD_LOGIC;
+ attribute async_reg of i_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of i_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of i_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of i_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of i_in_sync3_reg : label is "yes";
+begin
+\FSM_sequential_sm_reset_all[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AF0FAF00CFFFCFFF"
+ )
+ port map (
+ I0 => gtpowergood_sync,
+ I1 => \FSM_sequential_sm_reset_all_reg[0]\,
+ I2 => Q(2),
+ I3 => Q(0),
+ I4 => \FSM_sequential_sm_reset_all_reg[0]_0\,
+ I5 => Q(1),
+ O => E(0)
+ );
+i_in_meta_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => in0,
+ Q => i_in_meta,
+ R => '0'
+ );
+i_in_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync3,
+ Q => gtpowergood_sync,
+ R => '0'
+ );
+i_in_sync1_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_meta,
+ Q => i_in_sync1,
+ R => '0'
+ );
+i_in_sync2_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync1,
+ Q => i_in_sync2,
+ R => '0'
+ );
+i_in_sync3_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => i_in_sync2,
+ Q => i_in_sync3,
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gthe3_channel is
+ port (
+ cplllock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxn_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxp_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtpowergood_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrlock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxratedone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXPHALIGNDONE : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txprgdivresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXSYNCDONE : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ GTHE3_CHANNEL_CPLLPD : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxn_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxp_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_GTRXRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_GTTXRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outrefclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outrefclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxcdrhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_RXPROGDIVRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxslide_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_RXUSERRDY : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXDLYSRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXPROGDIVRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXSYNCALLIN : in STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXUSERRDY : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 127 downto 0 );
+ loopback_in : in STD_LOGIC_VECTOR ( 11 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gthe3_channel : entity is "gtwizard_ultrascale_v1_7_18_gthe3_channel";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gthe3_channel;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gthe3_channel is
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_0\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_10\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_100\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_101\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_102\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_103\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_104\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_105\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_106\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_107\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_108\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_109\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_11\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_110\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_111\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_112\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_113\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_114\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_115\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_116\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_117\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_118\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_119\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_12\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_120\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_121\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_122\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_123\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_124\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_125\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_126\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_127\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_128\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_129\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_13\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_130\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_131\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_132\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_133\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_134\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_135\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_136\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_137\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_138\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_139\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_14\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_140\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_141\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_142\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_143\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_144\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_145\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_146\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_147\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_148\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_149\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_15\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_150\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_151\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_152\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_153\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_154\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_155\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_156\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_157\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_158\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_159\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_16\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_160\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_161\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_162\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_163\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_164\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_165\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_166\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_167\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_168\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_169\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_17\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_170\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_171\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_172\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_173\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_174\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_175\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_176\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_177\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_178\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_179\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_18\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_180\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_181\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_182\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_183\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_184\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_185\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_186\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_187\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_188\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_189\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_190\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_191\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_192\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_193\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_2\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_20\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_21\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_210\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_211\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_212\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_213\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_214\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_215\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_216\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_217\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_218\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_219\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_22\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_220\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_221\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_222\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_223\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_224\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_225\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_226\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_227\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_228\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_229\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_23\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_230\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_231\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_232\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_233\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_234\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_235\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_236\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_237\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_238\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_239\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_24\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_240\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_241\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_242\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_243\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_244\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_245\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_246\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_247\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_248\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_249\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_25\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_250\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_251\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_252\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_253\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_254\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_255\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_256\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_257\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_258\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_259\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_26\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_260\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_261\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_262\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_263\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_264\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_265\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_266\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_267\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_268\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_269\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_27\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_270\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_271\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_272\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_273\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_274\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_275\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_276\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_277\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_278\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_279\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_28\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_280\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_281\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_282\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_283\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_284\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_285\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_286\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_287\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_288\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_289\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_29\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_290\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_291\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_292\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_293\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_294\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_295\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_296\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_297\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_298\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_299\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_3\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_30\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_300\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_301\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_302\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_303\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_304\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_305\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_306\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_307\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_308\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_309\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_31\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_310\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_311\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_312\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_313\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_314\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_315\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_316\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_317\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_318\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_319\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_32\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_320\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_321\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_322\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_323\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_324\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_325\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_326\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_327\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_328\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_329\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_33\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_330\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_331\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_332\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_333\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_334\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_335\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_336\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_337\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_338\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_339\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_340\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_341\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_342\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_343\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_344\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_345\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_346\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_347\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_348\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_349\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_35\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_350\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_351\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_352\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_353\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_354\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_355\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_356\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_357\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_358\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_359\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_36\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_360\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_361\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_362\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_363\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_364\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_365\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_37\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_38\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_4\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_40\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_41\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_42\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_43\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_44\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_46\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_48\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_49\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_50\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_51\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_52\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_53\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_54\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_55\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_56\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_58\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_59\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_61\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_64\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_65\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_66\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_70\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_71\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_72\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_73\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_74\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_75\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_76\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_77\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_78\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_79\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_8\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_80\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_81\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_82\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_83\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_84\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_85\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_86\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_87\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_88\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_89\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_9\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_90\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_91\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_92\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_93\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_94\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_95\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_96\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_97\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_98\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_99\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_0\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_10\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_100\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_101\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_102\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_103\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_104\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_105\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_106\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_107\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_108\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_109\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_11\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_110\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_111\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_112\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_113\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_114\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_115\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_116\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_117\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_118\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_119\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_12\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_120\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_121\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_122\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_123\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_124\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_125\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_126\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_127\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_128\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_129\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_13\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_130\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_131\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_132\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_133\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_134\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_135\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_136\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_137\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_138\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_139\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_14\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_140\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_141\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_142\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_143\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_144\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_145\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_146\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_147\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_148\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_149\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_15\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_150\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_151\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_152\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_153\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_154\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_155\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_156\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_157\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_158\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_159\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_16\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_160\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_161\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_162\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_163\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_164\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_165\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_166\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_167\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_168\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_169\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_17\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_170\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_171\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_172\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_173\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_174\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_175\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_176\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_177\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_178\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_179\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_18\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_180\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_181\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_182\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_183\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_184\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_185\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_186\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_187\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_188\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_189\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_190\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_191\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_192\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_193\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_2\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_20\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_21\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_210\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_211\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_212\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_213\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_214\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_215\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_216\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_217\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_218\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_219\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_22\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_220\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_221\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_222\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_223\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_224\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_225\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_226\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_227\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_228\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_229\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_23\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_230\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_231\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_232\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_233\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_234\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_235\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_236\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_237\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_238\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_239\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_24\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_240\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_241\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_242\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_243\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_244\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_245\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_246\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_247\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_248\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_249\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_25\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_250\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_251\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_252\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_253\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_254\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_255\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_256\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_257\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_258\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_259\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_26\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_260\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_261\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_262\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_263\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_264\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_265\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_266\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_267\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_268\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_269\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_27\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_270\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_271\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_272\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_273\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_274\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_275\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_276\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_277\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_278\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_279\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_28\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_280\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_281\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_282\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_283\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_284\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_285\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_286\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_287\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_288\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_289\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_29\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_290\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_291\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_292\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_293\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_294\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_295\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_296\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_297\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_298\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_299\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_3\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_30\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_300\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_301\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_302\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_303\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_304\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_305\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_306\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_307\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_308\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_309\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_31\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_310\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_311\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_312\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_313\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_314\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_315\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_316\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_317\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_318\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_319\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_32\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_320\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_321\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_322\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_323\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_324\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_325\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_326\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_327\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_328\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_329\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_33\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_330\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_331\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_332\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_333\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_334\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_335\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_336\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_337\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_338\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_339\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_340\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_341\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_342\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_343\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_344\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_345\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_346\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_347\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_348\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_349\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_35\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_350\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_351\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_352\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_353\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_354\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_355\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_356\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_357\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_358\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_359\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_36\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_360\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_361\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_362\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_363\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_364\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_365\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_37\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_38\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_4\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_40\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_41\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_42\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_43\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_44\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_46\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_48\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_49\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_50\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_51\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_52\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_53\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_54\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_55\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_56\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_58\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_59\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_61\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_64\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_65\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_66\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_68\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_69\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_70\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_71\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_72\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_73\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_74\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_75\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_76\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_77\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_78\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_79\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_8\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_80\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_81\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_82\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_83\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_84\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_85\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_86\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_87\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_88\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_89\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_9\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_90\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_91\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_92\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_93\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_94\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_95\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_96\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_97\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_98\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_99\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_0\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_10\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_100\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_101\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_102\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_103\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_104\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_105\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_106\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_107\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_108\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_109\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_11\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_110\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_111\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_112\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_113\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_114\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_115\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_116\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_117\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_118\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_119\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_12\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_120\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_121\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_122\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_123\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_124\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_125\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_126\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_127\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_128\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_129\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_13\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_130\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_131\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_132\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_133\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_134\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_135\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_136\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_137\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_138\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_139\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_14\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_140\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_141\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_142\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_143\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_144\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_145\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_146\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_147\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_148\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_149\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_15\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_150\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_151\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_152\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_153\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_154\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_155\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_156\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_157\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_158\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_159\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_16\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_160\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_161\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_162\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_163\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_164\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_165\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_166\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_167\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_168\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_169\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_17\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_170\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_171\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_172\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_173\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_174\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_175\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_176\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_177\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_178\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_179\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_18\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_180\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_181\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_182\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_183\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_184\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_185\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_186\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_187\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_188\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_189\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_190\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_191\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_192\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_193\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_2\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_20\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_21\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_210\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_211\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_212\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_213\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_214\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_215\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_216\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_217\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_218\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_219\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_22\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_220\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_221\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_222\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_223\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_224\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_225\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_226\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_227\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_228\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_229\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_23\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_230\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_231\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_232\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_233\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_234\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_235\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_236\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_237\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_238\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_239\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_24\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_240\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_241\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_242\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_243\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_244\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_245\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_246\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_247\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_248\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_249\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_25\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_250\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_251\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_252\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_253\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_254\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_255\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_256\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_257\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_258\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_259\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_26\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_260\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_261\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_262\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_263\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_264\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_265\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_266\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_267\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_268\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_269\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_27\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_270\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_271\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_272\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_273\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_274\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_275\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_276\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_277\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_278\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_279\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_28\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_280\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_281\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_282\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_283\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_284\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_285\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_286\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_287\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_288\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_289\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_29\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_290\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_291\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_292\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_293\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_294\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_295\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_296\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_297\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_298\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_299\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_3\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_30\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_300\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_301\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_302\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_303\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_304\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_305\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_306\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_307\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_308\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_309\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_31\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_310\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_311\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_312\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_313\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_314\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_315\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_316\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_317\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_318\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_319\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_32\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_320\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_321\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_322\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_323\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_324\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_325\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_326\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_327\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_328\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_329\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_33\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_330\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_331\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_332\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_333\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_334\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_335\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_336\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_337\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_338\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_339\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_340\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_341\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_342\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_343\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_344\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_345\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_346\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_347\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_348\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_349\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_35\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_350\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_351\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_352\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_353\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_354\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_355\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_356\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_357\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_358\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_359\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_36\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_360\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_361\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_362\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_363\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_364\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_365\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_37\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_38\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_4\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_40\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_41\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_42\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_43\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_44\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_46\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_48\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_49\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_50\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_51\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_52\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_53\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_54\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_55\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_56\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_58\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_59\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_61\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_64\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_65\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_66\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_68\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_69\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_70\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_71\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_72\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_73\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_74\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_75\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_76\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_77\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_78\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_79\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_8\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_80\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_81\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_82\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_83\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_84\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_85\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_86\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_87\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_88\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_89\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_9\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_90\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_91\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_92\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_93\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_94\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_95\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_96\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_97\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_98\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_99\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_0\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_10\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_100\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_101\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_102\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_103\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_104\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_105\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_106\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_107\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_108\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_109\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_11\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_110\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_111\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_112\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_113\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_114\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_115\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_116\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_117\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_118\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_119\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_12\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_120\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_121\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_122\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_123\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_124\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_125\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_126\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_127\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_128\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_129\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_13\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_130\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_131\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_132\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_133\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_134\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_135\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_136\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_137\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_138\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_139\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_14\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_140\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_141\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_142\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_143\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_144\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_145\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_146\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_147\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_148\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_149\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_15\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_150\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_151\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_152\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_153\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_154\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_155\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_156\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_157\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_158\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_159\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_16\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_160\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_161\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_162\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_163\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_164\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_165\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_166\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_167\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_168\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_169\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_17\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_170\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_171\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_172\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_173\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_174\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_175\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_176\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_177\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_178\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_179\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_18\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_180\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_181\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_182\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_183\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_184\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_185\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_186\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_187\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_188\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_189\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_190\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_191\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_192\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_193\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_2\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_20\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_21\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_210\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_211\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_212\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_213\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_214\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_215\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_216\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_217\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_218\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_219\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_22\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_220\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_221\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_222\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_223\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_224\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_225\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_226\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_227\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_228\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_229\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_23\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_230\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_231\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_232\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_233\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_234\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_235\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_236\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_237\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_238\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_239\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_24\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_240\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_241\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_242\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_243\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_244\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_245\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_246\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_247\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_248\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_249\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_25\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_250\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_251\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_252\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_253\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_254\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_255\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_256\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_257\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_258\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_259\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_26\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_260\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_261\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_262\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_263\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_264\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_265\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_266\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_267\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_268\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_269\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_27\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_270\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_271\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_272\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_273\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_274\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_275\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_276\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_277\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_278\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_279\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_28\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_280\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_281\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_282\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_283\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_284\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_285\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_286\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_287\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_288\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_289\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_29\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_290\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_291\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_292\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_293\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_294\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_295\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_296\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_297\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_298\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_299\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_3\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_30\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_300\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_301\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_302\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_303\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_304\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_305\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_306\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_307\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_308\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_309\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_31\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_310\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_311\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_312\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_313\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_314\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_315\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_316\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_317\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_318\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_319\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_32\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_320\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_321\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_322\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_323\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_324\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_325\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_326\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_327\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_328\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_329\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_33\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_330\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_331\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_332\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_333\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_334\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_335\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_336\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_337\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_338\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_339\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_340\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_341\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_342\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_343\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_344\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_345\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_346\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_347\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_348\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_349\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_35\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_350\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_351\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_352\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_353\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_354\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_355\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_356\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_357\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_358\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_359\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_36\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_360\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_361\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_362\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_363\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_364\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_365\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_37\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_38\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_4\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_40\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_41\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_42\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_43\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_44\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_46\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_48\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_49\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_50\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_51\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_52\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_53\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_54\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_55\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_56\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_58\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_59\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_61\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_64\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_65\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_66\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_68\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_69\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_70\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_71\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_72\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_73\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_74\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_75\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_76\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_77\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_78\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_79\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_8\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_80\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_81\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_82\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_83\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_84\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_85\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_86\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_87\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_88\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_89\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_9\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_90\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_91\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_92\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_93\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_94\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_95\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_96\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_97\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_98\ : STD_LOGIC;
+ signal \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_99\ : STD_LOGIC;
+ attribute BOX_TYPE : string;
+ attribute BOX_TYPE of \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST\ : label is "PRIMITIVE";
+ attribute BOX_TYPE of \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST\ : label is "PRIMITIVE";
+begin
+\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST\: unisim.vcomponents.GTHE3_CHANNEL
+ generic map(
+ ACJTAG_DEBUG_MODE => '0',
+ ACJTAG_MODE => '0',
+ ACJTAG_RESET => '0',
+ ADAPT_CFG0 => X"F800",
+ ADAPT_CFG1 => X"0000",
+ ALIGN_COMMA_DOUBLE => "FALSE",
+ ALIGN_COMMA_ENABLE => B"0000000000",
+ ALIGN_COMMA_WORD => 1,
+ ALIGN_MCOMMA_DET => "FALSE",
+ ALIGN_MCOMMA_VALUE => B"1010000011",
+ ALIGN_PCOMMA_DET => "FALSE",
+ ALIGN_PCOMMA_VALUE => B"0101111100",
+ A_RXOSCALRESET => '0',
+ A_RXPROGDIVRESET => '0',
+ A_TXPROGDIVRESET => '0',
+ CBCC_DATA_SOURCE_SEL => "ENCODED",
+ CDR_SWAP_MODE_EN => '0',
+ CHAN_BOND_KEEP_ALIGN => "FALSE",
+ CHAN_BOND_MAX_SKEW => 1,
+ CHAN_BOND_SEQ_1_1 => B"0000000000",
+ CHAN_BOND_SEQ_1_2 => B"0000000000",
+ CHAN_BOND_SEQ_1_3 => B"0000000000",
+ CHAN_BOND_SEQ_1_4 => B"0000000000",
+ CHAN_BOND_SEQ_1_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_1 => B"0000000000",
+ CHAN_BOND_SEQ_2_2 => B"0000000000",
+ CHAN_BOND_SEQ_2_3 => B"0000000000",
+ CHAN_BOND_SEQ_2_4 => B"0000000000",
+ CHAN_BOND_SEQ_2_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_USE => "FALSE",
+ CHAN_BOND_SEQ_LEN => 1,
+ CLK_CORRECT_USE => "FALSE",
+ CLK_COR_KEEP_IDLE => "FALSE",
+ CLK_COR_MAX_LAT => 6,
+ CLK_COR_MIN_LAT => 4,
+ CLK_COR_PRECEDENCE => "TRUE",
+ CLK_COR_REPEAT_WAIT => 0,
+ CLK_COR_SEQ_1_1 => B"0000000000",
+ CLK_COR_SEQ_1_2 => B"0000000000",
+ CLK_COR_SEQ_1_3 => B"0000000000",
+ CLK_COR_SEQ_1_4 => B"0000000000",
+ CLK_COR_SEQ_1_ENABLE => B"1111",
+ CLK_COR_SEQ_2_1 => B"0000000000",
+ CLK_COR_SEQ_2_2 => B"0000000000",
+ CLK_COR_SEQ_2_3 => B"0000000000",
+ CLK_COR_SEQ_2_4 => B"0000000000",
+ CLK_COR_SEQ_2_ENABLE => B"1111",
+ CLK_COR_SEQ_2_USE => "FALSE",
+ CLK_COR_SEQ_LEN => 1,
+ CPLL_CFG0 => X"67F8",
+ CPLL_CFG1 => X"A4AC",
+ CPLL_CFG2 => X"5007",
+ CPLL_CFG3 => B"00" & X"0",
+ CPLL_FBDIV => 2,
+ CPLL_FBDIV_45 => 4,
+ CPLL_INIT_CFG0 => X"02B2",
+ CPLL_INIT_CFG1 => X"00",
+ CPLL_LOCK_CFG => X"01E8",
+ CPLL_REFCLK_DIV => 1,
+ DDI_CTRL => B"00",
+ DDI_REALIGN_WAIT => 15,
+ DEC_MCOMMA_DETECT => "FALSE",
+ DEC_PCOMMA_DETECT => "FALSE",
+ DEC_VALID_COMMA_ONLY => "FALSE",
+ DFE_D_X_REL_POS => '0',
+ DFE_VCM_COMP_EN => '0',
+ DMONITOR_CFG0 => B"00" & X"00",
+ DMONITOR_CFG1 => X"00",
+ ES_CLK_PHASE_SEL => '0',
+ ES_CONTROL => B"000000",
+ ES_ERRDET_EN => "FALSE",
+ ES_EYE_SCAN_EN => "FALSE",
+ ES_HORZ_OFFSET => X"000",
+ ES_PMA_CFG => B"0000000000",
+ ES_PRESCALE => B"00000",
+ ES_QUALIFIER0 => X"0000",
+ ES_QUALIFIER1 => X"0000",
+ ES_QUALIFIER2 => X"0000",
+ ES_QUALIFIER3 => X"0000",
+ ES_QUALIFIER4 => X"0000",
+ ES_QUAL_MASK0 => X"0000",
+ ES_QUAL_MASK1 => X"0000",
+ ES_QUAL_MASK2 => X"0000",
+ ES_QUAL_MASK3 => X"0000",
+ ES_QUAL_MASK4 => X"0000",
+ ES_SDATA_MASK0 => X"0000",
+ ES_SDATA_MASK1 => X"0000",
+ ES_SDATA_MASK2 => X"0000",
+ ES_SDATA_MASK3 => X"0000",
+ ES_SDATA_MASK4 => X"0000",
+ EVODD_PHI_CFG => B"00000000000",
+ EYE_SCAN_SWAP_EN => '0',
+ FTS_DESKEW_SEQ_ENABLE => B"1111",
+ FTS_LANE_DESKEW_CFG => B"1111",
+ FTS_LANE_DESKEW_EN => "FALSE",
+ GEARBOX_MODE => B"00000",
+ GM_BIAS_SELECT => '0',
+ LOCAL_MASTER => '1',
+ OOBDIVCTL => B"00",
+ OOB_PWRUP => '0',
+ PCI3_AUTO_REALIGN => "OVR_1K_BLK",
+ PCI3_PIPE_RX_ELECIDLE => '0',
+ PCI3_RX_ASYNC_EBUF_BYPASS => B"00",
+ PCI3_RX_ELECIDLE_EI2_ENABLE => '0',
+ PCI3_RX_ELECIDLE_H2L_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_H2L_DISABLE => B"000",
+ PCI3_RX_ELECIDLE_HI_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_LP4_DISABLE => '0',
+ PCI3_RX_FIFO_DISABLE => '0',
+ PCIE_BUFG_DIV_CTRL => X"1000",
+ PCIE_RXPCS_CFG_GEN3 => X"02A4",
+ PCIE_RXPMA_CFG => X"000A",
+ PCIE_TXPCS_CFG_GEN3 => X"24A4",
+ PCIE_TXPMA_CFG => X"000A",
+ PCS_PCIE_EN => "FALSE",
+ PCS_RSVD0 => B"0000000000000000",
+ PCS_RSVD1 => B"000",
+ PD_TRANS_TIME_FROM_P2 => X"03C",
+ PD_TRANS_TIME_NONE_P2 => X"19",
+ PD_TRANS_TIME_TO_P2 => X"64",
+ PLL_SEL_MODE_GEN12 => B"00",
+ PLL_SEL_MODE_GEN3 => B"11",
+ PMA_RSV1 => X"F000",
+ PROCESS_PAR => B"010",
+ RATE_SW_USE_DRP => '1',
+ RESET_POWERSAVE_DISABLE => '0',
+ RXBUFRESET_TIME => B"00011",
+ RXBUF_ADDR_MODE => "FAST",
+ RXBUF_EIDLE_HI_CNT => B"1000",
+ RXBUF_EIDLE_LO_CNT => B"0000",
+ RXBUF_EN => "TRUE",
+ RXBUF_RESET_ON_CB_CHANGE => "TRUE",
+ RXBUF_RESET_ON_COMMAALIGN => "FALSE",
+ RXBUF_RESET_ON_EIDLE => "FALSE",
+ RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ RXBUF_THRESH_OVFLW => 61,
+ RXBUF_THRESH_OVRD => "TRUE",
+ RXBUF_THRESH_UNDFLW => 1,
+ RXCDRFREQRESET_TIME => B"00001",
+ RXCDRPHRESET_TIME => B"00001",
+ RXCDR_CFG0 => X"0000",
+ RXCDR_CFG0_GEN3 => X"0000",
+ RXCDR_CFG1 => X"0000",
+ RXCDR_CFG1_GEN3 => X"0000",
+ RXCDR_CFG2 => X"07E6",
+ RXCDR_CFG2_GEN3 => X"07E6",
+ RXCDR_CFG3 => X"0000",
+ RXCDR_CFG3_GEN3 => X"0000",
+ RXCDR_CFG4 => X"0000",
+ RXCDR_CFG4_GEN3 => X"0000",
+ RXCDR_CFG5 => X"0000",
+ RXCDR_CFG5_GEN3 => X"0000",
+ RXCDR_FR_RESET_ON_EIDLE => '0',
+ RXCDR_HOLD_DURING_EIDLE => '0',
+ RXCDR_LOCK_CFG0 => X"4480",
+ RXCDR_LOCK_CFG1 => X"5FFF",
+ RXCDR_LOCK_CFG2 => X"77C3",
+ RXCDR_PH_RESET_ON_EIDLE => '0',
+ RXCFOK_CFG0 => X"4000",
+ RXCFOK_CFG1 => X"0065",
+ RXCFOK_CFG2 => X"002E",
+ RXDFELPMRESET_TIME => B"0001111",
+ RXDFELPM_KL_CFG0 => X"0000",
+ RXDFELPM_KL_CFG1 => X"0002",
+ RXDFELPM_KL_CFG2 => X"0000",
+ RXDFE_CFG0 => X"0A00",
+ RXDFE_CFG1 => X"0000",
+ RXDFE_GC_CFG0 => X"0000",
+ RXDFE_GC_CFG1 => X"7870",
+ RXDFE_GC_CFG2 => X"0000",
+ RXDFE_H2_CFG0 => X"0000",
+ RXDFE_H2_CFG1 => X"0000",
+ RXDFE_H3_CFG0 => X"4000",
+ RXDFE_H3_CFG1 => X"0000",
+ RXDFE_H4_CFG0 => X"2000",
+ RXDFE_H4_CFG1 => X"0003",
+ RXDFE_H5_CFG0 => X"2000",
+ RXDFE_H5_CFG1 => X"0003",
+ RXDFE_H6_CFG0 => X"2000",
+ RXDFE_H6_CFG1 => X"0000",
+ RXDFE_H7_CFG0 => X"2000",
+ RXDFE_H7_CFG1 => X"0000",
+ RXDFE_H8_CFG0 => X"2000",
+ RXDFE_H8_CFG1 => X"0000",
+ RXDFE_H9_CFG0 => X"2000",
+ RXDFE_H9_CFG1 => X"0000",
+ RXDFE_HA_CFG0 => X"2000",
+ RXDFE_HA_CFG1 => X"0000",
+ RXDFE_HB_CFG0 => X"2000",
+ RXDFE_HB_CFG1 => X"0000",
+ RXDFE_HC_CFG0 => X"0000",
+ RXDFE_HC_CFG1 => X"0000",
+ RXDFE_HD_CFG0 => X"0000",
+ RXDFE_HD_CFG1 => X"0000",
+ RXDFE_HE_CFG0 => X"0000",
+ RXDFE_HE_CFG1 => X"0000",
+ RXDFE_HF_CFG0 => X"0000",
+ RXDFE_HF_CFG1 => X"0000",
+ RXDFE_OS_CFG0 => X"8000",
+ RXDFE_OS_CFG1 => X"0000",
+ RXDFE_UT_CFG0 => X"8000",
+ RXDFE_UT_CFG1 => X"0003",
+ RXDFE_VP_CFG0 => X"AA00",
+ RXDFE_VP_CFG1 => X"0033",
+ RXDLY_CFG => X"001F",
+ RXDLY_LCFG => X"0030",
+ RXELECIDLE_CFG => "Sigcfg_4",
+ RXGBOX_FIFO_INIT_RD_ADDR => 4,
+ RXGEARBOX_EN => "FALSE",
+ RXISCANRESET_TIME => B"00001",
+ RXLPM_CFG => X"0000",
+ RXLPM_GC_CFG => X"1000",
+ RXLPM_KH_CFG0 => X"0000",
+ RXLPM_KH_CFG1 => X"0002",
+ RXLPM_OS_CFG0 => X"8000",
+ RXLPM_OS_CFG1 => X"0002",
+ RXOOB_CFG => B"000000110",
+ RXOOB_CLK_CFG => "PMA",
+ RXOSCALRESET_TIME => B"00011",
+ RXOUT_DIV => 1,
+ RXPCSRESET_TIME => B"00011",
+ RXPHBEACON_CFG => X"0000",
+ RXPHDLY_CFG => X"2020",
+ RXPHSAMP_CFG => X"2100",
+ RXPHSLIP_CFG => X"6622",
+ RXPH_MONITOR_SEL => B"00000",
+ RXPI_CFG0 => B"00",
+ RXPI_CFG1 => B"00",
+ RXPI_CFG2 => B"00",
+ RXPI_CFG3 => B"00",
+ RXPI_CFG4 => '1',
+ RXPI_CFG5 => '1',
+ RXPI_CFG6 => B"011",
+ RXPI_LPM => '0',
+ RXPI_VREFSEL => '0',
+ RXPMACLK_SEL => "DATA",
+ RXPMARESET_TIME => B"00011",
+ RXPRBS_ERR_LOOPBACK => '0',
+ RXPRBS_LINKACQ_CNT => 15,
+ RXSLIDE_AUTO_WAIT => 7,
+ RXSLIDE_MODE => "OFF",
+ RXSYNC_MULTILANE => '1',
+ RXSYNC_OVRD => '0',
+ RXSYNC_SKIP_DA => '0',
+ RX_AFE_CM_EN => '0',
+ RX_BIAS_CFG0 => X"0AB4",
+ RX_BUFFER_CFG => B"000000",
+ RX_CAPFF_SARC_ENB => '0',
+ RX_CLK25_DIV => 13,
+ RX_CLKMUX_EN => '1',
+ RX_CLK_SLIP_OVRD => B"00000",
+ RX_CM_BUF_CFG => B"1010",
+ RX_CM_BUF_PD => '0',
+ RX_CM_SEL => B"11",
+ RX_CM_TRIM => B"1010",
+ RX_CTLE3_LPF => B"00000001",
+ RX_DATA_WIDTH => 16,
+ RX_DDI_SEL => B"000000",
+ RX_DEFER_RESET_BUF_EN => "TRUE",
+ RX_DFELPM_CFG0 => B"0110",
+ RX_DFELPM_CFG1 => '1',
+ RX_DFELPM_KLKH_AGC_STUP_EN => '1',
+ RX_DFE_AGC_CFG0 => B"10",
+ RX_DFE_AGC_CFG1 => B"100",
+ RX_DFE_KL_LPM_KH_CFG0 => B"01",
+ RX_DFE_KL_LPM_KH_CFG1 => B"100",
+ RX_DFE_KL_LPM_KL_CFG0 => B"01",
+ RX_DFE_KL_LPM_KL_CFG1 => B"100",
+ RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
+ RX_DISPERR_SEQ_MATCH => "TRUE",
+ RX_DIVRESET_TIME => B"00001",
+ RX_EN_HI_LR => '0',
+ RX_EYESCAN_VS_CODE => B"0000000",
+ RX_EYESCAN_VS_NEG_DIR => '0',
+ RX_EYESCAN_VS_RANGE => B"00",
+ RX_EYESCAN_VS_UT_SIGN => '0',
+ RX_FABINT_USRCLK_FLOP => '0',
+ RX_INT_DATAWIDTH => 0,
+ RX_PMA_POWER_SAVE => '0',
+ RX_PROGDIV_CFG => 0.000000,
+ RX_SAMPLE_PERIOD => B"111",
+ RX_SIG_VALID_DLY => 11,
+ RX_SUM_DFETAPREP_EN => '0',
+ RX_SUM_IREF_TUNE => B"0000",
+ RX_SUM_RES_CTRL => B"00",
+ RX_SUM_VCMTUNE => B"0000",
+ RX_SUM_VCM_OVWR => '0',
+ RX_SUM_VREF_TUNE => B"000",
+ RX_TUNE_AFE_OS => B"10",
+ RX_WIDEMODE_CDR => '0',
+ RX_XCLK_SEL => "RXDES",
+ SAS_MAX_COM => 64,
+ SAS_MIN_COM => 36,
+ SATA_BURST_SEQ_LEN => B"1110",
+ SATA_BURST_VAL => B"100",
+ SATA_CPLL_CFG => "VCO_3000MHZ",
+ SATA_EIDLE_VAL => B"100",
+ SATA_MAX_BURST => 8,
+ SATA_MAX_INIT => 21,
+ SATA_MAX_WAKE => 7,
+ SATA_MIN_BURST => 4,
+ SATA_MIN_INIT => 12,
+ SATA_MIN_WAKE => 4,
+ SHOW_REALIGN_COMMA => "TRUE",
+ SIM_MODE => "FAST",
+ SIM_RECEIVER_DETECT_PASS => "TRUE",
+ SIM_RESET_SPEEDUP => "TRUE",
+ SIM_TX_EIDLE_DRIVE_LEVEL => '0',
+ SIM_VERSION => 2,
+ TAPDLY_SET_TX => B"00",
+ TEMPERATUR_PAR => B"0010",
+ TERM_RCAL_CFG => B"100001000010000",
+ TERM_RCAL_OVRD => B"000",
+ TRANS_TIME_RATE => X"0E",
+ TST_RSV0 => X"00",
+ TST_RSV1 => X"00",
+ TXBUF_EN => "FALSE",
+ TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ TXDLY_CFG => X"0009",
+ TXDLY_LCFG => X"0050",
+ TXDRVBIAS_N => B"1010",
+ TXDRVBIAS_P => B"1010",
+ TXFIFO_ADDR_CFG => "LOW",
+ TXGBOX_FIFO_INIT_RD_ADDR => 4,
+ TXGEARBOX_EN => "FALSE",
+ TXOUT_DIV => 1,
+ TXPCSRESET_TIME => B"00011",
+ TXPHDLY_CFG0 => X"2020",
+ TXPHDLY_CFG1 => X"0075",
+ TXPH_CFG => X"0980",
+ TXPH_MONITOR_SEL => B"00000",
+ TXPI_CFG0 => B"00",
+ TXPI_CFG1 => B"00",
+ TXPI_CFG2 => B"00",
+ TXPI_CFG3 => '1',
+ TXPI_CFG4 => '1',
+ TXPI_CFG5 => B"000",
+ TXPI_GRAY_SEL => '0',
+ TXPI_INVSTROBE_SEL => '1',
+ TXPI_LPM => '0',
+ TXPI_PPMCLK_SEL => "TXUSRCLK2",
+ TXPI_PPM_CFG => B"00000000",
+ TXPI_SYNFREQ_PPM => B"001",
+ TXPI_VREFSEL => '0',
+ TXPMARESET_TIME => B"00011",
+ TXSYNC_MULTILANE => '1',
+ TXSYNC_OVRD => '0',
+ TXSYNC_SKIP_DA => '0',
+ TX_CLK25_DIV => 10,
+ TX_CLKMUX_EN => '1',
+ TX_DATA_WIDTH => 32,
+ TX_DCD_CFG => B"000010",
+ TX_DCD_EN => '0',
+ TX_DEEMPH0 => B"000000",
+ TX_DEEMPH1 => B"000000",
+ TX_DIVRESET_TIME => B"00001",
+ TX_DRIVE_MODE => "DIRECT",
+ TX_EIDLE_ASSERT_DELAY => B"100",
+ TX_EIDLE_DEASSERT_DELAY => B"011",
+ TX_EML_PHI_TUNE => '0',
+ TX_FABINT_USRCLK_FLOP => '0',
+ TX_IDLE_DATA_ZERO => '0',
+ TX_INT_DATAWIDTH => 1,
+ TX_LOOPBACK_DRIVE_HIZ => "FALSE",
+ TX_MAINCURSOR_SEL => '0',
+ TX_MARGIN_FULL_0 => B"1001111",
+ TX_MARGIN_FULL_1 => B"1001110",
+ TX_MARGIN_FULL_2 => B"1001100",
+ TX_MARGIN_FULL_3 => B"1001010",
+ TX_MARGIN_FULL_4 => B"1001000",
+ TX_MARGIN_LOW_0 => B"1000110",
+ TX_MARGIN_LOW_1 => B"1000101",
+ TX_MARGIN_LOW_2 => B"1000011",
+ TX_MARGIN_LOW_3 => B"1000010",
+ TX_MARGIN_LOW_4 => B"1000000",
+ TX_MODE_SEL => B"000",
+ TX_PMADATA_OPT => '0',
+ TX_PMA_POWER_SAVE => '0',
+ TX_PROGCLK_SEL => "PREPI",
+ TX_PROGDIV_CFG => 16.000000,
+ TX_QPI_STATUS_EN => '0',
+ TX_RXDETECT_CFG => B"00" & X"032",
+ TX_RXDETECT_REF => B"100",
+ TX_SAMPLE_PERIOD => B"111",
+ TX_SARC_LPBK_ENB => '0',
+ TX_XCLK_SEL => "TXUSR",
+ USE_PCS_CLK_PHASE_SEL => '0',
+ WB_MODE => B"00"
+ )
+ port map (
+ BUFGTCE(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_289\,
+ BUFGTCE(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_290\,
+ BUFGTCE(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_291\,
+ BUFGTCEMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_292\,
+ BUFGTCEMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_293\,
+ BUFGTCEMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_294\,
+ BUFGTDIV(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_357\,
+ BUFGTDIV(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_358\,
+ BUFGTDIV(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_359\,
+ BUFGTDIV(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_360\,
+ BUFGTDIV(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_361\,
+ BUFGTDIV(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_362\,
+ BUFGTDIV(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_363\,
+ BUFGTDIV(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_364\,
+ BUFGTDIV(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_365\,
+ BUFGTRESET(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_295\,
+ BUFGTRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_296\,
+ BUFGTRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_297\,
+ BUFGTRSTMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_298\,
+ BUFGTRSTMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_299\,
+ BUFGTRSTMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_300\,
+ CFGRESET => '0',
+ CLKRSVD0 => '0',
+ CLKRSVD1 => '0',
+ CPLLFBCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_0\,
+ CPLLLOCK => cplllock_out(0),
+ CPLLLOCKDETCLK => '0',
+ CPLLLOCKEN => '1',
+ CPLLPD => GTHE3_CHANNEL_CPLLPD(0),
+ CPLLREFCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_2\,
+ CPLLREFCLKSEL(2 downto 0) => B"001",
+ CPLLRESET => '0',
+ DMONFIFORESET => '0',
+ DMONITORCLK => '0',
+ DMONITOROUT(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_258\,
+ DMONITOROUT(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_259\,
+ DMONITOROUT(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_260\,
+ DMONITOROUT(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_261\,
+ DMONITOROUT(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_262\,
+ DMONITOROUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_263\,
+ DMONITOROUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_264\,
+ DMONITOROUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_265\,
+ DMONITOROUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_266\,
+ DMONITOROUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_267\,
+ DMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_268\,
+ DMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_269\,
+ DMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_270\,
+ DMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_271\,
+ DMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_272\,
+ DMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_273\,
+ DMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_274\,
+ DRPADDR(8 downto 0) => B"000000000",
+ DRPCLK => drpclk_in(0),
+ DRPDI(15 downto 0) => B"0000000000000000",
+ DRPDO(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_210\,
+ DRPDO(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_211\,
+ DRPDO(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_212\,
+ DRPDO(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_213\,
+ DRPDO(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_214\,
+ DRPDO(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_215\,
+ DRPDO(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_216\,
+ DRPDO(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_217\,
+ DRPDO(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_218\,
+ DRPDO(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_219\,
+ DRPDO(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_220\,
+ DRPDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_221\,
+ DRPDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_222\,
+ DRPDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_223\,
+ DRPDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_224\,
+ DRPDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_225\,
+ DRPEN => '0',
+ DRPRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_3\,
+ DRPWE => '0',
+ EVODDPHICALDONE => '0',
+ EVODDPHICALSTART => '0',
+ EVODDPHIDRDEN => '0',
+ EVODDPHIDWREN => '0',
+ EVODDPHIXRDEN => '0',
+ EVODDPHIXWREN => '0',
+ EYESCANDATAERROR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_4\,
+ EYESCANMODE => '0',
+ EYESCANRESET => '0',
+ EYESCANTRIGGER => '0',
+ GTGREFCLK => '0',
+ GTHRXN => gthrxn_in(0),
+ GTHRXP => gthrxp_in(0),
+ GTHTXN => gthtxn_out(0),
+ GTHTXP => gthtxp_out(0),
+ GTNORTHREFCLK0 => '0',
+ GTNORTHREFCLK1 => '0',
+ GTPOWERGOOD => gtpowergood_out(0),
+ GTREFCLK0 => gtrefclk0_in(0),
+ GTREFCLK1 => '0',
+ GTREFCLKMONITOR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_8\,
+ GTRESETSEL => '0',
+ GTRSVD(15 downto 0) => B"0000000000000000",
+ GTRXRESET => GTHE3_CHANNEL_GTRXRESET(0),
+ GTSOUTHREFCLK0 => '0',
+ GTSOUTHREFCLK1 => '0',
+ GTTXRESET => GTHE3_CHANNEL_GTTXRESET(0),
+ LOOPBACK(2 downto 0) => loopback_in(2 downto 0),
+ LPBKRXTXSEREN => '0',
+ LPBKTXRXSEREN => '0',
+ PCIEEQRXEQADAPTDONE => '0',
+ PCIERATEGEN3 => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_9\,
+ PCIERATEIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_10\,
+ PCIERATEQPLLPD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_275\,
+ PCIERATEQPLLPD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_276\,
+ PCIERATEQPLLRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_277\,
+ PCIERATEQPLLRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_278\,
+ PCIERSTIDLE => '0',
+ PCIERSTTXSYNCSTART => '0',
+ PCIESYNCTXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_11\,
+ PCIEUSERGEN3RDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_12\,
+ PCIEUSERPHYSTATUSRST => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_13\,
+ PCIEUSERRATEDONE => '0',
+ PCIEUSERRATESTART => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_14\,
+ PCSRSVDIN(15 downto 0) => B"0000000000000000",
+ PCSRSVDIN2(4 downto 0) => B"00000",
+ PCSRSVDOUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_70\,
+ PCSRSVDOUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_71\,
+ PCSRSVDOUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_72\,
+ PCSRSVDOUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_73\,
+ PCSRSVDOUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_74\,
+ PCSRSVDOUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_75\,
+ PCSRSVDOUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_76\,
+ PCSRSVDOUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_77\,
+ PCSRSVDOUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_78\,
+ PCSRSVDOUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_79\,
+ PCSRSVDOUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_80\,
+ PCSRSVDOUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_81\,
+ PHYSTATUS => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_15\,
+ PINRSRVDAS(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_325\,
+ PINRSRVDAS(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_326\,
+ PINRSRVDAS(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_327\,
+ PINRSRVDAS(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_328\,
+ PINRSRVDAS(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_329\,
+ PINRSRVDAS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_330\,
+ PINRSRVDAS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_331\,
+ PINRSRVDAS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_332\,
+ PMARSVDIN(4 downto 0) => B"00000",
+ QPLL0CLK => qpll0outclk_out(0),
+ QPLL0REFCLK => qpll0outrefclk_out(0),
+ QPLL1CLK => qpll1outclk_out(0),
+ QPLL1REFCLK => qpll1outrefclk_out(0),
+ RESETEXCEPTION => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_16\,
+ RESETOVRD => '0',
+ RSTCLKENTX => '0',
+ RX8B10BEN => '0',
+ RXBUFRESET => '0',
+ RXBUFSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_301\,
+ RXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_302\,
+ RXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_303\,
+ RXBYTEISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_17\,
+ RXBYTEREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_18\,
+ RXCDRFREQRESET => '0',
+ RXCDRHOLD => rxcdrhold_in(0),
+ RXCDRLOCK => rxcdrlock_out(0),
+ RXCDROVRDEN => '0',
+ RXCDRPHDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_20\,
+ RXCDRRESET => '0',
+ RXCDRRESETRSV => '0',
+ RXCHANBONDSEQ => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_21\,
+ RXCHANISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_22\,
+ RXCHANREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_23\,
+ RXCHBONDEN => '0',
+ RXCHBONDI(4 downto 0) => B"00000",
+ RXCHBONDLEVEL(2 downto 0) => B"000",
+ RXCHBONDMASTER => '0',
+ RXCHBONDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_307\,
+ RXCHBONDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_308\,
+ RXCHBONDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_309\,
+ RXCHBONDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_310\,
+ RXCHBONDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_311\,
+ RXCHBONDSLAVE => '0',
+ RXCLKCORCNT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_279\,
+ RXCLKCORCNT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_280\,
+ RXCOMINITDET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_24\,
+ RXCOMMADET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_25\,
+ RXCOMMADETEN => '0',
+ RXCOMSASDET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_26\,
+ RXCOMWAKEDET => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_27\,
+ RXCTRL0(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_226\,
+ RXCTRL0(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_227\,
+ RXCTRL0(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_228\,
+ RXCTRL0(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_229\,
+ RXCTRL0(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_230\,
+ RXCTRL0(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_231\,
+ RXCTRL0(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_232\,
+ RXCTRL0(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_233\,
+ RXCTRL0(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_234\,
+ RXCTRL0(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_235\,
+ RXCTRL0(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_236\,
+ RXCTRL0(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_237\,
+ RXCTRL0(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_238\,
+ RXCTRL0(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_239\,
+ RXCTRL0(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_240\,
+ RXCTRL0(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_241\,
+ RXCTRL1(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_242\,
+ RXCTRL1(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_243\,
+ RXCTRL1(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_244\,
+ RXCTRL1(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_245\,
+ RXCTRL1(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_246\,
+ RXCTRL1(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_247\,
+ RXCTRL1(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_248\,
+ RXCTRL1(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_249\,
+ RXCTRL1(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_250\,
+ RXCTRL1(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_251\,
+ RXCTRL1(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_252\,
+ RXCTRL1(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_253\,
+ RXCTRL1(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_254\,
+ RXCTRL1(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_255\,
+ RXCTRL1(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_256\,
+ RXCTRL1(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_257\,
+ RXCTRL2(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_333\,
+ RXCTRL2(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_334\,
+ RXCTRL2(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_335\,
+ RXCTRL2(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_336\,
+ RXCTRL2(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_337\,
+ RXCTRL2(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_338\,
+ RXCTRL2(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_339\,
+ RXCTRL2(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_340\,
+ RXCTRL3(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_341\,
+ RXCTRL3(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_342\,
+ RXCTRL3(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_343\,
+ RXCTRL3(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_344\,
+ RXCTRL3(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_345\,
+ RXCTRL3(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_346\,
+ RXCTRL3(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_347\,
+ RXCTRL3(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_348\,
+ RXDATA(127) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_82\,
+ RXDATA(126) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_83\,
+ RXDATA(125) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_84\,
+ RXDATA(124) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_85\,
+ RXDATA(123) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_86\,
+ RXDATA(122) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_87\,
+ RXDATA(121) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_88\,
+ RXDATA(120) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_89\,
+ RXDATA(119) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_90\,
+ RXDATA(118) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_91\,
+ RXDATA(117) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_92\,
+ RXDATA(116) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_93\,
+ RXDATA(115) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_94\,
+ RXDATA(114) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_95\,
+ RXDATA(113) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_96\,
+ RXDATA(112) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_97\,
+ RXDATA(111) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_98\,
+ RXDATA(110) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_99\,
+ RXDATA(109) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_100\,
+ RXDATA(108) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_101\,
+ RXDATA(107) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_102\,
+ RXDATA(106) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_103\,
+ RXDATA(105) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_104\,
+ RXDATA(104) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_105\,
+ RXDATA(103) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_106\,
+ RXDATA(102) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_107\,
+ RXDATA(101) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_108\,
+ RXDATA(100) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_109\,
+ RXDATA(99) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_110\,
+ RXDATA(98) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_111\,
+ RXDATA(97) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_112\,
+ RXDATA(96) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_113\,
+ RXDATA(95) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_114\,
+ RXDATA(94) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_115\,
+ RXDATA(93) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_116\,
+ RXDATA(92) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_117\,
+ RXDATA(91) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_118\,
+ RXDATA(90) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_119\,
+ RXDATA(89) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_120\,
+ RXDATA(88) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_121\,
+ RXDATA(87) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_122\,
+ RXDATA(86) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_123\,
+ RXDATA(85) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_124\,
+ RXDATA(84) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_125\,
+ RXDATA(83) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_126\,
+ RXDATA(82) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_127\,
+ RXDATA(81) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_128\,
+ RXDATA(80) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_129\,
+ RXDATA(79) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_130\,
+ RXDATA(78) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_131\,
+ RXDATA(77) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_132\,
+ RXDATA(76) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_133\,
+ RXDATA(75) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_134\,
+ RXDATA(74) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_135\,
+ RXDATA(73) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_136\,
+ RXDATA(72) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_137\,
+ RXDATA(71) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_138\,
+ RXDATA(70) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_139\,
+ RXDATA(69) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_140\,
+ RXDATA(68) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_141\,
+ RXDATA(67) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_142\,
+ RXDATA(66) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_143\,
+ RXDATA(65) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_144\,
+ RXDATA(64) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_145\,
+ RXDATA(63) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_146\,
+ RXDATA(62) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_147\,
+ RXDATA(61) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_148\,
+ RXDATA(60) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_149\,
+ RXDATA(59) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_150\,
+ RXDATA(58) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_151\,
+ RXDATA(57) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_152\,
+ RXDATA(56) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_153\,
+ RXDATA(55) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_154\,
+ RXDATA(54) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_155\,
+ RXDATA(53) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_156\,
+ RXDATA(52) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_157\,
+ RXDATA(51) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_158\,
+ RXDATA(50) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_159\,
+ RXDATA(49) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_160\,
+ RXDATA(48) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_161\,
+ RXDATA(47) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_162\,
+ RXDATA(46) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_163\,
+ RXDATA(45) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_164\,
+ RXDATA(44) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_165\,
+ RXDATA(43) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_166\,
+ RXDATA(42) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_167\,
+ RXDATA(41) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_168\,
+ RXDATA(40) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_169\,
+ RXDATA(39) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_170\,
+ RXDATA(38) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_171\,
+ RXDATA(37) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_172\,
+ RXDATA(36) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_173\,
+ RXDATA(35) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_174\,
+ RXDATA(34) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_175\,
+ RXDATA(33) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_176\,
+ RXDATA(32) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_177\,
+ RXDATA(31) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_178\,
+ RXDATA(30) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_179\,
+ RXDATA(29) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_180\,
+ RXDATA(28) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_181\,
+ RXDATA(27) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_182\,
+ RXDATA(26) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_183\,
+ RXDATA(25) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_184\,
+ RXDATA(24) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_185\,
+ RXDATA(23) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_186\,
+ RXDATA(22) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_187\,
+ RXDATA(21) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_188\,
+ RXDATA(20) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_189\,
+ RXDATA(19) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_190\,
+ RXDATA(18) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_191\,
+ RXDATA(17) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_192\,
+ RXDATA(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_193\,
+ RXDATA(15 downto 0) => gtwiz_userdata_rx_out(15 downto 0),
+ RXDATAEXTENDRSVD(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_349\,
+ RXDATAEXTENDRSVD(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_350\,
+ RXDATAEXTENDRSVD(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_351\,
+ RXDATAEXTENDRSVD(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_352\,
+ RXDATAEXTENDRSVD(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_353\,
+ RXDATAEXTENDRSVD(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_354\,
+ RXDATAEXTENDRSVD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_355\,
+ RXDATAEXTENDRSVD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_356\,
+ RXDATAVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_281\,
+ RXDATAVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_282\,
+ RXDFEAGCCTRL(1 downto 0) => B"01",
+ RXDFEAGCHOLD => '0',
+ RXDFEAGCOVRDEN => '0',
+ RXDFELFHOLD => '0',
+ RXDFELFOVRDEN => '0',
+ RXDFELPMRESET => '0',
+ RXDFETAP10HOLD => '0',
+ RXDFETAP10OVRDEN => '0',
+ RXDFETAP11HOLD => '0',
+ RXDFETAP11OVRDEN => '0',
+ RXDFETAP12HOLD => '0',
+ RXDFETAP12OVRDEN => '0',
+ RXDFETAP13HOLD => '0',
+ RXDFETAP13OVRDEN => '0',
+ RXDFETAP14HOLD => '0',
+ RXDFETAP14OVRDEN => '0',
+ RXDFETAP15HOLD => '0',
+ RXDFETAP15OVRDEN => '0',
+ RXDFETAP2HOLD => '0',
+ RXDFETAP2OVRDEN => '0',
+ RXDFETAP3HOLD => '0',
+ RXDFETAP3OVRDEN => '0',
+ RXDFETAP4HOLD => '0',
+ RXDFETAP4OVRDEN => '0',
+ RXDFETAP5HOLD => '0',
+ RXDFETAP5OVRDEN => '0',
+ RXDFETAP6HOLD => '0',
+ RXDFETAP6OVRDEN => '0',
+ RXDFETAP7HOLD => '0',
+ RXDFETAP7OVRDEN => '0',
+ RXDFETAP8HOLD => '0',
+ RXDFETAP8OVRDEN => '0',
+ RXDFETAP9HOLD => '0',
+ RXDFETAP9OVRDEN => '0',
+ RXDFEUTHOLD => '0',
+ RXDFEUTOVRDEN => '0',
+ RXDFEVPHOLD => '0',
+ RXDFEVPOVRDEN => '0',
+ RXDFEVSEN => '0',
+ RXDFEXYDEN => '1',
+ RXDLYBYPASS => '1',
+ RXDLYEN => '0',
+ RXDLYOVRDEN => '0',
+ RXDLYSRESET => '0',
+ RXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_28\,
+ RXELECIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_29\,
+ RXELECIDLEMODE(1 downto 0) => B"11",
+ RXGEARBOXSLIP => '0',
+ RXHEADER(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_312\,
+ RXHEADER(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_313\,
+ RXHEADER(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_314\,
+ RXHEADER(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_315\,
+ RXHEADER(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_316\,
+ RXHEADER(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_317\,
+ RXHEADERVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_283\,
+ RXHEADERVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_284\,
+ RXLATCLK => '0',
+ RXLPMEN => '0',
+ RXLPMGCHOLD => '0',
+ RXLPMGCOVRDEN => '0',
+ RXLPMHFHOLD => '0',
+ RXLPMHFOVRDEN => '0',
+ RXLPMLFHOLD => '0',
+ RXLPMLFKLOVRDEN => '0',
+ RXLPMOSHOLD => '0',
+ RXLPMOSOVRDEN => '0',
+ RXMCOMMAALIGNEN => '0',
+ RXMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_318\,
+ RXMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_319\,
+ RXMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_320\,
+ RXMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_321\,
+ RXMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_322\,
+ RXMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_323\,
+ RXMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_324\,
+ RXMONITORSEL(1 downto 0) => B"00",
+ RXOOBRESET => '0',
+ RXOSCALRESET => '0',
+ RXOSHOLD => '0',
+ RXOSINTCFG(3 downto 0) => B"1101",
+ RXOSINTDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_30\,
+ RXOSINTEN => '1',
+ RXOSINTHOLD => '0',
+ RXOSINTOVRDEN => '0',
+ RXOSINTSTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_31\,
+ RXOSINTSTROBE => '0',
+ RXOSINTSTROBEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_32\,
+ RXOSINTSTROBESTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_33\,
+ RXOSINTTESTOVRDEN => '0',
+ RXOSOVRDEN => '0',
+ RXOUTCLK => rxoutclk_out(0),
+ RXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_35\,
+ RXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_36\,
+ RXOUTCLKSEL(2 downto 0) => B"010",
+ RXPCOMMAALIGNEN => '0',
+ RXPCSRESET => '0',
+ RXPD(1 downto 0) => B"00",
+ RXPHALIGN => '0',
+ RXPHALIGNDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_37\,
+ RXPHALIGNEN => '0',
+ RXPHALIGNERR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_38\,
+ RXPHDLYPD => '1',
+ RXPHDLYRESET => '0',
+ RXPHOVRDEN => '0',
+ RXPLLCLKSEL(1 downto 0) => B"00",
+ RXPMARESET => '0',
+ RXPMARESETDONE => rxpmaresetdone_out(0),
+ RXPOLARITY => rxpolarity_in(0),
+ RXPRBSCNTRESET => '0',
+ RXPRBSERR => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_40\,
+ RXPRBSLOCKED => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_41\,
+ RXPRBSSEL(3 downto 0) => B"0000",
+ RXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_42\,
+ RXPROGDIVRESET => GTHE3_CHANNEL_RXPROGDIVRESET(0),
+ RXQPIEN => '0',
+ RXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_43\,
+ RXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_44\,
+ RXRATE(2 downto 0) => B"000",
+ RXRATEDONE => rxratedone_out(0),
+ RXRATEMODE => '0',
+ RXRECCLKOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_46\,
+ RXRESETDONE => rxresetdone_out(0),
+ RXSLIDE => rxslide_in(0),
+ RXSLIDERDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_48\,
+ RXSLIPDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_49\,
+ RXSLIPOUTCLK => '0',
+ RXSLIPOUTCLKRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_50\,
+ RXSLIPPMA => '0',
+ RXSLIPPMARDY => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_51\,
+ RXSTARTOFSEQ(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_285\,
+ RXSTARTOFSEQ(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_286\,
+ RXSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_304\,
+ RXSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_305\,
+ RXSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_306\,
+ RXSYNCALLIN => '0',
+ RXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_52\,
+ RXSYNCIN => '0',
+ RXSYNCMODE => '0',
+ RXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_53\,
+ RXSYSCLKSEL(1 downto 0) => B"00",
+ RXUSERRDY => GTHE3_CHANNEL_RXUSERRDY(0),
+ RXUSRCLK => rxusrclk_in(0),
+ RXUSRCLK2 => rxusrclk2_in(0),
+ RXVALID => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_54\,
+ SIGVALIDCLK => '0',
+ TSTIN(19 downto 0) => B"00000000000000000000",
+ TX8B10BBYPASS(7 downto 0) => B"00000000",
+ TX8B10BEN => '0',
+ TXBUFDIFFCTRL(2 downto 0) => B"000",
+ TXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_287\,
+ TXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_288\,
+ TXCOMFINISH => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_55\,
+ TXCOMINIT => '0',
+ TXCOMSAS => '0',
+ TXCOMWAKE => '0',
+ TXCTRL0(15 downto 0) => B"0000000000000000",
+ TXCTRL1(15 downto 0) => B"0000000000000000",
+ TXCTRL2(7 downto 0) => B"00000000",
+ TXDATA(127 downto 32) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ TXDATA(31 downto 0) => gtwiz_userdata_tx_in(31 downto 0),
+ TXDATAEXTENDRSVD(7 downto 0) => B"00000000",
+ TXDEEMPH => '0',
+ TXDETECTRX => '0',
+ TXDIFFCTRL(3 downto 0) => B"1100",
+ TXDIFFPD => '0',
+ TXDLYBYPASS => '0',
+ TXDLYEN => '0',
+ TXDLYHOLD => '0',
+ TXDLYOVRDEN => '0',
+ TXDLYSRESET => GTHE3_CHANNEL_TXDLYSRESET(0),
+ TXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_56\,
+ TXDLYUPDOWN => '0',
+ TXELECIDLE => '0',
+ TXHEADER(5 downto 0) => B"000000",
+ TXINHIBIT => '0',
+ TXLATCLK => '0',
+ TXMAINCURSOR(6 downto 0) => B"1000000",
+ TXMARGIN(2 downto 0) => B"000",
+ TXOUTCLK => txoutclk_out(0),
+ TXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_58\,
+ TXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_59\,
+ TXOUTCLKSEL(2 downto 0) => B"101",
+ TXPCSRESET => '0',
+ TXPD(1 downto 0) => B"00",
+ TXPDELECIDLEMODE => '0',
+ TXPHALIGN => '0',
+ TXPHALIGNDONE => GTHE3_CHANNEL_TXPHALIGNDONE(0),
+ TXPHALIGNEN => '0',
+ TXPHDLYPD => '0',
+ TXPHDLYRESET => '0',
+ TXPHDLYTSTCLK => '0',
+ TXPHINIT => '0',
+ TXPHINITDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_61\,
+ TXPHOVRDEN => '0',
+ TXPIPPMEN => '0',
+ TXPIPPMOVRDEN => '0',
+ TXPIPPMPD => '0',
+ TXPIPPMSEL => '0',
+ TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
+ TXPISOPD => '0',
+ TXPLLCLKSEL(1 downto 0) => B"10",
+ TXPMARESET => '0',
+ TXPMARESETDONE => txpmaresetdone_out(0),
+ TXPOLARITY => txpolarity_in(0),
+ TXPOSTCURSOR(4 downto 0) => B"00000",
+ TXPOSTCURSORINV => '0',
+ TXPRBSFORCEERR => '0',
+ TXPRBSSEL(3 downto 0) => B"0000",
+ TXPRECURSOR(4 downto 0) => B"00000",
+ TXPRECURSORINV => '0',
+ TXPRGDIVRESETDONE => txprgdivresetdone_out(0),
+ TXPROGDIVRESET => GTHE3_CHANNEL_TXPROGDIVRESET(0),
+ TXQPIBIASEN => '0',
+ TXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_64\,
+ TXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_65\,
+ TXQPISTRONGPDOWN => '0',
+ TXQPIWEAKPUP => '0',
+ TXRATE(2 downto 0) => B"000",
+ TXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_66\,
+ TXRATEMODE => '0',
+ TXRESETDONE => txresetdone_out(0),
+ TXSEQUENCE(6 downto 0) => B"0000000",
+ TXSWING => '0',
+ TXSYNCALLIN => GTHE3_CHANNEL_TXSYNCALLIN(0),
+ TXSYNCDONE => GTHE3_CHANNEL_TXSYNCDONE(0),
+ TXSYNCIN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYNCMODE => '1',
+ TXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYSCLKSEL(1 downto 0) => B"11",
+ TXUSERRDY => GTHE3_CHANNEL_TXUSERRDY(0),
+ TXUSRCLK => txusrclk_in(0),
+ TXUSRCLK2 => txusrclk2_in(0)
+ );
+\gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST\: unisim.vcomponents.GTHE3_CHANNEL
+ generic map(
+ ACJTAG_DEBUG_MODE => '0',
+ ACJTAG_MODE => '0',
+ ACJTAG_RESET => '0',
+ ADAPT_CFG0 => X"F800",
+ ADAPT_CFG1 => X"0000",
+ ALIGN_COMMA_DOUBLE => "FALSE",
+ ALIGN_COMMA_ENABLE => B"0000000000",
+ ALIGN_COMMA_WORD => 1,
+ ALIGN_MCOMMA_DET => "FALSE",
+ ALIGN_MCOMMA_VALUE => B"1010000011",
+ ALIGN_PCOMMA_DET => "FALSE",
+ ALIGN_PCOMMA_VALUE => B"0101111100",
+ A_RXOSCALRESET => '0',
+ A_RXPROGDIVRESET => '0',
+ A_TXPROGDIVRESET => '0',
+ CBCC_DATA_SOURCE_SEL => "ENCODED",
+ CDR_SWAP_MODE_EN => '0',
+ CHAN_BOND_KEEP_ALIGN => "FALSE",
+ CHAN_BOND_MAX_SKEW => 1,
+ CHAN_BOND_SEQ_1_1 => B"0000000000",
+ CHAN_BOND_SEQ_1_2 => B"0000000000",
+ CHAN_BOND_SEQ_1_3 => B"0000000000",
+ CHAN_BOND_SEQ_1_4 => B"0000000000",
+ CHAN_BOND_SEQ_1_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_1 => B"0000000000",
+ CHAN_BOND_SEQ_2_2 => B"0000000000",
+ CHAN_BOND_SEQ_2_3 => B"0000000000",
+ CHAN_BOND_SEQ_2_4 => B"0000000000",
+ CHAN_BOND_SEQ_2_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_USE => "FALSE",
+ CHAN_BOND_SEQ_LEN => 1,
+ CLK_CORRECT_USE => "FALSE",
+ CLK_COR_KEEP_IDLE => "FALSE",
+ CLK_COR_MAX_LAT => 6,
+ CLK_COR_MIN_LAT => 4,
+ CLK_COR_PRECEDENCE => "TRUE",
+ CLK_COR_REPEAT_WAIT => 0,
+ CLK_COR_SEQ_1_1 => B"0000000000",
+ CLK_COR_SEQ_1_2 => B"0000000000",
+ CLK_COR_SEQ_1_3 => B"0000000000",
+ CLK_COR_SEQ_1_4 => B"0000000000",
+ CLK_COR_SEQ_1_ENABLE => B"1111",
+ CLK_COR_SEQ_2_1 => B"0000000000",
+ CLK_COR_SEQ_2_2 => B"0000000000",
+ CLK_COR_SEQ_2_3 => B"0000000000",
+ CLK_COR_SEQ_2_4 => B"0000000000",
+ CLK_COR_SEQ_2_ENABLE => B"1111",
+ CLK_COR_SEQ_2_USE => "FALSE",
+ CLK_COR_SEQ_LEN => 1,
+ CPLL_CFG0 => X"67F8",
+ CPLL_CFG1 => X"A4AC",
+ CPLL_CFG2 => X"5007",
+ CPLL_CFG3 => B"00" & X"0",
+ CPLL_FBDIV => 2,
+ CPLL_FBDIV_45 => 4,
+ CPLL_INIT_CFG0 => X"02B2",
+ CPLL_INIT_CFG1 => X"00",
+ CPLL_LOCK_CFG => X"01E8",
+ CPLL_REFCLK_DIV => 1,
+ DDI_CTRL => B"00",
+ DDI_REALIGN_WAIT => 15,
+ DEC_MCOMMA_DETECT => "FALSE",
+ DEC_PCOMMA_DETECT => "FALSE",
+ DEC_VALID_COMMA_ONLY => "FALSE",
+ DFE_D_X_REL_POS => '0',
+ DFE_VCM_COMP_EN => '0',
+ DMONITOR_CFG0 => B"00" & X"00",
+ DMONITOR_CFG1 => X"00",
+ ES_CLK_PHASE_SEL => '0',
+ ES_CONTROL => B"000000",
+ ES_ERRDET_EN => "FALSE",
+ ES_EYE_SCAN_EN => "FALSE",
+ ES_HORZ_OFFSET => X"000",
+ ES_PMA_CFG => B"0000000000",
+ ES_PRESCALE => B"00000",
+ ES_QUALIFIER0 => X"0000",
+ ES_QUALIFIER1 => X"0000",
+ ES_QUALIFIER2 => X"0000",
+ ES_QUALIFIER3 => X"0000",
+ ES_QUALIFIER4 => X"0000",
+ ES_QUAL_MASK0 => X"0000",
+ ES_QUAL_MASK1 => X"0000",
+ ES_QUAL_MASK2 => X"0000",
+ ES_QUAL_MASK3 => X"0000",
+ ES_QUAL_MASK4 => X"0000",
+ ES_SDATA_MASK0 => X"0000",
+ ES_SDATA_MASK1 => X"0000",
+ ES_SDATA_MASK2 => X"0000",
+ ES_SDATA_MASK3 => X"0000",
+ ES_SDATA_MASK4 => X"0000",
+ EVODD_PHI_CFG => B"00000000000",
+ EYE_SCAN_SWAP_EN => '0',
+ FTS_DESKEW_SEQ_ENABLE => B"1111",
+ FTS_LANE_DESKEW_CFG => B"1111",
+ FTS_LANE_DESKEW_EN => "FALSE",
+ GEARBOX_MODE => B"00000",
+ GM_BIAS_SELECT => '0',
+ LOCAL_MASTER => '1',
+ OOBDIVCTL => B"00",
+ OOB_PWRUP => '0',
+ PCI3_AUTO_REALIGN => "OVR_1K_BLK",
+ PCI3_PIPE_RX_ELECIDLE => '0',
+ PCI3_RX_ASYNC_EBUF_BYPASS => B"00",
+ PCI3_RX_ELECIDLE_EI2_ENABLE => '0',
+ PCI3_RX_ELECIDLE_H2L_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_H2L_DISABLE => B"000",
+ PCI3_RX_ELECIDLE_HI_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_LP4_DISABLE => '0',
+ PCI3_RX_FIFO_DISABLE => '0',
+ PCIE_BUFG_DIV_CTRL => X"1000",
+ PCIE_RXPCS_CFG_GEN3 => X"02A4",
+ PCIE_RXPMA_CFG => X"000A",
+ PCIE_TXPCS_CFG_GEN3 => X"24A4",
+ PCIE_TXPMA_CFG => X"000A",
+ PCS_PCIE_EN => "FALSE",
+ PCS_RSVD0 => B"0000000000000000",
+ PCS_RSVD1 => B"000",
+ PD_TRANS_TIME_FROM_P2 => X"03C",
+ PD_TRANS_TIME_NONE_P2 => X"19",
+ PD_TRANS_TIME_TO_P2 => X"64",
+ PLL_SEL_MODE_GEN12 => B"00",
+ PLL_SEL_MODE_GEN3 => B"11",
+ PMA_RSV1 => X"F000",
+ PROCESS_PAR => B"010",
+ RATE_SW_USE_DRP => '1',
+ RESET_POWERSAVE_DISABLE => '0',
+ RXBUFRESET_TIME => B"00011",
+ RXBUF_ADDR_MODE => "FAST",
+ RXBUF_EIDLE_HI_CNT => B"1000",
+ RXBUF_EIDLE_LO_CNT => B"0000",
+ RXBUF_EN => "TRUE",
+ RXBUF_RESET_ON_CB_CHANGE => "TRUE",
+ RXBUF_RESET_ON_COMMAALIGN => "FALSE",
+ RXBUF_RESET_ON_EIDLE => "FALSE",
+ RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ RXBUF_THRESH_OVFLW => 61,
+ RXBUF_THRESH_OVRD => "TRUE",
+ RXBUF_THRESH_UNDFLW => 1,
+ RXCDRFREQRESET_TIME => B"00001",
+ RXCDRPHRESET_TIME => B"00001",
+ RXCDR_CFG0 => X"0000",
+ RXCDR_CFG0_GEN3 => X"0000",
+ RXCDR_CFG1 => X"0000",
+ RXCDR_CFG1_GEN3 => X"0000",
+ RXCDR_CFG2 => X"07E6",
+ RXCDR_CFG2_GEN3 => X"07E6",
+ RXCDR_CFG3 => X"0000",
+ RXCDR_CFG3_GEN3 => X"0000",
+ RXCDR_CFG4 => X"0000",
+ RXCDR_CFG4_GEN3 => X"0000",
+ RXCDR_CFG5 => X"0000",
+ RXCDR_CFG5_GEN3 => X"0000",
+ RXCDR_FR_RESET_ON_EIDLE => '0',
+ RXCDR_HOLD_DURING_EIDLE => '0',
+ RXCDR_LOCK_CFG0 => X"4480",
+ RXCDR_LOCK_CFG1 => X"5FFF",
+ RXCDR_LOCK_CFG2 => X"77C3",
+ RXCDR_PH_RESET_ON_EIDLE => '0',
+ RXCFOK_CFG0 => X"4000",
+ RXCFOK_CFG1 => X"0065",
+ RXCFOK_CFG2 => X"002E",
+ RXDFELPMRESET_TIME => B"0001111",
+ RXDFELPM_KL_CFG0 => X"0000",
+ RXDFELPM_KL_CFG1 => X"0002",
+ RXDFELPM_KL_CFG2 => X"0000",
+ RXDFE_CFG0 => X"0A00",
+ RXDFE_CFG1 => X"0000",
+ RXDFE_GC_CFG0 => X"0000",
+ RXDFE_GC_CFG1 => X"7870",
+ RXDFE_GC_CFG2 => X"0000",
+ RXDFE_H2_CFG0 => X"0000",
+ RXDFE_H2_CFG1 => X"0000",
+ RXDFE_H3_CFG0 => X"4000",
+ RXDFE_H3_CFG1 => X"0000",
+ RXDFE_H4_CFG0 => X"2000",
+ RXDFE_H4_CFG1 => X"0003",
+ RXDFE_H5_CFG0 => X"2000",
+ RXDFE_H5_CFG1 => X"0003",
+ RXDFE_H6_CFG0 => X"2000",
+ RXDFE_H6_CFG1 => X"0000",
+ RXDFE_H7_CFG0 => X"2000",
+ RXDFE_H7_CFG1 => X"0000",
+ RXDFE_H8_CFG0 => X"2000",
+ RXDFE_H8_CFG1 => X"0000",
+ RXDFE_H9_CFG0 => X"2000",
+ RXDFE_H9_CFG1 => X"0000",
+ RXDFE_HA_CFG0 => X"2000",
+ RXDFE_HA_CFG1 => X"0000",
+ RXDFE_HB_CFG0 => X"2000",
+ RXDFE_HB_CFG1 => X"0000",
+ RXDFE_HC_CFG0 => X"0000",
+ RXDFE_HC_CFG1 => X"0000",
+ RXDFE_HD_CFG0 => X"0000",
+ RXDFE_HD_CFG1 => X"0000",
+ RXDFE_HE_CFG0 => X"0000",
+ RXDFE_HE_CFG1 => X"0000",
+ RXDFE_HF_CFG0 => X"0000",
+ RXDFE_HF_CFG1 => X"0000",
+ RXDFE_OS_CFG0 => X"8000",
+ RXDFE_OS_CFG1 => X"0000",
+ RXDFE_UT_CFG0 => X"8000",
+ RXDFE_UT_CFG1 => X"0003",
+ RXDFE_VP_CFG0 => X"AA00",
+ RXDFE_VP_CFG1 => X"0033",
+ RXDLY_CFG => X"001F",
+ RXDLY_LCFG => X"0030",
+ RXELECIDLE_CFG => "Sigcfg_4",
+ RXGBOX_FIFO_INIT_RD_ADDR => 4,
+ RXGEARBOX_EN => "FALSE",
+ RXISCANRESET_TIME => B"00001",
+ RXLPM_CFG => X"0000",
+ RXLPM_GC_CFG => X"1000",
+ RXLPM_KH_CFG0 => X"0000",
+ RXLPM_KH_CFG1 => X"0002",
+ RXLPM_OS_CFG0 => X"8000",
+ RXLPM_OS_CFG1 => X"0002",
+ RXOOB_CFG => B"000000110",
+ RXOOB_CLK_CFG => "PMA",
+ RXOSCALRESET_TIME => B"00011",
+ RXOUT_DIV => 1,
+ RXPCSRESET_TIME => B"00011",
+ RXPHBEACON_CFG => X"0000",
+ RXPHDLY_CFG => X"2020",
+ RXPHSAMP_CFG => X"2100",
+ RXPHSLIP_CFG => X"6622",
+ RXPH_MONITOR_SEL => B"00000",
+ RXPI_CFG0 => B"00",
+ RXPI_CFG1 => B"00",
+ RXPI_CFG2 => B"00",
+ RXPI_CFG3 => B"00",
+ RXPI_CFG4 => '1',
+ RXPI_CFG5 => '1',
+ RXPI_CFG6 => B"011",
+ RXPI_LPM => '0',
+ RXPI_VREFSEL => '0',
+ RXPMACLK_SEL => "DATA",
+ RXPMARESET_TIME => B"00011",
+ RXPRBS_ERR_LOOPBACK => '0',
+ RXPRBS_LINKACQ_CNT => 15,
+ RXSLIDE_AUTO_WAIT => 7,
+ RXSLIDE_MODE => "OFF",
+ RXSYNC_MULTILANE => '1',
+ RXSYNC_OVRD => '0',
+ RXSYNC_SKIP_DA => '0',
+ RX_AFE_CM_EN => '0',
+ RX_BIAS_CFG0 => X"0AB4",
+ RX_BUFFER_CFG => B"000000",
+ RX_CAPFF_SARC_ENB => '0',
+ RX_CLK25_DIV => 13,
+ RX_CLKMUX_EN => '1',
+ RX_CLK_SLIP_OVRD => B"00000",
+ RX_CM_BUF_CFG => B"1010",
+ RX_CM_BUF_PD => '0',
+ RX_CM_SEL => B"11",
+ RX_CM_TRIM => B"1010",
+ RX_CTLE3_LPF => B"00000001",
+ RX_DATA_WIDTH => 16,
+ RX_DDI_SEL => B"000000",
+ RX_DEFER_RESET_BUF_EN => "TRUE",
+ RX_DFELPM_CFG0 => B"0110",
+ RX_DFELPM_CFG1 => '1',
+ RX_DFELPM_KLKH_AGC_STUP_EN => '1',
+ RX_DFE_AGC_CFG0 => B"10",
+ RX_DFE_AGC_CFG1 => B"100",
+ RX_DFE_KL_LPM_KH_CFG0 => B"01",
+ RX_DFE_KL_LPM_KH_CFG1 => B"100",
+ RX_DFE_KL_LPM_KL_CFG0 => B"01",
+ RX_DFE_KL_LPM_KL_CFG1 => B"100",
+ RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
+ RX_DISPERR_SEQ_MATCH => "TRUE",
+ RX_DIVRESET_TIME => B"00001",
+ RX_EN_HI_LR => '0',
+ RX_EYESCAN_VS_CODE => B"0000000",
+ RX_EYESCAN_VS_NEG_DIR => '0',
+ RX_EYESCAN_VS_RANGE => B"00",
+ RX_EYESCAN_VS_UT_SIGN => '0',
+ RX_FABINT_USRCLK_FLOP => '0',
+ RX_INT_DATAWIDTH => 0,
+ RX_PMA_POWER_SAVE => '0',
+ RX_PROGDIV_CFG => 0.000000,
+ RX_SAMPLE_PERIOD => B"111",
+ RX_SIG_VALID_DLY => 11,
+ RX_SUM_DFETAPREP_EN => '0',
+ RX_SUM_IREF_TUNE => B"0000",
+ RX_SUM_RES_CTRL => B"00",
+ RX_SUM_VCMTUNE => B"0000",
+ RX_SUM_VCM_OVWR => '0',
+ RX_SUM_VREF_TUNE => B"000",
+ RX_TUNE_AFE_OS => B"10",
+ RX_WIDEMODE_CDR => '0',
+ RX_XCLK_SEL => "RXDES",
+ SAS_MAX_COM => 64,
+ SAS_MIN_COM => 36,
+ SATA_BURST_SEQ_LEN => B"1110",
+ SATA_BURST_VAL => B"100",
+ SATA_CPLL_CFG => "VCO_3000MHZ",
+ SATA_EIDLE_VAL => B"100",
+ SATA_MAX_BURST => 8,
+ SATA_MAX_INIT => 21,
+ SATA_MAX_WAKE => 7,
+ SATA_MIN_BURST => 4,
+ SATA_MIN_INIT => 12,
+ SATA_MIN_WAKE => 4,
+ SHOW_REALIGN_COMMA => "TRUE",
+ SIM_MODE => "FAST",
+ SIM_RECEIVER_DETECT_PASS => "TRUE",
+ SIM_RESET_SPEEDUP => "TRUE",
+ SIM_TX_EIDLE_DRIVE_LEVEL => '0',
+ SIM_VERSION => 2,
+ TAPDLY_SET_TX => B"00",
+ TEMPERATUR_PAR => B"0010",
+ TERM_RCAL_CFG => B"100001000010000",
+ TERM_RCAL_OVRD => B"000",
+ TRANS_TIME_RATE => X"0E",
+ TST_RSV0 => X"00",
+ TST_RSV1 => X"00",
+ TXBUF_EN => "FALSE",
+ TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ TXDLY_CFG => X"0009",
+ TXDLY_LCFG => X"0050",
+ TXDRVBIAS_N => B"1010",
+ TXDRVBIAS_P => B"1010",
+ TXFIFO_ADDR_CFG => "LOW",
+ TXGBOX_FIFO_INIT_RD_ADDR => 4,
+ TXGEARBOX_EN => "FALSE",
+ TXOUT_DIV => 1,
+ TXPCSRESET_TIME => B"00011",
+ TXPHDLY_CFG0 => X"2020",
+ TXPHDLY_CFG1 => X"0075",
+ TXPH_CFG => X"0980",
+ TXPH_MONITOR_SEL => B"00000",
+ TXPI_CFG0 => B"00",
+ TXPI_CFG1 => B"00",
+ TXPI_CFG2 => B"00",
+ TXPI_CFG3 => '1',
+ TXPI_CFG4 => '1',
+ TXPI_CFG5 => B"000",
+ TXPI_GRAY_SEL => '0',
+ TXPI_INVSTROBE_SEL => '1',
+ TXPI_LPM => '0',
+ TXPI_PPMCLK_SEL => "TXUSRCLK2",
+ TXPI_PPM_CFG => B"00000000",
+ TXPI_SYNFREQ_PPM => B"001",
+ TXPI_VREFSEL => '0',
+ TXPMARESET_TIME => B"00011",
+ TXSYNC_MULTILANE => '1',
+ TXSYNC_OVRD => '0',
+ TXSYNC_SKIP_DA => '0',
+ TX_CLK25_DIV => 10,
+ TX_CLKMUX_EN => '1',
+ TX_DATA_WIDTH => 32,
+ TX_DCD_CFG => B"000010",
+ TX_DCD_EN => '0',
+ TX_DEEMPH0 => B"000000",
+ TX_DEEMPH1 => B"000000",
+ TX_DIVRESET_TIME => B"00001",
+ TX_DRIVE_MODE => "DIRECT",
+ TX_EIDLE_ASSERT_DELAY => B"100",
+ TX_EIDLE_DEASSERT_DELAY => B"011",
+ TX_EML_PHI_TUNE => '0',
+ TX_FABINT_USRCLK_FLOP => '0',
+ TX_IDLE_DATA_ZERO => '0',
+ TX_INT_DATAWIDTH => 1,
+ TX_LOOPBACK_DRIVE_HIZ => "FALSE",
+ TX_MAINCURSOR_SEL => '0',
+ TX_MARGIN_FULL_0 => B"1001111",
+ TX_MARGIN_FULL_1 => B"1001110",
+ TX_MARGIN_FULL_2 => B"1001100",
+ TX_MARGIN_FULL_3 => B"1001010",
+ TX_MARGIN_FULL_4 => B"1001000",
+ TX_MARGIN_LOW_0 => B"1000110",
+ TX_MARGIN_LOW_1 => B"1000101",
+ TX_MARGIN_LOW_2 => B"1000011",
+ TX_MARGIN_LOW_3 => B"1000010",
+ TX_MARGIN_LOW_4 => B"1000000",
+ TX_MODE_SEL => B"000",
+ TX_PMADATA_OPT => '0',
+ TX_PMA_POWER_SAVE => '0',
+ TX_PROGCLK_SEL => "PREPI",
+ TX_PROGDIV_CFG => 16.000000,
+ TX_QPI_STATUS_EN => '0',
+ TX_RXDETECT_CFG => B"00" & X"032",
+ TX_RXDETECT_REF => B"100",
+ TX_SAMPLE_PERIOD => B"111",
+ TX_SARC_LPBK_ENB => '0',
+ TX_XCLK_SEL => "TXUSR",
+ USE_PCS_CLK_PHASE_SEL => '0',
+ WB_MODE => B"00"
+ )
+ port map (
+ BUFGTCE(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_289\,
+ BUFGTCE(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_290\,
+ BUFGTCE(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_291\,
+ BUFGTCEMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_292\,
+ BUFGTCEMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_293\,
+ BUFGTCEMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_294\,
+ BUFGTDIV(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_357\,
+ BUFGTDIV(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_358\,
+ BUFGTDIV(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_359\,
+ BUFGTDIV(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_360\,
+ BUFGTDIV(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_361\,
+ BUFGTDIV(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_362\,
+ BUFGTDIV(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_363\,
+ BUFGTDIV(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_364\,
+ BUFGTDIV(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_365\,
+ BUFGTRESET(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_295\,
+ BUFGTRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_296\,
+ BUFGTRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_297\,
+ BUFGTRSTMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_298\,
+ BUFGTRSTMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_299\,
+ BUFGTRSTMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_300\,
+ CFGRESET => '0',
+ CLKRSVD0 => '0',
+ CLKRSVD1 => '0',
+ CPLLFBCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_0\,
+ CPLLLOCK => cplllock_out(1),
+ CPLLLOCKDETCLK => '0',
+ CPLLLOCKEN => '1',
+ CPLLPD => GTHE3_CHANNEL_CPLLPD(0),
+ CPLLREFCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_2\,
+ CPLLREFCLKSEL(2 downto 0) => B"001",
+ CPLLRESET => '0',
+ DMONFIFORESET => '0',
+ DMONITORCLK => '0',
+ DMONITOROUT(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_258\,
+ DMONITOROUT(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_259\,
+ DMONITOROUT(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_260\,
+ DMONITOROUT(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_261\,
+ DMONITOROUT(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_262\,
+ DMONITOROUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_263\,
+ DMONITOROUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_264\,
+ DMONITOROUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_265\,
+ DMONITOROUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_266\,
+ DMONITOROUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_267\,
+ DMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_268\,
+ DMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_269\,
+ DMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_270\,
+ DMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_271\,
+ DMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_272\,
+ DMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_273\,
+ DMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_274\,
+ DRPADDR(8 downto 0) => B"000000000",
+ DRPCLK => drpclk_in(1),
+ DRPDI(15 downto 0) => B"0000000000000000",
+ DRPDO(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_210\,
+ DRPDO(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_211\,
+ DRPDO(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_212\,
+ DRPDO(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_213\,
+ DRPDO(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_214\,
+ DRPDO(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_215\,
+ DRPDO(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_216\,
+ DRPDO(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_217\,
+ DRPDO(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_218\,
+ DRPDO(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_219\,
+ DRPDO(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_220\,
+ DRPDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_221\,
+ DRPDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_222\,
+ DRPDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_223\,
+ DRPDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_224\,
+ DRPDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_225\,
+ DRPEN => '0',
+ DRPRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_3\,
+ DRPWE => '0',
+ EVODDPHICALDONE => '0',
+ EVODDPHICALSTART => '0',
+ EVODDPHIDRDEN => '0',
+ EVODDPHIDWREN => '0',
+ EVODDPHIXRDEN => '0',
+ EVODDPHIXWREN => '0',
+ EYESCANDATAERROR => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_4\,
+ EYESCANMODE => '0',
+ EYESCANRESET => '0',
+ EYESCANTRIGGER => '0',
+ GTGREFCLK => '0',
+ GTHRXN => gthrxn_in(1),
+ GTHRXP => gthrxp_in(1),
+ GTHTXN => gthtxn_out(1),
+ GTHTXP => gthtxp_out(1),
+ GTNORTHREFCLK0 => '0',
+ GTNORTHREFCLK1 => '0',
+ GTPOWERGOOD => gtpowergood_out(1),
+ GTREFCLK0 => gtrefclk0_in(1),
+ GTREFCLK1 => '0',
+ GTREFCLKMONITOR => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_8\,
+ GTRESETSEL => '0',
+ GTRSVD(15 downto 0) => B"0000000000000000",
+ GTRXRESET => GTHE3_CHANNEL_GTRXRESET(0),
+ GTSOUTHREFCLK0 => '0',
+ GTSOUTHREFCLK1 => '0',
+ GTTXRESET => GTHE3_CHANNEL_GTTXRESET(0),
+ LOOPBACK(2 downto 0) => loopback_in(5 downto 3),
+ LPBKRXTXSEREN => '0',
+ LPBKTXRXSEREN => '0',
+ PCIEEQRXEQADAPTDONE => '0',
+ PCIERATEGEN3 => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_9\,
+ PCIERATEIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_10\,
+ PCIERATEQPLLPD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_275\,
+ PCIERATEQPLLPD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_276\,
+ PCIERATEQPLLRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_277\,
+ PCIERATEQPLLRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_278\,
+ PCIERSTIDLE => '0',
+ PCIERSTTXSYNCSTART => '0',
+ PCIESYNCTXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_11\,
+ PCIEUSERGEN3RDY => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_12\,
+ PCIEUSERPHYSTATUSRST => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_13\,
+ PCIEUSERRATEDONE => '0',
+ PCIEUSERRATESTART => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_14\,
+ PCSRSVDIN(15 downto 0) => B"0000000000000000",
+ PCSRSVDIN2(4 downto 0) => B"00000",
+ PCSRSVDOUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_70\,
+ PCSRSVDOUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_71\,
+ PCSRSVDOUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_72\,
+ PCSRSVDOUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_73\,
+ PCSRSVDOUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_74\,
+ PCSRSVDOUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_75\,
+ PCSRSVDOUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_76\,
+ PCSRSVDOUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_77\,
+ PCSRSVDOUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_78\,
+ PCSRSVDOUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_79\,
+ PCSRSVDOUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_80\,
+ PCSRSVDOUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_81\,
+ PHYSTATUS => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_15\,
+ PINRSRVDAS(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_325\,
+ PINRSRVDAS(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_326\,
+ PINRSRVDAS(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_327\,
+ PINRSRVDAS(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_328\,
+ PINRSRVDAS(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_329\,
+ PINRSRVDAS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_330\,
+ PINRSRVDAS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_331\,
+ PINRSRVDAS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_332\,
+ PMARSVDIN(4 downto 0) => B"00000",
+ QPLL0CLK => qpll0outclk_out(0),
+ QPLL0REFCLK => qpll0outrefclk_out(0),
+ QPLL1CLK => qpll1outclk_out(0),
+ QPLL1REFCLK => qpll1outrefclk_out(0),
+ RESETEXCEPTION => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_16\,
+ RESETOVRD => '0',
+ RSTCLKENTX => '0',
+ RX8B10BEN => '0',
+ RXBUFRESET => '0',
+ RXBUFSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_301\,
+ RXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_302\,
+ RXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_303\,
+ RXBYTEISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_17\,
+ RXBYTEREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_18\,
+ RXCDRFREQRESET => '0',
+ RXCDRHOLD => rxcdrhold_in(1),
+ RXCDRLOCK => rxcdrlock_out(1),
+ RXCDROVRDEN => '0',
+ RXCDRPHDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_20\,
+ RXCDRRESET => '0',
+ RXCDRRESETRSV => '0',
+ RXCHANBONDSEQ => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_21\,
+ RXCHANISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_22\,
+ RXCHANREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_23\,
+ RXCHBONDEN => '0',
+ RXCHBONDI(4 downto 0) => B"00000",
+ RXCHBONDLEVEL(2 downto 0) => B"000",
+ RXCHBONDMASTER => '0',
+ RXCHBONDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_307\,
+ RXCHBONDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_308\,
+ RXCHBONDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_309\,
+ RXCHBONDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_310\,
+ RXCHBONDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_311\,
+ RXCHBONDSLAVE => '0',
+ RXCLKCORCNT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_279\,
+ RXCLKCORCNT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_280\,
+ RXCOMINITDET => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_24\,
+ RXCOMMADET => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_25\,
+ RXCOMMADETEN => '0',
+ RXCOMSASDET => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_26\,
+ RXCOMWAKEDET => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_27\,
+ RXCTRL0(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_226\,
+ RXCTRL0(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_227\,
+ RXCTRL0(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_228\,
+ RXCTRL0(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_229\,
+ RXCTRL0(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_230\,
+ RXCTRL0(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_231\,
+ RXCTRL0(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_232\,
+ RXCTRL0(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_233\,
+ RXCTRL0(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_234\,
+ RXCTRL0(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_235\,
+ RXCTRL0(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_236\,
+ RXCTRL0(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_237\,
+ RXCTRL0(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_238\,
+ RXCTRL0(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_239\,
+ RXCTRL0(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_240\,
+ RXCTRL0(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_241\,
+ RXCTRL1(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_242\,
+ RXCTRL1(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_243\,
+ RXCTRL1(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_244\,
+ RXCTRL1(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_245\,
+ RXCTRL1(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_246\,
+ RXCTRL1(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_247\,
+ RXCTRL1(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_248\,
+ RXCTRL1(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_249\,
+ RXCTRL1(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_250\,
+ RXCTRL1(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_251\,
+ RXCTRL1(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_252\,
+ RXCTRL1(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_253\,
+ RXCTRL1(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_254\,
+ RXCTRL1(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_255\,
+ RXCTRL1(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_256\,
+ RXCTRL1(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_257\,
+ RXCTRL2(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_333\,
+ RXCTRL2(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_334\,
+ RXCTRL2(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_335\,
+ RXCTRL2(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_336\,
+ RXCTRL2(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_337\,
+ RXCTRL2(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_338\,
+ RXCTRL2(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_339\,
+ RXCTRL2(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_340\,
+ RXCTRL3(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_341\,
+ RXCTRL3(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_342\,
+ RXCTRL3(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_343\,
+ RXCTRL3(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_344\,
+ RXCTRL3(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_345\,
+ RXCTRL3(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_346\,
+ RXCTRL3(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_347\,
+ RXCTRL3(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_348\,
+ RXDATA(127) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_82\,
+ RXDATA(126) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_83\,
+ RXDATA(125) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_84\,
+ RXDATA(124) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_85\,
+ RXDATA(123) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_86\,
+ RXDATA(122) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_87\,
+ RXDATA(121) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_88\,
+ RXDATA(120) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_89\,
+ RXDATA(119) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_90\,
+ RXDATA(118) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_91\,
+ RXDATA(117) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_92\,
+ RXDATA(116) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_93\,
+ RXDATA(115) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_94\,
+ RXDATA(114) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_95\,
+ RXDATA(113) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_96\,
+ RXDATA(112) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_97\,
+ RXDATA(111) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_98\,
+ RXDATA(110) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_99\,
+ RXDATA(109) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_100\,
+ RXDATA(108) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_101\,
+ RXDATA(107) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_102\,
+ RXDATA(106) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_103\,
+ RXDATA(105) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_104\,
+ RXDATA(104) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_105\,
+ RXDATA(103) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_106\,
+ RXDATA(102) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_107\,
+ RXDATA(101) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_108\,
+ RXDATA(100) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_109\,
+ RXDATA(99) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_110\,
+ RXDATA(98) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_111\,
+ RXDATA(97) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_112\,
+ RXDATA(96) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_113\,
+ RXDATA(95) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_114\,
+ RXDATA(94) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_115\,
+ RXDATA(93) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_116\,
+ RXDATA(92) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_117\,
+ RXDATA(91) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_118\,
+ RXDATA(90) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_119\,
+ RXDATA(89) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_120\,
+ RXDATA(88) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_121\,
+ RXDATA(87) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_122\,
+ RXDATA(86) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_123\,
+ RXDATA(85) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_124\,
+ RXDATA(84) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_125\,
+ RXDATA(83) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_126\,
+ RXDATA(82) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_127\,
+ RXDATA(81) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_128\,
+ RXDATA(80) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_129\,
+ RXDATA(79) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_130\,
+ RXDATA(78) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_131\,
+ RXDATA(77) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_132\,
+ RXDATA(76) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_133\,
+ RXDATA(75) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_134\,
+ RXDATA(74) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_135\,
+ RXDATA(73) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_136\,
+ RXDATA(72) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_137\,
+ RXDATA(71) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_138\,
+ RXDATA(70) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_139\,
+ RXDATA(69) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_140\,
+ RXDATA(68) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_141\,
+ RXDATA(67) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_142\,
+ RXDATA(66) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_143\,
+ RXDATA(65) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_144\,
+ RXDATA(64) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_145\,
+ RXDATA(63) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_146\,
+ RXDATA(62) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_147\,
+ RXDATA(61) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_148\,
+ RXDATA(60) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_149\,
+ RXDATA(59) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_150\,
+ RXDATA(58) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_151\,
+ RXDATA(57) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_152\,
+ RXDATA(56) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_153\,
+ RXDATA(55) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_154\,
+ RXDATA(54) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_155\,
+ RXDATA(53) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_156\,
+ RXDATA(52) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_157\,
+ RXDATA(51) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_158\,
+ RXDATA(50) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_159\,
+ RXDATA(49) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_160\,
+ RXDATA(48) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_161\,
+ RXDATA(47) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_162\,
+ RXDATA(46) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_163\,
+ RXDATA(45) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_164\,
+ RXDATA(44) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_165\,
+ RXDATA(43) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_166\,
+ RXDATA(42) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_167\,
+ RXDATA(41) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_168\,
+ RXDATA(40) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_169\,
+ RXDATA(39) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_170\,
+ RXDATA(38) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_171\,
+ RXDATA(37) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_172\,
+ RXDATA(36) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_173\,
+ RXDATA(35) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_174\,
+ RXDATA(34) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_175\,
+ RXDATA(33) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_176\,
+ RXDATA(32) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_177\,
+ RXDATA(31) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_178\,
+ RXDATA(30) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_179\,
+ RXDATA(29) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_180\,
+ RXDATA(28) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_181\,
+ RXDATA(27) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_182\,
+ RXDATA(26) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_183\,
+ RXDATA(25) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_184\,
+ RXDATA(24) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_185\,
+ RXDATA(23) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_186\,
+ RXDATA(22) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_187\,
+ RXDATA(21) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_188\,
+ RXDATA(20) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_189\,
+ RXDATA(19) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_190\,
+ RXDATA(18) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_191\,
+ RXDATA(17) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_192\,
+ RXDATA(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_193\,
+ RXDATA(15 downto 0) => gtwiz_userdata_rx_out(31 downto 16),
+ RXDATAEXTENDRSVD(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_349\,
+ RXDATAEXTENDRSVD(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_350\,
+ RXDATAEXTENDRSVD(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_351\,
+ RXDATAEXTENDRSVD(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_352\,
+ RXDATAEXTENDRSVD(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_353\,
+ RXDATAEXTENDRSVD(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_354\,
+ RXDATAEXTENDRSVD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_355\,
+ RXDATAEXTENDRSVD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_356\,
+ RXDATAVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_281\,
+ RXDATAVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_282\,
+ RXDFEAGCCTRL(1 downto 0) => B"01",
+ RXDFEAGCHOLD => '0',
+ RXDFEAGCOVRDEN => '0',
+ RXDFELFHOLD => '0',
+ RXDFELFOVRDEN => '0',
+ RXDFELPMRESET => '0',
+ RXDFETAP10HOLD => '0',
+ RXDFETAP10OVRDEN => '0',
+ RXDFETAP11HOLD => '0',
+ RXDFETAP11OVRDEN => '0',
+ RXDFETAP12HOLD => '0',
+ RXDFETAP12OVRDEN => '0',
+ RXDFETAP13HOLD => '0',
+ RXDFETAP13OVRDEN => '0',
+ RXDFETAP14HOLD => '0',
+ RXDFETAP14OVRDEN => '0',
+ RXDFETAP15HOLD => '0',
+ RXDFETAP15OVRDEN => '0',
+ RXDFETAP2HOLD => '0',
+ RXDFETAP2OVRDEN => '0',
+ RXDFETAP3HOLD => '0',
+ RXDFETAP3OVRDEN => '0',
+ RXDFETAP4HOLD => '0',
+ RXDFETAP4OVRDEN => '0',
+ RXDFETAP5HOLD => '0',
+ RXDFETAP5OVRDEN => '0',
+ RXDFETAP6HOLD => '0',
+ RXDFETAP6OVRDEN => '0',
+ RXDFETAP7HOLD => '0',
+ RXDFETAP7OVRDEN => '0',
+ RXDFETAP8HOLD => '0',
+ RXDFETAP8OVRDEN => '0',
+ RXDFETAP9HOLD => '0',
+ RXDFETAP9OVRDEN => '0',
+ RXDFEUTHOLD => '0',
+ RXDFEUTOVRDEN => '0',
+ RXDFEVPHOLD => '0',
+ RXDFEVPOVRDEN => '0',
+ RXDFEVSEN => '0',
+ RXDFEXYDEN => '1',
+ RXDLYBYPASS => '1',
+ RXDLYEN => '0',
+ RXDLYOVRDEN => '0',
+ RXDLYSRESET => '0',
+ RXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_28\,
+ RXELECIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_29\,
+ RXELECIDLEMODE(1 downto 0) => B"11",
+ RXGEARBOXSLIP => '0',
+ RXHEADER(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_312\,
+ RXHEADER(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_313\,
+ RXHEADER(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_314\,
+ RXHEADER(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_315\,
+ RXHEADER(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_316\,
+ RXHEADER(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_317\,
+ RXHEADERVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_283\,
+ RXHEADERVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_284\,
+ RXLATCLK => '0',
+ RXLPMEN => '0',
+ RXLPMGCHOLD => '0',
+ RXLPMGCOVRDEN => '0',
+ RXLPMHFHOLD => '0',
+ RXLPMHFOVRDEN => '0',
+ RXLPMLFHOLD => '0',
+ RXLPMLFKLOVRDEN => '0',
+ RXLPMOSHOLD => '0',
+ RXLPMOSOVRDEN => '0',
+ RXMCOMMAALIGNEN => '0',
+ RXMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_318\,
+ RXMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_319\,
+ RXMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_320\,
+ RXMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_321\,
+ RXMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_322\,
+ RXMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_323\,
+ RXMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_324\,
+ RXMONITORSEL(1 downto 0) => B"00",
+ RXOOBRESET => '0',
+ RXOSCALRESET => '0',
+ RXOSHOLD => '0',
+ RXOSINTCFG(3 downto 0) => B"1101",
+ RXOSINTDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_30\,
+ RXOSINTEN => '1',
+ RXOSINTHOLD => '0',
+ RXOSINTOVRDEN => '0',
+ RXOSINTSTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_31\,
+ RXOSINTSTROBE => '0',
+ RXOSINTSTROBEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_32\,
+ RXOSINTSTROBESTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_33\,
+ RXOSINTTESTOVRDEN => '0',
+ RXOSOVRDEN => '0',
+ RXOUTCLK => rxoutclk_out(1),
+ RXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_35\,
+ RXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_36\,
+ RXOUTCLKSEL(2 downto 0) => B"010",
+ RXPCOMMAALIGNEN => '0',
+ RXPCSRESET => '0',
+ RXPD(1 downto 0) => B"00",
+ RXPHALIGN => '0',
+ RXPHALIGNDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_37\,
+ RXPHALIGNEN => '0',
+ RXPHALIGNERR => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_38\,
+ RXPHDLYPD => '1',
+ RXPHDLYRESET => '0',
+ RXPHOVRDEN => '0',
+ RXPLLCLKSEL(1 downto 0) => B"00",
+ RXPMARESET => '0',
+ RXPMARESETDONE => rxpmaresetdone_out(1),
+ RXPOLARITY => rxpolarity_in(1),
+ RXPRBSCNTRESET => '0',
+ RXPRBSERR => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_40\,
+ RXPRBSLOCKED => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_41\,
+ RXPRBSSEL(3 downto 0) => B"0000",
+ RXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_42\,
+ RXPROGDIVRESET => GTHE3_CHANNEL_RXPROGDIVRESET(0),
+ RXQPIEN => '0',
+ RXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_43\,
+ RXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_44\,
+ RXRATE(2 downto 0) => B"000",
+ RXRATEDONE => rxratedone_out(1),
+ RXRATEMODE => '0',
+ RXRECCLKOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_46\,
+ RXRESETDONE => rxresetdone_out(1),
+ RXSLIDE => rxslide_in(1),
+ RXSLIDERDY => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_48\,
+ RXSLIPDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_49\,
+ RXSLIPOUTCLK => '0',
+ RXSLIPOUTCLKRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_50\,
+ RXSLIPPMA => '0',
+ RXSLIPPMARDY => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_51\,
+ RXSTARTOFSEQ(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_285\,
+ RXSTARTOFSEQ(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_286\,
+ RXSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_304\,
+ RXSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_305\,
+ RXSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_306\,
+ RXSYNCALLIN => '0',
+ RXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_52\,
+ RXSYNCIN => '0',
+ RXSYNCMODE => '0',
+ RXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_53\,
+ RXSYSCLKSEL(1 downto 0) => B"00",
+ RXUSERRDY => GTHE3_CHANNEL_RXUSERRDY(0),
+ RXUSRCLK => rxusrclk_in(1),
+ RXUSRCLK2 => rxusrclk2_in(1),
+ RXVALID => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_54\,
+ SIGVALIDCLK => '0',
+ TSTIN(19 downto 0) => B"00000000000000000000",
+ TX8B10BBYPASS(7 downto 0) => B"00000000",
+ TX8B10BEN => '0',
+ TXBUFDIFFCTRL(2 downto 0) => B"000",
+ TXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_287\,
+ TXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_288\,
+ TXCOMFINISH => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_55\,
+ TXCOMINIT => '0',
+ TXCOMSAS => '0',
+ TXCOMWAKE => '0',
+ TXCTRL0(15 downto 0) => B"0000000000000000",
+ TXCTRL1(15 downto 0) => B"0000000000000000",
+ TXCTRL2(7 downto 0) => B"00000000",
+ TXDATA(127 downto 32) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ TXDATA(31 downto 0) => gtwiz_userdata_tx_in(63 downto 32),
+ TXDATAEXTENDRSVD(7 downto 0) => B"00000000",
+ TXDEEMPH => '0',
+ TXDETECTRX => '0',
+ TXDIFFCTRL(3 downto 0) => B"1100",
+ TXDIFFPD => '0',
+ TXDLYBYPASS => '0',
+ TXDLYEN => '0',
+ TXDLYHOLD => '0',
+ TXDLYOVRDEN => '0',
+ TXDLYSRESET => GTHE3_CHANNEL_TXDLYSRESET(0),
+ TXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_56\,
+ TXDLYUPDOWN => '0',
+ TXELECIDLE => '0',
+ TXHEADER(5 downto 0) => B"000000",
+ TXINHIBIT => '0',
+ TXLATCLK => '0',
+ TXMAINCURSOR(6 downto 0) => B"1000000",
+ TXMARGIN(2 downto 0) => B"000",
+ TXOUTCLK => txoutclk_out(1),
+ TXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_58\,
+ TXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_59\,
+ TXOUTCLKSEL(2 downto 0) => B"101",
+ TXPCSRESET => '0',
+ TXPD(1 downto 0) => B"00",
+ TXPDELECIDLEMODE => '0',
+ TXPHALIGN => '0',
+ TXPHALIGNDONE => GTHE3_CHANNEL_TXPHALIGNDONE(1),
+ TXPHALIGNEN => '0',
+ TXPHDLYPD => '0',
+ TXPHDLYRESET => '0',
+ TXPHDLYTSTCLK => '0',
+ TXPHINIT => '0',
+ TXPHINITDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_61\,
+ TXPHOVRDEN => '0',
+ TXPIPPMEN => '0',
+ TXPIPPMOVRDEN => '0',
+ TXPIPPMPD => '0',
+ TXPIPPMSEL => '0',
+ TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
+ TXPISOPD => '0',
+ TXPLLCLKSEL(1 downto 0) => B"10",
+ TXPMARESET => '0',
+ TXPMARESETDONE => txpmaresetdone_out(1),
+ TXPOLARITY => txpolarity_in(1),
+ TXPOSTCURSOR(4 downto 0) => B"00000",
+ TXPOSTCURSORINV => '0',
+ TXPRBSFORCEERR => '0',
+ TXPRBSSEL(3 downto 0) => B"0000",
+ TXPRECURSOR(4 downto 0) => B"00000",
+ TXPRECURSORINV => '0',
+ TXPRGDIVRESETDONE => txprgdivresetdone_out(1),
+ TXPROGDIVRESET => GTHE3_CHANNEL_TXPROGDIVRESET(0),
+ TXQPIBIASEN => '0',
+ TXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_64\,
+ TXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_65\,
+ TXQPISTRONGPDOWN => '0',
+ TXQPIWEAKPUP => '0',
+ TXRATE(2 downto 0) => B"000",
+ TXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_66\,
+ TXRATEMODE => '0',
+ TXRESETDONE => txresetdone_out(1),
+ TXSEQUENCE(6 downto 0) => B"0000000",
+ TXSWING => '0',
+ TXSYNCALLIN => GTHE3_CHANNEL_TXSYNCALLIN(0),
+ TXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_68\,
+ TXSYNCIN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYNCMODE => '0',
+ TXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYSCLKSEL(1 downto 0) => B"11",
+ TXUSERRDY => GTHE3_CHANNEL_TXUSERRDY(0),
+ TXUSRCLK => txusrclk_in(1),
+ TXUSRCLK2 => txusrclk2_in(1)
+ );
+\gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST\: unisim.vcomponents.GTHE3_CHANNEL
+ generic map(
+ ACJTAG_DEBUG_MODE => '0',
+ ACJTAG_MODE => '0',
+ ACJTAG_RESET => '0',
+ ADAPT_CFG0 => X"F800",
+ ADAPT_CFG1 => X"0000",
+ ALIGN_COMMA_DOUBLE => "FALSE",
+ ALIGN_COMMA_ENABLE => B"0000000000",
+ ALIGN_COMMA_WORD => 1,
+ ALIGN_MCOMMA_DET => "FALSE",
+ ALIGN_MCOMMA_VALUE => B"1010000011",
+ ALIGN_PCOMMA_DET => "FALSE",
+ ALIGN_PCOMMA_VALUE => B"0101111100",
+ A_RXOSCALRESET => '0',
+ A_RXPROGDIVRESET => '0',
+ A_TXPROGDIVRESET => '0',
+ CBCC_DATA_SOURCE_SEL => "ENCODED",
+ CDR_SWAP_MODE_EN => '0',
+ CHAN_BOND_KEEP_ALIGN => "FALSE",
+ CHAN_BOND_MAX_SKEW => 1,
+ CHAN_BOND_SEQ_1_1 => B"0000000000",
+ CHAN_BOND_SEQ_1_2 => B"0000000000",
+ CHAN_BOND_SEQ_1_3 => B"0000000000",
+ CHAN_BOND_SEQ_1_4 => B"0000000000",
+ CHAN_BOND_SEQ_1_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_1 => B"0000000000",
+ CHAN_BOND_SEQ_2_2 => B"0000000000",
+ CHAN_BOND_SEQ_2_3 => B"0000000000",
+ CHAN_BOND_SEQ_2_4 => B"0000000000",
+ CHAN_BOND_SEQ_2_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_USE => "FALSE",
+ CHAN_BOND_SEQ_LEN => 1,
+ CLK_CORRECT_USE => "FALSE",
+ CLK_COR_KEEP_IDLE => "FALSE",
+ CLK_COR_MAX_LAT => 6,
+ CLK_COR_MIN_LAT => 4,
+ CLK_COR_PRECEDENCE => "TRUE",
+ CLK_COR_REPEAT_WAIT => 0,
+ CLK_COR_SEQ_1_1 => B"0000000000",
+ CLK_COR_SEQ_1_2 => B"0000000000",
+ CLK_COR_SEQ_1_3 => B"0000000000",
+ CLK_COR_SEQ_1_4 => B"0000000000",
+ CLK_COR_SEQ_1_ENABLE => B"1111",
+ CLK_COR_SEQ_2_1 => B"0000000000",
+ CLK_COR_SEQ_2_2 => B"0000000000",
+ CLK_COR_SEQ_2_3 => B"0000000000",
+ CLK_COR_SEQ_2_4 => B"0000000000",
+ CLK_COR_SEQ_2_ENABLE => B"1111",
+ CLK_COR_SEQ_2_USE => "FALSE",
+ CLK_COR_SEQ_LEN => 1,
+ CPLL_CFG0 => X"67F8",
+ CPLL_CFG1 => X"A4AC",
+ CPLL_CFG2 => X"5007",
+ CPLL_CFG3 => B"00" & X"0",
+ CPLL_FBDIV => 2,
+ CPLL_FBDIV_45 => 4,
+ CPLL_INIT_CFG0 => X"02B2",
+ CPLL_INIT_CFG1 => X"00",
+ CPLL_LOCK_CFG => X"01E8",
+ CPLL_REFCLK_DIV => 1,
+ DDI_CTRL => B"00",
+ DDI_REALIGN_WAIT => 15,
+ DEC_MCOMMA_DETECT => "FALSE",
+ DEC_PCOMMA_DETECT => "FALSE",
+ DEC_VALID_COMMA_ONLY => "FALSE",
+ DFE_D_X_REL_POS => '0',
+ DFE_VCM_COMP_EN => '0',
+ DMONITOR_CFG0 => B"00" & X"00",
+ DMONITOR_CFG1 => X"00",
+ ES_CLK_PHASE_SEL => '0',
+ ES_CONTROL => B"000000",
+ ES_ERRDET_EN => "FALSE",
+ ES_EYE_SCAN_EN => "FALSE",
+ ES_HORZ_OFFSET => X"000",
+ ES_PMA_CFG => B"0000000000",
+ ES_PRESCALE => B"00000",
+ ES_QUALIFIER0 => X"0000",
+ ES_QUALIFIER1 => X"0000",
+ ES_QUALIFIER2 => X"0000",
+ ES_QUALIFIER3 => X"0000",
+ ES_QUALIFIER4 => X"0000",
+ ES_QUAL_MASK0 => X"0000",
+ ES_QUAL_MASK1 => X"0000",
+ ES_QUAL_MASK2 => X"0000",
+ ES_QUAL_MASK3 => X"0000",
+ ES_QUAL_MASK4 => X"0000",
+ ES_SDATA_MASK0 => X"0000",
+ ES_SDATA_MASK1 => X"0000",
+ ES_SDATA_MASK2 => X"0000",
+ ES_SDATA_MASK3 => X"0000",
+ ES_SDATA_MASK4 => X"0000",
+ EVODD_PHI_CFG => B"00000000000",
+ EYE_SCAN_SWAP_EN => '0',
+ FTS_DESKEW_SEQ_ENABLE => B"1111",
+ FTS_LANE_DESKEW_CFG => B"1111",
+ FTS_LANE_DESKEW_EN => "FALSE",
+ GEARBOX_MODE => B"00000",
+ GM_BIAS_SELECT => '0',
+ LOCAL_MASTER => '1',
+ OOBDIVCTL => B"00",
+ OOB_PWRUP => '0',
+ PCI3_AUTO_REALIGN => "OVR_1K_BLK",
+ PCI3_PIPE_RX_ELECIDLE => '0',
+ PCI3_RX_ASYNC_EBUF_BYPASS => B"00",
+ PCI3_RX_ELECIDLE_EI2_ENABLE => '0',
+ PCI3_RX_ELECIDLE_H2L_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_H2L_DISABLE => B"000",
+ PCI3_RX_ELECIDLE_HI_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_LP4_DISABLE => '0',
+ PCI3_RX_FIFO_DISABLE => '0',
+ PCIE_BUFG_DIV_CTRL => X"1000",
+ PCIE_RXPCS_CFG_GEN3 => X"02A4",
+ PCIE_RXPMA_CFG => X"000A",
+ PCIE_TXPCS_CFG_GEN3 => X"24A4",
+ PCIE_TXPMA_CFG => X"000A",
+ PCS_PCIE_EN => "FALSE",
+ PCS_RSVD0 => B"0000000000000000",
+ PCS_RSVD1 => B"000",
+ PD_TRANS_TIME_FROM_P2 => X"03C",
+ PD_TRANS_TIME_NONE_P2 => X"19",
+ PD_TRANS_TIME_TO_P2 => X"64",
+ PLL_SEL_MODE_GEN12 => B"00",
+ PLL_SEL_MODE_GEN3 => B"11",
+ PMA_RSV1 => X"F000",
+ PROCESS_PAR => B"010",
+ RATE_SW_USE_DRP => '1',
+ RESET_POWERSAVE_DISABLE => '0',
+ RXBUFRESET_TIME => B"00011",
+ RXBUF_ADDR_MODE => "FAST",
+ RXBUF_EIDLE_HI_CNT => B"1000",
+ RXBUF_EIDLE_LO_CNT => B"0000",
+ RXBUF_EN => "TRUE",
+ RXBUF_RESET_ON_CB_CHANGE => "TRUE",
+ RXBUF_RESET_ON_COMMAALIGN => "FALSE",
+ RXBUF_RESET_ON_EIDLE => "FALSE",
+ RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ RXBUF_THRESH_OVFLW => 61,
+ RXBUF_THRESH_OVRD => "TRUE",
+ RXBUF_THRESH_UNDFLW => 1,
+ RXCDRFREQRESET_TIME => B"00001",
+ RXCDRPHRESET_TIME => B"00001",
+ RXCDR_CFG0 => X"0000",
+ RXCDR_CFG0_GEN3 => X"0000",
+ RXCDR_CFG1 => X"0000",
+ RXCDR_CFG1_GEN3 => X"0000",
+ RXCDR_CFG2 => X"07E6",
+ RXCDR_CFG2_GEN3 => X"07E6",
+ RXCDR_CFG3 => X"0000",
+ RXCDR_CFG3_GEN3 => X"0000",
+ RXCDR_CFG4 => X"0000",
+ RXCDR_CFG4_GEN3 => X"0000",
+ RXCDR_CFG5 => X"0000",
+ RXCDR_CFG5_GEN3 => X"0000",
+ RXCDR_FR_RESET_ON_EIDLE => '0',
+ RXCDR_HOLD_DURING_EIDLE => '0',
+ RXCDR_LOCK_CFG0 => X"4480",
+ RXCDR_LOCK_CFG1 => X"5FFF",
+ RXCDR_LOCK_CFG2 => X"77C3",
+ RXCDR_PH_RESET_ON_EIDLE => '0',
+ RXCFOK_CFG0 => X"4000",
+ RXCFOK_CFG1 => X"0065",
+ RXCFOK_CFG2 => X"002E",
+ RXDFELPMRESET_TIME => B"0001111",
+ RXDFELPM_KL_CFG0 => X"0000",
+ RXDFELPM_KL_CFG1 => X"0002",
+ RXDFELPM_KL_CFG2 => X"0000",
+ RXDFE_CFG0 => X"0A00",
+ RXDFE_CFG1 => X"0000",
+ RXDFE_GC_CFG0 => X"0000",
+ RXDFE_GC_CFG1 => X"7870",
+ RXDFE_GC_CFG2 => X"0000",
+ RXDFE_H2_CFG0 => X"0000",
+ RXDFE_H2_CFG1 => X"0000",
+ RXDFE_H3_CFG0 => X"4000",
+ RXDFE_H3_CFG1 => X"0000",
+ RXDFE_H4_CFG0 => X"2000",
+ RXDFE_H4_CFG1 => X"0003",
+ RXDFE_H5_CFG0 => X"2000",
+ RXDFE_H5_CFG1 => X"0003",
+ RXDFE_H6_CFG0 => X"2000",
+ RXDFE_H6_CFG1 => X"0000",
+ RXDFE_H7_CFG0 => X"2000",
+ RXDFE_H7_CFG1 => X"0000",
+ RXDFE_H8_CFG0 => X"2000",
+ RXDFE_H8_CFG1 => X"0000",
+ RXDFE_H9_CFG0 => X"2000",
+ RXDFE_H9_CFG1 => X"0000",
+ RXDFE_HA_CFG0 => X"2000",
+ RXDFE_HA_CFG1 => X"0000",
+ RXDFE_HB_CFG0 => X"2000",
+ RXDFE_HB_CFG1 => X"0000",
+ RXDFE_HC_CFG0 => X"0000",
+ RXDFE_HC_CFG1 => X"0000",
+ RXDFE_HD_CFG0 => X"0000",
+ RXDFE_HD_CFG1 => X"0000",
+ RXDFE_HE_CFG0 => X"0000",
+ RXDFE_HE_CFG1 => X"0000",
+ RXDFE_HF_CFG0 => X"0000",
+ RXDFE_HF_CFG1 => X"0000",
+ RXDFE_OS_CFG0 => X"8000",
+ RXDFE_OS_CFG1 => X"0000",
+ RXDFE_UT_CFG0 => X"8000",
+ RXDFE_UT_CFG1 => X"0003",
+ RXDFE_VP_CFG0 => X"AA00",
+ RXDFE_VP_CFG1 => X"0033",
+ RXDLY_CFG => X"001F",
+ RXDLY_LCFG => X"0030",
+ RXELECIDLE_CFG => "Sigcfg_4",
+ RXGBOX_FIFO_INIT_RD_ADDR => 4,
+ RXGEARBOX_EN => "FALSE",
+ RXISCANRESET_TIME => B"00001",
+ RXLPM_CFG => X"0000",
+ RXLPM_GC_CFG => X"1000",
+ RXLPM_KH_CFG0 => X"0000",
+ RXLPM_KH_CFG1 => X"0002",
+ RXLPM_OS_CFG0 => X"8000",
+ RXLPM_OS_CFG1 => X"0002",
+ RXOOB_CFG => B"000000110",
+ RXOOB_CLK_CFG => "PMA",
+ RXOSCALRESET_TIME => B"00011",
+ RXOUT_DIV => 1,
+ RXPCSRESET_TIME => B"00011",
+ RXPHBEACON_CFG => X"0000",
+ RXPHDLY_CFG => X"2020",
+ RXPHSAMP_CFG => X"2100",
+ RXPHSLIP_CFG => X"6622",
+ RXPH_MONITOR_SEL => B"00000",
+ RXPI_CFG0 => B"00",
+ RXPI_CFG1 => B"00",
+ RXPI_CFG2 => B"00",
+ RXPI_CFG3 => B"00",
+ RXPI_CFG4 => '1',
+ RXPI_CFG5 => '1',
+ RXPI_CFG6 => B"011",
+ RXPI_LPM => '0',
+ RXPI_VREFSEL => '0',
+ RXPMACLK_SEL => "DATA",
+ RXPMARESET_TIME => B"00011",
+ RXPRBS_ERR_LOOPBACK => '0',
+ RXPRBS_LINKACQ_CNT => 15,
+ RXSLIDE_AUTO_WAIT => 7,
+ RXSLIDE_MODE => "OFF",
+ RXSYNC_MULTILANE => '1',
+ RXSYNC_OVRD => '0',
+ RXSYNC_SKIP_DA => '0',
+ RX_AFE_CM_EN => '0',
+ RX_BIAS_CFG0 => X"0AB4",
+ RX_BUFFER_CFG => B"000000",
+ RX_CAPFF_SARC_ENB => '0',
+ RX_CLK25_DIV => 13,
+ RX_CLKMUX_EN => '1',
+ RX_CLK_SLIP_OVRD => B"00000",
+ RX_CM_BUF_CFG => B"1010",
+ RX_CM_BUF_PD => '0',
+ RX_CM_SEL => B"11",
+ RX_CM_TRIM => B"1010",
+ RX_CTLE3_LPF => B"00000001",
+ RX_DATA_WIDTH => 16,
+ RX_DDI_SEL => B"000000",
+ RX_DEFER_RESET_BUF_EN => "TRUE",
+ RX_DFELPM_CFG0 => B"0110",
+ RX_DFELPM_CFG1 => '1',
+ RX_DFELPM_KLKH_AGC_STUP_EN => '1',
+ RX_DFE_AGC_CFG0 => B"10",
+ RX_DFE_AGC_CFG1 => B"100",
+ RX_DFE_KL_LPM_KH_CFG0 => B"01",
+ RX_DFE_KL_LPM_KH_CFG1 => B"100",
+ RX_DFE_KL_LPM_KL_CFG0 => B"01",
+ RX_DFE_KL_LPM_KL_CFG1 => B"100",
+ RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
+ RX_DISPERR_SEQ_MATCH => "TRUE",
+ RX_DIVRESET_TIME => B"00001",
+ RX_EN_HI_LR => '0',
+ RX_EYESCAN_VS_CODE => B"0000000",
+ RX_EYESCAN_VS_NEG_DIR => '0',
+ RX_EYESCAN_VS_RANGE => B"00",
+ RX_EYESCAN_VS_UT_SIGN => '0',
+ RX_FABINT_USRCLK_FLOP => '0',
+ RX_INT_DATAWIDTH => 0,
+ RX_PMA_POWER_SAVE => '0',
+ RX_PROGDIV_CFG => 0.000000,
+ RX_SAMPLE_PERIOD => B"111",
+ RX_SIG_VALID_DLY => 11,
+ RX_SUM_DFETAPREP_EN => '0',
+ RX_SUM_IREF_TUNE => B"0000",
+ RX_SUM_RES_CTRL => B"00",
+ RX_SUM_VCMTUNE => B"0000",
+ RX_SUM_VCM_OVWR => '0',
+ RX_SUM_VREF_TUNE => B"000",
+ RX_TUNE_AFE_OS => B"10",
+ RX_WIDEMODE_CDR => '0',
+ RX_XCLK_SEL => "RXDES",
+ SAS_MAX_COM => 64,
+ SAS_MIN_COM => 36,
+ SATA_BURST_SEQ_LEN => B"1110",
+ SATA_BURST_VAL => B"100",
+ SATA_CPLL_CFG => "VCO_3000MHZ",
+ SATA_EIDLE_VAL => B"100",
+ SATA_MAX_BURST => 8,
+ SATA_MAX_INIT => 21,
+ SATA_MAX_WAKE => 7,
+ SATA_MIN_BURST => 4,
+ SATA_MIN_INIT => 12,
+ SATA_MIN_WAKE => 4,
+ SHOW_REALIGN_COMMA => "TRUE",
+ SIM_MODE => "FAST",
+ SIM_RECEIVER_DETECT_PASS => "TRUE",
+ SIM_RESET_SPEEDUP => "TRUE",
+ SIM_TX_EIDLE_DRIVE_LEVEL => '0',
+ SIM_VERSION => 2,
+ TAPDLY_SET_TX => B"00",
+ TEMPERATUR_PAR => B"0010",
+ TERM_RCAL_CFG => B"100001000010000",
+ TERM_RCAL_OVRD => B"000",
+ TRANS_TIME_RATE => X"0E",
+ TST_RSV0 => X"00",
+ TST_RSV1 => X"00",
+ TXBUF_EN => "FALSE",
+ TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ TXDLY_CFG => X"0009",
+ TXDLY_LCFG => X"0050",
+ TXDRVBIAS_N => B"1010",
+ TXDRVBIAS_P => B"1010",
+ TXFIFO_ADDR_CFG => "LOW",
+ TXGBOX_FIFO_INIT_RD_ADDR => 4,
+ TXGEARBOX_EN => "FALSE",
+ TXOUT_DIV => 1,
+ TXPCSRESET_TIME => B"00011",
+ TXPHDLY_CFG0 => X"2020",
+ TXPHDLY_CFG1 => X"0075",
+ TXPH_CFG => X"0980",
+ TXPH_MONITOR_SEL => B"00000",
+ TXPI_CFG0 => B"00",
+ TXPI_CFG1 => B"00",
+ TXPI_CFG2 => B"00",
+ TXPI_CFG3 => '1',
+ TXPI_CFG4 => '1',
+ TXPI_CFG5 => B"000",
+ TXPI_GRAY_SEL => '0',
+ TXPI_INVSTROBE_SEL => '1',
+ TXPI_LPM => '0',
+ TXPI_PPMCLK_SEL => "TXUSRCLK2",
+ TXPI_PPM_CFG => B"00000000",
+ TXPI_SYNFREQ_PPM => B"001",
+ TXPI_VREFSEL => '0',
+ TXPMARESET_TIME => B"00011",
+ TXSYNC_MULTILANE => '1',
+ TXSYNC_OVRD => '0',
+ TXSYNC_SKIP_DA => '0',
+ TX_CLK25_DIV => 10,
+ TX_CLKMUX_EN => '1',
+ TX_DATA_WIDTH => 32,
+ TX_DCD_CFG => B"000010",
+ TX_DCD_EN => '0',
+ TX_DEEMPH0 => B"000000",
+ TX_DEEMPH1 => B"000000",
+ TX_DIVRESET_TIME => B"00001",
+ TX_DRIVE_MODE => "DIRECT",
+ TX_EIDLE_ASSERT_DELAY => B"100",
+ TX_EIDLE_DEASSERT_DELAY => B"011",
+ TX_EML_PHI_TUNE => '0',
+ TX_FABINT_USRCLK_FLOP => '0',
+ TX_IDLE_DATA_ZERO => '0',
+ TX_INT_DATAWIDTH => 1,
+ TX_LOOPBACK_DRIVE_HIZ => "FALSE",
+ TX_MAINCURSOR_SEL => '0',
+ TX_MARGIN_FULL_0 => B"1001111",
+ TX_MARGIN_FULL_1 => B"1001110",
+ TX_MARGIN_FULL_2 => B"1001100",
+ TX_MARGIN_FULL_3 => B"1001010",
+ TX_MARGIN_FULL_4 => B"1001000",
+ TX_MARGIN_LOW_0 => B"1000110",
+ TX_MARGIN_LOW_1 => B"1000101",
+ TX_MARGIN_LOW_2 => B"1000011",
+ TX_MARGIN_LOW_3 => B"1000010",
+ TX_MARGIN_LOW_4 => B"1000000",
+ TX_MODE_SEL => B"000",
+ TX_PMADATA_OPT => '0',
+ TX_PMA_POWER_SAVE => '0',
+ TX_PROGCLK_SEL => "PREPI",
+ TX_PROGDIV_CFG => 16.000000,
+ TX_QPI_STATUS_EN => '0',
+ TX_RXDETECT_CFG => B"00" & X"032",
+ TX_RXDETECT_REF => B"100",
+ TX_SAMPLE_PERIOD => B"111",
+ TX_SARC_LPBK_ENB => '0',
+ TX_XCLK_SEL => "TXUSR",
+ USE_PCS_CLK_PHASE_SEL => '0',
+ WB_MODE => B"00"
+ )
+ port map (
+ BUFGTCE(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_289\,
+ BUFGTCE(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_290\,
+ BUFGTCE(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_291\,
+ BUFGTCEMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_292\,
+ BUFGTCEMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_293\,
+ BUFGTCEMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_294\,
+ BUFGTDIV(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_357\,
+ BUFGTDIV(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_358\,
+ BUFGTDIV(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_359\,
+ BUFGTDIV(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_360\,
+ BUFGTDIV(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_361\,
+ BUFGTDIV(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_362\,
+ BUFGTDIV(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_363\,
+ BUFGTDIV(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_364\,
+ BUFGTDIV(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_365\,
+ BUFGTRESET(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_295\,
+ BUFGTRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_296\,
+ BUFGTRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_297\,
+ BUFGTRSTMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_298\,
+ BUFGTRSTMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_299\,
+ BUFGTRSTMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_300\,
+ CFGRESET => '0',
+ CLKRSVD0 => '0',
+ CLKRSVD1 => '0',
+ CPLLFBCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_0\,
+ CPLLLOCK => cplllock_out(2),
+ CPLLLOCKDETCLK => '0',
+ CPLLLOCKEN => '1',
+ CPLLPD => GTHE3_CHANNEL_CPLLPD(0),
+ CPLLREFCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_2\,
+ CPLLREFCLKSEL(2 downto 0) => B"001",
+ CPLLRESET => '0',
+ DMONFIFORESET => '0',
+ DMONITORCLK => '0',
+ DMONITOROUT(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_258\,
+ DMONITOROUT(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_259\,
+ DMONITOROUT(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_260\,
+ DMONITOROUT(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_261\,
+ DMONITOROUT(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_262\,
+ DMONITOROUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_263\,
+ DMONITOROUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_264\,
+ DMONITOROUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_265\,
+ DMONITOROUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_266\,
+ DMONITOROUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_267\,
+ DMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_268\,
+ DMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_269\,
+ DMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_270\,
+ DMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_271\,
+ DMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_272\,
+ DMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_273\,
+ DMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_274\,
+ DRPADDR(8 downto 0) => B"000000000",
+ DRPCLK => drpclk_in(2),
+ DRPDI(15 downto 0) => B"0000000000000000",
+ DRPDO(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_210\,
+ DRPDO(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_211\,
+ DRPDO(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_212\,
+ DRPDO(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_213\,
+ DRPDO(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_214\,
+ DRPDO(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_215\,
+ DRPDO(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_216\,
+ DRPDO(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_217\,
+ DRPDO(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_218\,
+ DRPDO(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_219\,
+ DRPDO(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_220\,
+ DRPDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_221\,
+ DRPDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_222\,
+ DRPDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_223\,
+ DRPDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_224\,
+ DRPDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_225\,
+ DRPEN => '0',
+ DRPRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_3\,
+ DRPWE => '0',
+ EVODDPHICALDONE => '0',
+ EVODDPHICALSTART => '0',
+ EVODDPHIDRDEN => '0',
+ EVODDPHIDWREN => '0',
+ EVODDPHIXRDEN => '0',
+ EVODDPHIXWREN => '0',
+ EYESCANDATAERROR => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_4\,
+ EYESCANMODE => '0',
+ EYESCANRESET => '0',
+ EYESCANTRIGGER => '0',
+ GTGREFCLK => '0',
+ GTHRXN => gthrxn_in(2),
+ GTHRXP => gthrxp_in(2),
+ GTHTXN => gthtxn_out(2),
+ GTHTXP => gthtxp_out(2),
+ GTNORTHREFCLK0 => '0',
+ GTNORTHREFCLK1 => '0',
+ GTPOWERGOOD => gtpowergood_out(2),
+ GTREFCLK0 => gtrefclk0_in(2),
+ GTREFCLK1 => '0',
+ GTREFCLKMONITOR => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_8\,
+ GTRESETSEL => '0',
+ GTRSVD(15 downto 0) => B"0000000000000000",
+ GTRXRESET => GTHE3_CHANNEL_GTRXRESET(0),
+ GTSOUTHREFCLK0 => '0',
+ GTSOUTHREFCLK1 => '0',
+ GTTXRESET => GTHE3_CHANNEL_GTTXRESET(0),
+ LOOPBACK(2 downto 0) => loopback_in(8 downto 6),
+ LPBKRXTXSEREN => '0',
+ LPBKTXRXSEREN => '0',
+ PCIEEQRXEQADAPTDONE => '0',
+ PCIERATEGEN3 => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_9\,
+ PCIERATEIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_10\,
+ PCIERATEQPLLPD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_275\,
+ PCIERATEQPLLPD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_276\,
+ PCIERATEQPLLRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_277\,
+ PCIERATEQPLLRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_278\,
+ PCIERSTIDLE => '0',
+ PCIERSTTXSYNCSTART => '0',
+ PCIESYNCTXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_11\,
+ PCIEUSERGEN3RDY => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_12\,
+ PCIEUSERPHYSTATUSRST => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_13\,
+ PCIEUSERRATEDONE => '0',
+ PCIEUSERRATESTART => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_14\,
+ PCSRSVDIN(15 downto 0) => B"0000000000000000",
+ PCSRSVDIN2(4 downto 0) => B"00000",
+ PCSRSVDOUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_70\,
+ PCSRSVDOUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_71\,
+ PCSRSVDOUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_72\,
+ PCSRSVDOUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_73\,
+ PCSRSVDOUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_74\,
+ PCSRSVDOUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_75\,
+ PCSRSVDOUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_76\,
+ PCSRSVDOUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_77\,
+ PCSRSVDOUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_78\,
+ PCSRSVDOUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_79\,
+ PCSRSVDOUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_80\,
+ PCSRSVDOUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_81\,
+ PHYSTATUS => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_15\,
+ PINRSRVDAS(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_325\,
+ PINRSRVDAS(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_326\,
+ PINRSRVDAS(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_327\,
+ PINRSRVDAS(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_328\,
+ PINRSRVDAS(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_329\,
+ PINRSRVDAS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_330\,
+ PINRSRVDAS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_331\,
+ PINRSRVDAS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_332\,
+ PMARSVDIN(4 downto 0) => B"00000",
+ QPLL0CLK => qpll0outclk_out(0),
+ QPLL0REFCLK => qpll0outrefclk_out(0),
+ QPLL1CLK => qpll1outclk_out(0),
+ QPLL1REFCLK => qpll1outrefclk_out(0),
+ RESETEXCEPTION => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_16\,
+ RESETOVRD => '0',
+ RSTCLKENTX => '0',
+ RX8B10BEN => '0',
+ RXBUFRESET => '0',
+ RXBUFSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_301\,
+ RXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_302\,
+ RXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_303\,
+ RXBYTEISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_17\,
+ RXBYTEREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_18\,
+ RXCDRFREQRESET => '0',
+ RXCDRHOLD => rxcdrhold_in(2),
+ RXCDRLOCK => rxcdrlock_out(2),
+ RXCDROVRDEN => '0',
+ RXCDRPHDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_20\,
+ RXCDRRESET => '0',
+ RXCDRRESETRSV => '0',
+ RXCHANBONDSEQ => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_21\,
+ RXCHANISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_22\,
+ RXCHANREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_23\,
+ RXCHBONDEN => '0',
+ RXCHBONDI(4 downto 0) => B"00000",
+ RXCHBONDLEVEL(2 downto 0) => B"000",
+ RXCHBONDMASTER => '0',
+ RXCHBONDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_307\,
+ RXCHBONDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_308\,
+ RXCHBONDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_309\,
+ RXCHBONDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_310\,
+ RXCHBONDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_311\,
+ RXCHBONDSLAVE => '0',
+ RXCLKCORCNT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_279\,
+ RXCLKCORCNT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_280\,
+ RXCOMINITDET => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_24\,
+ RXCOMMADET => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_25\,
+ RXCOMMADETEN => '0',
+ RXCOMSASDET => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_26\,
+ RXCOMWAKEDET => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_27\,
+ RXCTRL0(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_226\,
+ RXCTRL0(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_227\,
+ RXCTRL0(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_228\,
+ RXCTRL0(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_229\,
+ RXCTRL0(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_230\,
+ RXCTRL0(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_231\,
+ RXCTRL0(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_232\,
+ RXCTRL0(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_233\,
+ RXCTRL0(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_234\,
+ RXCTRL0(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_235\,
+ RXCTRL0(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_236\,
+ RXCTRL0(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_237\,
+ RXCTRL0(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_238\,
+ RXCTRL0(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_239\,
+ RXCTRL0(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_240\,
+ RXCTRL0(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_241\,
+ RXCTRL1(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_242\,
+ RXCTRL1(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_243\,
+ RXCTRL1(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_244\,
+ RXCTRL1(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_245\,
+ RXCTRL1(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_246\,
+ RXCTRL1(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_247\,
+ RXCTRL1(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_248\,
+ RXCTRL1(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_249\,
+ RXCTRL1(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_250\,
+ RXCTRL1(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_251\,
+ RXCTRL1(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_252\,
+ RXCTRL1(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_253\,
+ RXCTRL1(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_254\,
+ RXCTRL1(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_255\,
+ RXCTRL1(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_256\,
+ RXCTRL1(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_257\,
+ RXCTRL2(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_333\,
+ RXCTRL2(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_334\,
+ RXCTRL2(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_335\,
+ RXCTRL2(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_336\,
+ RXCTRL2(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_337\,
+ RXCTRL2(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_338\,
+ RXCTRL2(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_339\,
+ RXCTRL2(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_340\,
+ RXCTRL3(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_341\,
+ RXCTRL3(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_342\,
+ RXCTRL3(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_343\,
+ RXCTRL3(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_344\,
+ RXCTRL3(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_345\,
+ RXCTRL3(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_346\,
+ RXCTRL3(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_347\,
+ RXCTRL3(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_348\,
+ RXDATA(127) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_82\,
+ RXDATA(126) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_83\,
+ RXDATA(125) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_84\,
+ RXDATA(124) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_85\,
+ RXDATA(123) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_86\,
+ RXDATA(122) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_87\,
+ RXDATA(121) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_88\,
+ RXDATA(120) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_89\,
+ RXDATA(119) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_90\,
+ RXDATA(118) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_91\,
+ RXDATA(117) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_92\,
+ RXDATA(116) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_93\,
+ RXDATA(115) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_94\,
+ RXDATA(114) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_95\,
+ RXDATA(113) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_96\,
+ RXDATA(112) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_97\,
+ RXDATA(111) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_98\,
+ RXDATA(110) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_99\,
+ RXDATA(109) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_100\,
+ RXDATA(108) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_101\,
+ RXDATA(107) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_102\,
+ RXDATA(106) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_103\,
+ RXDATA(105) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_104\,
+ RXDATA(104) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_105\,
+ RXDATA(103) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_106\,
+ RXDATA(102) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_107\,
+ RXDATA(101) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_108\,
+ RXDATA(100) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_109\,
+ RXDATA(99) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_110\,
+ RXDATA(98) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_111\,
+ RXDATA(97) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_112\,
+ RXDATA(96) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_113\,
+ RXDATA(95) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_114\,
+ RXDATA(94) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_115\,
+ RXDATA(93) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_116\,
+ RXDATA(92) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_117\,
+ RXDATA(91) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_118\,
+ RXDATA(90) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_119\,
+ RXDATA(89) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_120\,
+ RXDATA(88) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_121\,
+ RXDATA(87) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_122\,
+ RXDATA(86) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_123\,
+ RXDATA(85) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_124\,
+ RXDATA(84) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_125\,
+ RXDATA(83) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_126\,
+ RXDATA(82) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_127\,
+ RXDATA(81) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_128\,
+ RXDATA(80) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_129\,
+ RXDATA(79) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_130\,
+ RXDATA(78) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_131\,
+ RXDATA(77) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_132\,
+ RXDATA(76) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_133\,
+ RXDATA(75) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_134\,
+ RXDATA(74) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_135\,
+ RXDATA(73) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_136\,
+ RXDATA(72) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_137\,
+ RXDATA(71) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_138\,
+ RXDATA(70) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_139\,
+ RXDATA(69) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_140\,
+ RXDATA(68) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_141\,
+ RXDATA(67) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_142\,
+ RXDATA(66) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_143\,
+ RXDATA(65) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_144\,
+ RXDATA(64) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_145\,
+ RXDATA(63) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_146\,
+ RXDATA(62) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_147\,
+ RXDATA(61) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_148\,
+ RXDATA(60) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_149\,
+ RXDATA(59) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_150\,
+ RXDATA(58) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_151\,
+ RXDATA(57) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_152\,
+ RXDATA(56) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_153\,
+ RXDATA(55) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_154\,
+ RXDATA(54) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_155\,
+ RXDATA(53) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_156\,
+ RXDATA(52) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_157\,
+ RXDATA(51) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_158\,
+ RXDATA(50) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_159\,
+ RXDATA(49) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_160\,
+ RXDATA(48) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_161\,
+ RXDATA(47) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_162\,
+ RXDATA(46) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_163\,
+ RXDATA(45) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_164\,
+ RXDATA(44) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_165\,
+ RXDATA(43) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_166\,
+ RXDATA(42) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_167\,
+ RXDATA(41) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_168\,
+ RXDATA(40) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_169\,
+ RXDATA(39) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_170\,
+ RXDATA(38) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_171\,
+ RXDATA(37) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_172\,
+ RXDATA(36) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_173\,
+ RXDATA(35) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_174\,
+ RXDATA(34) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_175\,
+ RXDATA(33) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_176\,
+ RXDATA(32) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_177\,
+ RXDATA(31) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_178\,
+ RXDATA(30) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_179\,
+ RXDATA(29) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_180\,
+ RXDATA(28) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_181\,
+ RXDATA(27) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_182\,
+ RXDATA(26) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_183\,
+ RXDATA(25) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_184\,
+ RXDATA(24) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_185\,
+ RXDATA(23) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_186\,
+ RXDATA(22) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_187\,
+ RXDATA(21) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_188\,
+ RXDATA(20) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_189\,
+ RXDATA(19) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_190\,
+ RXDATA(18) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_191\,
+ RXDATA(17) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_192\,
+ RXDATA(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_193\,
+ RXDATA(15 downto 0) => gtwiz_userdata_rx_out(47 downto 32),
+ RXDATAEXTENDRSVD(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_349\,
+ RXDATAEXTENDRSVD(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_350\,
+ RXDATAEXTENDRSVD(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_351\,
+ RXDATAEXTENDRSVD(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_352\,
+ RXDATAEXTENDRSVD(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_353\,
+ RXDATAEXTENDRSVD(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_354\,
+ RXDATAEXTENDRSVD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_355\,
+ RXDATAEXTENDRSVD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_356\,
+ RXDATAVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_281\,
+ RXDATAVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_282\,
+ RXDFEAGCCTRL(1 downto 0) => B"01",
+ RXDFEAGCHOLD => '0',
+ RXDFEAGCOVRDEN => '0',
+ RXDFELFHOLD => '0',
+ RXDFELFOVRDEN => '0',
+ RXDFELPMRESET => '0',
+ RXDFETAP10HOLD => '0',
+ RXDFETAP10OVRDEN => '0',
+ RXDFETAP11HOLD => '0',
+ RXDFETAP11OVRDEN => '0',
+ RXDFETAP12HOLD => '0',
+ RXDFETAP12OVRDEN => '0',
+ RXDFETAP13HOLD => '0',
+ RXDFETAP13OVRDEN => '0',
+ RXDFETAP14HOLD => '0',
+ RXDFETAP14OVRDEN => '0',
+ RXDFETAP15HOLD => '0',
+ RXDFETAP15OVRDEN => '0',
+ RXDFETAP2HOLD => '0',
+ RXDFETAP2OVRDEN => '0',
+ RXDFETAP3HOLD => '0',
+ RXDFETAP3OVRDEN => '0',
+ RXDFETAP4HOLD => '0',
+ RXDFETAP4OVRDEN => '0',
+ RXDFETAP5HOLD => '0',
+ RXDFETAP5OVRDEN => '0',
+ RXDFETAP6HOLD => '0',
+ RXDFETAP6OVRDEN => '0',
+ RXDFETAP7HOLD => '0',
+ RXDFETAP7OVRDEN => '0',
+ RXDFETAP8HOLD => '0',
+ RXDFETAP8OVRDEN => '0',
+ RXDFETAP9HOLD => '0',
+ RXDFETAP9OVRDEN => '0',
+ RXDFEUTHOLD => '0',
+ RXDFEUTOVRDEN => '0',
+ RXDFEVPHOLD => '0',
+ RXDFEVPOVRDEN => '0',
+ RXDFEVSEN => '0',
+ RXDFEXYDEN => '1',
+ RXDLYBYPASS => '1',
+ RXDLYEN => '0',
+ RXDLYOVRDEN => '0',
+ RXDLYSRESET => '0',
+ RXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_28\,
+ RXELECIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_29\,
+ RXELECIDLEMODE(1 downto 0) => B"11",
+ RXGEARBOXSLIP => '0',
+ RXHEADER(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_312\,
+ RXHEADER(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_313\,
+ RXHEADER(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_314\,
+ RXHEADER(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_315\,
+ RXHEADER(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_316\,
+ RXHEADER(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_317\,
+ RXHEADERVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_283\,
+ RXHEADERVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_284\,
+ RXLATCLK => '0',
+ RXLPMEN => '0',
+ RXLPMGCHOLD => '0',
+ RXLPMGCOVRDEN => '0',
+ RXLPMHFHOLD => '0',
+ RXLPMHFOVRDEN => '0',
+ RXLPMLFHOLD => '0',
+ RXLPMLFKLOVRDEN => '0',
+ RXLPMOSHOLD => '0',
+ RXLPMOSOVRDEN => '0',
+ RXMCOMMAALIGNEN => '0',
+ RXMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_318\,
+ RXMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_319\,
+ RXMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_320\,
+ RXMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_321\,
+ RXMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_322\,
+ RXMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_323\,
+ RXMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_324\,
+ RXMONITORSEL(1 downto 0) => B"00",
+ RXOOBRESET => '0',
+ RXOSCALRESET => '0',
+ RXOSHOLD => '0',
+ RXOSINTCFG(3 downto 0) => B"1101",
+ RXOSINTDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_30\,
+ RXOSINTEN => '1',
+ RXOSINTHOLD => '0',
+ RXOSINTOVRDEN => '0',
+ RXOSINTSTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_31\,
+ RXOSINTSTROBE => '0',
+ RXOSINTSTROBEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_32\,
+ RXOSINTSTROBESTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_33\,
+ RXOSINTTESTOVRDEN => '0',
+ RXOSOVRDEN => '0',
+ RXOUTCLK => rxoutclk_out(2),
+ RXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_35\,
+ RXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_36\,
+ RXOUTCLKSEL(2 downto 0) => B"010",
+ RXPCOMMAALIGNEN => '0',
+ RXPCSRESET => '0',
+ RXPD(1 downto 0) => B"00",
+ RXPHALIGN => '0',
+ RXPHALIGNDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_37\,
+ RXPHALIGNEN => '0',
+ RXPHALIGNERR => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_38\,
+ RXPHDLYPD => '1',
+ RXPHDLYRESET => '0',
+ RXPHOVRDEN => '0',
+ RXPLLCLKSEL(1 downto 0) => B"00",
+ RXPMARESET => '0',
+ RXPMARESETDONE => rxpmaresetdone_out(2),
+ RXPOLARITY => rxpolarity_in(2),
+ RXPRBSCNTRESET => '0',
+ RXPRBSERR => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_40\,
+ RXPRBSLOCKED => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_41\,
+ RXPRBSSEL(3 downto 0) => B"0000",
+ RXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_42\,
+ RXPROGDIVRESET => GTHE3_CHANNEL_RXPROGDIVRESET(0),
+ RXQPIEN => '0',
+ RXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_43\,
+ RXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_44\,
+ RXRATE(2 downto 0) => B"000",
+ RXRATEDONE => rxratedone_out(2),
+ RXRATEMODE => '0',
+ RXRECCLKOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_46\,
+ RXRESETDONE => rxresetdone_out(2),
+ RXSLIDE => rxslide_in(2),
+ RXSLIDERDY => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_48\,
+ RXSLIPDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_49\,
+ RXSLIPOUTCLK => '0',
+ RXSLIPOUTCLKRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_50\,
+ RXSLIPPMA => '0',
+ RXSLIPPMARDY => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_51\,
+ RXSTARTOFSEQ(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_285\,
+ RXSTARTOFSEQ(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_286\,
+ RXSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_304\,
+ RXSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_305\,
+ RXSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_306\,
+ RXSYNCALLIN => '0',
+ RXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_52\,
+ RXSYNCIN => '0',
+ RXSYNCMODE => '0',
+ RXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_53\,
+ RXSYSCLKSEL(1 downto 0) => B"00",
+ RXUSERRDY => GTHE3_CHANNEL_RXUSERRDY(0),
+ RXUSRCLK => rxusrclk_in(2),
+ RXUSRCLK2 => rxusrclk2_in(2),
+ RXVALID => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_54\,
+ SIGVALIDCLK => '0',
+ TSTIN(19 downto 0) => B"00000000000000000000",
+ TX8B10BBYPASS(7 downto 0) => B"00000000",
+ TX8B10BEN => '0',
+ TXBUFDIFFCTRL(2 downto 0) => B"000",
+ TXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_287\,
+ TXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_288\,
+ TXCOMFINISH => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_55\,
+ TXCOMINIT => '0',
+ TXCOMSAS => '0',
+ TXCOMWAKE => '0',
+ TXCTRL0(15 downto 0) => B"0000000000000000",
+ TXCTRL1(15 downto 0) => B"0000000000000000",
+ TXCTRL2(7 downto 0) => B"00000000",
+ TXDATA(127 downto 32) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ TXDATA(31 downto 0) => gtwiz_userdata_tx_in(95 downto 64),
+ TXDATAEXTENDRSVD(7 downto 0) => B"00000000",
+ TXDEEMPH => '0',
+ TXDETECTRX => '0',
+ TXDIFFCTRL(3 downto 0) => B"1100",
+ TXDIFFPD => '0',
+ TXDLYBYPASS => '0',
+ TXDLYEN => '0',
+ TXDLYHOLD => '0',
+ TXDLYOVRDEN => '0',
+ TXDLYSRESET => GTHE3_CHANNEL_TXDLYSRESET(0),
+ TXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_56\,
+ TXDLYUPDOWN => '0',
+ TXELECIDLE => '0',
+ TXHEADER(5 downto 0) => B"000000",
+ TXINHIBIT => '0',
+ TXLATCLK => '0',
+ TXMAINCURSOR(6 downto 0) => B"1000000",
+ TXMARGIN(2 downto 0) => B"000",
+ TXOUTCLK => txoutclk_out(2),
+ TXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_58\,
+ TXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_59\,
+ TXOUTCLKSEL(2 downto 0) => B"101",
+ TXPCSRESET => '0',
+ TXPD(1 downto 0) => B"00",
+ TXPDELECIDLEMODE => '0',
+ TXPHALIGN => '0',
+ TXPHALIGNDONE => GTHE3_CHANNEL_TXPHALIGNDONE(2),
+ TXPHALIGNEN => '0',
+ TXPHDLYPD => '0',
+ TXPHDLYRESET => '0',
+ TXPHDLYTSTCLK => '0',
+ TXPHINIT => '0',
+ TXPHINITDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_61\,
+ TXPHOVRDEN => '0',
+ TXPIPPMEN => '0',
+ TXPIPPMOVRDEN => '0',
+ TXPIPPMPD => '0',
+ TXPIPPMSEL => '0',
+ TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
+ TXPISOPD => '0',
+ TXPLLCLKSEL(1 downto 0) => B"10",
+ TXPMARESET => '0',
+ TXPMARESETDONE => txpmaresetdone_out(2),
+ TXPOLARITY => txpolarity_in(2),
+ TXPOSTCURSOR(4 downto 0) => B"00000",
+ TXPOSTCURSORINV => '0',
+ TXPRBSFORCEERR => '0',
+ TXPRBSSEL(3 downto 0) => B"0000",
+ TXPRECURSOR(4 downto 0) => B"00000",
+ TXPRECURSORINV => '0',
+ TXPRGDIVRESETDONE => txprgdivresetdone_out(2),
+ TXPROGDIVRESET => GTHE3_CHANNEL_TXPROGDIVRESET(0),
+ TXQPIBIASEN => '0',
+ TXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_64\,
+ TXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_65\,
+ TXQPISTRONGPDOWN => '0',
+ TXQPIWEAKPUP => '0',
+ TXRATE(2 downto 0) => B"000",
+ TXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_66\,
+ TXRATEMODE => '0',
+ TXRESETDONE => txresetdone_out(2),
+ TXSEQUENCE(6 downto 0) => B"0000000",
+ TXSWING => '0',
+ TXSYNCALLIN => GTHE3_CHANNEL_TXSYNCALLIN(0),
+ TXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_68\,
+ TXSYNCIN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYNCMODE => '0',
+ TXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYSCLKSEL(1 downto 0) => B"11",
+ TXUSERRDY => GTHE3_CHANNEL_TXUSERRDY(0),
+ TXUSRCLK => txusrclk_in(2),
+ TXUSRCLK2 => txusrclk2_in(2)
+ );
+\gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST\: unisim.vcomponents.GTHE3_CHANNEL
+ generic map(
+ ACJTAG_DEBUG_MODE => '0',
+ ACJTAG_MODE => '0',
+ ACJTAG_RESET => '0',
+ ADAPT_CFG0 => X"F800",
+ ADAPT_CFG1 => X"0000",
+ ALIGN_COMMA_DOUBLE => "FALSE",
+ ALIGN_COMMA_ENABLE => B"0000000000",
+ ALIGN_COMMA_WORD => 1,
+ ALIGN_MCOMMA_DET => "FALSE",
+ ALIGN_MCOMMA_VALUE => B"1010000011",
+ ALIGN_PCOMMA_DET => "FALSE",
+ ALIGN_PCOMMA_VALUE => B"0101111100",
+ A_RXOSCALRESET => '0',
+ A_RXPROGDIVRESET => '0',
+ A_TXPROGDIVRESET => '0',
+ CBCC_DATA_SOURCE_SEL => "ENCODED",
+ CDR_SWAP_MODE_EN => '0',
+ CHAN_BOND_KEEP_ALIGN => "FALSE",
+ CHAN_BOND_MAX_SKEW => 1,
+ CHAN_BOND_SEQ_1_1 => B"0000000000",
+ CHAN_BOND_SEQ_1_2 => B"0000000000",
+ CHAN_BOND_SEQ_1_3 => B"0000000000",
+ CHAN_BOND_SEQ_1_4 => B"0000000000",
+ CHAN_BOND_SEQ_1_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_1 => B"0000000000",
+ CHAN_BOND_SEQ_2_2 => B"0000000000",
+ CHAN_BOND_SEQ_2_3 => B"0000000000",
+ CHAN_BOND_SEQ_2_4 => B"0000000000",
+ CHAN_BOND_SEQ_2_ENABLE => B"1111",
+ CHAN_BOND_SEQ_2_USE => "FALSE",
+ CHAN_BOND_SEQ_LEN => 1,
+ CLK_CORRECT_USE => "FALSE",
+ CLK_COR_KEEP_IDLE => "FALSE",
+ CLK_COR_MAX_LAT => 6,
+ CLK_COR_MIN_LAT => 4,
+ CLK_COR_PRECEDENCE => "TRUE",
+ CLK_COR_REPEAT_WAIT => 0,
+ CLK_COR_SEQ_1_1 => B"0000000000",
+ CLK_COR_SEQ_1_2 => B"0000000000",
+ CLK_COR_SEQ_1_3 => B"0000000000",
+ CLK_COR_SEQ_1_4 => B"0000000000",
+ CLK_COR_SEQ_1_ENABLE => B"1111",
+ CLK_COR_SEQ_2_1 => B"0000000000",
+ CLK_COR_SEQ_2_2 => B"0000000000",
+ CLK_COR_SEQ_2_3 => B"0000000000",
+ CLK_COR_SEQ_2_4 => B"0000000000",
+ CLK_COR_SEQ_2_ENABLE => B"1111",
+ CLK_COR_SEQ_2_USE => "FALSE",
+ CLK_COR_SEQ_LEN => 1,
+ CPLL_CFG0 => X"67F8",
+ CPLL_CFG1 => X"A4AC",
+ CPLL_CFG2 => X"5007",
+ CPLL_CFG3 => B"00" & X"0",
+ CPLL_FBDIV => 2,
+ CPLL_FBDIV_45 => 4,
+ CPLL_INIT_CFG0 => X"02B2",
+ CPLL_INIT_CFG1 => X"00",
+ CPLL_LOCK_CFG => X"01E8",
+ CPLL_REFCLK_DIV => 1,
+ DDI_CTRL => B"00",
+ DDI_REALIGN_WAIT => 15,
+ DEC_MCOMMA_DETECT => "FALSE",
+ DEC_PCOMMA_DETECT => "FALSE",
+ DEC_VALID_COMMA_ONLY => "FALSE",
+ DFE_D_X_REL_POS => '0',
+ DFE_VCM_COMP_EN => '0',
+ DMONITOR_CFG0 => B"00" & X"00",
+ DMONITOR_CFG1 => X"00",
+ ES_CLK_PHASE_SEL => '0',
+ ES_CONTROL => B"000000",
+ ES_ERRDET_EN => "FALSE",
+ ES_EYE_SCAN_EN => "FALSE",
+ ES_HORZ_OFFSET => X"000",
+ ES_PMA_CFG => B"0000000000",
+ ES_PRESCALE => B"00000",
+ ES_QUALIFIER0 => X"0000",
+ ES_QUALIFIER1 => X"0000",
+ ES_QUALIFIER2 => X"0000",
+ ES_QUALIFIER3 => X"0000",
+ ES_QUALIFIER4 => X"0000",
+ ES_QUAL_MASK0 => X"0000",
+ ES_QUAL_MASK1 => X"0000",
+ ES_QUAL_MASK2 => X"0000",
+ ES_QUAL_MASK3 => X"0000",
+ ES_QUAL_MASK4 => X"0000",
+ ES_SDATA_MASK0 => X"0000",
+ ES_SDATA_MASK1 => X"0000",
+ ES_SDATA_MASK2 => X"0000",
+ ES_SDATA_MASK3 => X"0000",
+ ES_SDATA_MASK4 => X"0000",
+ EVODD_PHI_CFG => B"00000000000",
+ EYE_SCAN_SWAP_EN => '0',
+ FTS_DESKEW_SEQ_ENABLE => B"1111",
+ FTS_LANE_DESKEW_CFG => B"1111",
+ FTS_LANE_DESKEW_EN => "FALSE",
+ GEARBOX_MODE => B"00000",
+ GM_BIAS_SELECT => '0',
+ LOCAL_MASTER => '1',
+ OOBDIVCTL => B"00",
+ OOB_PWRUP => '0',
+ PCI3_AUTO_REALIGN => "OVR_1K_BLK",
+ PCI3_PIPE_RX_ELECIDLE => '0',
+ PCI3_RX_ASYNC_EBUF_BYPASS => B"00",
+ PCI3_RX_ELECIDLE_EI2_ENABLE => '0',
+ PCI3_RX_ELECIDLE_H2L_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_H2L_DISABLE => B"000",
+ PCI3_RX_ELECIDLE_HI_COUNT => B"000000",
+ PCI3_RX_ELECIDLE_LP4_DISABLE => '0',
+ PCI3_RX_FIFO_DISABLE => '0',
+ PCIE_BUFG_DIV_CTRL => X"1000",
+ PCIE_RXPCS_CFG_GEN3 => X"02A4",
+ PCIE_RXPMA_CFG => X"000A",
+ PCIE_TXPCS_CFG_GEN3 => X"24A4",
+ PCIE_TXPMA_CFG => X"000A",
+ PCS_PCIE_EN => "FALSE",
+ PCS_RSVD0 => B"0000000000000000",
+ PCS_RSVD1 => B"000",
+ PD_TRANS_TIME_FROM_P2 => X"03C",
+ PD_TRANS_TIME_NONE_P2 => X"19",
+ PD_TRANS_TIME_TO_P2 => X"64",
+ PLL_SEL_MODE_GEN12 => B"00",
+ PLL_SEL_MODE_GEN3 => B"11",
+ PMA_RSV1 => X"F000",
+ PROCESS_PAR => B"010",
+ RATE_SW_USE_DRP => '1',
+ RESET_POWERSAVE_DISABLE => '0',
+ RXBUFRESET_TIME => B"00011",
+ RXBUF_ADDR_MODE => "FAST",
+ RXBUF_EIDLE_HI_CNT => B"1000",
+ RXBUF_EIDLE_LO_CNT => B"0000",
+ RXBUF_EN => "TRUE",
+ RXBUF_RESET_ON_CB_CHANGE => "TRUE",
+ RXBUF_RESET_ON_COMMAALIGN => "FALSE",
+ RXBUF_RESET_ON_EIDLE => "FALSE",
+ RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ RXBUF_THRESH_OVFLW => 61,
+ RXBUF_THRESH_OVRD => "TRUE",
+ RXBUF_THRESH_UNDFLW => 1,
+ RXCDRFREQRESET_TIME => B"00001",
+ RXCDRPHRESET_TIME => B"00001",
+ RXCDR_CFG0 => X"0000",
+ RXCDR_CFG0_GEN3 => X"0000",
+ RXCDR_CFG1 => X"0000",
+ RXCDR_CFG1_GEN3 => X"0000",
+ RXCDR_CFG2 => X"07E6",
+ RXCDR_CFG2_GEN3 => X"07E6",
+ RXCDR_CFG3 => X"0000",
+ RXCDR_CFG3_GEN3 => X"0000",
+ RXCDR_CFG4 => X"0000",
+ RXCDR_CFG4_GEN3 => X"0000",
+ RXCDR_CFG5 => X"0000",
+ RXCDR_CFG5_GEN3 => X"0000",
+ RXCDR_FR_RESET_ON_EIDLE => '0',
+ RXCDR_HOLD_DURING_EIDLE => '0',
+ RXCDR_LOCK_CFG0 => X"4480",
+ RXCDR_LOCK_CFG1 => X"5FFF",
+ RXCDR_LOCK_CFG2 => X"77C3",
+ RXCDR_PH_RESET_ON_EIDLE => '0',
+ RXCFOK_CFG0 => X"4000",
+ RXCFOK_CFG1 => X"0065",
+ RXCFOK_CFG2 => X"002E",
+ RXDFELPMRESET_TIME => B"0001111",
+ RXDFELPM_KL_CFG0 => X"0000",
+ RXDFELPM_KL_CFG1 => X"0002",
+ RXDFELPM_KL_CFG2 => X"0000",
+ RXDFE_CFG0 => X"0A00",
+ RXDFE_CFG1 => X"0000",
+ RXDFE_GC_CFG0 => X"0000",
+ RXDFE_GC_CFG1 => X"7870",
+ RXDFE_GC_CFG2 => X"0000",
+ RXDFE_H2_CFG0 => X"0000",
+ RXDFE_H2_CFG1 => X"0000",
+ RXDFE_H3_CFG0 => X"4000",
+ RXDFE_H3_CFG1 => X"0000",
+ RXDFE_H4_CFG0 => X"2000",
+ RXDFE_H4_CFG1 => X"0003",
+ RXDFE_H5_CFG0 => X"2000",
+ RXDFE_H5_CFG1 => X"0003",
+ RXDFE_H6_CFG0 => X"2000",
+ RXDFE_H6_CFG1 => X"0000",
+ RXDFE_H7_CFG0 => X"2000",
+ RXDFE_H7_CFG1 => X"0000",
+ RXDFE_H8_CFG0 => X"2000",
+ RXDFE_H8_CFG1 => X"0000",
+ RXDFE_H9_CFG0 => X"2000",
+ RXDFE_H9_CFG1 => X"0000",
+ RXDFE_HA_CFG0 => X"2000",
+ RXDFE_HA_CFG1 => X"0000",
+ RXDFE_HB_CFG0 => X"2000",
+ RXDFE_HB_CFG1 => X"0000",
+ RXDFE_HC_CFG0 => X"0000",
+ RXDFE_HC_CFG1 => X"0000",
+ RXDFE_HD_CFG0 => X"0000",
+ RXDFE_HD_CFG1 => X"0000",
+ RXDFE_HE_CFG0 => X"0000",
+ RXDFE_HE_CFG1 => X"0000",
+ RXDFE_HF_CFG0 => X"0000",
+ RXDFE_HF_CFG1 => X"0000",
+ RXDFE_OS_CFG0 => X"8000",
+ RXDFE_OS_CFG1 => X"0000",
+ RXDFE_UT_CFG0 => X"8000",
+ RXDFE_UT_CFG1 => X"0003",
+ RXDFE_VP_CFG0 => X"AA00",
+ RXDFE_VP_CFG1 => X"0033",
+ RXDLY_CFG => X"001F",
+ RXDLY_LCFG => X"0030",
+ RXELECIDLE_CFG => "Sigcfg_4",
+ RXGBOX_FIFO_INIT_RD_ADDR => 4,
+ RXGEARBOX_EN => "FALSE",
+ RXISCANRESET_TIME => B"00001",
+ RXLPM_CFG => X"0000",
+ RXLPM_GC_CFG => X"1000",
+ RXLPM_KH_CFG0 => X"0000",
+ RXLPM_KH_CFG1 => X"0002",
+ RXLPM_OS_CFG0 => X"8000",
+ RXLPM_OS_CFG1 => X"0002",
+ RXOOB_CFG => B"000000110",
+ RXOOB_CLK_CFG => "PMA",
+ RXOSCALRESET_TIME => B"00011",
+ RXOUT_DIV => 1,
+ RXPCSRESET_TIME => B"00011",
+ RXPHBEACON_CFG => X"0000",
+ RXPHDLY_CFG => X"2020",
+ RXPHSAMP_CFG => X"2100",
+ RXPHSLIP_CFG => X"6622",
+ RXPH_MONITOR_SEL => B"00000",
+ RXPI_CFG0 => B"00",
+ RXPI_CFG1 => B"00",
+ RXPI_CFG2 => B"00",
+ RXPI_CFG3 => B"00",
+ RXPI_CFG4 => '1',
+ RXPI_CFG5 => '1',
+ RXPI_CFG6 => B"011",
+ RXPI_LPM => '0',
+ RXPI_VREFSEL => '0',
+ RXPMACLK_SEL => "DATA",
+ RXPMARESET_TIME => B"00011",
+ RXPRBS_ERR_LOOPBACK => '0',
+ RXPRBS_LINKACQ_CNT => 15,
+ RXSLIDE_AUTO_WAIT => 7,
+ RXSLIDE_MODE => "OFF",
+ RXSYNC_MULTILANE => '1',
+ RXSYNC_OVRD => '0',
+ RXSYNC_SKIP_DA => '0',
+ RX_AFE_CM_EN => '0',
+ RX_BIAS_CFG0 => X"0AB4",
+ RX_BUFFER_CFG => B"000000",
+ RX_CAPFF_SARC_ENB => '0',
+ RX_CLK25_DIV => 13,
+ RX_CLKMUX_EN => '1',
+ RX_CLK_SLIP_OVRD => B"00000",
+ RX_CM_BUF_CFG => B"1010",
+ RX_CM_BUF_PD => '0',
+ RX_CM_SEL => B"11",
+ RX_CM_TRIM => B"1010",
+ RX_CTLE3_LPF => B"00000001",
+ RX_DATA_WIDTH => 16,
+ RX_DDI_SEL => B"000000",
+ RX_DEFER_RESET_BUF_EN => "TRUE",
+ RX_DFELPM_CFG0 => B"0110",
+ RX_DFELPM_CFG1 => '1',
+ RX_DFELPM_KLKH_AGC_STUP_EN => '1',
+ RX_DFE_AGC_CFG0 => B"10",
+ RX_DFE_AGC_CFG1 => B"100",
+ RX_DFE_KL_LPM_KH_CFG0 => B"01",
+ RX_DFE_KL_LPM_KH_CFG1 => B"100",
+ RX_DFE_KL_LPM_KL_CFG0 => B"01",
+ RX_DFE_KL_LPM_KL_CFG1 => B"100",
+ RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
+ RX_DISPERR_SEQ_MATCH => "TRUE",
+ RX_DIVRESET_TIME => B"00001",
+ RX_EN_HI_LR => '0',
+ RX_EYESCAN_VS_CODE => B"0000000",
+ RX_EYESCAN_VS_NEG_DIR => '0',
+ RX_EYESCAN_VS_RANGE => B"00",
+ RX_EYESCAN_VS_UT_SIGN => '0',
+ RX_FABINT_USRCLK_FLOP => '0',
+ RX_INT_DATAWIDTH => 0,
+ RX_PMA_POWER_SAVE => '0',
+ RX_PROGDIV_CFG => 0.000000,
+ RX_SAMPLE_PERIOD => B"111",
+ RX_SIG_VALID_DLY => 11,
+ RX_SUM_DFETAPREP_EN => '0',
+ RX_SUM_IREF_TUNE => B"0000",
+ RX_SUM_RES_CTRL => B"00",
+ RX_SUM_VCMTUNE => B"0000",
+ RX_SUM_VCM_OVWR => '0',
+ RX_SUM_VREF_TUNE => B"000",
+ RX_TUNE_AFE_OS => B"10",
+ RX_WIDEMODE_CDR => '0',
+ RX_XCLK_SEL => "RXDES",
+ SAS_MAX_COM => 64,
+ SAS_MIN_COM => 36,
+ SATA_BURST_SEQ_LEN => B"1110",
+ SATA_BURST_VAL => B"100",
+ SATA_CPLL_CFG => "VCO_3000MHZ",
+ SATA_EIDLE_VAL => B"100",
+ SATA_MAX_BURST => 8,
+ SATA_MAX_INIT => 21,
+ SATA_MAX_WAKE => 7,
+ SATA_MIN_BURST => 4,
+ SATA_MIN_INIT => 12,
+ SATA_MIN_WAKE => 4,
+ SHOW_REALIGN_COMMA => "TRUE",
+ SIM_MODE => "FAST",
+ SIM_RECEIVER_DETECT_PASS => "TRUE",
+ SIM_RESET_SPEEDUP => "TRUE",
+ SIM_TX_EIDLE_DRIVE_LEVEL => '0',
+ SIM_VERSION => 2,
+ TAPDLY_SET_TX => B"00",
+ TEMPERATUR_PAR => B"0010",
+ TERM_RCAL_CFG => B"100001000010000",
+ TERM_RCAL_OVRD => B"000",
+ TRANS_TIME_RATE => X"0E",
+ TST_RSV0 => X"00",
+ TST_RSV1 => X"00",
+ TXBUF_EN => "FALSE",
+ TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
+ TXDLY_CFG => X"0009",
+ TXDLY_LCFG => X"0050",
+ TXDRVBIAS_N => B"1010",
+ TXDRVBIAS_P => B"1010",
+ TXFIFO_ADDR_CFG => "LOW",
+ TXGBOX_FIFO_INIT_RD_ADDR => 4,
+ TXGEARBOX_EN => "FALSE",
+ TXOUT_DIV => 1,
+ TXPCSRESET_TIME => B"00011",
+ TXPHDLY_CFG0 => X"2020",
+ TXPHDLY_CFG1 => X"0075",
+ TXPH_CFG => X"0980",
+ TXPH_MONITOR_SEL => B"00000",
+ TXPI_CFG0 => B"00",
+ TXPI_CFG1 => B"00",
+ TXPI_CFG2 => B"00",
+ TXPI_CFG3 => '1',
+ TXPI_CFG4 => '1',
+ TXPI_CFG5 => B"000",
+ TXPI_GRAY_SEL => '0',
+ TXPI_INVSTROBE_SEL => '1',
+ TXPI_LPM => '0',
+ TXPI_PPMCLK_SEL => "TXUSRCLK2",
+ TXPI_PPM_CFG => B"00000000",
+ TXPI_SYNFREQ_PPM => B"001",
+ TXPI_VREFSEL => '0',
+ TXPMARESET_TIME => B"00011",
+ TXSYNC_MULTILANE => '1',
+ TXSYNC_OVRD => '0',
+ TXSYNC_SKIP_DA => '0',
+ TX_CLK25_DIV => 10,
+ TX_CLKMUX_EN => '1',
+ TX_DATA_WIDTH => 32,
+ TX_DCD_CFG => B"000010",
+ TX_DCD_EN => '0',
+ TX_DEEMPH0 => B"000000",
+ TX_DEEMPH1 => B"000000",
+ TX_DIVRESET_TIME => B"00001",
+ TX_DRIVE_MODE => "DIRECT",
+ TX_EIDLE_ASSERT_DELAY => B"100",
+ TX_EIDLE_DEASSERT_DELAY => B"011",
+ TX_EML_PHI_TUNE => '0',
+ TX_FABINT_USRCLK_FLOP => '0',
+ TX_IDLE_DATA_ZERO => '0',
+ TX_INT_DATAWIDTH => 1,
+ TX_LOOPBACK_DRIVE_HIZ => "FALSE",
+ TX_MAINCURSOR_SEL => '0',
+ TX_MARGIN_FULL_0 => B"1001111",
+ TX_MARGIN_FULL_1 => B"1001110",
+ TX_MARGIN_FULL_2 => B"1001100",
+ TX_MARGIN_FULL_3 => B"1001010",
+ TX_MARGIN_FULL_4 => B"1001000",
+ TX_MARGIN_LOW_0 => B"1000110",
+ TX_MARGIN_LOW_1 => B"1000101",
+ TX_MARGIN_LOW_2 => B"1000011",
+ TX_MARGIN_LOW_3 => B"1000010",
+ TX_MARGIN_LOW_4 => B"1000000",
+ TX_MODE_SEL => B"000",
+ TX_PMADATA_OPT => '0',
+ TX_PMA_POWER_SAVE => '0',
+ TX_PROGCLK_SEL => "PREPI",
+ TX_PROGDIV_CFG => 16.000000,
+ TX_QPI_STATUS_EN => '0',
+ TX_RXDETECT_CFG => B"00" & X"032",
+ TX_RXDETECT_REF => B"100",
+ TX_SAMPLE_PERIOD => B"111",
+ TX_SARC_LPBK_ENB => '0',
+ TX_XCLK_SEL => "TXUSR",
+ USE_PCS_CLK_PHASE_SEL => '0',
+ WB_MODE => B"00"
+ )
+ port map (
+ BUFGTCE(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_289\,
+ BUFGTCE(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_290\,
+ BUFGTCE(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_291\,
+ BUFGTCEMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_292\,
+ BUFGTCEMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_293\,
+ BUFGTCEMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_294\,
+ BUFGTDIV(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_357\,
+ BUFGTDIV(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_358\,
+ BUFGTDIV(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_359\,
+ BUFGTDIV(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_360\,
+ BUFGTDIV(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_361\,
+ BUFGTDIV(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_362\,
+ BUFGTDIV(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_363\,
+ BUFGTDIV(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_364\,
+ BUFGTDIV(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_365\,
+ BUFGTRESET(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_295\,
+ BUFGTRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_296\,
+ BUFGTRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_297\,
+ BUFGTRSTMASK(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_298\,
+ BUFGTRSTMASK(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_299\,
+ BUFGTRSTMASK(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_300\,
+ CFGRESET => '0',
+ CLKRSVD0 => '0',
+ CLKRSVD1 => '0',
+ CPLLFBCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_0\,
+ CPLLLOCK => cplllock_out(3),
+ CPLLLOCKDETCLK => '0',
+ CPLLLOCKEN => '1',
+ CPLLPD => GTHE3_CHANNEL_CPLLPD(0),
+ CPLLREFCLKLOST => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_2\,
+ CPLLREFCLKSEL(2 downto 0) => B"001",
+ CPLLRESET => '0',
+ DMONFIFORESET => '0',
+ DMONITORCLK => '0',
+ DMONITOROUT(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_258\,
+ DMONITOROUT(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_259\,
+ DMONITOROUT(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_260\,
+ DMONITOROUT(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_261\,
+ DMONITOROUT(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_262\,
+ DMONITOROUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_263\,
+ DMONITOROUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_264\,
+ DMONITOROUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_265\,
+ DMONITOROUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_266\,
+ DMONITOROUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_267\,
+ DMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_268\,
+ DMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_269\,
+ DMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_270\,
+ DMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_271\,
+ DMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_272\,
+ DMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_273\,
+ DMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_274\,
+ DRPADDR(8 downto 0) => B"000000000",
+ DRPCLK => drpclk_in(3),
+ DRPDI(15 downto 0) => B"0000000000000000",
+ DRPDO(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_210\,
+ DRPDO(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_211\,
+ DRPDO(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_212\,
+ DRPDO(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_213\,
+ DRPDO(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_214\,
+ DRPDO(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_215\,
+ DRPDO(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_216\,
+ DRPDO(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_217\,
+ DRPDO(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_218\,
+ DRPDO(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_219\,
+ DRPDO(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_220\,
+ DRPDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_221\,
+ DRPDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_222\,
+ DRPDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_223\,
+ DRPDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_224\,
+ DRPDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_225\,
+ DRPEN => '0',
+ DRPRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_3\,
+ DRPWE => '0',
+ EVODDPHICALDONE => '0',
+ EVODDPHICALSTART => '0',
+ EVODDPHIDRDEN => '0',
+ EVODDPHIDWREN => '0',
+ EVODDPHIXRDEN => '0',
+ EVODDPHIXWREN => '0',
+ EYESCANDATAERROR => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_4\,
+ EYESCANMODE => '0',
+ EYESCANRESET => '0',
+ EYESCANTRIGGER => '0',
+ GTGREFCLK => '0',
+ GTHRXN => gthrxn_in(3),
+ GTHRXP => gthrxp_in(3),
+ GTHTXN => gthtxn_out(3),
+ GTHTXP => gthtxp_out(3),
+ GTNORTHREFCLK0 => '0',
+ GTNORTHREFCLK1 => '0',
+ GTPOWERGOOD => gtpowergood_out(3),
+ GTREFCLK0 => gtrefclk0_in(3),
+ GTREFCLK1 => '0',
+ GTREFCLKMONITOR => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_8\,
+ GTRESETSEL => '0',
+ GTRSVD(15 downto 0) => B"0000000000000000",
+ GTRXRESET => GTHE3_CHANNEL_GTRXRESET(0),
+ GTSOUTHREFCLK0 => '0',
+ GTSOUTHREFCLK1 => '0',
+ GTTXRESET => GTHE3_CHANNEL_GTTXRESET(0),
+ LOOPBACK(2 downto 0) => loopback_in(11 downto 9),
+ LPBKRXTXSEREN => '0',
+ LPBKTXRXSEREN => '0',
+ PCIEEQRXEQADAPTDONE => '0',
+ PCIERATEGEN3 => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_9\,
+ PCIERATEIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_10\,
+ PCIERATEQPLLPD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_275\,
+ PCIERATEQPLLPD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_276\,
+ PCIERATEQPLLRESET(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_277\,
+ PCIERATEQPLLRESET(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_278\,
+ PCIERSTIDLE => '0',
+ PCIERSTTXSYNCSTART => '0',
+ PCIESYNCTXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_11\,
+ PCIEUSERGEN3RDY => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_12\,
+ PCIEUSERPHYSTATUSRST => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_13\,
+ PCIEUSERRATEDONE => '0',
+ PCIEUSERRATESTART => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_14\,
+ PCSRSVDIN(15 downto 0) => B"0000000000000000",
+ PCSRSVDIN2(4 downto 0) => B"00000",
+ PCSRSVDOUT(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_70\,
+ PCSRSVDOUT(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_71\,
+ PCSRSVDOUT(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_72\,
+ PCSRSVDOUT(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_73\,
+ PCSRSVDOUT(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_74\,
+ PCSRSVDOUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_75\,
+ PCSRSVDOUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_76\,
+ PCSRSVDOUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_77\,
+ PCSRSVDOUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_78\,
+ PCSRSVDOUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_79\,
+ PCSRSVDOUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_80\,
+ PCSRSVDOUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_81\,
+ PHYSTATUS => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_15\,
+ PINRSRVDAS(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_325\,
+ PINRSRVDAS(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_326\,
+ PINRSRVDAS(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_327\,
+ PINRSRVDAS(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_328\,
+ PINRSRVDAS(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_329\,
+ PINRSRVDAS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_330\,
+ PINRSRVDAS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_331\,
+ PINRSRVDAS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_332\,
+ PMARSVDIN(4 downto 0) => B"00000",
+ QPLL0CLK => qpll0outclk_out(0),
+ QPLL0REFCLK => qpll0outrefclk_out(0),
+ QPLL1CLK => qpll1outclk_out(0),
+ QPLL1REFCLK => qpll1outrefclk_out(0),
+ RESETEXCEPTION => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_16\,
+ RESETOVRD => '0',
+ RSTCLKENTX => '0',
+ RX8B10BEN => '0',
+ RXBUFRESET => '0',
+ RXBUFSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_301\,
+ RXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_302\,
+ RXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_303\,
+ RXBYTEISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_17\,
+ RXBYTEREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_18\,
+ RXCDRFREQRESET => '0',
+ RXCDRHOLD => rxcdrhold_in(3),
+ RXCDRLOCK => rxcdrlock_out(3),
+ RXCDROVRDEN => '0',
+ RXCDRPHDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_20\,
+ RXCDRRESET => '0',
+ RXCDRRESETRSV => '0',
+ RXCHANBONDSEQ => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_21\,
+ RXCHANISALIGNED => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_22\,
+ RXCHANREALIGN => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_23\,
+ RXCHBONDEN => '0',
+ RXCHBONDI(4 downto 0) => B"00000",
+ RXCHBONDLEVEL(2 downto 0) => B"000",
+ RXCHBONDMASTER => '0',
+ RXCHBONDO(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_307\,
+ RXCHBONDO(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_308\,
+ RXCHBONDO(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_309\,
+ RXCHBONDO(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_310\,
+ RXCHBONDO(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_311\,
+ RXCHBONDSLAVE => '0',
+ RXCLKCORCNT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_279\,
+ RXCLKCORCNT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_280\,
+ RXCOMINITDET => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_24\,
+ RXCOMMADET => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_25\,
+ RXCOMMADETEN => '0',
+ RXCOMSASDET => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_26\,
+ RXCOMWAKEDET => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_27\,
+ RXCTRL0(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_226\,
+ RXCTRL0(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_227\,
+ RXCTRL0(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_228\,
+ RXCTRL0(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_229\,
+ RXCTRL0(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_230\,
+ RXCTRL0(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_231\,
+ RXCTRL0(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_232\,
+ RXCTRL0(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_233\,
+ RXCTRL0(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_234\,
+ RXCTRL0(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_235\,
+ RXCTRL0(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_236\,
+ RXCTRL0(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_237\,
+ RXCTRL0(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_238\,
+ RXCTRL0(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_239\,
+ RXCTRL0(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_240\,
+ RXCTRL0(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_241\,
+ RXCTRL1(15) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_242\,
+ RXCTRL1(14) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_243\,
+ RXCTRL1(13) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_244\,
+ RXCTRL1(12) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_245\,
+ RXCTRL1(11) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_246\,
+ RXCTRL1(10) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_247\,
+ RXCTRL1(9) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_248\,
+ RXCTRL1(8) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_249\,
+ RXCTRL1(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_250\,
+ RXCTRL1(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_251\,
+ RXCTRL1(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_252\,
+ RXCTRL1(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_253\,
+ RXCTRL1(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_254\,
+ RXCTRL1(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_255\,
+ RXCTRL1(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_256\,
+ RXCTRL1(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_257\,
+ RXCTRL2(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_333\,
+ RXCTRL2(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_334\,
+ RXCTRL2(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_335\,
+ RXCTRL2(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_336\,
+ RXCTRL2(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_337\,
+ RXCTRL2(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_338\,
+ RXCTRL2(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_339\,
+ RXCTRL2(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_340\,
+ RXCTRL3(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_341\,
+ RXCTRL3(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_342\,
+ RXCTRL3(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_343\,
+ RXCTRL3(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_344\,
+ RXCTRL3(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_345\,
+ RXCTRL3(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_346\,
+ RXCTRL3(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_347\,
+ RXCTRL3(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_348\,
+ RXDATA(127) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_82\,
+ RXDATA(126) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_83\,
+ RXDATA(125) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_84\,
+ RXDATA(124) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_85\,
+ RXDATA(123) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_86\,
+ RXDATA(122) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_87\,
+ RXDATA(121) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_88\,
+ RXDATA(120) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_89\,
+ RXDATA(119) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_90\,
+ RXDATA(118) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_91\,
+ RXDATA(117) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_92\,
+ RXDATA(116) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_93\,
+ RXDATA(115) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_94\,
+ RXDATA(114) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_95\,
+ RXDATA(113) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_96\,
+ RXDATA(112) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_97\,
+ RXDATA(111) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_98\,
+ RXDATA(110) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_99\,
+ RXDATA(109) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_100\,
+ RXDATA(108) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_101\,
+ RXDATA(107) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_102\,
+ RXDATA(106) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_103\,
+ RXDATA(105) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_104\,
+ RXDATA(104) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_105\,
+ RXDATA(103) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_106\,
+ RXDATA(102) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_107\,
+ RXDATA(101) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_108\,
+ RXDATA(100) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_109\,
+ RXDATA(99) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_110\,
+ RXDATA(98) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_111\,
+ RXDATA(97) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_112\,
+ RXDATA(96) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_113\,
+ RXDATA(95) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_114\,
+ RXDATA(94) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_115\,
+ RXDATA(93) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_116\,
+ RXDATA(92) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_117\,
+ RXDATA(91) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_118\,
+ RXDATA(90) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_119\,
+ RXDATA(89) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_120\,
+ RXDATA(88) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_121\,
+ RXDATA(87) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_122\,
+ RXDATA(86) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_123\,
+ RXDATA(85) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_124\,
+ RXDATA(84) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_125\,
+ RXDATA(83) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_126\,
+ RXDATA(82) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_127\,
+ RXDATA(81) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_128\,
+ RXDATA(80) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_129\,
+ RXDATA(79) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_130\,
+ RXDATA(78) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_131\,
+ RXDATA(77) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_132\,
+ RXDATA(76) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_133\,
+ RXDATA(75) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_134\,
+ RXDATA(74) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_135\,
+ RXDATA(73) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_136\,
+ RXDATA(72) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_137\,
+ RXDATA(71) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_138\,
+ RXDATA(70) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_139\,
+ RXDATA(69) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_140\,
+ RXDATA(68) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_141\,
+ RXDATA(67) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_142\,
+ RXDATA(66) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_143\,
+ RXDATA(65) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_144\,
+ RXDATA(64) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_145\,
+ RXDATA(63) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_146\,
+ RXDATA(62) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_147\,
+ RXDATA(61) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_148\,
+ RXDATA(60) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_149\,
+ RXDATA(59) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_150\,
+ RXDATA(58) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_151\,
+ RXDATA(57) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_152\,
+ RXDATA(56) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_153\,
+ RXDATA(55) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_154\,
+ RXDATA(54) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_155\,
+ RXDATA(53) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_156\,
+ RXDATA(52) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_157\,
+ RXDATA(51) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_158\,
+ RXDATA(50) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_159\,
+ RXDATA(49) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_160\,
+ RXDATA(48) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_161\,
+ RXDATA(47) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_162\,
+ RXDATA(46) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_163\,
+ RXDATA(45) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_164\,
+ RXDATA(44) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_165\,
+ RXDATA(43) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_166\,
+ RXDATA(42) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_167\,
+ RXDATA(41) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_168\,
+ RXDATA(40) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_169\,
+ RXDATA(39) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_170\,
+ RXDATA(38) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_171\,
+ RXDATA(37) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_172\,
+ RXDATA(36) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_173\,
+ RXDATA(35) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_174\,
+ RXDATA(34) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_175\,
+ RXDATA(33) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_176\,
+ RXDATA(32) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_177\,
+ RXDATA(31) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_178\,
+ RXDATA(30) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_179\,
+ RXDATA(29) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_180\,
+ RXDATA(28) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_181\,
+ RXDATA(27) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_182\,
+ RXDATA(26) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_183\,
+ RXDATA(25) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_184\,
+ RXDATA(24) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_185\,
+ RXDATA(23) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_186\,
+ RXDATA(22) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_187\,
+ RXDATA(21) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_188\,
+ RXDATA(20) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_189\,
+ RXDATA(19) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_190\,
+ RXDATA(18) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_191\,
+ RXDATA(17) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_192\,
+ RXDATA(16) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_193\,
+ RXDATA(15 downto 0) => gtwiz_userdata_rx_out(63 downto 48),
+ RXDATAEXTENDRSVD(7) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_349\,
+ RXDATAEXTENDRSVD(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_350\,
+ RXDATAEXTENDRSVD(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_351\,
+ RXDATAEXTENDRSVD(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_352\,
+ RXDATAEXTENDRSVD(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_353\,
+ RXDATAEXTENDRSVD(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_354\,
+ RXDATAEXTENDRSVD(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_355\,
+ RXDATAEXTENDRSVD(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_356\,
+ RXDATAVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_281\,
+ RXDATAVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_282\,
+ RXDFEAGCCTRL(1 downto 0) => B"01",
+ RXDFEAGCHOLD => '0',
+ RXDFEAGCOVRDEN => '0',
+ RXDFELFHOLD => '0',
+ RXDFELFOVRDEN => '0',
+ RXDFELPMRESET => '0',
+ RXDFETAP10HOLD => '0',
+ RXDFETAP10OVRDEN => '0',
+ RXDFETAP11HOLD => '0',
+ RXDFETAP11OVRDEN => '0',
+ RXDFETAP12HOLD => '0',
+ RXDFETAP12OVRDEN => '0',
+ RXDFETAP13HOLD => '0',
+ RXDFETAP13OVRDEN => '0',
+ RXDFETAP14HOLD => '0',
+ RXDFETAP14OVRDEN => '0',
+ RXDFETAP15HOLD => '0',
+ RXDFETAP15OVRDEN => '0',
+ RXDFETAP2HOLD => '0',
+ RXDFETAP2OVRDEN => '0',
+ RXDFETAP3HOLD => '0',
+ RXDFETAP3OVRDEN => '0',
+ RXDFETAP4HOLD => '0',
+ RXDFETAP4OVRDEN => '0',
+ RXDFETAP5HOLD => '0',
+ RXDFETAP5OVRDEN => '0',
+ RXDFETAP6HOLD => '0',
+ RXDFETAP6OVRDEN => '0',
+ RXDFETAP7HOLD => '0',
+ RXDFETAP7OVRDEN => '0',
+ RXDFETAP8HOLD => '0',
+ RXDFETAP8OVRDEN => '0',
+ RXDFETAP9HOLD => '0',
+ RXDFETAP9OVRDEN => '0',
+ RXDFEUTHOLD => '0',
+ RXDFEUTOVRDEN => '0',
+ RXDFEVPHOLD => '0',
+ RXDFEVPOVRDEN => '0',
+ RXDFEVSEN => '0',
+ RXDFEXYDEN => '1',
+ RXDLYBYPASS => '1',
+ RXDLYEN => '0',
+ RXDLYOVRDEN => '0',
+ RXDLYSRESET => '0',
+ RXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_28\,
+ RXELECIDLE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_29\,
+ RXELECIDLEMODE(1 downto 0) => B"11",
+ RXGEARBOXSLIP => '0',
+ RXHEADER(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_312\,
+ RXHEADER(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_313\,
+ RXHEADER(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_314\,
+ RXHEADER(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_315\,
+ RXHEADER(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_316\,
+ RXHEADER(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_317\,
+ RXHEADERVALID(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_283\,
+ RXHEADERVALID(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_284\,
+ RXLATCLK => '0',
+ RXLPMEN => '0',
+ RXLPMGCHOLD => '0',
+ RXLPMGCOVRDEN => '0',
+ RXLPMHFHOLD => '0',
+ RXLPMHFOVRDEN => '0',
+ RXLPMLFHOLD => '0',
+ RXLPMLFKLOVRDEN => '0',
+ RXLPMOSHOLD => '0',
+ RXLPMOSOVRDEN => '0',
+ RXMCOMMAALIGNEN => '0',
+ RXMONITOROUT(6) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_318\,
+ RXMONITOROUT(5) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_319\,
+ RXMONITOROUT(4) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_320\,
+ RXMONITOROUT(3) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_321\,
+ RXMONITOROUT(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_322\,
+ RXMONITOROUT(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_323\,
+ RXMONITOROUT(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_324\,
+ RXMONITORSEL(1 downto 0) => B"00",
+ RXOOBRESET => '0',
+ RXOSCALRESET => '0',
+ RXOSHOLD => '0',
+ RXOSINTCFG(3 downto 0) => B"1101",
+ RXOSINTDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_30\,
+ RXOSINTEN => '1',
+ RXOSINTHOLD => '0',
+ RXOSINTOVRDEN => '0',
+ RXOSINTSTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_31\,
+ RXOSINTSTROBE => '0',
+ RXOSINTSTROBEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_32\,
+ RXOSINTSTROBESTARTED => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_33\,
+ RXOSINTTESTOVRDEN => '0',
+ RXOSOVRDEN => '0',
+ RXOUTCLK => rxoutclk_out(3),
+ RXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_35\,
+ RXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_36\,
+ RXOUTCLKSEL(2 downto 0) => B"010",
+ RXPCOMMAALIGNEN => '0',
+ RXPCSRESET => '0',
+ RXPD(1 downto 0) => B"00",
+ RXPHALIGN => '0',
+ RXPHALIGNDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_37\,
+ RXPHALIGNEN => '0',
+ RXPHALIGNERR => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_38\,
+ RXPHDLYPD => '1',
+ RXPHDLYRESET => '0',
+ RXPHOVRDEN => '0',
+ RXPLLCLKSEL(1 downto 0) => B"00",
+ RXPMARESET => '0',
+ RXPMARESETDONE => rxpmaresetdone_out(3),
+ RXPOLARITY => rxpolarity_in(3),
+ RXPRBSCNTRESET => '0',
+ RXPRBSERR => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_40\,
+ RXPRBSLOCKED => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_41\,
+ RXPRBSSEL(3 downto 0) => B"0000",
+ RXPRGDIVRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_42\,
+ RXPROGDIVRESET => GTHE3_CHANNEL_RXPROGDIVRESET(0),
+ RXQPIEN => '0',
+ RXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_43\,
+ RXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_44\,
+ RXRATE(2 downto 0) => B"000",
+ RXRATEDONE => rxratedone_out(3),
+ RXRATEMODE => '0',
+ RXRECCLKOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_46\,
+ RXRESETDONE => rxresetdone_out(3),
+ RXSLIDE => rxslide_in(3),
+ RXSLIDERDY => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_48\,
+ RXSLIPDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_49\,
+ RXSLIPOUTCLK => '0',
+ RXSLIPOUTCLKRDY => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_50\,
+ RXSLIPPMA => '0',
+ RXSLIPPMARDY => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_51\,
+ RXSTARTOFSEQ(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_285\,
+ RXSTARTOFSEQ(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_286\,
+ RXSTATUS(2) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_304\,
+ RXSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_305\,
+ RXSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_306\,
+ RXSYNCALLIN => '0',
+ RXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_52\,
+ RXSYNCIN => '0',
+ RXSYNCMODE => '0',
+ RXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_53\,
+ RXSYSCLKSEL(1 downto 0) => B"00",
+ RXUSERRDY => GTHE3_CHANNEL_RXUSERRDY(0),
+ RXUSRCLK => rxusrclk_in(3),
+ RXUSRCLK2 => rxusrclk2_in(3),
+ RXVALID => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_54\,
+ SIGVALIDCLK => '0',
+ TSTIN(19 downto 0) => B"00000000000000000000",
+ TX8B10BBYPASS(7 downto 0) => B"00000000",
+ TX8B10BEN => '0',
+ TXBUFDIFFCTRL(2 downto 0) => B"000",
+ TXBUFSTATUS(1) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_287\,
+ TXBUFSTATUS(0) => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_288\,
+ TXCOMFINISH => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_55\,
+ TXCOMINIT => '0',
+ TXCOMSAS => '0',
+ TXCOMWAKE => '0',
+ TXCTRL0(15 downto 0) => B"0000000000000000",
+ TXCTRL1(15 downto 0) => B"0000000000000000",
+ TXCTRL2(7 downto 0) => B"00000000",
+ TXDATA(127 downto 32) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ TXDATA(31 downto 0) => gtwiz_userdata_tx_in(127 downto 96),
+ TXDATAEXTENDRSVD(7 downto 0) => B"00000000",
+ TXDEEMPH => '0',
+ TXDETECTRX => '0',
+ TXDIFFCTRL(3 downto 0) => B"1100",
+ TXDIFFPD => '0',
+ TXDLYBYPASS => '0',
+ TXDLYEN => '0',
+ TXDLYHOLD => '0',
+ TXDLYOVRDEN => '0',
+ TXDLYSRESET => GTHE3_CHANNEL_TXDLYSRESET(0),
+ TXDLYSRESETDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_56\,
+ TXDLYUPDOWN => '0',
+ TXELECIDLE => '0',
+ TXHEADER(5 downto 0) => B"000000",
+ TXINHIBIT => '0',
+ TXLATCLK => '0',
+ TXMAINCURSOR(6 downto 0) => B"1000000",
+ TXMARGIN(2 downto 0) => B"000",
+ TXOUTCLK => txoutclk_out(3),
+ TXOUTCLKFABRIC => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_58\,
+ TXOUTCLKPCS => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_59\,
+ TXOUTCLKSEL(2 downto 0) => B"101",
+ TXPCSRESET => '0',
+ TXPD(1 downto 0) => B"00",
+ TXPDELECIDLEMODE => '0',
+ TXPHALIGN => '0',
+ TXPHALIGNDONE => GTHE3_CHANNEL_TXPHALIGNDONE(3),
+ TXPHALIGNEN => '0',
+ TXPHDLYPD => '0',
+ TXPHDLYRESET => '0',
+ TXPHDLYTSTCLK => '0',
+ TXPHINIT => '0',
+ TXPHINITDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_61\,
+ TXPHOVRDEN => '0',
+ TXPIPPMEN => '0',
+ TXPIPPMOVRDEN => '0',
+ TXPIPPMPD => '0',
+ TXPIPPMSEL => '0',
+ TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
+ TXPISOPD => '0',
+ TXPLLCLKSEL(1 downto 0) => B"10",
+ TXPMARESET => '0',
+ TXPMARESETDONE => txpmaresetdone_out(3),
+ TXPOLARITY => txpolarity_in(3),
+ TXPOSTCURSOR(4 downto 0) => B"00000",
+ TXPOSTCURSORINV => '0',
+ TXPRBSFORCEERR => '0',
+ TXPRBSSEL(3 downto 0) => B"0000",
+ TXPRECURSOR(4 downto 0) => B"00000",
+ TXPRECURSORINV => '0',
+ TXPRGDIVRESETDONE => txprgdivresetdone_out(3),
+ TXPROGDIVRESET => GTHE3_CHANNEL_TXPROGDIVRESET(0),
+ TXQPIBIASEN => '0',
+ TXQPISENN => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_64\,
+ TXQPISENP => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_65\,
+ TXQPISTRONGPDOWN => '0',
+ TXQPIWEAKPUP => '0',
+ TXRATE(2 downto 0) => B"000",
+ TXRATEDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_66\,
+ TXRATEMODE => '0',
+ TXRESETDONE => txresetdone_out(3),
+ TXSEQUENCE(6 downto 0) => B"0000000",
+ TXSWING => '0',
+ TXSYNCALLIN => GTHE3_CHANNEL_TXSYNCALLIN(0),
+ TXSYNCDONE => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_68\,
+ TXSYNCIN => \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYNCMODE => '0',
+ TXSYNCOUT => \gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST_n_69\,
+ TXSYSCLKSEL(1 downto 0) => B"11",
+ TXUSERRDY => GTHE3_CHANNEL_TXUSERRDY(0),
+ TXUSRCLK => txusrclk_in(3),
+ TXUSRCLK2 => txusrclk2_in(3)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gthe3_common is
+ port (
+ qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in0 : out STD_LOGIC;
+ gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_0\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gthe3_common : entity is "gtwizard_ultrascale_v1_7_18_gthe3_common";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gthe3_common;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gthe3_common is
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_0\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_10\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_11\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_12\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_13\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_14\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_15\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_16\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_17\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_18\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_19\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_20\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_21\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_22\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_23\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_24\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_25\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_26\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_27\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_28\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_29\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_30\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_31\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_32\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_33\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_34\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_35\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_36\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_37\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_38\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_39\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_40\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_41\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_42\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_43\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_44\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_45\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_46\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_47\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_48\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_49\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_5\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_50\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_51\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_52\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_53\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_54\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_55\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_56\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_57\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_58\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_59\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_60\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_61\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_62\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_63\ : STD_LOGIC;
+ signal \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_64\ : STD_LOGIC;
+ signal \^qpll1lock_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ attribute BOX_TYPE : string;
+ attribute BOX_TYPE of \gthe3_common_gen.GTHE3_COMMON_PRIM_INST\ : label is "PRIMITIVE";
+begin
+ qpll1lock_out(0) <= \^qpll1lock_out\(0);
+\gthe3_common_gen.GTHE3_COMMON_PRIM_INST\: unisim.vcomponents.GTHE3_COMMON
+ generic map(
+ BIAS_CFG0 => X"0000",
+ BIAS_CFG1 => X"0000",
+ BIAS_CFG2 => X"0000",
+ BIAS_CFG3 => X"0040",
+ BIAS_CFG4 => X"0000",
+ BIAS_CFG_RSVD => B"0000000000",
+ COMMON_CFG0 => X"0000",
+ COMMON_CFG1 => X"0000",
+ POR_CFG => X"0004",
+ QPLL0_CFG0 => X"321C",
+ QPLL0_CFG1 => X"1018",
+ QPLL0_CFG1_G3 => X"1018",
+ QPLL0_CFG2 => X"0048",
+ QPLL0_CFG2_G3 => X"0048",
+ QPLL0_CFG3 => X"0120",
+ QPLL0_CFG4 => X"0009",
+ QPLL0_CP => B"0000011111",
+ QPLL0_CP_G3 => B"1111111111",
+ QPLL0_FBDIV => 66,
+ QPLL0_FBDIV_G3 => 80,
+ QPLL0_INIT_CFG0 => X"02B2",
+ QPLL0_INIT_CFG1 => X"00",
+ QPLL0_LOCK_CFG => X"21E8",
+ QPLL0_LOCK_CFG_G3 => X"21E8",
+ QPLL0_LPF => B"1111111100",
+ QPLL0_LPF_G3 => B"0000010101",
+ QPLL0_REFCLK_DIV => 1,
+ QPLL0_SDM_CFG0 => B"0000000000000000",
+ QPLL0_SDM_CFG1 => B"0000000000000000",
+ QPLL0_SDM_CFG2 => B"0000000000000000",
+ QPLL1_CFG0 => X"321C",
+ QPLL1_CFG1 => X"1018",
+ QPLL1_CFG1_G3 => X"1018",
+ QPLL1_CFG2 => X"0040",
+ QPLL1_CFG2_G3 => X"0040",
+ QPLL1_CFG3 => X"0120",
+ QPLL1_CFG4 => X"0009",
+ QPLL1_CP => B"0111111111",
+ QPLL1_CP_G3 => B"1111111111",
+ QPLL1_FBDIV => 128,
+ QPLL1_FBDIV_G3 => 80,
+ QPLL1_INIT_CFG0 => X"02B2",
+ QPLL1_INIT_CFG1 => X"00",
+ QPLL1_LOCK_CFG => X"21E8",
+ QPLL1_LOCK_CFG_G3 => X"21E8",
+ QPLL1_LPF => B"1111111100",
+ QPLL1_LPF_G3 => B"0000010101",
+ QPLL1_REFCLK_DIV => 3,
+ QPLL1_SDM_CFG0 => B"0000000000000000",
+ QPLL1_SDM_CFG1 => B"0000000000000000",
+ QPLL1_SDM_CFG2 => B"0000000000000000",
+ RSVD_ATTR0 => X"0000",
+ RSVD_ATTR1 => X"0000",
+ RSVD_ATTR2 => X"0000",
+ RSVD_ATTR3 => X"0000",
+ RXRECCLKOUT0_SEL => B"00",
+ RXRECCLKOUT1_SEL => B"00",
+ SARC_EN => '1',
+ SARC_SEL => '0',
+ SDM0DATA1_0 => B"0000000000000000",
+ SDM0DATA1_1 => B"000000000",
+ SDM0INITSEED0_0 => B"0000000000000000",
+ SDM0INITSEED0_1 => B"000000000",
+ SDM0_DATA_PIN_SEL => '0',
+ SDM0_WIDTH_PIN_SEL => '0',
+ SDM1DATA1_0 => B"0000000000000000",
+ SDM1DATA1_1 => B"000000000",
+ SDM1INITSEED0_0 => B"0000000000000000",
+ SDM1INITSEED0_1 => B"000000000",
+ SDM1_DATA_PIN_SEL => '0',
+ SDM1_WIDTH_PIN_SEL => '0',
+ SIM_MODE => "FAST",
+ SIM_RESET_SPEEDUP => "TRUE",
+ SIM_VERSION => 2
+ )
+ port map (
+ BGBYPASSB => '1',
+ BGMONITORENB => '1',
+ BGPDB => '1',
+ BGRCALOVRD(4 downto 0) => B"11111",
+ BGRCALOVRDENB => '1',
+ DRPADDR(8 downto 0) => B"000000000",
+ DRPCLK => '0',
+ DRPDI(15 downto 0) => B"0000000000000000",
+ DRPDO(15) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_13\,
+ DRPDO(14) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_14\,
+ DRPDO(13) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_15\,
+ DRPDO(12) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_16\,
+ DRPDO(11) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_17\,
+ DRPDO(10) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_18\,
+ DRPDO(9) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_19\,
+ DRPDO(8) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_20\,
+ DRPDO(7) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_21\,
+ DRPDO(6) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_22\,
+ DRPDO(5) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_23\,
+ DRPDO(4) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_24\,
+ DRPDO(3) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_25\,
+ DRPDO(2) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_26\,
+ DRPDO(1) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_27\,
+ DRPDO(0) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_28\,
+ DRPEN => '0',
+ DRPRDY => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_0\,
+ DRPWE => '0',
+ GTGREFCLK0 => '0',
+ GTGREFCLK1 => '0',
+ GTNORTHREFCLK00 => '0',
+ GTNORTHREFCLK01 => '0',
+ GTNORTHREFCLK10 => '0',
+ GTNORTHREFCLK11 => '0',
+ GTREFCLK00 => '0',
+ GTREFCLK01 => gtrefclk01_in(0),
+ GTREFCLK10 => '0',
+ GTREFCLK11 => '0',
+ GTSOUTHREFCLK00 => '0',
+ GTSOUTHREFCLK01 => '0',
+ GTSOUTHREFCLK10 => '0',
+ GTSOUTHREFCLK11 => '0',
+ PMARSVD0(7 downto 0) => B"00000000",
+ PMARSVD1(7 downto 0) => B"00000000",
+ PMARSVDOUT0(7) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_33\,
+ PMARSVDOUT0(6) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_34\,
+ PMARSVDOUT0(5) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_35\,
+ PMARSVDOUT0(4) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_36\,
+ PMARSVDOUT0(3) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_37\,
+ PMARSVDOUT0(2) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_38\,
+ PMARSVDOUT0(1) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_39\,
+ PMARSVDOUT0(0) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_40\,
+ PMARSVDOUT1(7) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_41\,
+ PMARSVDOUT1(6) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_42\,
+ PMARSVDOUT1(5) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_43\,
+ PMARSVDOUT1(4) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_44\,
+ PMARSVDOUT1(3) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_45\,
+ PMARSVDOUT1(2) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_46\,
+ PMARSVDOUT1(1) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_47\,
+ PMARSVDOUT1(0) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_48\,
+ QPLL0CLKRSVD0 => '0',
+ QPLL0CLKRSVD1 => '0',
+ QPLL0FBCLKLOST => qpll0fbclklost_out(0),
+ QPLL0LOCK => qpll0lock_out(0),
+ QPLL0LOCKDETCLK => '0',
+ QPLL0LOCKEN => '0',
+ QPLL0OUTCLK => qpll0outclk_out(0),
+ QPLL0OUTREFCLK => qpll0outrefclk_out(0),
+ QPLL0PD => '1',
+ QPLL0REFCLKLOST => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_5\,
+ QPLL0REFCLKSEL(2 downto 0) => B"001",
+ QPLL0RESET => '1',
+ QPLL1CLKRSVD0 => '0',
+ QPLL1CLKRSVD1 => '0',
+ QPLL1FBCLKLOST => qpll1fbclklost_out(0),
+ QPLL1LOCK => \^qpll1lock_out\(0),
+ QPLL1LOCKDETCLK => '0',
+ QPLL1LOCKEN => '1',
+ QPLL1OUTCLK => qpll1outclk_out(0),
+ QPLL1OUTREFCLK => qpll1outrefclk_out(0),
+ QPLL1PD => '0',
+ QPLL1REFCLKLOST => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_10\,
+ QPLL1REFCLKSEL(2 downto 0) => B"001",
+ QPLL1RESET => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_0\,
+ QPLLDMONITOR0(7) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_49\,
+ QPLLDMONITOR0(6) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_50\,
+ QPLLDMONITOR0(5) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_51\,
+ QPLLDMONITOR0(4) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_52\,
+ QPLLDMONITOR0(3) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_53\,
+ QPLLDMONITOR0(2) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_54\,
+ QPLLDMONITOR0(1) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_55\,
+ QPLLDMONITOR0(0) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_56\,
+ QPLLDMONITOR1(7) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_57\,
+ QPLLDMONITOR1(6) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_58\,
+ QPLLDMONITOR1(5) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_59\,
+ QPLLDMONITOR1(4) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_60\,
+ QPLLDMONITOR1(3) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_61\,
+ QPLLDMONITOR1(2) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_62\,
+ QPLLDMONITOR1(1) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_63\,
+ QPLLDMONITOR1(0) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_64\,
+ QPLLRSVD1(7 downto 0) => B"00000000",
+ QPLLRSVD2(4 downto 0) => B"00000",
+ QPLLRSVD3(4 downto 0) => B"00000",
+ QPLLRSVD4(7 downto 0) => B"00000000",
+ RCALENB => '1',
+ REFCLKOUTMONITOR0 => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_11\,
+ REFCLKOUTMONITOR1 => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_12\,
+ RXRECCLK0_SEL(1) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_29\,
+ RXRECCLK0_SEL(0) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_30\,
+ RXRECCLK1_SEL(1) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_31\,
+ RXRECCLK1_SEL(0) => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_n_32\
+ );
+\rst_in_meta_i_1__3\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^qpll1lock_out\(0),
+ O => rst_in0
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer is
+ port (
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\ : out STD_LOGIC;
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[0]\ : out STD_LOGIC;
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_sync2_reg_0 : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\ : in STD_LOGIC;
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\ : in STD_LOGIC;
+ gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer : entity is "gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer is
+ signal \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\ : STD_LOGIC;
+ signal p_0_in : STD_LOGIC;
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx[1]_i_3\ : label is "soft_lutpair21";
+ attribute SOFT_HLUTNM of \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_done_out_i_1\ : label is "soft_lutpair21";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\ <= \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\;
+\FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AEFEAEAE"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => p_0_in,
+ I2 => Q(1),
+ I3 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\,
+ I4 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\,
+ O => E(0)
+ );
+\FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx[1]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"F4"
+ )
+ port map (
+ I0 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\,
+ I1 => \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\,
+ I2 => gtwiz_buffbypass_tx_start_user_in(0),
+ O => p_0_in
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_done_out_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AAAA4454"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => gtwiz_buffbypass_tx_start_user_in(0),
+ I2 => \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\,
+ I3 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\,
+ I4 => Q(1),
+ O => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[0]\
+ );
+rst_in_meta_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => rst_in_sync2_reg_0,
+ D => '1',
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => rst_in_sync2_reg_0,
+ D => rst_in_sync3,
+ Q => \^gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => rst_in_sync2_reg_0,
+ D => rst_in_meta,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => rst_in_sync2_reg_0,
+ D => rst_in_sync1,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => rst_in_sync2_reg_0,
+ D => rst_in_sync2,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_25 is
+ port (
+ gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_sync2_reg_0 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_25 : entity is "gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_25;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_25 is
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal \rst_in_out_i_1__1_n_0\ : STD_LOGIC;
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+rst_in_meta_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => rxusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__1_n_0\,
+ D => '1',
+ Q => rst_in_meta
+ );
+\rst_in_out_i_1__1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => rst_in_sync2_reg_0,
+ O => \rst_in_out_i_1__1_n_0\
+ );
+rst_in_out_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => rxusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__1_n_0\,
+ D => rst_in_sync3,
+ Q => gtwiz_reset_rx_done_out(0)
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => rxusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__1_n_0\,
+ D => rst_in_meta,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => rxusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__1_n_0\,
+ D => rst_in_sync1,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => rxusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__1_n_0\,
+ D => rst_in_sync2,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_26 is
+ port (
+ gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_out_reg_0 : out STD_LOGIC;
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_sync3_reg_0 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_26 : entity is "gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_26;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_26 is
+ signal \^gtwiz_reset_tx_done_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal \rst_in_out_i_1__0_n_0\ : STD_LOGIC;
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+ gtwiz_reset_tx_done_out(0) <= \^gtwiz_reset_tx_done_out\(0);
+\rst_in_meta_i_1__4\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => \^gtwiz_reset_tx_done_out\(0),
+ O => rst_in_out_reg_0
+ );
+rst_in_meta_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__0_n_0\,
+ D => '1',
+ Q => rst_in_meta
+ );
+\rst_in_out_i_1__0\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => rst_in_sync3_reg_0,
+ O => \rst_in_out_i_1__0_n_0\
+ );
+rst_in_out_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__0_n_0\,
+ D => rst_in_sync3,
+ Q => \^gtwiz_reset_tx_done_out\(0)
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__0_n_0\,
+ D => rst_in_meta,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__0_n_0\,
+ D => rst_in_sync1,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDCE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ CLR => \rst_in_out_i_1__0_n_0\,
+ D => rst_in_sync2,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer is
+ port (
+ gtwiz_reset_all_sync : out STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer is
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => gtwiz_reset_all_in(0),
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => gtwiz_reset_all_in(0),
+ Q => gtwiz_reset_all_sync
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => gtwiz_reset_all_in(0),
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => gtwiz_reset_all_in(0),
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => gtwiz_reset_all_in(0),
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_19 is
+ port (
+ gtwiz_reset_rx_any_sync : out STD_LOGIC;
+ \FSM_sequential_sm_reset_rx_reg[1]\ : out STD_LOGIC;
+ rst_in_out_reg_0 : out STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ GTHE3_CHANNEL_CPLLPD : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \sm_reset_rx_timer_clr0__0\ : in STD_LOGIC;
+ GTHE3_CHANNEL_RXUSERRDY : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_out_reg_1 : in STD_LOGIC;
+ gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_out_reg_2 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_19 : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_19;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_19 is
+ signal gtwiz_reset_rx_any : STD_LOGIC;
+ signal \^gtwiz_reset_rx_any_sync\ : STD_LOGIC;
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+ gtwiz_reset_rx_any_sync <= \^gtwiz_reset_rx_any_sync\;
+pllreset_rx_out_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFDF0010"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => Q(2),
+ I2 => Q(0),
+ I3 => \^gtwiz_reset_rx_any_sync\,
+ I4 => GTHE3_CHANNEL_CPLLPD(0),
+ O => \FSM_sequential_sm_reset_rx_reg[1]\
+ );
+\rst_in_meta_i_1__0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => rst_in_out_reg_1,
+ I1 => gtwiz_reset_rx_datapath_in(0),
+ I2 => gtwiz_reset_rx_pll_and_datapath_in(0),
+ I3 => rst_in_out_reg_2,
+ O => gtwiz_reset_rx_any
+ );
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => gtwiz_reset_rx_any,
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => gtwiz_reset_rx_any,
+ Q => \^gtwiz_reset_rx_any_sync\
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => gtwiz_reset_rx_any,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => gtwiz_reset_rx_any,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => gtwiz_reset_rx_any,
+ Q => rst_in_sync3
+ );
+rxuserrdy_out_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFAAF00400000"
+ )
+ port map (
+ I0 => \^gtwiz_reset_rx_any_sync\,
+ I1 => \sm_reset_rx_timer_clr0__0\,
+ I2 => Q(0),
+ I3 => Q(1),
+ I4 => Q(2),
+ I5 => GTHE3_CHANNEL_RXUSERRDY(0),
+ O => rst_in_out_reg_0
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_20 is
+ port (
+ in0 : out STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_out_reg_0 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_20 : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_20;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_20 is
+ signal rst_in0_2 : STD_LOGIC;
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+\rst_in_meta_i_1__2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => gtwiz_reset_rx_datapath_in(0),
+ I1 => rst_in_out_reg_0,
+ O => rst_in0_2
+ );
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => rst_in0_2,
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => rst_in0_2,
+ Q => in0
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => rst_in0_2,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => rst_in0_2,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => rst_in0_2,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_21 is
+ port (
+ in0 : out STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_out_reg_0 : in STD_LOGIC;
+ gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_21 : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_21;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_21 is
+ signal p_0_in_1 : STD_LOGIC;
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+\rst_in_meta_i_1__1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => rst_in_out_reg_0,
+ I1 => gtwiz_reset_rx_pll_and_datapath_in(0),
+ O => p_0_in_1
+ );
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => p_0_in_1,
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => p_0_in_1,
+ Q => in0
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => p_0_in_1,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => p_0_in_1,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => p_0_in_1,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_22 is
+ port (
+ gtwiz_reset_tx_any_sync : out STD_LOGIC;
+ \FSM_sequential_sm_reset_tx_reg[1]\ : out STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ pllreset_tx_out_reg : in STD_LOGIC;
+ gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_sync3_reg_0 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_22 : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_22;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_22 is
+ signal gtwiz_reset_tx_any : STD_LOGIC;
+ signal \^gtwiz_reset_tx_any_sync\ : STD_LOGIC;
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+ gtwiz_reset_tx_any_sync <= \^gtwiz_reset_tx_any_sync\;
+pllreset_tx_out_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFDF0010"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => Q(2),
+ I2 => Q(0),
+ I3 => \^gtwiz_reset_tx_any_sync\,
+ I4 => pllreset_tx_out_reg,
+ O => \FSM_sequential_sm_reset_tx_reg[1]\
+ );
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => gtwiz_reset_tx_any,
+ Q => rst_in_meta
+ );
+rst_in_out_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"FE"
+ )
+ port map (
+ I0 => gtwiz_reset_tx_datapath_in(0),
+ I1 => gtwiz_reset_tx_pll_and_datapath_in(0),
+ I2 => rst_in_sync3_reg_0,
+ O => gtwiz_reset_tx_any
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => gtwiz_reset_tx_any,
+ Q => \^gtwiz_reset_tx_any_sync\
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => gtwiz_reset_tx_any,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => gtwiz_reset_tx_any,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => gtwiz_reset_tx_any,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_23 is
+ port (
+ in0 : out STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_23 : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_23;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_23 is
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => gtwiz_reset_tx_datapath_in(0),
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => gtwiz_reset_tx_datapath_in(0),
+ Q => in0
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => gtwiz_reset_tx_datapath_in(0),
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => gtwiz_reset_tx_datapath_in(0),
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => gtwiz_reset_tx_datapath_in(0),
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_24 is
+ port (
+ in0 : out STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_out_reg_0 : in STD_LOGIC;
+ gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_24 : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_24;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_24 is
+ signal p_1_in_0 : STD_LOGIC;
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+rst_in_meta_i_1: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => rst_in_out_reg_0,
+ I1 => gtwiz_reset_tx_pll_and_datapath_in(0),
+ O => p_1_in_0
+ );
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => p_1_in_0,
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => p_1_in_0,
+ Q => in0
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => p_1_in_0,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => p_1_in_0,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => p_1_in_0,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_27 is
+ port (
+ GTHE3_CHANNEL_TXPROGDIVRESET : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in0 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_27 : entity is "gtwizard_ultrascale_v1_7_18_reset_synchronizer";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_27;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_27 is
+ signal rst_in_meta : STD_LOGIC;
+ attribute async_reg : string;
+ attribute async_reg of rst_in_meta : signal is "true";
+ signal rst_in_sync1 : STD_LOGIC;
+ attribute async_reg of rst_in_sync1 : signal is "true";
+ signal rst_in_sync2 : STD_LOGIC;
+ attribute async_reg of rst_in_sync2 : signal is "true";
+ signal rst_in_sync3 : STD_LOGIC;
+ attribute async_reg of rst_in_sync3 : signal is "true";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of rst_in_meta_reg : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of rst_in_meta_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync1_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync1_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync2_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync2_reg : label is "yes";
+ attribute ASYNC_REG_boolean of rst_in_sync3_reg : label is std.standard.true;
+ attribute KEEP of rst_in_sync3_reg : label is "yes";
+begin
+rst_in_meta_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => '0',
+ PRE => rst_in0,
+ Q => rst_in_meta
+ );
+rst_in_out_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync3,
+ PRE => rst_in0,
+ Q => GTHE3_CHANNEL_TXPROGDIVRESET(0)
+ );
+rst_in_sync1_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_meta,
+ PRE => rst_in0,
+ Q => rst_in_sync1
+ );
+rst_in_sync2_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync1,
+ PRE => rst_in0,
+ Q => rst_in_sync2
+ );
+rst_in_sync3_reg: unisim.vcomponents.FDPE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => rst_in_sync2,
+ PRE => rst_in0,
+ Q => rst_in_sync3
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gthe3_channel_wrapper is
+ port (
+ cplllock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxn_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxp_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtpowergood_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrlock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxratedone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXPHALIGNDONE : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txprgdivresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXSYNCDONE : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ GTHE3_CHANNEL_CPLLPD : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxn_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxp_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_GTRXRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_GTTXRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outrefclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outrefclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxcdrhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_RXPROGDIVRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxslide_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_RXUSERRDY : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXDLYSRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ GTHE3_CHANNEL_TXPROGDIVRESET : in STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXSYNCALLIN : in STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXUSERRDY : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 127 downto 0 );
+ loopback_in : in STD_LOGIC_VECTOR ( 11 downto 0 )
+ );
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gthe3_channel_wrapper;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gthe3_channel_wrapper is
+begin
+channel_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gthe3_channel
+ port map (
+ GTHE3_CHANNEL_CPLLPD(0) => GTHE3_CHANNEL_CPLLPD(0),
+ GTHE3_CHANNEL_GTRXRESET(0) => GTHE3_CHANNEL_GTRXRESET(0),
+ GTHE3_CHANNEL_GTTXRESET(0) => GTHE3_CHANNEL_GTTXRESET(0),
+ GTHE3_CHANNEL_RXPROGDIVRESET(0) => GTHE3_CHANNEL_RXPROGDIVRESET(0),
+ GTHE3_CHANNEL_RXUSERRDY(0) => GTHE3_CHANNEL_RXUSERRDY(0),
+ GTHE3_CHANNEL_TXDLYSRESET(0) => GTHE3_CHANNEL_TXDLYSRESET(0),
+ GTHE3_CHANNEL_TXPHALIGNDONE(3 downto 0) => GTHE3_CHANNEL_TXPHALIGNDONE(3 downto 0),
+ GTHE3_CHANNEL_TXPROGDIVRESET(0) => GTHE3_CHANNEL_TXPROGDIVRESET(0),
+ GTHE3_CHANNEL_TXSYNCALLIN(0) => GTHE3_CHANNEL_TXSYNCALLIN(0),
+ GTHE3_CHANNEL_TXSYNCDONE(0) => GTHE3_CHANNEL_TXSYNCDONE(0),
+ GTHE3_CHANNEL_TXUSERRDY(0) => GTHE3_CHANNEL_TXUSERRDY(0),
+ cplllock_out(3 downto 0) => cplllock_out(3 downto 0),
+ drpclk_in(3 downto 0) => drpclk_in(3 downto 0),
+ gthrxn_in(3 downto 0) => gthrxn_in(3 downto 0),
+ gthrxp_in(3 downto 0) => gthrxp_in(3 downto 0),
+ gthtxn_out(3 downto 0) => gthtxn_out(3 downto 0),
+ gthtxp_out(3 downto 0) => gthtxp_out(3 downto 0),
+ gtpowergood_out(3 downto 0) => gtpowergood_out(3 downto 0),
+ gtrefclk0_in(3 downto 0) => gtrefclk0_in(3 downto 0),
+ gtwiz_userdata_rx_out(63 downto 0) => gtwiz_userdata_rx_out(63 downto 0),
+ gtwiz_userdata_tx_in(127 downto 0) => gtwiz_userdata_tx_in(127 downto 0),
+ loopback_in(11 downto 0) => loopback_in(11 downto 0),
+ qpll0outclk_out(0) => qpll0outclk_out(0),
+ qpll0outrefclk_out(0) => qpll0outrefclk_out(0),
+ qpll1outclk_out(0) => qpll1outclk_out(0),
+ qpll1outrefclk_out(0) => qpll1outrefclk_out(0),
+ rxcdrhold_in(3 downto 0) => rxcdrhold_in(3 downto 0),
+ rxcdrlock_out(3 downto 0) => rxcdrlock_out(3 downto 0),
+ rxoutclk_out(3 downto 0) => rxoutclk_out(3 downto 0),
+ rxpmaresetdone_out(3 downto 0) => rxpmaresetdone_out(3 downto 0),
+ rxpolarity_in(3 downto 0) => rxpolarity_in(3 downto 0),
+ rxratedone_out(3 downto 0) => rxratedone_out(3 downto 0),
+ rxresetdone_out(3 downto 0) => rxresetdone_out(3 downto 0),
+ rxslide_in(3 downto 0) => rxslide_in(3 downto 0),
+ rxusrclk2_in(3 downto 0) => rxusrclk2_in(3 downto 0),
+ rxusrclk_in(3 downto 0) => rxusrclk_in(3 downto 0),
+ txoutclk_out(3 downto 0) => txoutclk_out(3 downto 0),
+ txpmaresetdone_out(3 downto 0) => txpmaresetdone_out(3 downto 0),
+ txpolarity_in(3 downto 0) => txpolarity_in(3 downto 0),
+ txprgdivresetdone_out(3 downto 0) => txprgdivresetdone_out(3 downto 0),
+ txresetdone_out(3 downto 0) => txresetdone_out(3 downto 0),
+ txusrclk2_in(3 downto 0) => txusrclk2_in(3 downto 0),
+ txusrclk_in(3 downto 0) => txusrclk_in(3 downto 0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gthe3_common_wrapper is
+ port (
+ qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in0 : out STD_LOGIC;
+ gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \gthe3_common_gen.GTHE3_COMMON_PRIM_INST\ : in STD_LOGIC
+ );
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gthe3_common_wrapper;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gthe3_common_wrapper is
+begin
+common_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gthe3_common
+ port map (
+ \gthe3_common_gen.GTHE3_COMMON_PRIM_INST_0\ => \gthe3_common_gen.GTHE3_COMMON_PRIM_INST\,
+ gtrefclk01_in(0) => gtrefclk01_in(0),
+ qpll0fbclklost_out(0) => qpll0fbclklost_out(0),
+ qpll0lock_out(0) => qpll0lock_out(0),
+ qpll0outclk_out(0) => qpll0outclk_out(0),
+ qpll0outrefclk_out(0) => qpll0outrefclk_out(0),
+ qpll1fbclklost_out(0) => qpll1fbclklost_out(0),
+ qpll1lock_out(0) => qpll1lock_out(0),
+ qpll1outclk_out(0) => qpll1outclk_out(0),
+ qpll1outrefclk_out(0) => qpll1outrefclk_out(0),
+ rst_in0 => rst_in0
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gtwiz_buffbypass_tx is
+ port (
+ gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXSYNCALLIN : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXDLYSRESET : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXSYNCDONE : in STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXPHALIGNDONE : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_sync2_reg : in STD_LOGIC;
+ gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gtwiz_buffbypass_tx : entity is "gtwizard_ultrascale_v1_7_18_gtwiz_buffbypass_tx";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gtwiz_buffbypass_tx;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gtwiz_buffbypass_tx is
+ signal \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg_n_0_[1]\ : STD_LOGIC;
+ signal \^gthe3_channel_txdlysreset\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.bit_synchronizer_master_phaligndone_inst_n_0\ : STD_LOGIC;
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\ : STD_LOGIC;
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\ : STD_LOGIC;
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\ : STD_LOGIC;
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\ : STD_LOGIC;
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_1\ : STD_LOGIC;
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_2\ : STD_LOGIC;
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.txdlysreset_out[3]_i_1_n_0\ : STD_LOGIC;
+ attribute FSM_ENCODED_STATES : string;
+ attribute FSM_ENCODED_STATES of \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[0]\ : label is "ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET:01,ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE:10,iSTATE:00,ST_BUFFBYPASS_TX_DONE:11";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[1]\ : label is "ST_BUFFBYPASS_TX_DEASSERT_TXDLYSRESET:01,ST_BUFFBYPASS_TX_WAIT_TXSYNCDONE:10,iSTATE:00,ST_BUFFBYPASS_TX_DONE:11";
+begin
+ GTHE3_CHANNEL_TXDLYSRESET(0) <= \^gthe3_channel_txdlysreset\(0);
+\FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_1\,
+ D => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx\(0),
+ Q => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx__0\(0),
+ R => gtwiz_buffbypass_tx_reset_in(0)
+ );
+\FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_1\,
+ D => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx\(1),
+ Q => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg_n_0_[1]\,
+ R => gtwiz_buffbypass_tx_reset_in(0)
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.bit_synchronizer_master_phaligndone_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_7
+ port map (
+ \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[1]\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.bit_synchronizer_master_phaligndone_inst_n_0\,
+ GTHE3_CHANNEL_TXPHALIGNDONE(0) => GTHE3_CHANNEL_TXPHALIGNDONE(0),
+ Q(0) => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg_n_0_[1]\,
+ txusrclk2_in(0) => txusrclk2_in(0)
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.bit_synchronizer_master_syncdone_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_8
+ port map (
+ D(1 downto 0) => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx\(1 downto 0),
+ GTHE3_CHANNEL_TXSYNCDONE(0) => GTHE3_CHANNEL_TXSYNCDONE(0),
+ Q(1) => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg_n_0_[1]\,
+ Q(0) => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx__0\(0),
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\,
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\,
+ txusrclk2_in(0) => txusrclk2_in(0)
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_done_out_reg\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_2\,
+ D => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg_n_0_[1]\,
+ Q => gtwiz_buffbypass_tx_done_out(0),
+ R => gtwiz_buffbypass_tx_reset_in(0)
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_error_out_reg\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_2\,
+ D => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.bit_synchronizer_master_phaligndone_inst_n_0\,
+ Q => gtwiz_buffbypass_tx_error_out(0),
+ R => gtwiz_buffbypass_tx_reset_in(0)
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg_reg\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\,
+ Q => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\,
+ R => '0'
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg_reg\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\,
+ Q => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\,
+ R => gtwiz_buffbypass_tx_reset_in(0)
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer
+ port map (
+ E(0) => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_1\,
+ \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg[0]\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst_n_2\,
+ Q(1) => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg_n_0_[1]\,
+ Q(0) => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx__0\(0),
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_int\,
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_master_syncdone_sync_reg\,
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\,
+ \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\ => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\,
+ gtwiz_buffbypass_tx_start_user_in(0) => gtwiz_buffbypass_tx_start_user_in(0),
+ rst_in_sync2_reg_0 => rst_in_sync2_reg,
+ txusrclk2_in(0) => txusrclk2_in(0)
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.txdlysreset_out[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AAAAFFFF00005510"
+ )
+ port map (
+ I0 => \FSM_sequential_gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx_reg_n_0_[1]\,
+ I1 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_reg\,
+ I2 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.gtwiz_buffbypass_tx_resetdone_sync_int\,
+ I3 => gtwiz_buffbypass_tx_start_user_in(0),
+ I4 => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.sm_buffbypass_tx__0\(0),
+ I5 => \^gthe3_channel_txdlysreset\(0),
+ O => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.txdlysreset_out[3]_i_1_n_0\
+ );
+\gen_gtwiz_buffbypass_tx_main.gen_auto_mode.txdlysreset_out_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => txusrclk2_in(0),
+ CE => '1',
+ D => \gen_gtwiz_buffbypass_tx_main.gen_auto_mode.txdlysreset_out[3]_i_1_n_0\,
+ Q => \^gthe3_channel_txdlysreset\(0),
+ R => gtwiz_buffbypass_tx_reset_in(0)
+ );
+txsyncallin_out0: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => GTHE3_CHANNEL_TXPHALIGNDONE(1),
+ I1 => GTHE3_CHANNEL_TXPHALIGNDONE(0),
+ I2 => GTHE3_CHANNEL_TXPHALIGNDONE(3),
+ I3 => GTHE3_CHANNEL_TXPHALIGNDONE(2),
+ O => GTHE3_CHANNEL_TXSYNCALLIN(0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gtwiz_reset is
+ port (
+ gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXPROGDIVRESET : out STD_LOGIC_VECTOR ( 0 to 0 );
+ i_in_out_reg : out STD_LOGIC;
+ gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ pllreset_tx_out_reg_0 : out STD_LOGIC;
+ GTHE3_CHANNEL_GTTXRESET : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_TXUSERRDY : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_CPLLPD : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_RXPROGDIVRESET : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_GTRXRESET : out STD_LOGIC_VECTOR ( 0 to 0 );
+ GTHE3_CHANNEL_RXUSERRDY : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in_out_reg : out STD_LOGIC;
+ in0 : in STD_LOGIC;
+ gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1lock_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ i_in_meta_reg : in STD_LOGIC;
+ i_in_meta_reg_0 : in STD_LOGIC;
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rst_in0 : in STD_LOGIC;
+ rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gtwiz_reset : entity is "gtwizard_ultrascale_v1_7_18_gtwiz_reset";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gtwiz_reset;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gtwiz_reset is
+ signal \FSM_sequential_sm_reset_all[2]_i_3_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_sm_reset_all[2]_i_4_n_0\ : STD_LOGIC;
+ signal \^gthe3_channel_cpllpd\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^gthe3_channel_gtrxreset\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^gthe3_channel_gttxreset\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^gthe3_channel_rxprogdivreset\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^gthe3_channel_rxuserrdy\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^gthe3_channel_txuserrdy\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal bit_synchronizer_gtpowergood_inst_n_0 : STD_LOGIC;
+ signal bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst_n_0 : STD_LOGIC;
+ signal bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0 : STD_LOGIC;
+ signal bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_0 : STD_LOGIC;
+ signal bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2 : STD_LOGIC;
+ signal bit_synchronizer_plllock_rx_inst_n_0 : STD_LOGIC;
+ signal bit_synchronizer_plllock_rx_inst_n_1 : STD_LOGIC;
+ signal bit_synchronizer_plllock_rx_inst_n_2 : STD_LOGIC;
+ signal bit_synchronizer_plllock_rx_inst_n_3 : STD_LOGIC;
+ signal bit_synchronizer_plllock_rx_inst_n_4 : STD_LOGIC;
+ signal bit_synchronizer_plllock_tx_inst_n_0 : STD_LOGIC;
+ signal bit_synchronizer_plllock_tx_inst_n_1 : STD_LOGIC;
+ signal bit_synchronizer_plllock_tx_inst_n_2 : STD_LOGIC;
+ signal bit_synchronizer_plllock_tx_inst_n_3 : STD_LOGIC;
+ signal bit_synchronizer_rxcdrlock_inst_n_1 : STD_LOGIC;
+ signal bit_synchronizer_rxcdrlock_inst_n_2 : STD_LOGIC;
+ signal bit_synchronizer_rxcdrlock_inst_n_3 : STD_LOGIC;
+ signal gtwiz_reset_all_sync : STD_LOGIC;
+ signal gtwiz_reset_rx_any_sync : STD_LOGIC;
+ signal gtwiz_reset_rx_datapath_int_i_1_n_0 : STD_LOGIC;
+ signal gtwiz_reset_rx_datapath_int_reg_n_0 : STD_LOGIC;
+ signal gtwiz_reset_rx_datapath_sync : STD_LOGIC;
+ signal gtwiz_reset_rx_done_int_reg_n_0 : STD_LOGIC;
+ signal gtwiz_reset_rx_pll_and_datapath_dly : STD_LOGIC;
+ signal gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0 : STD_LOGIC;
+ signal gtwiz_reset_rx_pll_and_datapath_int_reg_n_0 : STD_LOGIC;
+ signal gtwiz_reset_rx_pll_and_datapath_sync : STD_LOGIC;
+ signal gtwiz_reset_tx_any_sync : STD_LOGIC;
+ signal gtwiz_reset_tx_datapath_sync : STD_LOGIC;
+ signal \gtwiz_reset_tx_done_int0__0\ : STD_LOGIC;
+ signal gtwiz_reset_tx_done_int_reg_n_0 : STD_LOGIC;
+ signal gtwiz_reset_tx_pll_and_datapath_dly : STD_LOGIC;
+ signal gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0 : STD_LOGIC;
+ signal gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 : STD_LOGIC;
+ signal gtwiz_reset_tx_pll_and_datapath_sync : STD_LOGIC;
+ signal p_0_in : STD_LOGIC;
+ signal \p_0_in11_out__0\ : STD_LOGIC;
+ signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal p_1_in : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \^pllreset_tx_out_reg_0\ : STD_LOGIC;
+ signal reset_synchronizer_gtwiz_reset_rx_any_inst_n_1 : STD_LOGIC;
+ signal reset_synchronizer_gtwiz_reset_rx_any_inst_n_2 : STD_LOGIC;
+ signal reset_synchronizer_gtwiz_reset_tx_any_inst_n_1 : STD_LOGIC;
+ signal sel : STD_LOGIC;
+ signal sm_reset_all : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \sm_reset_all__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal sm_reset_all_timer_clr_i_1_n_0 : STD_LOGIC;
+ signal sm_reset_all_timer_clr_i_2_n_0 : STD_LOGIC;
+ signal sm_reset_all_timer_clr_reg_n_0 : STD_LOGIC;
+ signal sm_reset_all_timer_ctr : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \sm_reset_all_timer_ctr0_inferred__0/i__n_0\ : STD_LOGIC;
+ signal \sm_reset_all_timer_ctr[0]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_all_timer_ctr[1]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_all_timer_ctr[2]_i_1_n_0\ : STD_LOGIC;
+ signal sm_reset_all_timer_sat : STD_LOGIC;
+ signal sm_reset_all_timer_sat_i_1_n_0 : STD_LOGIC;
+ signal sm_reset_rx : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \sm_reset_rx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal sm_reset_rx_cdr_to_clr : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0\ : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_ctr_reg : STD_LOGIC_VECTOR ( 25 downto 0 );
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8\ : STD_LOGIC;
+ signal \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9\ : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat_i_1_n_0 : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat_i_2_n_0 : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat_i_3_n_0 : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat_i_4_n_0 : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat_i_5_n_0 : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat_i_6_n_0 : STD_LOGIC;
+ signal sm_reset_rx_cdr_to_sat_i_7_n_0 : STD_LOGIC;
+ signal sm_reset_rx_pll_timer_clr_i_1_n_0 : STD_LOGIC;
+ signal sm_reset_rx_pll_timer_clr_reg_n_0 : STD_LOGIC;
+ signal \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\ : STD_LOGIC;
+ signal sm_reset_rx_pll_timer_ctr_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal sm_reset_rx_pll_timer_sat : STD_LOGIC;
+ signal sm_reset_rx_pll_timer_sat_i_1_n_0 : STD_LOGIC;
+ signal \sm_reset_rx_timer_clr010_out__0\ : STD_LOGIC;
+ signal \sm_reset_rx_timer_clr0__0\ : STD_LOGIC;
+ signal sm_reset_rx_timer_clr_reg_n_0 : STD_LOGIC;
+ signal sm_reset_rx_timer_ctr : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \sm_reset_rx_timer_ctr0_inferred__0/i__n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_timer_ctr[0]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_timer_ctr[1]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_rx_timer_ctr[2]_i_1_n_0\ : STD_LOGIC;
+ signal sm_reset_rx_timer_sat : STD_LOGIC;
+ signal sm_reset_rx_timer_sat_i_1_n_0 : STD_LOGIC;
+ signal sm_reset_tx : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \sm_reset_tx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal sm_reset_tx_pll_timer_clr_i_1_n_0 : STD_LOGIC;
+ signal sm_reset_tx_pll_timer_clr_reg_n_0 : STD_LOGIC;
+ signal \sm_reset_tx_pll_timer_ctr[2]_i_1_n_0\ : STD_LOGIC;
+ signal \sm_reset_tx_pll_timer_ctr[6]_i_2_n_0\ : STD_LOGIC;
+ signal \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0\ : STD_LOGIC;
+ signal \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\ : STD_LOGIC;
+ signal sm_reset_tx_pll_timer_ctr_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal sm_reset_tx_pll_timer_sat : STD_LOGIC;
+ signal sm_reset_tx_pll_timer_sat_i_1_n_0 : STD_LOGIC;
+ signal \sm_reset_tx_timer_clr0__0\ : STD_LOGIC;
+ signal sm_reset_tx_timer_clr_reg_n_0 : STD_LOGIC;
+ signal sm_reset_tx_timer_ctr : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal sm_reset_tx_timer_sat : STD_LOGIC;
+ signal sm_reset_tx_timer_sat_i_1_n_0 : STD_LOGIC;
+ signal \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
+ signal \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[1]_i_1\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[2]_i_2\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[2]_i_3\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \FSM_sequential_sm_reset_all[2]_i_4\ : label is "soft_lutpair11";
+ attribute FSM_ENCODED_STATES : string;
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_all_reg[0]\ : label is "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_all_reg[1]\ : label is "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_all_reg[2]\ : label is "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_rx_reg[0]\ : label is "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_rx_reg[1]\ : label is "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_rx_reg[2]\ : label is "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_tx_reg[0]\ : label is "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_tx_reg[1]\ : label is "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001";
+ attribute FSM_ENCODED_STATES of \FSM_sequential_sm_reset_tx_reg[2]\ : label is "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001";
+ attribute SOFT_HLUTNM of gtwiz_reset_rx_datapath_int_i_1 : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of gtwiz_reset_tx_pll_and_datapath_int_i_1 : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \sm_reset_all_timer_ctr[1]_i_1\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \sm_reset_all_timer_ctr[2]_i_1\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \sm_reset_rx_cdr_to_ctr[0]_i_3\ : label is "soft_lutpair4";
+ attribute ADDER_THRESHOLD : integer;
+ attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[0]_i_2\ : label is 16;
+ attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[16]_i_1\ : label is 16;
+ attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[24]_i_1\ : label is 16;
+ attribute ADDER_THRESHOLD of \sm_reset_rx_cdr_to_ctr_reg[8]_i_1\ : label is 16;
+ attribute SOFT_HLUTNM of sm_reset_rx_cdr_to_sat_i_5 : label is "soft_lutpair4";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[1]_i_1\ : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[2]_i_1\ : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[3]_i_1\ : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[4]_i_1\ : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[6]_i_1\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[7]_i_1\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[8]_i_1\ : label is "soft_lutpair6";
+ attribute SOFT_HLUTNM of \sm_reset_rx_pll_timer_ctr[9]_i_2\ : label is "soft_lutpair6";
+ attribute SOFT_HLUTNM of sm_reset_rx_timer_clr_i_4 : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \sm_reset_rx_timer_ctr[1]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \sm_reset_rx_timer_ctr[2]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of sm_reset_rx_timer_sat_i_1 : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[0]_i_1\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[1]_i_1\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[2]_i_1\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[3]_i_1\ : label is "soft_lutpair7";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[4]_i_1\ : label is "soft_lutpair7";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[6]_i_2\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[8]_i_1\ : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of \sm_reset_tx_pll_timer_ctr[9]_i_2\ : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of \sm_reset_tx_timer_ctr[1]_i_1\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \sm_reset_tx_timer_ctr[2]_i_1\ : label is "soft_lutpair15";
+begin
+ GTHE3_CHANNEL_CPLLPD(0) <= \^gthe3_channel_cpllpd\(0);
+ GTHE3_CHANNEL_GTRXRESET(0) <= \^gthe3_channel_gtrxreset\(0);
+ GTHE3_CHANNEL_GTTXRESET(0) <= \^gthe3_channel_gttxreset\(0);
+ GTHE3_CHANNEL_RXPROGDIVRESET(0) <= \^gthe3_channel_rxprogdivreset\(0);
+ GTHE3_CHANNEL_RXUSERRDY(0) <= \^gthe3_channel_rxuserrdy\(0);
+ GTHE3_CHANNEL_TXUSERRDY(0) <= \^gthe3_channel_txuserrdy\(0);
+ pllreset_tx_out_reg_0 <= \^pllreset_tx_out_reg_0\;
+\FSM_sequential_sm_reset_all[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00FFF7000000FFFF"
+ )
+ port map (
+ I0 => gtwiz_reset_rx_done_int_reg_n_0,
+ I1 => sm_reset_all_timer_sat,
+ I2 => sm_reset_all_timer_clr_reg_n_0,
+ I3 => sm_reset_all(2),
+ I4 => sm_reset_all(1),
+ I5 => sm_reset_all(0),
+ O => \sm_reset_all__0\(0)
+ );
+\FSM_sequential_sm_reset_all[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => sm_reset_all(0),
+ I1 => sm_reset_all(1),
+ O => \sm_reset_all__0\(1)
+ );
+\FSM_sequential_sm_reset_all[2]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => sm_reset_all(2),
+ I1 => sm_reset_all(1),
+ O => \sm_reset_all__0\(2)
+ );
+\FSM_sequential_sm_reset_all[2]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => sm_reset_all_timer_sat,
+ I1 => gtwiz_reset_rx_done_int_reg_n_0,
+ I2 => sm_reset_all_timer_clr_reg_n_0,
+ O => \FSM_sequential_sm_reset_all[2]_i_3_n_0\
+ );
+\FSM_sequential_sm_reset_all[2]_i_4\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"40"
+ )
+ port map (
+ I0 => sm_reset_all_timer_clr_reg_n_0,
+ I1 => sm_reset_all_timer_sat,
+ I2 => gtwiz_reset_tx_done_int_reg_n_0,
+ O => \FSM_sequential_sm_reset_all[2]_i_4_n_0\
+ );
+\FSM_sequential_sm_reset_all_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtpowergood_inst_n_0,
+ D => \sm_reset_all__0\(0),
+ Q => sm_reset_all(0),
+ R => gtwiz_reset_all_sync
+ );
+\FSM_sequential_sm_reset_all_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtpowergood_inst_n_0,
+ D => \sm_reset_all__0\(1),
+ Q => sm_reset_all(1),
+ R => gtwiz_reset_all_sync
+ );
+\FSM_sequential_sm_reset_all_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtpowergood_inst_n_0,
+ D => \sm_reset_all__0\(2),
+ Q => sm_reset_all(2),
+ R => gtwiz_reset_all_sync
+ );
+\FSM_sequential_sm_reset_rx[2]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"F8B8"
+ )
+ port map (
+ I0 => sm_reset_rx(0),
+ I1 => sm_reset_rx(1),
+ I2 => sm_reset_rx(2),
+ I3 => \p_0_in11_out__0\,
+ O => \sm_reset_rx__0\(2)
+ );
+\FSM_sequential_sm_reset_rx[2]_i_6\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000800000000000"
+ )
+ port map (
+ I0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(2),
+ I1 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(3),
+ I2 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0),
+ I3 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(1),
+ I4 => sm_reset_rx_timer_clr_reg_n_0,
+ I5 => sm_reset_rx_timer_sat,
+ O => \p_0_in11_out__0\
+ );
+\FSM_sequential_sm_reset_rx_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst_n_0,
+ D => \sm_reset_rx__0\(0),
+ Q => sm_reset_rx(0),
+ R => gtwiz_reset_rx_any_sync
+ );
+\FSM_sequential_sm_reset_rx_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst_n_0,
+ D => \sm_reset_rx__0\(1),
+ Q => sm_reset_rx(1),
+ R => gtwiz_reset_rx_any_sync
+ );
+\FSM_sequential_sm_reset_rx_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst_n_0,
+ D => \sm_reset_rx__0\(2),
+ Q => sm_reset_rx(2),
+ R => gtwiz_reset_rx_any_sync
+ );
+\FSM_sequential_sm_reset_tx[2]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"2C"
+ )
+ port map (
+ I0 => sm_reset_tx(0),
+ I1 => sm_reset_tx(2),
+ I2 => sm_reset_tx(1),
+ O => \sm_reset_tx__0\(2)
+ );
+\FSM_sequential_sm_reset_tx[2]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000800000000000"
+ )
+ port map (
+ I0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(2),
+ I1 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(3),
+ I2 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0),
+ I3 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(1),
+ I4 => sm_reset_tx_timer_clr_reg_n_0,
+ I5 => sm_reset_tx_timer_sat,
+ O => \gtwiz_reset_tx_done_int0__0\
+ );
+\FSM_sequential_sm_reset_tx_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2,
+ D => \sm_reset_tx__0\(0),
+ Q => sm_reset_tx(0),
+ R => gtwiz_reset_tx_any_sync
+ );
+\FSM_sequential_sm_reset_tx_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2,
+ D => \sm_reset_tx__0\(1),
+ Q => sm_reset_tx(1),
+ R => gtwiz_reset_tx_any_sync
+ );
+\FSM_sequential_sm_reset_tx_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2,
+ D => \sm_reset_tx__0\(2),
+ Q => sm_reset_tx(2),
+ R => gtwiz_reset_tx_any_sync
+ );
+bit_synchronizer_gtpowergood_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_9
+ port map (
+ E(0) => bit_synchronizer_gtpowergood_inst_n_0,
+ \FSM_sequential_sm_reset_all_reg[0]\ => \FSM_sequential_sm_reset_all[2]_i_3_n_0\,
+ \FSM_sequential_sm_reset_all_reg[0]_0\ => \FSM_sequential_sm_reset_all[2]_i_4_n_0\,
+ Q(2 downto 0) => sm_reset_all(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ in0 => in0
+ );
+bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_10
+ port map (
+ E(0) => bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst_n_0,
+ \FSM_sequential_sm_reset_rx_reg[0]\ => bit_synchronizer_plllock_rx_inst_n_4,
+ \FSM_sequential_sm_reset_rx_reg[0]_0\ => bit_synchronizer_rxcdrlock_inst_n_2,
+ \FSM_sequential_sm_reset_rx_reg[0]_1\ => sm_reset_rx_pll_timer_clr_reg_n_0,
+ Q(2 downto 0) => sm_reset_rx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_pll_and_datapath_dly => gtwiz_reset_rx_pll_and_datapath_dly,
+ in0 => gtwiz_reset_rx_datapath_sync,
+ sm_reset_rx_pll_timer_sat => sm_reset_rx_pll_timer_sat
+ );
+bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_11
+ port map (
+ D(1 downto 0) => \sm_reset_rx__0\(1 downto 0),
+ Q(2 downto 0) => sm_reset_rx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_pll_and_datapath_dly => gtwiz_reset_rx_pll_and_datapath_dly,
+ in0 => gtwiz_reset_rx_pll_and_datapath_sync,
+ \p_0_in11_out__0\ => \p_0_in11_out__0\
+ );
+bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_12
+ port map (
+ \FSM_sequential_sm_reset_tx[2]_i_5\ => sm_reset_tx_pll_timer_clr_reg_n_0,
+ Q(0) => sm_reset_tx(0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_tx_pll_and_datapath_dly => gtwiz_reset_tx_pll_and_datapath_dly,
+ i_in_out_reg_0 => bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0,
+ in0 => gtwiz_reset_tx_datapath_sync,
+ sm_reset_tx_pll_timer_sat => sm_reset_tx_pll_timer_sat
+ );
+bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_13
+ port map (
+ D(1 downto 0) => \sm_reset_tx__0\(1 downto 0),
+ Q(2 downto 0) => sm_reset_tx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_tx_pll_and_datapath_dly => gtwiz_reset_tx_pll_and_datapath_dly,
+ in0 => gtwiz_reset_tx_pll_and_datapath_sync
+ );
+bit_synchronizer_gtwiz_reset_userclk_rx_active_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_14
+ port map (
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_userclk_rx_active_in(0) => gtwiz_userclk_rx_active_in(0),
+ rxuserrdy_out_reg => sm_reset_rx_timer_clr_reg_n_0,
+ \sm_reset_rx_timer_clr0__0\ => \sm_reset_rx_timer_clr0__0\,
+ sm_reset_rx_timer_sat => sm_reset_rx_timer_sat
+ );
+bit_synchronizer_gtwiz_reset_userclk_tx_active_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_15
+ port map (
+ E(0) => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2,
+ \FSM_sequential_sm_reset_tx_reg[0]\ => bit_synchronizer_plllock_tx_inst_n_3,
+ \FSM_sequential_sm_reset_tx_reg[1]\ => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_0,
+ GTHE3_CHANNEL_TXUSERRDY(0) => \^gthe3_channel_txuserrdy\(0),
+ Q(2 downto 0) => sm_reset_tx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_tx_any_sync => gtwiz_reset_tx_any_sync,
+ \gtwiz_reset_tx_done_int0__0\ => \gtwiz_reset_tx_done_int0__0\,
+ gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0),
+ \sm_reset_tx_timer_clr0__0\ => \sm_reset_tx_timer_clr0__0\,
+ sm_reset_tx_timer_sat => sm_reset_tx_timer_sat,
+ txuserrdy_out_reg => sm_reset_tx_timer_clr_reg_n_0
+ );
+bit_synchronizer_plllock_rx_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_16
+ port map (
+ \FSM_sequential_sm_reset_rx_reg[0]\ => bit_synchronizer_plllock_rx_inst_n_1,
+ \FSM_sequential_sm_reset_rx_reg[2]\ => bit_synchronizer_plllock_rx_inst_n_2,
+ \FSM_sequential_sm_reset_rx_reg[2]_0\ => bit_synchronizer_plllock_rx_inst_n_3,
+ GTHE3_CHANNEL_GTRXRESET(0) => \^gthe3_channel_gtrxreset\(0),
+ Q(2 downto 0) => sm_reset_rx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_any_sync => gtwiz_reset_rx_any_sync,
+ gtwiz_reset_rx_done_int_reg => gtwiz_reset_rx_done_int_reg_n_0,
+ i_in_meta_reg_0 => i_in_meta_reg,
+ i_in_out_reg_0 => bit_synchronizer_plllock_rx_inst_n_0,
+ i_in_out_reg_1 => bit_synchronizer_plllock_rx_inst_n_4,
+ \p_0_in11_out__0\ => \p_0_in11_out__0\,
+ sm_reset_rx_cdr_to_clr => sm_reset_rx_cdr_to_clr,
+ sm_reset_rx_cdr_to_clr_reg => bit_synchronizer_rxcdrlock_inst_n_3,
+ \sm_reset_rx_timer_clr010_out__0\ => \sm_reset_rx_timer_clr010_out__0\,
+ \sm_reset_rx_timer_clr0__0\ => \sm_reset_rx_timer_clr0__0\,
+ sm_reset_rx_timer_clr_reg => sm_reset_rx_timer_clr_reg_n_0,
+ sm_reset_rx_timer_sat => sm_reset_rx_timer_sat
+ );
+bit_synchronizer_plllock_tx_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_17
+ port map (
+ \FSM_sequential_sm_reset_tx_reg[0]\ => bit_synchronizer_plllock_tx_inst_n_2,
+ \FSM_sequential_sm_reset_tx_reg[0]_0\ => bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0,
+ \FSM_sequential_sm_reset_tx_reg[2]\ => bit_synchronizer_plllock_tx_inst_n_1,
+ GTHE3_CHANNEL_GTTXRESET(0) => \^gthe3_channel_gttxreset\(0),
+ Q(2 downto 0) => sm_reset_tx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_tx_any_sync => gtwiz_reset_tx_any_sync,
+ \gtwiz_reset_tx_done_int0__0\ => \gtwiz_reset_tx_done_int0__0\,
+ gtwiz_reset_tx_done_int_reg => gtwiz_reset_tx_done_int_reg_n_0,
+ i_in_out_reg_0 => bit_synchronizer_plllock_tx_inst_n_0,
+ i_in_out_reg_1 => bit_synchronizer_plllock_tx_inst_n_3,
+ qpll1lock_out(0) => qpll1lock_out(0),
+ \sm_reset_tx_timer_clr0__0\ => \sm_reset_tx_timer_clr0__0\,
+ sm_reset_tx_timer_clr_reg => sm_reset_tx_timer_clr_reg_n_0,
+ sm_reset_tx_timer_sat => sm_reset_tx_timer_sat
+ );
+bit_synchronizer_rxcdrlock_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_18
+ port map (
+ \FSM_sequential_sm_reset_rx_reg[2]\ => bit_synchronizer_rxcdrlock_inst_n_1,
+ \FSM_sequential_sm_reset_rx_reg[2]_0\ => bit_synchronizer_rxcdrlock_inst_n_3,
+ GTHE3_CHANNEL_RXPROGDIVRESET(0) => \^gthe3_channel_rxprogdivreset\(0),
+ Q(2 downto 0) => sm_reset_rx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_any_sync => gtwiz_reset_rx_any_sync,
+ i_in_meta_reg_0 => i_in_meta_reg_0,
+ i_in_out_reg_0 => i_in_out_reg,
+ i_in_out_reg_1 => bit_synchronizer_rxcdrlock_inst_n_2,
+ \p_0_in11_out__0\ => \p_0_in11_out__0\,
+ sm_reset_rx_cdr_to_sat => sm_reset_rx_cdr_to_sat,
+ \sm_reset_rx_timer_clr0__0\ => \sm_reset_rx_timer_clr0__0\
+ );
+gtrxreset_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_plllock_rx_inst_n_3,
+ Q => \^gthe3_channel_gtrxreset\(0),
+ R => '0'
+ );
+gttxreset_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_plllock_tx_inst_n_2,
+ Q => \^gthe3_channel_gttxreset\(0),
+ R => '0'
+ );
+gtwiz_reset_rx_datapath_int_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"F740"
+ )
+ port map (
+ I0 => sm_reset_all(2),
+ I1 => sm_reset_all(0),
+ I2 => sm_reset_all(1),
+ I3 => gtwiz_reset_rx_datapath_int_reg_n_0,
+ O => gtwiz_reset_rx_datapath_int_i_1_n_0
+ );
+gtwiz_reset_rx_datapath_int_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => gtwiz_reset_rx_datapath_int_i_1_n_0,
+ Q => gtwiz_reset_rx_datapath_int_reg_n_0,
+ R => gtwiz_reset_all_sync
+ );
+gtwiz_reset_rx_done_int_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_plllock_rx_inst_n_0,
+ Q => gtwiz_reset_rx_done_int_reg_n_0,
+ R => gtwiz_reset_rx_any_sync
+ );
+gtwiz_reset_rx_pll_and_datapath_int_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"F704"
+ )
+ port map (
+ I0 => sm_reset_all(0),
+ I1 => sm_reset_all(2),
+ I2 => sm_reset_all(1),
+ I3 => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0,
+ O => gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0
+ );
+gtwiz_reset_rx_pll_and_datapath_int_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0,
+ Q => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0,
+ R => gtwiz_reset_all_sync
+ );
+gtwiz_reset_tx_done_int_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_plllock_tx_inst_n_0,
+ Q => gtwiz_reset_tx_done_int_reg_n_0,
+ R => gtwiz_reset_tx_any_sync
+ );
+gtwiz_reset_tx_pll_and_datapath_int_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FB02"
+ )
+ port map (
+ I0 => sm_reset_all(0),
+ I1 => sm_reset_all(1),
+ I2 => sm_reset_all(2),
+ I3 => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0,
+ O => gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0
+ );
+gtwiz_reset_tx_pll_and_datapath_int_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0,
+ Q => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0,
+ R => gtwiz_reset_all_sync
+ );
+pllreset_rx_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => reset_synchronizer_gtwiz_reset_rx_any_inst_n_1,
+ Q => \^gthe3_channel_cpllpd\(0),
+ R => '0'
+ );
+pllreset_tx_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => reset_synchronizer_gtwiz_reset_tx_any_inst_n_1,
+ Q => \^pllreset_tx_out_reg_0\,
+ R => '0'
+ );
+reset_synchronizer_gtwiz_reset_all_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer
+ port map (
+ gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0),
+ gtwiz_reset_all_sync => gtwiz_reset_all_sync,
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0)
+ );
+reset_synchronizer_gtwiz_reset_rx_any_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_19
+ port map (
+ \FSM_sequential_sm_reset_rx_reg[1]\ => reset_synchronizer_gtwiz_reset_rx_any_inst_n_1,
+ GTHE3_CHANNEL_CPLLPD(0) => \^gthe3_channel_cpllpd\(0),
+ GTHE3_CHANNEL_RXUSERRDY(0) => \^gthe3_channel_rxuserrdy\(0),
+ Q(2 downto 0) => sm_reset_rx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_any_sync => gtwiz_reset_rx_any_sync,
+ gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0),
+ gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0),
+ rst_in_out_reg_0 => reset_synchronizer_gtwiz_reset_rx_any_inst_n_2,
+ rst_in_out_reg_1 => gtwiz_reset_rx_datapath_int_reg_n_0,
+ rst_in_out_reg_2 => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0,
+ \sm_reset_rx_timer_clr0__0\ => \sm_reset_rx_timer_clr0__0\
+ );
+reset_synchronizer_gtwiz_reset_rx_datapath_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_20
+ port map (
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0),
+ in0 => gtwiz_reset_rx_datapath_sync,
+ rst_in_out_reg_0 => gtwiz_reset_rx_datapath_int_reg_n_0
+ );
+reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_21
+ port map (
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0),
+ in0 => gtwiz_reset_rx_pll_and_datapath_sync,
+ rst_in_out_reg_0 => gtwiz_reset_rx_pll_and_datapath_int_reg_n_0
+ );
+reset_synchronizer_gtwiz_reset_tx_any_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_22
+ port map (
+ \FSM_sequential_sm_reset_tx_reg[1]\ => reset_synchronizer_gtwiz_reset_tx_any_inst_n_1,
+ Q(2 downto 0) => sm_reset_tx(2 downto 0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_tx_any_sync => gtwiz_reset_tx_any_sync,
+ gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0),
+ gtwiz_reset_tx_pll_and_datapath_in(0) => gtwiz_reset_tx_pll_and_datapath_in(0),
+ pllreset_tx_out_reg => \^pllreset_tx_out_reg_0\,
+ rst_in_sync3_reg_0 => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0
+ );
+reset_synchronizer_gtwiz_reset_tx_datapath_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_23
+ port map (
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0),
+ in0 => gtwiz_reset_tx_datapath_sync
+ );
+reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_24
+ port map (
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_tx_pll_and_datapath_in(0) => gtwiz_reset_tx_pll_and_datapath_in(0),
+ in0 => gtwiz_reset_tx_pll_and_datapath_sync,
+ rst_in_out_reg_0 => gtwiz_reset_tx_pll_and_datapath_int_reg_n_0
+ );
+reset_synchronizer_rx_done_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_25
+ port map (
+ gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0),
+ rst_in_sync2_reg_0 => gtwiz_reset_rx_done_int_reg_n_0,
+ rxusrclk2_in(0) => rxusrclk2_in(0)
+ );
+reset_synchronizer_tx_done_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_inv_synchronizer_26
+ port map (
+ gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0),
+ rst_in_out_reg_0 => rst_in_out_reg,
+ rst_in_sync3_reg_0 => gtwiz_reset_tx_done_int_reg_n_0,
+ txusrclk2_in(0) => txusrclk2_in(0)
+ );
+reset_synchronizer_txprogdivreset_inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_reset_synchronizer_27
+ port map (
+ GTHE3_CHANNEL_TXPROGDIVRESET(0) => GTHE3_CHANNEL_TXPROGDIVRESET(0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ rst_in0 => rst_in0
+ );
+rxprogdivreset_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_rxcdrlock_inst_n_1,
+ Q => \^gthe3_channel_rxprogdivreset\(0),
+ R => '0'
+ );
+rxuserrdy_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => reset_synchronizer_gtwiz_reset_rx_any_inst_n_2,
+ Q => \^gthe3_channel_rxuserrdy\(0),
+ R => '0'
+ );
+sm_reset_all_timer_clr_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"EFFA200A"
+ )
+ port map (
+ I0 => sm_reset_all_timer_clr_i_2_n_0,
+ I1 => sm_reset_all(1),
+ I2 => sm_reset_all(2),
+ I3 => sm_reset_all(0),
+ I4 => sm_reset_all_timer_clr_reg_n_0,
+ O => sm_reset_all_timer_clr_i_1_n_0
+ );
+sm_reset_all_timer_clr_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000B0003333BB33"
+ )
+ port map (
+ I0 => gtwiz_reset_rx_done_int_reg_n_0,
+ I1 => sm_reset_all(2),
+ I2 => gtwiz_reset_tx_done_int_reg_n_0,
+ I3 => sm_reset_all_timer_sat,
+ I4 => sm_reset_all_timer_clr_reg_n_0,
+ I5 => sm_reset_all(1),
+ O => sm_reset_all_timer_clr_i_2_n_0
+ );
+sm_reset_all_timer_clr_reg: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_all_timer_clr_i_1_n_0,
+ Q => sm_reset_all_timer_clr_reg_n_0,
+ S => gtwiz_reset_all_sync
+ );
+\sm_reset_all_timer_ctr0_inferred__0/i_\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"7F"
+ )
+ port map (
+ I0 => sm_reset_all_timer_ctr(2),
+ I1 => sm_reset_all_timer_ctr(0),
+ I2 => sm_reset_all_timer_ctr(1),
+ O => \sm_reset_all_timer_ctr0_inferred__0/i__n_0\
+ );
+\sm_reset_all_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => sm_reset_all_timer_ctr(0),
+ O => \sm_reset_all_timer_ctr[0]_i_1_n_0\
+ );
+\sm_reset_all_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => sm_reset_all_timer_ctr(0),
+ I1 => sm_reset_all_timer_ctr(1),
+ O => \sm_reset_all_timer_ctr[1]_i_1_n_0\
+ );
+\sm_reset_all_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => sm_reset_all_timer_ctr(0),
+ I1 => sm_reset_all_timer_ctr(1),
+ I2 => sm_reset_all_timer_ctr(2),
+ O => \sm_reset_all_timer_ctr[2]_i_1_n_0\
+ );
+\sm_reset_all_timer_ctr_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_all_timer_ctr0_inferred__0/i__n_0\,
+ D => \sm_reset_all_timer_ctr[0]_i_1_n_0\,
+ Q => sm_reset_all_timer_ctr(0),
+ R => sm_reset_all_timer_clr_reg_n_0
+ );
+\sm_reset_all_timer_ctr_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_all_timer_ctr0_inferred__0/i__n_0\,
+ D => \sm_reset_all_timer_ctr[1]_i_1_n_0\,
+ Q => sm_reset_all_timer_ctr(1),
+ R => sm_reset_all_timer_clr_reg_n_0
+ );
+\sm_reset_all_timer_ctr_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_all_timer_ctr0_inferred__0/i__n_0\,
+ D => \sm_reset_all_timer_ctr[2]_i_1_n_0\,
+ Q => sm_reset_all_timer_ctr(2),
+ R => sm_reset_all_timer_clr_reg_n_0
+ );
+sm_reset_all_timer_sat_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0000FF80"
+ )
+ port map (
+ I0 => sm_reset_all_timer_ctr(2),
+ I1 => sm_reset_all_timer_ctr(0),
+ I2 => sm_reset_all_timer_ctr(1),
+ I3 => sm_reset_all_timer_sat,
+ I4 => sm_reset_all_timer_clr_reg_n_0,
+ O => sm_reset_all_timer_sat_i_1_n_0
+ );
+sm_reset_all_timer_sat_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_all_timer_sat_i_1_n_0,
+ Q => sm_reset_all_timer_sat,
+ R => '0'
+ );
+sm_reset_rx_cdr_to_clr_reg: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_plllock_rx_inst_n_2,
+ Q => sm_reset_rx_cdr_to_clr,
+ S => gtwiz_reset_rx_any_sync
+ );
+\sm_reset_rx_cdr_to_ctr[0]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFFFFEF"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_ctr_reg(24),
+ I1 => sm_reset_rx_cdr_to_ctr_reg(21),
+ I2 => \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0\,
+ I3 => \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\,
+ I4 => sm_reset_rx_cdr_to_sat_i_3_n_0,
+ O => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\
+ );
+\sm_reset_rx_cdr_to_ctr[0]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"02000000"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_sat_i_4_n_0,
+ I1 => sm_reset_rx_cdr_to_ctr_reg(2),
+ I2 => sm_reset_rx_cdr_to_ctr_reg(1),
+ I3 => sm_reset_rx_cdr_to_ctr_reg(0),
+ I4 => sm_reset_rx_cdr_to_sat_i_6_n_0,
+ O => \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0\
+ );
+\sm_reset_rx_cdr_to_ctr[0]_i_4\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_ctr_reg(15),
+ I1 => sm_reset_rx_cdr_to_ctr_reg(14),
+ I2 => sm_reset_rx_cdr_to_ctr_reg(9),
+ I3 => sm_reset_rx_cdr_to_ctr_reg(5),
+ O => \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\
+ );
+\sm_reset_rx_cdr_to_ctr[0]_i_5\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_ctr_reg(0),
+ O => \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0\
+ );
+\sm_reset_rx_cdr_to_ctr_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(0),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[0]_i_2\: unisim.vcomponents.CARRY8
+ port map (
+ CI => '0',
+ CI_TOP => '0',
+ CO(7) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0\,
+ CO(6) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1\,
+ CO(5) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2\,
+ CO(4) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3\,
+ CO(3) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4\,
+ CO(2) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5\,
+ CO(1) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6\,
+ CO(0) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7\,
+ DI(7 downto 0) => B"00000001",
+ O(7) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8\,
+ O(6) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9\,
+ O(5) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10\,
+ O(4) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11\,
+ O(3) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12\,
+ O(2) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13\,
+ O(1) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14\,
+ O(0) => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15\,
+ S(7 downto 1) => sm_reset_rx_cdr_to_ctr_reg(7 downto 1),
+ S(0) => \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0\
+ );
+\sm_reset_rx_cdr_to_ctr_reg[10]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(10),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[11]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(11),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[12]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(12),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[13]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(13),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[14]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(14),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[15]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(15),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[16]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(16),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[16]_i_1\: unisim.vcomponents.CARRY8
+ port map (
+ CI => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0\,
+ CI_TOP => '0',
+ CO(7) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0\,
+ CO(6) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1\,
+ CO(5) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2\,
+ CO(4) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3\,
+ CO(3) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4\,
+ CO(2) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5\,
+ CO(1) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6\,
+ CO(0) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7\,
+ DI(7 downto 0) => B"00000000",
+ O(7) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8\,
+ O(6) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9\,
+ O(5) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10\,
+ O(4) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11\,
+ O(3) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12\,
+ O(2) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13\,
+ O(1) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14\,
+ O(0) => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15\,
+ S(7 downto 0) => sm_reset_rx_cdr_to_ctr_reg(23 downto 16)
+ );
+\sm_reset_rx_cdr_to_ctr_reg[17]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(17),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[18]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(18),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[19]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(19),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(1),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[20]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(20),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[21]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(21),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[22]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(22),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[23]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(23),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[24]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(24),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[24]_i_1\: unisim.vcomponents.CARRY8
+ port map (
+ CI => \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0\,
+ CI_TOP => '0',
+ CO(7 downto 1) => \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED\(7 downto 1),
+ CO(0) => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7\,
+ DI(7 downto 0) => B"00000000",
+ O(7 downto 2) => \NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED\(7 downto 2),
+ O(1) => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14\,
+ O(0) => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15\,
+ S(7 downto 2) => B"000000",
+ S(1 downto 0) => sm_reset_rx_cdr_to_ctr_reg(25 downto 24)
+ );
+\sm_reset_rx_cdr_to_ctr_reg[25]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(25),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(2),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(3),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(4),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(5),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[6]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(6),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[7]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(7),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[8]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(8),
+ R => sm_reset_rx_cdr_to_clr
+ );
+\sm_reset_rx_cdr_to_ctr_reg[8]_i_1\: unisim.vcomponents.CARRY8
+ port map (
+ CI => \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0\,
+ CI_TOP => '0',
+ CO(7) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0\,
+ CO(6) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1\,
+ CO(5) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2\,
+ CO(4) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3\,
+ CO(3) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4\,
+ CO(2) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5\,
+ CO(1) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6\,
+ CO(0) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7\,
+ DI(7 downto 0) => B"00000000",
+ O(7) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8\,
+ O(6) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9\,
+ O(5) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10\,
+ O(4) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11\,
+ O(3) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12\,
+ O(2) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13\,
+ O(1) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14\,
+ O(0) => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15\,
+ S(7 downto 0) => sm_reset_rx_cdr_to_ctr_reg(15 downto 8)
+ );
+\sm_reset_rx_cdr_to_ctr_reg[9]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0\,
+ D => \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14\,
+ Q => sm_reset_rx_cdr_to_ctr_reg(9),
+ R => sm_reset_rx_cdr_to_clr
+ );
+sm_reset_rx_cdr_to_sat_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00F1"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_sat_i_2_n_0,
+ I1 => sm_reset_rx_cdr_to_sat_i_3_n_0,
+ I2 => sm_reset_rx_cdr_to_sat,
+ I3 => sm_reset_rx_cdr_to_clr,
+ O => sm_reset_rx_cdr_to_sat_i_1_n_0
+ );
+sm_reset_rx_cdr_to_sat_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFBFFF"
+ )
+ port map (
+ I0 => \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0\,
+ I1 => sm_reset_rx_cdr_to_sat_i_4_n_0,
+ I2 => sm_reset_rx_cdr_to_sat_i_5_n_0,
+ I3 => sm_reset_rx_cdr_to_sat_i_6_n_0,
+ I4 => sm_reset_rx_cdr_to_ctr_reg(21),
+ I5 => sm_reset_rx_cdr_to_ctr_reg(24),
+ O => sm_reset_rx_cdr_to_sat_i_2_n_0
+ );
+sm_reset_rx_cdr_to_sat_i_3: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_sat_i_7_n_0,
+ I1 => sm_reset_rx_cdr_to_ctr_reg(16),
+ I2 => sm_reset_rx_cdr_to_ctr_reg(23),
+ I3 => sm_reset_rx_cdr_to_ctr_reg(25),
+ O => sm_reset_rx_cdr_to_sat_i_3_n_0
+ );
+sm_reset_rx_cdr_to_sat_i_4: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0008"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_ctr_reg(7),
+ I1 => sm_reset_rx_cdr_to_ctr_reg(6),
+ I2 => sm_reset_rx_cdr_to_ctr_reg(4),
+ I3 => sm_reset_rx_cdr_to_ctr_reg(3),
+ O => sm_reset_rx_cdr_to_sat_i_4_n_0
+ );
+sm_reset_rx_cdr_to_sat_i_5: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"10"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_ctr_reg(2),
+ I1 => sm_reset_rx_cdr_to_ctr_reg(1),
+ I2 => sm_reset_rx_cdr_to_ctr_reg(0),
+ O => sm_reset_rx_cdr_to_sat_i_5_n_0
+ );
+sm_reset_rx_cdr_to_sat_i_6: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8000000000000000"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_ctr_reg(8),
+ I1 => sm_reset_rx_cdr_to_ctr_reg(10),
+ I2 => sm_reset_rx_cdr_to_ctr_reg(11),
+ I3 => sm_reset_rx_cdr_to_ctr_reg(17),
+ I4 => sm_reset_rx_cdr_to_ctr_reg(20),
+ I5 => sm_reset_rx_cdr_to_ctr_reg(18),
+ O => sm_reset_rx_cdr_to_sat_i_6_n_0
+ );
+sm_reset_rx_cdr_to_sat_i_7: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => sm_reset_rx_cdr_to_ctr_reg(13),
+ I1 => sm_reset_rx_cdr_to_ctr_reg(12),
+ I2 => sm_reset_rx_cdr_to_ctr_reg(19),
+ I3 => sm_reset_rx_cdr_to_ctr_reg(22),
+ O => sm_reset_rx_cdr_to_sat_i_7_n_0
+ );
+sm_reset_rx_cdr_to_sat_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_rx_cdr_to_sat_i_1_n_0,
+ Q => sm_reset_rx_cdr_to_sat,
+ R => '0'
+ );
+sm_reset_rx_pll_timer_clr_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFF3000B"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_sat,
+ I1 => sm_reset_rx(0),
+ I2 => sm_reset_rx(1),
+ I3 => sm_reset_rx(2),
+ I4 => sm_reset_rx_pll_timer_clr_reg_n_0,
+ O => sm_reset_rx_pll_timer_clr_i_1_n_0
+ );
+sm_reset_rx_pll_timer_clr_reg: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_rx_pll_timer_clr_i_1_n_0,
+ Q => sm_reset_rx_pll_timer_clr_reg_n_0,
+ S => gtwiz_reset_rx_any_sync
+ );
+\sm_reset_rx_pll_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(0),
+ O => \p_0_in__1\(0)
+ );
+\sm_reset_rx_pll_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(0),
+ I1 => sm_reset_rx_pll_timer_ctr_reg(1),
+ O => \p_0_in__1\(1)
+ );
+\sm_reset_rx_pll_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(0),
+ I1 => sm_reset_rx_pll_timer_ctr_reg(1),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(2),
+ O => \p_0_in__1\(2)
+ );
+\sm_reset_rx_pll_timer_ctr[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"7F80"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(1),
+ I1 => sm_reset_rx_pll_timer_ctr_reg(0),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(2),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(3),
+ O => \p_0_in__1\(3)
+ );
+\sm_reset_rx_pll_timer_ctr[4]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"7FFF8000"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(2),
+ I1 => sm_reset_rx_pll_timer_ctr_reg(0),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(1),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(3),
+ I4 => sm_reset_rx_pll_timer_ctr_reg(4),
+ O => \p_0_in__1\(4)
+ );
+\sm_reset_rx_pll_timer_ctr[5]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"7FFFFFFF80000000"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(3),
+ I1 => sm_reset_rx_pll_timer_ctr_reg(1),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(0),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(2),
+ I4 => sm_reset_rx_pll_timer_ctr_reg(4),
+ I5 => sm_reset_rx_pll_timer_ctr_reg(5),
+ O => \p_0_in__1\(5)
+ );
+\sm_reset_rx_pll_timer_ctr[6]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\,
+ I1 => sm_reset_rx_pll_timer_ctr_reg(6),
+ O => \p_0_in__1\(6)
+ );
+\sm_reset_rx_pll_timer_ctr[7]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\,
+ I1 => sm_reset_rx_pll_timer_ctr_reg(6),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(7),
+ O => \p_0_in__1\(7)
+ );
+\sm_reset_rx_pll_timer_ctr[8]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"7F80"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(6),
+ I1 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\,
+ I2 => sm_reset_rx_pll_timer_ctr_reg(7),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(8),
+ O => \p_0_in__1\(8)
+ );
+\sm_reset_rx_pll_timer_ctr[9]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFFFFEF"
+ )
+ port map (
+ I0 => \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0\,
+ I1 => sm_reset_rx_pll_timer_ctr_reg(9),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(7),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(3),
+ I4 => sm_reset_rx_pll_timer_ctr_reg(6),
+ O => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\
+ );
+\sm_reset_rx_pll_timer_ctr[9]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"7FFF8000"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(7),
+ I1 => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\,
+ I2 => sm_reset_rx_pll_timer_ctr_reg(6),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(8),
+ I4 => sm_reset_rx_pll_timer_ctr_reg(9),
+ O => \p_0_in__1\(9)
+ );
+\sm_reset_rx_pll_timer_ctr[9]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFBFFF"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(0),
+ I1 => sm_reset_rx_pll_timer_ctr_reg(8),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(1),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(4),
+ I4 => sm_reset_rx_pll_timer_ctr_reg(2),
+ I5 => sm_reset_rx_pll_timer_ctr_reg(5),
+ O => \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0\
+ );
+\sm_reset_rx_pll_timer_ctr[9]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8000000000000000"
+ )
+ port map (
+ I0 => sm_reset_rx_pll_timer_ctr_reg(5),
+ I1 => sm_reset_rx_pll_timer_ctr_reg(3),
+ I2 => sm_reset_rx_pll_timer_ctr_reg(1),
+ I3 => sm_reset_rx_pll_timer_ctr_reg(0),
+ I4 => sm_reset_rx_pll_timer_ctr_reg(2),
+ I5 => sm_reset_rx_pll_timer_ctr_reg(4),
+ O => \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0\
+ );
+\sm_reset_rx_pll_timer_ctr_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(0),
+ Q => sm_reset_rx_pll_timer_ctr_reg(0),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(1),
+ Q => sm_reset_rx_pll_timer_ctr_reg(1),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(2),
+ Q => sm_reset_rx_pll_timer_ctr_reg(2),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(3),
+ Q => sm_reset_rx_pll_timer_ctr_reg(3),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(4),
+ Q => sm_reset_rx_pll_timer_ctr_reg(4),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(5),
+ Q => sm_reset_rx_pll_timer_ctr_reg(5),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[6]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(6),
+ Q => sm_reset_rx_pll_timer_ctr_reg(6),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[7]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(7),
+ Q => sm_reset_rx_pll_timer_ctr_reg(7),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[8]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(8),
+ Q => sm_reset_rx_pll_timer_ctr_reg(8),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_rx_pll_timer_ctr_reg[9]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ D => \p_0_in__1\(9),
+ Q => sm_reset_rx_pll_timer_ctr_reg(9),
+ R => sm_reset_rx_pll_timer_clr_reg_n_0
+ );
+sm_reset_rx_pll_timer_sat_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"0D"
+ )
+ port map (
+ I0 => \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0\,
+ I1 => sm_reset_rx_pll_timer_sat,
+ I2 => sm_reset_rx_pll_timer_clr_reg_n_0,
+ O => sm_reset_rx_pll_timer_sat_i_1_n_0
+ );
+sm_reset_rx_pll_timer_sat_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_rx_pll_timer_sat_i_1_n_0,
+ Q => sm_reset_rx_pll_timer_sat,
+ R => '0'
+ );
+sm_reset_rx_timer_clr_i_4: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => sm_reset_rx_timer_sat,
+ I1 => sm_reset_rx_timer_clr_reg_n_0,
+ O => \sm_reset_rx_timer_clr010_out__0\
+ );
+sm_reset_rx_timer_clr_reg: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_plllock_rx_inst_n_1,
+ Q => sm_reset_rx_timer_clr_reg_n_0,
+ S => gtwiz_reset_rx_any_sync
+ );
+\sm_reset_rx_timer_ctr0_inferred__0/i_\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"7F"
+ )
+ port map (
+ I0 => sm_reset_rx_timer_ctr(2),
+ I1 => sm_reset_rx_timer_ctr(0),
+ I2 => sm_reset_rx_timer_ctr(1),
+ O => \sm_reset_rx_timer_ctr0_inferred__0/i__n_0\
+ );
+\sm_reset_rx_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => sm_reset_rx_timer_ctr(0),
+ O => \sm_reset_rx_timer_ctr[0]_i_1_n_0\
+ );
+\sm_reset_rx_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => sm_reset_rx_timer_ctr(0),
+ I1 => sm_reset_rx_timer_ctr(1),
+ O => \sm_reset_rx_timer_ctr[1]_i_1_n_0\
+ );
+\sm_reset_rx_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => sm_reset_rx_timer_ctr(0),
+ I1 => sm_reset_rx_timer_ctr(1),
+ I2 => sm_reset_rx_timer_ctr(2),
+ O => \sm_reset_rx_timer_ctr[2]_i_1_n_0\
+ );
+\sm_reset_rx_timer_ctr_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_timer_ctr0_inferred__0/i__n_0\,
+ D => \sm_reset_rx_timer_ctr[0]_i_1_n_0\,
+ Q => sm_reset_rx_timer_ctr(0),
+ R => sm_reset_rx_timer_clr_reg_n_0
+ );
+\sm_reset_rx_timer_ctr_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_timer_ctr0_inferred__0/i__n_0\,
+ D => \sm_reset_rx_timer_ctr[1]_i_1_n_0\,
+ Q => sm_reset_rx_timer_ctr(1),
+ R => sm_reset_rx_timer_clr_reg_n_0
+ );
+\sm_reset_rx_timer_ctr_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => \sm_reset_rx_timer_ctr0_inferred__0/i__n_0\,
+ D => \sm_reset_rx_timer_ctr[2]_i_1_n_0\,
+ Q => sm_reset_rx_timer_ctr(2),
+ R => sm_reset_rx_timer_clr_reg_n_0
+ );
+sm_reset_rx_timer_sat_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0000FF80"
+ )
+ port map (
+ I0 => sm_reset_rx_timer_ctr(2),
+ I1 => sm_reset_rx_timer_ctr(0),
+ I2 => sm_reset_rx_timer_ctr(1),
+ I3 => sm_reset_rx_timer_sat,
+ I4 => sm_reset_rx_timer_clr_reg_n_0,
+ O => sm_reset_rx_timer_sat_i_1_n_0
+ );
+sm_reset_rx_timer_sat_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_rx_timer_sat_i_1_n_0,
+ Q => sm_reset_rx_timer_sat,
+ R => '0'
+ );
+sm_reset_tx_pll_timer_clr_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFF3000B"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_sat,
+ I1 => sm_reset_tx(0),
+ I2 => sm_reset_tx(1),
+ I3 => sm_reset_tx(2),
+ I4 => sm_reset_tx_pll_timer_clr_reg_n_0,
+ O => sm_reset_tx_pll_timer_clr_i_1_n_0
+ );
+sm_reset_tx_pll_timer_clr_reg: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_tx_pll_timer_clr_i_1_n_0,
+ Q => sm_reset_tx_pll_timer_clr_reg_n_0,
+ S => gtwiz_reset_tx_any_sync
+ );
+\sm_reset_tx_pll_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(0),
+ O => \p_0_in__0\(0)
+ );
+\sm_reset_tx_pll_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(1),
+ O => \p_0_in__0\(1)
+ );
+\sm_reset_tx_pll_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(1),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(2),
+ O => \sm_reset_tx_pll_timer_ctr[2]_i_1_n_0\
+ );
+\sm_reset_tx_pll_timer_ctr[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"7F80"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(1),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(2),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(3),
+ O => \p_0_in__0\(3)
+ );
+\sm_reset_tx_pll_timer_ctr[4]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"7FFF8000"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(2),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(1),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(3),
+ I4 => sm_reset_tx_pll_timer_ctr_reg(4),
+ O => \p_0_in__0\(4)
+ );
+\sm_reset_tx_pll_timer_ctr[5]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"7FFFFFFF80000000"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(3),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(1),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(2),
+ I4 => sm_reset_tx_pll_timer_ctr_reg(4),
+ I5 => sm_reset_tx_pll_timer_ctr_reg(5),
+ O => \p_0_in__0\(5)
+ );
+\sm_reset_tx_pll_timer_ctr[6]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"F7FFFFFF08000000"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(4),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(2),
+ I2 => \sm_reset_tx_pll_timer_ctr[6]_i_2_n_0\,
+ I3 => sm_reset_tx_pll_timer_ctr_reg(3),
+ I4 => sm_reset_tx_pll_timer_ctr_reg(5),
+ I5 => sm_reset_tx_pll_timer_ctr_reg(6),
+ O => \p_0_in__0\(6)
+ );
+\sm_reset_tx_pll_timer_ctr[6]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"7"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(1),
+ O => \sm_reset_tx_pll_timer_ctr[6]_i_2_n_0\
+ );
+\sm_reset_tx_pll_timer_ctr[7]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\,
+ I1 => sm_reset_tx_pll_timer_ctr_reg(6),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(7),
+ O => \p_0_in__0\(7)
+ );
+\sm_reset_tx_pll_timer_ctr[8]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"7F80"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(6),
+ I1 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\,
+ I2 => sm_reset_tx_pll_timer_ctr_reg(7),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(8),
+ O => \p_0_in__0\(8)
+ );
+\sm_reset_tx_pll_timer_ctr[9]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFFFFEF"
+ )
+ port map (
+ I0 => \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0\,
+ I1 => sm_reset_tx_pll_timer_ctr_reg(8),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(2),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(6),
+ I4 => sm_reset_tx_pll_timer_ctr_reg(9),
+ O => sel
+ );
+\sm_reset_tx_pll_timer_ctr[9]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"7FFF8000"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(7),
+ I1 => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\,
+ I2 => sm_reset_tx_pll_timer_ctr_reg(6),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(8),
+ I4 => sm_reset_tx_pll_timer_ctr_reg(9),
+ O => \p_0_in__0\(9)
+ );
+\sm_reset_tx_pll_timer_ctr[9]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFEFFF"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(3),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(4),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(1),
+ I4 => sm_reset_tx_pll_timer_ctr_reg(5),
+ I5 => sm_reset_tx_pll_timer_ctr_reg(7),
+ O => \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0\
+ );
+\sm_reset_tx_pll_timer_ctr[9]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8000000000000000"
+ )
+ port map (
+ I0 => sm_reset_tx_pll_timer_ctr_reg(5),
+ I1 => sm_reset_tx_pll_timer_ctr_reg(3),
+ I2 => sm_reset_tx_pll_timer_ctr_reg(0),
+ I3 => sm_reset_tx_pll_timer_ctr_reg(1),
+ I4 => sm_reset_tx_pll_timer_ctr_reg(2),
+ I5 => sm_reset_tx_pll_timer_ctr_reg(4),
+ O => \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0\
+ );
+\sm_reset_tx_pll_timer_ctr_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(0),
+ Q => sm_reset_tx_pll_timer_ctr_reg(0),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(1),
+ Q => sm_reset_tx_pll_timer_ctr_reg(1),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \sm_reset_tx_pll_timer_ctr[2]_i_1_n_0\,
+ Q => sm_reset_tx_pll_timer_ctr_reg(2),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(3),
+ Q => sm_reset_tx_pll_timer_ctr_reg(3),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(4),
+ Q => sm_reset_tx_pll_timer_ctr_reg(4),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(5),
+ Q => sm_reset_tx_pll_timer_ctr_reg(5),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[6]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(6),
+ Q => sm_reset_tx_pll_timer_ctr_reg(6),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[7]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(7),
+ Q => sm_reset_tx_pll_timer_ctr_reg(7),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[8]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(8),
+ Q => sm_reset_tx_pll_timer_ctr_reg(8),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+\sm_reset_tx_pll_timer_ctr_reg[9]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => sel,
+ D => \p_0_in__0\(9),
+ Q => sm_reset_tx_pll_timer_ctr_reg(9),
+ R => sm_reset_tx_pll_timer_clr_reg_n_0
+ );
+sm_reset_tx_pll_timer_sat_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"0D"
+ )
+ port map (
+ I0 => sel,
+ I1 => sm_reset_tx_pll_timer_sat,
+ I2 => sm_reset_tx_pll_timer_clr_reg_n_0,
+ O => sm_reset_tx_pll_timer_sat_i_1_n_0
+ );
+sm_reset_tx_pll_timer_sat_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_tx_pll_timer_sat_i_1_n_0,
+ Q => sm_reset_tx_pll_timer_sat,
+ R => '0'
+ );
+sm_reset_tx_timer_clr_reg: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_plllock_tx_inst_n_1,
+ Q => sm_reset_tx_timer_clr_reg_n_0,
+ S => gtwiz_reset_tx_any_sync
+ );
+\sm_reset_tx_timer_ctr0_inferred__0/i_\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"7F"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_ctr(2),
+ I1 => sm_reset_tx_timer_ctr(0),
+ I2 => sm_reset_tx_timer_ctr(1),
+ O => p_0_in
+ );
+\sm_reset_tx_timer_ctr[0]_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_ctr(0),
+ O => p_1_in(0)
+ );
+\sm_reset_tx_timer_ctr[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_ctr(0),
+ I1 => sm_reset_tx_timer_ctr(1),
+ O => p_1_in(1)
+ );
+\sm_reset_tx_timer_ctr[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"78"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_ctr(0),
+ I1 => sm_reset_tx_timer_ctr(1),
+ I2 => sm_reset_tx_timer_ctr(2),
+ O => p_1_in(2)
+ );
+\sm_reset_tx_timer_ctr_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => p_0_in,
+ D => p_1_in(0),
+ Q => sm_reset_tx_timer_ctr(0),
+ R => sm_reset_tx_timer_clr_reg_n_0
+ );
+\sm_reset_tx_timer_ctr_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => p_0_in,
+ D => p_1_in(1),
+ Q => sm_reset_tx_timer_ctr(1),
+ R => sm_reset_tx_timer_clr_reg_n_0
+ );
+\sm_reset_tx_timer_ctr_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => p_0_in,
+ D => p_1_in(2),
+ Q => sm_reset_tx_timer_ctr(2),
+ R => sm_reset_tx_timer_clr_reg_n_0
+ );
+sm_reset_tx_timer_sat_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0000FF80"
+ )
+ port map (
+ I0 => sm_reset_tx_timer_ctr(2),
+ I1 => sm_reset_tx_timer_ctr(0),
+ I2 => sm_reset_tx_timer_ctr(1),
+ I3 => sm_reset_tx_timer_sat,
+ I4 => sm_reset_tx_timer_clr_reg_n_0,
+ O => sm_reset_tx_timer_sat_i_1_n_0
+ );
+sm_reset_tx_timer_sat_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => sm_reset_tx_timer_sat_i_1_n_0,
+ Q => sm_reset_tx_timer_sat,
+ R => '0'
+ );
+txuserrdy_out_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => gtwiz_reset_clk_freerun_in(0),
+ CE => '1',
+ D => bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_0,
+ Q => \^gthe3_channel_txuserrdy\(0),
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_gthe3 is
+ port (
+ qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ cplllock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxn_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxp_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtpowergood_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrlock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxratedone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txprgdivresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxn_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxp_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslide_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 127 downto 0 );
+ loopback_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_gthe3;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_gthe3 is
+ signal \^cplllock_out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_40\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_41\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_42\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_43\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_56\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_common.gen_common_container[2].gen_enabled_common.gthe3_common_wrapper_inst_n_2\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_common.gen_common_container[2].gen_enabled_common.gthe3_common_wrapper_inst_n_3\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gtpowergood_int__0\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gtrxreset_int\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gttxreset_int\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst_n_11\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst_n_4\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_plllock_rx_int__0\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxcdrlock_int__0\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxprogdivreset_int\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxuserrdy_int\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_txprogdivreset_int\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_txuserrdy_int\ : STD_LOGIC;
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \gen_gtwizard_gthe3.txdlysreset_int\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal \gen_gtwizard_gthe3.txsyncallin_int\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^gtpowergood_out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \^qpll1lock_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^qpll1outclk_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^qpll1outrefclk_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal rst_in0 : STD_LOGIC;
+ signal \^rxcdrlock_out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \^rxresetdone_out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \^txresetdone_out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+begin
+ cplllock_out(3 downto 0) <= \^cplllock_out\(3 downto 0);
+ gtpowergood_out(3 downto 0) <= \^gtpowergood_out\(3 downto 0);
+ qpll1lock_out(0) <= \^qpll1lock_out\(0);
+ qpll1outclk_out(0) <= \^qpll1outclk_out\(0);
+ qpll1outrefclk_out(0) <= \^qpll1outrefclk_out\(0);
+ rxcdrlock_out(3 downto 0) <= \^rxcdrlock_out\(3 downto 0);
+ rxresetdone_out(3 downto 0) <= \^rxresetdone_out\(3 downto 0);
+ txresetdone_out(3 downto 0) <= \^txresetdone_out\(3 downto 0);
+\gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gthe3_channel_wrapper
+ port map (
+ GTHE3_CHANNEL_CPLLPD(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\,
+ GTHE3_CHANNEL_GTRXRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gtrxreset_int\,
+ GTHE3_CHANNEL_GTTXRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gttxreset_int\,
+ GTHE3_CHANNEL_RXPROGDIVRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxprogdivreset_int\,
+ GTHE3_CHANNEL_RXUSERRDY(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxuserrdy_int\,
+ GTHE3_CHANNEL_TXDLYSRESET(0) => \gen_gtwizard_gthe3.txdlysreset_int\(3),
+ GTHE3_CHANNEL_TXPHALIGNDONE(3) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_40\,
+ GTHE3_CHANNEL_TXPHALIGNDONE(2) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_41\,
+ GTHE3_CHANNEL_TXPHALIGNDONE(1) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_42\,
+ GTHE3_CHANNEL_TXPHALIGNDONE(0) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_43\,
+ GTHE3_CHANNEL_TXPROGDIVRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_txprogdivreset_int\,
+ GTHE3_CHANNEL_TXSYNCALLIN(0) => \gen_gtwizard_gthe3.txsyncallin_int\(0),
+ GTHE3_CHANNEL_TXSYNCDONE(0) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_56\,
+ GTHE3_CHANNEL_TXUSERRDY(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_txuserrdy_int\,
+ cplllock_out(3 downto 0) => \^cplllock_out\(3 downto 0),
+ drpclk_in(3 downto 0) => drpclk_in(3 downto 0),
+ gthrxn_in(3 downto 0) => gthrxn_in(3 downto 0),
+ gthrxp_in(3 downto 0) => gthrxp_in(3 downto 0),
+ gthtxn_out(3 downto 0) => gthtxn_out(3 downto 0),
+ gthtxp_out(3 downto 0) => gthtxp_out(3 downto 0),
+ gtpowergood_out(3 downto 0) => \^gtpowergood_out\(3 downto 0),
+ gtrefclk0_in(3 downto 0) => gtrefclk0_in(3 downto 0),
+ gtwiz_userdata_rx_out(63 downto 0) => gtwiz_userdata_rx_out(63 downto 0),
+ gtwiz_userdata_tx_in(127 downto 0) => gtwiz_userdata_tx_in(127 downto 0),
+ loopback_in(11 downto 0) => loopback_in(11 downto 0),
+ qpll0outclk_out(0) => \gen_gtwizard_gthe3.gen_common.gen_common_container[2].gen_enabled_common.gthe3_common_wrapper_inst_n_2\,
+ qpll0outrefclk_out(0) => \gen_gtwizard_gthe3.gen_common.gen_common_container[2].gen_enabled_common.gthe3_common_wrapper_inst_n_3\,
+ qpll1outclk_out(0) => \^qpll1outclk_out\(0),
+ qpll1outrefclk_out(0) => \^qpll1outrefclk_out\(0),
+ rxcdrhold_in(3 downto 0) => rxcdrhold_in(3 downto 0),
+ rxcdrlock_out(3 downto 0) => \^rxcdrlock_out\(3 downto 0),
+ rxoutclk_out(3 downto 0) => rxoutclk_out(3 downto 0),
+ rxpmaresetdone_out(3 downto 0) => rxpmaresetdone_out(3 downto 0),
+ rxpolarity_in(3 downto 0) => rxpolarity_in(3 downto 0),
+ rxratedone_out(3 downto 0) => rxratedone_out(3 downto 0),
+ rxresetdone_out(3 downto 0) => \^rxresetdone_out\(3 downto 0),
+ rxslide_in(3 downto 0) => rxslide_in(3 downto 0),
+ rxusrclk2_in(3 downto 0) => rxusrclk2_in(3 downto 0),
+ rxusrclk_in(3 downto 0) => rxusrclk_in(3 downto 0),
+ txoutclk_out(3 downto 0) => txoutclk_out(3 downto 0),
+ txpmaresetdone_out(3 downto 0) => txpmaresetdone_out(3 downto 0),
+ txpolarity_in(3 downto 0) => txpolarity_in(3 downto 0),
+ txprgdivresetdone_out(3 downto 0) => txprgdivresetdone_out(3 downto 0),
+ txresetdone_out(3 downto 0) => \^txresetdone_out\(3 downto 0),
+ txusrclk2_in(3 downto 0) => txusrclk2_in(3 downto 0),
+ txusrclk_in(3 downto 0) => txusrclk_in(3 downto 0)
+ );
+\gen_gtwizard_gthe3.gen_common.gen_common_container[2].gen_enabled_common.gthe3_common_wrapper_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gthe3_common_wrapper
+ port map (
+ \gthe3_common_gen.GTHE3_COMMON_PRIM_INST\ => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst_n_4\,
+ gtrefclk01_in(0) => gtrefclk01_in(0),
+ qpll0fbclklost_out(0) => qpll0fbclklost_out(0),
+ qpll0lock_out(0) => qpll0lock_out(0),
+ qpll0outclk_out(0) => \gen_gtwizard_gthe3.gen_common.gen_common_container[2].gen_enabled_common.gthe3_common_wrapper_inst_n_2\,
+ qpll0outrefclk_out(0) => \gen_gtwizard_gthe3.gen_common.gen_common_container[2].gen_enabled_common.gthe3_common_wrapper_inst_n_3\,
+ qpll1fbclklost_out(0) => qpll1fbclklost_out(0),
+ qpll1lock_out(0) => \^qpll1lock_out\(0),
+ qpll1outclk_out(0) => \^qpll1outclk_out\(0),
+ qpll1outrefclk_out(0) => \^qpll1outrefclk_out\(0),
+ rst_in0 => rst_in0
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_rxresetdone_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ rxresetdone_out(0) => \^rxresetdone_out\(0)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_txresetdone_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_0
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ txresetdone_out(0) => \^txresetdone_out\(0)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[1].bit_synchronizer_rxresetdone_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_1
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(1),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ rxresetdone_out(0) => \^rxresetdone_out\(1)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[1].bit_synchronizer_txresetdone_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_2
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(1),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ txresetdone_out(0) => \^txresetdone_out\(1)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[2].bit_synchronizer_rxresetdone_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_3
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(2),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ rxresetdone_out(0) => \^rxresetdone_out\(2)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[2].bit_synchronizer_txresetdone_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_4
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(2),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ txresetdone_out(0) => \^txresetdone_out\(2)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[3].bit_synchronizer_rxresetdone_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_5
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(3),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ rxresetdone_out(0) => \^rxresetdone_out\(3)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[3].bit_synchronizer_txresetdone_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_bit_synchronizer_6
+ port map (
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(3),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ txresetdone_out(0) => \^txresetdone_out\(3)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gtpowergood_int\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => \^gtpowergood_out\(1),
+ I1 => \^gtpowergood_out\(0),
+ I2 => \^gtpowergood_out\(3),
+ I3 => \^gtpowergood_out\(2),
+ O => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gtpowergood_int__0\
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gtwiz_reset
+ port map (
+ GTHE3_CHANNEL_CPLLPD(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int\,
+ GTHE3_CHANNEL_GTRXRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gtrxreset_int\,
+ GTHE3_CHANNEL_GTTXRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gttxreset_int\,
+ GTHE3_CHANNEL_RXPROGDIVRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxprogdivreset_int\,
+ GTHE3_CHANNEL_RXUSERRDY(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxuserrdy_int\,
+ GTHE3_CHANNEL_TXPROGDIVRESET(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_txprogdivreset_int\,
+ GTHE3_CHANNEL_TXUSERRDY(0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_txuserrdy_int\,
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(3 downto 0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync\(3 downto 0),
+ \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(3 downto 0) => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync\(3 downto 0),
+ gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0),
+ gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0),
+ gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0),
+ gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0),
+ gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0),
+ gtwiz_reset_tx_pll_and_datapath_in(0) => gtwiz_reset_tx_pll_and_datapath_in(0),
+ gtwiz_userclk_rx_active_in(0) => gtwiz_userclk_rx_active_in(0),
+ gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0),
+ i_in_meta_reg => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_plllock_rx_int__0\,
+ i_in_meta_reg_0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxcdrlock_int__0\,
+ i_in_out_reg => gtwiz_reset_rx_cdr_stable_out(0),
+ in0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_gtpowergood_int__0\,
+ pllreset_tx_out_reg_0 => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst_n_4\,
+ qpll1lock_out(0) => \^qpll1lock_out\(0),
+ rst_in0 => rst_in0,
+ rst_in_out_reg => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst_n_11\,
+ rxusrclk2_in(0) => rxusrclk2_in(0),
+ txusrclk2_in(0) => txusrclk2_in(0)
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_plllock_rx_int\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => \^cplllock_out\(1),
+ I1 => \^cplllock_out\(0),
+ I2 => \^cplllock_out\(3),
+ I3 => \^cplllock_out\(2),
+ O => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_plllock_rx_int__0\
+ );
+\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxcdrlock_int\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => \^rxcdrlock_out\(1),
+ I1 => \^rxcdrlock_out\(0),
+ I2 => \^rxcdrlock_out\(3),
+ I3 => \^rxcdrlock_out\(2),
+ O => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_rxcdrlock_int__0\
+ );
+\gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_ultrascale_v1_7_18_gtwiz_buffbypass_tx
+ port map (
+ GTHE3_CHANNEL_TXDLYSRESET(0) => \gen_gtwizard_gthe3.txdlysreset_int\(3),
+ GTHE3_CHANNEL_TXPHALIGNDONE(3) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_40\,
+ GTHE3_CHANNEL_TXPHALIGNDONE(2) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_41\,
+ GTHE3_CHANNEL_TXPHALIGNDONE(1) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_42\,
+ GTHE3_CHANNEL_TXPHALIGNDONE(0) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_43\,
+ GTHE3_CHANNEL_TXSYNCALLIN(0) => \gen_gtwizard_gthe3.txsyncallin_int\(0),
+ GTHE3_CHANNEL_TXSYNCDONE(0) => \gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst_n_56\,
+ gtwiz_buffbypass_tx_done_out(0) => gtwiz_buffbypass_tx_done_out(0),
+ gtwiz_buffbypass_tx_error_out(0) => gtwiz_buffbypass_tx_error_out(0),
+ gtwiz_buffbypass_tx_reset_in(0) => gtwiz_buffbypass_tx_reset_in(0),
+ gtwiz_buffbypass_tx_start_user_in(0) => gtwiz_buffbypass_tx_start_user_in(0),
+ rst_in_sync2_reg => \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst_n_11\,
+ txusrclk2_in(0) => txusrclk2_in(0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top is
+ port (
+ gtwiz_userclk_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_tx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_tx_usrclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_tx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_tx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_srcclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_usrclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_usrclk2_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_active_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_rx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_rx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_rx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_done_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_done_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_qpll0lock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_qpll1lock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_qpll0reset_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_qpll1reset_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_gthe3_cpll_cal_txoutclk_period_in : in STD_LOGIC_VECTOR ( 71 downto 0 );
+ gtwiz_gthe3_cpll_cal_cnt_tol_in : in STD_LOGIC_VECTOR ( 71 downto 0 );
+ gtwiz_gthe3_cpll_cal_bufg_ce_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtwiz_gthe4_cpll_cal_txoutclk_period_in : in STD_LOGIC_VECTOR ( 71 downto 0 );
+ gtwiz_gthe4_cpll_cal_cnt_tol_in : in STD_LOGIC_VECTOR ( 71 downto 0 );
+ gtwiz_gthe4_cpll_cal_bufg_ce_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtwiz_gtye4_cpll_cal_txoutclk_period_in : in STD_LOGIC_VECTOR ( 71 downto 0 );
+ gtwiz_gtye4_cpll_cal_cnt_tol_in : in STD_LOGIC_VECTOR ( 71 downto 0 );
+ gtwiz_gtye4_cpll_cal_bufg_ce_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 127 downto 0 );
+ gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ bgbypassb_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ bgmonitorenb_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ bgpdb_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ bgrcalovrd_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ bgrcalovrdenb_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpaddr_common_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
+ drpclk_common_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpdi_common_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ drpen_common_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpwe_common_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtgrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtgrefclk1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtnorthrefclk00_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtnorthrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtnorthrefclk10_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtnorthrefclk11_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtrefclk00_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtrefclk10_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtrefclk11_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtsouthrefclk00_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtsouthrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtsouthrefclk10_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtsouthrefclk11_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ pcierateqpll0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ pcierateqpll1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ pmarsvd0_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ pmarsvd1_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ qpll0clkrsvd0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0clkrsvd1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0fbdiv_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0lockdetclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0locken_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0pd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0refclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ qpll0reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1clkrsvd0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1clkrsvd1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1fbdiv_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1lockdetclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1locken_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1pd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1refclksel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ qpll1reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpllrsvd1_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ qpllrsvd2_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ qpllrsvd3_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ qpllrsvd4_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ rcalenb_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm0data_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm0reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm0toggle_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm0width_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm1data_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm1reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm1toggle_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm1width_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ tcongpi_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ tconpowerup_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ tconreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ tconrsvdin1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubcfgstreamen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubdo_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubdrdy_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubenable_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubgpi_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubintr_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubiolmbrst_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmbrst_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmcapture_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmdbgrst_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmdbgupdate_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmregen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmshift_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmsysrst_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmtck_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmtdi_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpdo_common_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
+ drprdy_common_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ pmarsvdout0_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ pmarsvdout1_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0refclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1refclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qplldmonitor0_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ qplldmonitor1_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ refclkoutmonitor0_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ refclkoutmonitor1_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxrecclk0_sel_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ rxrecclk1_sel_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ rxrecclk0sel_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxrecclk1sel_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm0finalout_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm0testdata_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm1finalout_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ sdm1testdata_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ tcongpo_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ tconrsvdout0_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ ubdaddr_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ ubden_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ ubdi_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ ubdwe_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ ubmdmtdo_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ ubrsvdout_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ ubtxuart_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ cdrstepdir_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ cdrstepsq_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ cdrstepsx_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ cfgreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ clkrsvd0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ clkrsvd1_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ cpllfreqlock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ cplllockdetclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ cplllocken_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ cpllpd_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ cpllrefclksel_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ cpllreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ dmonfiforeset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ dmonitorclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ drpaddr_in : in STD_LOGIC_VECTOR ( 35 downto 0 );
+ drpclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ drpdi_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ drpen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ drprst_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ drpwe_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ elpcaldvorwren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ elpcalpaorwren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ evoddphicaldone_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ evoddphicalstart_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ evoddphidrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ evoddphidwren_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ evoddphixrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ evoddphixwren_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ eyescanmode_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ eyescanreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ eyescantrigger_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ freqos_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtgrefclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxn_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxp_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtnorthrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtnorthrefclk1_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrefclk1_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtresetsel_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrsvd_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ gtrxreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrxresetsel_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtsouthrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtsouthrefclk1_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gttxreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gttxresetsel_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ incpctrl_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtyrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtyrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ loopback_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ looprsvd_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ lpbkrxtxseren_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ lpbktxrxseren_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcieeqrxeqadaptdone_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcierstidle_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ pciersttxsyncstart_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcieuserratedone_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcsrsvdin_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ pcsrsvdin2_in : in STD_LOGIC_VECTOR ( 19 downto 0 );
+ pmarsvdin_in : in STD_LOGIC_VECTOR ( 19 downto 0 );
+ qpll0clk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ qpll0freqlock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0refclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ qpll1clk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ qpll1freqlock_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1refclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ resetovrd_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rstclkentx_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rx8b10ben_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxafecfoken_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxbufreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrfreqreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrresetrsv_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxchbonden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxchbondi_in : in STD_LOGIC_VECTOR ( 19 downto 0 );
+ rxchbondlevel_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ rxchbondmaster_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxchbondslave_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxckcalreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxckcalstart_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxcommadeten_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfeagcctrl_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxdccforcestart_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfeagchold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfeagcovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfecfokfcnum_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfecfokfen_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfecfokfpulse_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfecfokhold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfecfokovren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfekhhold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfekhovrden_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxdfelfhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfelfovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfelpmreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap10hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap10ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap11hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap11ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap12hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap12ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap13hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap13ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap14hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap14ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap15hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap15ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap2hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap2ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap3hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap3ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap4hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap4ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap5hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap5ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap6hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap6ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap7hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap7ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap8hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap8ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap9hold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfetap9ovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfeuthold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfeutovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfevphold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfevpovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfevsen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdfexyden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdlybypass_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdlyen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdlyovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxdlysreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxelecidlemode_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxeqtraining_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxgearboxslip_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlatclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmgchold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmgcovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmhfhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmhfovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmlfhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmlfklovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmoshold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxlpmosovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxmcommaalignen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxmonitorsel_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxoobreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoscalreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoshold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosintcfg_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ rxosinten_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosinthold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosintovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosintstrobe_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosinttestovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclksel_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ rxpcommaalignen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpcsreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpd_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxphalign_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxphalignen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxphdlypd_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxphdlyreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxphovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpllclksel_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxpmareset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxprbscntreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxprbssel_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ rxprogdivreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxqpien_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxrate_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ rxratemode_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslide_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslipoutclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslippma_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxsyncallin_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxsyncin_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxsyncmode_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxsysclksel_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxtermination_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ rxuserrdy_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ sigvalidclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ tstin_in : in STD_LOGIC_VECTOR ( 79 downto 0 );
+ tx8b10bbypass_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ tx8b10ben_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txbufdiffctrl_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ txcominit_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txcomsas_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txcomwake_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txctrl0_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ txctrl1_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
+ txctrl2_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ txdata_in : in STD_LOGIC_VECTOR ( 511 downto 0 );
+ txdataextendrsvd_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ txdccforcestart_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txdccreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txdeemph_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdetectrx_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdiffctrl_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ txdiffpd_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdlybypass_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdlyen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdlyhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdlyovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdlysreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdlyupdown_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txelecidle_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txelforcestart_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txheader_in : in STD_LOGIC_VECTOR ( 23 downto 0 );
+ txinhibit_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txlatclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txlfpstreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txlfpsu2lpexit_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txlfpsu3wake_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txmaincursor_in : in STD_LOGIC_VECTOR ( 27 downto 0 );
+ txmargin_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ txmuxdcdexhold_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txmuxdcdorwren_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txoneszeros_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ txoutclksel_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ txpcsreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpd_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ txpdelecidlemode_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphalign_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphalignen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphdlypd_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphdlyreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphdlytstclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphinit_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpippmen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpippmovrden_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpippmpd_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpippmsel_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpippmstepsize_in : in STD_LOGIC_VECTOR ( 19 downto 0 );
+ txpisopd_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpllclksel_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ txpmareset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpostcursor_in : in STD_LOGIC_VECTOR ( 19 downto 0 );
+ txpostcursorinv_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txprbsforceerr_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txprbssel_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ txprecursor_in : in STD_LOGIC_VECTOR ( 19 downto 0 );
+ txprecursorinv_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txprogdivreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txqpibiasen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txqpistrongpdown_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txqpiweakpup_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txrate_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ txratemode_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txsequence_in : in STD_LOGIC_VECTOR ( 27 downto 0 );
+ txswing_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txsyncallin_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txsyncin_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txsyncmode_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txsysclksel_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ txuserrdy_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ bufgtce_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ bufgtcemask_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ bufgtdiv_out : out STD_LOGIC_VECTOR ( 35 downto 0 );
+ bufgtreset_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ bufgtrstmask_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ cpllfbclklost_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ cplllock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ cpllrefclklost_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ dmonitorout_out : out STD_LOGIC_VECTOR ( 67 downto 0 );
+ dmonitoroutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ drpdo_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ drprdy_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ eyescandataerror_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxn_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxp_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtpowergood_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrefclkmonitor_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtytxn_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtytxp_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ pcierategen3_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcierateidle_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcierateqpllpd_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ pcierateqpllreset_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ pciesynctxsyncdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcieusergen3rdy_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcieuserphystatusrst_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcieuserratestart_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ pcsrsvdout_out : out STD_LOGIC_VECTOR ( 47 downto 0 );
+ phystatus_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ pinrsrvdas_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ powerpresent_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ resetexception_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxbufstatus_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ rxbyteisaligned_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxbyterealign_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrlock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrphdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxchanbondseq_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxchanisaligned_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxchanrealign_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxchbondo_out : out STD_LOGIC_VECTOR ( 19 downto 0 );
+ rxckcaldone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxclkcorcnt_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxcominitdet_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcommadet_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcomsasdet_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcomwakedet_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxctrl0_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ rxctrl1_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ rxctrl2_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ rxctrl3_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ rxdata_out : out STD_LOGIC_VECTOR ( 511 downto 0 );
+ rxdataextendrsvd_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ rxdatavalid_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxdlysresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxelecidle_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxheader_out : out STD_LOGIC_VECTOR ( 23 downto 0 );
+ rxheadervalid_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxlfpstresetdet_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxlfpsu2lpexitdet_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxlfpsu3wakedet_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ rxmonitorout_out : out STD_LOGIC_VECTOR ( 27 downto 0 );
+ rxosintdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosintstarted_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosintstrobedone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxosintstrobestarted_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclkfabric_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclkpcs_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxphaligndone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxphalignerr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxprbserr_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxprbslocked_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxprgdivresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxqpisenn_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxqpisenp_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxratedone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxrecclkout_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxsliderdy_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslipdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslipoutclkrdy_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslippmardy_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxstartofseq_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ rxstatus_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ rxsyncdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxsyncout_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxvalid_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txbufstatus_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ txcomfinish_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txdccdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ txdlysresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txoutclkfabric_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txoutclkpcs_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphaligndone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txphinitdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txprgdivresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txqpisenn_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txqpisenp_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txratedone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txsyncdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txsyncout_out : out STD_LOGIC_VECTOR ( 3 downto 0 )
+ );
+ attribute C_CHANNEL_ENABLE : string;
+ attribute C_CHANNEL_ENABLE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100000000";
+ attribute C_COMMON_SCALING_FACTOR : integer;
+ attribute C_COMMON_SCALING_FACTOR of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_CPLL_VCO_FREQUENCY : string;
+ attribute C_CPLL_VCO_FREQUENCY of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "2560.000000";
+ attribute C_ENABLE_COMMON_USRCLK : integer;
+ attribute C_ENABLE_COMMON_USRCLK of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_FORCE_COMMONS : integer;
+ attribute C_FORCE_COMMONS of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_FREERUN_FREQUENCY : string;
+ attribute C_FREERUN_FREQUENCY of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "200.000000";
+ attribute C_GT_REV : integer;
+ attribute C_GT_REV of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 17;
+ attribute C_GT_TYPE : integer;
+ attribute C_GT_TYPE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_INCLUDE_CPLL_CAL : integer;
+ attribute C_INCLUDE_CPLL_CAL of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 2;
+ attribute C_LOCATE_COMMON : integer;
+ attribute C_LOCATE_COMMON of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_LOCATE_IN_SYSTEM_IBERT_CORE : integer;
+ attribute C_LOCATE_IN_SYSTEM_IBERT_CORE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 2;
+ attribute C_LOCATE_RESET_CONTROLLER : integer;
+ attribute C_LOCATE_RESET_CONTROLLER of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER : integer;
+ attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_LOCATE_RX_USER_CLOCKING : integer;
+ attribute C_LOCATE_RX_USER_CLOCKING of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER : integer;
+ attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_LOCATE_TX_USER_CLOCKING : integer;
+ attribute C_LOCATE_TX_USER_CLOCKING of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_LOCATE_USER_DATA_WIDTH_SIZING : integer;
+ attribute C_LOCATE_USER_DATA_WIDTH_SIZING of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_PCIE_CORECLK_FREQ : integer;
+ attribute C_PCIE_CORECLK_FREQ of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 250;
+ attribute C_PCIE_ENABLE : integer;
+ attribute C_PCIE_ENABLE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_RESET_CONTROLLER_INSTANCE_CTRL : integer;
+ attribute C_RESET_CONTROLLER_INSTANCE_CTRL of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_RESET_SEQUENCE_INTERVAL : integer;
+ attribute C_RESET_SEQUENCE_INTERVAL of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_RX_BUFFBYPASS_MODE : integer;
+ attribute C_RX_BUFFBYPASS_MODE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL : integer;
+ attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_RX_BUFFER_MODE : integer;
+ attribute C_RX_BUFFER_MODE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_RX_CB_DISP : string;
+ attribute C_RX_CB_DISP of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "8'b00000000";
+ attribute C_RX_CB_K : string;
+ attribute C_RX_CB_K of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "8'b00000000";
+ attribute C_RX_CB_LEN_SEQ : integer;
+ attribute C_RX_CB_LEN_SEQ of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_RX_CB_MAX_LEVEL : integer;
+ attribute C_RX_CB_MAX_LEVEL of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 2;
+ attribute C_RX_CB_NUM_SEQ : integer;
+ attribute C_RX_CB_NUM_SEQ of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_RX_CB_VAL : string;
+ attribute C_RX_CB_VAL of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_RX_CC_DISP : string;
+ attribute C_RX_CC_DISP of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "8'b00000000";
+ attribute C_RX_CC_ENABLE : integer;
+ attribute C_RX_CC_ENABLE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_RX_CC_K : string;
+ attribute C_RX_CC_K of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "8'b00000000";
+ attribute C_RX_CC_LEN_SEQ : integer;
+ attribute C_RX_CC_LEN_SEQ of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_RX_CC_NUM_SEQ : integer;
+ attribute C_RX_CC_NUM_SEQ of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_RX_CC_PERIODICITY : integer;
+ attribute C_RX_CC_PERIODICITY of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 5000;
+ attribute C_RX_CC_VAL : string;
+ attribute C_RX_CC_VAL of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_RX_COMMA_M_ENABLE : integer;
+ attribute C_RX_COMMA_M_ENABLE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_RX_COMMA_M_VAL : string;
+ attribute C_RX_COMMA_M_VAL of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "10'b1010000011";
+ attribute C_RX_COMMA_P_ENABLE : integer;
+ attribute C_RX_COMMA_P_ENABLE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_RX_COMMA_P_VAL : string;
+ attribute C_RX_COMMA_P_VAL of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "10'b0101111100";
+ attribute C_RX_DATA_DECODING : integer;
+ attribute C_RX_DATA_DECODING of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_RX_ENABLE : integer;
+ attribute C_RX_ENABLE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_RX_INT_DATA_WIDTH : integer;
+ attribute C_RX_INT_DATA_WIDTH of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 16;
+ attribute C_RX_LINE_RATE : string;
+ attribute C_RX_LINE_RATE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "5.120000";
+ attribute C_RX_MASTER_CHANNEL_IDX : integer;
+ attribute C_RX_MASTER_CHANNEL_IDX of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 8;
+ attribute C_RX_OUTCLK_BUFG_GT_DIV : integer;
+ attribute C_RX_OUTCLK_BUFG_GT_DIV of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_RX_OUTCLK_FREQUENCY : string;
+ attribute C_RX_OUTCLK_FREQUENCY of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "320.000000";
+ attribute C_RX_OUTCLK_SOURCE : integer;
+ attribute C_RX_OUTCLK_SOURCE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_RX_PLL_TYPE : integer;
+ attribute C_RX_PLL_TYPE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 2;
+ attribute C_RX_RECCLK_OUTPUT : string;
+ attribute C_RX_RECCLK_OUTPUT of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_RX_REFCLK_FREQUENCY : string;
+ attribute C_RX_REFCLK_FREQUENCY of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "320.000000";
+ attribute C_RX_SLIDE_MODE : integer;
+ attribute C_RX_SLIDE_MODE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_RX_USER_CLOCKING_CONTENTS : integer;
+ attribute C_RX_USER_CLOCKING_CONTENTS of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_RX_USER_CLOCKING_INSTANCE_CTRL : integer;
+ attribute C_RX_USER_CLOCKING_INSTANCE_CTRL of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer;
+ attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer;
+ attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_RX_USER_CLOCKING_SOURCE : integer;
+ attribute C_RX_USER_CLOCKING_SOURCE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_RX_USER_DATA_WIDTH : integer;
+ attribute C_RX_USER_DATA_WIDTH of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 16;
+ attribute C_RX_USRCLK2_FREQUENCY : string;
+ attribute C_RX_USRCLK2_FREQUENCY of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "320.000000";
+ attribute C_RX_USRCLK_FREQUENCY : string;
+ attribute C_RX_USRCLK_FREQUENCY of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "320.000000";
+ attribute C_SECONDARY_QPLL_ENABLE : integer;
+ attribute C_SECONDARY_QPLL_ENABLE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY : string;
+ attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "257.812500";
+ attribute C_SIM_CPLL_CAL_BYPASS : integer;
+ attribute C_SIM_CPLL_CAL_BYPASS of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_TOTAL_NUM_CHANNELS : integer;
+ attribute C_TOTAL_NUM_CHANNELS of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 4;
+ attribute C_TOTAL_NUM_COMMONS : integer;
+ attribute C_TOTAL_NUM_COMMONS of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_TOTAL_NUM_COMMONS_EXAMPLE : integer;
+ attribute C_TOTAL_NUM_COMMONS_EXAMPLE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_TXPROGDIV_FREQ_ENABLE : integer;
+ attribute C_TXPROGDIV_FREQ_ENABLE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_TXPROGDIV_FREQ_SOURCE : integer;
+ attribute C_TXPROGDIV_FREQ_SOURCE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_TXPROGDIV_FREQ_VAL : string;
+ attribute C_TXPROGDIV_FREQ_VAL of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "320.000000";
+ attribute C_TX_BUFFBYPASS_MODE : integer;
+ attribute C_TX_BUFFBYPASS_MODE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL : integer;
+ attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_TX_BUFFER_MODE : integer;
+ attribute C_TX_BUFFER_MODE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_TX_DATA_ENCODING : integer;
+ attribute C_TX_DATA_ENCODING of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_TX_ENABLE : integer;
+ attribute C_TX_ENABLE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_TX_INT_DATA_WIDTH : integer;
+ attribute C_TX_INT_DATA_WIDTH of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 32;
+ attribute C_TX_LINE_RATE : string;
+ attribute C_TX_LINE_RATE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "10.240000";
+ attribute C_TX_MASTER_CHANNEL_IDX : integer;
+ attribute C_TX_MASTER_CHANNEL_IDX of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 8;
+ attribute C_TX_OUTCLK_BUFG_GT_DIV : integer;
+ attribute C_TX_OUTCLK_BUFG_GT_DIV of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_TX_OUTCLK_FREQUENCY : string;
+ attribute C_TX_OUTCLK_FREQUENCY of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "320.000000";
+ attribute C_TX_OUTCLK_SOURCE : integer;
+ attribute C_TX_OUTCLK_SOURCE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 4;
+ attribute C_TX_PLL_TYPE : integer;
+ attribute C_TX_PLL_TYPE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_TX_REFCLK_FREQUENCY : string;
+ attribute C_TX_REFCLK_FREQUENCY of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "240.000000";
+ attribute C_TX_USER_CLOCKING_CONTENTS : integer;
+ attribute C_TX_USER_CLOCKING_CONTENTS of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_TX_USER_CLOCKING_INSTANCE_CTRL : integer;
+ attribute C_TX_USER_CLOCKING_INSTANCE_CTRL of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer;
+ attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer;
+ attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 1;
+ attribute C_TX_USER_CLOCKING_SOURCE : integer;
+ attribute C_TX_USER_CLOCKING_SOURCE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+ attribute C_TX_USER_DATA_WIDTH : integer;
+ attribute C_TX_USER_DATA_WIDTH of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 32;
+ attribute C_TX_USRCLK2_FREQUENCY : string;
+ attribute C_TX_USRCLK2_FREQUENCY of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "320.000000";
+ attribute C_TX_USRCLK_FREQUENCY : string;
+ attribute C_TX_USRCLK_FREQUENCY of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is "320.000000";
+ attribute C_USER_GTPOWERGOOD_DELAY_EN : integer;
+ attribute C_USER_GTPOWERGOOD_DELAY_EN of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top : entity is 0;
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top is
+ signal \<const0>\ : STD_LOGIC;
+begin
+ bufgtce_out(11) <= \<const0>\;
+ bufgtce_out(10) <= \<const0>\;
+ bufgtce_out(9) <= \<const0>\;
+ bufgtce_out(8) <= \<const0>\;
+ bufgtce_out(7) <= \<const0>\;
+ bufgtce_out(6) <= \<const0>\;
+ bufgtce_out(5) <= \<const0>\;
+ bufgtce_out(4) <= \<const0>\;
+ bufgtce_out(3) <= \<const0>\;
+ bufgtce_out(2) <= \<const0>\;
+ bufgtce_out(1) <= \<const0>\;
+ bufgtce_out(0) <= \<const0>\;
+ bufgtcemask_out(11) <= \<const0>\;
+ bufgtcemask_out(10) <= \<const0>\;
+ bufgtcemask_out(9) <= \<const0>\;
+ bufgtcemask_out(8) <= \<const0>\;
+ bufgtcemask_out(7) <= \<const0>\;
+ bufgtcemask_out(6) <= \<const0>\;
+ bufgtcemask_out(5) <= \<const0>\;
+ bufgtcemask_out(4) <= \<const0>\;
+ bufgtcemask_out(3) <= \<const0>\;
+ bufgtcemask_out(2) <= \<const0>\;
+ bufgtcemask_out(1) <= \<const0>\;
+ bufgtcemask_out(0) <= \<const0>\;
+ bufgtdiv_out(35) <= \<const0>\;
+ bufgtdiv_out(34) <= \<const0>\;
+ bufgtdiv_out(33) <= \<const0>\;
+ bufgtdiv_out(32) <= \<const0>\;
+ bufgtdiv_out(31) <= \<const0>\;
+ bufgtdiv_out(30) <= \<const0>\;
+ bufgtdiv_out(29) <= \<const0>\;
+ bufgtdiv_out(28) <= \<const0>\;
+ bufgtdiv_out(27) <= \<const0>\;
+ bufgtdiv_out(26) <= \<const0>\;
+ bufgtdiv_out(25) <= \<const0>\;
+ bufgtdiv_out(24) <= \<const0>\;
+ bufgtdiv_out(23) <= \<const0>\;
+ bufgtdiv_out(22) <= \<const0>\;
+ bufgtdiv_out(21) <= \<const0>\;
+ bufgtdiv_out(20) <= \<const0>\;
+ bufgtdiv_out(19) <= \<const0>\;
+ bufgtdiv_out(18) <= \<const0>\;
+ bufgtdiv_out(17) <= \<const0>\;
+ bufgtdiv_out(16) <= \<const0>\;
+ bufgtdiv_out(15) <= \<const0>\;
+ bufgtdiv_out(14) <= \<const0>\;
+ bufgtdiv_out(13) <= \<const0>\;
+ bufgtdiv_out(12) <= \<const0>\;
+ bufgtdiv_out(11) <= \<const0>\;
+ bufgtdiv_out(10) <= \<const0>\;
+ bufgtdiv_out(9) <= \<const0>\;
+ bufgtdiv_out(8) <= \<const0>\;
+ bufgtdiv_out(7) <= \<const0>\;
+ bufgtdiv_out(6) <= \<const0>\;
+ bufgtdiv_out(5) <= \<const0>\;
+ bufgtdiv_out(4) <= \<const0>\;
+ bufgtdiv_out(3) <= \<const0>\;
+ bufgtdiv_out(2) <= \<const0>\;
+ bufgtdiv_out(1) <= \<const0>\;
+ bufgtdiv_out(0) <= \<const0>\;
+ bufgtreset_out(11) <= \<const0>\;
+ bufgtreset_out(10) <= \<const0>\;
+ bufgtreset_out(9) <= \<const0>\;
+ bufgtreset_out(8) <= \<const0>\;
+ bufgtreset_out(7) <= \<const0>\;
+ bufgtreset_out(6) <= \<const0>\;
+ bufgtreset_out(5) <= \<const0>\;
+ bufgtreset_out(4) <= \<const0>\;
+ bufgtreset_out(3) <= \<const0>\;
+ bufgtreset_out(2) <= \<const0>\;
+ bufgtreset_out(1) <= \<const0>\;
+ bufgtreset_out(0) <= \<const0>\;
+ bufgtrstmask_out(11) <= \<const0>\;
+ bufgtrstmask_out(10) <= \<const0>\;
+ bufgtrstmask_out(9) <= \<const0>\;
+ bufgtrstmask_out(8) <= \<const0>\;
+ bufgtrstmask_out(7) <= \<const0>\;
+ bufgtrstmask_out(6) <= \<const0>\;
+ bufgtrstmask_out(5) <= \<const0>\;
+ bufgtrstmask_out(4) <= \<const0>\;
+ bufgtrstmask_out(3) <= \<const0>\;
+ bufgtrstmask_out(2) <= \<const0>\;
+ bufgtrstmask_out(1) <= \<const0>\;
+ bufgtrstmask_out(0) <= \<const0>\;
+ cpllfbclklost_out(3) <= \<const0>\;
+ cpllfbclklost_out(2) <= \<const0>\;
+ cpllfbclklost_out(1) <= \<const0>\;
+ cpllfbclklost_out(0) <= \<const0>\;
+ cpllrefclklost_out(3) <= \<const0>\;
+ cpllrefclklost_out(2) <= \<const0>\;
+ cpllrefclklost_out(1) <= \<const0>\;
+ cpllrefclklost_out(0) <= \<const0>\;
+ dmonitorout_out(67) <= \<const0>\;
+ dmonitorout_out(66) <= \<const0>\;
+ dmonitorout_out(65) <= \<const0>\;
+ dmonitorout_out(64) <= \<const0>\;
+ dmonitorout_out(63) <= \<const0>\;
+ dmonitorout_out(62) <= \<const0>\;
+ dmonitorout_out(61) <= \<const0>\;
+ dmonitorout_out(60) <= \<const0>\;
+ dmonitorout_out(59) <= \<const0>\;
+ dmonitorout_out(58) <= \<const0>\;
+ dmonitorout_out(57) <= \<const0>\;
+ dmonitorout_out(56) <= \<const0>\;
+ dmonitorout_out(55) <= \<const0>\;
+ dmonitorout_out(54) <= \<const0>\;
+ dmonitorout_out(53) <= \<const0>\;
+ dmonitorout_out(52) <= \<const0>\;
+ dmonitorout_out(51) <= \<const0>\;
+ dmonitorout_out(50) <= \<const0>\;
+ dmonitorout_out(49) <= \<const0>\;
+ dmonitorout_out(48) <= \<const0>\;
+ dmonitorout_out(47) <= \<const0>\;
+ dmonitorout_out(46) <= \<const0>\;
+ dmonitorout_out(45) <= \<const0>\;
+ dmonitorout_out(44) <= \<const0>\;
+ dmonitorout_out(43) <= \<const0>\;
+ dmonitorout_out(42) <= \<const0>\;
+ dmonitorout_out(41) <= \<const0>\;
+ dmonitorout_out(40) <= \<const0>\;
+ dmonitorout_out(39) <= \<const0>\;
+ dmonitorout_out(38) <= \<const0>\;
+ dmonitorout_out(37) <= \<const0>\;
+ dmonitorout_out(36) <= \<const0>\;
+ dmonitorout_out(35) <= \<const0>\;
+ dmonitorout_out(34) <= \<const0>\;
+ dmonitorout_out(33) <= \<const0>\;
+ dmonitorout_out(32) <= \<const0>\;
+ dmonitorout_out(31) <= \<const0>\;
+ dmonitorout_out(30) <= \<const0>\;
+ dmonitorout_out(29) <= \<const0>\;
+ dmonitorout_out(28) <= \<const0>\;
+ dmonitorout_out(27) <= \<const0>\;
+ dmonitorout_out(26) <= \<const0>\;
+ dmonitorout_out(25) <= \<const0>\;
+ dmonitorout_out(24) <= \<const0>\;
+ dmonitorout_out(23) <= \<const0>\;
+ dmonitorout_out(22) <= \<const0>\;
+ dmonitorout_out(21) <= \<const0>\;
+ dmonitorout_out(20) <= \<const0>\;
+ dmonitorout_out(19) <= \<const0>\;
+ dmonitorout_out(18) <= \<const0>\;
+ dmonitorout_out(17) <= \<const0>\;
+ dmonitorout_out(16) <= \<const0>\;
+ dmonitorout_out(15) <= \<const0>\;
+ dmonitorout_out(14) <= \<const0>\;
+ dmonitorout_out(13) <= \<const0>\;
+ dmonitorout_out(12) <= \<const0>\;
+ dmonitorout_out(11) <= \<const0>\;
+ dmonitorout_out(10) <= \<const0>\;
+ dmonitorout_out(9) <= \<const0>\;
+ dmonitorout_out(8) <= \<const0>\;
+ dmonitorout_out(7) <= \<const0>\;
+ dmonitorout_out(6) <= \<const0>\;
+ dmonitorout_out(5) <= \<const0>\;
+ dmonitorout_out(4) <= \<const0>\;
+ dmonitorout_out(3) <= \<const0>\;
+ dmonitorout_out(2) <= \<const0>\;
+ dmonitorout_out(1) <= \<const0>\;
+ dmonitorout_out(0) <= \<const0>\;
+ dmonitoroutclk_out(0) <= \<const0>\;
+ drpdo_common_out(15) <= \<const0>\;
+ drpdo_common_out(14) <= \<const0>\;
+ drpdo_common_out(13) <= \<const0>\;
+ drpdo_common_out(12) <= \<const0>\;
+ drpdo_common_out(11) <= \<const0>\;
+ drpdo_common_out(10) <= \<const0>\;
+ drpdo_common_out(9) <= \<const0>\;
+ drpdo_common_out(8) <= \<const0>\;
+ drpdo_common_out(7) <= \<const0>\;
+ drpdo_common_out(6) <= \<const0>\;
+ drpdo_common_out(5) <= \<const0>\;
+ drpdo_common_out(4) <= \<const0>\;
+ drpdo_common_out(3) <= \<const0>\;
+ drpdo_common_out(2) <= \<const0>\;
+ drpdo_common_out(1) <= \<const0>\;
+ drpdo_common_out(0) <= \<const0>\;
+ drpdo_out(63) <= \<const0>\;
+ drpdo_out(62) <= \<const0>\;
+ drpdo_out(61) <= \<const0>\;
+ drpdo_out(60) <= \<const0>\;
+ drpdo_out(59) <= \<const0>\;
+ drpdo_out(58) <= \<const0>\;
+ drpdo_out(57) <= \<const0>\;
+ drpdo_out(56) <= \<const0>\;
+ drpdo_out(55) <= \<const0>\;
+ drpdo_out(54) <= \<const0>\;
+ drpdo_out(53) <= \<const0>\;
+ drpdo_out(52) <= \<const0>\;
+ drpdo_out(51) <= \<const0>\;
+ drpdo_out(50) <= \<const0>\;
+ drpdo_out(49) <= \<const0>\;
+ drpdo_out(48) <= \<const0>\;
+ drpdo_out(47) <= \<const0>\;
+ drpdo_out(46) <= \<const0>\;
+ drpdo_out(45) <= \<const0>\;
+ drpdo_out(44) <= \<const0>\;
+ drpdo_out(43) <= \<const0>\;
+ drpdo_out(42) <= \<const0>\;
+ drpdo_out(41) <= \<const0>\;
+ drpdo_out(40) <= \<const0>\;
+ drpdo_out(39) <= \<const0>\;
+ drpdo_out(38) <= \<const0>\;
+ drpdo_out(37) <= \<const0>\;
+ drpdo_out(36) <= \<const0>\;
+ drpdo_out(35) <= \<const0>\;
+ drpdo_out(34) <= \<const0>\;
+ drpdo_out(33) <= \<const0>\;
+ drpdo_out(32) <= \<const0>\;
+ drpdo_out(31) <= \<const0>\;
+ drpdo_out(30) <= \<const0>\;
+ drpdo_out(29) <= \<const0>\;
+ drpdo_out(28) <= \<const0>\;
+ drpdo_out(27) <= \<const0>\;
+ drpdo_out(26) <= \<const0>\;
+ drpdo_out(25) <= \<const0>\;
+ drpdo_out(24) <= \<const0>\;
+ drpdo_out(23) <= \<const0>\;
+ drpdo_out(22) <= \<const0>\;
+ drpdo_out(21) <= \<const0>\;
+ drpdo_out(20) <= \<const0>\;
+ drpdo_out(19) <= \<const0>\;
+ drpdo_out(18) <= \<const0>\;
+ drpdo_out(17) <= \<const0>\;
+ drpdo_out(16) <= \<const0>\;
+ drpdo_out(15) <= \<const0>\;
+ drpdo_out(14) <= \<const0>\;
+ drpdo_out(13) <= \<const0>\;
+ drpdo_out(12) <= \<const0>\;
+ drpdo_out(11) <= \<const0>\;
+ drpdo_out(10) <= \<const0>\;
+ drpdo_out(9) <= \<const0>\;
+ drpdo_out(8) <= \<const0>\;
+ drpdo_out(7) <= \<const0>\;
+ drpdo_out(6) <= \<const0>\;
+ drpdo_out(5) <= \<const0>\;
+ drpdo_out(4) <= \<const0>\;
+ drpdo_out(3) <= \<const0>\;
+ drpdo_out(2) <= \<const0>\;
+ drpdo_out(1) <= \<const0>\;
+ drpdo_out(0) <= \<const0>\;
+ drprdy_common_out(0) <= \<const0>\;
+ drprdy_out(3) <= \<const0>\;
+ drprdy_out(2) <= \<const0>\;
+ drprdy_out(1) <= \<const0>\;
+ drprdy_out(0) <= \<const0>\;
+ eyescandataerror_out(3) <= \<const0>\;
+ eyescandataerror_out(2) <= \<const0>\;
+ eyescandataerror_out(1) <= \<const0>\;
+ eyescandataerror_out(0) <= \<const0>\;
+ gtrefclkmonitor_out(3) <= \<const0>\;
+ gtrefclkmonitor_out(2) <= \<const0>\;
+ gtrefclkmonitor_out(1) <= \<const0>\;
+ gtrefclkmonitor_out(0) <= \<const0>\;
+ gtwiz_buffbypass_rx_done_out(0) <= \<const0>\;
+ gtwiz_buffbypass_rx_error_out(0) <= \<const0>\;
+ gtwiz_reset_qpll0reset_out(0) <= \<const0>\;
+ gtwiz_reset_qpll1reset_out(0) <= \<const0>\;
+ gtwiz_userclk_rx_active_out(0) <= \<const0>\;
+ gtwiz_userclk_rx_srcclk_out(0) <= \<const0>\;
+ gtwiz_userclk_rx_usrclk2_out(0) <= \<const0>\;
+ gtwiz_userclk_rx_usrclk_out(0) <= \<const0>\;
+ gtwiz_userclk_tx_active_out(0) <= \<const0>\;
+ gtwiz_userclk_tx_srcclk_out(0) <= \<const0>\;
+ gtwiz_userclk_tx_usrclk2_out(0) <= \<const0>\;
+ gtwiz_userclk_tx_usrclk_out(0) <= \<const0>\;
+ gtytxn_out(0) <= \<const0>\;
+ gtytxp_out(0) <= \<const0>\;
+ pcierategen3_out(3) <= \<const0>\;
+ pcierategen3_out(2) <= \<const0>\;
+ pcierategen3_out(1) <= \<const0>\;
+ pcierategen3_out(0) <= \<const0>\;
+ pcierateidle_out(3) <= \<const0>\;
+ pcierateidle_out(2) <= \<const0>\;
+ pcierateidle_out(1) <= \<const0>\;
+ pcierateidle_out(0) <= \<const0>\;
+ pcierateqpllpd_out(7) <= \<const0>\;
+ pcierateqpllpd_out(6) <= \<const0>\;
+ pcierateqpllpd_out(5) <= \<const0>\;
+ pcierateqpllpd_out(4) <= \<const0>\;
+ pcierateqpllpd_out(3) <= \<const0>\;
+ pcierateqpllpd_out(2) <= \<const0>\;
+ pcierateqpllpd_out(1) <= \<const0>\;
+ pcierateqpllpd_out(0) <= \<const0>\;
+ pcierateqpllreset_out(7) <= \<const0>\;
+ pcierateqpllreset_out(6) <= \<const0>\;
+ pcierateqpllreset_out(5) <= \<const0>\;
+ pcierateqpllreset_out(4) <= \<const0>\;
+ pcierateqpllreset_out(3) <= \<const0>\;
+ pcierateqpllreset_out(2) <= \<const0>\;
+ pcierateqpllreset_out(1) <= \<const0>\;
+ pcierateqpllreset_out(0) <= \<const0>\;
+ pciesynctxsyncdone_out(3) <= \<const0>\;
+ pciesynctxsyncdone_out(2) <= \<const0>\;
+ pciesynctxsyncdone_out(1) <= \<const0>\;
+ pciesynctxsyncdone_out(0) <= \<const0>\;
+ pcieusergen3rdy_out(3) <= \<const0>\;
+ pcieusergen3rdy_out(2) <= \<const0>\;
+ pcieusergen3rdy_out(1) <= \<const0>\;
+ pcieusergen3rdy_out(0) <= \<const0>\;
+ pcieuserphystatusrst_out(3) <= \<const0>\;
+ pcieuserphystatusrst_out(2) <= \<const0>\;
+ pcieuserphystatusrst_out(1) <= \<const0>\;
+ pcieuserphystatusrst_out(0) <= \<const0>\;
+ pcieuserratestart_out(3) <= \<const0>\;
+ pcieuserratestart_out(2) <= \<const0>\;
+ pcieuserratestart_out(1) <= \<const0>\;
+ pcieuserratestart_out(0) <= \<const0>\;
+ pcsrsvdout_out(47) <= \<const0>\;
+ pcsrsvdout_out(46) <= \<const0>\;
+ pcsrsvdout_out(45) <= \<const0>\;
+ pcsrsvdout_out(44) <= \<const0>\;
+ pcsrsvdout_out(43) <= \<const0>\;
+ pcsrsvdout_out(42) <= \<const0>\;
+ pcsrsvdout_out(41) <= \<const0>\;
+ pcsrsvdout_out(40) <= \<const0>\;
+ pcsrsvdout_out(39) <= \<const0>\;
+ pcsrsvdout_out(38) <= \<const0>\;
+ pcsrsvdout_out(37) <= \<const0>\;
+ pcsrsvdout_out(36) <= \<const0>\;
+ pcsrsvdout_out(35) <= \<const0>\;
+ pcsrsvdout_out(34) <= \<const0>\;
+ pcsrsvdout_out(33) <= \<const0>\;
+ pcsrsvdout_out(32) <= \<const0>\;
+ pcsrsvdout_out(31) <= \<const0>\;
+ pcsrsvdout_out(30) <= \<const0>\;
+ pcsrsvdout_out(29) <= \<const0>\;
+ pcsrsvdout_out(28) <= \<const0>\;
+ pcsrsvdout_out(27) <= \<const0>\;
+ pcsrsvdout_out(26) <= \<const0>\;
+ pcsrsvdout_out(25) <= \<const0>\;
+ pcsrsvdout_out(24) <= \<const0>\;
+ pcsrsvdout_out(23) <= \<const0>\;
+ pcsrsvdout_out(22) <= \<const0>\;
+ pcsrsvdout_out(21) <= \<const0>\;
+ pcsrsvdout_out(20) <= \<const0>\;
+ pcsrsvdout_out(19) <= \<const0>\;
+ pcsrsvdout_out(18) <= \<const0>\;
+ pcsrsvdout_out(17) <= \<const0>\;
+ pcsrsvdout_out(16) <= \<const0>\;
+ pcsrsvdout_out(15) <= \<const0>\;
+ pcsrsvdout_out(14) <= \<const0>\;
+ pcsrsvdout_out(13) <= \<const0>\;
+ pcsrsvdout_out(12) <= \<const0>\;
+ pcsrsvdout_out(11) <= \<const0>\;
+ pcsrsvdout_out(10) <= \<const0>\;
+ pcsrsvdout_out(9) <= \<const0>\;
+ pcsrsvdout_out(8) <= \<const0>\;
+ pcsrsvdout_out(7) <= \<const0>\;
+ pcsrsvdout_out(6) <= \<const0>\;
+ pcsrsvdout_out(5) <= \<const0>\;
+ pcsrsvdout_out(4) <= \<const0>\;
+ pcsrsvdout_out(3) <= \<const0>\;
+ pcsrsvdout_out(2) <= \<const0>\;
+ pcsrsvdout_out(1) <= \<const0>\;
+ pcsrsvdout_out(0) <= \<const0>\;
+ phystatus_out(3) <= \<const0>\;
+ phystatus_out(2) <= \<const0>\;
+ phystatus_out(1) <= \<const0>\;
+ phystatus_out(0) <= \<const0>\;
+ pinrsrvdas_out(31) <= \<const0>\;
+ pinrsrvdas_out(30) <= \<const0>\;
+ pinrsrvdas_out(29) <= \<const0>\;
+ pinrsrvdas_out(28) <= \<const0>\;
+ pinrsrvdas_out(27) <= \<const0>\;
+ pinrsrvdas_out(26) <= \<const0>\;
+ pinrsrvdas_out(25) <= \<const0>\;
+ pinrsrvdas_out(24) <= \<const0>\;
+ pinrsrvdas_out(23) <= \<const0>\;
+ pinrsrvdas_out(22) <= \<const0>\;
+ pinrsrvdas_out(21) <= \<const0>\;
+ pinrsrvdas_out(20) <= \<const0>\;
+ pinrsrvdas_out(19) <= \<const0>\;
+ pinrsrvdas_out(18) <= \<const0>\;
+ pinrsrvdas_out(17) <= \<const0>\;
+ pinrsrvdas_out(16) <= \<const0>\;
+ pinrsrvdas_out(15) <= \<const0>\;
+ pinrsrvdas_out(14) <= \<const0>\;
+ pinrsrvdas_out(13) <= \<const0>\;
+ pinrsrvdas_out(12) <= \<const0>\;
+ pinrsrvdas_out(11) <= \<const0>\;
+ pinrsrvdas_out(10) <= \<const0>\;
+ pinrsrvdas_out(9) <= \<const0>\;
+ pinrsrvdas_out(8) <= \<const0>\;
+ pinrsrvdas_out(7) <= \<const0>\;
+ pinrsrvdas_out(6) <= \<const0>\;
+ pinrsrvdas_out(5) <= \<const0>\;
+ pinrsrvdas_out(4) <= \<const0>\;
+ pinrsrvdas_out(3) <= \<const0>\;
+ pinrsrvdas_out(2) <= \<const0>\;
+ pinrsrvdas_out(1) <= \<const0>\;
+ pinrsrvdas_out(0) <= \<const0>\;
+ pmarsvdout0_out(7) <= \<const0>\;
+ pmarsvdout0_out(6) <= \<const0>\;
+ pmarsvdout0_out(5) <= \<const0>\;
+ pmarsvdout0_out(4) <= \<const0>\;
+ pmarsvdout0_out(3) <= \<const0>\;
+ pmarsvdout0_out(2) <= \<const0>\;
+ pmarsvdout0_out(1) <= \<const0>\;
+ pmarsvdout0_out(0) <= \<const0>\;
+ pmarsvdout1_out(7) <= \<const0>\;
+ pmarsvdout1_out(6) <= \<const0>\;
+ pmarsvdout1_out(5) <= \<const0>\;
+ pmarsvdout1_out(4) <= \<const0>\;
+ pmarsvdout1_out(3) <= \<const0>\;
+ pmarsvdout1_out(2) <= \<const0>\;
+ pmarsvdout1_out(1) <= \<const0>\;
+ pmarsvdout1_out(0) <= \<const0>\;
+ powerpresent_out(0) <= \<const0>\;
+ qpll0outclk_out(0) <= \<const0>\;
+ qpll0outrefclk_out(0) <= \<const0>\;
+ qpll0refclklost_out(0) <= \<const0>\;
+ qpll1refclklost_out(0) <= \<const0>\;
+ qplldmonitor0_out(7) <= \<const0>\;
+ qplldmonitor0_out(6) <= \<const0>\;
+ qplldmonitor0_out(5) <= \<const0>\;
+ qplldmonitor0_out(4) <= \<const0>\;
+ qplldmonitor0_out(3) <= \<const0>\;
+ qplldmonitor0_out(2) <= \<const0>\;
+ qplldmonitor0_out(1) <= \<const0>\;
+ qplldmonitor0_out(0) <= \<const0>\;
+ qplldmonitor1_out(7) <= \<const0>\;
+ qplldmonitor1_out(6) <= \<const0>\;
+ qplldmonitor1_out(5) <= \<const0>\;
+ qplldmonitor1_out(4) <= \<const0>\;
+ qplldmonitor1_out(3) <= \<const0>\;
+ qplldmonitor1_out(2) <= \<const0>\;
+ qplldmonitor1_out(1) <= \<const0>\;
+ qplldmonitor1_out(0) <= \<const0>\;
+ refclkoutmonitor0_out(0) <= \<const0>\;
+ refclkoutmonitor1_out(0) <= \<const0>\;
+ resetexception_out(3) <= \<const0>\;
+ resetexception_out(2) <= \<const0>\;
+ resetexception_out(1) <= \<const0>\;
+ resetexception_out(0) <= \<const0>\;
+ rxbufstatus_out(11) <= \<const0>\;
+ rxbufstatus_out(10) <= \<const0>\;
+ rxbufstatus_out(9) <= \<const0>\;
+ rxbufstatus_out(8) <= \<const0>\;
+ rxbufstatus_out(7) <= \<const0>\;
+ rxbufstatus_out(6) <= \<const0>\;
+ rxbufstatus_out(5) <= \<const0>\;
+ rxbufstatus_out(4) <= \<const0>\;
+ rxbufstatus_out(3) <= \<const0>\;
+ rxbufstatus_out(2) <= \<const0>\;
+ rxbufstatus_out(1) <= \<const0>\;
+ rxbufstatus_out(0) <= \<const0>\;
+ rxbyteisaligned_out(3) <= \<const0>\;
+ rxbyteisaligned_out(2) <= \<const0>\;
+ rxbyteisaligned_out(1) <= \<const0>\;
+ rxbyteisaligned_out(0) <= \<const0>\;
+ rxbyterealign_out(3) <= \<const0>\;
+ rxbyterealign_out(2) <= \<const0>\;
+ rxbyterealign_out(1) <= \<const0>\;
+ rxbyterealign_out(0) <= \<const0>\;
+ rxcdrphdone_out(3) <= \<const0>\;
+ rxcdrphdone_out(2) <= \<const0>\;
+ rxcdrphdone_out(1) <= \<const0>\;
+ rxcdrphdone_out(0) <= \<const0>\;
+ rxchanbondseq_out(3) <= \<const0>\;
+ rxchanbondseq_out(2) <= \<const0>\;
+ rxchanbondseq_out(1) <= \<const0>\;
+ rxchanbondseq_out(0) <= \<const0>\;
+ rxchanisaligned_out(3) <= \<const0>\;
+ rxchanisaligned_out(2) <= \<const0>\;
+ rxchanisaligned_out(1) <= \<const0>\;
+ rxchanisaligned_out(0) <= \<const0>\;
+ rxchanrealign_out(3) <= \<const0>\;
+ rxchanrealign_out(2) <= \<const0>\;
+ rxchanrealign_out(1) <= \<const0>\;
+ rxchanrealign_out(0) <= \<const0>\;
+ rxchbondo_out(19) <= \<const0>\;
+ rxchbondo_out(18) <= \<const0>\;
+ rxchbondo_out(17) <= \<const0>\;
+ rxchbondo_out(16) <= \<const0>\;
+ rxchbondo_out(15) <= \<const0>\;
+ rxchbondo_out(14) <= \<const0>\;
+ rxchbondo_out(13) <= \<const0>\;
+ rxchbondo_out(12) <= \<const0>\;
+ rxchbondo_out(11) <= \<const0>\;
+ rxchbondo_out(10) <= \<const0>\;
+ rxchbondo_out(9) <= \<const0>\;
+ rxchbondo_out(8) <= \<const0>\;
+ rxchbondo_out(7) <= \<const0>\;
+ rxchbondo_out(6) <= \<const0>\;
+ rxchbondo_out(5) <= \<const0>\;
+ rxchbondo_out(4) <= \<const0>\;
+ rxchbondo_out(3) <= \<const0>\;
+ rxchbondo_out(2) <= \<const0>\;
+ rxchbondo_out(1) <= \<const0>\;
+ rxchbondo_out(0) <= \<const0>\;
+ rxckcaldone_out(0) <= \<const0>\;
+ rxclkcorcnt_out(7) <= \<const0>\;
+ rxclkcorcnt_out(6) <= \<const0>\;
+ rxclkcorcnt_out(5) <= \<const0>\;
+ rxclkcorcnt_out(4) <= \<const0>\;
+ rxclkcorcnt_out(3) <= \<const0>\;
+ rxclkcorcnt_out(2) <= \<const0>\;
+ rxclkcorcnt_out(1) <= \<const0>\;
+ rxclkcorcnt_out(0) <= \<const0>\;
+ rxcominitdet_out(3) <= \<const0>\;
+ rxcominitdet_out(2) <= \<const0>\;
+ rxcominitdet_out(1) <= \<const0>\;
+ rxcominitdet_out(0) <= \<const0>\;
+ rxcommadet_out(3) <= \<const0>\;
+ rxcommadet_out(2) <= \<const0>\;
+ rxcommadet_out(1) <= \<const0>\;
+ rxcommadet_out(0) <= \<const0>\;
+ rxcomsasdet_out(3) <= \<const0>\;
+ rxcomsasdet_out(2) <= \<const0>\;
+ rxcomsasdet_out(1) <= \<const0>\;
+ rxcomsasdet_out(0) <= \<const0>\;
+ rxcomwakedet_out(3) <= \<const0>\;
+ rxcomwakedet_out(2) <= \<const0>\;
+ rxcomwakedet_out(1) <= \<const0>\;
+ rxcomwakedet_out(0) <= \<const0>\;
+ rxctrl0_out(63) <= \<const0>\;
+ rxctrl0_out(62) <= \<const0>\;
+ rxctrl0_out(61) <= \<const0>\;
+ rxctrl0_out(60) <= \<const0>\;
+ rxctrl0_out(59) <= \<const0>\;
+ rxctrl0_out(58) <= \<const0>\;
+ rxctrl0_out(57) <= \<const0>\;
+ rxctrl0_out(56) <= \<const0>\;
+ rxctrl0_out(55) <= \<const0>\;
+ rxctrl0_out(54) <= \<const0>\;
+ rxctrl0_out(53) <= \<const0>\;
+ rxctrl0_out(52) <= \<const0>\;
+ rxctrl0_out(51) <= \<const0>\;
+ rxctrl0_out(50) <= \<const0>\;
+ rxctrl0_out(49) <= \<const0>\;
+ rxctrl0_out(48) <= \<const0>\;
+ rxctrl0_out(47) <= \<const0>\;
+ rxctrl0_out(46) <= \<const0>\;
+ rxctrl0_out(45) <= \<const0>\;
+ rxctrl0_out(44) <= \<const0>\;
+ rxctrl0_out(43) <= \<const0>\;
+ rxctrl0_out(42) <= \<const0>\;
+ rxctrl0_out(41) <= \<const0>\;
+ rxctrl0_out(40) <= \<const0>\;
+ rxctrl0_out(39) <= \<const0>\;
+ rxctrl0_out(38) <= \<const0>\;
+ rxctrl0_out(37) <= \<const0>\;
+ rxctrl0_out(36) <= \<const0>\;
+ rxctrl0_out(35) <= \<const0>\;
+ rxctrl0_out(34) <= \<const0>\;
+ rxctrl0_out(33) <= \<const0>\;
+ rxctrl0_out(32) <= \<const0>\;
+ rxctrl0_out(31) <= \<const0>\;
+ rxctrl0_out(30) <= \<const0>\;
+ rxctrl0_out(29) <= \<const0>\;
+ rxctrl0_out(28) <= \<const0>\;
+ rxctrl0_out(27) <= \<const0>\;
+ rxctrl0_out(26) <= \<const0>\;
+ rxctrl0_out(25) <= \<const0>\;
+ rxctrl0_out(24) <= \<const0>\;
+ rxctrl0_out(23) <= \<const0>\;
+ rxctrl0_out(22) <= \<const0>\;
+ rxctrl0_out(21) <= \<const0>\;
+ rxctrl0_out(20) <= \<const0>\;
+ rxctrl0_out(19) <= \<const0>\;
+ rxctrl0_out(18) <= \<const0>\;
+ rxctrl0_out(17) <= \<const0>\;
+ rxctrl0_out(16) <= \<const0>\;
+ rxctrl0_out(15) <= \<const0>\;
+ rxctrl0_out(14) <= \<const0>\;
+ rxctrl0_out(13) <= \<const0>\;
+ rxctrl0_out(12) <= \<const0>\;
+ rxctrl0_out(11) <= \<const0>\;
+ rxctrl0_out(10) <= \<const0>\;
+ rxctrl0_out(9) <= \<const0>\;
+ rxctrl0_out(8) <= \<const0>\;
+ rxctrl0_out(7) <= \<const0>\;
+ rxctrl0_out(6) <= \<const0>\;
+ rxctrl0_out(5) <= \<const0>\;
+ rxctrl0_out(4) <= \<const0>\;
+ rxctrl0_out(3) <= \<const0>\;
+ rxctrl0_out(2) <= \<const0>\;
+ rxctrl0_out(1) <= \<const0>\;
+ rxctrl0_out(0) <= \<const0>\;
+ rxctrl1_out(63) <= \<const0>\;
+ rxctrl1_out(62) <= \<const0>\;
+ rxctrl1_out(61) <= \<const0>\;
+ rxctrl1_out(60) <= \<const0>\;
+ rxctrl1_out(59) <= \<const0>\;
+ rxctrl1_out(58) <= \<const0>\;
+ rxctrl1_out(57) <= \<const0>\;
+ rxctrl1_out(56) <= \<const0>\;
+ rxctrl1_out(55) <= \<const0>\;
+ rxctrl1_out(54) <= \<const0>\;
+ rxctrl1_out(53) <= \<const0>\;
+ rxctrl1_out(52) <= \<const0>\;
+ rxctrl1_out(51) <= \<const0>\;
+ rxctrl1_out(50) <= \<const0>\;
+ rxctrl1_out(49) <= \<const0>\;
+ rxctrl1_out(48) <= \<const0>\;
+ rxctrl1_out(47) <= \<const0>\;
+ rxctrl1_out(46) <= \<const0>\;
+ rxctrl1_out(45) <= \<const0>\;
+ rxctrl1_out(44) <= \<const0>\;
+ rxctrl1_out(43) <= \<const0>\;
+ rxctrl1_out(42) <= \<const0>\;
+ rxctrl1_out(41) <= \<const0>\;
+ rxctrl1_out(40) <= \<const0>\;
+ rxctrl1_out(39) <= \<const0>\;
+ rxctrl1_out(38) <= \<const0>\;
+ rxctrl1_out(37) <= \<const0>\;
+ rxctrl1_out(36) <= \<const0>\;
+ rxctrl1_out(35) <= \<const0>\;
+ rxctrl1_out(34) <= \<const0>\;
+ rxctrl1_out(33) <= \<const0>\;
+ rxctrl1_out(32) <= \<const0>\;
+ rxctrl1_out(31) <= \<const0>\;
+ rxctrl1_out(30) <= \<const0>\;
+ rxctrl1_out(29) <= \<const0>\;
+ rxctrl1_out(28) <= \<const0>\;
+ rxctrl1_out(27) <= \<const0>\;
+ rxctrl1_out(26) <= \<const0>\;
+ rxctrl1_out(25) <= \<const0>\;
+ rxctrl1_out(24) <= \<const0>\;
+ rxctrl1_out(23) <= \<const0>\;
+ rxctrl1_out(22) <= \<const0>\;
+ rxctrl1_out(21) <= \<const0>\;
+ rxctrl1_out(20) <= \<const0>\;
+ rxctrl1_out(19) <= \<const0>\;
+ rxctrl1_out(18) <= \<const0>\;
+ rxctrl1_out(17) <= \<const0>\;
+ rxctrl1_out(16) <= \<const0>\;
+ rxctrl1_out(15) <= \<const0>\;
+ rxctrl1_out(14) <= \<const0>\;
+ rxctrl1_out(13) <= \<const0>\;
+ rxctrl1_out(12) <= \<const0>\;
+ rxctrl1_out(11) <= \<const0>\;
+ rxctrl1_out(10) <= \<const0>\;
+ rxctrl1_out(9) <= \<const0>\;
+ rxctrl1_out(8) <= \<const0>\;
+ rxctrl1_out(7) <= \<const0>\;
+ rxctrl1_out(6) <= \<const0>\;
+ rxctrl1_out(5) <= \<const0>\;
+ rxctrl1_out(4) <= \<const0>\;
+ rxctrl1_out(3) <= \<const0>\;
+ rxctrl1_out(2) <= \<const0>\;
+ rxctrl1_out(1) <= \<const0>\;
+ rxctrl1_out(0) <= \<const0>\;
+ rxctrl2_out(31) <= \<const0>\;
+ rxctrl2_out(30) <= \<const0>\;
+ rxctrl2_out(29) <= \<const0>\;
+ rxctrl2_out(28) <= \<const0>\;
+ rxctrl2_out(27) <= \<const0>\;
+ rxctrl2_out(26) <= \<const0>\;
+ rxctrl2_out(25) <= \<const0>\;
+ rxctrl2_out(24) <= \<const0>\;
+ rxctrl2_out(23) <= \<const0>\;
+ rxctrl2_out(22) <= \<const0>\;
+ rxctrl2_out(21) <= \<const0>\;
+ rxctrl2_out(20) <= \<const0>\;
+ rxctrl2_out(19) <= \<const0>\;
+ rxctrl2_out(18) <= \<const0>\;
+ rxctrl2_out(17) <= \<const0>\;
+ rxctrl2_out(16) <= \<const0>\;
+ rxctrl2_out(15) <= \<const0>\;
+ rxctrl2_out(14) <= \<const0>\;
+ rxctrl2_out(13) <= \<const0>\;
+ rxctrl2_out(12) <= \<const0>\;
+ rxctrl2_out(11) <= \<const0>\;
+ rxctrl2_out(10) <= \<const0>\;
+ rxctrl2_out(9) <= \<const0>\;
+ rxctrl2_out(8) <= \<const0>\;
+ rxctrl2_out(7) <= \<const0>\;
+ rxctrl2_out(6) <= \<const0>\;
+ rxctrl2_out(5) <= \<const0>\;
+ rxctrl2_out(4) <= \<const0>\;
+ rxctrl2_out(3) <= \<const0>\;
+ rxctrl2_out(2) <= \<const0>\;
+ rxctrl2_out(1) <= \<const0>\;
+ rxctrl2_out(0) <= \<const0>\;
+ rxctrl3_out(31) <= \<const0>\;
+ rxctrl3_out(30) <= \<const0>\;
+ rxctrl3_out(29) <= \<const0>\;
+ rxctrl3_out(28) <= \<const0>\;
+ rxctrl3_out(27) <= \<const0>\;
+ rxctrl3_out(26) <= \<const0>\;
+ rxctrl3_out(25) <= \<const0>\;
+ rxctrl3_out(24) <= \<const0>\;
+ rxctrl3_out(23) <= \<const0>\;
+ rxctrl3_out(22) <= \<const0>\;
+ rxctrl3_out(21) <= \<const0>\;
+ rxctrl3_out(20) <= \<const0>\;
+ rxctrl3_out(19) <= \<const0>\;
+ rxctrl3_out(18) <= \<const0>\;
+ rxctrl3_out(17) <= \<const0>\;
+ rxctrl3_out(16) <= \<const0>\;
+ rxctrl3_out(15) <= \<const0>\;
+ rxctrl3_out(14) <= \<const0>\;
+ rxctrl3_out(13) <= \<const0>\;
+ rxctrl3_out(12) <= \<const0>\;
+ rxctrl3_out(11) <= \<const0>\;
+ rxctrl3_out(10) <= \<const0>\;
+ rxctrl3_out(9) <= \<const0>\;
+ rxctrl3_out(8) <= \<const0>\;
+ rxctrl3_out(7) <= \<const0>\;
+ rxctrl3_out(6) <= \<const0>\;
+ rxctrl3_out(5) <= \<const0>\;
+ rxctrl3_out(4) <= \<const0>\;
+ rxctrl3_out(3) <= \<const0>\;
+ rxctrl3_out(2) <= \<const0>\;
+ rxctrl3_out(1) <= \<const0>\;
+ rxctrl3_out(0) <= \<const0>\;
+ rxdata_out(511) <= \<const0>\;
+ rxdata_out(510) <= \<const0>\;
+ rxdata_out(509) <= \<const0>\;
+ rxdata_out(508) <= \<const0>\;
+ rxdata_out(507) <= \<const0>\;
+ rxdata_out(506) <= \<const0>\;
+ rxdata_out(505) <= \<const0>\;
+ rxdata_out(504) <= \<const0>\;
+ rxdata_out(503) <= \<const0>\;
+ rxdata_out(502) <= \<const0>\;
+ rxdata_out(501) <= \<const0>\;
+ rxdata_out(500) <= \<const0>\;
+ rxdata_out(499) <= \<const0>\;
+ rxdata_out(498) <= \<const0>\;
+ rxdata_out(497) <= \<const0>\;
+ rxdata_out(496) <= \<const0>\;
+ rxdata_out(495) <= \<const0>\;
+ rxdata_out(494) <= \<const0>\;
+ rxdata_out(493) <= \<const0>\;
+ rxdata_out(492) <= \<const0>\;
+ rxdata_out(491) <= \<const0>\;
+ rxdata_out(490) <= \<const0>\;
+ rxdata_out(489) <= \<const0>\;
+ rxdata_out(488) <= \<const0>\;
+ rxdata_out(487) <= \<const0>\;
+ rxdata_out(486) <= \<const0>\;
+ rxdata_out(485) <= \<const0>\;
+ rxdata_out(484) <= \<const0>\;
+ rxdata_out(483) <= \<const0>\;
+ rxdata_out(482) <= \<const0>\;
+ rxdata_out(481) <= \<const0>\;
+ rxdata_out(480) <= \<const0>\;
+ rxdata_out(479) <= \<const0>\;
+ rxdata_out(478) <= \<const0>\;
+ rxdata_out(477) <= \<const0>\;
+ rxdata_out(476) <= \<const0>\;
+ rxdata_out(475) <= \<const0>\;
+ rxdata_out(474) <= \<const0>\;
+ rxdata_out(473) <= \<const0>\;
+ rxdata_out(472) <= \<const0>\;
+ rxdata_out(471) <= \<const0>\;
+ rxdata_out(470) <= \<const0>\;
+ rxdata_out(469) <= \<const0>\;
+ rxdata_out(468) <= \<const0>\;
+ rxdata_out(467) <= \<const0>\;
+ rxdata_out(466) <= \<const0>\;
+ rxdata_out(465) <= \<const0>\;
+ rxdata_out(464) <= \<const0>\;
+ rxdata_out(463) <= \<const0>\;
+ rxdata_out(462) <= \<const0>\;
+ rxdata_out(461) <= \<const0>\;
+ rxdata_out(460) <= \<const0>\;
+ rxdata_out(459) <= \<const0>\;
+ rxdata_out(458) <= \<const0>\;
+ rxdata_out(457) <= \<const0>\;
+ rxdata_out(456) <= \<const0>\;
+ rxdata_out(455) <= \<const0>\;
+ rxdata_out(454) <= \<const0>\;
+ rxdata_out(453) <= \<const0>\;
+ rxdata_out(452) <= \<const0>\;
+ rxdata_out(451) <= \<const0>\;
+ rxdata_out(450) <= \<const0>\;
+ rxdata_out(449) <= \<const0>\;
+ rxdata_out(448) <= \<const0>\;
+ rxdata_out(447) <= \<const0>\;
+ rxdata_out(446) <= \<const0>\;
+ rxdata_out(445) <= \<const0>\;
+ rxdata_out(444) <= \<const0>\;
+ rxdata_out(443) <= \<const0>\;
+ rxdata_out(442) <= \<const0>\;
+ rxdata_out(441) <= \<const0>\;
+ rxdata_out(440) <= \<const0>\;
+ rxdata_out(439) <= \<const0>\;
+ rxdata_out(438) <= \<const0>\;
+ rxdata_out(437) <= \<const0>\;
+ rxdata_out(436) <= \<const0>\;
+ rxdata_out(435) <= \<const0>\;
+ rxdata_out(434) <= \<const0>\;
+ rxdata_out(433) <= \<const0>\;
+ rxdata_out(432) <= \<const0>\;
+ rxdata_out(431) <= \<const0>\;
+ rxdata_out(430) <= \<const0>\;
+ rxdata_out(429) <= \<const0>\;
+ rxdata_out(428) <= \<const0>\;
+ rxdata_out(427) <= \<const0>\;
+ rxdata_out(426) <= \<const0>\;
+ rxdata_out(425) <= \<const0>\;
+ rxdata_out(424) <= \<const0>\;
+ rxdata_out(423) <= \<const0>\;
+ rxdata_out(422) <= \<const0>\;
+ rxdata_out(421) <= \<const0>\;
+ rxdata_out(420) <= \<const0>\;
+ rxdata_out(419) <= \<const0>\;
+ rxdata_out(418) <= \<const0>\;
+ rxdata_out(417) <= \<const0>\;
+ rxdata_out(416) <= \<const0>\;
+ rxdata_out(415) <= \<const0>\;
+ rxdata_out(414) <= \<const0>\;
+ rxdata_out(413) <= \<const0>\;
+ rxdata_out(412) <= \<const0>\;
+ rxdata_out(411) <= \<const0>\;
+ rxdata_out(410) <= \<const0>\;
+ rxdata_out(409) <= \<const0>\;
+ rxdata_out(408) <= \<const0>\;
+ rxdata_out(407) <= \<const0>\;
+ rxdata_out(406) <= \<const0>\;
+ rxdata_out(405) <= \<const0>\;
+ rxdata_out(404) <= \<const0>\;
+ rxdata_out(403) <= \<const0>\;
+ rxdata_out(402) <= \<const0>\;
+ rxdata_out(401) <= \<const0>\;
+ rxdata_out(400) <= \<const0>\;
+ rxdata_out(399) <= \<const0>\;
+ rxdata_out(398) <= \<const0>\;
+ rxdata_out(397) <= \<const0>\;
+ rxdata_out(396) <= \<const0>\;
+ rxdata_out(395) <= \<const0>\;
+ rxdata_out(394) <= \<const0>\;
+ rxdata_out(393) <= \<const0>\;
+ rxdata_out(392) <= \<const0>\;
+ rxdata_out(391) <= \<const0>\;
+ rxdata_out(390) <= \<const0>\;
+ rxdata_out(389) <= \<const0>\;
+ rxdata_out(388) <= \<const0>\;
+ rxdata_out(387) <= \<const0>\;
+ rxdata_out(386) <= \<const0>\;
+ rxdata_out(385) <= \<const0>\;
+ rxdata_out(384) <= \<const0>\;
+ rxdata_out(383) <= \<const0>\;
+ rxdata_out(382) <= \<const0>\;
+ rxdata_out(381) <= \<const0>\;
+ rxdata_out(380) <= \<const0>\;
+ rxdata_out(379) <= \<const0>\;
+ rxdata_out(378) <= \<const0>\;
+ rxdata_out(377) <= \<const0>\;
+ rxdata_out(376) <= \<const0>\;
+ rxdata_out(375) <= \<const0>\;
+ rxdata_out(374) <= \<const0>\;
+ rxdata_out(373) <= \<const0>\;
+ rxdata_out(372) <= \<const0>\;
+ rxdata_out(371) <= \<const0>\;
+ rxdata_out(370) <= \<const0>\;
+ rxdata_out(369) <= \<const0>\;
+ rxdata_out(368) <= \<const0>\;
+ rxdata_out(367) <= \<const0>\;
+ rxdata_out(366) <= \<const0>\;
+ rxdata_out(365) <= \<const0>\;
+ rxdata_out(364) <= \<const0>\;
+ rxdata_out(363) <= \<const0>\;
+ rxdata_out(362) <= \<const0>\;
+ rxdata_out(361) <= \<const0>\;
+ rxdata_out(360) <= \<const0>\;
+ rxdata_out(359) <= \<const0>\;
+ rxdata_out(358) <= \<const0>\;
+ rxdata_out(357) <= \<const0>\;
+ rxdata_out(356) <= \<const0>\;
+ rxdata_out(355) <= \<const0>\;
+ rxdata_out(354) <= \<const0>\;
+ rxdata_out(353) <= \<const0>\;
+ rxdata_out(352) <= \<const0>\;
+ rxdata_out(351) <= \<const0>\;
+ rxdata_out(350) <= \<const0>\;
+ rxdata_out(349) <= \<const0>\;
+ rxdata_out(348) <= \<const0>\;
+ rxdata_out(347) <= \<const0>\;
+ rxdata_out(346) <= \<const0>\;
+ rxdata_out(345) <= \<const0>\;
+ rxdata_out(344) <= \<const0>\;
+ rxdata_out(343) <= \<const0>\;
+ rxdata_out(342) <= \<const0>\;
+ rxdata_out(341) <= \<const0>\;
+ rxdata_out(340) <= \<const0>\;
+ rxdata_out(339) <= \<const0>\;
+ rxdata_out(338) <= \<const0>\;
+ rxdata_out(337) <= \<const0>\;
+ rxdata_out(336) <= \<const0>\;
+ rxdata_out(335) <= \<const0>\;
+ rxdata_out(334) <= \<const0>\;
+ rxdata_out(333) <= \<const0>\;
+ rxdata_out(332) <= \<const0>\;
+ rxdata_out(331) <= \<const0>\;
+ rxdata_out(330) <= \<const0>\;
+ rxdata_out(329) <= \<const0>\;
+ rxdata_out(328) <= \<const0>\;
+ rxdata_out(327) <= \<const0>\;
+ rxdata_out(326) <= \<const0>\;
+ rxdata_out(325) <= \<const0>\;
+ rxdata_out(324) <= \<const0>\;
+ rxdata_out(323) <= \<const0>\;
+ rxdata_out(322) <= \<const0>\;
+ rxdata_out(321) <= \<const0>\;
+ rxdata_out(320) <= \<const0>\;
+ rxdata_out(319) <= \<const0>\;
+ rxdata_out(318) <= \<const0>\;
+ rxdata_out(317) <= \<const0>\;
+ rxdata_out(316) <= \<const0>\;
+ rxdata_out(315) <= \<const0>\;
+ rxdata_out(314) <= \<const0>\;
+ rxdata_out(313) <= \<const0>\;
+ rxdata_out(312) <= \<const0>\;
+ rxdata_out(311) <= \<const0>\;
+ rxdata_out(310) <= \<const0>\;
+ rxdata_out(309) <= \<const0>\;
+ rxdata_out(308) <= \<const0>\;
+ rxdata_out(307) <= \<const0>\;
+ rxdata_out(306) <= \<const0>\;
+ rxdata_out(305) <= \<const0>\;
+ rxdata_out(304) <= \<const0>\;
+ rxdata_out(303) <= \<const0>\;
+ rxdata_out(302) <= \<const0>\;
+ rxdata_out(301) <= \<const0>\;
+ rxdata_out(300) <= \<const0>\;
+ rxdata_out(299) <= \<const0>\;
+ rxdata_out(298) <= \<const0>\;
+ rxdata_out(297) <= \<const0>\;
+ rxdata_out(296) <= \<const0>\;
+ rxdata_out(295) <= \<const0>\;
+ rxdata_out(294) <= \<const0>\;
+ rxdata_out(293) <= \<const0>\;
+ rxdata_out(292) <= \<const0>\;
+ rxdata_out(291) <= \<const0>\;
+ rxdata_out(290) <= \<const0>\;
+ rxdata_out(289) <= \<const0>\;
+ rxdata_out(288) <= \<const0>\;
+ rxdata_out(287) <= \<const0>\;
+ rxdata_out(286) <= \<const0>\;
+ rxdata_out(285) <= \<const0>\;
+ rxdata_out(284) <= \<const0>\;
+ rxdata_out(283) <= \<const0>\;
+ rxdata_out(282) <= \<const0>\;
+ rxdata_out(281) <= \<const0>\;
+ rxdata_out(280) <= \<const0>\;
+ rxdata_out(279) <= \<const0>\;
+ rxdata_out(278) <= \<const0>\;
+ rxdata_out(277) <= \<const0>\;
+ rxdata_out(276) <= \<const0>\;
+ rxdata_out(275) <= \<const0>\;
+ rxdata_out(274) <= \<const0>\;
+ rxdata_out(273) <= \<const0>\;
+ rxdata_out(272) <= \<const0>\;
+ rxdata_out(271) <= \<const0>\;
+ rxdata_out(270) <= \<const0>\;
+ rxdata_out(269) <= \<const0>\;
+ rxdata_out(268) <= \<const0>\;
+ rxdata_out(267) <= \<const0>\;
+ rxdata_out(266) <= \<const0>\;
+ rxdata_out(265) <= \<const0>\;
+ rxdata_out(264) <= \<const0>\;
+ rxdata_out(263) <= \<const0>\;
+ rxdata_out(262) <= \<const0>\;
+ rxdata_out(261) <= \<const0>\;
+ rxdata_out(260) <= \<const0>\;
+ rxdata_out(259) <= \<const0>\;
+ rxdata_out(258) <= \<const0>\;
+ rxdata_out(257) <= \<const0>\;
+ rxdata_out(256) <= \<const0>\;
+ rxdata_out(255) <= \<const0>\;
+ rxdata_out(254) <= \<const0>\;
+ rxdata_out(253) <= \<const0>\;
+ rxdata_out(252) <= \<const0>\;
+ rxdata_out(251) <= \<const0>\;
+ rxdata_out(250) <= \<const0>\;
+ rxdata_out(249) <= \<const0>\;
+ rxdata_out(248) <= \<const0>\;
+ rxdata_out(247) <= \<const0>\;
+ rxdata_out(246) <= \<const0>\;
+ rxdata_out(245) <= \<const0>\;
+ rxdata_out(244) <= \<const0>\;
+ rxdata_out(243) <= \<const0>\;
+ rxdata_out(242) <= \<const0>\;
+ rxdata_out(241) <= \<const0>\;
+ rxdata_out(240) <= \<const0>\;
+ rxdata_out(239) <= \<const0>\;
+ rxdata_out(238) <= \<const0>\;
+ rxdata_out(237) <= \<const0>\;
+ rxdata_out(236) <= \<const0>\;
+ rxdata_out(235) <= \<const0>\;
+ rxdata_out(234) <= \<const0>\;
+ rxdata_out(233) <= \<const0>\;
+ rxdata_out(232) <= \<const0>\;
+ rxdata_out(231) <= \<const0>\;
+ rxdata_out(230) <= \<const0>\;
+ rxdata_out(229) <= \<const0>\;
+ rxdata_out(228) <= \<const0>\;
+ rxdata_out(227) <= \<const0>\;
+ rxdata_out(226) <= \<const0>\;
+ rxdata_out(225) <= \<const0>\;
+ rxdata_out(224) <= \<const0>\;
+ rxdata_out(223) <= \<const0>\;
+ rxdata_out(222) <= \<const0>\;
+ rxdata_out(221) <= \<const0>\;
+ rxdata_out(220) <= \<const0>\;
+ rxdata_out(219) <= \<const0>\;
+ rxdata_out(218) <= \<const0>\;
+ rxdata_out(217) <= \<const0>\;
+ rxdata_out(216) <= \<const0>\;
+ rxdata_out(215) <= \<const0>\;
+ rxdata_out(214) <= \<const0>\;
+ rxdata_out(213) <= \<const0>\;
+ rxdata_out(212) <= \<const0>\;
+ rxdata_out(211) <= \<const0>\;
+ rxdata_out(210) <= \<const0>\;
+ rxdata_out(209) <= \<const0>\;
+ rxdata_out(208) <= \<const0>\;
+ rxdata_out(207) <= \<const0>\;
+ rxdata_out(206) <= \<const0>\;
+ rxdata_out(205) <= \<const0>\;
+ rxdata_out(204) <= \<const0>\;
+ rxdata_out(203) <= \<const0>\;
+ rxdata_out(202) <= \<const0>\;
+ rxdata_out(201) <= \<const0>\;
+ rxdata_out(200) <= \<const0>\;
+ rxdata_out(199) <= \<const0>\;
+ rxdata_out(198) <= \<const0>\;
+ rxdata_out(197) <= \<const0>\;
+ rxdata_out(196) <= \<const0>\;
+ rxdata_out(195) <= \<const0>\;
+ rxdata_out(194) <= \<const0>\;
+ rxdata_out(193) <= \<const0>\;
+ rxdata_out(192) <= \<const0>\;
+ rxdata_out(191) <= \<const0>\;
+ rxdata_out(190) <= \<const0>\;
+ rxdata_out(189) <= \<const0>\;
+ rxdata_out(188) <= \<const0>\;
+ rxdata_out(187) <= \<const0>\;
+ rxdata_out(186) <= \<const0>\;
+ rxdata_out(185) <= \<const0>\;
+ rxdata_out(184) <= \<const0>\;
+ rxdata_out(183) <= \<const0>\;
+ rxdata_out(182) <= \<const0>\;
+ rxdata_out(181) <= \<const0>\;
+ rxdata_out(180) <= \<const0>\;
+ rxdata_out(179) <= \<const0>\;
+ rxdata_out(178) <= \<const0>\;
+ rxdata_out(177) <= \<const0>\;
+ rxdata_out(176) <= \<const0>\;
+ rxdata_out(175) <= \<const0>\;
+ rxdata_out(174) <= \<const0>\;
+ rxdata_out(173) <= \<const0>\;
+ rxdata_out(172) <= \<const0>\;
+ rxdata_out(171) <= \<const0>\;
+ rxdata_out(170) <= \<const0>\;
+ rxdata_out(169) <= \<const0>\;
+ rxdata_out(168) <= \<const0>\;
+ rxdata_out(167) <= \<const0>\;
+ rxdata_out(166) <= \<const0>\;
+ rxdata_out(165) <= \<const0>\;
+ rxdata_out(164) <= \<const0>\;
+ rxdata_out(163) <= \<const0>\;
+ rxdata_out(162) <= \<const0>\;
+ rxdata_out(161) <= \<const0>\;
+ rxdata_out(160) <= \<const0>\;
+ rxdata_out(159) <= \<const0>\;
+ rxdata_out(158) <= \<const0>\;
+ rxdata_out(157) <= \<const0>\;
+ rxdata_out(156) <= \<const0>\;
+ rxdata_out(155) <= \<const0>\;
+ rxdata_out(154) <= \<const0>\;
+ rxdata_out(153) <= \<const0>\;
+ rxdata_out(152) <= \<const0>\;
+ rxdata_out(151) <= \<const0>\;
+ rxdata_out(150) <= \<const0>\;
+ rxdata_out(149) <= \<const0>\;
+ rxdata_out(148) <= \<const0>\;
+ rxdata_out(147) <= \<const0>\;
+ rxdata_out(146) <= \<const0>\;
+ rxdata_out(145) <= \<const0>\;
+ rxdata_out(144) <= \<const0>\;
+ rxdata_out(143) <= \<const0>\;
+ rxdata_out(142) <= \<const0>\;
+ rxdata_out(141) <= \<const0>\;
+ rxdata_out(140) <= \<const0>\;
+ rxdata_out(139) <= \<const0>\;
+ rxdata_out(138) <= \<const0>\;
+ rxdata_out(137) <= \<const0>\;
+ rxdata_out(136) <= \<const0>\;
+ rxdata_out(135) <= \<const0>\;
+ rxdata_out(134) <= \<const0>\;
+ rxdata_out(133) <= \<const0>\;
+ rxdata_out(132) <= \<const0>\;
+ rxdata_out(131) <= \<const0>\;
+ rxdata_out(130) <= \<const0>\;
+ rxdata_out(129) <= \<const0>\;
+ rxdata_out(128) <= \<const0>\;
+ rxdata_out(127) <= \<const0>\;
+ rxdata_out(126) <= \<const0>\;
+ rxdata_out(125) <= \<const0>\;
+ rxdata_out(124) <= \<const0>\;
+ rxdata_out(123) <= \<const0>\;
+ rxdata_out(122) <= \<const0>\;
+ rxdata_out(121) <= \<const0>\;
+ rxdata_out(120) <= \<const0>\;
+ rxdata_out(119) <= \<const0>\;
+ rxdata_out(118) <= \<const0>\;
+ rxdata_out(117) <= \<const0>\;
+ rxdata_out(116) <= \<const0>\;
+ rxdata_out(115) <= \<const0>\;
+ rxdata_out(114) <= \<const0>\;
+ rxdata_out(113) <= \<const0>\;
+ rxdata_out(112) <= \<const0>\;
+ rxdata_out(111) <= \<const0>\;
+ rxdata_out(110) <= \<const0>\;
+ rxdata_out(109) <= \<const0>\;
+ rxdata_out(108) <= \<const0>\;
+ rxdata_out(107) <= \<const0>\;
+ rxdata_out(106) <= \<const0>\;
+ rxdata_out(105) <= \<const0>\;
+ rxdata_out(104) <= \<const0>\;
+ rxdata_out(103) <= \<const0>\;
+ rxdata_out(102) <= \<const0>\;
+ rxdata_out(101) <= \<const0>\;
+ rxdata_out(100) <= \<const0>\;
+ rxdata_out(99) <= \<const0>\;
+ rxdata_out(98) <= \<const0>\;
+ rxdata_out(97) <= \<const0>\;
+ rxdata_out(96) <= \<const0>\;
+ rxdata_out(95) <= \<const0>\;
+ rxdata_out(94) <= \<const0>\;
+ rxdata_out(93) <= \<const0>\;
+ rxdata_out(92) <= \<const0>\;
+ rxdata_out(91) <= \<const0>\;
+ rxdata_out(90) <= \<const0>\;
+ rxdata_out(89) <= \<const0>\;
+ rxdata_out(88) <= \<const0>\;
+ rxdata_out(87) <= \<const0>\;
+ rxdata_out(86) <= \<const0>\;
+ rxdata_out(85) <= \<const0>\;
+ rxdata_out(84) <= \<const0>\;
+ rxdata_out(83) <= \<const0>\;
+ rxdata_out(82) <= \<const0>\;
+ rxdata_out(81) <= \<const0>\;
+ rxdata_out(80) <= \<const0>\;
+ rxdata_out(79) <= \<const0>\;
+ rxdata_out(78) <= \<const0>\;
+ rxdata_out(77) <= \<const0>\;
+ rxdata_out(76) <= \<const0>\;
+ rxdata_out(75) <= \<const0>\;
+ rxdata_out(74) <= \<const0>\;
+ rxdata_out(73) <= \<const0>\;
+ rxdata_out(72) <= \<const0>\;
+ rxdata_out(71) <= \<const0>\;
+ rxdata_out(70) <= \<const0>\;
+ rxdata_out(69) <= \<const0>\;
+ rxdata_out(68) <= \<const0>\;
+ rxdata_out(67) <= \<const0>\;
+ rxdata_out(66) <= \<const0>\;
+ rxdata_out(65) <= \<const0>\;
+ rxdata_out(64) <= \<const0>\;
+ rxdata_out(63) <= \<const0>\;
+ rxdata_out(62) <= \<const0>\;
+ rxdata_out(61) <= \<const0>\;
+ rxdata_out(60) <= \<const0>\;
+ rxdata_out(59) <= \<const0>\;
+ rxdata_out(58) <= \<const0>\;
+ rxdata_out(57) <= \<const0>\;
+ rxdata_out(56) <= \<const0>\;
+ rxdata_out(55) <= \<const0>\;
+ rxdata_out(54) <= \<const0>\;
+ rxdata_out(53) <= \<const0>\;
+ rxdata_out(52) <= \<const0>\;
+ rxdata_out(51) <= \<const0>\;
+ rxdata_out(50) <= \<const0>\;
+ rxdata_out(49) <= \<const0>\;
+ rxdata_out(48) <= \<const0>\;
+ rxdata_out(47) <= \<const0>\;
+ rxdata_out(46) <= \<const0>\;
+ rxdata_out(45) <= \<const0>\;
+ rxdata_out(44) <= \<const0>\;
+ rxdata_out(43) <= \<const0>\;
+ rxdata_out(42) <= \<const0>\;
+ rxdata_out(41) <= \<const0>\;
+ rxdata_out(40) <= \<const0>\;
+ rxdata_out(39) <= \<const0>\;
+ rxdata_out(38) <= \<const0>\;
+ rxdata_out(37) <= \<const0>\;
+ rxdata_out(36) <= \<const0>\;
+ rxdata_out(35) <= \<const0>\;
+ rxdata_out(34) <= \<const0>\;
+ rxdata_out(33) <= \<const0>\;
+ rxdata_out(32) <= \<const0>\;
+ rxdata_out(31) <= \<const0>\;
+ rxdata_out(30) <= \<const0>\;
+ rxdata_out(29) <= \<const0>\;
+ rxdata_out(28) <= \<const0>\;
+ rxdata_out(27) <= \<const0>\;
+ rxdata_out(26) <= \<const0>\;
+ rxdata_out(25) <= \<const0>\;
+ rxdata_out(24) <= \<const0>\;
+ rxdata_out(23) <= \<const0>\;
+ rxdata_out(22) <= \<const0>\;
+ rxdata_out(21) <= \<const0>\;
+ rxdata_out(20) <= \<const0>\;
+ rxdata_out(19) <= \<const0>\;
+ rxdata_out(18) <= \<const0>\;
+ rxdata_out(17) <= \<const0>\;
+ rxdata_out(16) <= \<const0>\;
+ rxdata_out(15) <= \<const0>\;
+ rxdata_out(14) <= \<const0>\;
+ rxdata_out(13) <= \<const0>\;
+ rxdata_out(12) <= \<const0>\;
+ rxdata_out(11) <= \<const0>\;
+ rxdata_out(10) <= \<const0>\;
+ rxdata_out(9) <= \<const0>\;
+ rxdata_out(8) <= \<const0>\;
+ rxdata_out(7) <= \<const0>\;
+ rxdata_out(6) <= \<const0>\;
+ rxdata_out(5) <= \<const0>\;
+ rxdata_out(4) <= \<const0>\;
+ rxdata_out(3) <= \<const0>\;
+ rxdata_out(2) <= \<const0>\;
+ rxdata_out(1) <= \<const0>\;
+ rxdata_out(0) <= \<const0>\;
+ rxdataextendrsvd_out(31) <= \<const0>\;
+ rxdataextendrsvd_out(30) <= \<const0>\;
+ rxdataextendrsvd_out(29) <= \<const0>\;
+ rxdataextendrsvd_out(28) <= \<const0>\;
+ rxdataextendrsvd_out(27) <= \<const0>\;
+ rxdataextendrsvd_out(26) <= \<const0>\;
+ rxdataextendrsvd_out(25) <= \<const0>\;
+ rxdataextendrsvd_out(24) <= \<const0>\;
+ rxdataextendrsvd_out(23) <= \<const0>\;
+ rxdataextendrsvd_out(22) <= \<const0>\;
+ rxdataextendrsvd_out(21) <= \<const0>\;
+ rxdataextendrsvd_out(20) <= \<const0>\;
+ rxdataextendrsvd_out(19) <= \<const0>\;
+ rxdataextendrsvd_out(18) <= \<const0>\;
+ rxdataextendrsvd_out(17) <= \<const0>\;
+ rxdataextendrsvd_out(16) <= \<const0>\;
+ rxdataextendrsvd_out(15) <= \<const0>\;
+ rxdataextendrsvd_out(14) <= \<const0>\;
+ rxdataextendrsvd_out(13) <= \<const0>\;
+ rxdataextendrsvd_out(12) <= \<const0>\;
+ rxdataextendrsvd_out(11) <= \<const0>\;
+ rxdataextendrsvd_out(10) <= \<const0>\;
+ rxdataextendrsvd_out(9) <= \<const0>\;
+ rxdataextendrsvd_out(8) <= \<const0>\;
+ rxdataextendrsvd_out(7) <= \<const0>\;
+ rxdataextendrsvd_out(6) <= \<const0>\;
+ rxdataextendrsvd_out(5) <= \<const0>\;
+ rxdataextendrsvd_out(4) <= \<const0>\;
+ rxdataextendrsvd_out(3) <= \<const0>\;
+ rxdataextendrsvd_out(2) <= \<const0>\;
+ rxdataextendrsvd_out(1) <= \<const0>\;
+ rxdataextendrsvd_out(0) <= \<const0>\;
+ rxdatavalid_out(7) <= \<const0>\;
+ rxdatavalid_out(6) <= \<const0>\;
+ rxdatavalid_out(5) <= \<const0>\;
+ rxdatavalid_out(4) <= \<const0>\;
+ rxdatavalid_out(3) <= \<const0>\;
+ rxdatavalid_out(2) <= \<const0>\;
+ rxdatavalid_out(1) <= \<const0>\;
+ rxdatavalid_out(0) <= \<const0>\;
+ rxdlysresetdone_out(3) <= \<const0>\;
+ rxdlysresetdone_out(2) <= \<const0>\;
+ rxdlysresetdone_out(1) <= \<const0>\;
+ rxdlysresetdone_out(0) <= \<const0>\;
+ rxelecidle_out(3) <= \<const0>\;
+ rxelecidle_out(2) <= \<const0>\;
+ rxelecidle_out(1) <= \<const0>\;
+ rxelecidle_out(0) <= \<const0>\;
+ rxheader_out(23) <= \<const0>\;
+ rxheader_out(22) <= \<const0>\;
+ rxheader_out(21) <= \<const0>\;
+ rxheader_out(20) <= \<const0>\;
+ rxheader_out(19) <= \<const0>\;
+ rxheader_out(18) <= \<const0>\;
+ rxheader_out(17) <= \<const0>\;
+ rxheader_out(16) <= \<const0>\;
+ rxheader_out(15) <= \<const0>\;
+ rxheader_out(14) <= \<const0>\;
+ rxheader_out(13) <= \<const0>\;
+ rxheader_out(12) <= \<const0>\;
+ rxheader_out(11) <= \<const0>\;
+ rxheader_out(10) <= \<const0>\;
+ rxheader_out(9) <= \<const0>\;
+ rxheader_out(8) <= \<const0>\;
+ rxheader_out(7) <= \<const0>\;
+ rxheader_out(6) <= \<const0>\;
+ rxheader_out(5) <= \<const0>\;
+ rxheader_out(4) <= \<const0>\;
+ rxheader_out(3) <= \<const0>\;
+ rxheader_out(2) <= \<const0>\;
+ rxheader_out(1) <= \<const0>\;
+ rxheader_out(0) <= \<const0>\;
+ rxheadervalid_out(7) <= \<const0>\;
+ rxheadervalid_out(6) <= \<const0>\;
+ rxheadervalid_out(5) <= \<const0>\;
+ rxheadervalid_out(4) <= \<const0>\;
+ rxheadervalid_out(3) <= \<const0>\;
+ rxheadervalid_out(2) <= \<const0>\;
+ rxheadervalid_out(1) <= \<const0>\;
+ rxheadervalid_out(0) <= \<const0>\;
+ rxlfpstresetdet_out(0) <= \<const0>\;
+ rxlfpsu2lpexitdet_out(0) <= \<const0>\;
+ rxlfpsu3wakedet_out(0) <= \<const0>\;
+ rxmonitorout_out(27) <= \<const0>\;
+ rxmonitorout_out(26) <= \<const0>\;
+ rxmonitorout_out(25) <= \<const0>\;
+ rxmonitorout_out(24) <= \<const0>\;
+ rxmonitorout_out(23) <= \<const0>\;
+ rxmonitorout_out(22) <= \<const0>\;
+ rxmonitorout_out(21) <= \<const0>\;
+ rxmonitorout_out(20) <= \<const0>\;
+ rxmonitorout_out(19) <= \<const0>\;
+ rxmonitorout_out(18) <= \<const0>\;
+ rxmonitorout_out(17) <= \<const0>\;
+ rxmonitorout_out(16) <= \<const0>\;
+ rxmonitorout_out(15) <= \<const0>\;
+ rxmonitorout_out(14) <= \<const0>\;
+ rxmonitorout_out(13) <= \<const0>\;
+ rxmonitorout_out(12) <= \<const0>\;
+ rxmonitorout_out(11) <= \<const0>\;
+ rxmonitorout_out(10) <= \<const0>\;
+ rxmonitorout_out(9) <= \<const0>\;
+ rxmonitorout_out(8) <= \<const0>\;
+ rxmonitorout_out(7) <= \<const0>\;
+ rxmonitorout_out(6) <= \<const0>\;
+ rxmonitorout_out(5) <= \<const0>\;
+ rxmonitorout_out(4) <= \<const0>\;
+ rxmonitorout_out(3) <= \<const0>\;
+ rxmonitorout_out(2) <= \<const0>\;
+ rxmonitorout_out(1) <= \<const0>\;
+ rxmonitorout_out(0) <= \<const0>\;
+ rxosintdone_out(3) <= \<const0>\;
+ rxosintdone_out(2) <= \<const0>\;
+ rxosintdone_out(1) <= \<const0>\;
+ rxosintdone_out(0) <= \<const0>\;
+ rxosintstarted_out(3) <= \<const0>\;
+ rxosintstarted_out(2) <= \<const0>\;
+ rxosintstarted_out(1) <= \<const0>\;
+ rxosintstarted_out(0) <= \<const0>\;
+ rxosintstrobedone_out(3) <= \<const0>\;
+ rxosintstrobedone_out(2) <= \<const0>\;
+ rxosintstrobedone_out(1) <= \<const0>\;
+ rxosintstrobedone_out(0) <= \<const0>\;
+ rxosintstrobestarted_out(3) <= \<const0>\;
+ rxosintstrobestarted_out(2) <= \<const0>\;
+ rxosintstrobestarted_out(1) <= \<const0>\;
+ rxosintstrobestarted_out(0) <= \<const0>\;
+ rxoutclkfabric_out(3) <= \<const0>\;
+ rxoutclkfabric_out(2) <= \<const0>\;
+ rxoutclkfabric_out(1) <= \<const0>\;
+ rxoutclkfabric_out(0) <= \<const0>\;
+ rxoutclkpcs_out(3) <= \<const0>\;
+ rxoutclkpcs_out(2) <= \<const0>\;
+ rxoutclkpcs_out(1) <= \<const0>\;
+ rxoutclkpcs_out(0) <= \<const0>\;
+ rxphaligndone_out(3) <= \<const0>\;
+ rxphaligndone_out(2) <= \<const0>\;
+ rxphaligndone_out(1) <= \<const0>\;
+ rxphaligndone_out(0) <= \<const0>\;
+ rxphalignerr_out(3) <= \<const0>\;
+ rxphalignerr_out(2) <= \<const0>\;
+ rxphalignerr_out(1) <= \<const0>\;
+ rxphalignerr_out(0) <= \<const0>\;
+ rxprbserr_out(3) <= \<const0>\;
+ rxprbserr_out(2) <= \<const0>\;
+ rxprbserr_out(1) <= \<const0>\;
+ rxprbserr_out(0) <= \<const0>\;
+ rxprbslocked_out(3) <= \<const0>\;
+ rxprbslocked_out(2) <= \<const0>\;
+ rxprbslocked_out(1) <= \<const0>\;
+ rxprbslocked_out(0) <= \<const0>\;
+ rxprgdivresetdone_out(3) <= \<const0>\;
+ rxprgdivresetdone_out(2) <= \<const0>\;
+ rxprgdivresetdone_out(1) <= \<const0>\;
+ rxprgdivresetdone_out(0) <= \<const0>\;
+ rxqpisenn_out(3) <= \<const0>\;
+ rxqpisenn_out(2) <= \<const0>\;
+ rxqpisenn_out(1) <= \<const0>\;
+ rxqpisenn_out(0) <= \<const0>\;
+ rxqpisenp_out(3) <= \<const0>\;
+ rxqpisenp_out(2) <= \<const0>\;
+ rxqpisenp_out(1) <= \<const0>\;
+ rxqpisenp_out(0) <= \<const0>\;
+ rxrecclk0_sel_out(1) <= \<const0>\;
+ rxrecclk0_sel_out(0) <= \<const0>\;
+ rxrecclk0sel_out(0) <= \<const0>\;
+ rxrecclk1_sel_out(1) <= \<const0>\;
+ rxrecclk1_sel_out(0) <= \<const0>\;
+ rxrecclk1sel_out(0) <= \<const0>\;
+ rxrecclkout_out(3) <= \<const0>\;
+ rxrecclkout_out(2) <= \<const0>\;
+ rxrecclkout_out(1) <= \<const0>\;
+ rxrecclkout_out(0) <= \<const0>\;
+ rxsliderdy_out(3) <= \<const0>\;
+ rxsliderdy_out(2) <= \<const0>\;
+ rxsliderdy_out(1) <= \<const0>\;
+ rxsliderdy_out(0) <= \<const0>\;
+ rxslipdone_out(3) <= \<const0>\;
+ rxslipdone_out(2) <= \<const0>\;
+ rxslipdone_out(1) <= \<const0>\;
+ rxslipdone_out(0) <= \<const0>\;
+ rxslipoutclkrdy_out(3) <= \<const0>\;
+ rxslipoutclkrdy_out(2) <= \<const0>\;
+ rxslipoutclkrdy_out(1) <= \<const0>\;
+ rxslipoutclkrdy_out(0) <= \<const0>\;
+ rxslippmardy_out(3) <= \<const0>\;
+ rxslippmardy_out(2) <= \<const0>\;
+ rxslippmardy_out(1) <= \<const0>\;
+ rxslippmardy_out(0) <= \<const0>\;
+ rxstartofseq_out(7) <= \<const0>\;
+ rxstartofseq_out(6) <= \<const0>\;
+ rxstartofseq_out(5) <= \<const0>\;
+ rxstartofseq_out(4) <= \<const0>\;
+ rxstartofseq_out(3) <= \<const0>\;
+ rxstartofseq_out(2) <= \<const0>\;
+ rxstartofseq_out(1) <= \<const0>\;
+ rxstartofseq_out(0) <= \<const0>\;
+ rxstatus_out(11) <= \<const0>\;
+ rxstatus_out(10) <= \<const0>\;
+ rxstatus_out(9) <= \<const0>\;
+ rxstatus_out(8) <= \<const0>\;
+ rxstatus_out(7) <= \<const0>\;
+ rxstatus_out(6) <= \<const0>\;
+ rxstatus_out(5) <= \<const0>\;
+ rxstatus_out(4) <= \<const0>\;
+ rxstatus_out(3) <= \<const0>\;
+ rxstatus_out(2) <= \<const0>\;
+ rxstatus_out(1) <= \<const0>\;
+ rxstatus_out(0) <= \<const0>\;
+ rxsyncdone_out(3) <= \<const0>\;
+ rxsyncdone_out(2) <= \<const0>\;
+ rxsyncdone_out(1) <= \<const0>\;
+ rxsyncdone_out(0) <= \<const0>\;
+ rxsyncout_out(3) <= \<const0>\;
+ rxsyncout_out(2) <= \<const0>\;
+ rxsyncout_out(1) <= \<const0>\;
+ rxsyncout_out(0) <= \<const0>\;
+ rxvalid_out(3) <= \<const0>\;
+ rxvalid_out(2) <= \<const0>\;
+ rxvalid_out(1) <= \<const0>\;
+ rxvalid_out(0) <= \<const0>\;
+ sdm0finalout_out(0) <= \<const0>\;
+ sdm0testdata_out(0) <= \<const0>\;
+ sdm1finalout_out(0) <= \<const0>\;
+ sdm1testdata_out(0) <= \<const0>\;
+ tcongpo_out(0) <= \<const0>\;
+ tconrsvdout0_out(0) <= \<const0>\;
+ txbufstatus_out(7) <= \<const0>\;
+ txbufstatus_out(6) <= \<const0>\;
+ txbufstatus_out(5) <= \<const0>\;
+ txbufstatus_out(4) <= \<const0>\;
+ txbufstatus_out(3) <= \<const0>\;
+ txbufstatus_out(2) <= \<const0>\;
+ txbufstatus_out(1) <= \<const0>\;
+ txbufstatus_out(0) <= \<const0>\;
+ txcomfinish_out(3) <= \<const0>\;
+ txcomfinish_out(2) <= \<const0>\;
+ txcomfinish_out(1) <= \<const0>\;
+ txcomfinish_out(0) <= \<const0>\;
+ txdccdone_out(0) <= \<const0>\;
+ txdlysresetdone_out(3) <= \<const0>\;
+ txdlysresetdone_out(2) <= \<const0>\;
+ txdlysresetdone_out(1) <= \<const0>\;
+ txdlysresetdone_out(0) <= \<const0>\;
+ txoutclkfabric_out(3) <= \<const0>\;
+ txoutclkfabric_out(2) <= \<const0>\;
+ txoutclkfabric_out(1) <= \<const0>\;
+ txoutclkfabric_out(0) <= \<const0>\;
+ txoutclkpcs_out(3) <= \<const0>\;
+ txoutclkpcs_out(2) <= \<const0>\;
+ txoutclkpcs_out(1) <= \<const0>\;
+ txoutclkpcs_out(0) <= \<const0>\;
+ txphaligndone_out(3) <= \<const0>\;
+ txphaligndone_out(2) <= \<const0>\;
+ txphaligndone_out(1) <= \<const0>\;
+ txphaligndone_out(0) <= \<const0>\;
+ txphinitdone_out(3) <= \<const0>\;
+ txphinitdone_out(2) <= \<const0>\;
+ txphinitdone_out(1) <= \<const0>\;
+ txphinitdone_out(0) <= \<const0>\;
+ txqpisenn_out(3) <= \<const0>\;
+ txqpisenn_out(2) <= \<const0>\;
+ txqpisenn_out(1) <= \<const0>\;
+ txqpisenn_out(0) <= \<const0>\;
+ txqpisenp_out(3) <= \<const0>\;
+ txqpisenp_out(2) <= \<const0>\;
+ txqpisenp_out(1) <= \<const0>\;
+ txqpisenp_out(0) <= \<const0>\;
+ txratedone_out(3) <= \<const0>\;
+ txratedone_out(2) <= \<const0>\;
+ txratedone_out(1) <= \<const0>\;
+ txratedone_out(0) <= \<const0>\;
+ txsyncdone_out(3) <= \<const0>\;
+ txsyncdone_out(2) <= \<const0>\;
+ txsyncdone_out(1) <= \<const0>\;
+ txsyncdone_out(0) <= \<const0>\;
+ txsyncout_out(3) <= \<const0>\;
+ txsyncout_out(2) <= \<const0>\;
+ txsyncout_out(1) <= \<const0>\;
+ txsyncout_out(0) <= \<const0>\;
+ ubdaddr_out(0) <= \<const0>\;
+ ubden_out(0) <= \<const0>\;
+ ubdi_out(0) <= \<const0>\;
+ ubdwe_out(0) <= \<const0>\;
+ ubmdmtdo_out(0) <= \<const0>\;
+ ubrsvdout_out(0) <= \<const0>\;
+ ubtxuart_out(0) <= \<const0>\;
+GND: unisim.vcomponents.GND
+ port map (
+ G => \<const0>\
+ );
+\gen_gtwizard_gthe3_top.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_gthe3_inst\: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_gthe3
+ port map (
+ cplllock_out(3 downto 0) => cplllock_out(3 downto 0),
+ drpclk_in(3 downto 0) => drpclk_in(3 downto 0),
+ gthrxn_in(3 downto 0) => gthrxn_in(3 downto 0),
+ gthrxp_in(3 downto 0) => gthrxp_in(3 downto 0),
+ gthtxn_out(3 downto 0) => gthtxn_out(3 downto 0),
+ gthtxp_out(3 downto 0) => gthtxp_out(3 downto 0),
+ gtpowergood_out(3 downto 0) => gtpowergood_out(3 downto 0),
+ gtrefclk01_in(0) => gtrefclk01_in(0),
+ gtrefclk0_in(3 downto 0) => gtrefclk0_in(3 downto 0),
+ gtwiz_buffbypass_tx_done_out(0) => gtwiz_buffbypass_tx_done_out(0),
+ gtwiz_buffbypass_tx_error_out(0) => gtwiz_buffbypass_tx_error_out(0),
+ gtwiz_buffbypass_tx_reset_in(0) => gtwiz_buffbypass_tx_reset_in(0),
+ gtwiz_buffbypass_tx_start_user_in(0) => gtwiz_buffbypass_tx_start_user_in(0),
+ gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_rx_cdr_stable_out(0) => gtwiz_reset_rx_cdr_stable_out(0),
+ gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0),
+ gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0),
+ gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0),
+ gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0),
+ gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0),
+ gtwiz_reset_tx_pll_and_datapath_in(0) => gtwiz_reset_tx_pll_and_datapath_in(0),
+ gtwiz_userclk_rx_active_in(0) => gtwiz_userclk_rx_active_in(0),
+ gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0),
+ gtwiz_userdata_rx_out(63 downto 0) => gtwiz_userdata_rx_out(63 downto 0),
+ gtwiz_userdata_tx_in(127 downto 0) => gtwiz_userdata_tx_in(127 downto 0),
+ loopback_in(11 downto 0) => loopback_in(11 downto 0),
+ qpll0fbclklost_out(0) => qpll0fbclklost_out(0),
+ qpll0lock_out(0) => qpll0lock_out(0),
+ qpll1fbclklost_out(0) => qpll1fbclklost_out(0),
+ qpll1lock_out(0) => qpll1lock_out(0),
+ qpll1outclk_out(0) => qpll1outclk_out(0),
+ qpll1outrefclk_out(0) => qpll1outrefclk_out(0),
+ rxcdrhold_in(3 downto 0) => rxcdrhold_in(3 downto 0),
+ rxcdrlock_out(3 downto 0) => rxcdrlock_out(3 downto 0),
+ rxoutclk_out(3 downto 0) => rxoutclk_out(3 downto 0),
+ rxpmaresetdone_out(3 downto 0) => rxpmaresetdone_out(3 downto 0),
+ rxpolarity_in(3 downto 0) => rxpolarity_in(3 downto 0),
+ rxratedone_out(3 downto 0) => rxratedone_out(3 downto 0),
+ rxresetdone_out(3 downto 0) => rxresetdone_out(3 downto 0),
+ rxslide_in(3 downto 0) => rxslide_in(3 downto 0),
+ rxusrclk2_in(3 downto 0) => rxusrclk2_in(3 downto 0),
+ rxusrclk_in(3 downto 0) => rxusrclk_in(3 downto 0),
+ txoutclk_out(3 downto 0) => txoutclk_out(3 downto 0),
+ txpmaresetdone_out(3 downto 0) => txpmaresetdone_out(3 downto 0),
+ txpolarity_in(3 downto 0) => txpolarity_in(3 downto 0),
+ txprgdivresetdone_out(3 downto 0) => txprgdivresetdone_out(3 downto 0),
+ txresetdone_out(3 downto 0) => txresetdone_out(3 downto 0),
+ txusrclk2_in(3 downto 0) => txusrclk2_in(3 downto 0),
+ txusrclk_in(3 downto 0) => txusrclk_in(3 downto 0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH is
+ port (
+ gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 127 downto 0 );
+ gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
+ gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
+ drpclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxn_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthrxp_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ loopback_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ rxcdrhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxslide_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ txusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ cplllock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxn_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gthtxp_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ gtpowergood_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxcdrlock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxratedone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ rxresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txprgdivresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ txresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 )
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH : entity is true;
+ attribute CHECK_LICENSE_TYPE : string;
+ attribute CHECK_LICENSE_TYPE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH : entity is "KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH,KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top,{}";
+ attribute DowngradeIPIdentifiedWarnings : string;
+ attribute DowngradeIPIdentifiedWarnings of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH : entity is "yes";
+ attribute X_CORE_INFO : string;
+ attribute X_CORE_INFO of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH : entity is "KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top,Vivado 2024.1";
+end KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH;
+
+architecture STRUCTURE of KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH is
+ signal NLW_inst_bufgtce_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_bufgtcemask_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_bufgtdiv_out_UNCONNECTED : STD_LOGIC_VECTOR ( 35 downto 0 );
+ signal NLW_inst_bufgtreset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_bufgtrstmask_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_cpllfbclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_cpllrefclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_dmonitorout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 67 downto 0 );
+ signal NLW_inst_dmonitoroutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_drpdo_common_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+ signal NLW_inst_drpdo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_inst_drprdy_common_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_drprdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_eyescandataerror_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_gtrefclkmonitor_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_reset_qpll0reset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_rx_active_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_rx_srcclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_rx_usrclk2_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_rx_usrclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_tx_active_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_tx_srcclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_tx_usrclk2_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtwiz_userclk_tx_usrclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtytxn_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_gtytxp_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_pcierategen3_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_pcierateidle_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_pcierateqpllpd_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_pcierateqpllreset_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_pciesynctxsyncdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_pcieusergen3rdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_pcieuserphystatusrst_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_pcieuserratestart_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_pcsrsvdout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
+ signal NLW_inst_phystatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_pinrsrvdas_out_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_inst_pmarsvdout0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_pmarsvdout1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_powerpresent_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_qpll0outclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_qpll0outrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_qpll0refclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_qpll1refclklost_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_qplldmonitor0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_qplldmonitor1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_refclkoutmonitor0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_refclkoutmonitor1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_resetexception_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxbufstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_rxbyteisaligned_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxbyterealign_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxcdrphdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxchanbondseq_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxchanisaligned_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxchanrealign_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxchbondo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
+ signal NLW_inst_rxckcaldone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_rxclkcorcnt_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_rxcominitdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxcommadet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxcomsasdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxcomwakedet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxctrl0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_inst_rxctrl1_out_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_inst_rxctrl2_out_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_inst_rxctrl3_out_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_inst_rxdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 511 downto 0 );
+ signal NLW_inst_rxdataextendrsvd_out_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_inst_rxdatavalid_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_rxdlysresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxelecidle_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxheader_out_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
+ signal NLW_inst_rxheadervalid_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_rxlfpstresetdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_rxmonitorout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 27 downto 0 );
+ signal NLW_inst_rxosintdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxosintstarted_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxosintstrobedone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxosintstrobestarted_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxoutclkfabric_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxoutclkpcs_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxphaligndone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxphalignerr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxprbserr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxprbslocked_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxprgdivresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxqpisenn_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxqpisenp_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxrecclk0_sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_rxrecclk0sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_rxrecclk1_sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_inst_rxrecclk1sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_rxrecclkout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxsliderdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxslipdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxslipoutclkrdy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxslippmardy_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxstartofseq_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_rxstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal NLW_inst_rxsyncdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxsyncout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_rxvalid_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_sdm0finalout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_sdm0testdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_sdm1finalout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_sdm1testdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_tcongpo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_tconrsvdout0_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_txbufstatus_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_inst_txcomfinish_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txdccdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_txdlysresetdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txoutclkfabric_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txoutclkpcs_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txphaligndone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txphinitdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txqpisenn_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txqpisenp_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txratedone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txsyncdone_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_txsyncout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_inst_ubdaddr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_ubden_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_ubdi_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_ubdwe_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_ubmdmtdo_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_ubrsvdout_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_ubtxuart_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ attribute C_CHANNEL_ENABLE : string;
+ attribute C_CHANNEL_ENABLE of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100000000";
+ attribute C_COMMON_SCALING_FACTOR : integer;
+ attribute C_COMMON_SCALING_FACTOR of inst : label is 1;
+ attribute C_CPLL_VCO_FREQUENCY : string;
+ attribute C_CPLL_VCO_FREQUENCY of inst : label is "2560.000000";
+ attribute C_ENABLE_COMMON_USRCLK : integer;
+ attribute C_ENABLE_COMMON_USRCLK of inst : label is 0;
+ attribute C_FORCE_COMMONS : integer;
+ attribute C_FORCE_COMMONS of inst : label is 0;
+ attribute C_FREERUN_FREQUENCY : string;
+ attribute C_FREERUN_FREQUENCY of inst : label is "200.000000";
+ attribute C_GT_REV : integer;
+ attribute C_GT_REV of inst : label is 17;
+ attribute C_GT_TYPE : integer;
+ attribute C_GT_TYPE of inst : label is 0;
+ attribute C_INCLUDE_CPLL_CAL : integer;
+ attribute C_INCLUDE_CPLL_CAL of inst : label is 2;
+ attribute C_LOCATE_COMMON : integer;
+ attribute C_LOCATE_COMMON of inst : label is 0;
+ attribute C_LOCATE_IN_SYSTEM_IBERT_CORE : integer;
+ attribute C_LOCATE_IN_SYSTEM_IBERT_CORE of inst : label is 2;
+ attribute C_LOCATE_RESET_CONTROLLER : integer;
+ attribute C_LOCATE_RESET_CONTROLLER of inst : label is 0;
+ attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER : integer;
+ attribute C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER of inst : label is 0;
+ attribute C_LOCATE_RX_USER_CLOCKING : integer;
+ attribute C_LOCATE_RX_USER_CLOCKING of inst : label is 1;
+ attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER : integer;
+ attribute C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER of inst : label is 0;
+ attribute C_LOCATE_TX_USER_CLOCKING : integer;
+ attribute C_LOCATE_TX_USER_CLOCKING of inst : label is 1;
+ attribute C_LOCATE_USER_DATA_WIDTH_SIZING : integer;
+ attribute C_LOCATE_USER_DATA_WIDTH_SIZING of inst : label is 0;
+ attribute C_PCIE_CORECLK_FREQ : integer;
+ attribute C_PCIE_CORECLK_FREQ of inst : label is 250;
+ attribute C_PCIE_ENABLE : integer;
+ attribute C_PCIE_ENABLE of inst : label is 0;
+ attribute C_RESET_CONTROLLER_INSTANCE_CTRL : integer;
+ attribute C_RESET_CONTROLLER_INSTANCE_CTRL of inst : label is 0;
+ attribute C_RESET_SEQUENCE_INTERVAL : integer;
+ attribute C_RESET_SEQUENCE_INTERVAL of inst : label is 0;
+ attribute C_RX_BUFFBYPASS_MODE : integer;
+ attribute C_RX_BUFFBYPASS_MODE of inst : label is 0;
+ attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL : integer;
+ attribute C_RX_BUFFER_BYPASS_INSTANCE_CTRL of inst : label is 0;
+ attribute C_RX_BUFFER_MODE : integer;
+ attribute C_RX_BUFFER_MODE of inst : label is 1;
+ attribute C_RX_CB_DISP : string;
+ attribute C_RX_CB_DISP of inst : label is "8'b00000000";
+ attribute C_RX_CB_K : string;
+ attribute C_RX_CB_K of inst : label is "8'b00000000";
+ attribute C_RX_CB_LEN_SEQ : integer;
+ attribute C_RX_CB_LEN_SEQ of inst : label is 1;
+ attribute C_RX_CB_MAX_LEVEL : integer;
+ attribute C_RX_CB_MAX_LEVEL of inst : label is 2;
+ attribute C_RX_CB_NUM_SEQ : integer;
+ attribute C_RX_CB_NUM_SEQ of inst : label is 0;
+ attribute C_RX_CB_VAL : string;
+ attribute C_RX_CB_VAL of inst : label is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_RX_CC_DISP : string;
+ attribute C_RX_CC_DISP of inst : label is "8'b00000000";
+ attribute C_RX_CC_ENABLE : integer;
+ attribute C_RX_CC_ENABLE of inst : label is 0;
+ attribute C_RX_CC_K : string;
+ attribute C_RX_CC_K of inst : label is "8'b00000000";
+ attribute C_RX_CC_LEN_SEQ : integer;
+ attribute C_RX_CC_LEN_SEQ of inst : label is 1;
+ attribute C_RX_CC_NUM_SEQ : integer;
+ attribute C_RX_CC_NUM_SEQ of inst : label is 0;
+ attribute C_RX_CC_PERIODICITY : integer;
+ attribute C_RX_CC_PERIODICITY of inst : label is 5000;
+ attribute C_RX_CC_VAL : string;
+ attribute C_RX_CC_VAL of inst : label is "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_RX_COMMA_M_ENABLE : integer;
+ attribute C_RX_COMMA_M_ENABLE of inst : label is 0;
+ attribute C_RX_COMMA_M_VAL : string;
+ attribute C_RX_COMMA_M_VAL of inst : label is "10'b1010000011";
+ attribute C_RX_COMMA_P_ENABLE : integer;
+ attribute C_RX_COMMA_P_ENABLE of inst : label is 0;
+ attribute C_RX_COMMA_P_VAL : string;
+ attribute C_RX_COMMA_P_VAL of inst : label is "10'b0101111100";
+ attribute C_RX_DATA_DECODING : integer;
+ attribute C_RX_DATA_DECODING of inst : label is 0;
+ attribute C_RX_ENABLE : integer;
+ attribute C_RX_ENABLE of inst : label is 1;
+ attribute C_RX_INT_DATA_WIDTH : integer;
+ attribute C_RX_INT_DATA_WIDTH of inst : label is 16;
+ attribute C_RX_LINE_RATE : string;
+ attribute C_RX_LINE_RATE of inst : label is "5.120000";
+ attribute C_RX_MASTER_CHANNEL_IDX : integer;
+ attribute C_RX_MASTER_CHANNEL_IDX of inst : label is 8;
+ attribute C_RX_OUTCLK_BUFG_GT_DIV : integer;
+ attribute C_RX_OUTCLK_BUFG_GT_DIV of inst : label is 1;
+ attribute C_RX_OUTCLK_FREQUENCY : string;
+ attribute C_RX_OUTCLK_FREQUENCY of inst : label is "320.000000";
+ attribute C_RX_OUTCLK_SOURCE : integer;
+ attribute C_RX_OUTCLK_SOURCE of inst : label is 1;
+ attribute C_RX_PLL_TYPE : integer;
+ attribute C_RX_PLL_TYPE of inst : label is 2;
+ attribute C_RX_RECCLK_OUTPUT : string;
+ attribute C_RX_RECCLK_OUTPUT of inst : label is "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_RX_REFCLK_FREQUENCY : string;
+ attribute C_RX_REFCLK_FREQUENCY of inst : label is "320.000000";
+ attribute C_RX_SLIDE_MODE : integer;
+ attribute C_RX_SLIDE_MODE of inst : label is 0;
+ attribute C_RX_USER_CLOCKING_CONTENTS : integer;
+ attribute C_RX_USER_CLOCKING_CONTENTS of inst : label is 0;
+ attribute C_RX_USER_CLOCKING_INSTANCE_CTRL : integer;
+ attribute C_RX_USER_CLOCKING_INSTANCE_CTRL of inst : label is 0;
+ attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer;
+ attribute C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of inst : label is 1;
+ attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer;
+ attribute C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of inst : label is 1;
+ attribute C_RX_USER_CLOCKING_SOURCE : integer;
+ attribute C_RX_USER_CLOCKING_SOURCE of inst : label is 0;
+ attribute C_RX_USER_DATA_WIDTH : integer;
+ attribute C_RX_USER_DATA_WIDTH of inst : label is 16;
+ attribute C_RX_USRCLK2_FREQUENCY : string;
+ attribute C_RX_USRCLK2_FREQUENCY of inst : label is "320.000000";
+ attribute C_RX_USRCLK_FREQUENCY : string;
+ attribute C_RX_USRCLK_FREQUENCY of inst : label is "320.000000";
+ attribute C_SECONDARY_QPLL_ENABLE : integer;
+ attribute C_SECONDARY_QPLL_ENABLE of inst : label is 0;
+ attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY : string;
+ attribute C_SECONDARY_QPLL_REFCLK_FREQUENCY of inst : label is "257.812500";
+ attribute C_SIM_CPLL_CAL_BYPASS : integer;
+ attribute C_SIM_CPLL_CAL_BYPASS of inst : label is 1;
+ attribute C_TOTAL_NUM_CHANNELS : integer;
+ attribute C_TOTAL_NUM_CHANNELS of inst : label is 4;
+ attribute C_TOTAL_NUM_COMMONS : integer;
+ attribute C_TOTAL_NUM_COMMONS of inst : label is 1;
+ attribute C_TOTAL_NUM_COMMONS_EXAMPLE : integer;
+ attribute C_TOTAL_NUM_COMMONS_EXAMPLE of inst : label is 0;
+ attribute C_TXPROGDIV_FREQ_ENABLE : integer;
+ attribute C_TXPROGDIV_FREQ_ENABLE of inst : label is 0;
+ attribute C_TXPROGDIV_FREQ_SOURCE : integer;
+ attribute C_TXPROGDIV_FREQ_SOURCE of inst : label is 1;
+ attribute C_TXPROGDIV_FREQ_VAL : string;
+ attribute C_TXPROGDIV_FREQ_VAL of inst : label is "320.000000";
+ attribute C_TX_BUFFBYPASS_MODE : integer;
+ attribute C_TX_BUFFBYPASS_MODE of inst : label is 0;
+ attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL : integer;
+ attribute C_TX_BUFFER_BYPASS_INSTANCE_CTRL of inst : label is 0;
+ attribute C_TX_BUFFER_MODE : integer;
+ attribute C_TX_BUFFER_MODE of inst : label is 0;
+ attribute C_TX_DATA_ENCODING : integer;
+ attribute C_TX_DATA_ENCODING of inst : label is 0;
+ attribute C_TX_ENABLE : integer;
+ attribute C_TX_ENABLE of inst : label is 1;
+ attribute C_TX_INT_DATA_WIDTH : integer;
+ attribute C_TX_INT_DATA_WIDTH of inst : label is 32;
+ attribute C_TX_LINE_RATE : string;
+ attribute C_TX_LINE_RATE of inst : label is "10.240000";
+ attribute C_TX_MASTER_CHANNEL_IDX : integer;
+ attribute C_TX_MASTER_CHANNEL_IDX of inst : label is 8;
+ attribute C_TX_OUTCLK_BUFG_GT_DIV : integer;
+ attribute C_TX_OUTCLK_BUFG_GT_DIV of inst : label is 1;
+ attribute C_TX_OUTCLK_FREQUENCY : string;
+ attribute C_TX_OUTCLK_FREQUENCY of inst : label is "320.000000";
+ attribute C_TX_OUTCLK_SOURCE : integer;
+ attribute C_TX_OUTCLK_SOURCE of inst : label is 4;
+ attribute C_TX_PLL_TYPE : integer;
+ attribute C_TX_PLL_TYPE of inst : label is 1;
+ attribute C_TX_REFCLK_FREQUENCY : string;
+ attribute C_TX_REFCLK_FREQUENCY of inst : label is "240.000000";
+ attribute C_TX_USER_CLOCKING_CONTENTS : integer;
+ attribute C_TX_USER_CLOCKING_CONTENTS of inst : label is 0;
+ attribute C_TX_USER_CLOCKING_INSTANCE_CTRL : integer;
+ attribute C_TX_USER_CLOCKING_INSTANCE_CTRL of inst : label is 0;
+ attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK : integer;
+ attribute C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK of inst : label is 1;
+ attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 : integer;
+ attribute C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 of inst : label is 1;
+ attribute C_TX_USER_CLOCKING_SOURCE : integer;
+ attribute C_TX_USER_CLOCKING_SOURCE of inst : label is 0;
+ attribute C_TX_USER_DATA_WIDTH : integer;
+ attribute C_TX_USER_DATA_WIDTH of inst : label is 32;
+ attribute C_TX_USRCLK2_FREQUENCY : string;
+ attribute C_TX_USRCLK2_FREQUENCY of inst : label is "320.000000";
+ attribute C_TX_USRCLK_FREQUENCY : string;
+ attribute C_TX_USRCLK_FREQUENCY of inst : label is "320.000000";
+ attribute C_USER_GTPOWERGOOD_DELAY_EN : integer;
+ attribute C_USER_GTPOWERGOOD_DELAY_EN of inst : label is 0;
+begin
+inst: entity work.KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH_gtwizard_top
+ port map (
+ bgbypassb_in(0) => '1',
+ bgmonitorenb_in(0) => '1',
+ bgpdb_in(0) => '1',
+ bgrcalovrd_in(4 downto 0) => B"11111",
+ bgrcalovrdenb_in(0) => '1',
+ bufgtce_out(11 downto 0) => NLW_inst_bufgtce_out_UNCONNECTED(11 downto 0),
+ bufgtcemask_out(11 downto 0) => NLW_inst_bufgtcemask_out_UNCONNECTED(11 downto 0),
+ bufgtdiv_out(35 downto 0) => NLW_inst_bufgtdiv_out_UNCONNECTED(35 downto 0),
+ bufgtreset_out(11 downto 0) => NLW_inst_bufgtreset_out_UNCONNECTED(11 downto 0),
+ bufgtrstmask_out(11 downto 0) => NLW_inst_bufgtrstmask_out_UNCONNECTED(11 downto 0),
+ cdrstepdir_in(0) => '0',
+ cdrstepsq_in(0) => '0',
+ cdrstepsx_in(0) => '0',
+ cfgreset_in(3 downto 0) => B"0000",
+ clkrsvd0_in(3 downto 0) => B"0000",
+ clkrsvd1_in(3 downto 0) => B"0000",
+ cpllfbclklost_out(3 downto 0) => NLW_inst_cpllfbclklost_out_UNCONNECTED(3 downto 0),
+ cpllfreqlock_in(0) => '0',
+ cplllock_out(3 downto 0) => cplllock_out(3 downto 0),
+ cplllockdetclk_in(3 downto 0) => B"0000",
+ cplllocken_in(3 downto 0) => B"1111",
+ cpllpd_in(3 downto 0) => B"0000",
+ cpllrefclklost_out(3 downto 0) => NLW_inst_cpllrefclklost_out_UNCONNECTED(3 downto 0),
+ cpllrefclksel_in(11 downto 0) => B"001001001001",
+ cpllreset_in(3 downto 0) => B"0000",
+ dmonfiforeset_in(3 downto 0) => B"0000",
+ dmonitorclk_in(3 downto 0) => B"0000",
+ dmonitorout_out(67 downto 0) => NLW_inst_dmonitorout_out_UNCONNECTED(67 downto 0),
+ dmonitoroutclk_out(0) => NLW_inst_dmonitoroutclk_out_UNCONNECTED(0),
+ drpaddr_common_in(8 downto 0) => B"000000000",
+ drpaddr_in(35 downto 0) => B"000000000000000000000000000000000000",
+ drpclk_common_in(0) => '0',
+ drpclk_in(3 downto 0) => drpclk_in(3 downto 0),
+ drpdi_common_in(15 downto 0) => B"0000000000000000",
+ drpdi_in(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ drpdo_common_out(15 downto 0) => NLW_inst_drpdo_common_out_UNCONNECTED(15 downto 0),
+ drpdo_out(63 downto 0) => NLW_inst_drpdo_out_UNCONNECTED(63 downto 0),
+ drpen_common_in(0) => '0',
+ drpen_in(3 downto 0) => B"0000",
+ drprdy_common_out(0) => NLW_inst_drprdy_common_out_UNCONNECTED(0),
+ drprdy_out(3 downto 0) => NLW_inst_drprdy_out_UNCONNECTED(3 downto 0),
+ drprst_in(0) => '0',
+ drpwe_common_in(0) => '0',
+ drpwe_in(3 downto 0) => B"0000",
+ elpcaldvorwren_in(0) => '0',
+ elpcalpaorwren_in(0) => '0',
+ evoddphicaldone_in(3 downto 0) => B"0000",
+ evoddphicalstart_in(3 downto 0) => B"0000",
+ evoddphidrden_in(3 downto 0) => B"0000",
+ evoddphidwren_in(3 downto 0) => B"0000",
+ evoddphixrden_in(3 downto 0) => B"0000",
+ evoddphixwren_in(3 downto 0) => B"0000",
+ eyescandataerror_out(3 downto 0) => NLW_inst_eyescandataerror_out_UNCONNECTED(3 downto 0),
+ eyescanmode_in(3 downto 0) => B"0000",
+ eyescanreset_in(3 downto 0) => B"0000",
+ eyescantrigger_in(3 downto 0) => B"0000",
+ freqos_in(0) => '0',
+ gtgrefclk0_in(0) => '0',
+ gtgrefclk1_in(0) => '0',
+ gtgrefclk_in(3 downto 0) => B"0000",
+ gthrxn_in(3 downto 0) => gthrxn_in(3 downto 0),
+ gthrxp_in(3 downto 0) => gthrxp_in(3 downto 0),
+ gthtxn_out(3 downto 0) => gthtxn_out(3 downto 0),
+ gthtxp_out(3 downto 0) => gthtxp_out(3 downto 0),
+ gtnorthrefclk00_in(0) => '0',
+ gtnorthrefclk01_in(0) => '0',
+ gtnorthrefclk0_in(3 downto 0) => B"0000",
+ gtnorthrefclk10_in(0) => '0',
+ gtnorthrefclk11_in(0) => '0',
+ gtnorthrefclk1_in(3 downto 0) => B"0000",
+ gtpowergood_out(3 downto 0) => gtpowergood_out(3 downto 0),
+ gtrefclk00_in(0) => '0',
+ gtrefclk01_in(0) => gtrefclk01_in(0),
+ gtrefclk0_in(3 downto 0) => gtrefclk0_in(3 downto 0),
+ gtrefclk10_in(0) => '0',
+ gtrefclk11_in(0) => '0',
+ gtrefclk1_in(3 downto 0) => B"0000",
+ gtrefclkmonitor_out(3 downto 0) => NLW_inst_gtrefclkmonitor_out_UNCONNECTED(3 downto 0),
+ gtresetsel_in(3 downto 0) => B"0000",
+ gtrsvd_in(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ gtrxreset_in(3 downto 0) => B"0000",
+ gtrxresetsel_in(0) => '0',
+ gtsouthrefclk00_in(0) => '0',
+ gtsouthrefclk01_in(0) => '0',
+ gtsouthrefclk0_in(3 downto 0) => B"0000",
+ gtsouthrefclk10_in(0) => '0',
+ gtsouthrefclk11_in(0) => '0',
+ gtsouthrefclk1_in(3 downto 0) => B"0000",
+ gttxreset_in(3 downto 0) => B"0000",
+ gttxresetsel_in(0) => '0',
+ gtwiz_buffbypass_rx_done_out(0) => NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED(0),
+ gtwiz_buffbypass_rx_error_out(0) => NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED(0),
+ gtwiz_buffbypass_rx_reset_in(0) => '0',
+ gtwiz_buffbypass_rx_start_user_in(0) => '0',
+ gtwiz_buffbypass_tx_done_out(0) => gtwiz_buffbypass_tx_done_out(0),
+ gtwiz_buffbypass_tx_error_out(0) => gtwiz_buffbypass_tx_error_out(0),
+ gtwiz_buffbypass_tx_reset_in(0) => gtwiz_buffbypass_tx_reset_in(0),
+ gtwiz_buffbypass_tx_start_user_in(0) => gtwiz_buffbypass_tx_start_user_in(0),
+ gtwiz_gthe3_cpll_cal_bufg_ce_in(3 downto 0) => B"0000",
+ gtwiz_gthe3_cpll_cal_cnt_tol_in(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
+ gtwiz_gthe3_cpll_cal_txoutclk_period_in(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
+ gtwiz_gthe4_cpll_cal_bufg_ce_in(3 downto 0) => B"0000",
+ gtwiz_gthe4_cpll_cal_cnt_tol_in(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
+ gtwiz_gthe4_cpll_cal_txoutclk_period_in(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
+ gtwiz_gtye4_cpll_cal_bufg_ce_in(3 downto 0) => B"0000",
+ gtwiz_gtye4_cpll_cal_cnt_tol_in(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
+ gtwiz_gtye4_cpll_cal_txoutclk_period_in(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
+ gtwiz_reset_all_in(0) => gtwiz_reset_all_in(0),
+ gtwiz_reset_clk_freerun_in(0) => gtwiz_reset_clk_freerun_in(0),
+ gtwiz_reset_qpll0lock_in(0) => '0',
+ gtwiz_reset_qpll0reset_out(0) => NLW_inst_gtwiz_reset_qpll0reset_out_UNCONNECTED(0),
+ gtwiz_reset_qpll1lock_in(0) => '0',
+ gtwiz_reset_qpll1reset_out(0) => NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED(0),
+ gtwiz_reset_rx_cdr_stable_out(0) => gtwiz_reset_rx_cdr_stable_out(0),
+ gtwiz_reset_rx_datapath_in(0) => gtwiz_reset_rx_datapath_in(0),
+ gtwiz_reset_rx_done_in(0) => '0',
+ gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out(0),
+ gtwiz_reset_rx_pll_and_datapath_in(0) => gtwiz_reset_rx_pll_and_datapath_in(0),
+ gtwiz_reset_tx_datapath_in(0) => gtwiz_reset_tx_datapath_in(0),
+ gtwiz_reset_tx_done_in(0) => '0',
+ gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out(0),
+ gtwiz_reset_tx_pll_and_datapath_in(0) => gtwiz_reset_tx_pll_and_datapath_in(0),
+ gtwiz_userclk_rx_active_in(0) => gtwiz_userclk_rx_active_in(0),
+ gtwiz_userclk_rx_active_out(0) => NLW_inst_gtwiz_userclk_rx_active_out_UNCONNECTED(0),
+ gtwiz_userclk_rx_reset_in(0) => '0',
+ gtwiz_userclk_rx_srcclk_out(0) => NLW_inst_gtwiz_userclk_rx_srcclk_out_UNCONNECTED(0),
+ gtwiz_userclk_rx_usrclk2_out(0) => NLW_inst_gtwiz_userclk_rx_usrclk2_out_UNCONNECTED(0),
+ gtwiz_userclk_rx_usrclk_out(0) => NLW_inst_gtwiz_userclk_rx_usrclk_out_UNCONNECTED(0),
+ gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_in(0),
+ gtwiz_userclk_tx_active_out(0) => NLW_inst_gtwiz_userclk_tx_active_out_UNCONNECTED(0),
+ gtwiz_userclk_tx_reset_in(0) => '0',
+ gtwiz_userclk_tx_srcclk_out(0) => NLW_inst_gtwiz_userclk_tx_srcclk_out_UNCONNECTED(0),
+ gtwiz_userclk_tx_usrclk2_out(0) => NLW_inst_gtwiz_userclk_tx_usrclk2_out_UNCONNECTED(0),
+ gtwiz_userclk_tx_usrclk_out(0) => NLW_inst_gtwiz_userclk_tx_usrclk_out_UNCONNECTED(0),
+ gtwiz_userdata_rx_out(63 downto 0) => gtwiz_userdata_rx_out(63 downto 0),
+ gtwiz_userdata_tx_in(127 downto 0) => gtwiz_userdata_tx_in(127 downto 0),
+ gtyrxn_in(0) => '0',
+ gtyrxp_in(0) => '0',
+ gtytxn_out(0) => NLW_inst_gtytxn_out_UNCONNECTED(0),
+ gtytxp_out(0) => NLW_inst_gtytxp_out_UNCONNECTED(0),
+ incpctrl_in(0) => '0',
+ loopback_in(11 downto 0) => loopback_in(11 downto 0),
+ looprsvd_in(0) => '0',
+ lpbkrxtxseren_in(3 downto 0) => B"0000",
+ lpbktxrxseren_in(3 downto 0) => B"0000",
+ pcieeqrxeqadaptdone_in(3 downto 0) => B"0000",
+ pcierategen3_out(3 downto 0) => NLW_inst_pcierategen3_out_UNCONNECTED(3 downto 0),
+ pcierateidle_out(3 downto 0) => NLW_inst_pcierateidle_out_UNCONNECTED(3 downto 0),
+ pcierateqpll0_in(0) => '0',
+ pcierateqpll1_in(0) => '0',
+ pcierateqpllpd_out(7 downto 0) => NLW_inst_pcierateqpllpd_out_UNCONNECTED(7 downto 0),
+ pcierateqpllreset_out(7 downto 0) => NLW_inst_pcierateqpllreset_out_UNCONNECTED(7 downto 0),
+ pcierstidle_in(3 downto 0) => B"0000",
+ pciersttxsyncstart_in(3 downto 0) => B"0000",
+ pciesynctxsyncdone_out(3 downto 0) => NLW_inst_pciesynctxsyncdone_out_UNCONNECTED(3 downto 0),
+ pcieusergen3rdy_out(3 downto 0) => NLW_inst_pcieusergen3rdy_out_UNCONNECTED(3 downto 0),
+ pcieuserphystatusrst_out(3 downto 0) => NLW_inst_pcieuserphystatusrst_out_UNCONNECTED(3 downto 0),
+ pcieuserratedone_in(3 downto 0) => B"0000",
+ pcieuserratestart_out(3 downto 0) => NLW_inst_pcieuserratestart_out_UNCONNECTED(3 downto 0),
+ pcsrsvdin2_in(19 downto 0) => B"00000000000000000000",
+ pcsrsvdin_in(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ pcsrsvdout_out(47 downto 0) => NLW_inst_pcsrsvdout_out_UNCONNECTED(47 downto 0),
+ phystatus_out(3 downto 0) => NLW_inst_phystatus_out_UNCONNECTED(3 downto 0),
+ pinrsrvdas_out(31 downto 0) => NLW_inst_pinrsrvdas_out_UNCONNECTED(31 downto 0),
+ pmarsvd0_in(7 downto 0) => B"00000000",
+ pmarsvd1_in(7 downto 0) => B"00000000",
+ pmarsvdin_in(19 downto 0) => B"00000000000000000000",
+ pmarsvdout0_out(7 downto 0) => NLW_inst_pmarsvdout0_out_UNCONNECTED(7 downto 0),
+ pmarsvdout1_out(7 downto 0) => NLW_inst_pmarsvdout1_out_UNCONNECTED(7 downto 0),
+ powerpresent_out(0) => NLW_inst_powerpresent_out_UNCONNECTED(0),
+ qpll0clk_in(3 downto 0) => B"0000",
+ qpll0clkrsvd0_in(0) => '0',
+ qpll0clkrsvd1_in(0) => '0',
+ qpll0fbclklost_out(0) => qpll0fbclklost_out(0),
+ qpll0fbdiv_in(0) => '0',
+ qpll0freqlock_in(0) => '0',
+ qpll0lock_out(0) => qpll0lock_out(0),
+ qpll0lockdetclk_in(0) => '0',
+ qpll0locken_in(0) => '0',
+ qpll0outclk_out(0) => NLW_inst_qpll0outclk_out_UNCONNECTED(0),
+ qpll0outrefclk_out(0) => NLW_inst_qpll0outrefclk_out_UNCONNECTED(0),
+ qpll0pd_in(0) => '1',
+ qpll0refclk_in(3 downto 0) => B"0000",
+ qpll0refclklost_out(0) => NLW_inst_qpll0refclklost_out_UNCONNECTED(0),
+ qpll0refclksel_in(2 downto 0) => B"001",
+ qpll0reset_in(0) => '1',
+ qpll1clk_in(3 downto 0) => B"0000",
+ qpll1clkrsvd0_in(0) => '0',
+ qpll1clkrsvd1_in(0) => '0',
+ qpll1fbclklost_out(0) => qpll1fbclklost_out(0),
+ qpll1fbdiv_in(0) => '0',
+ qpll1freqlock_in(0) => '0',
+ qpll1lock_out(0) => qpll1lock_out(0),
+ qpll1lockdetclk_in(0) => '0',
+ qpll1locken_in(0) => '1',
+ qpll1outclk_out(0) => qpll1outclk_out(0),
+ qpll1outrefclk_out(0) => qpll1outrefclk_out(0),
+ qpll1pd_in(0) => '0',
+ qpll1refclk_in(3 downto 0) => B"0000",
+ qpll1refclklost_out(0) => NLW_inst_qpll1refclklost_out_UNCONNECTED(0),
+ qpll1refclksel_in(2 downto 0) => B"001",
+ qpll1reset_in(0) => '0',
+ qplldmonitor0_out(7 downto 0) => NLW_inst_qplldmonitor0_out_UNCONNECTED(7 downto 0),
+ qplldmonitor1_out(7 downto 0) => NLW_inst_qplldmonitor1_out_UNCONNECTED(7 downto 0),
+ qpllrsvd1_in(7 downto 0) => B"00000000",
+ qpllrsvd2_in(4 downto 0) => B"00000",
+ qpllrsvd3_in(4 downto 0) => B"00000",
+ qpllrsvd4_in(7 downto 0) => B"00000000",
+ rcalenb_in(0) => '1',
+ refclkoutmonitor0_out(0) => NLW_inst_refclkoutmonitor0_out_UNCONNECTED(0),
+ refclkoutmonitor1_out(0) => NLW_inst_refclkoutmonitor1_out_UNCONNECTED(0),
+ resetexception_out(3 downto 0) => NLW_inst_resetexception_out_UNCONNECTED(3 downto 0),
+ resetovrd_in(3 downto 0) => B"0000",
+ rstclkentx_in(3 downto 0) => B"0000",
+ rx8b10ben_in(3 downto 0) => B"0000",
+ rxafecfoken_in(0) => '0',
+ rxbufreset_in(3 downto 0) => B"0000",
+ rxbufstatus_out(11 downto 0) => NLW_inst_rxbufstatus_out_UNCONNECTED(11 downto 0),
+ rxbyteisaligned_out(3 downto 0) => NLW_inst_rxbyteisaligned_out_UNCONNECTED(3 downto 0),
+ rxbyterealign_out(3 downto 0) => NLW_inst_rxbyterealign_out_UNCONNECTED(3 downto 0),
+ rxcdrfreqreset_in(3 downto 0) => B"0000",
+ rxcdrhold_in(3 downto 0) => rxcdrhold_in(3 downto 0),
+ rxcdrlock_out(3 downto 0) => rxcdrlock_out(3 downto 0),
+ rxcdrovrden_in(3 downto 0) => B"0000",
+ rxcdrphdone_out(3 downto 0) => NLW_inst_rxcdrphdone_out_UNCONNECTED(3 downto 0),
+ rxcdrreset_in(3 downto 0) => B"0000",
+ rxcdrresetrsv_in(3 downto 0) => B"0000",
+ rxchanbondseq_out(3 downto 0) => NLW_inst_rxchanbondseq_out_UNCONNECTED(3 downto 0),
+ rxchanisaligned_out(3 downto 0) => NLW_inst_rxchanisaligned_out_UNCONNECTED(3 downto 0),
+ rxchanrealign_out(3 downto 0) => NLW_inst_rxchanrealign_out_UNCONNECTED(3 downto 0),
+ rxchbonden_in(3 downto 0) => B"0000",
+ rxchbondi_in(19 downto 0) => B"00000000000000000000",
+ rxchbondlevel_in(11 downto 0) => B"000000000000",
+ rxchbondmaster_in(3 downto 0) => B"0000",
+ rxchbondo_out(19 downto 0) => NLW_inst_rxchbondo_out_UNCONNECTED(19 downto 0),
+ rxchbondslave_in(3 downto 0) => B"0000",
+ rxckcaldone_out(0) => NLW_inst_rxckcaldone_out_UNCONNECTED(0),
+ rxckcalreset_in(0) => '0',
+ rxckcalstart_in(0) => '0',
+ rxclkcorcnt_out(7 downto 0) => NLW_inst_rxclkcorcnt_out_UNCONNECTED(7 downto 0),
+ rxcominitdet_out(3 downto 0) => NLW_inst_rxcominitdet_out_UNCONNECTED(3 downto 0),
+ rxcommadet_out(3 downto 0) => NLW_inst_rxcommadet_out_UNCONNECTED(3 downto 0),
+ rxcommadeten_in(3 downto 0) => B"0000",
+ rxcomsasdet_out(3 downto 0) => NLW_inst_rxcomsasdet_out_UNCONNECTED(3 downto 0),
+ rxcomwakedet_out(3 downto 0) => NLW_inst_rxcomwakedet_out_UNCONNECTED(3 downto 0),
+ rxctrl0_out(63 downto 0) => NLW_inst_rxctrl0_out_UNCONNECTED(63 downto 0),
+ rxctrl1_out(63 downto 0) => NLW_inst_rxctrl1_out_UNCONNECTED(63 downto 0),
+ rxctrl2_out(31 downto 0) => NLW_inst_rxctrl2_out_UNCONNECTED(31 downto 0),
+ rxctrl3_out(31 downto 0) => NLW_inst_rxctrl3_out_UNCONNECTED(31 downto 0),
+ rxdata_out(511 downto 0) => NLW_inst_rxdata_out_UNCONNECTED(511 downto 0),
+ rxdataextendrsvd_out(31 downto 0) => NLW_inst_rxdataextendrsvd_out_UNCONNECTED(31 downto 0),
+ rxdatavalid_out(7 downto 0) => NLW_inst_rxdatavalid_out_UNCONNECTED(7 downto 0),
+ rxdccforcestart_in(0) => '0',
+ rxdfeagcctrl_in(7 downto 0) => B"01010101",
+ rxdfeagchold_in(3 downto 0) => B"0000",
+ rxdfeagcovrden_in(3 downto 0) => B"0000",
+ rxdfecfokfcnum_in(0) => '0',
+ rxdfecfokfen_in(0) => '0',
+ rxdfecfokfpulse_in(0) => '0',
+ rxdfecfokhold_in(0) => '0',
+ rxdfecfokovren_in(0) => '0',
+ rxdfekhhold_in(0) => '0',
+ rxdfekhovrden_in(0) => '0',
+ rxdfelfhold_in(3 downto 0) => B"0000",
+ rxdfelfovrden_in(3 downto 0) => B"0000",
+ rxdfelpmreset_in(3 downto 0) => B"0000",
+ rxdfetap10hold_in(3 downto 0) => B"0000",
+ rxdfetap10ovrden_in(3 downto 0) => B"0000",
+ rxdfetap11hold_in(3 downto 0) => B"0000",
+ rxdfetap11ovrden_in(3 downto 0) => B"0000",
+ rxdfetap12hold_in(3 downto 0) => B"0000",
+ rxdfetap12ovrden_in(3 downto 0) => B"0000",
+ rxdfetap13hold_in(3 downto 0) => B"0000",
+ rxdfetap13ovrden_in(3 downto 0) => B"0000",
+ rxdfetap14hold_in(3 downto 0) => B"0000",
+ rxdfetap14ovrden_in(3 downto 0) => B"0000",
+ rxdfetap15hold_in(3 downto 0) => B"0000",
+ rxdfetap15ovrden_in(3 downto 0) => B"0000",
+ rxdfetap2hold_in(3 downto 0) => B"0000",
+ rxdfetap2ovrden_in(3 downto 0) => B"0000",
+ rxdfetap3hold_in(3 downto 0) => B"0000",
+ rxdfetap3ovrden_in(3 downto 0) => B"0000",
+ rxdfetap4hold_in(3 downto 0) => B"0000",
+ rxdfetap4ovrden_in(3 downto 0) => B"0000",
+ rxdfetap5hold_in(3 downto 0) => B"0000",
+ rxdfetap5ovrden_in(3 downto 0) => B"0000",
+ rxdfetap6hold_in(3 downto 0) => B"0000",
+ rxdfetap6ovrden_in(3 downto 0) => B"0000",
+ rxdfetap7hold_in(3 downto 0) => B"0000",
+ rxdfetap7ovrden_in(3 downto 0) => B"0000",
+ rxdfetap8hold_in(3 downto 0) => B"0000",
+ rxdfetap8ovrden_in(3 downto 0) => B"0000",
+ rxdfetap9hold_in(3 downto 0) => B"0000",
+ rxdfetap9ovrden_in(3 downto 0) => B"0000",
+ rxdfeuthold_in(3 downto 0) => B"0000",
+ rxdfeutovrden_in(3 downto 0) => B"0000",
+ rxdfevphold_in(3 downto 0) => B"0000",
+ rxdfevpovrden_in(3 downto 0) => B"0000",
+ rxdfevsen_in(3 downto 0) => B"0000",
+ rxdfexyden_in(3 downto 0) => B"1111",
+ rxdlybypass_in(3 downto 0) => B"1111",
+ rxdlyen_in(3 downto 0) => B"0000",
+ rxdlyovrden_in(3 downto 0) => B"0000",
+ rxdlysreset_in(3 downto 0) => B"0000",
+ rxdlysresetdone_out(3 downto 0) => NLW_inst_rxdlysresetdone_out_UNCONNECTED(3 downto 0),
+ rxelecidle_out(3 downto 0) => NLW_inst_rxelecidle_out_UNCONNECTED(3 downto 0),
+ rxelecidlemode_in(7 downto 0) => B"11111111",
+ rxeqtraining_in(0) => '0',
+ rxgearboxslip_in(3 downto 0) => B"0000",
+ rxheader_out(23 downto 0) => NLW_inst_rxheader_out_UNCONNECTED(23 downto 0),
+ rxheadervalid_out(7 downto 0) => NLW_inst_rxheadervalid_out_UNCONNECTED(7 downto 0),
+ rxlatclk_in(3 downto 0) => B"0000",
+ rxlfpstresetdet_out(0) => NLW_inst_rxlfpstresetdet_out_UNCONNECTED(0),
+ rxlfpsu2lpexitdet_out(0) => NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED(0),
+ rxlfpsu3wakedet_out(0) => NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED(0),
+ rxlpmen_in(3 downto 0) => B"0000",
+ rxlpmgchold_in(3 downto 0) => B"0000",
+ rxlpmgcovrden_in(3 downto 0) => B"0000",
+ rxlpmhfhold_in(3 downto 0) => B"0000",
+ rxlpmhfovrden_in(3 downto 0) => B"0000",
+ rxlpmlfhold_in(3 downto 0) => B"0000",
+ rxlpmlfklovrden_in(3 downto 0) => B"0000",
+ rxlpmoshold_in(3 downto 0) => B"0000",
+ rxlpmosovrden_in(3 downto 0) => B"0000",
+ rxmcommaalignen_in(3 downto 0) => B"0000",
+ rxmonitorout_out(27 downto 0) => NLW_inst_rxmonitorout_out_UNCONNECTED(27 downto 0),
+ rxmonitorsel_in(7 downto 0) => B"00000000",
+ rxoobreset_in(3 downto 0) => B"0000",
+ rxoscalreset_in(3 downto 0) => B"0000",
+ rxoshold_in(3 downto 0) => B"0000",
+ rxosintcfg_in(15 downto 0) => B"1101110111011101",
+ rxosintdone_out(3 downto 0) => NLW_inst_rxosintdone_out_UNCONNECTED(3 downto 0),
+ rxosinten_in(3 downto 0) => B"1111",
+ rxosinthold_in(3 downto 0) => B"0000",
+ rxosintovrden_in(3 downto 0) => B"0000",
+ rxosintstarted_out(3 downto 0) => NLW_inst_rxosintstarted_out_UNCONNECTED(3 downto 0),
+ rxosintstrobe_in(3 downto 0) => B"0000",
+ rxosintstrobedone_out(3 downto 0) => NLW_inst_rxosintstrobedone_out_UNCONNECTED(3 downto 0),
+ rxosintstrobestarted_out(3 downto 0) => NLW_inst_rxosintstrobestarted_out_UNCONNECTED(3 downto 0),
+ rxosinttestovrden_in(3 downto 0) => B"0000",
+ rxosovrden_in(3 downto 0) => B"0000",
+ rxoutclk_out(3 downto 0) => rxoutclk_out(3 downto 0),
+ rxoutclkfabric_out(3 downto 0) => NLW_inst_rxoutclkfabric_out_UNCONNECTED(3 downto 0),
+ rxoutclkpcs_out(3 downto 0) => NLW_inst_rxoutclkpcs_out_UNCONNECTED(3 downto 0),
+ rxoutclksel_in(11 downto 0) => B"010010010010",
+ rxpcommaalignen_in(3 downto 0) => B"0000",
+ rxpcsreset_in(3 downto 0) => B"0000",
+ rxpd_in(7 downto 0) => B"00000000",
+ rxphalign_in(3 downto 0) => B"0000",
+ rxphaligndone_out(3 downto 0) => NLW_inst_rxphaligndone_out_UNCONNECTED(3 downto 0),
+ rxphalignen_in(3 downto 0) => B"0000",
+ rxphalignerr_out(3 downto 0) => NLW_inst_rxphalignerr_out_UNCONNECTED(3 downto 0),
+ rxphdlypd_in(3 downto 0) => B"1111",
+ rxphdlyreset_in(3 downto 0) => B"0000",
+ rxphovrden_in(3 downto 0) => B"0000",
+ rxpllclksel_in(7 downto 0) => B"00000000",
+ rxpmareset_in(3 downto 0) => B"0000",
+ rxpmaresetdone_out(3 downto 0) => rxpmaresetdone_out(3 downto 0),
+ rxpolarity_in(3 downto 0) => rxpolarity_in(3 downto 0),
+ rxprbscntreset_in(3 downto 0) => B"0000",
+ rxprbserr_out(3 downto 0) => NLW_inst_rxprbserr_out_UNCONNECTED(3 downto 0),
+ rxprbslocked_out(3 downto 0) => NLW_inst_rxprbslocked_out_UNCONNECTED(3 downto 0),
+ rxprbssel_in(15 downto 0) => B"0000000000000000",
+ rxprgdivresetdone_out(3 downto 0) => NLW_inst_rxprgdivresetdone_out_UNCONNECTED(3 downto 0),
+ rxprogdivreset_in(3 downto 0) => B"0000",
+ rxqpien_in(3 downto 0) => B"0000",
+ rxqpisenn_out(3 downto 0) => NLW_inst_rxqpisenn_out_UNCONNECTED(3 downto 0),
+ rxqpisenp_out(3 downto 0) => NLW_inst_rxqpisenp_out_UNCONNECTED(3 downto 0),
+ rxrate_in(11 downto 0) => B"000000000000",
+ rxratedone_out(3 downto 0) => rxratedone_out(3 downto 0),
+ rxratemode_in(3 downto 0) => B"0000",
+ rxrecclk0_sel_out(1 downto 0) => NLW_inst_rxrecclk0_sel_out_UNCONNECTED(1 downto 0),
+ rxrecclk0sel_out(0) => NLW_inst_rxrecclk0sel_out_UNCONNECTED(0),
+ rxrecclk1_sel_out(1 downto 0) => NLW_inst_rxrecclk1_sel_out_UNCONNECTED(1 downto 0),
+ rxrecclk1sel_out(0) => NLW_inst_rxrecclk1sel_out_UNCONNECTED(0),
+ rxrecclkout_out(3 downto 0) => NLW_inst_rxrecclkout_out_UNCONNECTED(3 downto 0),
+ rxresetdone_out(3 downto 0) => rxresetdone_out(3 downto 0),
+ rxslide_in(3 downto 0) => rxslide_in(3 downto 0),
+ rxsliderdy_out(3 downto 0) => NLW_inst_rxsliderdy_out_UNCONNECTED(3 downto 0),
+ rxslipdone_out(3 downto 0) => NLW_inst_rxslipdone_out_UNCONNECTED(3 downto 0),
+ rxslipoutclk_in(3 downto 0) => B"0000",
+ rxslipoutclkrdy_out(3 downto 0) => NLW_inst_rxslipoutclkrdy_out_UNCONNECTED(3 downto 0),
+ rxslippma_in(3 downto 0) => B"0000",
+ rxslippmardy_out(3 downto 0) => NLW_inst_rxslippmardy_out_UNCONNECTED(3 downto 0),
+ rxstartofseq_out(7 downto 0) => NLW_inst_rxstartofseq_out_UNCONNECTED(7 downto 0),
+ rxstatus_out(11 downto 0) => NLW_inst_rxstatus_out_UNCONNECTED(11 downto 0),
+ rxsyncallin_in(3 downto 0) => B"0000",
+ rxsyncdone_out(3 downto 0) => NLW_inst_rxsyncdone_out_UNCONNECTED(3 downto 0),
+ rxsyncin_in(3 downto 0) => B"0000",
+ rxsyncmode_in(3 downto 0) => B"0000",
+ rxsyncout_out(3 downto 0) => NLW_inst_rxsyncout_out_UNCONNECTED(3 downto 0),
+ rxsysclksel_in(7 downto 0) => B"00000000",
+ rxtermination_in(0) => '0',
+ rxuserrdy_in(3 downto 0) => B"1111",
+ rxusrclk2_in(3 downto 0) => rxusrclk2_in(3 downto 0),
+ rxusrclk_in(3 downto 0) => rxusrclk_in(3 downto 0),
+ rxvalid_out(3 downto 0) => NLW_inst_rxvalid_out_UNCONNECTED(3 downto 0),
+ sdm0data_in(0) => '0',
+ sdm0finalout_out(0) => NLW_inst_sdm0finalout_out_UNCONNECTED(0),
+ sdm0reset_in(0) => '0',
+ sdm0testdata_out(0) => NLW_inst_sdm0testdata_out_UNCONNECTED(0),
+ sdm0toggle_in(0) => '0',
+ sdm0width_in(0) => '0',
+ sdm1data_in(0) => '0',
+ sdm1finalout_out(0) => NLW_inst_sdm1finalout_out_UNCONNECTED(0),
+ sdm1reset_in(0) => '0',
+ sdm1testdata_out(0) => NLW_inst_sdm1testdata_out_UNCONNECTED(0),
+ sdm1toggle_in(0) => '0',
+ sdm1width_in(0) => '0',
+ sigvalidclk_in(3 downto 0) => B"0000",
+ tcongpi_in(0) => '0',
+ tcongpo_out(0) => NLW_inst_tcongpo_out_UNCONNECTED(0),
+ tconpowerup_in(0) => '0',
+ tconreset_in(0) => '0',
+ tconrsvdin1_in(0) => '0',
+ tconrsvdout0_out(0) => NLW_inst_tconrsvdout0_out_UNCONNECTED(0),
+ tstin_in(79 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ tx8b10bbypass_in(31 downto 0) => B"00000000000000000000000000000000",
+ tx8b10ben_in(3 downto 0) => B"0000",
+ txbufdiffctrl_in(11 downto 0) => B"000000000000",
+ txbufstatus_out(7 downto 0) => NLW_inst_txbufstatus_out_UNCONNECTED(7 downto 0),
+ txcomfinish_out(3 downto 0) => NLW_inst_txcomfinish_out_UNCONNECTED(3 downto 0),
+ txcominit_in(3 downto 0) => B"0000",
+ txcomsas_in(3 downto 0) => B"0000",
+ txcomwake_in(3 downto 0) => B"0000",
+ txctrl0_in(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ txctrl1_in(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ txctrl2_in(31 downto 0) => B"00000000000000000000000000000000",
+ txdata_in(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ txdataextendrsvd_in(31 downto 0) => B"00000000000000000000000000000000",
+ txdccdone_out(0) => NLW_inst_txdccdone_out_UNCONNECTED(0),
+ txdccforcestart_in(0) => '0',
+ txdccreset_in(0) => '0',
+ txdeemph_in(3 downto 0) => B"0000",
+ txdetectrx_in(3 downto 0) => B"0000",
+ txdiffctrl_in(15 downto 0) => B"1100110011001100",
+ txdiffpd_in(3 downto 0) => B"0000",
+ txdlybypass_in(3 downto 0) => B"0000",
+ txdlyen_in(3 downto 0) => B"0000",
+ txdlyhold_in(3 downto 0) => B"0000",
+ txdlyovrden_in(3 downto 0) => B"0000",
+ txdlysreset_in(3 downto 0) => B"0000",
+ txdlysresetdone_out(3 downto 0) => NLW_inst_txdlysresetdone_out_UNCONNECTED(3 downto 0),
+ txdlyupdown_in(3 downto 0) => B"0000",
+ txelecidle_in(3 downto 0) => B"0000",
+ txelforcestart_in(0) => '0',
+ txheader_in(23 downto 0) => B"000000000000000000000000",
+ txinhibit_in(3 downto 0) => B"0000",
+ txlatclk_in(3 downto 0) => B"0000",
+ txlfpstreset_in(0) => '0',
+ txlfpsu2lpexit_in(0) => '0',
+ txlfpsu3wake_in(0) => '0',
+ txmaincursor_in(27 downto 0) => B"1000000100000010000001000000",
+ txmargin_in(11 downto 0) => B"000000000000",
+ txmuxdcdexhold_in(0) => '0',
+ txmuxdcdorwren_in(0) => '0',
+ txoneszeros_in(0) => '0',
+ txoutclk_out(3 downto 0) => txoutclk_out(3 downto 0),
+ txoutclkfabric_out(3 downto 0) => NLW_inst_txoutclkfabric_out_UNCONNECTED(3 downto 0),
+ txoutclkpcs_out(3 downto 0) => NLW_inst_txoutclkpcs_out_UNCONNECTED(3 downto 0),
+ txoutclksel_in(11 downto 0) => B"101101101101",
+ txpcsreset_in(3 downto 0) => B"0000",
+ txpd_in(7 downto 0) => B"00000000",
+ txpdelecidlemode_in(3 downto 0) => B"0000",
+ txphalign_in(3 downto 0) => B"0000",
+ txphaligndone_out(3 downto 0) => NLW_inst_txphaligndone_out_UNCONNECTED(3 downto 0),
+ txphalignen_in(3 downto 0) => B"0000",
+ txphdlypd_in(3 downto 0) => B"0000",
+ txphdlyreset_in(3 downto 0) => B"0000",
+ txphdlytstclk_in(3 downto 0) => B"0000",
+ txphinit_in(3 downto 0) => B"0000",
+ txphinitdone_out(3 downto 0) => NLW_inst_txphinitdone_out_UNCONNECTED(3 downto 0),
+ txphovrden_in(3 downto 0) => B"0000",
+ txpippmen_in(3 downto 0) => B"0000",
+ txpippmovrden_in(3 downto 0) => B"0000",
+ txpippmpd_in(3 downto 0) => B"0000",
+ txpippmsel_in(3 downto 0) => B"0000",
+ txpippmstepsize_in(19 downto 0) => B"00000000000000000000",
+ txpisopd_in(3 downto 0) => B"0000",
+ txpllclksel_in(7 downto 0) => B"10101010",
+ txpmareset_in(3 downto 0) => B"0000",
+ txpmaresetdone_out(3 downto 0) => txpmaresetdone_out(3 downto 0),
+ txpolarity_in(3 downto 0) => txpolarity_in(3 downto 0),
+ txpostcursor_in(19 downto 0) => B"00000000000000000000",
+ txpostcursorinv_in(3 downto 0) => B"0000",
+ txprbsforceerr_in(3 downto 0) => B"0000",
+ txprbssel_in(15 downto 0) => B"0000000000000000",
+ txprecursor_in(19 downto 0) => B"00000000000000000000",
+ txprecursorinv_in(3 downto 0) => B"0000",
+ txprgdivresetdone_out(3 downto 0) => txprgdivresetdone_out(3 downto 0),
+ txprogdivreset_in(3 downto 0) => B"0000",
+ txqpibiasen_in(3 downto 0) => B"0000",
+ txqpisenn_out(3 downto 0) => NLW_inst_txqpisenn_out_UNCONNECTED(3 downto 0),
+ txqpisenp_out(3 downto 0) => NLW_inst_txqpisenp_out_UNCONNECTED(3 downto 0),
+ txqpistrongpdown_in(3 downto 0) => B"0000",
+ txqpiweakpup_in(3 downto 0) => B"0000",
+ txrate_in(11 downto 0) => B"000000000000",
+ txratedone_out(3 downto 0) => NLW_inst_txratedone_out_UNCONNECTED(3 downto 0),
+ txratemode_in(3 downto 0) => B"0000",
+ txresetdone_out(3 downto 0) => txresetdone_out(3 downto 0),
+ txsequence_in(27 downto 0) => B"0000000000000000000000000000",
+ txswing_in(3 downto 0) => B"0000",
+ txsyncallin_in(3 downto 0) => B"0000",
+ txsyncdone_out(3 downto 0) => NLW_inst_txsyncdone_out_UNCONNECTED(3 downto 0),
+ txsyncin_in(3 downto 0) => B"0000",
+ txsyncmode_in(3 downto 0) => B"0000",
+ txsyncout_out(3 downto 0) => NLW_inst_txsyncout_out_UNCONNECTED(3 downto 0),
+ txsysclksel_in(7 downto 0) => B"11111111",
+ txuserrdy_in(3 downto 0) => B"1111",
+ txusrclk2_in(3 downto 0) => txusrclk2_in(3 downto 0),
+ txusrclk_in(3 downto 0) => txusrclk_in(3 downto 0),
+ ubcfgstreamen_in(0) => '0',
+ ubdaddr_out(0) => NLW_inst_ubdaddr_out_UNCONNECTED(0),
+ ubden_out(0) => NLW_inst_ubden_out_UNCONNECTED(0),
+ ubdi_out(0) => NLW_inst_ubdi_out_UNCONNECTED(0),
+ ubdo_in(0) => '0',
+ ubdrdy_in(0) => '0',
+ ubdwe_out(0) => NLW_inst_ubdwe_out_UNCONNECTED(0),
+ ubenable_in(0) => '0',
+ ubgpi_in(0) => '0',
+ ubintr_in(0) => '0',
+ ubiolmbrst_in(0) => '0',
+ ubmbrst_in(0) => '0',
+ ubmdmcapture_in(0) => '0',
+ ubmdmdbgrst_in(0) => '0',
+ ubmdmdbgupdate_in(0) => '0',
+ ubmdmregen_in(0) => '0',
+ ubmdmshift_in(0) => '0',
+ ubmdmsysrst_in(0) => '0',
+ ubmdmtck_in(0) => '0',
+ ubmdmtdi_in(0) => '0',
+ ubmdmtdo_out(0) => NLW_inst_ubmdmtdo_out_UNCONNECTED(0),
+ ubrsvdout_out(0) => NLW_inst_ubrsvdout_out_UNCONNECTED(0),
+ ubtxuart_out(0) => NLW_inst_ubtxuart_out_UNCONNECTED(0)
+ );
+end STRUCTURE;
diff --git a/sources/ip_cores/sim/fifo_generator_fe_sim_netlist.vhdl b/sources/ip_cores/sim/fifo_generator_fe_sim_netlist.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..a0ba0d7c940f5c47f5adb74b746ae9b22e78ccc1
--- /dev/null
+++ b/sources/ip_cores/sim/fifo_generator_fe_sim_netlist.vhdl
@@ -0,0 +1,4842 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Fri Jun 14 11:28:36 2024
+-- Host : lbp001app.nikhef.nl running 64-bit unknown
+-- Command : write_vhdl -force -mode funcsim
+-- /localstore/et/franss/felix/firmware/Projects/FLX712_FELIG/FLX712_FELIG.gen/sources_1/ip/fifo_generator_fe/fifo_generator_fe_sim_netlist.vhdl
+-- Design : fifo_generator_fe
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xcku115-flvf1924-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity fifo_generator_fe_xpm_cdc_gray is
+ port (
+ src_clk : in STD_LOGIC;
+ src_in_bin : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ dest_clk : in STD_LOGIC;
+ dest_out_bin : out STD_LOGIC_VECTOR ( 5 downto 0 )
+ );
+ attribute DEST_SYNC_FF : integer;
+ attribute DEST_SYNC_FF of fifo_generator_fe_xpm_cdc_gray : entity is 2;
+ attribute INIT_SYNC_FF : integer;
+ attribute INIT_SYNC_FF of fifo_generator_fe_xpm_cdc_gray : entity is 0;
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of fifo_generator_fe_xpm_cdc_gray : entity is "xpm_cdc_gray";
+ attribute REG_OUTPUT : integer;
+ attribute REG_OUTPUT of fifo_generator_fe_xpm_cdc_gray : entity is 1;
+ attribute SIM_ASSERT_CHK : integer;
+ attribute SIM_ASSERT_CHK of fifo_generator_fe_xpm_cdc_gray : entity is 0;
+ attribute SIM_LOSSLESS_GRAY_CHK : integer;
+ attribute SIM_LOSSLESS_GRAY_CHK of fifo_generator_fe_xpm_cdc_gray : entity is 0;
+ attribute VERSION : integer;
+ attribute VERSION of fifo_generator_fe_xpm_cdc_gray : entity is 0;
+ attribute WIDTH : integer;
+ attribute WIDTH of fifo_generator_fe_xpm_cdc_gray : entity is 6;
+ attribute XPM_MODULE : string;
+ attribute XPM_MODULE of fifo_generator_fe_xpm_cdc_gray : entity is "TRUE";
+ attribute is_du_within_envelope : string;
+ attribute is_du_within_envelope of fifo_generator_fe_xpm_cdc_gray : entity is "true";
+ attribute keep_hierarchy : string;
+ attribute keep_hierarchy of fifo_generator_fe_xpm_cdc_gray : entity is "true";
+ attribute xpm_cdc : string;
+ attribute xpm_cdc of fifo_generator_fe_xpm_cdc_gray : entity is "GRAY";
+end fifo_generator_fe_xpm_cdc_gray;
+
+architecture STRUCTURE of fifo_generator_fe_xpm_cdc_gray is
+ signal async_path : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal binval : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
+ attribute RTL_KEEP : string;
+ attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
+ attribute async_reg : string;
+ attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
+ attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
+ signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
+ attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
+ attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
+ attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
+ signal gray_enc : STD_LOGIC_VECTOR ( 4 downto 0 );
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair3";
+ attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair3";
+begin
+\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => async_path(0),
+ Q => \dest_graysync_ff[0]\(0),
+ R => '0'
+ );
+\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => async_path(1),
+ Q => \dest_graysync_ff[0]\(1),
+ R => '0'
+ );
+\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => async_path(2),
+ Q => \dest_graysync_ff[0]\(2),
+ R => '0'
+ );
+\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => async_path(3),
+ Q => \dest_graysync_ff[0]\(3),
+ R => '0'
+ );
+\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => async_path(4),
+ Q => \dest_graysync_ff[0]\(4),
+ R => '0'
+ );
+\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => async_path(5),
+ Q => \dest_graysync_ff[0]\(5),
+ R => '0'
+ );
+\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => \dest_graysync_ff[0]\(0),
+ Q => \dest_graysync_ff[1]\(0),
+ R => '0'
+ );
+\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => \dest_graysync_ff[0]\(1),
+ Q => \dest_graysync_ff[1]\(1),
+ R => '0'
+ );
+\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => \dest_graysync_ff[0]\(2),
+ Q => \dest_graysync_ff[1]\(2),
+ R => '0'
+ );
+\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => \dest_graysync_ff[0]\(3),
+ Q => \dest_graysync_ff[1]\(3),
+ R => '0'
+ );
+\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => \dest_graysync_ff[0]\(4),
+ Q => \dest_graysync_ff[1]\(4),
+ R => '0'
+ );
+\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => \dest_graysync_ff[0]\(5),
+ Q => \dest_graysync_ff[1]\(5),
+ R => '0'
+ );
+\dest_out_bin_ff[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"6996966996696996"
+ )
+ port map (
+ I0 => \dest_graysync_ff[1]\(0),
+ I1 => \dest_graysync_ff[1]\(2),
+ I2 => \dest_graysync_ff[1]\(4),
+ I3 => \dest_graysync_ff[1]\(5),
+ I4 => \dest_graysync_ff[1]\(3),
+ I5 => \dest_graysync_ff[1]\(1),
+ O => binval(0)
+ );
+\dest_out_bin_ff[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"96696996"
+ )
+ port map (
+ I0 => \dest_graysync_ff[1]\(1),
+ I1 => \dest_graysync_ff[1]\(3),
+ I2 => \dest_graysync_ff[1]\(5),
+ I3 => \dest_graysync_ff[1]\(4),
+ I4 => \dest_graysync_ff[1]\(2),
+ O => binval(1)
+ );
+\dest_out_bin_ff[2]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"6996"
+ )
+ port map (
+ I0 => \dest_graysync_ff[1]\(2),
+ I1 => \dest_graysync_ff[1]\(4),
+ I2 => \dest_graysync_ff[1]\(5),
+ I3 => \dest_graysync_ff[1]\(3),
+ O => binval(2)
+ );
+\dest_out_bin_ff[3]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"96"
+ )
+ port map (
+ I0 => \dest_graysync_ff[1]\(3),
+ I1 => \dest_graysync_ff[1]\(5),
+ I2 => \dest_graysync_ff[1]\(4),
+ O => binval(3)
+ );
+\dest_out_bin_ff[4]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => \dest_graysync_ff[1]\(4),
+ I1 => \dest_graysync_ff[1]\(5),
+ O => binval(4)
+ );
+\dest_out_bin_ff_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => binval(0),
+ Q => dest_out_bin(0),
+ R => '0'
+ );
+\dest_out_bin_ff_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => binval(1),
+ Q => dest_out_bin(1),
+ R => '0'
+ );
+\dest_out_bin_ff_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => binval(2),
+ Q => dest_out_bin(2),
+ R => '0'
+ );
+\dest_out_bin_ff_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => binval(3),
+ Q => dest_out_bin(3),
+ R => '0'
+ );
+\dest_out_bin_ff_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => binval(4),
+ Q => dest_out_bin(4),
+ R => '0'
+ );
+\dest_out_bin_ff_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => \dest_graysync_ff[1]\(5),
+ Q => dest_out_bin(5),
+ R => '0'
+ );
+\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => src_in_bin(1),
+ I1 => src_in_bin(0),
+ O => gray_enc(0)
+ );
+\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => src_in_bin(2),
+ I1 => src_in_bin(1),
+ O => gray_enc(1)
+ );
+\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => src_in_bin(3),
+ I1 => src_in_bin(2),
+ O => gray_enc(2)
+ );
+\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => src_in_bin(4),
+ I1 => src_in_bin(3),
+ O => gray_enc(3)
+ );
+\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => src_in_bin(5),
+ I1 => src_in_bin(4),
+ O => gray_enc(4)
+ );
+\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => src_clk,
+ CE => '1',
+ D => gray_enc(0),
+ Q => async_path(0),
+ R => '0'
+ );
+\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => src_clk,
+ CE => '1',
+ D => gray_enc(1),
+ Q => async_path(1),
+ R => '0'
+ );
+\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => src_clk,
+ CE => '1',
+ D => gray_enc(2),
+ Q => async_path(2),
+ R => '0'
+ );
+\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => src_clk,
+ CE => '1',
+ D => gray_enc(3),
+ Q => async_path(3),
+ R => '0'
+ );
+\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => src_clk,
+ CE => '1',
+ D => gray_enc(4),
+ Q => async_path(4),
+ R => '0'
+ );
+\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => src_clk,
+ CE => '1',
+ D => src_in_bin(5),
+ Q => async_path(5),
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity \fifo_generator_fe_xpm_cdc_gray__2\ is
+ port (
+ src_clk : in STD_LOGIC;
+ src_in_bin : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ dest_clk : in STD_LOGIC;
+ dest_out_bin : out STD_LOGIC_VECTOR ( 5 downto 0 )
+ );
+ attribute DEST_SYNC_FF : integer;
+ attribute DEST_SYNC_FF of \fifo_generator_fe_xpm_cdc_gray__2\ : entity is 2;
+ attribute INIT_SYNC_FF : integer;
+ attribute INIT_SYNC_FF of \fifo_generator_fe_xpm_cdc_gray__2\ : entity is 0;
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of \fifo_generator_fe_xpm_cdc_gray__2\ : entity is "xpm_cdc_gray";
+ attribute REG_OUTPUT : integer;
+ attribute REG_OUTPUT of \fifo_generator_fe_xpm_cdc_gray__2\ : entity is 1;
+ attribute SIM_ASSERT_CHK : integer;
+ attribute SIM_ASSERT_CHK of \fifo_generator_fe_xpm_cdc_gray__2\ : entity is 0;
+ attribute SIM_LOSSLESS_GRAY_CHK : integer;
+ attribute SIM_LOSSLESS_GRAY_CHK of \fifo_generator_fe_xpm_cdc_gray__2\ : entity is 0;
+ attribute VERSION : integer;
+ attribute VERSION of \fifo_generator_fe_xpm_cdc_gray__2\ : entity is 0;
+ attribute WIDTH : integer;
+ attribute WIDTH of \fifo_generator_fe_xpm_cdc_gray__2\ : entity is 6;
+ attribute XPM_MODULE : string;
+ attribute XPM_MODULE of \fifo_generator_fe_xpm_cdc_gray__2\ : entity is "TRUE";
+ attribute is_du_within_envelope : string;
+ attribute is_du_within_envelope of \fifo_generator_fe_xpm_cdc_gray__2\ : entity is "true";
+ attribute keep_hierarchy : string;
+ attribute keep_hierarchy of \fifo_generator_fe_xpm_cdc_gray__2\ : entity is "true";
+ attribute xpm_cdc : string;
+ attribute xpm_cdc of \fifo_generator_fe_xpm_cdc_gray__2\ : entity is "GRAY";
+end \fifo_generator_fe_xpm_cdc_gray__2\;
+
+architecture STRUCTURE of \fifo_generator_fe_xpm_cdc_gray__2\ is
+ signal async_path : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal binval : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
+ attribute RTL_KEEP : string;
+ attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
+ attribute async_reg : string;
+ attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
+ attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
+ signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
+ attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
+ attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
+ attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
+ signal gray_enc : STD_LOGIC_VECTOR ( 4 downto 0 );
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
+ attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true;
+ attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true";
+ attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair1";
+begin
+\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => async_path(0),
+ Q => \dest_graysync_ff[0]\(0),
+ R => '0'
+ );
+\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => async_path(1),
+ Q => \dest_graysync_ff[0]\(1),
+ R => '0'
+ );
+\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => async_path(2),
+ Q => \dest_graysync_ff[0]\(2),
+ R => '0'
+ );
+\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => async_path(3),
+ Q => \dest_graysync_ff[0]\(3),
+ R => '0'
+ );
+\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => async_path(4),
+ Q => \dest_graysync_ff[0]\(4),
+ R => '0'
+ );
+\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => async_path(5),
+ Q => \dest_graysync_ff[0]\(5),
+ R => '0'
+ );
+\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => \dest_graysync_ff[0]\(0),
+ Q => \dest_graysync_ff[1]\(0),
+ R => '0'
+ );
+\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => \dest_graysync_ff[0]\(1),
+ Q => \dest_graysync_ff[1]\(1),
+ R => '0'
+ );
+\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => \dest_graysync_ff[0]\(2),
+ Q => \dest_graysync_ff[1]\(2),
+ R => '0'
+ );
+\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => \dest_graysync_ff[0]\(3),
+ Q => \dest_graysync_ff[1]\(3),
+ R => '0'
+ );
+\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => \dest_graysync_ff[0]\(4),
+ Q => \dest_graysync_ff[1]\(4),
+ R => '0'
+ );
+\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => \dest_graysync_ff[0]\(5),
+ Q => \dest_graysync_ff[1]\(5),
+ R => '0'
+ );
+\dest_out_bin_ff[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"6996966996696996"
+ )
+ port map (
+ I0 => \dest_graysync_ff[1]\(0),
+ I1 => \dest_graysync_ff[1]\(2),
+ I2 => \dest_graysync_ff[1]\(4),
+ I3 => \dest_graysync_ff[1]\(5),
+ I4 => \dest_graysync_ff[1]\(3),
+ I5 => \dest_graysync_ff[1]\(1),
+ O => binval(0)
+ );
+\dest_out_bin_ff[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"96696996"
+ )
+ port map (
+ I0 => \dest_graysync_ff[1]\(1),
+ I1 => \dest_graysync_ff[1]\(3),
+ I2 => \dest_graysync_ff[1]\(5),
+ I3 => \dest_graysync_ff[1]\(4),
+ I4 => \dest_graysync_ff[1]\(2),
+ O => binval(1)
+ );
+\dest_out_bin_ff[2]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"6996"
+ )
+ port map (
+ I0 => \dest_graysync_ff[1]\(2),
+ I1 => \dest_graysync_ff[1]\(4),
+ I2 => \dest_graysync_ff[1]\(5),
+ I3 => \dest_graysync_ff[1]\(3),
+ O => binval(2)
+ );
+\dest_out_bin_ff[3]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"96"
+ )
+ port map (
+ I0 => \dest_graysync_ff[1]\(3),
+ I1 => \dest_graysync_ff[1]\(5),
+ I2 => \dest_graysync_ff[1]\(4),
+ O => binval(3)
+ );
+\dest_out_bin_ff[4]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => \dest_graysync_ff[1]\(4),
+ I1 => \dest_graysync_ff[1]\(5),
+ O => binval(4)
+ );
+\dest_out_bin_ff_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => binval(0),
+ Q => dest_out_bin(0),
+ R => '0'
+ );
+\dest_out_bin_ff_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => binval(1),
+ Q => dest_out_bin(1),
+ R => '0'
+ );
+\dest_out_bin_ff_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => binval(2),
+ Q => dest_out_bin(2),
+ R => '0'
+ );
+\dest_out_bin_ff_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => binval(3),
+ Q => dest_out_bin(3),
+ R => '0'
+ );
+\dest_out_bin_ff_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => binval(4),
+ Q => dest_out_bin(4),
+ R => '0'
+ );
+\dest_out_bin_ff_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => \dest_graysync_ff[1]\(5),
+ Q => dest_out_bin(5),
+ R => '0'
+ );
+\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => src_in_bin(1),
+ I1 => src_in_bin(0),
+ O => gray_enc(0)
+ );
+\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => src_in_bin(2),
+ I1 => src_in_bin(1),
+ O => gray_enc(1)
+ );
+\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => src_in_bin(3),
+ I1 => src_in_bin(2),
+ O => gray_enc(2)
+ );
+\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => src_in_bin(4),
+ I1 => src_in_bin(3),
+ O => gray_enc(3)
+ );
+\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"6"
+ )
+ port map (
+ I0 => src_in_bin(5),
+ I1 => src_in_bin(4),
+ O => gray_enc(4)
+ );
+\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => src_clk,
+ CE => '1',
+ D => gray_enc(0),
+ Q => async_path(0),
+ R => '0'
+ );
+\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => src_clk,
+ CE => '1',
+ D => gray_enc(1),
+ Q => async_path(1),
+ R => '0'
+ );
+\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => src_clk,
+ CE => '1',
+ D => gray_enc(2),
+ Q => async_path(2),
+ R => '0'
+ );
+\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => src_clk,
+ CE => '1',
+ D => gray_enc(3),
+ Q => async_path(3),
+ R => '0'
+ );
+\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => src_clk,
+ CE => '1',
+ D => gray_enc(4),
+ Q => async_path(4),
+ R => '0'
+ );
+\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => src_clk,
+ CE => '1',
+ D => src_in_bin(5),
+ Q => async_path(5),
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity fifo_generator_fe_xpm_cdc_single is
+ port (
+ src_clk : in STD_LOGIC;
+ src_in : in STD_LOGIC;
+ dest_clk : in STD_LOGIC;
+ dest_out : out STD_LOGIC
+ );
+ attribute DEST_SYNC_FF : integer;
+ attribute DEST_SYNC_FF of fifo_generator_fe_xpm_cdc_single : entity is 5;
+ attribute INIT_SYNC_FF : integer;
+ attribute INIT_SYNC_FF of fifo_generator_fe_xpm_cdc_single : entity is 0;
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of fifo_generator_fe_xpm_cdc_single : entity is "xpm_cdc_single";
+ attribute SIM_ASSERT_CHK : integer;
+ attribute SIM_ASSERT_CHK of fifo_generator_fe_xpm_cdc_single : entity is 0;
+ attribute SRC_INPUT_REG : integer;
+ attribute SRC_INPUT_REG of fifo_generator_fe_xpm_cdc_single : entity is 0;
+ attribute VERSION : integer;
+ attribute VERSION of fifo_generator_fe_xpm_cdc_single : entity is 0;
+ attribute XPM_MODULE : string;
+ attribute XPM_MODULE of fifo_generator_fe_xpm_cdc_single : entity is "TRUE";
+ attribute is_du_within_envelope : string;
+ attribute is_du_within_envelope of fifo_generator_fe_xpm_cdc_single : entity is "true";
+ attribute keep_hierarchy : string;
+ attribute keep_hierarchy of fifo_generator_fe_xpm_cdc_single : entity is "true";
+ attribute xpm_cdc : string;
+ attribute xpm_cdc of fifo_generator_fe_xpm_cdc_single : entity is "SINGLE";
+end fifo_generator_fe_xpm_cdc_single;
+
+architecture STRUCTURE of fifo_generator_fe_xpm_cdc_single is
+ signal syncstages_ff : STD_LOGIC_VECTOR ( 4 downto 0 );
+ attribute RTL_KEEP : string;
+ attribute RTL_KEEP of syncstages_ff : signal is "true";
+ attribute async_reg : string;
+ attribute async_reg of syncstages_ff : signal is "true";
+ attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[3]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[3]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[3]\ : label is "SINGLE";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[4]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[4]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[4]\ : label is "SINGLE";
+begin
+ dest_out <= syncstages_ff(4);
+\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => src_in,
+ Q => syncstages_ff(0),
+ R => '0'
+ );
+\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(0),
+ Q => syncstages_ff(1),
+ R => '0'
+ );
+\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(1),
+ Q => syncstages_ff(2),
+ R => '0'
+ );
+\syncstages_ff_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(2),
+ Q => syncstages_ff(3),
+ R => '0'
+ );
+\syncstages_ff_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(3),
+ Q => syncstages_ff(4),
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity \fifo_generator_fe_xpm_cdc_single__2\ is
+ port (
+ src_clk : in STD_LOGIC;
+ src_in : in STD_LOGIC;
+ dest_clk : in STD_LOGIC;
+ dest_out : out STD_LOGIC
+ );
+ attribute DEST_SYNC_FF : integer;
+ attribute DEST_SYNC_FF of \fifo_generator_fe_xpm_cdc_single__2\ : entity is 5;
+ attribute INIT_SYNC_FF : integer;
+ attribute INIT_SYNC_FF of \fifo_generator_fe_xpm_cdc_single__2\ : entity is 0;
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of \fifo_generator_fe_xpm_cdc_single__2\ : entity is "xpm_cdc_single";
+ attribute SIM_ASSERT_CHK : integer;
+ attribute SIM_ASSERT_CHK of \fifo_generator_fe_xpm_cdc_single__2\ : entity is 0;
+ attribute SRC_INPUT_REG : integer;
+ attribute SRC_INPUT_REG of \fifo_generator_fe_xpm_cdc_single__2\ : entity is 0;
+ attribute VERSION : integer;
+ attribute VERSION of \fifo_generator_fe_xpm_cdc_single__2\ : entity is 0;
+ attribute XPM_MODULE : string;
+ attribute XPM_MODULE of \fifo_generator_fe_xpm_cdc_single__2\ : entity is "TRUE";
+ attribute is_du_within_envelope : string;
+ attribute is_du_within_envelope of \fifo_generator_fe_xpm_cdc_single__2\ : entity is "true";
+ attribute keep_hierarchy : string;
+ attribute keep_hierarchy of \fifo_generator_fe_xpm_cdc_single__2\ : entity is "true";
+ attribute xpm_cdc : string;
+ attribute xpm_cdc of \fifo_generator_fe_xpm_cdc_single__2\ : entity is "SINGLE";
+end \fifo_generator_fe_xpm_cdc_single__2\;
+
+architecture STRUCTURE of \fifo_generator_fe_xpm_cdc_single__2\ is
+ signal syncstages_ff : STD_LOGIC_VECTOR ( 4 downto 0 );
+ attribute RTL_KEEP : string;
+ attribute RTL_KEEP of syncstages_ff : signal is "true";
+ attribute async_reg : string;
+ attribute async_reg of syncstages_ff : signal is "true";
+ attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[3]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[3]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[3]\ : label is "SINGLE";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[4]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[4]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[4]\ : label is "SINGLE";
+begin
+ dest_out <= syncstages_ff(4);
+\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => src_in,
+ Q => syncstages_ff(0),
+ R => '0'
+ );
+\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(0),
+ Q => syncstages_ff(1),
+ R => '0'
+ );
+\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(1),
+ Q => syncstages_ff(2),
+ R => '0'
+ );
+\syncstages_ff_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(2),
+ Q => syncstages_ff(3),
+ R => '0'
+ );
+\syncstages_ff_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(3),
+ Q => syncstages_ff(4),
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity fifo_generator_fe_xpm_cdc_sync_rst is
+ port (
+ src_rst : in STD_LOGIC;
+ dest_clk : in STD_LOGIC;
+ dest_rst : out STD_LOGIC
+ );
+ attribute DEF_VAL : string;
+ attribute DEF_VAL of fifo_generator_fe_xpm_cdc_sync_rst : entity is "1'b1";
+ attribute DEST_SYNC_FF : integer;
+ attribute DEST_SYNC_FF of fifo_generator_fe_xpm_cdc_sync_rst : entity is 5;
+ attribute INIT : string;
+ attribute INIT of fifo_generator_fe_xpm_cdc_sync_rst : entity is "1";
+ attribute INIT_SYNC_FF : integer;
+ attribute INIT_SYNC_FF of fifo_generator_fe_xpm_cdc_sync_rst : entity is 0;
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of fifo_generator_fe_xpm_cdc_sync_rst : entity is "xpm_cdc_sync_rst";
+ attribute SIM_ASSERT_CHK : integer;
+ attribute SIM_ASSERT_CHK of fifo_generator_fe_xpm_cdc_sync_rst : entity is 0;
+ attribute VERSION : integer;
+ attribute VERSION of fifo_generator_fe_xpm_cdc_sync_rst : entity is 0;
+ attribute XPM_MODULE : string;
+ attribute XPM_MODULE of fifo_generator_fe_xpm_cdc_sync_rst : entity is "TRUE";
+ attribute is_du_within_envelope : string;
+ attribute is_du_within_envelope of fifo_generator_fe_xpm_cdc_sync_rst : entity is "true";
+ attribute keep_hierarchy : string;
+ attribute keep_hierarchy of fifo_generator_fe_xpm_cdc_sync_rst : entity is "true";
+ attribute xpm_cdc : string;
+ attribute xpm_cdc of fifo_generator_fe_xpm_cdc_sync_rst : entity is "SYNC_RST";
+end fifo_generator_fe_xpm_cdc_sync_rst;
+
+architecture STRUCTURE of fifo_generator_fe_xpm_cdc_sync_rst is
+ signal syncstages_ff : STD_LOGIC_VECTOR ( 4 downto 0 );
+ attribute RTL_KEEP : string;
+ attribute RTL_KEEP of syncstages_ff : signal is "true";
+ attribute async_reg : string;
+ attribute async_reg of syncstages_ff : signal is "true";
+ attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SYNC_RST";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[3]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[3]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[3]\ : label is "SYNC_RST";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[4]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[4]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[4]\ : label is "SYNC_RST";
+begin
+ dest_rst <= syncstages_ff(4);
+\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => src_rst,
+ Q => syncstages_ff(0),
+ R => '0'
+ );
+\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(0),
+ Q => syncstages_ff(1),
+ R => '0'
+ );
+\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(1),
+ Q => syncstages_ff(2),
+ R => '0'
+ );
+\syncstages_ff_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(2),
+ Q => syncstages_ff(3),
+ R => '0'
+ );
+\syncstages_ff_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(3),
+ Q => syncstages_ff(4),
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity \fifo_generator_fe_xpm_cdc_sync_rst__2\ is
+ port (
+ src_rst : in STD_LOGIC;
+ dest_clk : in STD_LOGIC;
+ dest_rst : out STD_LOGIC
+ );
+ attribute DEF_VAL : string;
+ attribute DEF_VAL of \fifo_generator_fe_xpm_cdc_sync_rst__2\ : entity is "1'b1";
+ attribute DEST_SYNC_FF : integer;
+ attribute DEST_SYNC_FF of \fifo_generator_fe_xpm_cdc_sync_rst__2\ : entity is 5;
+ attribute INIT : string;
+ attribute INIT of \fifo_generator_fe_xpm_cdc_sync_rst__2\ : entity is "1";
+ attribute INIT_SYNC_FF : integer;
+ attribute INIT_SYNC_FF of \fifo_generator_fe_xpm_cdc_sync_rst__2\ : entity is 0;
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of \fifo_generator_fe_xpm_cdc_sync_rst__2\ : entity is "xpm_cdc_sync_rst";
+ attribute SIM_ASSERT_CHK : integer;
+ attribute SIM_ASSERT_CHK of \fifo_generator_fe_xpm_cdc_sync_rst__2\ : entity is 0;
+ attribute VERSION : integer;
+ attribute VERSION of \fifo_generator_fe_xpm_cdc_sync_rst__2\ : entity is 0;
+ attribute XPM_MODULE : string;
+ attribute XPM_MODULE of \fifo_generator_fe_xpm_cdc_sync_rst__2\ : entity is "TRUE";
+ attribute is_du_within_envelope : string;
+ attribute is_du_within_envelope of \fifo_generator_fe_xpm_cdc_sync_rst__2\ : entity is "true";
+ attribute keep_hierarchy : string;
+ attribute keep_hierarchy of \fifo_generator_fe_xpm_cdc_sync_rst__2\ : entity is "true";
+ attribute xpm_cdc : string;
+ attribute xpm_cdc of \fifo_generator_fe_xpm_cdc_sync_rst__2\ : entity is "SYNC_RST";
+end \fifo_generator_fe_xpm_cdc_sync_rst__2\;
+
+architecture STRUCTURE of \fifo_generator_fe_xpm_cdc_sync_rst__2\ is
+ signal syncstages_ff : STD_LOGIC_VECTOR ( 4 downto 0 );
+ attribute RTL_KEEP : string;
+ attribute RTL_KEEP of syncstages_ff : signal is "true";
+ attribute async_reg : string;
+ attribute async_reg of syncstages_ff : signal is "true";
+ attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST";
+ attribute ASYNC_REG_boolean : boolean;
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
+ attribute KEEP : string;
+ attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SYNC_RST";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[3]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[3]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[3]\ : label is "SYNC_RST";
+ attribute ASYNC_REG_boolean of \syncstages_ff_reg[4]\ : label is std.standard.true;
+ attribute KEEP of \syncstages_ff_reg[4]\ : label is "true";
+ attribute XPM_CDC of \syncstages_ff_reg[4]\ : label is "SYNC_RST";
+begin
+ dest_rst <= syncstages_ff(4);
+\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => src_rst,
+ Q => syncstages_ff(0),
+ R => '0'
+ );
+\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(0),
+ Q => syncstages_ff(1),
+ R => '0'
+ );
+\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(1),
+ Q => syncstages_ff(2),
+ R => '0'
+ );
+\syncstages_ff_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(2),
+ Q => syncstages_ff(3),
+ R => '0'
+ );
+\syncstages_ff_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '1'
+ )
+ port map (
+ C => dest_clk,
+ CE => '1',
+ D => syncstages_ff(3),
+ Q => syncstages_ff(4),
+ R => '0'
+ );
+end STRUCTURE;
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+
+`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect key_keyowner="Xilinx", key_keyname="xilinxt_2023_11", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=384)
+`protect key_block
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+`protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect data_method = "AES128-CBC"
+`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 154560)
+`protect data_block
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+`protect end_protected
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity fifo_generator_fe is
+ port (
+ rst : in STD_LOGIC;
+ wr_clk : in STD_LOGIC;
+ rd_clk : in STD_LOGIC;
+ din : in STD_LOGIC_VECTOR ( 35 downto 0 );
+ wr_en : in STD_LOGIC;
+ rd_en : in STD_LOGIC;
+ dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
+ full : out STD_LOGIC;
+ empty : out STD_LOGIC;
+ prog_full : out STD_LOGIC;
+ prog_empty : out STD_LOGIC;
+ wr_rst_busy : out STD_LOGIC;
+ rd_rst_busy : out STD_LOGIC
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of fifo_generator_fe : entity is true;
+ attribute CHECK_LICENSE_TYPE : string;
+ attribute CHECK_LICENSE_TYPE of fifo_generator_fe : entity is "fifo_generator_fe,fifo_generator_v13_2_10,{}";
+ attribute downgradeipidentifiedwarnings : string;
+ attribute downgradeipidentifiedwarnings of fifo_generator_fe : entity is "yes";
+ attribute x_core_info : string;
+ attribute x_core_info of fifo_generator_fe : entity is "fifo_generator_v13_2_10,Vivado 2024.1";
+end fifo_generator_fe;
+
+architecture STRUCTURE of fifo_generator_fe is
+ signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
+ signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
+ signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
+ signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
+ signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
+ signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
+ signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
+ signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
+ signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
+ signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
+ signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
+ attribute C_ADD_NGC_CONSTRAINT : integer;
+ attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
+ attribute C_APPLICATION_TYPE_AXIS : integer;
+ attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
+ attribute C_APPLICATION_TYPE_RACH : integer;
+ attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
+ attribute C_APPLICATION_TYPE_RDCH : integer;
+ attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
+ attribute C_APPLICATION_TYPE_WACH : integer;
+ attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
+ attribute C_APPLICATION_TYPE_WDCH : integer;
+ attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
+ attribute C_APPLICATION_TYPE_WRCH : integer;
+ attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
+ attribute C_AXIS_TDATA_WIDTH : integer;
+ attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
+ attribute C_AXIS_TDEST_WIDTH : integer;
+ attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
+ attribute C_AXIS_TID_WIDTH : integer;
+ attribute C_AXIS_TID_WIDTH of U0 : label is 1;
+ attribute C_AXIS_TKEEP_WIDTH : integer;
+ attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
+ attribute C_AXIS_TSTRB_WIDTH : integer;
+ attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
+ attribute C_AXIS_TUSER_WIDTH : integer;
+ attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
+ attribute C_AXIS_TYPE : integer;
+ attribute C_AXIS_TYPE of U0 : label is 0;
+ attribute C_AXI_ADDR_WIDTH : integer;
+ attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
+ attribute C_AXI_ARUSER_WIDTH : integer;
+ attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
+ attribute C_AXI_AWUSER_WIDTH : integer;
+ attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
+ attribute C_AXI_BUSER_WIDTH : integer;
+ attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
+ attribute C_AXI_DATA_WIDTH : integer;
+ attribute C_AXI_DATA_WIDTH of U0 : label is 64;
+ attribute C_AXI_ID_WIDTH : integer;
+ attribute C_AXI_ID_WIDTH of U0 : label is 1;
+ attribute C_AXI_LEN_WIDTH : integer;
+ attribute C_AXI_LEN_WIDTH of U0 : label is 8;
+ attribute C_AXI_LOCK_WIDTH : integer;
+ attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
+ attribute C_AXI_RUSER_WIDTH : integer;
+ attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
+ attribute C_AXI_TYPE : integer;
+ attribute C_AXI_TYPE of U0 : label is 1;
+ attribute C_AXI_WUSER_WIDTH : integer;
+ attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
+ attribute C_COMMON_CLOCK : integer;
+ attribute C_COMMON_CLOCK of U0 : label is 0;
+ attribute C_COUNT_TYPE : integer;
+ attribute C_COUNT_TYPE of U0 : label is 0;
+ attribute C_DATA_COUNT_WIDTH : integer;
+ attribute C_DATA_COUNT_WIDTH of U0 : label is 6;
+ attribute C_DEFAULT_VALUE : string;
+ attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
+ attribute C_DIN_WIDTH : integer;
+ attribute C_DIN_WIDTH of U0 : label is 36;
+ attribute C_DIN_WIDTH_AXIS : integer;
+ attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
+ attribute C_DIN_WIDTH_RACH : integer;
+ attribute C_DIN_WIDTH_RACH of U0 : label is 32;
+ attribute C_DIN_WIDTH_RDCH : integer;
+ attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
+ attribute C_DIN_WIDTH_WACH : integer;
+ attribute C_DIN_WIDTH_WACH of U0 : label is 1;
+ attribute C_DIN_WIDTH_WDCH : integer;
+ attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
+ attribute C_DIN_WIDTH_WRCH : integer;
+ attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
+ attribute C_DOUT_RST_VAL : string;
+ attribute C_DOUT_RST_VAL of U0 : label is "0";
+ attribute C_DOUT_WIDTH : integer;
+ attribute C_DOUT_WIDTH of U0 : label is 36;
+ attribute C_ENABLE_RLOCS : integer;
+ attribute C_ENABLE_RLOCS of U0 : label is 0;
+ attribute C_ENABLE_RST_SYNC : integer;
+ attribute C_ENABLE_RST_SYNC of U0 : label is 1;
+ attribute C_EN_SAFETY_CKT : integer;
+ attribute C_EN_SAFETY_CKT of U0 : label is 1;
+ attribute C_ERROR_INJECTION_TYPE : integer;
+ attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
+ attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
+ attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
+ attribute C_ERROR_INJECTION_TYPE_RACH : integer;
+ attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
+ attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
+ attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
+ attribute C_ERROR_INJECTION_TYPE_WACH : integer;
+ attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
+ attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
+ attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
+ attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
+ attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
+ attribute C_FAMILY : string;
+ attribute C_FAMILY of U0 : label is "kintexu";
+ attribute C_FULL_FLAGS_RST_VAL : integer;
+ attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
+ attribute C_HAS_ALMOST_EMPTY : integer;
+ attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
+ attribute C_HAS_ALMOST_FULL : integer;
+ attribute C_HAS_ALMOST_FULL of U0 : label is 0;
+ attribute C_HAS_AXIS_TDATA : integer;
+ attribute C_HAS_AXIS_TDATA of U0 : label is 1;
+ attribute C_HAS_AXIS_TDEST : integer;
+ attribute C_HAS_AXIS_TDEST of U0 : label is 0;
+ attribute C_HAS_AXIS_TID : integer;
+ attribute C_HAS_AXIS_TID of U0 : label is 0;
+ attribute C_HAS_AXIS_TKEEP : integer;
+ attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
+ attribute C_HAS_AXIS_TLAST : integer;
+ attribute C_HAS_AXIS_TLAST of U0 : label is 0;
+ attribute C_HAS_AXIS_TREADY : integer;
+ attribute C_HAS_AXIS_TREADY of U0 : label is 1;
+ attribute C_HAS_AXIS_TSTRB : integer;
+ attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
+ attribute C_HAS_AXIS_TUSER : integer;
+ attribute C_HAS_AXIS_TUSER of U0 : label is 1;
+ attribute C_HAS_AXI_ARUSER : integer;
+ attribute C_HAS_AXI_ARUSER of U0 : label is 0;
+ attribute C_HAS_AXI_AWUSER : integer;
+ attribute C_HAS_AXI_AWUSER of U0 : label is 0;
+ attribute C_HAS_AXI_BUSER : integer;
+ attribute C_HAS_AXI_BUSER of U0 : label is 0;
+ attribute C_HAS_AXI_ID : integer;
+ attribute C_HAS_AXI_ID of U0 : label is 0;
+ attribute C_HAS_AXI_RD_CHANNEL : integer;
+ attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
+ attribute C_HAS_AXI_RUSER : integer;
+ attribute C_HAS_AXI_RUSER of U0 : label is 0;
+ attribute C_HAS_AXI_WR_CHANNEL : integer;
+ attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
+ attribute C_HAS_AXI_WUSER : integer;
+ attribute C_HAS_AXI_WUSER of U0 : label is 0;
+ attribute C_HAS_BACKUP : integer;
+ attribute C_HAS_BACKUP of U0 : label is 0;
+ attribute C_HAS_DATA_COUNT : integer;
+ attribute C_HAS_DATA_COUNT of U0 : label is 0;
+ attribute C_HAS_DATA_COUNTS_AXIS : integer;
+ attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
+ attribute C_HAS_DATA_COUNTS_RACH : integer;
+ attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
+ attribute C_HAS_DATA_COUNTS_RDCH : integer;
+ attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
+ attribute C_HAS_DATA_COUNTS_WACH : integer;
+ attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
+ attribute C_HAS_DATA_COUNTS_WDCH : integer;
+ attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
+ attribute C_HAS_DATA_COUNTS_WRCH : integer;
+ attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
+ attribute C_HAS_INT_CLK : integer;
+ attribute C_HAS_INT_CLK of U0 : label is 0;
+ attribute C_HAS_MASTER_CE : integer;
+ attribute C_HAS_MASTER_CE of U0 : label is 0;
+ attribute C_HAS_MEMINIT_FILE : integer;
+ attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
+ attribute C_HAS_OVERFLOW : integer;
+ attribute C_HAS_OVERFLOW of U0 : label is 0;
+ attribute C_HAS_PROG_FLAGS_AXIS : integer;
+ attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
+ attribute C_HAS_PROG_FLAGS_RACH : integer;
+ attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
+ attribute C_HAS_PROG_FLAGS_RDCH : integer;
+ attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
+ attribute C_HAS_PROG_FLAGS_WACH : integer;
+ attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
+ attribute C_HAS_PROG_FLAGS_WDCH : integer;
+ attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
+ attribute C_HAS_PROG_FLAGS_WRCH : integer;
+ attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
+ attribute C_HAS_RD_DATA_COUNT : integer;
+ attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
+ attribute C_HAS_RD_RST : integer;
+ attribute C_HAS_RD_RST of U0 : label is 0;
+ attribute C_HAS_RST : integer;
+ attribute C_HAS_RST of U0 : label is 1;
+ attribute C_HAS_SLAVE_CE : integer;
+ attribute C_HAS_SLAVE_CE of U0 : label is 0;
+ attribute C_HAS_SRST : integer;
+ attribute C_HAS_SRST of U0 : label is 0;
+ attribute C_HAS_UNDERFLOW : integer;
+ attribute C_HAS_UNDERFLOW of U0 : label is 0;
+ attribute C_HAS_VALID : integer;
+ attribute C_HAS_VALID of U0 : label is 0;
+ attribute C_HAS_WR_ACK : integer;
+ attribute C_HAS_WR_ACK of U0 : label is 0;
+ attribute C_HAS_WR_DATA_COUNT : integer;
+ attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
+ attribute C_HAS_WR_RST : integer;
+ attribute C_HAS_WR_RST of U0 : label is 0;
+ attribute C_IMPLEMENTATION_TYPE : integer;
+ attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
+ attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
+ attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
+ attribute C_IMPLEMENTATION_TYPE_RACH : integer;
+ attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
+ attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
+ attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
+ attribute C_IMPLEMENTATION_TYPE_WACH : integer;
+ attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
+ attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
+ attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
+ attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
+ attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
+ attribute C_INIT_WR_PNTR_VAL : integer;
+ attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
+ attribute C_INTERFACE_TYPE : integer;
+ attribute C_INTERFACE_TYPE of U0 : label is 0;
+ attribute C_MEMORY_TYPE : integer;
+ attribute C_MEMORY_TYPE of U0 : label is 1;
+ attribute C_MIF_FILE_NAME : string;
+ attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
+ attribute C_MSGON_VAL : integer;
+ attribute C_MSGON_VAL of U0 : label is 1;
+ attribute C_OPTIMIZATION_MODE : integer;
+ attribute C_OPTIMIZATION_MODE of U0 : label is 0;
+ attribute C_OVERFLOW_LOW : integer;
+ attribute C_OVERFLOW_LOW of U0 : label is 0;
+ attribute C_POWER_SAVING_MODE : integer;
+ attribute C_POWER_SAVING_MODE of U0 : label is 0;
+ attribute C_PRELOAD_LATENCY : integer;
+ attribute C_PRELOAD_LATENCY of U0 : label is 2;
+ attribute C_PRELOAD_REGS : integer;
+ attribute C_PRELOAD_REGS of U0 : label is 1;
+ attribute C_PRIM_FIFO_TYPE : string;
+ attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
+ attribute C_PRIM_FIFO_TYPE_AXIS : string;
+ attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
+ attribute C_PRIM_FIFO_TYPE_RACH : string;
+ attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
+ attribute C_PRIM_FIFO_TYPE_RDCH : string;
+ attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "512x72";
+ attribute C_PRIM_FIFO_TYPE_WACH : string;
+ attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
+ attribute C_PRIM_FIFO_TYPE_WDCH : string;
+ attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "512x72";
+ attribute C_PRIM_FIFO_TYPE_WRCH : string;
+ attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
+ attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
+ attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 6;
+ attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
+ attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
+ attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
+ attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
+ attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
+ attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
+ attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
+ attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
+ attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
+ attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
+ attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
+ attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
+ attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
+ attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 12;
+ attribute C_PROG_EMPTY_TYPE : integer;
+ attribute C_PROG_EMPTY_TYPE of U0 : label is 2;
+ attribute C_PROG_EMPTY_TYPE_AXIS : integer;
+ attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
+ attribute C_PROG_EMPTY_TYPE_RACH : integer;
+ attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
+ attribute C_PROG_EMPTY_TYPE_RDCH : integer;
+ attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
+ attribute C_PROG_EMPTY_TYPE_WACH : integer;
+ attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
+ attribute C_PROG_EMPTY_TYPE_WDCH : integer;
+ attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
+ attribute C_PROG_EMPTY_TYPE_WRCH : integer;
+ attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
+ attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
+ attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 50;
+ attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
+ attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
+ attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
+ attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
+ attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
+ attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
+ attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
+ attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
+ attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
+ attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
+ attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
+ attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
+ attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
+ attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 45;
+ attribute C_PROG_FULL_TYPE : integer;
+ attribute C_PROG_FULL_TYPE of U0 : label is 2;
+ attribute C_PROG_FULL_TYPE_AXIS : integer;
+ attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
+ attribute C_PROG_FULL_TYPE_RACH : integer;
+ attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
+ attribute C_PROG_FULL_TYPE_RDCH : integer;
+ attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
+ attribute C_PROG_FULL_TYPE_WACH : integer;
+ attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
+ attribute C_PROG_FULL_TYPE_WDCH : integer;
+ attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
+ attribute C_PROG_FULL_TYPE_WRCH : integer;
+ attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
+ attribute C_RACH_TYPE : integer;
+ attribute C_RACH_TYPE of U0 : label is 0;
+ attribute C_RDCH_TYPE : integer;
+ attribute C_RDCH_TYPE of U0 : label is 0;
+ attribute C_RD_DATA_COUNT_WIDTH : integer;
+ attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 6;
+ attribute C_RD_DEPTH : integer;
+ attribute C_RD_DEPTH of U0 : label is 64;
+ attribute C_RD_FREQ : integer;
+ attribute C_RD_FREQ of U0 : label is 1;
+ attribute C_RD_PNTR_WIDTH : integer;
+ attribute C_RD_PNTR_WIDTH of U0 : label is 6;
+ attribute C_REG_SLICE_MODE_AXIS : integer;
+ attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
+ attribute C_REG_SLICE_MODE_RACH : integer;
+ attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
+ attribute C_REG_SLICE_MODE_RDCH : integer;
+ attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
+ attribute C_REG_SLICE_MODE_WACH : integer;
+ attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
+ attribute C_REG_SLICE_MODE_WDCH : integer;
+ attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
+ attribute C_REG_SLICE_MODE_WRCH : integer;
+ attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
+ attribute C_SELECT_XPM : integer;
+ attribute C_SELECT_XPM of U0 : label is 0;
+ attribute C_SYNCHRONIZER_STAGE : integer;
+ attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
+ attribute C_UNDERFLOW_LOW : integer;
+ attribute C_UNDERFLOW_LOW of U0 : label is 0;
+ attribute C_USE_COMMON_OVERFLOW : integer;
+ attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
+ attribute C_USE_COMMON_UNDERFLOW : integer;
+ attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
+ attribute C_USE_DEFAULT_SETTINGS : integer;
+ attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
+ attribute C_USE_DOUT_RST : integer;
+ attribute C_USE_DOUT_RST of U0 : label is 1;
+ attribute C_USE_ECC : integer;
+ attribute C_USE_ECC of U0 : label is 0;
+ attribute C_USE_ECC_AXIS : integer;
+ attribute C_USE_ECC_AXIS of U0 : label is 0;
+ attribute C_USE_ECC_RACH : integer;
+ attribute C_USE_ECC_RACH of U0 : label is 0;
+ attribute C_USE_ECC_RDCH : integer;
+ attribute C_USE_ECC_RDCH of U0 : label is 0;
+ attribute C_USE_ECC_WACH : integer;
+ attribute C_USE_ECC_WACH of U0 : label is 0;
+ attribute C_USE_ECC_WDCH : integer;
+ attribute C_USE_ECC_WDCH of U0 : label is 0;
+ attribute C_USE_ECC_WRCH : integer;
+ attribute C_USE_ECC_WRCH of U0 : label is 0;
+ attribute C_USE_EMBEDDED_REG : integer;
+ attribute C_USE_EMBEDDED_REG of U0 : label is 1;
+ attribute C_USE_FIFO16_FLAGS : integer;
+ attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
+ attribute C_USE_FWFT_DATA_COUNT : integer;
+ attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
+ attribute C_USE_PIPELINE_REG : integer;
+ attribute C_USE_PIPELINE_REG of U0 : label is 0;
+ attribute C_VALID_LOW : integer;
+ attribute C_VALID_LOW of U0 : label is 0;
+ attribute C_WACH_TYPE : integer;
+ attribute C_WACH_TYPE of U0 : label is 0;
+ attribute C_WDCH_TYPE : integer;
+ attribute C_WDCH_TYPE of U0 : label is 0;
+ attribute C_WRCH_TYPE : integer;
+ attribute C_WRCH_TYPE of U0 : label is 0;
+ attribute C_WR_ACK_LOW : integer;
+ attribute C_WR_ACK_LOW of U0 : label is 0;
+ attribute C_WR_DATA_COUNT_WIDTH : integer;
+ attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 6;
+ attribute C_WR_DEPTH : integer;
+ attribute C_WR_DEPTH of U0 : label is 64;
+ attribute C_WR_DEPTH_AXIS : integer;
+ attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
+ attribute C_WR_DEPTH_RACH : integer;
+ attribute C_WR_DEPTH_RACH of U0 : label is 16;
+ attribute C_WR_DEPTH_RDCH : integer;
+ attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
+ attribute C_WR_DEPTH_WACH : integer;
+ attribute C_WR_DEPTH_WACH of U0 : label is 16;
+ attribute C_WR_DEPTH_WDCH : integer;
+ attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
+ attribute C_WR_DEPTH_WRCH : integer;
+ attribute C_WR_DEPTH_WRCH of U0 : label is 16;
+ attribute C_WR_FREQ : integer;
+ attribute C_WR_FREQ of U0 : label is 1;
+ attribute C_WR_PNTR_WIDTH : integer;
+ attribute C_WR_PNTR_WIDTH of U0 : label is 6;
+ attribute C_WR_PNTR_WIDTH_AXIS : integer;
+ attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
+ attribute C_WR_PNTR_WIDTH_RACH : integer;
+ attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
+ attribute C_WR_PNTR_WIDTH_RDCH : integer;
+ attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
+ attribute C_WR_PNTR_WIDTH_WACH : integer;
+ attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
+ attribute C_WR_PNTR_WIDTH_WDCH : integer;
+ attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
+ attribute C_WR_PNTR_WIDTH_WRCH : integer;
+ attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
+ attribute C_WR_RESPONSE_LATENCY : integer;
+ attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
+ attribute is_du_within_envelope : string;
+ attribute is_du_within_envelope of U0 : label is "true";
+ attribute x_interface_info : string;
+ attribute x_interface_info of empty : signal is "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
+ attribute x_interface_info of full : signal is "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
+ attribute x_interface_info of rd_clk : signal is "xilinx.com:signal:clock:1.0 read_clk CLK";
+ attribute x_interface_parameter : string;
+ attribute x_interface_parameter of rd_clk : signal is "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+ attribute x_interface_info of rd_en : signal is "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
+ attribute x_interface_info of wr_clk : signal is "xilinx.com:signal:clock:1.0 write_clk CLK";
+ attribute x_interface_parameter of wr_clk : signal is "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+ attribute x_interface_info of wr_en : signal is "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
+ attribute x_interface_info of din : signal is "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
+ attribute x_interface_info of dout : signal is "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
+begin
+U0: entity work.fifo_generator_fe_fifo_generator_v13_2_10
+ port map (
+ almost_empty => NLW_U0_almost_empty_UNCONNECTED,
+ almost_full => NLW_U0_almost_full_UNCONNECTED,
+ axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
+ axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
+ axi_ar_injectdbiterr => '0',
+ axi_ar_injectsbiterr => '0',
+ axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
+ axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
+ axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
+ axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
+ axi_ar_prog_full_thresh(3 downto 0) => B"0000",
+ axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
+ axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
+ axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
+ axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
+ axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
+ axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
+ axi_aw_injectdbiterr => '0',
+ axi_aw_injectsbiterr => '0',
+ axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
+ axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
+ axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
+ axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
+ axi_aw_prog_full_thresh(3 downto 0) => B"0000",
+ axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
+ axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
+ axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
+ axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
+ axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
+ axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
+ axi_b_injectdbiterr => '0',
+ axi_b_injectsbiterr => '0',
+ axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
+ axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
+ axi_b_prog_empty_thresh(3 downto 0) => B"0000",
+ axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
+ axi_b_prog_full_thresh(3 downto 0) => B"0000",
+ axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
+ axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
+ axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
+ axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
+ axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
+ axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
+ axi_r_injectdbiterr => '0',
+ axi_r_injectsbiterr => '0',
+ axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
+ axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
+ axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
+ axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
+ axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
+ axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
+ axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
+ axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
+ axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
+ axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
+ axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
+ axi_w_injectdbiterr => '0',
+ axi_w_injectsbiterr => '0',
+ axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
+ axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
+ axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
+ axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
+ axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
+ axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
+ axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
+ axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
+ axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
+ axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
+ axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
+ axis_injectdbiterr => '0',
+ axis_injectsbiterr => '0',
+ axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
+ axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
+ axis_prog_empty_thresh(9 downto 0) => B"0000000000",
+ axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
+ axis_prog_full_thresh(9 downto 0) => B"0000000000",
+ axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
+ axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
+ axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
+ axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
+ backup => '0',
+ backup_marker => '0',
+ clk => '0',
+ data_count(5 downto 0) => NLW_U0_data_count_UNCONNECTED(5 downto 0),
+ dbiterr => NLW_U0_dbiterr_UNCONNECTED,
+ din(35 downto 0) => din(35 downto 0),
+ dout(35 downto 0) => dout(35 downto 0),
+ empty => empty,
+ full => full,
+ injectdbiterr => '0',
+ injectsbiterr => '0',
+ int_clk => '0',
+ m_aclk => '0',
+ m_aclk_en => '0',
+ m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
+ m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
+ m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
+ m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
+ m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
+ m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
+ m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
+ m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
+ m_axi_arready => '0',
+ m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
+ m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
+ m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
+ m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
+ m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
+ m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
+ m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
+ m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
+ m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
+ m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
+ m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
+ m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
+ m_axi_awready => '0',
+ m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
+ m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
+ m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
+ m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
+ m_axi_bid(0) => '0',
+ m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
+ m_axi_bresp(1 downto 0) => B"00",
+ m_axi_buser(0) => '0',
+ m_axi_bvalid => '0',
+ m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ m_axi_rid(0) => '0',
+ m_axi_rlast => '0',
+ m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
+ m_axi_rresp(1 downto 0) => B"00",
+ m_axi_ruser(0) => '0',
+ m_axi_rvalid => '0',
+ m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
+ m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
+ m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
+ m_axi_wready => '0',
+ m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
+ m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
+ m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
+ m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
+ m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
+ m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
+ m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
+ m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
+ m_axis_tready => '0',
+ m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
+ m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
+ m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
+ overflow => NLW_U0_overflow_UNCONNECTED,
+ prog_empty => prog_empty,
+ prog_empty_thresh(5 downto 0) => B"000000",
+ prog_empty_thresh_assert(5 downto 0) => B"000000",
+ prog_empty_thresh_negate(5 downto 0) => B"000000",
+ prog_full => prog_full,
+ prog_full_thresh(5 downto 0) => B"000000",
+ prog_full_thresh_assert(5 downto 0) => B"000000",
+ prog_full_thresh_negate(5 downto 0) => B"000000",
+ rd_clk => rd_clk,
+ rd_data_count(5 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(5 downto 0),
+ rd_en => rd_en,
+ rd_rst => '0',
+ rd_rst_busy => rd_rst_busy,
+ rst => rst,
+ s_aclk => '0',
+ s_aclk_en => '0',
+ s_aresetn => '0',
+ s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
+ s_axi_arburst(1 downto 0) => B"00",
+ s_axi_arcache(3 downto 0) => B"0000",
+ s_axi_arid(0) => '0',
+ s_axi_arlen(7 downto 0) => B"00000000",
+ s_axi_arlock(0) => '0',
+ s_axi_arprot(2 downto 0) => B"000",
+ s_axi_arqos(3 downto 0) => B"0000",
+ s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
+ s_axi_arregion(3 downto 0) => B"0000",
+ s_axi_arsize(2 downto 0) => B"000",
+ s_axi_aruser(0) => '0',
+ s_axi_arvalid => '0',
+ s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
+ s_axi_awburst(1 downto 0) => B"00",
+ s_axi_awcache(3 downto 0) => B"0000",
+ s_axi_awid(0) => '0',
+ s_axi_awlen(7 downto 0) => B"00000000",
+ s_axi_awlock(0) => '0',
+ s_axi_awprot(2 downto 0) => B"000",
+ s_axi_awqos(3 downto 0) => B"0000",
+ s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
+ s_axi_awregion(3 downto 0) => B"0000",
+ s_axi_awsize(2 downto 0) => B"000",
+ s_axi_awuser(0) => '0',
+ s_axi_awvalid => '0',
+ s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
+ s_axi_bready => '0',
+ s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
+ s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
+ s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
+ s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
+ s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
+ s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
+ s_axi_rready => '0',
+ s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
+ s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
+ s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
+ s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
+ s_axi_wid(0) => '0',
+ s_axi_wlast => '0',
+ s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
+ s_axi_wstrb(7 downto 0) => B"00000000",
+ s_axi_wuser(0) => '0',
+ s_axi_wvalid => '0',
+ s_axis_tdata(7 downto 0) => B"00000000",
+ s_axis_tdest(0) => '0',
+ s_axis_tid(0) => '0',
+ s_axis_tkeep(0) => '0',
+ s_axis_tlast => '0',
+ s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
+ s_axis_tstrb(0) => '0',
+ s_axis_tuser(3 downto 0) => B"0000",
+ s_axis_tvalid => '0',
+ sbiterr => NLW_U0_sbiterr_UNCONNECTED,
+ sleep => '0',
+ srst => '0',
+ underflow => NLW_U0_underflow_UNCONNECTED,
+ valid => NLW_U0_valid_UNCONNECTED,
+ wr_ack => NLW_U0_wr_ack_UNCONNECTED,
+ wr_clk => wr_clk,
+ wr_data_count(5 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(5 downto 0),
+ wr_en => wr_en,
+ wr_rst => '0',
+ wr_rst_busy => wr_rst_busy
+ );
+end STRUCTURE;
diff --git a/sources/ip_cores/sim/ila_gbt_rx_frame_sim_netlist.vhdl b/sources/ip_cores/sim/ila_gbt_rx_frame_sim_netlist.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..6b9c465b141c0505a9b9d6c726dd19c513fd9317
--- /dev/null
+++ b/sources/ip_cores/sim/ila_gbt_rx_frame_sim_netlist.vhdl
@@ -0,0 +1,32 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Wed Jun 12 16:30:55 2024
+-- Host : lbp001app.nikhef.nl running 64-bit unknown
+-- Command : write_vhdl -force -mode synth_stub
+-- /localstore/et/franss/felix/firmware/Projects/FLX712_FMEMU/FLX712_FMEMU.gen/sources_1/ip/ila_gbt_rx_frame/ila_gbt_rx_frame_stub.vhdl
+-- Design : ila_gbt_rx_frame
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xcku115-flvf1924-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+ use IEEE.STD_LOGIC_1164.ALL;
+
+entity ila_gbt_rx_frame is
+ Port (
+ clk : in STD_LOGIC;
+ probe0 : in STD_LOGIC_VECTOR ( 79 downto 0 )
+ );
+
+end ila_gbt_rx_frame;
+
+architecture stub of ila_gbt_rx_frame is
+ attribute syn_black_box : boolean;
+ attribute black_box_pad_pin : string;
+ attribute syn_black_box of stub : architecture is true;
+ attribute black_box_pad_pin of stub : architecture is "clk,probe0[79:0]";
+ attribute x_core_info : string;
+ attribute x_core_info of stub : architecture is "ila,Vivado 2024.1";
+begin
+end;
diff --git a/sources/ip_cores/sim/ila_lti_decoder_sim_netlist.vhdl b/sources/ip_cores/sim/ila_lti_decoder_sim_netlist.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..e8e0c4a04da84fcdaa80e6a8b073dbd99b836d63
--- /dev/null
+++ b/sources/ip_cores/sim/ila_lti_decoder_sim_netlist.vhdl
@@ -0,0 +1,39 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Wed Jun 12 16:30:57 2024
+-- Host : lbp001app.nikhef.nl running 64-bit unknown
+-- Command : write_vhdl -force -mode synth_stub
+-- /localstore/et/franss/felix/firmware/Projects/FLX712_FMEMU/FLX712_FMEMU.gen/sources_1/ip/ila_lti_decoder/ila_lti_decoder_stub.vhdl
+-- Design : ila_lti_decoder
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xcku115-flvf1924-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+ use IEEE.STD_LOGIC_1164.ALL;
+
+entity ila_lti_decoder is
+ Port (
+ clk : in STD_LOGIC;
+ probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+ probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+ probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
+ probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
+ probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
+ probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
+ probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
+ probe7 : in STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+
+end ila_lti_decoder;
+
+architecture stub of ila_lti_decoder is
+ attribute syn_black_box : boolean;
+ attribute black_box_pad_pin : string;
+ attribute syn_black_box of stub : architecture is true;
+ attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0]";
+ attribute x_core_info : string;
+ attribute x_core_info of stub : architecture is "ila,Vivado 2024.1";
+begin
+end;
diff --git a/sources/ip_cores/sim/ila_lti_rx_data_sim_netlist.vhdl b/sources/ip_cores/sim/ila_lti_rx_data_sim_netlist.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..52a2f99506e167884012b89f9f9c74e33cfb891c
--- /dev/null
+++ b/sources/ip_cores/sim/ila_lti_rx_data_sim_netlist.vhdl
@@ -0,0 +1,32 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Wed Jun 12 16:30:55 2024
+-- Host : lbp001app.nikhef.nl running 64-bit unknown
+-- Command : write_vhdl -force -mode synth_stub
+-- /localstore/et/franss/felix/firmware/Projects/FLX712_FMEMU/FLX712_FMEMU.gen/sources_1/ip/ila_lti_rx_data/ila_lti_rx_data_stub.vhdl
+-- Design : ila_lti_rx_data
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xcku115-flvf1924-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+ use IEEE.STD_LOGIC_1164.ALL;
+
+entity ila_lti_rx_data is
+ Port (
+ clk : in STD_LOGIC;
+ probe0 : in STD_LOGIC_VECTOR ( 35 downto 0 )
+ );
+
+end ila_lti_rx_data;
+
+architecture stub of ila_lti_rx_data is
+ attribute syn_black_box : boolean;
+ attribute black_box_pad_pin : string;
+ attribute syn_black_box of stub : architecture is true;
+ attribute black_box_pad_pin of stub : architecture is "clk,probe0[35:0]";
+ attribute x_core_info : string;
+ attribute x_core_info of stub : architecture is "ila,Vivado 2024.1";
+begin
+end;
diff --git a/sources/ip_cores/sim/rxclkgen_sim_netlist.vhdl b/sources/ip_cores/sim/rxclkgen_sim_netlist.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..3f0ade7287ea5ba1ebc4013c9f20b9aac5d2acbb
--- /dev/null
+++ b/sources/ip_cores/sim/rxclkgen_sim_netlist.vhdl
@@ -0,0 +1,184 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Fri Jun 14 11:28:28 2024
+-- Host : lbp001app.nikhef.nl running 64-bit unknown
+-- Command : write_vhdl -force -mode funcsim
+-- /localstore/et/franss/felix/firmware/Projects/FLX712_FELIG/FLX712_FELIG.gen/sources_1/ip/rxclkgen/rxclkgen_sim_netlist.vhdl
+-- Design : rxclkgen
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xcku115-flvf1924-2-e
+-- --------------------------------------------------------------------------------
+library IEEE;
+ use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+ use UNISIM.VCOMPONENTS.ALL;
+entity rxclkgen_clk_wiz is
+ port (
+ clk_out1 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+end rxclkgen_clk_wiz;
+
+architecture STRUCTURE of rxclkgen_clk_wiz is
+ signal clk_out1_rxclkgen : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CDDCDONE_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CLKFBIN_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CLKFBOUT_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcme3_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+ attribute BOX_TYPE : string;
+ attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+ attribute XILINX_LEGACY_PRIM : string;
+ attribute XILINX_LEGACY_PRIM of clkout1_buf : label is "BUFG";
+ attribute XILINX_TRANSFORM_PINMAP : string;
+ attribute XILINX_TRANSFORM_PINMAP of clkout1_buf : label is "VCC:CE";
+ attribute BOX_TYPE of mmcme3_adv_inst : label is "PRIMITIVE";
+ attribute OPT_MODIFIED : string;
+ attribute OPT_MODIFIED of mmcme3_adv_inst : label is "MLO";
+begin
+ clkout1_buf: unisim.vcomponents.BUFGCE
+ generic map(
+ CE_TYPE => "ASYNC",
+ SIM_DEVICE => "ULTRASCALE"
+ )
+ port map (
+ CE => '1',
+ I => clk_out1_rxclkgen,
+ O => clk_out1
+ );
+ mmcme3_adv_inst: unisim.vcomponents.MMCME3_ADV
+ generic map(
+ BANDWIDTH => "OPTIMIZED",
+ CLKFBOUT_MULT_F => 3.125000,
+ CLKFBOUT_PHASE => 0.000000,
+ CLKFBOUT_USE_FINE_PS => "FALSE",
+ CLKIN1_PERIOD => 3.125000,
+ CLKIN2_PERIOD => 0.000000,
+ CLKOUT0_DIVIDE_F => 25.000000,
+ CLKOUT0_DUTY_CYCLE => 0.500000,
+ CLKOUT0_PHASE => 0.000000,
+ CLKOUT0_USE_FINE_PS => "FALSE",
+ CLKOUT1_DIVIDE => 1,
+ CLKOUT1_DUTY_CYCLE => 0.500000,
+ CLKOUT1_PHASE => 0.000000,
+ CLKOUT1_USE_FINE_PS => "FALSE",
+ CLKOUT2_DIVIDE => 1,
+ CLKOUT2_DUTY_CYCLE => 0.500000,
+ CLKOUT2_PHASE => 0.000000,
+ CLKOUT2_USE_FINE_PS => "FALSE",
+ CLKOUT3_DIVIDE => 1,
+ CLKOUT3_DUTY_CYCLE => 0.500000,
+ CLKOUT3_PHASE => 0.000000,
+ CLKOUT3_USE_FINE_PS => "FALSE",
+ CLKOUT4_CASCADE => "FALSE",
+ CLKOUT4_DIVIDE => 1,
+ CLKOUT4_DUTY_CYCLE => 0.500000,
+ CLKOUT4_PHASE => 0.000000,
+ CLKOUT4_USE_FINE_PS => "FALSE",
+ CLKOUT5_DIVIDE => 1,
+ CLKOUT5_DUTY_CYCLE => 0.500000,
+ CLKOUT5_PHASE => 0.000000,
+ CLKOUT5_USE_FINE_PS => "FALSE",
+ CLKOUT6_DIVIDE => 1,
+ CLKOUT6_DUTY_CYCLE => 0.500000,
+ CLKOUT6_PHASE => 0.000000,
+ CLKOUT6_USE_FINE_PS => "FALSE",
+ COMPENSATION => "INTERNAL",
+ DIVCLK_DIVIDE => 1,
+ IS_CLKFBIN_INVERTED => '0',
+ IS_CLKIN1_INVERTED => '0',
+ IS_CLKIN2_INVERTED => '0',
+ IS_CLKINSEL_INVERTED => '0',
+ IS_PSEN_INVERTED => '0',
+ IS_PSINCDEC_INVERTED => '0',
+ IS_PWRDWN_INVERTED => '0',
+ IS_RST_INVERTED => '0',
+ REF_JITTER1 => 0.010000,
+ REF_JITTER2 => 0.010000,
+ SS_EN => "FALSE",
+ SS_MODE => "CENTER_HIGH",
+ SS_MOD_PERIOD => 10000,
+ STARTUP_WAIT => "FALSE"
+ )
+ port map (
+ CDDCDONE => NLW_mmcme3_adv_inst_CDDCDONE_UNCONNECTED,
+ CDDCREQ => '0',
+ CLKFBIN => NLW_mmcme3_adv_inst_CLKFBIN_UNCONNECTED,
+ CLKFBOUT => NLW_mmcme3_adv_inst_CLKFBOUT_UNCONNECTED,
+ CLKFBOUTB => NLW_mmcme3_adv_inst_CLKFBOUTB_UNCONNECTED,
+ CLKFBSTOPPED => NLW_mmcme3_adv_inst_CLKFBSTOPPED_UNCONNECTED,
+ CLKIN1 => clk_in1,
+ CLKIN2 => '0',
+ CLKINSEL => '1',
+ CLKINSTOPPED => NLW_mmcme3_adv_inst_CLKINSTOPPED_UNCONNECTED,
+ CLKOUT0 => clk_out1_rxclkgen,
+ CLKOUT0B => NLW_mmcme3_adv_inst_CLKOUT0B_UNCONNECTED,
+ CLKOUT1 => NLW_mmcme3_adv_inst_CLKOUT1_UNCONNECTED,
+ CLKOUT1B => NLW_mmcme3_adv_inst_CLKOUT1B_UNCONNECTED,
+ CLKOUT2 => NLW_mmcme3_adv_inst_CLKOUT2_UNCONNECTED,
+ CLKOUT2B => NLW_mmcme3_adv_inst_CLKOUT2B_UNCONNECTED,
+ CLKOUT3 => NLW_mmcme3_adv_inst_CLKOUT3_UNCONNECTED,
+ CLKOUT3B => NLW_mmcme3_adv_inst_CLKOUT3B_UNCONNECTED,
+ CLKOUT4 => NLW_mmcme3_adv_inst_CLKOUT4_UNCONNECTED,
+ CLKOUT5 => NLW_mmcme3_adv_inst_CLKOUT5_UNCONNECTED,
+ CLKOUT6 => NLW_mmcme3_adv_inst_CLKOUT6_UNCONNECTED,
+ DADDR(6 downto 0) => B"0000000",
+ DCLK => '0',
+ DEN => '0',
+ DI(15 downto 0) => B"0000000000000000",
+ DO(15 downto 0) => NLW_mmcme3_adv_inst_DO_UNCONNECTED(15 downto 0),
+ DRDY => NLW_mmcme3_adv_inst_DRDY_UNCONNECTED,
+ DWE => '0',
+ LOCKED => locked,
+ PSCLK => '0',
+ PSDONE => NLW_mmcme3_adv_inst_PSDONE_UNCONNECTED,
+ PSEN => '0',
+ PSINCDEC => '0',
+ PWRDWN => '0',
+ RST => reset
+ );
+end STRUCTURE;
+library IEEE;
+ use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+ use UNISIM.VCOMPONENTS.ALL;
+entity rxclkgen is
+ port (
+ clk_out1 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of rxclkgen : entity is true;
+end rxclkgen;
+
+architecture STRUCTURE of rxclkgen is
+begin
+ inst: entity work.rxclkgen_clk_wiz
+ port map (
+ clk_in1 => clk_in1,
+ clk_out1 => clk_out1,
+ locked => locked,
+ reset => reset
+ );
+end STRUCTURE;
diff --git a/sources/ip_cores/sim/vio_tclink_clk40_reset_sim_netlist.vhdl b/sources/ip_cores/sim/vio_tclink_clk40_reset_sim_netlist.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..0f418ec36f0cfdfe8b7649c05e0db27771237a2a
--- /dev/null
+++ b/sources/ip_cores/sim/vio_tclink_clk40_reset_sim_netlist.vhdl
@@ -0,0 +1,10412 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Wed Jun 12 16:30:30 2024
+-- Host : lbp001app.nikhef.nl running 64-bit unknown
+-- Command : write_vhdl -force -mode funcsim
+-- /localstore/et/franss/felix/firmware/Projects/FLX712_FMEMU/FLX712_FMEMU.gen/sources_1/ip/vio_tclink_clk40_reset/vio_tclink_clk40_reset_sim_netlist.vhdl
+-- Design : vio_tclink_clk40_reset
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xcku115-flvf1924-2-e
+-- --------------------------------------------------------------------------------
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+`protect begin_protected
+`protect version = 1
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+`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
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+`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
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+`protect key_block
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+`protect key_block
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+`protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
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+`protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
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+`protect key_block
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+`protect key_keyowner="Xilinx", key_keyname="xilinxt_2023_11", key_method="rsa"
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+`protect key_block
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+`protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=384)
+`protect key_block
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+`protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+`protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+
+`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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+`protect begin_protected
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+`protect end_protected
+library IEEE;
+ use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+ use UNISIM.VCOMPONENTS.ALL;
+entity vio_tclink_clk40_reset is
+ port (
+ clk : in STD_LOGIC;
+ probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
+ probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 )
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of vio_tclink_clk40_reset : entity is true;
+ attribute CHECK_LICENSE_TYPE : string;
+ attribute CHECK_LICENSE_TYPE of vio_tclink_clk40_reset : entity is "vio_tclink_clk40_reset,vio,{}";
+ attribute X_CORE_INFO : string;
+ attribute X_CORE_INFO of vio_tclink_clk40_reset : entity is "vio,Vivado 2024.1";
+end vio_tclink_clk40_reset;
+
+architecture STRUCTURE of vio_tclink_clk40_reset is
+ signal NLW_inst_probe_out10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out100_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out101_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out102_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out103_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out104_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out105_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out106_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out107_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out108_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out109_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out110_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out111_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out112_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out113_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out114_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out115_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out116_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out117_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out118_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out119_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out120_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out121_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out122_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out123_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out124_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out125_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out126_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out127_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out128_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out129_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out130_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out131_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out132_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out133_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out134_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out135_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out136_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out137_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out138_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out139_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out140_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out141_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out142_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out143_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out144_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out145_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out146_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out147_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out148_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out149_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out150_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out151_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out152_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out153_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out154_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out155_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out156_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out157_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out158_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out159_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out160_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out161_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out162_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out163_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out164_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out165_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out166_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out167_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out168_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out169_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out170_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out171_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out172_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out173_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out174_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out175_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out176_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out177_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out178_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out179_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out180_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out181_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out182_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out183_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out184_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out185_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out186_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out187_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out188_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out189_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out190_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out191_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out192_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out193_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out194_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out195_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out196_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out197_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out198_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out199_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out200_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out201_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out202_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out203_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out204_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out205_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out206_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out207_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out208_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out209_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out210_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out211_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out212_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out213_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out214_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out215_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out216_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out217_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out218_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out219_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out220_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out221_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out222_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out223_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out224_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out225_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out226_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out227_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out228_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out229_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out230_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out231_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out232_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out233_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out234_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out235_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out236_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out237_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out238_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out239_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out240_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out241_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out242_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out243_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out244_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out245_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out246_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out247_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out248_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out249_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out250_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out251_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out252_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out253_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out254_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out255_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out32_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out33_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out34_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out35_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out36_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out37_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out38_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out39_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out40_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out41_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out42_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out43_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out44_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out45_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out46_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out47_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out48_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out49_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out50_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out51_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out52_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out53_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out54_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out55_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out56_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out57_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out58_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out59_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out60_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out61_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out62_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out63_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out64_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out65_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out66_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out67_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out68_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out69_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out70_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out71_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out72_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out73_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out74_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out75_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out76_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out77_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out78_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out79_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out80_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out81_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out82_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out83_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out84_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out85_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out86_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out87_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out88_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out89_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out90_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out91_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out92_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out93_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out94_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out95_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out96_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out97_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out98_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_probe_out99_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal NLW_inst_sl_oport0_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
+ attribute C_BUILD_REVISION : integer;
+ attribute C_BUILD_REVISION of inst : label is 0;
+ attribute C_BUS_ADDR_WIDTH : integer;
+ attribute C_BUS_ADDR_WIDTH of inst : label is 17;
+ attribute C_BUS_DATA_WIDTH : integer;
+ attribute C_BUS_DATA_WIDTH of inst : label is 16;
+ attribute C_CORE_INFO1 : string;
+ attribute C_CORE_INFO1 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_CORE_INFO2 : string;
+ attribute C_CORE_INFO2 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_CORE_MAJOR_VER : integer;
+ attribute C_CORE_MAJOR_VER of inst : label is 2;
+ attribute C_CORE_MINOR_ALPHA_VER : integer;
+ attribute C_CORE_MINOR_ALPHA_VER of inst : label is 97;
+ attribute C_CORE_MINOR_VER : integer;
+ attribute C_CORE_MINOR_VER of inst : label is 0;
+ attribute C_CORE_TYPE : integer;
+ attribute C_CORE_TYPE of inst : label is 2;
+ attribute C_CSE_DRV_VER : integer;
+ attribute C_CSE_DRV_VER of inst : label is 1;
+ attribute C_EN_PROBE_IN_ACTIVITY : integer;
+ attribute C_EN_PROBE_IN_ACTIVITY of inst : label is 0;
+ attribute C_EN_SYNCHRONIZATION : integer;
+ attribute C_EN_SYNCHRONIZATION of inst : label is 1;
+ attribute C_MAJOR_VERSION : integer;
+ attribute C_MAJOR_VERSION of inst : label is 2013;
+ attribute C_MAX_NUM_PROBE : integer;
+ attribute C_MAX_NUM_PROBE of inst : label is 256;
+ attribute C_MAX_WIDTH_PER_PROBE : integer;
+ attribute C_MAX_WIDTH_PER_PROBE of inst : label is 256;
+ attribute C_MINOR_VERSION : integer;
+ attribute C_MINOR_VERSION of inst : label is 1;
+ attribute C_NEXT_SLAVE : integer;
+ attribute C_NEXT_SLAVE of inst : label is 0;
+ attribute C_NUM_PROBE_IN : integer;
+ attribute C_NUM_PROBE_IN of inst : label is 0;
+ attribute C_NUM_PROBE_OUT : integer;
+ attribute C_NUM_PROBE_OUT of inst : label is 3;
+ attribute C_PIPE_IFACE : integer;
+ attribute C_PIPE_IFACE of inst : label is 0;
+ attribute C_PROBE_IN0_WIDTH : integer;
+ attribute C_PROBE_IN0_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN100_WIDTH : integer;
+ attribute C_PROBE_IN100_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN101_WIDTH : integer;
+ attribute C_PROBE_IN101_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN102_WIDTH : integer;
+ attribute C_PROBE_IN102_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN103_WIDTH : integer;
+ attribute C_PROBE_IN103_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN104_WIDTH : integer;
+ attribute C_PROBE_IN104_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN105_WIDTH : integer;
+ attribute C_PROBE_IN105_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN106_WIDTH : integer;
+ attribute C_PROBE_IN106_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN107_WIDTH : integer;
+ attribute C_PROBE_IN107_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN108_WIDTH : integer;
+ attribute C_PROBE_IN108_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN109_WIDTH : integer;
+ attribute C_PROBE_IN109_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN10_WIDTH : integer;
+ attribute C_PROBE_IN10_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN110_WIDTH : integer;
+ attribute C_PROBE_IN110_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN111_WIDTH : integer;
+ attribute C_PROBE_IN111_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN112_WIDTH : integer;
+ attribute C_PROBE_IN112_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN113_WIDTH : integer;
+ attribute C_PROBE_IN113_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN114_WIDTH : integer;
+ attribute C_PROBE_IN114_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN115_WIDTH : integer;
+ attribute C_PROBE_IN115_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN116_WIDTH : integer;
+ attribute C_PROBE_IN116_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN117_WIDTH : integer;
+ attribute C_PROBE_IN117_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN118_WIDTH : integer;
+ attribute C_PROBE_IN118_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN119_WIDTH : integer;
+ attribute C_PROBE_IN119_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN11_WIDTH : integer;
+ attribute C_PROBE_IN11_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN120_WIDTH : integer;
+ attribute C_PROBE_IN120_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN121_WIDTH : integer;
+ attribute C_PROBE_IN121_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN122_WIDTH : integer;
+ attribute C_PROBE_IN122_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN123_WIDTH : integer;
+ attribute C_PROBE_IN123_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN124_WIDTH : integer;
+ attribute C_PROBE_IN124_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN125_WIDTH : integer;
+ attribute C_PROBE_IN125_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN126_WIDTH : integer;
+ attribute C_PROBE_IN126_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN127_WIDTH : integer;
+ attribute C_PROBE_IN127_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN128_WIDTH : integer;
+ attribute C_PROBE_IN128_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN129_WIDTH : integer;
+ attribute C_PROBE_IN129_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN12_WIDTH : integer;
+ attribute C_PROBE_IN12_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN130_WIDTH : integer;
+ attribute C_PROBE_IN130_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN131_WIDTH : integer;
+ attribute C_PROBE_IN131_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN132_WIDTH : integer;
+ attribute C_PROBE_IN132_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN133_WIDTH : integer;
+ attribute C_PROBE_IN133_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN134_WIDTH : integer;
+ attribute C_PROBE_IN134_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN135_WIDTH : integer;
+ attribute C_PROBE_IN135_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN136_WIDTH : integer;
+ attribute C_PROBE_IN136_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN137_WIDTH : integer;
+ attribute C_PROBE_IN137_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN138_WIDTH : integer;
+ attribute C_PROBE_IN138_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN139_WIDTH : integer;
+ attribute C_PROBE_IN139_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN13_WIDTH : integer;
+ attribute C_PROBE_IN13_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN140_WIDTH : integer;
+ attribute C_PROBE_IN140_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN141_WIDTH : integer;
+ attribute C_PROBE_IN141_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN142_WIDTH : integer;
+ attribute C_PROBE_IN142_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN143_WIDTH : integer;
+ attribute C_PROBE_IN143_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN144_WIDTH : integer;
+ attribute C_PROBE_IN144_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN145_WIDTH : integer;
+ attribute C_PROBE_IN145_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN146_WIDTH : integer;
+ attribute C_PROBE_IN146_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN147_WIDTH : integer;
+ attribute C_PROBE_IN147_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN148_WIDTH : integer;
+ attribute C_PROBE_IN148_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN149_WIDTH : integer;
+ attribute C_PROBE_IN149_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN14_WIDTH : integer;
+ attribute C_PROBE_IN14_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN150_WIDTH : integer;
+ attribute C_PROBE_IN150_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN151_WIDTH : integer;
+ attribute C_PROBE_IN151_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN152_WIDTH : integer;
+ attribute C_PROBE_IN152_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN153_WIDTH : integer;
+ attribute C_PROBE_IN153_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN154_WIDTH : integer;
+ attribute C_PROBE_IN154_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN155_WIDTH : integer;
+ attribute C_PROBE_IN155_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN156_WIDTH : integer;
+ attribute C_PROBE_IN156_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN157_WIDTH : integer;
+ attribute C_PROBE_IN157_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN158_WIDTH : integer;
+ attribute C_PROBE_IN158_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN159_WIDTH : integer;
+ attribute C_PROBE_IN159_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN15_WIDTH : integer;
+ attribute C_PROBE_IN15_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN160_WIDTH : integer;
+ attribute C_PROBE_IN160_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN161_WIDTH : integer;
+ attribute C_PROBE_IN161_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN162_WIDTH : integer;
+ attribute C_PROBE_IN162_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN163_WIDTH : integer;
+ attribute C_PROBE_IN163_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN164_WIDTH : integer;
+ attribute C_PROBE_IN164_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN165_WIDTH : integer;
+ attribute C_PROBE_IN165_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN166_WIDTH : integer;
+ attribute C_PROBE_IN166_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN167_WIDTH : integer;
+ attribute C_PROBE_IN167_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN168_WIDTH : integer;
+ attribute C_PROBE_IN168_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN169_WIDTH : integer;
+ attribute C_PROBE_IN169_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN16_WIDTH : integer;
+ attribute C_PROBE_IN16_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN170_WIDTH : integer;
+ attribute C_PROBE_IN170_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN171_WIDTH : integer;
+ attribute C_PROBE_IN171_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN172_WIDTH : integer;
+ attribute C_PROBE_IN172_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN173_WIDTH : integer;
+ attribute C_PROBE_IN173_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN174_WIDTH : integer;
+ attribute C_PROBE_IN174_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN175_WIDTH : integer;
+ attribute C_PROBE_IN175_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN176_WIDTH : integer;
+ attribute C_PROBE_IN176_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN177_WIDTH : integer;
+ attribute C_PROBE_IN177_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN178_WIDTH : integer;
+ attribute C_PROBE_IN178_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN179_WIDTH : integer;
+ attribute C_PROBE_IN179_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN17_WIDTH : integer;
+ attribute C_PROBE_IN17_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN180_WIDTH : integer;
+ attribute C_PROBE_IN180_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN181_WIDTH : integer;
+ attribute C_PROBE_IN181_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN182_WIDTH : integer;
+ attribute C_PROBE_IN182_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN183_WIDTH : integer;
+ attribute C_PROBE_IN183_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN184_WIDTH : integer;
+ attribute C_PROBE_IN184_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN185_WIDTH : integer;
+ attribute C_PROBE_IN185_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN186_WIDTH : integer;
+ attribute C_PROBE_IN186_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN187_WIDTH : integer;
+ attribute C_PROBE_IN187_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN188_WIDTH : integer;
+ attribute C_PROBE_IN188_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN189_WIDTH : integer;
+ attribute C_PROBE_IN189_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN18_WIDTH : integer;
+ attribute C_PROBE_IN18_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN190_WIDTH : integer;
+ attribute C_PROBE_IN190_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN191_WIDTH : integer;
+ attribute C_PROBE_IN191_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN192_WIDTH : integer;
+ attribute C_PROBE_IN192_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN193_WIDTH : integer;
+ attribute C_PROBE_IN193_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN194_WIDTH : integer;
+ attribute C_PROBE_IN194_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN195_WIDTH : integer;
+ attribute C_PROBE_IN195_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN196_WIDTH : integer;
+ attribute C_PROBE_IN196_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN197_WIDTH : integer;
+ attribute C_PROBE_IN197_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN198_WIDTH : integer;
+ attribute C_PROBE_IN198_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN199_WIDTH : integer;
+ attribute C_PROBE_IN199_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN19_WIDTH : integer;
+ attribute C_PROBE_IN19_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN1_WIDTH : integer;
+ attribute C_PROBE_IN1_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN200_WIDTH : integer;
+ attribute C_PROBE_IN200_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN201_WIDTH : integer;
+ attribute C_PROBE_IN201_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN202_WIDTH : integer;
+ attribute C_PROBE_IN202_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN203_WIDTH : integer;
+ attribute C_PROBE_IN203_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN204_WIDTH : integer;
+ attribute C_PROBE_IN204_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN205_WIDTH : integer;
+ attribute C_PROBE_IN205_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN206_WIDTH : integer;
+ attribute C_PROBE_IN206_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN207_WIDTH : integer;
+ attribute C_PROBE_IN207_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN208_WIDTH : integer;
+ attribute C_PROBE_IN208_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN209_WIDTH : integer;
+ attribute C_PROBE_IN209_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN20_WIDTH : integer;
+ attribute C_PROBE_IN20_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN210_WIDTH : integer;
+ attribute C_PROBE_IN210_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN211_WIDTH : integer;
+ attribute C_PROBE_IN211_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN212_WIDTH : integer;
+ attribute C_PROBE_IN212_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN213_WIDTH : integer;
+ attribute C_PROBE_IN213_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN214_WIDTH : integer;
+ attribute C_PROBE_IN214_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN215_WIDTH : integer;
+ attribute C_PROBE_IN215_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN216_WIDTH : integer;
+ attribute C_PROBE_IN216_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN217_WIDTH : integer;
+ attribute C_PROBE_IN217_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN218_WIDTH : integer;
+ attribute C_PROBE_IN218_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN219_WIDTH : integer;
+ attribute C_PROBE_IN219_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN21_WIDTH : integer;
+ attribute C_PROBE_IN21_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN220_WIDTH : integer;
+ attribute C_PROBE_IN220_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN221_WIDTH : integer;
+ attribute C_PROBE_IN221_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN222_WIDTH : integer;
+ attribute C_PROBE_IN222_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN223_WIDTH : integer;
+ attribute C_PROBE_IN223_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN224_WIDTH : integer;
+ attribute C_PROBE_IN224_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN225_WIDTH : integer;
+ attribute C_PROBE_IN225_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN226_WIDTH : integer;
+ attribute C_PROBE_IN226_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN227_WIDTH : integer;
+ attribute C_PROBE_IN227_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN228_WIDTH : integer;
+ attribute C_PROBE_IN228_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN229_WIDTH : integer;
+ attribute C_PROBE_IN229_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN22_WIDTH : integer;
+ attribute C_PROBE_IN22_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN230_WIDTH : integer;
+ attribute C_PROBE_IN230_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN231_WIDTH : integer;
+ attribute C_PROBE_IN231_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN232_WIDTH : integer;
+ attribute C_PROBE_IN232_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN233_WIDTH : integer;
+ attribute C_PROBE_IN233_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN234_WIDTH : integer;
+ attribute C_PROBE_IN234_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN235_WIDTH : integer;
+ attribute C_PROBE_IN235_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN236_WIDTH : integer;
+ attribute C_PROBE_IN236_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN237_WIDTH : integer;
+ attribute C_PROBE_IN237_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN238_WIDTH : integer;
+ attribute C_PROBE_IN238_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN239_WIDTH : integer;
+ attribute C_PROBE_IN239_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN23_WIDTH : integer;
+ attribute C_PROBE_IN23_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN240_WIDTH : integer;
+ attribute C_PROBE_IN240_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN241_WIDTH : integer;
+ attribute C_PROBE_IN241_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN242_WIDTH : integer;
+ attribute C_PROBE_IN242_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN243_WIDTH : integer;
+ attribute C_PROBE_IN243_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN244_WIDTH : integer;
+ attribute C_PROBE_IN244_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN245_WIDTH : integer;
+ attribute C_PROBE_IN245_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN246_WIDTH : integer;
+ attribute C_PROBE_IN246_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN247_WIDTH : integer;
+ attribute C_PROBE_IN247_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN248_WIDTH : integer;
+ attribute C_PROBE_IN248_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN249_WIDTH : integer;
+ attribute C_PROBE_IN249_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN24_WIDTH : integer;
+ attribute C_PROBE_IN24_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN250_WIDTH : integer;
+ attribute C_PROBE_IN250_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN251_WIDTH : integer;
+ attribute C_PROBE_IN251_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN252_WIDTH : integer;
+ attribute C_PROBE_IN252_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN253_WIDTH : integer;
+ attribute C_PROBE_IN253_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN254_WIDTH : integer;
+ attribute C_PROBE_IN254_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN255_WIDTH : integer;
+ attribute C_PROBE_IN255_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN25_WIDTH : integer;
+ attribute C_PROBE_IN25_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN26_WIDTH : integer;
+ attribute C_PROBE_IN26_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN27_WIDTH : integer;
+ attribute C_PROBE_IN27_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN28_WIDTH : integer;
+ attribute C_PROBE_IN28_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN29_WIDTH : integer;
+ attribute C_PROBE_IN29_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN2_WIDTH : integer;
+ attribute C_PROBE_IN2_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN30_WIDTH : integer;
+ attribute C_PROBE_IN30_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN31_WIDTH : integer;
+ attribute C_PROBE_IN31_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN32_WIDTH : integer;
+ attribute C_PROBE_IN32_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN33_WIDTH : integer;
+ attribute C_PROBE_IN33_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN34_WIDTH : integer;
+ attribute C_PROBE_IN34_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN35_WIDTH : integer;
+ attribute C_PROBE_IN35_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN36_WIDTH : integer;
+ attribute C_PROBE_IN36_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN37_WIDTH : integer;
+ attribute C_PROBE_IN37_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN38_WIDTH : integer;
+ attribute C_PROBE_IN38_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN39_WIDTH : integer;
+ attribute C_PROBE_IN39_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN3_WIDTH : integer;
+ attribute C_PROBE_IN3_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN40_WIDTH : integer;
+ attribute C_PROBE_IN40_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN41_WIDTH : integer;
+ attribute C_PROBE_IN41_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN42_WIDTH : integer;
+ attribute C_PROBE_IN42_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN43_WIDTH : integer;
+ attribute C_PROBE_IN43_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN44_WIDTH : integer;
+ attribute C_PROBE_IN44_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN45_WIDTH : integer;
+ attribute C_PROBE_IN45_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN46_WIDTH : integer;
+ attribute C_PROBE_IN46_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN47_WIDTH : integer;
+ attribute C_PROBE_IN47_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN48_WIDTH : integer;
+ attribute C_PROBE_IN48_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN49_WIDTH : integer;
+ attribute C_PROBE_IN49_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN4_WIDTH : integer;
+ attribute C_PROBE_IN4_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN50_WIDTH : integer;
+ attribute C_PROBE_IN50_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN51_WIDTH : integer;
+ attribute C_PROBE_IN51_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN52_WIDTH : integer;
+ attribute C_PROBE_IN52_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN53_WIDTH : integer;
+ attribute C_PROBE_IN53_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN54_WIDTH : integer;
+ attribute C_PROBE_IN54_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN55_WIDTH : integer;
+ attribute C_PROBE_IN55_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN56_WIDTH : integer;
+ attribute C_PROBE_IN56_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN57_WIDTH : integer;
+ attribute C_PROBE_IN57_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN58_WIDTH : integer;
+ attribute C_PROBE_IN58_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN59_WIDTH : integer;
+ attribute C_PROBE_IN59_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN5_WIDTH : integer;
+ attribute C_PROBE_IN5_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN60_WIDTH : integer;
+ attribute C_PROBE_IN60_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN61_WIDTH : integer;
+ attribute C_PROBE_IN61_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN62_WIDTH : integer;
+ attribute C_PROBE_IN62_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN63_WIDTH : integer;
+ attribute C_PROBE_IN63_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN64_WIDTH : integer;
+ attribute C_PROBE_IN64_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN65_WIDTH : integer;
+ attribute C_PROBE_IN65_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN66_WIDTH : integer;
+ attribute C_PROBE_IN66_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN67_WIDTH : integer;
+ attribute C_PROBE_IN67_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN68_WIDTH : integer;
+ attribute C_PROBE_IN68_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN69_WIDTH : integer;
+ attribute C_PROBE_IN69_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN6_WIDTH : integer;
+ attribute C_PROBE_IN6_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN70_WIDTH : integer;
+ attribute C_PROBE_IN70_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN71_WIDTH : integer;
+ attribute C_PROBE_IN71_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN72_WIDTH : integer;
+ attribute C_PROBE_IN72_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN73_WIDTH : integer;
+ attribute C_PROBE_IN73_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN74_WIDTH : integer;
+ attribute C_PROBE_IN74_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN75_WIDTH : integer;
+ attribute C_PROBE_IN75_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN76_WIDTH : integer;
+ attribute C_PROBE_IN76_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN77_WIDTH : integer;
+ attribute C_PROBE_IN77_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN78_WIDTH : integer;
+ attribute C_PROBE_IN78_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN79_WIDTH : integer;
+ attribute C_PROBE_IN79_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN7_WIDTH : integer;
+ attribute C_PROBE_IN7_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN80_WIDTH : integer;
+ attribute C_PROBE_IN80_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN81_WIDTH : integer;
+ attribute C_PROBE_IN81_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN82_WIDTH : integer;
+ attribute C_PROBE_IN82_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN83_WIDTH : integer;
+ attribute C_PROBE_IN83_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN84_WIDTH : integer;
+ attribute C_PROBE_IN84_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN85_WIDTH : integer;
+ attribute C_PROBE_IN85_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN86_WIDTH : integer;
+ attribute C_PROBE_IN86_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN87_WIDTH : integer;
+ attribute C_PROBE_IN87_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN88_WIDTH : integer;
+ attribute C_PROBE_IN88_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN89_WIDTH : integer;
+ attribute C_PROBE_IN89_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN8_WIDTH : integer;
+ attribute C_PROBE_IN8_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN90_WIDTH : integer;
+ attribute C_PROBE_IN90_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN91_WIDTH : integer;
+ attribute C_PROBE_IN91_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN92_WIDTH : integer;
+ attribute C_PROBE_IN92_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN93_WIDTH : integer;
+ attribute C_PROBE_IN93_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN94_WIDTH : integer;
+ attribute C_PROBE_IN94_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN95_WIDTH : integer;
+ attribute C_PROBE_IN95_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN96_WIDTH : integer;
+ attribute C_PROBE_IN96_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN97_WIDTH : integer;
+ attribute C_PROBE_IN97_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN98_WIDTH : integer;
+ attribute C_PROBE_IN98_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN99_WIDTH : integer;
+ attribute C_PROBE_IN99_WIDTH of inst : label is 1;
+ attribute C_PROBE_IN9_WIDTH : integer;
+ attribute C_PROBE_IN9_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT0_INIT_VAL : string;
+ attribute C_PROBE_OUT0_INIT_VAL of inst : label is "3'b010";
+ attribute C_PROBE_OUT0_WIDTH : integer;
+ attribute C_PROBE_OUT0_WIDTH of inst : label is 3;
+ attribute C_PROBE_OUT100_INIT_VAL : string;
+ attribute C_PROBE_OUT100_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT100_WIDTH : integer;
+ attribute C_PROBE_OUT100_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT101_INIT_VAL : string;
+ attribute C_PROBE_OUT101_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT101_WIDTH : integer;
+ attribute C_PROBE_OUT101_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT102_INIT_VAL : string;
+ attribute C_PROBE_OUT102_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT102_WIDTH : integer;
+ attribute C_PROBE_OUT102_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT103_INIT_VAL : string;
+ attribute C_PROBE_OUT103_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT103_WIDTH : integer;
+ attribute C_PROBE_OUT103_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT104_INIT_VAL : string;
+ attribute C_PROBE_OUT104_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT104_WIDTH : integer;
+ attribute C_PROBE_OUT104_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT105_INIT_VAL : string;
+ attribute C_PROBE_OUT105_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT105_WIDTH : integer;
+ attribute C_PROBE_OUT105_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT106_INIT_VAL : string;
+ attribute C_PROBE_OUT106_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT106_WIDTH : integer;
+ attribute C_PROBE_OUT106_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT107_INIT_VAL : string;
+ attribute C_PROBE_OUT107_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT107_WIDTH : integer;
+ attribute C_PROBE_OUT107_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT108_INIT_VAL : string;
+ attribute C_PROBE_OUT108_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT108_WIDTH : integer;
+ attribute C_PROBE_OUT108_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT109_INIT_VAL : string;
+ attribute C_PROBE_OUT109_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT109_WIDTH : integer;
+ attribute C_PROBE_OUT109_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT10_INIT_VAL : string;
+ attribute C_PROBE_OUT10_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT10_WIDTH : integer;
+ attribute C_PROBE_OUT10_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT110_INIT_VAL : string;
+ attribute C_PROBE_OUT110_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT110_WIDTH : integer;
+ attribute C_PROBE_OUT110_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT111_INIT_VAL : string;
+ attribute C_PROBE_OUT111_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT111_WIDTH : integer;
+ attribute C_PROBE_OUT111_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT112_INIT_VAL : string;
+ attribute C_PROBE_OUT112_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT112_WIDTH : integer;
+ attribute C_PROBE_OUT112_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT113_INIT_VAL : string;
+ attribute C_PROBE_OUT113_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT113_WIDTH : integer;
+ attribute C_PROBE_OUT113_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT114_INIT_VAL : string;
+ attribute C_PROBE_OUT114_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT114_WIDTH : integer;
+ attribute C_PROBE_OUT114_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT115_INIT_VAL : string;
+ attribute C_PROBE_OUT115_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT115_WIDTH : integer;
+ attribute C_PROBE_OUT115_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT116_INIT_VAL : string;
+ attribute C_PROBE_OUT116_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT116_WIDTH : integer;
+ attribute C_PROBE_OUT116_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT117_INIT_VAL : string;
+ attribute C_PROBE_OUT117_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT117_WIDTH : integer;
+ attribute C_PROBE_OUT117_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT118_INIT_VAL : string;
+ attribute C_PROBE_OUT118_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT118_WIDTH : integer;
+ attribute C_PROBE_OUT118_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT119_INIT_VAL : string;
+ attribute C_PROBE_OUT119_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT119_WIDTH : integer;
+ attribute C_PROBE_OUT119_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT11_INIT_VAL : string;
+ attribute C_PROBE_OUT11_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT11_WIDTH : integer;
+ attribute C_PROBE_OUT11_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT120_INIT_VAL : string;
+ attribute C_PROBE_OUT120_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT120_WIDTH : integer;
+ attribute C_PROBE_OUT120_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT121_INIT_VAL : string;
+ attribute C_PROBE_OUT121_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT121_WIDTH : integer;
+ attribute C_PROBE_OUT121_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT122_INIT_VAL : string;
+ attribute C_PROBE_OUT122_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT122_WIDTH : integer;
+ attribute C_PROBE_OUT122_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT123_INIT_VAL : string;
+ attribute C_PROBE_OUT123_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT123_WIDTH : integer;
+ attribute C_PROBE_OUT123_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT124_INIT_VAL : string;
+ attribute C_PROBE_OUT124_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT124_WIDTH : integer;
+ attribute C_PROBE_OUT124_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT125_INIT_VAL : string;
+ attribute C_PROBE_OUT125_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT125_WIDTH : integer;
+ attribute C_PROBE_OUT125_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT126_INIT_VAL : string;
+ attribute C_PROBE_OUT126_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT126_WIDTH : integer;
+ attribute C_PROBE_OUT126_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT127_INIT_VAL : string;
+ attribute C_PROBE_OUT127_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT127_WIDTH : integer;
+ attribute C_PROBE_OUT127_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT128_INIT_VAL : string;
+ attribute C_PROBE_OUT128_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT128_WIDTH : integer;
+ attribute C_PROBE_OUT128_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT129_INIT_VAL : string;
+ attribute C_PROBE_OUT129_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT129_WIDTH : integer;
+ attribute C_PROBE_OUT129_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT12_INIT_VAL : string;
+ attribute C_PROBE_OUT12_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT12_WIDTH : integer;
+ attribute C_PROBE_OUT12_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT130_INIT_VAL : string;
+ attribute C_PROBE_OUT130_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT130_WIDTH : integer;
+ attribute C_PROBE_OUT130_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT131_INIT_VAL : string;
+ attribute C_PROBE_OUT131_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT131_WIDTH : integer;
+ attribute C_PROBE_OUT131_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT132_INIT_VAL : string;
+ attribute C_PROBE_OUT132_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT132_WIDTH : integer;
+ attribute C_PROBE_OUT132_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT133_INIT_VAL : string;
+ attribute C_PROBE_OUT133_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT133_WIDTH : integer;
+ attribute C_PROBE_OUT133_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT134_INIT_VAL : string;
+ attribute C_PROBE_OUT134_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT134_WIDTH : integer;
+ attribute C_PROBE_OUT134_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT135_INIT_VAL : string;
+ attribute C_PROBE_OUT135_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT135_WIDTH : integer;
+ attribute C_PROBE_OUT135_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT136_INIT_VAL : string;
+ attribute C_PROBE_OUT136_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT136_WIDTH : integer;
+ attribute C_PROBE_OUT136_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT137_INIT_VAL : string;
+ attribute C_PROBE_OUT137_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT137_WIDTH : integer;
+ attribute C_PROBE_OUT137_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT138_INIT_VAL : string;
+ attribute C_PROBE_OUT138_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT138_WIDTH : integer;
+ attribute C_PROBE_OUT138_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT139_INIT_VAL : string;
+ attribute C_PROBE_OUT139_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT139_WIDTH : integer;
+ attribute C_PROBE_OUT139_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT13_INIT_VAL : string;
+ attribute C_PROBE_OUT13_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT13_WIDTH : integer;
+ attribute C_PROBE_OUT13_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT140_INIT_VAL : string;
+ attribute C_PROBE_OUT140_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT140_WIDTH : integer;
+ attribute C_PROBE_OUT140_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT141_INIT_VAL : string;
+ attribute C_PROBE_OUT141_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT141_WIDTH : integer;
+ attribute C_PROBE_OUT141_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT142_INIT_VAL : string;
+ attribute C_PROBE_OUT142_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT142_WIDTH : integer;
+ attribute C_PROBE_OUT142_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT143_INIT_VAL : string;
+ attribute C_PROBE_OUT143_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT143_WIDTH : integer;
+ attribute C_PROBE_OUT143_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT144_INIT_VAL : string;
+ attribute C_PROBE_OUT144_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT144_WIDTH : integer;
+ attribute C_PROBE_OUT144_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT145_INIT_VAL : string;
+ attribute C_PROBE_OUT145_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT145_WIDTH : integer;
+ attribute C_PROBE_OUT145_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT146_INIT_VAL : string;
+ attribute C_PROBE_OUT146_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT146_WIDTH : integer;
+ attribute C_PROBE_OUT146_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT147_INIT_VAL : string;
+ attribute C_PROBE_OUT147_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT147_WIDTH : integer;
+ attribute C_PROBE_OUT147_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT148_INIT_VAL : string;
+ attribute C_PROBE_OUT148_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT148_WIDTH : integer;
+ attribute C_PROBE_OUT148_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT149_INIT_VAL : string;
+ attribute C_PROBE_OUT149_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT149_WIDTH : integer;
+ attribute C_PROBE_OUT149_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT14_INIT_VAL : string;
+ attribute C_PROBE_OUT14_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT14_WIDTH : integer;
+ attribute C_PROBE_OUT14_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT150_INIT_VAL : string;
+ attribute C_PROBE_OUT150_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT150_WIDTH : integer;
+ attribute C_PROBE_OUT150_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT151_INIT_VAL : string;
+ attribute C_PROBE_OUT151_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT151_WIDTH : integer;
+ attribute C_PROBE_OUT151_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT152_INIT_VAL : string;
+ attribute C_PROBE_OUT152_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT152_WIDTH : integer;
+ attribute C_PROBE_OUT152_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT153_INIT_VAL : string;
+ attribute C_PROBE_OUT153_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT153_WIDTH : integer;
+ attribute C_PROBE_OUT153_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT154_INIT_VAL : string;
+ attribute C_PROBE_OUT154_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT154_WIDTH : integer;
+ attribute C_PROBE_OUT154_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT155_INIT_VAL : string;
+ attribute C_PROBE_OUT155_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT155_WIDTH : integer;
+ attribute C_PROBE_OUT155_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT156_INIT_VAL : string;
+ attribute C_PROBE_OUT156_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT156_WIDTH : integer;
+ attribute C_PROBE_OUT156_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT157_INIT_VAL : string;
+ attribute C_PROBE_OUT157_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT157_WIDTH : integer;
+ attribute C_PROBE_OUT157_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT158_INIT_VAL : string;
+ attribute C_PROBE_OUT158_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT158_WIDTH : integer;
+ attribute C_PROBE_OUT158_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT159_INIT_VAL : string;
+ attribute C_PROBE_OUT159_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT159_WIDTH : integer;
+ attribute C_PROBE_OUT159_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT15_INIT_VAL : string;
+ attribute C_PROBE_OUT15_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT15_WIDTH : integer;
+ attribute C_PROBE_OUT15_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT160_INIT_VAL : string;
+ attribute C_PROBE_OUT160_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT160_WIDTH : integer;
+ attribute C_PROBE_OUT160_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT161_INIT_VAL : string;
+ attribute C_PROBE_OUT161_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT161_WIDTH : integer;
+ attribute C_PROBE_OUT161_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT162_INIT_VAL : string;
+ attribute C_PROBE_OUT162_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT162_WIDTH : integer;
+ attribute C_PROBE_OUT162_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT163_INIT_VAL : string;
+ attribute C_PROBE_OUT163_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT163_WIDTH : integer;
+ attribute C_PROBE_OUT163_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT164_INIT_VAL : string;
+ attribute C_PROBE_OUT164_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT164_WIDTH : integer;
+ attribute C_PROBE_OUT164_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT165_INIT_VAL : string;
+ attribute C_PROBE_OUT165_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT165_WIDTH : integer;
+ attribute C_PROBE_OUT165_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT166_INIT_VAL : string;
+ attribute C_PROBE_OUT166_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT166_WIDTH : integer;
+ attribute C_PROBE_OUT166_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT167_INIT_VAL : string;
+ attribute C_PROBE_OUT167_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT167_WIDTH : integer;
+ attribute C_PROBE_OUT167_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT168_INIT_VAL : string;
+ attribute C_PROBE_OUT168_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT168_WIDTH : integer;
+ attribute C_PROBE_OUT168_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT169_INIT_VAL : string;
+ attribute C_PROBE_OUT169_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT169_WIDTH : integer;
+ attribute C_PROBE_OUT169_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT16_INIT_VAL : string;
+ attribute C_PROBE_OUT16_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT16_WIDTH : integer;
+ attribute C_PROBE_OUT16_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT170_INIT_VAL : string;
+ attribute C_PROBE_OUT170_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT170_WIDTH : integer;
+ attribute C_PROBE_OUT170_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT171_INIT_VAL : string;
+ attribute C_PROBE_OUT171_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT171_WIDTH : integer;
+ attribute C_PROBE_OUT171_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT172_INIT_VAL : string;
+ attribute C_PROBE_OUT172_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT172_WIDTH : integer;
+ attribute C_PROBE_OUT172_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT173_INIT_VAL : string;
+ attribute C_PROBE_OUT173_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT173_WIDTH : integer;
+ attribute C_PROBE_OUT173_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT174_INIT_VAL : string;
+ attribute C_PROBE_OUT174_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT174_WIDTH : integer;
+ attribute C_PROBE_OUT174_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT175_INIT_VAL : string;
+ attribute C_PROBE_OUT175_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT175_WIDTH : integer;
+ attribute C_PROBE_OUT175_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT176_INIT_VAL : string;
+ attribute C_PROBE_OUT176_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT176_WIDTH : integer;
+ attribute C_PROBE_OUT176_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT177_INIT_VAL : string;
+ attribute C_PROBE_OUT177_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT177_WIDTH : integer;
+ attribute C_PROBE_OUT177_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT178_INIT_VAL : string;
+ attribute C_PROBE_OUT178_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT178_WIDTH : integer;
+ attribute C_PROBE_OUT178_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT179_INIT_VAL : string;
+ attribute C_PROBE_OUT179_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT179_WIDTH : integer;
+ attribute C_PROBE_OUT179_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT17_INIT_VAL : string;
+ attribute C_PROBE_OUT17_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT17_WIDTH : integer;
+ attribute C_PROBE_OUT17_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT180_INIT_VAL : string;
+ attribute C_PROBE_OUT180_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT180_WIDTH : integer;
+ attribute C_PROBE_OUT180_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT181_INIT_VAL : string;
+ attribute C_PROBE_OUT181_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT181_WIDTH : integer;
+ attribute C_PROBE_OUT181_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT182_INIT_VAL : string;
+ attribute C_PROBE_OUT182_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT182_WIDTH : integer;
+ attribute C_PROBE_OUT182_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT183_INIT_VAL : string;
+ attribute C_PROBE_OUT183_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT183_WIDTH : integer;
+ attribute C_PROBE_OUT183_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT184_INIT_VAL : string;
+ attribute C_PROBE_OUT184_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT184_WIDTH : integer;
+ attribute C_PROBE_OUT184_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT185_INIT_VAL : string;
+ attribute C_PROBE_OUT185_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT185_WIDTH : integer;
+ attribute C_PROBE_OUT185_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT186_INIT_VAL : string;
+ attribute C_PROBE_OUT186_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT186_WIDTH : integer;
+ attribute C_PROBE_OUT186_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT187_INIT_VAL : string;
+ attribute C_PROBE_OUT187_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT187_WIDTH : integer;
+ attribute C_PROBE_OUT187_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT188_INIT_VAL : string;
+ attribute C_PROBE_OUT188_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT188_WIDTH : integer;
+ attribute C_PROBE_OUT188_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT189_INIT_VAL : string;
+ attribute C_PROBE_OUT189_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT189_WIDTH : integer;
+ attribute C_PROBE_OUT189_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT18_INIT_VAL : string;
+ attribute C_PROBE_OUT18_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT18_WIDTH : integer;
+ attribute C_PROBE_OUT18_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT190_INIT_VAL : string;
+ attribute C_PROBE_OUT190_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT190_WIDTH : integer;
+ attribute C_PROBE_OUT190_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT191_INIT_VAL : string;
+ attribute C_PROBE_OUT191_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT191_WIDTH : integer;
+ attribute C_PROBE_OUT191_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT192_INIT_VAL : string;
+ attribute C_PROBE_OUT192_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT192_WIDTH : integer;
+ attribute C_PROBE_OUT192_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT193_INIT_VAL : string;
+ attribute C_PROBE_OUT193_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT193_WIDTH : integer;
+ attribute C_PROBE_OUT193_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT194_INIT_VAL : string;
+ attribute C_PROBE_OUT194_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT194_WIDTH : integer;
+ attribute C_PROBE_OUT194_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT195_INIT_VAL : string;
+ attribute C_PROBE_OUT195_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT195_WIDTH : integer;
+ attribute C_PROBE_OUT195_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT196_INIT_VAL : string;
+ attribute C_PROBE_OUT196_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT196_WIDTH : integer;
+ attribute C_PROBE_OUT196_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT197_INIT_VAL : string;
+ attribute C_PROBE_OUT197_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT197_WIDTH : integer;
+ attribute C_PROBE_OUT197_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT198_INIT_VAL : string;
+ attribute C_PROBE_OUT198_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT198_WIDTH : integer;
+ attribute C_PROBE_OUT198_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT199_INIT_VAL : string;
+ attribute C_PROBE_OUT199_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT199_WIDTH : integer;
+ attribute C_PROBE_OUT199_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT19_INIT_VAL : string;
+ attribute C_PROBE_OUT19_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT19_WIDTH : integer;
+ attribute C_PROBE_OUT19_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT1_INIT_VAL : string;
+ attribute C_PROBE_OUT1_INIT_VAL of inst : label is "1'b1";
+ attribute C_PROBE_OUT1_WIDTH : integer;
+ attribute C_PROBE_OUT1_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT200_INIT_VAL : string;
+ attribute C_PROBE_OUT200_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT200_WIDTH : integer;
+ attribute C_PROBE_OUT200_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT201_INIT_VAL : string;
+ attribute C_PROBE_OUT201_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT201_WIDTH : integer;
+ attribute C_PROBE_OUT201_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT202_INIT_VAL : string;
+ attribute C_PROBE_OUT202_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT202_WIDTH : integer;
+ attribute C_PROBE_OUT202_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT203_INIT_VAL : string;
+ attribute C_PROBE_OUT203_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT203_WIDTH : integer;
+ attribute C_PROBE_OUT203_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT204_INIT_VAL : string;
+ attribute C_PROBE_OUT204_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT204_WIDTH : integer;
+ attribute C_PROBE_OUT204_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT205_INIT_VAL : string;
+ attribute C_PROBE_OUT205_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT205_WIDTH : integer;
+ attribute C_PROBE_OUT205_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT206_INIT_VAL : string;
+ attribute C_PROBE_OUT206_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT206_WIDTH : integer;
+ attribute C_PROBE_OUT206_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT207_INIT_VAL : string;
+ attribute C_PROBE_OUT207_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT207_WIDTH : integer;
+ attribute C_PROBE_OUT207_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT208_INIT_VAL : string;
+ attribute C_PROBE_OUT208_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT208_WIDTH : integer;
+ attribute C_PROBE_OUT208_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT209_INIT_VAL : string;
+ attribute C_PROBE_OUT209_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT209_WIDTH : integer;
+ attribute C_PROBE_OUT209_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT20_INIT_VAL : string;
+ attribute C_PROBE_OUT20_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT20_WIDTH : integer;
+ attribute C_PROBE_OUT20_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT210_INIT_VAL : string;
+ attribute C_PROBE_OUT210_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT210_WIDTH : integer;
+ attribute C_PROBE_OUT210_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT211_INIT_VAL : string;
+ attribute C_PROBE_OUT211_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT211_WIDTH : integer;
+ attribute C_PROBE_OUT211_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT212_INIT_VAL : string;
+ attribute C_PROBE_OUT212_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT212_WIDTH : integer;
+ attribute C_PROBE_OUT212_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT213_INIT_VAL : string;
+ attribute C_PROBE_OUT213_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT213_WIDTH : integer;
+ attribute C_PROBE_OUT213_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT214_INIT_VAL : string;
+ attribute C_PROBE_OUT214_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT214_WIDTH : integer;
+ attribute C_PROBE_OUT214_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT215_INIT_VAL : string;
+ attribute C_PROBE_OUT215_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT215_WIDTH : integer;
+ attribute C_PROBE_OUT215_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT216_INIT_VAL : string;
+ attribute C_PROBE_OUT216_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT216_WIDTH : integer;
+ attribute C_PROBE_OUT216_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT217_INIT_VAL : string;
+ attribute C_PROBE_OUT217_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT217_WIDTH : integer;
+ attribute C_PROBE_OUT217_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT218_INIT_VAL : string;
+ attribute C_PROBE_OUT218_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT218_WIDTH : integer;
+ attribute C_PROBE_OUT218_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT219_INIT_VAL : string;
+ attribute C_PROBE_OUT219_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT219_WIDTH : integer;
+ attribute C_PROBE_OUT219_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT21_INIT_VAL : string;
+ attribute C_PROBE_OUT21_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT21_WIDTH : integer;
+ attribute C_PROBE_OUT21_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT220_INIT_VAL : string;
+ attribute C_PROBE_OUT220_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT220_WIDTH : integer;
+ attribute C_PROBE_OUT220_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT221_INIT_VAL : string;
+ attribute C_PROBE_OUT221_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT221_WIDTH : integer;
+ attribute C_PROBE_OUT221_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT222_INIT_VAL : string;
+ attribute C_PROBE_OUT222_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT222_WIDTH : integer;
+ attribute C_PROBE_OUT222_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT223_INIT_VAL : string;
+ attribute C_PROBE_OUT223_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT223_WIDTH : integer;
+ attribute C_PROBE_OUT223_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT224_INIT_VAL : string;
+ attribute C_PROBE_OUT224_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT224_WIDTH : integer;
+ attribute C_PROBE_OUT224_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT225_INIT_VAL : string;
+ attribute C_PROBE_OUT225_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT225_WIDTH : integer;
+ attribute C_PROBE_OUT225_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT226_INIT_VAL : string;
+ attribute C_PROBE_OUT226_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT226_WIDTH : integer;
+ attribute C_PROBE_OUT226_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT227_INIT_VAL : string;
+ attribute C_PROBE_OUT227_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT227_WIDTH : integer;
+ attribute C_PROBE_OUT227_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT228_INIT_VAL : string;
+ attribute C_PROBE_OUT228_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT228_WIDTH : integer;
+ attribute C_PROBE_OUT228_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT229_INIT_VAL : string;
+ attribute C_PROBE_OUT229_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT229_WIDTH : integer;
+ attribute C_PROBE_OUT229_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT22_INIT_VAL : string;
+ attribute C_PROBE_OUT22_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT22_WIDTH : integer;
+ attribute C_PROBE_OUT22_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT230_INIT_VAL : string;
+ attribute C_PROBE_OUT230_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT230_WIDTH : integer;
+ attribute C_PROBE_OUT230_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT231_INIT_VAL : string;
+ attribute C_PROBE_OUT231_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT231_WIDTH : integer;
+ attribute C_PROBE_OUT231_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT232_INIT_VAL : string;
+ attribute C_PROBE_OUT232_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT232_WIDTH : integer;
+ attribute C_PROBE_OUT232_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT233_INIT_VAL : string;
+ attribute C_PROBE_OUT233_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT233_WIDTH : integer;
+ attribute C_PROBE_OUT233_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT234_INIT_VAL : string;
+ attribute C_PROBE_OUT234_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT234_WIDTH : integer;
+ attribute C_PROBE_OUT234_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT235_INIT_VAL : string;
+ attribute C_PROBE_OUT235_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT235_WIDTH : integer;
+ attribute C_PROBE_OUT235_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT236_INIT_VAL : string;
+ attribute C_PROBE_OUT236_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT236_WIDTH : integer;
+ attribute C_PROBE_OUT236_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT237_INIT_VAL : string;
+ attribute C_PROBE_OUT237_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT237_WIDTH : integer;
+ attribute C_PROBE_OUT237_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT238_INIT_VAL : string;
+ attribute C_PROBE_OUT238_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT238_WIDTH : integer;
+ attribute C_PROBE_OUT238_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT239_INIT_VAL : string;
+ attribute C_PROBE_OUT239_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT239_WIDTH : integer;
+ attribute C_PROBE_OUT239_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT23_INIT_VAL : string;
+ attribute C_PROBE_OUT23_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT23_WIDTH : integer;
+ attribute C_PROBE_OUT23_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT240_INIT_VAL : string;
+ attribute C_PROBE_OUT240_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT240_WIDTH : integer;
+ attribute C_PROBE_OUT240_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT241_INIT_VAL : string;
+ attribute C_PROBE_OUT241_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT241_WIDTH : integer;
+ attribute C_PROBE_OUT241_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT242_INIT_VAL : string;
+ attribute C_PROBE_OUT242_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT242_WIDTH : integer;
+ attribute C_PROBE_OUT242_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT243_INIT_VAL : string;
+ attribute C_PROBE_OUT243_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT243_WIDTH : integer;
+ attribute C_PROBE_OUT243_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT244_INIT_VAL : string;
+ attribute C_PROBE_OUT244_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT244_WIDTH : integer;
+ attribute C_PROBE_OUT244_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT245_INIT_VAL : string;
+ attribute C_PROBE_OUT245_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT245_WIDTH : integer;
+ attribute C_PROBE_OUT245_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT246_INIT_VAL : string;
+ attribute C_PROBE_OUT246_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT246_WIDTH : integer;
+ attribute C_PROBE_OUT246_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT247_INIT_VAL : string;
+ attribute C_PROBE_OUT247_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT247_WIDTH : integer;
+ attribute C_PROBE_OUT247_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT248_INIT_VAL : string;
+ attribute C_PROBE_OUT248_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT248_WIDTH : integer;
+ attribute C_PROBE_OUT248_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT249_INIT_VAL : string;
+ attribute C_PROBE_OUT249_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT249_WIDTH : integer;
+ attribute C_PROBE_OUT249_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT24_INIT_VAL : string;
+ attribute C_PROBE_OUT24_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT24_WIDTH : integer;
+ attribute C_PROBE_OUT24_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT250_INIT_VAL : string;
+ attribute C_PROBE_OUT250_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT250_WIDTH : integer;
+ attribute C_PROBE_OUT250_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT251_INIT_VAL : string;
+ attribute C_PROBE_OUT251_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT251_WIDTH : integer;
+ attribute C_PROBE_OUT251_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT252_INIT_VAL : string;
+ attribute C_PROBE_OUT252_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT252_WIDTH : integer;
+ attribute C_PROBE_OUT252_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT253_INIT_VAL : string;
+ attribute C_PROBE_OUT253_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT253_WIDTH : integer;
+ attribute C_PROBE_OUT253_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT254_INIT_VAL : string;
+ attribute C_PROBE_OUT254_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT254_WIDTH : integer;
+ attribute C_PROBE_OUT254_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT255_INIT_VAL : string;
+ attribute C_PROBE_OUT255_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT255_WIDTH : integer;
+ attribute C_PROBE_OUT255_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT25_INIT_VAL : string;
+ attribute C_PROBE_OUT25_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT25_WIDTH : integer;
+ attribute C_PROBE_OUT25_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT26_INIT_VAL : string;
+ attribute C_PROBE_OUT26_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT26_WIDTH : integer;
+ attribute C_PROBE_OUT26_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT27_INIT_VAL : string;
+ attribute C_PROBE_OUT27_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT27_WIDTH : integer;
+ attribute C_PROBE_OUT27_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT28_INIT_VAL : string;
+ attribute C_PROBE_OUT28_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT28_WIDTH : integer;
+ attribute C_PROBE_OUT28_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT29_INIT_VAL : string;
+ attribute C_PROBE_OUT29_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT29_WIDTH : integer;
+ attribute C_PROBE_OUT29_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT2_INIT_VAL : string;
+ attribute C_PROBE_OUT2_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT2_WIDTH : integer;
+ attribute C_PROBE_OUT2_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT30_INIT_VAL : string;
+ attribute C_PROBE_OUT30_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT30_WIDTH : integer;
+ attribute C_PROBE_OUT30_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT31_INIT_VAL : string;
+ attribute C_PROBE_OUT31_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT31_WIDTH : integer;
+ attribute C_PROBE_OUT31_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT32_INIT_VAL : string;
+ attribute C_PROBE_OUT32_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT32_WIDTH : integer;
+ attribute C_PROBE_OUT32_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT33_INIT_VAL : string;
+ attribute C_PROBE_OUT33_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT33_WIDTH : integer;
+ attribute C_PROBE_OUT33_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT34_INIT_VAL : string;
+ attribute C_PROBE_OUT34_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT34_WIDTH : integer;
+ attribute C_PROBE_OUT34_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT35_INIT_VAL : string;
+ attribute C_PROBE_OUT35_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT35_WIDTH : integer;
+ attribute C_PROBE_OUT35_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT36_INIT_VAL : string;
+ attribute C_PROBE_OUT36_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT36_WIDTH : integer;
+ attribute C_PROBE_OUT36_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT37_INIT_VAL : string;
+ attribute C_PROBE_OUT37_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT37_WIDTH : integer;
+ attribute C_PROBE_OUT37_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT38_INIT_VAL : string;
+ attribute C_PROBE_OUT38_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT38_WIDTH : integer;
+ attribute C_PROBE_OUT38_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT39_INIT_VAL : string;
+ attribute C_PROBE_OUT39_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT39_WIDTH : integer;
+ attribute C_PROBE_OUT39_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT3_INIT_VAL : string;
+ attribute C_PROBE_OUT3_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT3_WIDTH : integer;
+ attribute C_PROBE_OUT3_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT40_INIT_VAL : string;
+ attribute C_PROBE_OUT40_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT40_WIDTH : integer;
+ attribute C_PROBE_OUT40_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT41_INIT_VAL : string;
+ attribute C_PROBE_OUT41_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT41_WIDTH : integer;
+ attribute C_PROBE_OUT41_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT42_INIT_VAL : string;
+ attribute C_PROBE_OUT42_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT42_WIDTH : integer;
+ attribute C_PROBE_OUT42_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT43_INIT_VAL : string;
+ attribute C_PROBE_OUT43_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT43_WIDTH : integer;
+ attribute C_PROBE_OUT43_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT44_INIT_VAL : string;
+ attribute C_PROBE_OUT44_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT44_WIDTH : integer;
+ attribute C_PROBE_OUT44_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT45_INIT_VAL : string;
+ attribute C_PROBE_OUT45_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT45_WIDTH : integer;
+ attribute C_PROBE_OUT45_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT46_INIT_VAL : string;
+ attribute C_PROBE_OUT46_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT46_WIDTH : integer;
+ attribute C_PROBE_OUT46_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT47_INIT_VAL : string;
+ attribute C_PROBE_OUT47_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT47_WIDTH : integer;
+ attribute C_PROBE_OUT47_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT48_INIT_VAL : string;
+ attribute C_PROBE_OUT48_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT48_WIDTH : integer;
+ attribute C_PROBE_OUT48_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT49_INIT_VAL : string;
+ attribute C_PROBE_OUT49_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT49_WIDTH : integer;
+ attribute C_PROBE_OUT49_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT4_INIT_VAL : string;
+ attribute C_PROBE_OUT4_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT4_WIDTH : integer;
+ attribute C_PROBE_OUT4_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT50_INIT_VAL : string;
+ attribute C_PROBE_OUT50_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT50_WIDTH : integer;
+ attribute C_PROBE_OUT50_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT51_INIT_VAL : string;
+ attribute C_PROBE_OUT51_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT51_WIDTH : integer;
+ attribute C_PROBE_OUT51_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT52_INIT_VAL : string;
+ attribute C_PROBE_OUT52_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT52_WIDTH : integer;
+ attribute C_PROBE_OUT52_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT53_INIT_VAL : string;
+ attribute C_PROBE_OUT53_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT53_WIDTH : integer;
+ attribute C_PROBE_OUT53_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT54_INIT_VAL : string;
+ attribute C_PROBE_OUT54_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT54_WIDTH : integer;
+ attribute C_PROBE_OUT54_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT55_INIT_VAL : string;
+ attribute C_PROBE_OUT55_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT55_WIDTH : integer;
+ attribute C_PROBE_OUT55_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT56_INIT_VAL : string;
+ attribute C_PROBE_OUT56_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT56_WIDTH : integer;
+ attribute C_PROBE_OUT56_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT57_INIT_VAL : string;
+ attribute C_PROBE_OUT57_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT57_WIDTH : integer;
+ attribute C_PROBE_OUT57_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT58_INIT_VAL : string;
+ attribute C_PROBE_OUT58_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT58_WIDTH : integer;
+ attribute C_PROBE_OUT58_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT59_INIT_VAL : string;
+ attribute C_PROBE_OUT59_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT59_WIDTH : integer;
+ attribute C_PROBE_OUT59_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT5_INIT_VAL : string;
+ attribute C_PROBE_OUT5_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT5_WIDTH : integer;
+ attribute C_PROBE_OUT5_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT60_INIT_VAL : string;
+ attribute C_PROBE_OUT60_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT60_WIDTH : integer;
+ attribute C_PROBE_OUT60_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT61_INIT_VAL : string;
+ attribute C_PROBE_OUT61_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT61_WIDTH : integer;
+ attribute C_PROBE_OUT61_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT62_INIT_VAL : string;
+ attribute C_PROBE_OUT62_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT62_WIDTH : integer;
+ attribute C_PROBE_OUT62_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT63_INIT_VAL : string;
+ attribute C_PROBE_OUT63_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT63_WIDTH : integer;
+ attribute C_PROBE_OUT63_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT64_INIT_VAL : string;
+ attribute C_PROBE_OUT64_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT64_WIDTH : integer;
+ attribute C_PROBE_OUT64_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT65_INIT_VAL : string;
+ attribute C_PROBE_OUT65_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT65_WIDTH : integer;
+ attribute C_PROBE_OUT65_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT66_INIT_VAL : string;
+ attribute C_PROBE_OUT66_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT66_WIDTH : integer;
+ attribute C_PROBE_OUT66_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT67_INIT_VAL : string;
+ attribute C_PROBE_OUT67_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT67_WIDTH : integer;
+ attribute C_PROBE_OUT67_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT68_INIT_VAL : string;
+ attribute C_PROBE_OUT68_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT68_WIDTH : integer;
+ attribute C_PROBE_OUT68_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT69_INIT_VAL : string;
+ attribute C_PROBE_OUT69_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT69_WIDTH : integer;
+ attribute C_PROBE_OUT69_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT6_INIT_VAL : string;
+ attribute C_PROBE_OUT6_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT6_WIDTH : integer;
+ attribute C_PROBE_OUT6_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT70_INIT_VAL : string;
+ attribute C_PROBE_OUT70_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT70_WIDTH : integer;
+ attribute C_PROBE_OUT70_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT71_INIT_VAL : string;
+ attribute C_PROBE_OUT71_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT71_WIDTH : integer;
+ attribute C_PROBE_OUT71_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT72_INIT_VAL : string;
+ attribute C_PROBE_OUT72_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT72_WIDTH : integer;
+ attribute C_PROBE_OUT72_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT73_INIT_VAL : string;
+ attribute C_PROBE_OUT73_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT73_WIDTH : integer;
+ attribute C_PROBE_OUT73_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT74_INIT_VAL : string;
+ attribute C_PROBE_OUT74_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT74_WIDTH : integer;
+ attribute C_PROBE_OUT74_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT75_INIT_VAL : string;
+ attribute C_PROBE_OUT75_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT75_WIDTH : integer;
+ attribute C_PROBE_OUT75_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT76_INIT_VAL : string;
+ attribute C_PROBE_OUT76_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT76_WIDTH : integer;
+ attribute C_PROBE_OUT76_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT77_INIT_VAL : string;
+ attribute C_PROBE_OUT77_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT77_WIDTH : integer;
+ attribute C_PROBE_OUT77_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT78_INIT_VAL : string;
+ attribute C_PROBE_OUT78_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT78_WIDTH : integer;
+ attribute C_PROBE_OUT78_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT79_INIT_VAL : string;
+ attribute C_PROBE_OUT79_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT79_WIDTH : integer;
+ attribute C_PROBE_OUT79_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT7_INIT_VAL : string;
+ attribute C_PROBE_OUT7_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT7_WIDTH : integer;
+ attribute C_PROBE_OUT7_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT80_INIT_VAL : string;
+ attribute C_PROBE_OUT80_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT80_WIDTH : integer;
+ attribute C_PROBE_OUT80_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT81_INIT_VAL : string;
+ attribute C_PROBE_OUT81_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT81_WIDTH : integer;
+ attribute C_PROBE_OUT81_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT82_INIT_VAL : string;
+ attribute C_PROBE_OUT82_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT82_WIDTH : integer;
+ attribute C_PROBE_OUT82_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT83_INIT_VAL : string;
+ attribute C_PROBE_OUT83_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT83_WIDTH : integer;
+ attribute C_PROBE_OUT83_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT84_INIT_VAL : string;
+ attribute C_PROBE_OUT84_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT84_WIDTH : integer;
+ attribute C_PROBE_OUT84_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT85_INIT_VAL : string;
+ attribute C_PROBE_OUT85_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT85_WIDTH : integer;
+ attribute C_PROBE_OUT85_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT86_INIT_VAL : string;
+ attribute C_PROBE_OUT86_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT86_WIDTH : integer;
+ attribute C_PROBE_OUT86_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT87_INIT_VAL : string;
+ attribute C_PROBE_OUT87_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT87_WIDTH : integer;
+ attribute C_PROBE_OUT87_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT88_INIT_VAL : string;
+ attribute C_PROBE_OUT88_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT88_WIDTH : integer;
+ attribute C_PROBE_OUT88_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT89_INIT_VAL : string;
+ attribute C_PROBE_OUT89_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT89_WIDTH : integer;
+ attribute C_PROBE_OUT89_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT8_INIT_VAL : string;
+ attribute C_PROBE_OUT8_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT8_WIDTH : integer;
+ attribute C_PROBE_OUT8_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT90_INIT_VAL : string;
+ attribute C_PROBE_OUT90_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT90_WIDTH : integer;
+ attribute C_PROBE_OUT90_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT91_INIT_VAL : string;
+ attribute C_PROBE_OUT91_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT91_WIDTH : integer;
+ attribute C_PROBE_OUT91_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT92_INIT_VAL : string;
+ attribute C_PROBE_OUT92_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT92_WIDTH : integer;
+ attribute C_PROBE_OUT92_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT93_INIT_VAL : string;
+ attribute C_PROBE_OUT93_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT93_WIDTH : integer;
+ attribute C_PROBE_OUT93_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT94_INIT_VAL : string;
+ attribute C_PROBE_OUT94_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT94_WIDTH : integer;
+ attribute C_PROBE_OUT94_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT95_INIT_VAL : string;
+ attribute C_PROBE_OUT95_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT95_WIDTH : integer;
+ attribute C_PROBE_OUT95_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT96_INIT_VAL : string;
+ attribute C_PROBE_OUT96_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT96_WIDTH : integer;
+ attribute C_PROBE_OUT96_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT97_INIT_VAL : string;
+ attribute C_PROBE_OUT97_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT97_WIDTH : integer;
+ attribute C_PROBE_OUT97_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT98_INIT_VAL : string;
+ attribute C_PROBE_OUT98_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT98_WIDTH : integer;
+ attribute C_PROBE_OUT98_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT99_INIT_VAL : string;
+ attribute C_PROBE_OUT99_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT99_WIDTH : integer;
+ attribute C_PROBE_OUT99_WIDTH of inst : label is 1;
+ attribute C_PROBE_OUT9_INIT_VAL : string;
+ attribute C_PROBE_OUT9_INIT_VAL of inst : label is "1'b0";
+ attribute C_PROBE_OUT9_WIDTH : integer;
+ attribute C_PROBE_OUT9_WIDTH of inst : label is 1;
+ attribute C_USE_TEST_REG : integer;
+ attribute C_USE_TEST_REG of inst : label is 1;
+ attribute C_XDEVICEFAMILY : string;
+ attribute C_XDEVICEFAMILY of inst : label is "kintexu";
+ attribute C_XLNX_HW_PROBE_INFO : string;
+ attribute C_XLNX_HW_PROBE_INFO of inst : label is "DEFAULT";
+ attribute C_XSDB_SLAVE_TYPE : integer;
+ attribute C_XSDB_SLAVE_TYPE of inst : label is 33;
+ attribute DONT_TOUCH : boolean;
+ attribute DONT_TOUCH of inst : label is std.standard.true;
+ attribute DowngradeIPIdentifiedWarnings : string;
+ attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
+ attribute KEEP_HIERARCHY : string;
+ attribute KEEP_HIERARCHY of inst : label is "soft";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001101000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001101001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001110000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001110001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001111000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001111001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000010000000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000010000001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010001000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010001001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000010000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010010000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010010001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000010001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010011000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010011001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010100000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010100001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010101000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010101001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010110000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010110001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010111000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010111001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000011000000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000011000001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011001000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011001001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011010000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011010001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011011000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011011001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000011000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011100000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011100001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000011001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011101000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011101001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011110000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011110001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011111000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011111001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000100000000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000100000001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000100000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000100001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000101000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000101001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000110000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000110001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000111000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000111001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000001000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000001000000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000001000001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000001001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001001000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001001001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001010000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001010001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001011000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001011001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011101";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011110";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011111";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001100000";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001100001";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100010";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100011";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100100";
+ attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string;
+ attribute LC_HIGH_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT0 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT1 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT10 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT100 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT101 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT102 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001101000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT103 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001101001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT104 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT105 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT106 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT107 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT108 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT109 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT11 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT110 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001110000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT111 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001110001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT112 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT113 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT114 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT115 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT116 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT117 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT118 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001111000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT119 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001111001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT12 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT120 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT121 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT122 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT123 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT124 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT125 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT126 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000010000000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT127 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000010000001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT128 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT129 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT13 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT130 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT131 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT132 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT133 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT134 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010001000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT135 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010001001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT136 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT137 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT138 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT139 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT14 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000010000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT140 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT141 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT142 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010010000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT143 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010010001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT144 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT145 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT146 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT147 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT148 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT149 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT15 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000010001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT150 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010011000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT151 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010011001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT152 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT153 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT154 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT155 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT156 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT157 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT158 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010100000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT159 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010100001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT16 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT160 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT161 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT162 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT163 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT164 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT165 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT166 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010101000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT167 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010101001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT168 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT169 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT17 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT170 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT171 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT172 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT173 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT174 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010110000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT175 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010110001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT176 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT177 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT178 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT179 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT18 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT180 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT181 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT182 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010111000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT183 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010111001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT184 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT185 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT186 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT187 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT188 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT189 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT19 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT190 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000011000000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT191 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000011000001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT192 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT193 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT194 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT195 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT196 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT197 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT198 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011001000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT199 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011001001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT2 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT20 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT200 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT201 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT202 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT203 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT204 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT205 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT206 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011010000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT207 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011010001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT208 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT209 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT21 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT210 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT211 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT212 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT213 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT214 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011011000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT215 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011011001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT216 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT217 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT218 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT219 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT22 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000011000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT220 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT221 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT222 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011100000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT223 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011100001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT224 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT225 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT226 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT227 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT228 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT229 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT23 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000011001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT230 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011101000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT231 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011101001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT232 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT233 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT234 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT235 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT236 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT237 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT238 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011110000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT239 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011110001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT24 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT240 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT241 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT242 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT243 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT244 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT245 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT246 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011111000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT247 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011111001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT248 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT249 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT25 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT250 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT251 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT252 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT253 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT254 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000100000000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT255 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000100000001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT26 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT27 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT28 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT29 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT3 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT30 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000100000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT31 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000100001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT32 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT33 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT34 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT35 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT36 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT37 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT38 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000101000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT39 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000101001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT4 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT40 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT41 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT42 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT43 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT44 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT45 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT46 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000110000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT47 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000110001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT48 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT49 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT5 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT50 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT51 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT52 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT53 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT54 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000111000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT55 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000111001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT56 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT57 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT58 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT59 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT6 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000001000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT60 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT61 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT62 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000001000000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT63 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000001000001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT64 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT65 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT66 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT67 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT68 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT69 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT7 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000001001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT70 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001001000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT71 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001001001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT72 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT73 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT74 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT75 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT76 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT77 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT78 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001010000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT79 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001010001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT8 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT80 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT81 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT82 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT83 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT84 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT85 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT86 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001011000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT87 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001011001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT88 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT89 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT9 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT90 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT91 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011101";
+ attribute LC_LOW_BIT_POS_PROBE_OUT92 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011110";
+ attribute LC_LOW_BIT_POS_PROBE_OUT93 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011111";
+ attribute LC_LOW_BIT_POS_PROBE_OUT94 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001100000";
+ attribute LC_LOW_BIT_POS_PROBE_OUT95 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001100001";
+ attribute LC_LOW_BIT_POS_PROBE_OUT96 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100010";
+ attribute LC_LOW_BIT_POS_PROBE_OUT97 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100011";
+ attribute LC_LOW_BIT_POS_PROBE_OUT98 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100100";
+ attribute LC_LOW_BIT_POS_PROBE_OUT99 : string;
+ attribute LC_LOW_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100101";
+ attribute LC_PROBE_IN_WIDTH_STRING : string;
+ attribute LC_PROBE_IN_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string;
+ attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of inst : label is "4096'b0000000100000001000000010000000000000000111111110000000011111110000000001111110100000000111111000000000011111011000000001111101000000000111110010000000011111000000000001111011100000000111101100000000011110101000000001111010000000000111100110000000011110010000000001111000100000000111100000000000011101111000000001110111000000000111011010000000011101100000000001110101100000000111010100000000011101001000000001110100000000000111001110000000011100110000000001110010100000000111001000000000011100011000000001110001000000000111000010000000011100000000000001101111100000000110111100000000011011101000000001101110000000000110110110000000011011010000000001101100100000000110110000000000011010111000000001101011000000000110101010000000011010100000000001101001100000000110100100000000011010001000000001101000000000000110011110000000011001110000000001100110100000000110011000000000011001011000000001100101000000000110010010000000011001000000000001100011100000000110001100000000011000101000000001100010000000000110000110000000011000010000000001100000100000000110000000000000010111111000000001011111000000000101111010000000010111100000000001011101100000000101110100000000010111001000000001011100000000000101101110000000010110110000000001011010100000000101101000000000010110011000000001011001000000000101100010000000010110000000000001010111100000000101011100000000010101101000000001010110000000000101010110000000010101010000000001010100100000000101010000000000010100111000000001010011000000000101001010000000010100100000000001010001100000000101000100000000010100001000000001010000000000000100111110000000010011110000000001001110100000000100111000000000010011011000000001001101000000000100110010000000010011000000000001001011100000000100101100000000010010101000000001001010000000000100100110000000010010010000000001001000100000000100100000000000010001111000000001000111000000000100011010000000010001100000000001000101100000000100010100000000010001001000000001000100000000000100001110000000010000110000000001000010100000000100001000000000010000011000000001000001000000000100000010000000010000000000000000111111100000000011111100000000001111101000000000111110000000000011110110000000001111010000000000111100100000000011110000000000001110111000000000111011000000000011101010000000001110100000000000111001100000000011100100000000001110001000000000111000000000000011011110000000001101110000000000110110100000000011011000000000001101011000000000110101000000000011010010000000001101000000000000110011100000000011001100000000001100101000000000110010000000000011000110000000001100010000000000110000100000000011000000000000001011111000000000101111000000000010111010000000001011100000000000101101100000000010110100000000001011001000000000101100000000000010101110000000001010110000000000101010100000000010101000000000001010011000000000101001000000000010100010000000001010000000000000100111100000000010011100000000001001101000000000100110000000000010010110000000001001010000000000100100100000000010010000000000001000111000000000100011000000000010001010000000001000100000000000100001100000000010000100000000001000001000000000100000000000000001111110000000000111110000000000011110100000000001111000000000000111011000000000011101000000000001110010000000000111000000000000011011100000000001101100000000000110101000000000011010000000000001100110000000000110010000000000011000100000000001100000000000000101111000000000010111000000000001011010000000000101100000000000010101100000000001010100000000000101001000000000010100000000000001001110000000000100110000000000010010100000000001001000000000000100011000000000010001000000000001000010000000000100000000000000001111100000000000111100000000000011101000000000001110000000000000110110000000000011010000000000001100100000000000110000000000000010111000000000001011000000000000101010000000000010100000000000001001100000000000100100000000000010001000000000001000000000000000011110000000000001110000000000000110100000000000011000000000000001011000000000000101000000000000010010000000000001000000000000000011100000000000001100000000000000101000000000000010000000000000000110000000000000010";
+ attribute LC_PROBE_OUT_INIT_VAL_STRING : string;
+ attribute LC_PROBE_OUT_INIT_VAL_STRING of inst : label is "258'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010";
+ attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string;
+ attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of inst : label is "4096'b0000000100000001000000010000000000000000111111110000000011111110000000001111110100000000111111000000000011111011000000001111101000000000111110010000000011111000000000001111011100000000111101100000000011110101000000001111010000000000111100110000000011110010000000001111000100000000111100000000000011101111000000001110111000000000111011010000000011101100000000001110101100000000111010100000000011101001000000001110100000000000111001110000000011100110000000001110010100000000111001000000000011100011000000001110001000000000111000010000000011100000000000001101111100000000110111100000000011011101000000001101110000000000110110110000000011011010000000001101100100000000110110000000000011010111000000001101011000000000110101010000000011010100000000001101001100000000110100100000000011010001000000001101000000000000110011110000000011001110000000001100110100000000110011000000000011001011000000001100101000000000110010010000000011001000000000001100011100000000110001100000000011000101000000001100010000000000110000110000000011000010000000001100000100000000110000000000000010111111000000001011111000000000101111010000000010111100000000001011101100000000101110100000000010111001000000001011100000000000101101110000000010110110000000001011010100000000101101000000000010110011000000001011001000000000101100010000000010110000000000001010111100000000101011100000000010101101000000001010110000000000101010110000000010101010000000001010100100000000101010000000000010100111000000001010011000000000101001010000000010100100000000001010001100000000101000100000000010100001000000001010000000000000100111110000000010011110000000001001110100000000100111000000000010011011000000001001101000000000100110010000000010011000000000001001011100000000100101100000000010010101000000001001010000000000100100110000000010010010000000001001000100000000100100000000000010001111000000001000111000000000100011010000000010001100000000001000101100000000100010100000000010001001000000001000100000000000100001110000000010000110000000001000010100000000100001000000000010000011000000001000001000000000100000010000000010000000000000000111111100000000011111100000000001111101000000000111110000000000011110110000000001111010000000000111100100000000011110000000000001110111000000000111011000000000011101010000000001110100000000000111001100000000011100100000000001110001000000000111000000000000011011110000000001101110000000000110110100000000011011000000000001101011000000000110101000000000011010010000000001101000000000000110011100000000011001100000000001100101000000000110010000000000011000110000000001100010000000000110000100000000011000000000000001011111000000000101111000000000010111010000000001011100000000000101101100000000010110100000000001011001000000000101100000000000010101110000000001010110000000000101010100000000010101000000000001010011000000000101001000000000010100010000000001010000000000000100111100000000010011100000000001001101000000000100110000000000010010110000000001001010000000000100100100000000010010000000000001000111000000000100011000000000010001010000000001000100000000000100001100000000010000100000000001000001000000000100000000000000001111110000000000111110000000000011110100000000001111000000000000111011000000000011101000000000001110010000000000111000000000000011011100000000001101100000000000110101000000000011010000000000001100110000000000110010000000000011000100000000001100000000000000101111000000000010111000000000001011010000000000101100000000000010101100000000001010100000000000101001000000000010100000000000001001110000000000100110000000000010010100000000001001000000000000100011000000000010001000000000001000010000000000100000000000000001111100000000000111100000000000011101000000000001110000000000000110110000000000011010000000000001100100000000000110000000000000010111000000000001011000000000000101010000000000010100000000000001001100000000000100100000000000010001000000000001000000000000000011110000000000001110000000000000110100000000000011000000000000001011000000000000101000000000000010010000000000001000000000000000011100000000000001100000000000000101000000000000010000000000000000110000000000000000";
+ attribute LC_PROBE_OUT_WIDTH_STRING : string;
+ attribute LC_PROBE_OUT_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
+ attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
+ attribute LC_TOTAL_PROBE_IN_WIDTH of inst : label is 0;
+ attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
+ attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 5;
+ attribute is_du_within_envelope : string;
+ attribute is_du_within_envelope of inst : label is "true";
+ attribute syn_noprune : string;
+ attribute syn_noprune of inst : label is "1";
+begin
+ inst: entity work.vio_tclink_clk40_reset_vio_v3_0_25_vio
+ port map (
+ clk => clk,
+ probe_in0(0) => '0',
+ probe_in1(0) => '0',
+ probe_in10(0) => '0',
+ probe_in100(0) => '0',
+ probe_in101(0) => '0',
+ probe_in102(0) => '0',
+ probe_in103(0) => '0',
+ probe_in104(0) => '0',
+ probe_in105(0) => '0',
+ probe_in106(0) => '0',
+ probe_in107(0) => '0',
+ probe_in108(0) => '0',
+ probe_in109(0) => '0',
+ probe_in11(0) => '0',
+ probe_in110(0) => '0',
+ probe_in111(0) => '0',
+ probe_in112(0) => '0',
+ probe_in113(0) => '0',
+ probe_in114(0) => '0',
+ probe_in115(0) => '0',
+ probe_in116(0) => '0',
+ probe_in117(0) => '0',
+ probe_in118(0) => '0',
+ probe_in119(0) => '0',
+ probe_in12(0) => '0',
+ probe_in120(0) => '0',
+ probe_in121(0) => '0',
+ probe_in122(0) => '0',
+ probe_in123(0) => '0',
+ probe_in124(0) => '0',
+ probe_in125(0) => '0',
+ probe_in126(0) => '0',
+ probe_in127(0) => '0',
+ probe_in128(0) => '0',
+ probe_in129(0) => '0',
+ probe_in13(0) => '0',
+ probe_in130(0) => '0',
+ probe_in131(0) => '0',
+ probe_in132(0) => '0',
+ probe_in133(0) => '0',
+ probe_in134(0) => '0',
+ probe_in135(0) => '0',
+ probe_in136(0) => '0',
+ probe_in137(0) => '0',
+ probe_in138(0) => '0',
+ probe_in139(0) => '0',
+ probe_in14(0) => '0',
+ probe_in140(0) => '0',
+ probe_in141(0) => '0',
+ probe_in142(0) => '0',
+ probe_in143(0) => '0',
+ probe_in144(0) => '0',
+ probe_in145(0) => '0',
+ probe_in146(0) => '0',
+ probe_in147(0) => '0',
+ probe_in148(0) => '0',
+ probe_in149(0) => '0',
+ probe_in15(0) => '0',
+ probe_in150(0) => '0',
+ probe_in151(0) => '0',
+ probe_in152(0) => '0',
+ probe_in153(0) => '0',
+ probe_in154(0) => '0',
+ probe_in155(0) => '0',
+ probe_in156(0) => '0',
+ probe_in157(0) => '0',
+ probe_in158(0) => '0',
+ probe_in159(0) => '0',
+ probe_in16(0) => '0',
+ probe_in160(0) => '0',
+ probe_in161(0) => '0',
+ probe_in162(0) => '0',
+ probe_in163(0) => '0',
+ probe_in164(0) => '0',
+ probe_in165(0) => '0',
+ probe_in166(0) => '0',
+ probe_in167(0) => '0',
+ probe_in168(0) => '0',
+ probe_in169(0) => '0',
+ probe_in17(0) => '0',
+ probe_in170(0) => '0',
+ probe_in171(0) => '0',
+ probe_in172(0) => '0',
+ probe_in173(0) => '0',
+ probe_in174(0) => '0',
+ probe_in175(0) => '0',
+ probe_in176(0) => '0',
+ probe_in177(0) => '0',
+ probe_in178(0) => '0',
+ probe_in179(0) => '0',
+ probe_in18(0) => '0',
+ probe_in180(0) => '0',
+ probe_in181(0) => '0',
+ probe_in182(0) => '0',
+ probe_in183(0) => '0',
+ probe_in184(0) => '0',
+ probe_in185(0) => '0',
+ probe_in186(0) => '0',
+ probe_in187(0) => '0',
+ probe_in188(0) => '0',
+ probe_in189(0) => '0',
+ probe_in19(0) => '0',
+ probe_in190(0) => '0',
+ probe_in191(0) => '0',
+ probe_in192(0) => '0',
+ probe_in193(0) => '0',
+ probe_in194(0) => '0',
+ probe_in195(0) => '0',
+ probe_in196(0) => '0',
+ probe_in197(0) => '0',
+ probe_in198(0) => '0',
+ probe_in199(0) => '0',
+ probe_in2(0) => '0',
+ probe_in20(0) => '0',
+ probe_in200(0) => '0',
+ probe_in201(0) => '0',
+ probe_in202(0) => '0',
+ probe_in203(0) => '0',
+ probe_in204(0) => '0',
+ probe_in205(0) => '0',
+ probe_in206(0) => '0',
+ probe_in207(0) => '0',
+ probe_in208(0) => '0',
+ probe_in209(0) => '0',
+ probe_in21(0) => '0',
+ probe_in210(0) => '0',
+ probe_in211(0) => '0',
+ probe_in212(0) => '0',
+ probe_in213(0) => '0',
+ probe_in214(0) => '0',
+ probe_in215(0) => '0',
+ probe_in216(0) => '0',
+ probe_in217(0) => '0',
+ probe_in218(0) => '0',
+ probe_in219(0) => '0',
+ probe_in22(0) => '0',
+ probe_in220(0) => '0',
+ probe_in221(0) => '0',
+ probe_in222(0) => '0',
+ probe_in223(0) => '0',
+ probe_in224(0) => '0',
+ probe_in225(0) => '0',
+ probe_in226(0) => '0',
+ probe_in227(0) => '0',
+ probe_in228(0) => '0',
+ probe_in229(0) => '0',
+ probe_in23(0) => '0',
+ probe_in230(0) => '0',
+ probe_in231(0) => '0',
+ probe_in232(0) => '0',
+ probe_in233(0) => '0',
+ probe_in234(0) => '0',
+ probe_in235(0) => '0',
+ probe_in236(0) => '0',
+ probe_in237(0) => '0',
+ probe_in238(0) => '0',
+ probe_in239(0) => '0',
+ probe_in24(0) => '0',
+ probe_in240(0) => '0',
+ probe_in241(0) => '0',
+ probe_in242(0) => '0',
+ probe_in243(0) => '0',
+ probe_in244(0) => '0',
+ probe_in245(0) => '0',
+ probe_in246(0) => '0',
+ probe_in247(0) => '0',
+ probe_in248(0) => '0',
+ probe_in249(0) => '0',
+ probe_in25(0) => '0',
+ probe_in250(0) => '0',
+ probe_in251(0) => '0',
+ probe_in252(0) => '0',
+ probe_in253(0) => '0',
+ probe_in254(0) => '0',
+ probe_in255(0) => '0',
+ probe_in26(0) => '0',
+ probe_in27(0) => '0',
+ probe_in28(0) => '0',
+ probe_in29(0) => '0',
+ probe_in3(0) => '0',
+ probe_in30(0) => '0',
+ probe_in31(0) => '0',
+ probe_in32(0) => '0',
+ probe_in33(0) => '0',
+ probe_in34(0) => '0',
+ probe_in35(0) => '0',
+ probe_in36(0) => '0',
+ probe_in37(0) => '0',
+ probe_in38(0) => '0',
+ probe_in39(0) => '0',
+ probe_in4(0) => '0',
+ probe_in40(0) => '0',
+ probe_in41(0) => '0',
+ probe_in42(0) => '0',
+ probe_in43(0) => '0',
+ probe_in44(0) => '0',
+ probe_in45(0) => '0',
+ probe_in46(0) => '0',
+ probe_in47(0) => '0',
+ probe_in48(0) => '0',
+ probe_in49(0) => '0',
+ probe_in5(0) => '0',
+ probe_in50(0) => '0',
+ probe_in51(0) => '0',
+ probe_in52(0) => '0',
+ probe_in53(0) => '0',
+ probe_in54(0) => '0',
+ probe_in55(0) => '0',
+ probe_in56(0) => '0',
+ probe_in57(0) => '0',
+ probe_in58(0) => '0',
+ probe_in59(0) => '0',
+ probe_in6(0) => '0',
+ probe_in60(0) => '0',
+ probe_in61(0) => '0',
+ probe_in62(0) => '0',
+ probe_in63(0) => '0',
+ probe_in64(0) => '0',
+ probe_in65(0) => '0',
+ probe_in66(0) => '0',
+ probe_in67(0) => '0',
+ probe_in68(0) => '0',
+ probe_in69(0) => '0',
+ probe_in7(0) => '0',
+ probe_in70(0) => '0',
+ probe_in71(0) => '0',
+ probe_in72(0) => '0',
+ probe_in73(0) => '0',
+ probe_in74(0) => '0',
+ probe_in75(0) => '0',
+ probe_in76(0) => '0',
+ probe_in77(0) => '0',
+ probe_in78(0) => '0',
+ probe_in79(0) => '0',
+ probe_in8(0) => '0',
+ probe_in80(0) => '0',
+ probe_in81(0) => '0',
+ probe_in82(0) => '0',
+ probe_in83(0) => '0',
+ probe_in84(0) => '0',
+ probe_in85(0) => '0',
+ probe_in86(0) => '0',
+ probe_in87(0) => '0',
+ probe_in88(0) => '0',
+ probe_in89(0) => '0',
+ probe_in9(0) => '0',
+ probe_in90(0) => '0',
+ probe_in91(0) => '0',
+ probe_in92(0) => '0',
+ probe_in93(0) => '0',
+ probe_in94(0) => '0',
+ probe_in95(0) => '0',
+ probe_in96(0) => '0',
+ probe_in97(0) => '0',
+ probe_in98(0) => '0',
+ probe_in99(0) => '0',
+ probe_out0(2 downto 0) => probe_out0(2 downto 0),
+ probe_out1(0) => probe_out1(0),
+ probe_out10(0) => NLW_inst_probe_out10_UNCONNECTED(0),
+ probe_out100(0) => NLW_inst_probe_out100_UNCONNECTED(0),
+ probe_out101(0) => NLW_inst_probe_out101_UNCONNECTED(0),
+ probe_out102(0) => NLW_inst_probe_out102_UNCONNECTED(0),
+ probe_out103(0) => NLW_inst_probe_out103_UNCONNECTED(0),
+ probe_out104(0) => NLW_inst_probe_out104_UNCONNECTED(0),
+ probe_out105(0) => NLW_inst_probe_out105_UNCONNECTED(0),
+ probe_out106(0) => NLW_inst_probe_out106_UNCONNECTED(0),
+ probe_out107(0) => NLW_inst_probe_out107_UNCONNECTED(0),
+ probe_out108(0) => NLW_inst_probe_out108_UNCONNECTED(0),
+ probe_out109(0) => NLW_inst_probe_out109_UNCONNECTED(0),
+ probe_out11(0) => NLW_inst_probe_out11_UNCONNECTED(0),
+ probe_out110(0) => NLW_inst_probe_out110_UNCONNECTED(0),
+ probe_out111(0) => NLW_inst_probe_out111_UNCONNECTED(0),
+ probe_out112(0) => NLW_inst_probe_out112_UNCONNECTED(0),
+ probe_out113(0) => NLW_inst_probe_out113_UNCONNECTED(0),
+ probe_out114(0) => NLW_inst_probe_out114_UNCONNECTED(0),
+ probe_out115(0) => NLW_inst_probe_out115_UNCONNECTED(0),
+ probe_out116(0) => NLW_inst_probe_out116_UNCONNECTED(0),
+ probe_out117(0) => NLW_inst_probe_out117_UNCONNECTED(0),
+ probe_out118(0) => NLW_inst_probe_out118_UNCONNECTED(0),
+ probe_out119(0) => NLW_inst_probe_out119_UNCONNECTED(0),
+ probe_out12(0) => NLW_inst_probe_out12_UNCONNECTED(0),
+ probe_out120(0) => NLW_inst_probe_out120_UNCONNECTED(0),
+ probe_out121(0) => NLW_inst_probe_out121_UNCONNECTED(0),
+ probe_out122(0) => NLW_inst_probe_out122_UNCONNECTED(0),
+ probe_out123(0) => NLW_inst_probe_out123_UNCONNECTED(0),
+ probe_out124(0) => NLW_inst_probe_out124_UNCONNECTED(0),
+ probe_out125(0) => NLW_inst_probe_out125_UNCONNECTED(0),
+ probe_out126(0) => NLW_inst_probe_out126_UNCONNECTED(0),
+ probe_out127(0) => NLW_inst_probe_out127_UNCONNECTED(0),
+ probe_out128(0) => NLW_inst_probe_out128_UNCONNECTED(0),
+ probe_out129(0) => NLW_inst_probe_out129_UNCONNECTED(0),
+ probe_out13(0) => NLW_inst_probe_out13_UNCONNECTED(0),
+ probe_out130(0) => NLW_inst_probe_out130_UNCONNECTED(0),
+ probe_out131(0) => NLW_inst_probe_out131_UNCONNECTED(0),
+ probe_out132(0) => NLW_inst_probe_out132_UNCONNECTED(0),
+ probe_out133(0) => NLW_inst_probe_out133_UNCONNECTED(0),
+ probe_out134(0) => NLW_inst_probe_out134_UNCONNECTED(0),
+ probe_out135(0) => NLW_inst_probe_out135_UNCONNECTED(0),
+ probe_out136(0) => NLW_inst_probe_out136_UNCONNECTED(0),
+ probe_out137(0) => NLW_inst_probe_out137_UNCONNECTED(0),
+ probe_out138(0) => NLW_inst_probe_out138_UNCONNECTED(0),
+ probe_out139(0) => NLW_inst_probe_out139_UNCONNECTED(0),
+ probe_out14(0) => NLW_inst_probe_out14_UNCONNECTED(0),
+ probe_out140(0) => NLW_inst_probe_out140_UNCONNECTED(0),
+ probe_out141(0) => NLW_inst_probe_out141_UNCONNECTED(0),
+ probe_out142(0) => NLW_inst_probe_out142_UNCONNECTED(0),
+ probe_out143(0) => NLW_inst_probe_out143_UNCONNECTED(0),
+ probe_out144(0) => NLW_inst_probe_out144_UNCONNECTED(0),
+ probe_out145(0) => NLW_inst_probe_out145_UNCONNECTED(0),
+ probe_out146(0) => NLW_inst_probe_out146_UNCONNECTED(0),
+ probe_out147(0) => NLW_inst_probe_out147_UNCONNECTED(0),
+ probe_out148(0) => NLW_inst_probe_out148_UNCONNECTED(0),
+ probe_out149(0) => NLW_inst_probe_out149_UNCONNECTED(0),
+ probe_out15(0) => NLW_inst_probe_out15_UNCONNECTED(0),
+ probe_out150(0) => NLW_inst_probe_out150_UNCONNECTED(0),
+ probe_out151(0) => NLW_inst_probe_out151_UNCONNECTED(0),
+ probe_out152(0) => NLW_inst_probe_out152_UNCONNECTED(0),
+ probe_out153(0) => NLW_inst_probe_out153_UNCONNECTED(0),
+ probe_out154(0) => NLW_inst_probe_out154_UNCONNECTED(0),
+ probe_out155(0) => NLW_inst_probe_out155_UNCONNECTED(0),
+ probe_out156(0) => NLW_inst_probe_out156_UNCONNECTED(0),
+ probe_out157(0) => NLW_inst_probe_out157_UNCONNECTED(0),
+ probe_out158(0) => NLW_inst_probe_out158_UNCONNECTED(0),
+ probe_out159(0) => NLW_inst_probe_out159_UNCONNECTED(0),
+ probe_out16(0) => NLW_inst_probe_out16_UNCONNECTED(0),
+ probe_out160(0) => NLW_inst_probe_out160_UNCONNECTED(0),
+ probe_out161(0) => NLW_inst_probe_out161_UNCONNECTED(0),
+ probe_out162(0) => NLW_inst_probe_out162_UNCONNECTED(0),
+ probe_out163(0) => NLW_inst_probe_out163_UNCONNECTED(0),
+ probe_out164(0) => NLW_inst_probe_out164_UNCONNECTED(0),
+ probe_out165(0) => NLW_inst_probe_out165_UNCONNECTED(0),
+ probe_out166(0) => NLW_inst_probe_out166_UNCONNECTED(0),
+ probe_out167(0) => NLW_inst_probe_out167_UNCONNECTED(0),
+ probe_out168(0) => NLW_inst_probe_out168_UNCONNECTED(0),
+ probe_out169(0) => NLW_inst_probe_out169_UNCONNECTED(0),
+ probe_out17(0) => NLW_inst_probe_out17_UNCONNECTED(0),
+ probe_out170(0) => NLW_inst_probe_out170_UNCONNECTED(0),
+ probe_out171(0) => NLW_inst_probe_out171_UNCONNECTED(0),
+ probe_out172(0) => NLW_inst_probe_out172_UNCONNECTED(0),
+ probe_out173(0) => NLW_inst_probe_out173_UNCONNECTED(0),
+ probe_out174(0) => NLW_inst_probe_out174_UNCONNECTED(0),
+ probe_out175(0) => NLW_inst_probe_out175_UNCONNECTED(0),
+ probe_out176(0) => NLW_inst_probe_out176_UNCONNECTED(0),
+ probe_out177(0) => NLW_inst_probe_out177_UNCONNECTED(0),
+ probe_out178(0) => NLW_inst_probe_out178_UNCONNECTED(0),
+ probe_out179(0) => NLW_inst_probe_out179_UNCONNECTED(0),
+ probe_out18(0) => NLW_inst_probe_out18_UNCONNECTED(0),
+ probe_out180(0) => NLW_inst_probe_out180_UNCONNECTED(0),
+ probe_out181(0) => NLW_inst_probe_out181_UNCONNECTED(0),
+ probe_out182(0) => NLW_inst_probe_out182_UNCONNECTED(0),
+ probe_out183(0) => NLW_inst_probe_out183_UNCONNECTED(0),
+ probe_out184(0) => NLW_inst_probe_out184_UNCONNECTED(0),
+ probe_out185(0) => NLW_inst_probe_out185_UNCONNECTED(0),
+ probe_out186(0) => NLW_inst_probe_out186_UNCONNECTED(0),
+ probe_out187(0) => NLW_inst_probe_out187_UNCONNECTED(0),
+ probe_out188(0) => NLW_inst_probe_out188_UNCONNECTED(0),
+ probe_out189(0) => NLW_inst_probe_out189_UNCONNECTED(0),
+ probe_out19(0) => NLW_inst_probe_out19_UNCONNECTED(0),
+ probe_out190(0) => NLW_inst_probe_out190_UNCONNECTED(0),
+ probe_out191(0) => NLW_inst_probe_out191_UNCONNECTED(0),
+ probe_out192(0) => NLW_inst_probe_out192_UNCONNECTED(0),
+ probe_out193(0) => NLW_inst_probe_out193_UNCONNECTED(0),
+ probe_out194(0) => NLW_inst_probe_out194_UNCONNECTED(0),
+ probe_out195(0) => NLW_inst_probe_out195_UNCONNECTED(0),
+ probe_out196(0) => NLW_inst_probe_out196_UNCONNECTED(0),
+ probe_out197(0) => NLW_inst_probe_out197_UNCONNECTED(0),
+ probe_out198(0) => NLW_inst_probe_out198_UNCONNECTED(0),
+ probe_out199(0) => NLW_inst_probe_out199_UNCONNECTED(0),
+ probe_out2(0) => probe_out2(0),
+ probe_out20(0) => NLW_inst_probe_out20_UNCONNECTED(0),
+ probe_out200(0) => NLW_inst_probe_out200_UNCONNECTED(0),
+ probe_out201(0) => NLW_inst_probe_out201_UNCONNECTED(0),
+ probe_out202(0) => NLW_inst_probe_out202_UNCONNECTED(0),
+ probe_out203(0) => NLW_inst_probe_out203_UNCONNECTED(0),
+ probe_out204(0) => NLW_inst_probe_out204_UNCONNECTED(0),
+ probe_out205(0) => NLW_inst_probe_out205_UNCONNECTED(0),
+ probe_out206(0) => NLW_inst_probe_out206_UNCONNECTED(0),
+ probe_out207(0) => NLW_inst_probe_out207_UNCONNECTED(0),
+ probe_out208(0) => NLW_inst_probe_out208_UNCONNECTED(0),
+ probe_out209(0) => NLW_inst_probe_out209_UNCONNECTED(0),
+ probe_out21(0) => NLW_inst_probe_out21_UNCONNECTED(0),
+ probe_out210(0) => NLW_inst_probe_out210_UNCONNECTED(0),
+ probe_out211(0) => NLW_inst_probe_out211_UNCONNECTED(0),
+ probe_out212(0) => NLW_inst_probe_out212_UNCONNECTED(0),
+ probe_out213(0) => NLW_inst_probe_out213_UNCONNECTED(0),
+ probe_out214(0) => NLW_inst_probe_out214_UNCONNECTED(0),
+ probe_out215(0) => NLW_inst_probe_out215_UNCONNECTED(0),
+ probe_out216(0) => NLW_inst_probe_out216_UNCONNECTED(0),
+ probe_out217(0) => NLW_inst_probe_out217_UNCONNECTED(0),
+ probe_out218(0) => NLW_inst_probe_out218_UNCONNECTED(0),
+ probe_out219(0) => NLW_inst_probe_out219_UNCONNECTED(0),
+ probe_out22(0) => NLW_inst_probe_out22_UNCONNECTED(0),
+ probe_out220(0) => NLW_inst_probe_out220_UNCONNECTED(0),
+ probe_out221(0) => NLW_inst_probe_out221_UNCONNECTED(0),
+ probe_out222(0) => NLW_inst_probe_out222_UNCONNECTED(0),
+ probe_out223(0) => NLW_inst_probe_out223_UNCONNECTED(0),
+ probe_out224(0) => NLW_inst_probe_out224_UNCONNECTED(0),
+ probe_out225(0) => NLW_inst_probe_out225_UNCONNECTED(0),
+ probe_out226(0) => NLW_inst_probe_out226_UNCONNECTED(0),
+ probe_out227(0) => NLW_inst_probe_out227_UNCONNECTED(0),
+ probe_out228(0) => NLW_inst_probe_out228_UNCONNECTED(0),
+ probe_out229(0) => NLW_inst_probe_out229_UNCONNECTED(0),
+ probe_out23(0) => NLW_inst_probe_out23_UNCONNECTED(0),
+ probe_out230(0) => NLW_inst_probe_out230_UNCONNECTED(0),
+ probe_out231(0) => NLW_inst_probe_out231_UNCONNECTED(0),
+ probe_out232(0) => NLW_inst_probe_out232_UNCONNECTED(0),
+ probe_out233(0) => NLW_inst_probe_out233_UNCONNECTED(0),
+ probe_out234(0) => NLW_inst_probe_out234_UNCONNECTED(0),
+ probe_out235(0) => NLW_inst_probe_out235_UNCONNECTED(0),
+ probe_out236(0) => NLW_inst_probe_out236_UNCONNECTED(0),
+ probe_out237(0) => NLW_inst_probe_out237_UNCONNECTED(0),
+ probe_out238(0) => NLW_inst_probe_out238_UNCONNECTED(0),
+ probe_out239(0) => NLW_inst_probe_out239_UNCONNECTED(0),
+ probe_out24(0) => NLW_inst_probe_out24_UNCONNECTED(0),
+ probe_out240(0) => NLW_inst_probe_out240_UNCONNECTED(0),
+ probe_out241(0) => NLW_inst_probe_out241_UNCONNECTED(0),
+ probe_out242(0) => NLW_inst_probe_out242_UNCONNECTED(0),
+ probe_out243(0) => NLW_inst_probe_out243_UNCONNECTED(0),
+ probe_out244(0) => NLW_inst_probe_out244_UNCONNECTED(0),
+ probe_out245(0) => NLW_inst_probe_out245_UNCONNECTED(0),
+ probe_out246(0) => NLW_inst_probe_out246_UNCONNECTED(0),
+ probe_out247(0) => NLW_inst_probe_out247_UNCONNECTED(0),
+ probe_out248(0) => NLW_inst_probe_out248_UNCONNECTED(0),
+ probe_out249(0) => NLW_inst_probe_out249_UNCONNECTED(0),
+ probe_out25(0) => NLW_inst_probe_out25_UNCONNECTED(0),
+ probe_out250(0) => NLW_inst_probe_out250_UNCONNECTED(0),
+ probe_out251(0) => NLW_inst_probe_out251_UNCONNECTED(0),
+ probe_out252(0) => NLW_inst_probe_out252_UNCONNECTED(0),
+ probe_out253(0) => NLW_inst_probe_out253_UNCONNECTED(0),
+ probe_out254(0) => NLW_inst_probe_out254_UNCONNECTED(0),
+ probe_out255(0) => NLW_inst_probe_out255_UNCONNECTED(0),
+ probe_out26(0) => NLW_inst_probe_out26_UNCONNECTED(0),
+ probe_out27(0) => NLW_inst_probe_out27_UNCONNECTED(0),
+ probe_out28(0) => NLW_inst_probe_out28_UNCONNECTED(0),
+ probe_out29(0) => NLW_inst_probe_out29_UNCONNECTED(0),
+ probe_out3(0) => NLW_inst_probe_out3_UNCONNECTED(0),
+ probe_out30(0) => NLW_inst_probe_out30_UNCONNECTED(0),
+ probe_out31(0) => NLW_inst_probe_out31_UNCONNECTED(0),
+ probe_out32(0) => NLW_inst_probe_out32_UNCONNECTED(0),
+ probe_out33(0) => NLW_inst_probe_out33_UNCONNECTED(0),
+ probe_out34(0) => NLW_inst_probe_out34_UNCONNECTED(0),
+ probe_out35(0) => NLW_inst_probe_out35_UNCONNECTED(0),
+ probe_out36(0) => NLW_inst_probe_out36_UNCONNECTED(0),
+ probe_out37(0) => NLW_inst_probe_out37_UNCONNECTED(0),
+ probe_out38(0) => NLW_inst_probe_out38_UNCONNECTED(0),
+ probe_out39(0) => NLW_inst_probe_out39_UNCONNECTED(0),
+ probe_out4(0) => NLW_inst_probe_out4_UNCONNECTED(0),
+ probe_out40(0) => NLW_inst_probe_out40_UNCONNECTED(0),
+ probe_out41(0) => NLW_inst_probe_out41_UNCONNECTED(0),
+ probe_out42(0) => NLW_inst_probe_out42_UNCONNECTED(0),
+ probe_out43(0) => NLW_inst_probe_out43_UNCONNECTED(0),
+ probe_out44(0) => NLW_inst_probe_out44_UNCONNECTED(0),
+ probe_out45(0) => NLW_inst_probe_out45_UNCONNECTED(0),
+ probe_out46(0) => NLW_inst_probe_out46_UNCONNECTED(0),
+ probe_out47(0) => NLW_inst_probe_out47_UNCONNECTED(0),
+ probe_out48(0) => NLW_inst_probe_out48_UNCONNECTED(0),
+ probe_out49(0) => NLW_inst_probe_out49_UNCONNECTED(0),
+ probe_out5(0) => NLW_inst_probe_out5_UNCONNECTED(0),
+ probe_out50(0) => NLW_inst_probe_out50_UNCONNECTED(0),
+ probe_out51(0) => NLW_inst_probe_out51_UNCONNECTED(0),
+ probe_out52(0) => NLW_inst_probe_out52_UNCONNECTED(0),
+ probe_out53(0) => NLW_inst_probe_out53_UNCONNECTED(0),
+ probe_out54(0) => NLW_inst_probe_out54_UNCONNECTED(0),
+ probe_out55(0) => NLW_inst_probe_out55_UNCONNECTED(0),
+ probe_out56(0) => NLW_inst_probe_out56_UNCONNECTED(0),
+ probe_out57(0) => NLW_inst_probe_out57_UNCONNECTED(0),
+ probe_out58(0) => NLW_inst_probe_out58_UNCONNECTED(0),
+ probe_out59(0) => NLW_inst_probe_out59_UNCONNECTED(0),
+ probe_out6(0) => NLW_inst_probe_out6_UNCONNECTED(0),
+ probe_out60(0) => NLW_inst_probe_out60_UNCONNECTED(0),
+ probe_out61(0) => NLW_inst_probe_out61_UNCONNECTED(0),
+ probe_out62(0) => NLW_inst_probe_out62_UNCONNECTED(0),
+ probe_out63(0) => NLW_inst_probe_out63_UNCONNECTED(0),
+ probe_out64(0) => NLW_inst_probe_out64_UNCONNECTED(0),
+ probe_out65(0) => NLW_inst_probe_out65_UNCONNECTED(0),
+ probe_out66(0) => NLW_inst_probe_out66_UNCONNECTED(0),
+ probe_out67(0) => NLW_inst_probe_out67_UNCONNECTED(0),
+ probe_out68(0) => NLW_inst_probe_out68_UNCONNECTED(0),
+ probe_out69(0) => NLW_inst_probe_out69_UNCONNECTED(0),
+ probe_out7(0) => NLW_inst_probe_out7_UNCONNECTED(0),
+ probe_out70(0) => NLW_inst_probe_out70_UNCONNECTED(0),
+ probe_out71(0) => NLW_inst_probe_out71_UNCONNECTED(0),
+ probe_out72(0) => NLW_inst_probe_out72_UNCONNECTED(0),
+ probe_out73(0) => NLW_inst_probe_out73_UNCONNECTED(0),
+ probe_out74(0) => NLW_inst_probe_out74_UNCONNECTED(0),
+ probe_out75(0) => NLW_inst_probe_out75_UNCONNECTED(0),
+ probe_out76(0) => NLW_inst_probe_out76_UNCONNECTED(0),
+ probe_out77(0) => NLW_inst_probe_out77_UNCONNECTED(0),
+ probe_out78(0) => NLW_inst_probe_out78_UNCONNECTED(0),
+ probe_out79(0) => NLW_inst_probe_out79_UNCONNECTED(0),
+ probe_out8(0) => NLW_inst_probe_out8_UNCONNECTED(0),
+ probe_out80(0) => NLW_inst_probe_out80_UNCONNECTED(0),
+ probe_out81(0) => NLW_inst_probe_out81_UNCONNECTED(0),
+ probe_out82(0) => NLW_inst_probe_out82_UNCONNECTED(0),
+ probe_out83(0) => NLW_inst_probe_out83_UNCONNECTED(0),
+ probe_out84(0) => NLW_inst_probe_out84_UNCONNECTED(0),
+ probe_out85(0) => NLW_inst_probe_out85_UNCONNECTED(0),
+ probe_out86(0) => NLW_inst_probe_out86_UNCONNECTED(0),
+ probe_out87(0) => NLW_inst_probe_out87_UNCONNECTED(0),
+ probe_out88(0) => NLW_inst_probe_out88_UNCONNECTED(0),
+ probe_out89(0) => NLW_inst_probe_out89_UNCONNECTED(0),
+ probe_out9(0) => NLW_inst_probe_out9_UNCONNECTED(0),
+ probe_out90(0) => NLW_inst_probe_out90_UNCONNECTED(0),
+ probe_out91(0) => NLW_inst_probe_out91_UNCONNECTED(0),
+ probe_out92(0) => NLW_inst_probe_out92_UNCONNECTED(0),
+ probe_out93(0) => NLW_inst_probe_out93_UNCONNECTED(0),
+ probe_out94(0) => NLW_inst_probe_out94_UNCONNECTED(0),
+ probe_out95(0) => NLW_inst_probe_out95_UNCONNECTED(0),
+ probe_out96(0) => NLW_inst_probe_out96_UNCONNECTED(0),
+ probe_out97(0) => NLW_inst_probe_out97_UNCONNECTED(0),
+ probe_out98(0) => NLW_inst_probe_out98_UNCONNECTED(0),
+ probe_out99(0) => NLW_inst_probe_out99_UNCONNECTED(0),
+ sl_iport0(36 downto 0) => B"0000000000000000000000000000000000000",
+ sl_oport0(16 downto 0) => NLW_inst_sl_oport0_UNCONNECTED(16 downto 0)
+ );
+end STRUCTURE;
diff --git a/sources/templates/docs/html/registers-5.0.html b/sources/templates/docs/html/registers-5.0.html
index e813e1243ed44cf03a34c6e1588fb5e5888555dc..3d0548d1cdf667f04fc6d7751d9c70470c20c1b3 100644
--- a/sources/templates/docs/html/registers-5.0.html
+++ b/sources/templates/docs/html/registers-5.0.html
@@ -8,11 +8,11 @@
DO NOT EDIT THIS FILE
This file was generated from template '../../../WupperCodeGen/input/registers.html.template'
- and register map ../../../sources/templates/yaml/registers-5.0.yaml, version 5.0
+ and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.0.yaml, version 5.0
by the script 'wuppercodegen', version: 0.9.1,
using the following commandline:
- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.0.yaml ../../../WupperCodeGen/input/registers.html.template ../docs/html/registers-5.0.html
+ ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.0.yaml ../../../WupperCodeGen/input/registers.html.template ../docs/html/registers-5.0.html
Please do NOT edit this file, but edit the source file at '../../../WupperCodeGen/input/registers.html.template'
diff --git a/sources/templates/docs/html/registers-5.1.html b/sources/templates/docs/html/registers-5.1.html
index d85b6a52f981fb15cd9c2648e96816995f41876c..e239ab62dd9c907a9b1676afebb8b686b49794de 100644
--- a/sources/templates/docs/html/registers-5.1.html
+++ b/sources/templates/docs/html/registers-5.1.html
@@ -8,11 +8,11 @@
DO NOT EDIT THIS FILE
This file was generated from template '../../../WupperCodeGen/input/registers.html.template'
- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+ and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
by the script 'wuppercodegen', version: 0.9.1,
using the following commandline:
- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../WupperCodeGen/input/registers.html.template ../docs/html/registers-5.1.html
+ ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../WupperCodeGen/input/registers.html.template ../docs/html/registers-5.1.html
Please do NOT edit this file, but edit the source file at '../../../WupperCodeGen/input/registers.html.template'
diff --git a/sources/templates/generated/dma_control.vhd b/sources/templates/generated/dma_control.vhd
index 573ec2e66db6f34c0f10fd7f63658163146a49f6..58b56bed5bcc1be12a0771d1042621955a5ad603 100644
--- a/sources/templates/generated/dma_control.vhd
+++ b/sources/templates/generated/dma_control.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control.vhd
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control.vhd
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_0.vhd b/sources/templates/generated/dma_control_0.vhd
index ce781df0262adb8d3c1ced4a3214887ba0ba9873..75b959d2f7d5b1a2b15b861bc18c7522e551b332 100644
--- a/sources/templates/generated/dma_control_0.vhd
+++ b/sources/templates/generated/dma_control_0.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_0.vhd --fw_mode 0
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_0.vhd --fw_mode 0
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_1.vhd b/sources/templates/generated/dma_control_1.vhd
index dce2450c3590c81b7b8bf90ba582361febecf1d5..82c2bd0b1bb49f628232925a1e9793d675230aee 100644
--- a/sources/templates/generated/dma_control_1.vhd
+++ b/sources/templates/generated/dma_control_1.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_1.vhd --fw_mode 1
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_1.vhd --fw_mode 1
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_10.vhd b/sources/templates/generated/dma_control_10.vhd
index ea4f2dacc545f1fc45a63de1b00f2f4ce1a3fb43..a0770d1924de900cf7dbfcfd82bc16c57071218e 100644
--- a/sources/templates/generated/dma_control_10.vhd
+++ b/sources/templates/generated/dma_control_10.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_10.vhd --fw_mode 10
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_10.vhd --fw_mode 10
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_11.vhd b/sources/templates/generated/dma_control_11.vhd
index 5ca8aa9c75e264f89563512cebe5ee57c6056637..ac45033bca8f92f99897d789dd9c1185aa04d0b5 100644
--- a/sources/templates/generated/dma_control_11.vhd
+++ b/sources/templates/generated/dma_control_11.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_11.vhd --fw_mode 11
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_11.vhd --fw_mode 11
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_12.vhd b/sources/templates/generated/dma_control_12.vhd
index f160a4b545f01ff2dd0247440661115140e96125..0b299cfd89a9c45e3ce515f8d4eddf0e674b8514 100644
--- a/sources/templates/generated/dma_control_12.vhd
+++ b/sources/templates/generated/dma_control_12.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_12.vhd --fw_mode 12
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_12.vhd --fw_mode 12
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_13.vhd b/sources/templates/generated/dma_control_13.vhd
index 5cf502cf1f73ad515286177cdab8feecd117b728..5362267ef19da6639b22e3c4e4de1fea763fb8d2 100644
--- a/sources/templates/generated/dma_control_13.vhd
+++ b/sources/templates/generated/dma_control_13.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_13.vhd --fw_mode 13
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_13.vhd --fw_mode 13
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_14.vhd b/sources/templates/generated/dma_control_14.vhd
index 28cb1eb507c0eaf0c32dbed9cd30bd683d8d819b..c29c572903c7c319838b56c18d00aede62a7ce67 100644
--- a/sources/templates/generated/dma_control_14.vhd
+++ b/sources/templates/generated/dma_control_14.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_14.vhd --fw_mode 14
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_14.vhd --fw_mode 14
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_15.vhd b/sources/templates/generated/dma_control_15.vhd
index 8ad83bd91aba9841e6b96173e42f48caf940c90c..bfbab1f52f8354e6df5e2341a58abd73110d7d07 100644
--- a/sources/templates/generated/dma_control_15.vhd
+++ b/sources/templates/generated/dma_control_15.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_15.vhd --fw_mode 15
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_15.vhd --fw_mode 15
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_2.vhd b/sources/templates/generated/dma_control_2.vhd
index 380c3edcd6673a57cf1154453bb145bfb28f7c41..40b31f6de4abe6cb10187bb5418288bb358dfa0f 100644
--- a/sources/templates/generated/dma_control_2.vhd
+++ b/sources/templates/generated/dma_control_2.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_2.vhd --fw_mode 2
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_2.vhd --fw_mode 2
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_3.vhd b/sources/templates/generated/dma_control_3.vhd
index e57cfa6c751562bf8a0eb2868f631dade5233847..8f56e94cc290d23e0e1769af170559ab228ab788 100644
--- a/sources/templates/generated/dma_control_3.vhd
+++ b/sources/templates/generated/dma_control_3.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_3.vhd --fw_mode 3
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_3.vhd --fw_mode 3
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_4.vhd b/sources/templates/generated/dma_control_4.vhd
index 60988028be110acf7ee3656f394664a0e166932d..0f9b9644c66375447c6ad6fb03935ddff22c715b 100644
--- a/sources/templates/generated/dma_control_4.vhd
+++ b/sources/templates/generated/dma_control_4.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_4.vhd --fw_mode 4
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_4.vhd --fw_mode 4
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_5.vhd b/sources/templates/generated/dma_control_5.vhd
index dbeb5be2a71c1c6a876d339b5b8b4b85d7d35723..d9c90e140ff451fb6aba243900d630beba3c856f 100644
--- a/sources/templates/generated/dma_control_5.vhd
+++ b/sources/templates/generated/dma_control_5.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_5.vhd --fw_mode 5
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_5.vhd --fw_mode 5
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_6.vhd b/sources/templates/generated/dma_control_6.vhd
index 90119c5e9d93b332638a6a9cb81743bcc23a3cc6..34fe4f9bae4bebcf2b211504f5bd517116db7384 100644
--- a/sources/templates/generated/dma_control_6.vhd
+++ b/sources/templates/generated/dma_control_6.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_6.vhd --fw_mode 6
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_6.vhd --fw_mode 6
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_7.vhd b/sources/templates/generated/dma_control_7.vhd
index 34d02bf64a7eccf854c86580e6030fe40e10607d..87de660b19720a7f817627b05d1653eb7ab5563c 100644
--- a/sources/templates/generated/dma_control_7.vhd
+++ b/sources/templates/generated/dma_control_7.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_7.vhd --fw_mode 7
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_7.vhd --fw_mode 7
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_8.vhd b/sources/templates/generated/dma_control_8.vhd
index 12d1e4fcc2faf64ca6488bc7fe8b04226ddb66f7..3510d0681db56ac7f42784bcc032e0f9802e1a66 100644
--- a/sources/templates/generated/dma_control_8.vhd
+++ b/sources/templates/generated/dma_control_8.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_8.vhd --fw_mode 8
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_8.vhd --fw_mode 8
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/dma_control_9.vhd b/sources/templates/generated/dma_control_9.vhd
index 09af7d114ec1a6415dbc8c7ea199d8cb3731aa1c..34f1d26f08b73211ca2b16fe5c14429434379b6d 100644
--- a/sources/templates/generated/dma_control_9.vhd
+++ b/sources/templates/generated/dma_control_9.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/dma_control.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_9.vhd --fw_mode 9
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/dma_control.vhd.template ../../../sources/templates/generated/dma_control_9.vhd --fw_mode 9
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/dma_control.vhd.template'
--
diff --git a/sources/templates/generated/pcie_package.vhd b/sources/templates/generated/pcie_package.vhd
index 9f7551b5b2b5c2762c32435669d15b26d2972ed4..902b86aa62fa4528f96c73a5b7b5078cca2a8bef 100644
--- a/sources/templates/generated/pcie_package.vhd
+++ b/sources/templates/generated/pcie_package.vhd
@@ -39,11 +39,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/pcie_package.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/pcie_package.vhd.template ../../../sources/templates/generated/pcie_package.vhd
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/pcie_package.vhd.template ../../../sources/templates/generated/pcie_package.vhd
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/pcie_package.vhd.template'
--
diff --git a/sources/templates/generated/register_map_sync.vhd b/sources/templates/generated/register_map_sync.vhd
index 1ed57b2d6ee366372aea572dca55df7a2f992f95..f7d123e6ab4274f488b7c65c1773d8c3f47a87f2 100644
--- a/sources/templates/generated/register_map_sync.vhd
+++ b/sources/templates/generated/register_map_sync.vhd
@@ -23,11 +23,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/register_map_sync.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/register_map_sync.vhd.template ../../../sources/templates/generated/register_map_sync.vhd
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/register_map_sync.vhd.template ../../../sources/templates/generated/register_map_sync.vhd
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/register_map_sync.vhd.template'
--
diff --git a/sources/templates/generated/wupper.vhd b/sources/templates/generated/wupper.vhd
index baa25c8f0342dfc8d7c975f57895af0f0fec503d..83d74b61110eacee95b1fc68353f0f8ddcd67449 100644
--- a/sources/templates/generated/wupper.vhd
+++ b/sources/templates/generated/wupper.vhd
@@ -30,11 +30,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../../sources/templates/jinja/wupper.vhd.template'
--- and register map ../../../sources/templates/yaml/registers-5.1.yaml, version 5.1
+-- and register map ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml, version 5.1
-- by the script 'wuppercodegen', version: 0.9.1,
-- using the following commandline:
--
--- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/registers-5.1.yaml ../../../sources/templates/jinja/wupper.vhd.template ../../../sources/templates/generated/wupper.vhd
+-- ../../../WupperCodeGen/wuppercodegen/cli.py ../../../sources/templates/yaml/regmap/yaml/registers-5.1.yaml ../../../sources/templates/jinja/wupper.vhd.template ../../../sources/templates/generated/wupper.vhd
--
-- Please do NOT edit this file, but edit the source file at '../../../sources/templates/jinja/wupper.vhd.template'
--
diff --git a/sources/templates/scripts/build-diff.sh b/sources/templates/scripts/build-diff.sh
index aa051e6ba84ac878291fcb91dfa6c6201e34de3d..3f9f4399c94803380b3954f21a3ff29993777ea0 100755
--- a/sources/templates/scripts/build-diff.sh
+++ b/sources/templates/scripts/build-diff.sh
@@ -39,8 +39,8 @@ echo $scriptdir
wuppercodegen_dir=$firmware_dir/WupperCodeGen
wuppercodegen=$wuppercodegen_dir/wuppercodegen/cli.py
-prev_registers=$template_dir/registers-${prev_version}.yaml
-current_registers=$template_dir/registers-${current_version}.yaml
+prev_registers=$template_dir/yaml/regmap/yaml/registers-${prev_version}.yaml
+current_registers=$template_dir/yaml/regmap/yaml/registers-${current_version}.yaml
#next_registers=$template_dir/registers-${next_version}.yaml
$wuppercodegen --version
echo "Previous version: $prev_version"
diff --git a/sources/templates/scripts/build-doc.sh b/sources/templates/scripts/build-doc.sh
index dd2c53b7d8a0f60f17e507576053b5ba264d58e8..e29f1539e2947a24fa6c302917b47955ca442abc 100755
--- a/sources/templates/scripts/build-doc.sh
+++ b/sources/templates/scripts/build-doc.sh
@@ -36,8 +36,8 @@ generated_dir=$template_dir/generated
wuppercodegen_dir=$firmware_dir/WupperCodeGen
wuppercodegen=$wuppercodegen_dir/wuppercodegen/cli.py
-prev_registers=$template_dir/yaml/registers-${prev_version}.yaml
-current_registers=$template_dir/yaml/registers-${current_version}.yaml
+prev_registers=$template_dir/yaml/regmap/yaml/registers-${prev_version}.yaml
+current_registers=$template_dir/yaml/regmap/yaml/registers-${current_version}.yaml
$wuppercodegen --version
$wuppercodegen $current_registers $template_dir/jinja/registermap.tex.template $template_dir/docs/registermap-${current_version}.tex
diff --git a/sources/templates/scripts/build-html.sh b/sources/templates/scripts/build-html.sh
index c9420dfacf71f3fdc34e4f61d6b454564c9fff75..9087ad3ba6b7257332dbebbd6be318c94a7e01ec 100755
--- a/sources/templates/scripts/build-html.sh
+++ b/sources/templates/scripts/build-html.sh
@@ -35,7 +35,7 @@ echo $scriptdir
wuppercodegen_dir=$firmware_dir/WupperCodeGen
wuppercodegen=$wuppercodegen_dir/wuppercodegen/cli.py
-current_registers=$template_dir/registers-$1.yaml
+current_registers=$template_dir/yaml/regmap/yaml/registers-$1.yaml
$wuppercodegen --version
echo "Generating html documentation for current version..."
$wuppercodegen $current_registers $wuppercodegen_dir/input/registers.html.template registers-$1.html
diff --git a/sources/templates/scripts/build.sh b/sources/templates/scripts/build.sh
index db9af2e571be9eed1702923f4b42f74d7113d709..7ea2122ab913700a415f832e2af16838beba9093 100755
--- a/sources/templates/scripts/build.sh
+++ b/sources/templates/scripts/build.sh
@@ -47,8 +47,8 @@ echo $scriptdir
wuppercodegen_dir=$firmware_dir/WupperCodeGen
wuppercodegen=$wuppercodegen_dir/wuppercodegen/cli.py
-prev_registers=$template_dir/yaml/registers-${prev_version}.yaml
-current_registers=$template_dir/yaml/registers-${current_version}.yaml
+prev_registers=$template_dir/yaml/regmap/yaml/registers-${prev_version}.yaml
+current_registers=$template_dir/yaml/regmap/yaml/registers-${current_version}.yaml
#next_registers=$template_dir/registers-${next_version}.yaml
$wuppercodegen --version
echo "Previous version: $prev_version"
diff --git a/sources/templates/yaml/registers-2.0.yaml b/sources/templates/yaml/registers-2.0.yaml
deleted file mode 100644
index ec7521d1ad7ebdd37ec6e0ef58063c52f366faac..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-2.0.yaml
+++ /dev/null
@@ -1,864 +0,0 @@
-Registers:
- version: '2.0'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
-
-Bar0:
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: RD_POINTER
- desc: PC Read Pointer
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: READ_WRITE
- desc: Read/<o>Write</o>
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: CURRENT_ADDRESS
- desc: Current Address
-
-Bar1:
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 8
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControls
- offset: 0x1000
- - ref: CentralRouterMonitors
- offset: 0x3000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x4000
- - ref: GBTWrapperControls
- offset: 0x5000
- - ref: GBTWrapperMonitors
- offset: 0x6000
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x7000
-
-GenericBoardInformation:
- entries:
- - name: BOARD_ID{bitfield}
- bitfield:
- - name: SVN
- range: 79..64
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
- - name: TIMESTAMP
- range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: STATUS_LEDS
- offset: 0x0010
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS{bitfield}
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- value: std_logic_vector(to_unsigned(GBT_NUM,8))
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709: VC709
- - 710: HTG710
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- value: std_logic_vector(to_unsigned(GBT_MAPPING,8))
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
-CentralRouterControls:
- offset: 0x0100
- desc: See Central Router Doc
- entries:
- - ref: GBT_CONTROL
- - name: CR_TH_UPDATE_CTRL
- type: T
- value: 1
- bitfield:
- - range: any
- - name: CR_FH_UPDATE_CTRL
- type: T
- value: 1
- bitfield:
- - range: any
-
-GBT_CONTROL:
- number: 24
- type: W
- bitfield:
- - range: 63..0
- entries:
- - ref: TH
- - ref: FH
-
-TH:
- number: 7
- format_name: GBT{index:02}
- entries:
- - name: TH
- desc: See Central Router Doc, indices [5,6] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
-
-FH:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FH
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
-
-CentralRouterMonitors:
- desc: See Central Router Doc
- entries:
- - ref: GBT_MON
-
-GBT_MON:
- number: 24
- bitfield:
- - range: 63..0
- entries:
- - name: TH
- format_name: CR_{name}_GBT{index:02}_MON
- - name: FH
- format_name: CR_{name}_GBT{index:02}_MON
-
-GBTEmulatorControlsAndMonitors:
- entries:
- - name: GBT_EMU_ENA{bitfield}
- type: W
- bitfield:
- - range: 1
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
- - range: 0
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
-
- - name: GBT_EMU_CONFIG{bitfield}
- type: W
- bitfield:
- - range: 70..64
- name: WE_ARRAY
- desc: write enable array, every bit is one emulator RAM block
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
-GBTWrapperControls:
- type: W
- entries:
- - name: GBT_LOGIC_RESET
- offset: 0x0400
- bitfield:
- - range: 63..0
- desc: Not internally connected (?)
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL{bitfield}
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE{bitfield}
- offset: 0x0480
- bitfield:
- - range: 59..48
- name: BF1
- desc: RxSlide select [23:12]
- - range: 43..32
- name: BF2
- desc: RxSlide select [11:0]
- - range: 27..16
- name: BF3
- desc: RxSlide manual [23:12
- - range: 11..0
- name: BF4
- desc: RxSlide manual [11:0]
-
- - name: GBT_TXUSRRDY{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- default: 0xFFF
- desc: TxUsrRdy [23:12]
- - range: 11..0
- name: BF2
- default: 0xFFF
- desc: TxUsrRdy [11:0]
-
- - name: GBT_RXUSRRDY{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- default: 0xFFF
- desc: RxUsrRdy [23:12]
- - range: 11..0
- name: BF2
- default: 0xFFF
- desc: RxUsrRdy [11:0]
-
- - name: GBT_GTTX_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: BF1
- desc: SOFT_RESET [5:3]
- - range: 27..16
- name: BF2
- desc: GTTX_RESET [23:12]
- - range: 14..12
- name: BF3
- desc: SOFT_RESET [2:0]
- - range: 11..0
- name: BF4
- desc: GTTX_RESET [11:0]
-
- - name: GBT_GTRX_RESET{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: GTRX_RESET [23:0]
- - range: 11..0
- name: BF2
- desc: GTRX_RESET [11:0]
-
- - name: GBT_PLL_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: BF1
- desc: QPLL_RESET [5:3]
- - range: 27..16
- name: BF2
- desc: CPLL_RESET [23:12]
- - range: 14..12
- name: BF3
- desc: QPLL_RESET [2:0]
- - range: 11..0
- name: BF4
- desc: CPLL_RESET [11:0]
-
- - name: GBT_SOFT_TX_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: BF1
- desc: SOFT_TX_RESET_ALL [5:3]
- - range: 27..16
- name: BF2
- desc: SOFT_TX_RESET_GT [23:12]
- - range: 14..12
- name: BF3
- desc: SOFT_TX_RESET_ALL [2:0]
- - range: 11..0
- name: BF4
- desc: SOFT_TX_RESET_GT [11:0]
-
- - name: GBT_SOFT_RX_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: BF1
- desc: SOFT_RX_RESET_ALL [5:3]
- - range: 27..16
- name: BF2
- desc: SOFT_RX_RESET_GT [23:12]
- - range: 14..12
- name: BF3
- desc: SOFT_RX_RESET_ALL [2:0]
- - range: 11..0
- name: BF4
- desc: SOFT_RX_RESET_GT [11:0]
-
- - name: GBT_ODD_EVEN{bitfield}
- offset: 0x0500
- bitfield:
- - range: 27..16
- name: BF1
- desc: OddEven [23:12]
- - range: 11..0
- name: BF2
- desc: OddEven [11:0]
-
- - name: GBT_TOPBOT{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: TopBot [23:12]
- - range: 11..0
- name: BF2
- desc: TopBot [11:0]
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: TX_OPT
-
- - name: GBT_RX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: RX_OPT
-
- - name: GBT_DATA_TXFORMAT{bitfield}
- bitfield:
- - range: 55..32
- name: BF1
- desc: DATA_TXFORMAT [47:24]
- - range: 23..0
- name: BF2
- desc: DATA_TXFORMAT [23:0]
-
- - name: GBT_DATA_RXFORMAT{bitfield}
- bitfield:
- - range: 55..32
- name: BF1
- desc: DATA_RXFORMAT [47:24]
- - range: 23..0
- name: BF2
- desc: DATA_RXFORMAT [23:0]
-
- - name: GBT_TX_RESET{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: TX Logic reset [23:12]
- - range: 11..0
- name: BF2
- desc: TX Logic reset [11:0]
-
- - name: GBT_RX_RESET{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX Logic reset [23:12]
- - range: 11..0
- name: BF2
- desc: RX Logic reset [11:0]
-
- - name: GBT_TX_TC_METHOD{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: TX time domain crossing method [23:12]
- - range: 11..0
- name: BF2
- desc: TX time domain crossing method [11:0]
-
- - name: GBT_OUTMUX_SEL{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: Descrambler output MUX selection [23:12]
- - range: 11..0
- name: BF2
- desc: Descrambler output MUX selection [11:0]
-
- - name: GBT_DNLNK_FO_SEL
- offset: 0x0600
- bitfield:
- - range: 31..0
- default: 0xFFFFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_UPLNK_FO_SEL
- bitfield:
- - range: 31..0
- default: 0xFFFFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-GBTWrapperMonitors:
- entries:
- - name: GBT_VERSION{bitfield}
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATA
- desc: Data
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE{bitfield}
- offset: 0x0680
- bitfield:
- - range: 27..16
- name: BF1
- desc: TX Reset done [23:12]
- - range: 11..0
- name: BF2
- desc: TX Reset done [11:0]
-
- - name: GBT_RXRESET_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX Reset done [23:12]
- - range: 11..0
- name: BF2
- desc: RX Reset done [11:0]
-
- - name: GBT_TXFSMRESET_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: TX FSM Reset done [23:12]
- - range: 11..0
- name: BF2
- desc: TX FSM Reset done [11:0]
-
- - name: GBT_RXFSMRESET_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX FSM Reset done [23:12]
- - range: 11..0
- name: BF2
- desc: RX FSM Reset done [11:0]
-
- - name: GBT_CPLL_FBCLK_LOST{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: CPLL FBCLK LOST [23:12]
- - range: 11..0
- name: BF2
- desc: CPLL FBCLK LOST [11:0]
-
- - name: GBT_CPLL_LOCK{bitfield}
- bitfield:
- - range: 30..28
- name: BF1
- desc: QPLL LOCK [5:3]
- - range: 27..16
- name: BF2
- desc: CPLL LOCK [23:12]
- - range: 14..12
- name: BF3
- desc: QPLL LOCK [2:0]
- - range: 11..0
- name: BF4
- desc: CPLL LOCK [11:0]
-
- - name: GBT_RXCDR_LOCK{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX CDR LOCK [23:12]
- - range: 11..0
- name: BF2
- desc: RX CDR LOCK [11:0]
-
- - name: GBT_CLK_SAMPLED{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: clk sampled [23:12]
- - range: 11..0
- name: BF2
- desc: clk sampled [11:0]
-
- - name: GBT_RX_IS_HEADER{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX IS HEADER [23:12]
- - range: 11..0
- name: BF2
- desc: RX IS HEADER [11:0]
-
- - name: GBT_RX_IS_DATA{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX IS DATA [23:12]
- - range: 11..0
- name: BF2
- desc: RX IS DATA [11:0]
-
- - name: GBT_RX_HEADER_FOUND{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX HEADER FOUND [23:12]
- - range: 11..0
- name: BF2
- desc: RX HEADER FOUND [11:0]
-
- - name: GBT_ALIGNMENT_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX ALIGNMENT DONE [23:12]
- - range: 11..0
- name: BF2
- desc: RX ALIGNMENT DONE [11:0]
-
- - name: GBT_OUT_MUX_STATUS{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: GBT output mux status [23:12]
- - range: 11..0
- name: BF2
- desc: GBT output mux status [11:0]
-
- - name: GBT_ERROR{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: Error flags [23:12]
- - range: 11..0
- name: BF2
- desc: Error flags [11:0]
-
- - name: GBT_GBT_TOPBOT_C{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: TopBot_c [23:12]
- - range: 11..0
- name: BF2
- desc: TopBot_c [11:0]
-
-HouseKeepingControlsAndMonitors:
- entries:
- - name: HK_CTRL{bitfield}
- offset: 0x0200
- type: W
- bitfield:
- - range: 66
- name: CDCE_REF_SEL
- desc: REF_SEL
- - range: 65
- name: CDCE_PD
- desc: PD
- - range: 64
- name: CDCE_SYNC
- desc: SYNC
- - range: 1
- name: I2C_CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: I2C_CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: PLL_LOCK
- offset: 0x0300
- bitfield:
- - range: 1..0
- desc: Main MMCM PLL Lock Status
-
- - name: HK_MON{bitfield}
- bitfield:
- - range: 1
- name: CDCE_PLL_LOCK
- desc: CDCE_PLL_LOCK
- - range: 0
- name: I2C_ACK_ERROR
- desc: i2c_ack_error
-
- - name: SPI_WR{bitfield}
- offset: 0x0400
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD{bitfield}
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR{bitfield}
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD{bitfield}
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
- - name: DEBUG_PORT{bitfield}
- offset: 0x0500
- type: W
- bitfield:
- - range: 67..64
- name: CLK
- desc: Debug clock and L1A port on SMA HTGx#4
- - range: 6..0
- name: GBT
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: INT_TEST_2
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#2
-
- - name: INT_TEST_3
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#3
diff --git a/sources/templates/yaml/registers-2.1.yaml b/sources/templates/yaml/registers-2.1.yaml
deleted file mode 100644
index 95ce0e32c6c891cbcdf87de2cfa457cf875dfd45..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-2.1.yaml
+++ /dev/null
@@ -1,878 +0,0 @@
-Registers:
- version: '2.1'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
-
-Bar0:
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: RD_POINTER
- desc: PC Read Pointer
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: READ_WRITE
- desc: Read/<o>Write</o>
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: CURRENT_ADDRESS
- desc: Current Address
-
-Bar1:
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 8
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControls
- offset: 0x1000
- - ref: CentralRouterMonitors
- offset: 0x3000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x4000
- - ref: GBTWrapperControls
- offset: 0x5000
- - ref: GBTWrapperMonitors
- offset: 0x6000
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x7000
-
-GenericBoardInformation:
- entries:
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- offset: 0x0008
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: STATUS_LEDS
- offset: 0x0010
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS{bitfield}
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- value: std_logic_vector(to_unsigned(GBT_NUM,8))
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709: VC709
- - 710: HTG710
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- value: std_logic_vector(to_unsigned(GBT_MAPPING,8))
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
-CentralRouterControls:
- offset: 0x0100
- desc: See Central Router Doc
- entries:
- - ref: GBT_CONTROL
- - name: CR_TH_UPDATE_CTRL
- type: T
- value: 1
- bitfield:
- - range: any
- - name: CR_FH_UPDATE_CTRL
- type: T
- value: 1
- bitfield:
- - range: any
-
-GBT_CONTROL:
- number: 24
- type: W
- bitfield:
- - range: 63..0
- entries:
- - ref: TH
- - ref: FH
-
-TH:
- number: 7
- format_name: GBT{index:02}
- entries:
- - name: TH
- desc: See Central Router Doc, indices [5,6] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
-
-FH:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FH
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
-
-CentralRouterMonitors:
- desc: See Central Router Doc
- entries:
- - ref: GBT_MON
-
-GBT_MON:
- number: 24
- bitfield:
- - range: 63..0
- entries:
- - name: TH
- format_name: CR_{name}_GBT{index:02}_MON
- - name: FH
- format_name: CR_{name}_GBT{index:02}_MON
-
-GBTEmulatorControlsAndMonitors:
- entries:
- - name: GBT_EMU_ENA{bitfield}
- type: W
- bitfield:
- - range: 1
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
- - range: 0
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
-
- - name: GBT_EMU_CONFIG{bitfield}
- type: W
- bitfield:
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- offset: 0x0018
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
-GBTWrapperControls:
- type: W
- entries:
- - name: GBT_LOGIC_RESET
- offset: 0x0400
- bitfield:
- - range: 63..0
- desc: Not internally connected (?)
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL{bitfield}
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE{bitfield}
- offset: 0x0480
- bitfield:
- - range: 59..48
- name: BF1
- desc: RxSlide select [23:12]
- - range: 43..32
- name: BF2
- desc: RxSlide select [11:0]
- - range: 27..16
- name: BF3
- desc: RxSlide manual [23:12
- - range: 11..0
- name: BF4
- desc: RxSlide manual [11:0]
-
- - name: GBT_TXUSRRDY{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- default: 0xFFF
- desc: TxUsrRdy [23:12]
- - range: 11..0
- name: BF2
- default: 0xFFF
- desc: TxUsrRdy [11:0]
-
- - name: GBT_RXUSRRDY{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- default: 0xFFF
- desc: RxUsrRdy [23:12]
- - range: 11..0
- name: BF2
- default: 0xFFF
- desc: RxUsrRdy [11:0]
-
- - name: GBT_GTTX_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: BF1
- desc: SOFT_RESET [5:3]
- - range: 27..16
- name: BF2
- desc: GTTX_RESET [23:12]
- - range: 14..12
- name: BF3
- desc: SOFT_RESET [2:0]
- - range: 11..0
- name: BF4
- desc: GTTX_RESET [11:0]
-
- - name: GBT_GTRX_RESET{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: GTRX_RESET [23:0]
- - range: 11..0
- name: BF2
- desc: GTRX_RESET [11:0]
-
- - name: GBT_PLL_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: BF1
- desc: QPLL_RESET [5:3]
- - range: 27..16
- name: BF2
- desc: CPLL_RESET [23:12]
- - range: 14..12
- name: BF3
- desc: QPLL_RESET [2:0]
- - range: 11..0
- name: BF4
- desc: CPLL_RESET [11:0]
-
- - name: GBT_SOFT_TX_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: BF1
- desc: SOFT_TX_RESET_ALL [5:3]
- - range: 27..16
- name: BF2
- desc: SOFT_TX_RESET_GT [23:12]
- - range: 14..12
- name: BF3
- desc: SOFT_TX_RESET_ALL [2:0]
- - range: 11..0
- name: BF4
- desc: SOFT_TX_RESET_GT [11:0]
-
- - name: GBT_SOFT_RX_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: BF1
- desc: SOFT_RX_RESET_ALL [5:3]
- - range: 27..16
- name: BF2
- desc: SOFT_RX_RESET_GT [23:12]
- - range: 14..12
- name: BF3
- desc: SOFT_RX_RESET_ALL [2:0]
- - range: 11..0
- name: BF4
- desc: SOFT_RX_RESET_GT [11:0]
-
- - name: GBT_ODD_EVEN{bitfield}
- offset: 0x0500
- bitfield:
- - range: 27..16
- name: BF1
- desc: OddEven [23:12]
- - range: 11..0
- name: BF2
- desc: OddEven [11:0]
-
- - name: GBT_TOPBOT{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: TopBot [23:12]
- - range: 11..0
- name: BF2
- desc: TopBot [11:0]
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: TX_OPT
-
- - name: GBT_RX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: RX_OPT
-
- - name: GBT_DATA_TXFORMAT{bitfield}
- bitfield:
- - range: 55..32
- name: BF1
- desc: DATA_TXFORMAT [47:24]
- - range: 23..0
- name: BF2
- desc: DATA_TXFORMAT [23:0]
-
- - name: GBT_DATA_RXFORMAT{bitfield}
- bitfield:
- - range: 55..32
- name: BF1
- desc: DATA_RXFORMAT [47:24]
- - range: 23..0
- name: BF2
- desc: DATA_RXFORMAT [23:0]
-
- - name: GBT_TX_RESET{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: TX Logic reset [23:12]
- - range: 11..0
- name: BF2
- desc: TX Logic reset [11:0]
-
- - name: GBT_RX_RESET{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX Logic reset [23:12]
- - range: 11..0
- name: BF2
- desc: RX Logic reset [11:0]
-
- - name: GBT_TX_TC_METHOD{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: TX time domain crossing method [23:12]
- - range: 11..0
- name: BF2
- desc: TX time domain crossing method [11:0]
-
- - name: GBT_OUTMUX_SEL{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: Descrambler output MUX selection [23:12]
- - range: 11..0
- name: BF2
- desc: Descrambler output MUX selection [11:0]
-
- - name: GBT_DNLNK_FO_SEL
- offset: 0x0600
- bitfield:
- - range: 31..0
- default: 0xFFFFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_UPLNK_FO_SEL
- bitfield:
- - range: 31..0
- default: 0xFFFFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-GBTWrapperMonitors:
- entries:
- - name: GBT_VERSION{bitfield}
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATA
- desc: Data
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE{bitfield}
- offset: 0x0680
- bitfield:
- - range: 27..16
- name: BF1
- desc: TX Reset done [23:12]
- - range: 11..0
- name: BF2
- desc: TX Reset done [11:0]
-
- - name: GBT_RXRESET_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX Reset done [23:12]
- - range: 11..0
- name: BF2
- desc: RX Reset done [11:0]
-
- - name: GBT_TXFSMRESET_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: TX FSM Reset done [23:12]
- - range: 11..0
- name: BF2
- desc: TX FSM Reset done [11:0]
-
- - name: GBT_RXFSMRESET_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX FSM Reset done [23:12]
- - range: 11..0
- name: BF2
- desc: RX FSM Reset done [11:0]
-
- - name: GBT_CPLL_FBCLK_LOST{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: CPLL FBCLK LOST [23:12]
- - range: 11..0
- name: BF2
- desc: CPLL FBCLK LOST [11:0]
-
- - name: GBT_CPLL_LOCK{bitfield}
- bitfield:
- - range: 30..28
- name: BF1
- desc: QPLL LOCK [5:3]
- - range: 27..16
- name: BF2
- desc: CPLL LOCK [23:12]
- - range: 14..12
- name: BF3
- desc: QPLL LOCK [2:0]
- - range: 11..0
- name: BF4
- desc: CPLL LOCK [11:0]
-
- - name: GBT_RXCDR_LOCK{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX CDR LOCK [23:12]
- - range: 11..0
- name: BF2
- desc: RX CDR LOCK [11:0]
-
- - name: GBT_CLK_SAMPLED{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: clk sampled [23:12]
- - range: 11..0
- name: BF2
- desc: clk sampled [11:0]
-
- - name: GBT_RX_IS_HEADER{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX IS HEADER [23:12]
- - range: 11..0
- name: BF2
- desc: RX IS HEADER [11:0]
-
- - name: GBT_RX_IS_DATA{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX IS DATA [23:12]
- - range: 11..0
- name: BF2
- desc: RX IS DATA [11:0]
-
- - name: GBT_RX_HEADER_FOUND{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX HEADER FOUND [23:12]
- - range: 11..0
- name: BF2
- desc: RX HEADER FOUND [11:0]
-
- - name: GBT_ALIGNMENT_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: RX ALIGNMENT DONE [23:12]
- - range: 11..0
- name: BF2
- desc: RX ALIGNMENT DONE [11:0]
-
- - name: GBT_OUT_MUX_STATUS{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: GBT output mux status [23:12]
- - range: 11..0
- name: BF2
- desc: GBT output mux status [11:0]
-
- - name: GBT_ERROR{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: Error flags [23:12]
- - range: 11..0
- name: BF2
- desc: Error flags [11:0]
-
- - name: GBT_GBT_TOPBOT_C{bitfield}
- bitfield:
- - range: 27..16
- name: BF1
- desc: TopBot_c [23:12]
- - range: 11..0
- name: BF2
- desc: TopBot_c [11:0]
-
-HouseKeepingControlsAndMonitors:
- entries:
- - name: HK_CTRL_I2C{bitfield}
- offset: 0x0200
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_CDCE{bitfield}
- offset: 0x0208
- type: W
- bitfield:
- - range: 2
- name: REF_SEL
- desc: REF_SEL
- - range: 1
- name: PD
- desc: PD
- - range: 0
- name: SYNC
- desc: SYNC
-
- - name: PLL_LOCK
- offset: 0x0300
- bitfield:
- - range: 1..0
- desc: Main MMCM PLL Lock Status
-
- - name: HK_MON{bitfield}
- bitfield:
- - range: 1
- name: CDCE_PLL_LOCK
- desc: CDCE_PLL_LOCK
- - range: 0
- name: I2C_ACK_ERROR
- desc: i2c_ack_error
-
- - name: SPI_WR{bitfield}
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD{bitfield}
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR{bitfield}
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD{bitfield}
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- offset: 0x0508
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_2
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#2
-
- - name: INT_TEST_3
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#3
diff --git a/sources/templates/yaml/registers-3.0.yaml b/sources/templates/yaml/registers-3.0.yaml
deleted file mode 100644
index 81c6d77706b3c7f49bbb72c380a7102958fb86aa..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-3.0.yaml
+++ /dev/null
@@ -1,922 +0,0 @@
-Registers:
- version: '3.0'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
-
-Bar0:
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: RD_POINTER
- desc: PC Read Pointer
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: READ_WRITE
- desc: Read/<o>Write</o>
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: CURRENT_ADDRESS
- desc: Current Address
-
-Bar1:
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 8
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControls
- offset: 0x1000
- - ref: CentralRouterMonitors
- offset: 0x3000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x4000
- - ref: GBTWrapperControls
- offset: 0x5000
- - ref: GBTWrapperMonitors
- offset: 0x6000
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x7000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS{bitfield}
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- value: std_logic_vector(to_unsigned(GBT_NUM,8))
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709: VC709
- - 710: HTG710
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- value: std_logic_vector(to_unsigned(GBT_MAPPING,8))
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
-CentralRouterControls:
- group: CRC
- desc: Central Router Controls
- entries:
- - name: CR_TH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: CR_FH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
-CR_GBT_CTRL:
- number: 24
- type: W
- bitfield:
- - range: 63..0
- entries:
- - ref: EGROUP_TH
- - ref: EGROUP_FH
-
-EGROUP_TH:
- number: 7
- format_name: GBT{index:02}
- entries:
- - name: TH
- desc: See Central Router Doc, indices [5,6] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - 0x00000124aaaa8006
- - 0x00000124aaaa8078
- - 0x00000124aaaa8001
- - 0x00000124aaaaff80
- - 0x00000124aaaae628
- - 0x00000124aaaa99d0
- - 0x0000000000000000
-
-EGROUP_FH:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FH
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
-
-CentralRouterMonitors:
- group: CRM
- desc: Central Router Monitors
- entries:
- - ref: CR_GBT_MON
-
-CR_GBT_MON:
- desc: See Central Router Doc
- number: 24
- bitfield:
- - range: 63..0
- entries:
- - name: TH
- format_name: CR_{name}_GBT{index:02}_MON
- - name: FH
- format_name: CR_{name}_GBT{index:02}_MON
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- entries:
- - name: GBT_EMU_ENA{bitfield}
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG{bitfield}
- type: W
- bitfield:
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- entries:
- - name: GBT_LOGIC_RESET
- offset: 0x0400
- bitfield:
- - range: 63..0
- desc: Not internally connected (?)
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL{bitfield}
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE{bitfield}
- offset: 0x0480
- bitfield:
- - range: 59..48
- name: S2312
- desc: RxSlide select [23:12]
- - range: 43..32
- name: S1100
- desc: RxSlide select [11:0]
- - range: 27..16
- name: M2312
- desc: RxSlide manual [23:12]
- - range: 11..0
- name: M1100
- desc: RxSlide manual [11:0]
-
- - name: GBT_TXUSRRDY{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: TxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: TxUsrRdy [11:0]
-
- - name: GBT_RXUSRRDY{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: RxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: RxUsrRdy [11:0]
-
- - name: GBT_GTTX_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: GTTX_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: GTTX_RESET [11:0]
-
- - name: GBT_GTRX_RESET{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: GTRX_RESET [23:12]
- - range: 11..0
- name: B1100
- desc: GTRX_RESET [11:0]
-
- - name: GBT_PLL_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL_RESET [11:0]
-
- - name: GBT_SOFT_TX_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_TX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_TX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_TX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_TX_RESET_GT [11:0]
-
- - name: GBT_SOFT_RX_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_RX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_RX_RESET_GT [11:0]
-
- - name: GBT_ODD_EVEN{bitfield}
- offset: 0x0500
- bitfield:
- - range: 27..16
- name: B2312
- desc: OddEven [23:12]
- - range: 11..0
- name: B1100
- desc: OddEven [11:0]
-
- - name: GBT_TOPBOT{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot [11:0]
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: TX_OPT
-
- - name: GBT_RX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: RX_OPT
-
- - name: GBT_DATA_TXFORMAT{bitfield}
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_TXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_TXFORMAT [23:0]
-
- - name: GBT_DATA_RXFORMAT{bitfield}
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_RXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_RXFORMAT [23:0]
-
- - name: GBT_TX_RESET{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: TX Logic reset [11:0]
-
- - name: GBT_RX_RESET{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: RX Logic reset [11:0]
-
- - name: GBT_TX_TC_METHOD{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX time domain crossing method [23:12]
- - range: 11..0
- name: B1100
- desc: TX time domain crossing method [11:0]
-
- - name: GBT_OUTMUX_SEL{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: Descrambler output MUX selection [23:12]
- - range: 11..0
- name: B1100
- desc: Descrambler output MUX selection [11:0]
-
- - name: GBT_DNLNK_FO_SEL
- offset: 0x0600
- bitfield:
- - range: 31..0
- default: 0xFFFFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_UPLNK_FO_SEL
- bitfield:
- - range: 31..0
- default: 0xFFFFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- entries:
- - name: GBT_VERSION{bitfield}
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE{bitfield}
- offset: 0x0680
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX Reset done [11:0]
-
- - name: GBT_RXRESET_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX Reset done [11:0]
-
- - name: GBT_TXFSMRESET_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX FSM Reset done [11:0]
-
- - name: GBT_RXFSMRESET_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX FSM Reset done [11:0]
-
- - name: GBT_CPLL_FBCLK_LOST{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: CPLL FBCLK LOST [23:12]
- - range: 11..0
- name: B1100
- desc: CPLL FBCLK LOST [11:0]
-
- - name: GBT_CPLL_LOCK{bitfield}
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL LOCK [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL LOCK [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL LOCK [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL LOCK [11:0]
-
- - name: GBT_RXCDR_LOCK{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX CDR LOCK [23:12]
- - range: 11..0
- name: B1100
- desc: RX CDR LOCK [11:0]
-
- - name: GBT_CLK_SAMPLED{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: clk sampled [23:12]
- - range: 11..0
- name: B1100
- desc: clk sampled [11:0]
-
- - name: GBT_RX_IS_HEADER{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS HEADER [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS HEADER [11:0]
-
- - name: GBT_RX_IS_DATA{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS DATA [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS DATA [11:0]
-
- - name: GBT_RX_HEADER_FOUND{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX HEADER FOUND [23:12]
- - range: 11..0
- name: B1100
- desc: RX HEADER FOUND [11:0]
-
- - name: GBT_ALIGNMENT_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX ALIGNMENT DONE [23:12]
- - range: 11..0
- name: B1100
- desc: RX ALIGNMENT DONE [11:0]
-
- - name: GBT_OUT_MUX_STATUS{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: GBT output mux status [23:12]
- - range: 11..0
- name: B1100
- desc: GBT output mux status [11:0]
-
- - name: GBT_ERROR{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: Error flags [23:12]
- - range: 11..0
- name: B1100
- desc: Error flags [11:0]
-
- - name: GBT_GBT_TOPBOT_C{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot_c [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot_c [11:0]
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- entries:
- - name: HK_CTRL_CDCE{bitfield}
- offset: 0x0200
- type: W
- bitfield:
- - range: 2
- name: REF_SEL
- desc: REF_SEL
- - range: 1
- name: PD
- desc: PD
- - range: 0
- name: SYNC
- desc: SYNC
-
- - name: HK_CTRL_I2C{bitfield}
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: MMCM_MAIN{bitfield}
- offset: 0x0300
- bitfield:
- - range: 1
- name: OSC_SEL
- desc: Main MMCM Oscillator Select
- - range: 0
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: HK_MON{bitfield}
- bitfield:
- - range: 1
- name: CDCE_PLL_LOCK
- desc: CDCE_PLL_LOCK
- - range: 0
- name: I2C_ACK_ERROR
- desc: i2c_ack_error
-
- - name: SPI_WR{bitfield}
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD{bitfield}
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR{bitfield}
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD{bitfield}
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
- - name: TTC_EMU{bitfield}
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_2
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#2
-
- - name: INT_TEST_3
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#3
diff --git a/sources/templates/yaml/registers-3.1.yaml b/sources/templates/yaml/registers-3.1.yaml
deleted file mode 100644
index 0a235e5cc19c4a7844b30f1fa655d08df3d1403e..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-3.1.yaml
+++ /dev/null
@@ -1,988 +0,0 @@
-Registers:
- version: '3.1'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: RD_POINTER
- desc: PC Read Pointer
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: READ_WRITE
- desc: Read/<o>Write</o>
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: CURRENT_ADDRESS
- desc: Current Address
-
-Bar1:
- endpoints: 0,1
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 8
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControls
- offset: 0x1000
- - ref: CentralRouterMonitors
- offset: 0x3000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x4000
- - ref: GBTWrapperControls
- offset: 0x5000
- - ref: GBTWrapperMonitors
- offset: 0x6000
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x7000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS{bitfield}
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709: VC709
- - 710: HTG710
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST{bitfield}
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - name: INCLUDE_EPROC16
- type: R
- bitfield:
- - range: 0
- desc: EPROC16 is included in Central Router
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
-
-CentralRouterControls:
- group: CRC
- desc: Central Router Controls
- endpoints: 0,1
- entries:
- - name: CR_TH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: CR_FH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
-CR_GBT_CTRL:
- number: 24
- type: W
- bitfield:
- - range: 63..0
- entries:
- - ref: EGROUP_TH
- - ref: EGROUP_FH
-
-EGROUP_TH:
- number: 7
- format_name: GBT{index:02}
- entries:
- - name: TH
- desc: See Central Router Doc, indices [5,6] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - 0x00000124aaaa8006
- - 0x00000124aaaa8078
- - 0x00000124aaaa8001
- - 0x00000124aaaaff80
- - 0x00000124aaaae628
- - 0x00000124aaaa99d0
- - 0x0000000000000000
-
-EGROUP_FH:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FH
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
-
-CentralRouterMonitors:
- group: CRM
- desc: Central Router Monitors
- endpoints: 0,1
- entries:
- - ref: CR_GBT_MON
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- bitfield:
- - range: 63..0
- entries:
- - name: TH
- format_name: CR_{name}_GBT{index:02}_MON
- - name: FH
- format_name: CR_{name}_GBT{index:02}_MON
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA{bitfield}
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG{bitfield}
- type: W
- bitfield:
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_LOGIC_RESET
- offset: 0x0400
- bitfield:
- - range: 63..0
- desc: Not internally connected (?)
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL{bitfield}
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE{bitfield}
- offset: 0x0480
- bitfield:
- - range: 59..48
- name: S2312
- desc: RxSlide select [23:12]
- - range: 43..32
- name: S1100
- desc: RxSlide select [11:0]
- - range: 27..16
- name: M2312
- desc: RxSlide manual [23:12]
- - range: 11..0
- name: M1100
- desc: RxSlide manual [11:0]
-
- - name: GBT_TXUSRRDY{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: TxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: TxUsrRdy [11:0]
-
- - name: GBT_RXUSRRDY{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: RxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: RxUsrRdy [11:0]
-
- - name: GBT_GTTX_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: GTTX_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: GTTX_RESET [11:0]
-
- - name: GBT_GTRX_RESET{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: GTRX_RESET [23:12]
- - range: 11..0
- name: B1100
- desc: GTRX_RESET [11:0]
-
- - name: GBT_PLL_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL_RESET [11:0]
-
- - name: GBT_SOFT_TX_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_TX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_TX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_TX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_TX_RESET_GT [11:0]
-
- - name: GBT_SOFT_RX_RESET{bitfield}
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_RX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_RX_RESET_GT [11:0]
-
- - name: GBT_ODD_EVEN{bitfield}
- offset: 0x0500
- bitfield:
- - range: 27..16
- name: B2312
- desc: OddEven [23:12]
- - range: 11..0
- name: B1100
- desc: OddEven [11:0]
-
- - name: GBT_TOPBOT{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot [11:0]
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: TX_OPT
-
- - name: GBT_RX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: RX_OPT
-
- - name: GBT_DATA_TXFORMAT{bitfield}
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_TXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_TXFORMAT [23:0]
-
- - name: GBT_DATA_RXFORMAT{bitfield}
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_RXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_RXFORMAT [23:0]
-
- - name: GBT_TX_RESET{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: TX Logic reset [11:0]
-
- - name: GBT_RX_RESET{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: RX Logic reset [11:0]
-
- - name: GBT_TX_TC_METHOD{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX time domain crossing method [23:12]
- - range: 11..0
- name: B1100
- desc: TX time domain crossing method [11:0]
-
- - name: GBT_OUTMUX_SEL{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: Descrambler output MUX selection [23:12]
- - range: 11..0
- name: B1100
- desc: Descrambler output MUX selection [11:0]
-
- - name: GBT_DNLNK_FO_SEL
- offset: 0x0600
- bitfield:
- - range: 31..0
- default: 0xFFFFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_UPLNK_FO_SEL
- bitfield:
- - range: 31..0
- default: 0xFFFFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION{bitfield}
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE{bitfield}
- offset: 0x0680
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX Reset done [11:0]
-
- - name: GBT_RXRESET_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX Reset done [11:0]
-
- - name: GBT_TXFSMRESET_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX FSM Reset done [11:0]
-
- - name: GBT_RXFSMRESET_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX FSM Reset done [11:0]
-
- - name: GBT_CPLL_FBCLK_LOST{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: CPLL FBCLK LOST [23:12]
- - range: 11..0
- name: B1100
- desc: CPLL FBCLK LOST [11:0]
-
- - name: GBT_CPLL_LOCK{bitfield}
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL LOCK [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL LOCK [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL LOCK [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL LOCK [11:0]
-
- - name: GBT_RXCDR_LOCK{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX CDR LOCK [23:12]
- - range: 11..0
- name: B1100
- desc: RX CDR LOCK [11:0]
-
- - name: GBT_CLK_SAMPLED{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: clk sampled [23:12]
- - range: 11..0
- name: B1100
- desc: clk sampled [11:0]
-
- - name: GBT_RX_IS_HEADER{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS HEADER [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS HEADER [11:0]
-
- - name: GBT_RX_IS_DATA{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS DATA [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS DATA [11:0]
-
- - name: GBT_RX_HEADER_FOUND{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX HEADER FOUND [23:12]
- - range: 11..0
- name: B1100
- desc: RX HEADER FOUND [11:0]
-
- - name: GBT_ALIGNMENT_DONE{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX ALIGNMENT DONE [23:12]
- - range: 11..0
- name: B1100
- desc: RX ALIGNMENT DONE [11:0]
-
- - name: GBT_OUT_MUX_STATUS{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: GBT output mux status [23:12]
- - range: 11..0
- name: B1100
- desc: GBT output mux status [11:0]
-
- - name: GBT_ERROR{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: Error flags [23:12]
- - range: 11..0
- name: B1100
- desc: Error flags [11:0]
-
- - name: GBT_GBT_TOPBOT_C{bitfield}
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot_c [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot_c [11:0]
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
-
- - name: HK_CTRL_CDCE{bitfield}
- offset: 0x0200
- type: W
- bitfield:
- - range: 2
- name: REF_SEL
- desc: REF_SEL
- - range: 1
- name: PD
- desc: PD
- - range: 0
- name: SYNC
- desc: SYNC
-
- - name: HK_CTRL_I2C{bitfield}
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: MMCM_MAIN{bitfield}
- offset: 0x0300
- bitfield:
- - range: 2
- name: AUTOMATIC_CLOCK_SWITCH_ENABLED
- desc: 1 when the automatic clock switch is enabled in the design
- - range: 1
- name: OSC_SEL
- desc: |
- Main MMCM Oscillator Select
- 1: TTC clock
- 0: Local clock
- - range: 0
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: HK_MON{bitfield}
- bitfield:
- - range: 1
- name: CDCE_PLL_LOCK
- desc: CDCE_PLL_LOCK
- - range: 0
- name: I2C_ACK_ERROR
- desc: i2c_ack_error
-
- - name: SPI_WR{bitfield}
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD{bitfield}
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR{bitfield}
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD{bitfield}
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
- - name: TTC_EMU{bitfield}
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_2
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#2
-
- - name: INT_TEST_3
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#3
diff --git a/sources/templates/yaml/registers-3.2.yaml b/sources/templates/yaml/registers-3.2.yaml
deleted file mode 100644
index a7f17a418908cf973a5dd6ab4c8533ec9553263a..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-3.2.yaml
+++ /dev/null
@@ -1,1337 +0,0 @@
-Registers:
- version: '3.2'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: RD_POINTER
- desc: PC Read Pointer
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: READ_WRITE
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: CURRENT_ADDRESS
- desc: Current Address
-
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 8
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControls
- offset: 0x1000
- - ref: CentralRouterMonitors
- offset: 0x3000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x4000
- - ref: GBTWrapperControls
- offset: 0x5000
- - ref: GBTWrapperMonitors
- offset: 0x6000
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x7000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC709
- - 710 (0x2c6): HTG710
- - 711 (0x2c7): BNL711
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - name: INCLUDE_EPROC16
- type: R
- bitfield:
- - range: 7
- name: FRHOEPROC2
- desc: FromHost EPROC2 is included in Central Router
- - range: 6
- name: FRHOEPROC4
- desc: FromHost EPROC4 is included in Central Router
- - range: 5
- name: FRHOEPROC8
- desc: FromHost EPROC8 is included in Central Router
- - range: 4
- name: FRHOEPROC16
- desc: FromHost EPROC16 is included in Central Router
- - range: 3
- name: TOHOEPROC2
- desc: ToHost EPROC2 is included in Central Router
- - range: 2
- name: TOHOEPROC4
- desc: ToHost EPROC4 is included in Central Router
- - range: 1
- name: TOHOEPROC8
- desc: ToHost EPROC8 is included in Central Router
- - range: 0
- name: TOHOEPROC16
- desc: ToHost EPROC16 is included in Central Router
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
-
-CentralRouterControls:
- group: CRC
- desc: Central Router Controls
- endpoints: 0,1
- entries:
- - name: CR_TH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: CR_FH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: FH_IC_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - ref: TTC_FANOUT_CTRL
- desc: Controls the TTC Fanout delay values
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the busy or Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
-CR_GBT_CTRL:
- number: 24
- type: W
- bitfield:
- - range: 63..0
- entries:
- - ref: EGROUP_TH
- - ref: EGROUP_FH
-
-EGROUP_TH:
- number: 7
- format_name: GBT{index:02}
- entries:
- - name: TH
- desc: See Central Router Doc, indices [5,6] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - 0x00000124aaaa8006
- - 0x00000124aaaa8078
- - 0x00000124aaaa8001
- - 0x00000124aaaaff80
- - 0x00000124aaaae628
- - 0x00000124aaaa99d0
- - 0x0000000000000000
-
-EGROUP_FH:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FH
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
-
-
-IC_FIFOS:
- number: 24
- format_name: FH_TH_IC_FIFOS
- entries:
- - name: FH
- format_name: FH_IC_FIFO_{index:02}
- type_name: FH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.FH_IC_FIFO_{index:02}.FULL
- name: WE
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TH
- format_name: TH_IC_FIFO_{index:02}
- type_name: TH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.TH_IC_FIFO_{index:02}.EMPTY
- name: RE
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- bitfield:
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- bitfield:
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
- - name: TTC_TOHOST
- format_name: TTC_TOHOST_{index:02}
- type_name: TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 0
- default: 0x0
-
-TTC_FANOUT_CTRL:
- number: 24
- format_name: TTC_FANOUT_CTRLS
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Configures the FromHost TTC pipeline in the fanout selector
- type: W
- bitfield:
- - range: 3..0
- default: 0
-
-CentralRouterMonitors:
- group: CRM
- desc: Central Router Monitors
- endpoints: 0,1
- entries:
- - ref: CR_GBT_MON
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - name: CR_DEFAULT_EPROC_ENA0
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENA1
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENA2
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENA3
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENA4
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENA5
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENA6
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENA7
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING0
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING1
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING2
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING3
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING4
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING5
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING6
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING7
- type: R
- bitfield:
- - range: 14..0
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- bitfield:
- - range: 63..0
- entries:
- - name: TH
- format_name: CR_{name}_GBT{index:02}_MON
- - name: FH
- format_name: CR_{name}_GBT{index:02}_MON
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_LOGIC_RESET
- offset: 0x0400
- bitfield:
- - range: 63..0
- desc: Not internally connected (?)
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE
- offset: 0x0480
- bitfield:
- - range: 59..48
- name: S2312
- desc: RxSlide select [23:12]
- - range: 43..32
- name: S1100
- desc: RxSlide select [11:0]
- - range: 27..16
- name: M2312
- desc: RxSlide manual [23:12]
- - range: 11..0
- name: M1100
- desc: RxSlide manual [11:0]
-
- - name: GBT_TXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: TxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: TxUsrRdy [11:0]
-
- - name: GBT_RXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: RxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: RxUsrRdy [11:0]
-
- - name: GBT_GTTX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: GTTX_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: GTTX_RESET [11:0]
-
- - name: GBT_GTRX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: GTRX_RESET [23:12]
- - range: 11..0
- name: B1100
- desc: GTRX_RESET [11:0]
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL_RESET [11:0]
-
- - name: GBT_SOFT_TX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_TX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_TX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_TX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_TX_RESET_GT [11:0]
-
- - name: GBT_SOFT_RX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_RX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_RX_RESET_GT [11:0]
-
- - name: GBT_ODD_EVEN
- offset: 0x0500
- bitfield:
- - range: 27..16
- name: B2312
- desc: OddEven [23:12]
- - range: 11..0
- name: B1100
- desc: OddEven [11:0]
-
- - name: GBT_TOPBOT
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot [11:0]
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: TX_OPT
-
- - name: GBT_RX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: RX_OPT
-
- - name: GBT_DATA_TXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_TXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_TXFORMAT [23:0]
-
- - name: GBT_DATA_RXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_RXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_RXFORMAT [23:0]
-
- - name: GBT_TX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: TX Logic reset [11:0]
-
- - name: GBT_RX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: RX Logic reset [11:0]
-
- - name: GBT_TX_TC_METHOD
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX time domain crossing method [23:12]
- - range: 11..0
- name: B1100
- desc: TX time domain crossing method [11:0]
-
- - name: GBT_OUTMUX_SEL
- bitfield:
- - range: 27..16
- name: B2312
- desc: Descrambler output MUX selection [23:12]
- - range: 11..0
- name: B1100
- desc: Descrambler output MUX selection [11:0]
-
- - name: GBT_TC_EDGE
- bitfield:
- - range: 27..16
- name: B2312
- desc: Sampling edge selection for TX domain crossing [23:12]
- - range: 11..0
- name: B1100
- desc: Sampling edge selection for TX domain crossing [11:0]
-
- - name: GBT_DNLNK_FO_SEL
- offset: 0x0600
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_UPLNK_FO_SEL
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX Reset done [11:0]
-
- - name: GBT_RXRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX Reset done [11:0]
-
- - name: GBT_TXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX FSM Reset done [11:0]
-
- - name: GBT_RXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX FSM Reset done [11:0]
-
- - name: GBT_CPLL_FBCLK_LOST
- bitfield:
- - range: 27..16
- name: B2312
- desc: CPLL FBCLK LOST [23:12]
- - range: 11..0
- name: B1100
- desc: CPLL FBCLK LOST [11:0]
-
- - name: GBT_CPLL_LOCK
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL LOCK [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL LOCK [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL LOCK [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL LOCK [11:0]
-
- - name: GBT_RXCDR_LOCK
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX CDR LOCK [23:12]
- - range: 11..0
- name: B1100
- desc: RX CDR LOCK [11:0]
-
- - name: GBT_CLK_SAMPLED
- bitfield:
- - range: 27..16
- name: B2312
- desc: clk sampled [23:12]
- - range: 11..0
- name: B1100
- desc: clk sampled [11:0]
-
- - name: GBT_RX_IS_HEADER
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS HEADER [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS HEADER [11:0]
-
- - name: GBT_RX_IS_DATA
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS DATA [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS DATA [11:0]
-
- - name: GBT_RX_HEADER_FOUND
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX HEADER FOUND [23:12]
- - range: 11..0
- name: B1100
- desc: RX HEADER FOUND [11:0]
-
- - name: GBT_ALIGNMENT_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX ALIGNMENT DONE [23:12]
- - range: 11..0
- name: B1100
- desc: RX ALIGNMENT DONE [11:0]
-
- - name: GBT_OUT_MUX_STATUS
- bitfield:
- - range: 27..16
- name: B2312
- desc: GBT output mux status [23:12]
- - range: 11..0
- name: B1100
- desc: GBT output mux status [11:0]
-
- - name: GBT_ERROR
- bitfield:
- - range: 27..16
- name: B2312
- desc: Error flags [23:12]
- - range: 11..0
- name: B1100
- desc: Error flags [11:0]
-
- - name: GBT_GBT_TOPBOT_C
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot_c [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot_c [11:0]
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
- - name: HK_CTRL_CDCE
- offset: 0x0200
- type: W
- bitfield:
- - range: 2
- name: REF_SEL
- desc: REF_SEL
- - range: 1
- name: PD
- desc: PD
- - range: 0
- name: SYNC
- desc: SYNC
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_FORCE
- desc: force the use of the Local Clock in any circumstance, overrule automatic clock switch
- - range: 2
- type: R
- name: AUTOMATIC_CLOCK_SWITCH_ENABLED
- desc: 1 when the automatic clock switch is enabled in the design
- - range: 1
- type: R
- name: OSC_SEL
- desc: |
- Main MMCM Oscillator Select
- 1: TTC clock
- 0: Local clock
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: HK_MON
- bitfield:
- - range: 1
- name: CDCE_PLL_LOCK
- desc: CDCE_PLL_LOCK
- - range: 0
- name: I2C_ACK_ERROR
- desc: i2c_ack_error
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL711 locked
- - endpoints: 0,1
- name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
- - endpoints: 0,1
- name: FPGA_ENDPOINT
- type: R
- bitfield:
- - range: 0
- desc: Endpoint of the FPGA
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_2
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#2
-
- - name: INT_TEST_3
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#3
diff --git a/sources/templates/yaml/registers-3.3.yaml b/sources/templates/yaml/registers-3.3.yaml
deleted file mode 100644
index 415a95c93860dba1b207666f6c0b57e63a3bbde9..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-3.3.yaml
+++ /dev/null
@@ -1,1337 +0,0 @@
-Registers:
- version: '3.3'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: RD_POINTER
- desc: PC Read Pointer
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: READ_WRITE
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: CURRENT_ADDRESS
- desc: Current Address
-
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 8
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControls
- offset: 0x1000
- - ref: CentralRouterMonitors
- offset: 0x3000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x4000
- - ref: GBTWrapperControls
- offset: 0x5000
- - ref: GBTWrapperMonitors
- offset: 0x6000
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x7000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC709
- - 710 (0x2c6): HTG710
- - 711 (0x2c7): BNL711
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - name: INCLUDE_EPROC16
- type: R
- bitfield:
- - range: 7
- name: FRHOEPROC2
- desc: FromHost EPROC2 is included in Central Router
- - range: 6
- name: FRHOEPROC4
- desc: FromHost EPROC4 is included in Central Router
- - range: 5
- name: FRHOEPROC8
- desc: FromHost EPROC8 is included in Central Router
- - range: 4
- name: FRHOEPROC16
- desc: FromHost EPROC16 is included in Central Router
- - range: 3
- name: TOHOEPROC2
- desc: ToHost EPROC2 is included in Central Router
- - range: 2
- name: TOHOEPROC4
- desc: ToHost EPROC4 is included in Central Router
- - range: 1
- name: TOHOEPROC8
- desc: ToHost EPROC8 is included in Central Router
- - range: 0
- name: TOHOEPROC16
- desc: ToHost EPROC16 is included in Central Router
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
-
-CentralRouterControls:
- group: CRC
- desc: Central Router Controls
- endpoints: 0,1
- entries:
- - name: CR_TH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: CR_FH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: FH_IC_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - ref: TTC_FANOUT_CTRL
- desc: Controls the TTC Fanout delay values
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the busy or Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
-CR_GBT_CTRL:
- number: 24
- type: W
- bitfield:
- - range: 63..0
- entries:
- - ref: EGROUP_TH
- - ref: EGROUP_FH
-
-EGROUP_TH:
- number: 7
- format_name: GBT{index:02}
- entries:
- - name: TH
- desc: See Central Router Doc, indices [5,6] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - 0x00000124aaaa8006
- - 0x00000124aaaa8078
- - 0x00000124aaaa8001
- - 0x00000124aaaaff80
- - 0x00000124aaaae628
- - 0x00000124aaaa99d0
- - 0x0000000000000000
-
-EGROUP_FH:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FH
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
-
-
-IC_FIFOS:
- number: 24
- format_name: FH_TH_IC_FIFOS
- entries:
- - name: FH
- format_name: FH_IC_FIFO_{index:02}
- type_name: FH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.FH_IC_FIFO_{index:02}.FULL
- name: WE
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TH
- format_name: TH_IC_FIFO_{index:02}
- type_name: TH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.TH_IC_FIFO_{index:02}.EMPTY
- name: RE
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- bitfield:
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- bitfield:
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
- - name: TTC_TOHOST
- format_name: TTC_TOHOST_{index:02}
- type_name: TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 0
- default: 0x0
-
-TTC_FANOUT_CTRL:
- number: 24
- format_name: TTC_FANOUT_CTRLS
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Configures the FromHost TTC pipeline in the fanout selector
- type: W
- bitfield:
- - range: 3..0
- default: 0
-
-CentralRouterMonitors:
- group: CRM
- desc: Central Router Monitors
- endpoints: 0,1
- entries:
- - ref: CR_GBT_MON
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - name: CR_DEFAULT_EPROC_ENA0
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENA1
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENA2
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENA3
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENA4
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENA5
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENA6
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENA7
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING0
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING1
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING2
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING3
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING4
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING5
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING6
- type: R
- bitfield:
- - range: 14..0
- - name: CR_DEFAULT_EPROC_ENCODING7
- type: R
- bitfield:
- - range: 14..0
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- bitfield:
- - range: 63..0
- entries:
- - name: TH
- format_name: CR_{name}_GBT{index:02}_MON
- - name: FH
- format_name: CR_{name}_GBT{index:02}_MON
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_LOGIC_RESET
- offset: 0x0400
- bitfield:
- - range: 63..0
- desc: Not internally connected (?)
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE
- offset: 0x0480
- bitfield:
- - range: 59..48
- name: S2312
- desc: RxSlide select [23:12]
- - range: 43..32
- name: S1100
- desc: RxSlide select [11:0]
- - range: 27..16
- name: M2312
- desc: RxSlide manual [23:12]
- - range: 11..0
- name: M1100
- desc: RxSlide manual [11:0]
-
- - name: GBT_TXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: TxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: TxUsrRdy [11:0]
-
- - name: GBT_RXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: RxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: RxUsrRdy [11:0]
-
- - name: GBT_GTTX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: GTTX_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: GTTX_RESET [11:0]
-
- - name: GBT_GTRX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: GTRX_RESET [23:12]
- - range: 11..0
- name: B1100
- desc: GTRX_RESET [11:0]
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL_RESET [11:0]
-
- - name: GBT_SOFT_TX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_TX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_TX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_TX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_TX_RESET_GT [11:0]
-
- - name: GBT_SOFT_RX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_RX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_RX_RESET_GT [11:0]
-
- - name: GBT_ODD_EVEN
- offset: 0x0500
- bitfield:
- - range: 27..16
- name: B2312
- desc: OddEven [23:12]
- - range: 11..0
- name: B1100
- desc: OddEven [11:0]
-
- - name: GBT_TOPBOT
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot [11:0]
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: TX_OPT
-
- - name: GBT_RX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: RX_OPT
-
- - name: GBT_DATA_TXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_TXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_TXFORMAT [23:0]
-
- - name: GBT_DATA_RXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_RXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_RXFORMAT [23:0]
-
- - name: GBT_TX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: TX Logic reset [11:0]
-
- - name: GBT_RX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: RX Logic reset [11:0]
-
- - name: GBT_TX_TC_METHOD
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX time domain crossing method [23:12]
- - range: 11..0
- name: B1100
- desc: TX time domain crossing method [11:0]
-
- - name: GBT_OUTMUX_SEL
- bitfield:
- - range: 27..16
- name: B2312
- desc: Descrambler output MUX selection [23:12]
- - range: 11..0
- name: B1100
- desc: Descrambler output MUX selection [11:0]
-
- - name: GBT_TC_EDGE
- bitfield:
- - range: 27..16
- name: B2312
- desc: Sampling edge selection for TX domain crossing [23:12]
- - range: 11..0
- name: B1100
- desc: Sampling edge selection for TX domain crossing [11:0]
-
- - name: GBT_DNLNK_FO_SEL
- offset: 0x0600
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_UPLNK_FO_SEL
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX Reset done [11:0]
-
- - name: GBT_RXRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX Reset done [11:0]
-
- - name: GBT_TXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX FSM Reset done [11:0]
-
- - name: GBT_RXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX FSM Reset done [11:0]
-
- - name: GBT_CPLL_FBCLK_LOST
- bitfield:
- - range: 27..16
- name: B2312
- desc: CPLL FBCLK LOST [23:12]
- - range: 11..0
- name: B1100
- desc: CPLL FBCLK LOST [11:0]
-
- - name: GBT_CPLL_LOCK
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL LOCK [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL LOCK [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL LOCK [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL LOCK [11:0]
-
- - name: GBT_RXCDR_LOCK
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX CDR LOCK [23:12]
- - range: 11..0
- name: B1100
- desc: RX CDR LOCK [11:0]
-
- - name: GBT_CLK_SAMPLED
- bitfield:
- - range: 27..16
- name: B2312
- desc: clk sampled [23:12]
- - range: 11..0
- name: B1100
- desc: clk sampled [11:0]
-
- - name: GBT_RX_IS_HEADER
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS HEADER [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS HEADER [11:0]
-
- - name: GBT_RX_IS_DATA
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS DATA [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS DATA [11:0]
-
- - name: GBT_RX_HEADER_FOUND
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX HEADER FOUND [23:12]
- - range: 11..0
- name: B1100
- desc: RX HEADER FOUND [11:0]
-
- - name: GBT_ALIGNMENT_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX ALIGNMENT DONE [23:12]
- - range: 11..0
- name: B1100
- desc: RX ALIGNMENT DONE [11:0]
-
- - name: GBT_OUT_MUX_STATUS
- bitfield:
- - range: 27..16
- name: B2312
- desc: GBT output mux status [23:12]
- - range: 11..0
- name: B1100
- desc: GBT output mux status [11:0]
-
- - name: GBT_ERROR
- bitfield:
- - range: 27..16
- name: B2312
- desc: Error flags [23:12]
- - range: 11..0
- name: B1100
- desc: Error flags [11:0]
-
- - name: GBT_GBT_TOPBOT_C
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot_c [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot_c [11:0]
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
- - name: HK_CTRL_CDCE
- offset: 0x0200
- type: W
- bitfield:
- - range: 2
- name: REF_SEL
- desc: REF_SEL
- - range: 1
- name: PD
- desc: PD
- - range: 0
- name: SYNC
- desc: SYNC
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_FORCE
- desc: force the use of the Local Clock in any circumstance, overrule automatic clock switch
- - range: 2
- type: R
- name: AUTOMATIC_CLOCK_SWITCH_ENABLED
- desc: 1 when the automatic clock switch is enabled in the design
- - range: 1
- type: R
- name: OSC_SEL
- desc: |
- Main MMCM Oscillator Select
- 1: TTC clock
- 0: Local clock
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: HK_MON
- bitfield:
- - range: 1
- name: CDCE_PLL_LOCK
- desc: CDCE_PLL_LOCK
- - range: 0
- name: I2C_ACK_ERROR
- desc: i2c_ack_error
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL711 locked
- - endpoints: 0,1
- name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
- - endpoints: 0,1
- name: FPGA_ENDPOINT
- type: R
- bitfield:
- - range: 0
- desc: Endpoint of the FPGA
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_2
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#2
-
- - name: INT_TEST_3
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#3
diff --git a/sources/templates/yaml/registers-3.4.yaml b/sources/templates/yaml/registers-3.4.yaml
deleted file mode 100644
index 173ca09bd720ec5b186ebb2c4fb5c3561eb96e99..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-3.4.yaml
+++ /dev/null
@@ -1,1617 +0,0 @@
-Registers:
- version: '3.4'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: RD_POINTER
- desc: PC Read Pointer
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: READ_WRITE
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: CURRENT_ADDRESS
- desc: Current Address
-
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 8
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControls
- offset: 0x1000
- - ref: CentralRouterMonitors
- offset: 0x3000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x4000
- - ref: GBTWrapperControls
- offset: 0x5000
- - ref: GBTWrapperMonitors
- offset: 0x6000
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x7000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC709
- - 710 (0x2c6): HTG710
- - 711 (0x2c7): BNL711
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - name: INCLUDE_EPROC16
- type: R
- bitfield:
- - range: 7
- name: FRHOEPROC2
- desc: FromHost EPROC2 is included in Central Router
- - range: 6
- name: FRHOEPROC4
- desc: FromHost EPROC4 is included in Central Router
- - range: 5
- name: FRHOEPROC8
- desc: FromHost EPROC8 is included in Central Router
- - range: 4
- name: FRHOEPROC16
- desc: FromHost EPROC16 is included in Central Router
- - range: 3
- name: TOHOEPROC2
- desc: ToHost EPROC2 is included in Central Router
- - range: 2
- name: TOHOEPROC4
- desc: ToHost EPROC4 is included in Central Router
- - range: 1
- name: TOHOEPROC8
- desc: ToHost EPROC8 is included in Central Router
- - range: 0
- name: TOHOEPROC16
- desc: ToHost EPROC16 is included in Central Router
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
-
-CentralRouterControls:
- group: CRC
- desc: Central Router Controls
- endpoints: 0,1
- entries:
- - name: CR_TH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: CR_FH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: FH_IC_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - ref: TTC_FANOUT_CTRL
- desc: Controls the TTC Fanout delay values
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the busy or Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
- - name: COMMA_CHAR
- desc: Idle character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0FA
- desc: -K.28.5
- - range: 17..8
- name: P
- default: 0x305
- desc: +K.28.5
- - range: 7..0
- name: BYTE
- default: 0xBC
- desc: K28.5
-
- - name: SOC_CHAR
- desc: Start of chunk character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F9
- desc: -K.28.1
- - range: 17..8
- name: P
- default: 0x306
- desc: +K.28.1
- - range: 7..0
- name: BYTE
- default: 0x3C
- desc: K28.1
-
- - name: EOC_CHAR
- desc: End of chunk character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F6
- desc: -K.28.6
- - range: 17..8
- name: P
- default: 0x309
- desc: +K.28.6
- - range: 7..0
- name: BYTE
- default: 0xDC
- desc: K28.6
-
- - name: SOB_CHAR
- desc: Start of busy character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F5
- desc: -K.28.2
- - range: 17..8
- name: P
- default: 0x30A
- desc: +K.28.2
- - range: 7..0
- name: BYTE
- default: 0x5C
- desc: K28.2
-
- - name: EOB_CHAR
- desc: End of busy character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F3
- desc: -K.28.3
- - range: 17..8
- name: P
- default: 0x30C
- desc: +K.28.3
- - range: 7..0
- name: BYTE
- default: 0x7C
- desc: K28.3
-
- - name: FM_EMU_CONTROL
- type: W
- bitfield:
- - range: 32
- name: EMU_ENABLE
- default: 0
- desc: Set to 1 to enable Full mode data emulator RAM
- - range: 31..16
- name: PACKAGE_COUNT
- desc: Number of packets to be sent out, 0 means infinite
- default: 0
- - range: 15..0
- name: PACKAGE_LENGTH
- desc: number of 32 bit words in one FM packet
- default: 117
-
-
-CR_GBT_CTRL:
- number: 24
- type: W
- bitfield:
- - range: 63..0
- entries:
- - ref: EGROUP_TH
- - ref: EGROUP_FH
-
-EGROUP_TH:
- number: 7
- format_name: GBT{index:02}
- entries:
- - name: TH
- desc: See Central Router Doc, indices [5,6] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - 0x000000002aaa8006
- - 0x000000002aaa8078
- - 0x000000002aaa8001
- - 0x000000002aaaff80
- - 0x000000002aaae628
- - 0x000000002aaa99d0
- - 0x0000000020004000
-
-EGROUP_FH:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FH
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - 0x0000088888888006
- - 0x0000088888888078
- - 0x0000088888888001
- - 0x000008888888ff80
- - 0x000008888888e628
- - 0x00000888888899d0
- - 0x0000080000004000
-
-
-IC_FIFOS:
- number: 24
- format_name: FH_TH_IC_FIFOS
- entries:
- - name: FH
- format_name: FH_IC_FIFO_{index:02}
- type_name: FH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.FH_IC_FIFO_{index:02}.FULL
- name: WE
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TH
- format_name: TH_IC_FIFO_{index:02}
- type_name: TH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.TH_IC_FIFO_{index:02}.EMPTY
- name: RE
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- bitfield:
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- bitfield:
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
- - name: TTC_TOHOST
- format_name: TTC_TOHOST_{index:02}
- type_name: TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 0
- default: 0x0
-
-TTC_FANOUT_CTRL:
- number: 24
- format_name: TTC_FANOUT_CTRLS
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Configures the FromHost TTC pipeline in the fanout selector
- type: W
- bitfield:
- - range: 3..0
- default: 0
-
-CentralRouterMonitors:
- group: CRM
- desc: Central Router Monitors
- endpoints: 0,1
- entries:
- - ref: CR_GBT_MON
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA
- - ref: CR_DEFAULT_EPROC_ENCODING
- - ref: TTC_BUSY_ACCEPTED
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 31..0
- desc: read emu ram data
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0,1
- number: 24
- bitfield:
- - range: 63..0
- entries:
- - name: TH
- format_name: CR_{name}_GBT{index:02}_MON
- - name: FH
- format_name: CR_{name}_GBT{index:02}_MON
-
-CR_DEFAULT_EPROC_ENA:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 14..0
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
-
-CR_DEFAULT_EPROC_ENCODING:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 15..0
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
-
-TTC_BUSY_ACCEPTED:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- bitfield:
- - range: 56..0
- entries:
- - name: BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_LOGIC_RESET
- offset: 0x0400
- bitfield:
- - range: 63..0
- desc: Not internally connected (?)
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE
- offset: 0x0480
- bitfield:
- - range: 59..48
- name: S2312
- desc: RxSlide select [23:12]
- - range: 43..32
- name: S1100
- desc: RxSlide select [11:0]
- - range: 27..16
- name: M2312
- desc: RxSlide manual [23:12]
- - range: 11..0
- name: M1100
- desc: RxSlide manual [11:0]
-
- - name: GBT_TXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: TxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: TxUsrRdy [11:0]
-
- - name: GBT_RXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: RxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: RxUsrRdy [11:0]
-
- - name: GBT_GTTX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: GTTX_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: GTTX_RESET [11:0]
-
- - name: GBT_GTRX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: GTRX_RESET [23:12]
- - range: 11..0
- name: B1100
- desc: GTRX_RESET [11:0]
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL_RESET [11:0]
-
- - name: GBT_SOFT_TX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_TX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_TX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_TX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_TX_RESET_GT [11:0]
-
- - name: GBT_SOFT_RX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_RX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_RX_RESET_GT [11:0]
-
- - name: GBT_ODD_EVEN
- offset: 0x0500
- bitfield:
- - range: 27..16
- name: B2312
- desc: OddEven [23:12]
- - range: 11..0
- name: B1100
- desc: OddEven [11:0]
-
- - name: GBT_TOPBOT
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot [11:0]
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: TX_OPT
-
- - name: GBT_RX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: RX_OPT
-
- - name: GBT_DATA_TXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_TXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_TXFORMAT [23:0]
-
- - name: GBT_DATA_RXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_RXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_RXFORMAT [23:0]
-
- - name: GBT_TX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: TX Logic reset [11:0]
-
- - name: GBT_RX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: RX Logic reset [11:0]
-
- - name: GBT_TX_TC_METHOD
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX time domain crossing method [23:12]
- - range: 11..0
- name: B1100
- desc: TX time domain crossing method [11:0]
-
- - name: GBT_OUTMUX_SEL
- bitfield:
- - range: 27..16
- name: B2312
- desc: Descrambler output MUX selection [23:12]
- - range: 11..0
- name: B1100
- desc: Descrambler output MUX selection [11:0]
-
- - name: GBT_TC_EDGE
- bitfield:
- - range: 27..16
- name: B2312
- desc: Sampling edge selection for TX domain crossing [23:12]
- - range: 11..0
- name: B1100
- desc: Sampling edge selection for TX domain crossing [11:0]
-
- - name: GBT_TRANSCEIVER_POLARITY
- bitfield:
- - range: 47..24
- name: TXPOLARITY
- desc: "0: default polarity, 1: reversed polarity for transmitter of GTH channels"
- default: 0
- - range: 23..0
- name: RXPOLARITY
- desc: "0: default polarity, 1: reversed polarity for the receiver of the GTH channels"
- default: 0
-
- - name: GBT_DNLNK_FO_SEL
- offset: 0x0600
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_UPLNK_FO_SEL
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX Reset done [11:0]
-
- - name: GBT_RXRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX Reset done [11:0]
-
- - name: GBT_TXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX FSM Reset done [11:0]
-
- - name: GBT_RXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX FSM Reset done [11:0]
-
- - name: GBT_CPLL_FBCLK_LOST
- bitfield:
- - range: 27..16
- name: B2312
- desc: CPLL FBCLK LOST [23:12]
- - range: 11..0
- name: B1100
- desc: CPLL FBCLK LOST [11:0]
-
- - name: GBT_CPLL_LOCK
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL LOCK [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL LOCK [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL LOCK [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL LOCK [11:0]
-
- - name: GBT_RXCDR_LOCK
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX CDR LOCK [23:12]
- - range: 11..0
- name: B1100
- desc: RX CDR LOCK [11:0]
-
- - name: GBT_CLK_SAMPLED
- bitfield:
- - range: 27..16
- name: B2312
- desc: clk sampled [23:12]
- - range: 11..0
- name: B1100
- desc: clk sampled [11:0]
-
- - name: GBT_RX_IS_HEADER
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS HEADER [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS HEADER [11:0]
-
- - name: GBT_RX_IS_DATA
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS DATA [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS DATA [11:0]
-
- - name: GBT_RX_HEADER_FOUND
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX HEADER FOUND [23:12]
- - range: 11..0
- name: B1100
- desc: RX HEADER FOUND [11:0]
-
- - name: GBT_ALIGNMENT_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX ALIGNMENT DONE [23:12]
- - range: 11..0
- name: B1100
- desc: RX ALIGNMENT DONE [11:0]
-
- - name: GBT_OUT_MUX_STATUS
- bitfield:
- - range: 27..16
- name: B2312
- desc: GBT output mux status [23:12]
- - range: 11..0
- name: B1100
- desc: GBT output mux status [11:0]
-
- - name: GBT_ERROR
- bitfield:
- - range: 27..16
- name: B2312
- desc: Error flags [23:12]
- - range: 11..0
- name: B1100
- desc: Error flags [11:0]
-
- - name: GBT_GBT_TOPBOT_C
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot_c [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot_c [11:0]
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
- - name: HK_CTRL_CDCE
- offset: 0x0200
- type: W
- bitfield:
- - range: 2
- name: REF_SEL
- desc: REF_SEL
- - range: 1
- name: PD
- desc: PD
- - range: 0
- name: SYNC
- desc: SYNC
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_FORCE
- default: 0x1
- desc: force the use of the Local Clock in any circumstance, overrule automatic clock switch
- - range: 2
- type: R
- name: AUTOMATIC_CLOCK_SWITCH_ENABLED
- desc: 1 when the automatic clock switch is enabled in the design
- - range: 1
- type: R
- name: OSC_SEL
- desc: |
- Main MMCM Oscillator Select
- 1: TTC clock
- 0: Local clock
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: HK_MON
- bitfield:
- - range: 1
- name: CDCE_PLL_LOCK
- desc: CDCE_PLL_LOCK
- - range: 0
- name: I2C_ACK_ERROR
- desc: i2c_ack_error
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL711 locked
- - endpoints: 0,1
- name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
- - endpoints: 0,1
- name: FPGA_ENDPOINT
- type: R
- bitfield:
- - range: 0
- desc: Endpoint of the FPGA
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_2
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#2
-
- - name: INT_TEST_3
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#3
-
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
diff --git a/sources/templates/yaml/registers-3.5.yaml b/sources/templates/yaml/registers-3.5.yaml
deleted file mode 100644
index 34791ebe2f5d24146be392d146101c5e70be510f..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-3.5.yaml
+++ /dev/null
@@ -1,1617 +0,0 @@
-Registers:
- version: '3.4'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: RD_POINTER
- desc: PC Read Pointer
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: READ_WRITE
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: CURRENT_ADDRESS
- desc: Current Address
-
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 8
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControls
- offset: 0x1000
- - ref: CentralRouterMonitors
- offset: 0x3000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x4000
- - ref: GBTWrapperControls
- offset: 0x5000
- - ref: GBTWrapperMonitors
- offset: 0x6000
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x7000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC709
- - 710 (0x2c6): HTG710
- - 711 (0x2c7): BNL711
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - name: INCLUDE_EPROC16
- type: R
- bitfield:
- - range: 7
- name: FRHOEPROC2
- desc: FromHost EPROC2 is included in Central Router
- - range: 6
- name: FRHOEPROC4
- desc: FromHost EPROC4 is included in Central Router
- - range: 5
- name: FRHOEPROC8
- desc: FromHost EPROC8 is included in Central Router
- - range: 4
- name: FRHOEPROC16
- desc: FromHost EPROC16 is included in Central Router
- - range: 3
- name: TOHOEPROC2
- desc: ToHost EPROC2 is included in Central Router
- - range: 2
- name: TOHOEPROC4
- desc: ToHost EPROC4 is included in Central Router
- - range: 1
- name: TOHOEPROC8
- desc: ToHost EPROC8 is included in Central Router
- - range: 0
- name: TOHOEPROC16
- desc: ToHost EPROC16 is included in Central Router
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
-
-CentralRouterControls:
- group: CRC
- desc: Central Router Controls
- endpoints: 0,1
- entries:
- - name: CR_TH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: CR_FH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: FH_IC_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - ref: TTC_FANOUT_CTRL
- desc: Controls the TTC Fanout delay values
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the busy or Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
- - name: COMMA_CHAR
- desc: Idle character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0FA
- desc: -K.28.5
- - range: 17..8
- name: P
- default: 0x305
- desc: +K.28.5
- - range: 7..0
- name: BYTE
- default: 0xBC
- desc: K28.5
-
- - name: SOC_CHAR
- desc: Start of chunk character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F9
- desc: -K.28.1
- - range: 17..8
- name: P
- default: 0x306
- desc: +K.28.1
- - range: 7..0
- name: BYTE
- default: 0x3C
- desc: K28.1
-
- - name: EOC_CHAR
- desc: End of chunk character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F6
- desc: -K.28.6
- - range: 17..8
- name: P
- default: 0x309
- desc: +K.28.6
- - range: 7..0
- name: BYTE
- default: 0xDC
- desc: K28.6
-
- - name: SOB_CHAR
- desc: Start of busy character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F5
- desc: -K.28.2
- - range: 17..8
- name: P
- default: 0x30A
- desc: +K.28.2
- - range: 7..0
- name: BYTE
- default: 0x5C
- desc: K28.2
-
- - name: EOB_CHAR
- desc: End of busy character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F3
- desc: -K.28.3
- - range: 17..8
- name: P
- default: 0x30C
- desc: +K.28.3
- - range: 7..0
- name: BYTE
- default: 0x7C
- desc: K28.3
-
- - name: FM_EMU_CONTROL
- type: W
- bitfield:
- - range: 32
- name: EMU_ENABLE
- default: 0
- desc: Set to 1 to enable Full mode data emulator RAM
- - range: 31..16
- name: PACKAGE_COUNT
- desc: Number of packets to be sent out, 0 means infinite
- default: 0
- - range: 15..0
- name: PACKAGE_LENGTH
- desc: number of 32 bit words in one FM packet
- default: 117
-
-
-CR_GBT_CTRL:
- number: 24
- type: W
- bitfield:
- - range: 63..0
- entries:
- - ref: EGROUP_TH
- - ref: EGROUP_FH
-
-EGROUP_TH:
- number: 7
- format_name: GBT{index:02}
- entries:
- - name: TH
- desc: See Central Router Doc, indices [5,6] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - CR_TH_EGROUP0_CTRL_C
- - CR_TH_EGROUP1_CTRL_C
- - CR_TH_EGROUP2_CTRL_C
- - CR_TH_EGROUP3_CTRL_C
- - CR_TH_EGROUP4_CTRL_C
- - CR_TH_EGROUP5_CTRL_C
- - CR_TH_EGROUP6_CTRL_C
-
-EGROUP_FH:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FH
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - CR_FH_EGROUP0_CTRL_C
- - CR_FH_EGROUP1_CTRL_C
- - CR_FH_EGROUP2_CTRL_C
- - CR_FH_EGROUP3_CTRL_C
- - CR_FH_EGROUP4_CTRL_C
- - CR_FH_EGROUP5_CTRL_C
- - CR_FH_EGROUP6_CTRL_C
-
-
-IC_FIFOS:
- number: 24
- format_name: FH_TH_IC_FIFOS
- entries:
- - name: FH
- format_name: FH_IC_FIFO_{index:02}
- type_name: FH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.FH_IC_FIFO_{index:02}.FULL
- name: WE
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TH
- format_name: TH_IC_FIFO_{index:02}
- type_name: TH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.TH_IC_FIFO_{index:02}.EMPTY
- name: RE
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- bitfield:
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- bitfield:
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
- - name: TTC_TOHOST
- format_name: TTC_TOHOST_{index:02}
- type_name: TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 0
- default: 0x0
-
-TTC_FANOUT_CTRL:
- number: 24
- format_name: TTC_FANOUT_CTRLS
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Configures the FromHost TTC pipeline in the fanout selector
- type: W
- bitfield:
- - range: 3..0
- default: 0
-
-CentralRouterMonitors:
- group: CRM
- desc: Central Router Monitors
- endpoints: 0,1
- entries:
- - ref: CR_GBT_MON
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA
- - ref: CR_DEFAULT_EPROC_ENCODING
- - ref: TTC_BUSY_ACCEPTED
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 31..0
- desc: read emu ram data
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0,1
- number: 24
- bitfield:
- - range: 63..0
- entries:
- - name: TH
- format_name: CR_{name}_GBT{index:02}_MON
- - name: FH
- format_name: CR_{name}_GBT{index:02}_MON
-
-CR_DEFAULT_EPROC_ENA:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 14..0
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
-
-CR_DEFAULT_EPROC_ENCODING:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 15..0
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
-
-TTC_BUSY_ACCEPTED:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- bitfield:
- - range: 56..0
- entries:
- - name: BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_LOGIC_RESET
- offset: 0x0400
- bitfield:
- - range: 63..0
- desc: Not internally connected (?)
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE
- offset: 0x0480
- bitfield:
- - range: 59..48
- name: S2312
- desc: RxSlide select [23:12]
- - range: 43..32
- name: S1100
- desc: RxSlide select [11:0]
- - range: 27..16
- name: M2312
- desc: RxSlide manual [23:12]
- - range: 11..0
- name: M1100
- desc: RxSlide manual [11:0]
-
- - name: GBT_TXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: TxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: TxUsrRdy [11:0]
-
- - name: GBT_RXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: RxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: RxUsrRdy [11:0]
-
- - name: GBT_GTTX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: GTTX_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: GTTX_RESET [11:0]
-
- - name: GBT_GTRX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: GTRX_RESET [23:12]
- - range: 11..0
- name: B1100
- desc: GTRX_RESET [11:0]
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL_RESET [11:0]
-
- - name: GBT_SOFT_TX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_TX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_TX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_TX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_TX_RESET_GT [11:0]
-
- - name: GBT_SOFT_RX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_RX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_RX_RESET_GT [11:0]
-
- - name: GBT_ODD_EVEN
- offset: 0x0500
- bitfield:
- - range: 27..16
- name: B2312
- desc: OddEven [23:12]
- - range: 11..0
- name: B1100
- desc: OddEven [11:0]
-
- - name: GBT_TOPBOT
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot [11:0]
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: TX_OPT
-
- - name: GBT_RX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: RX_OPT
-
- - name: GBT_DATA_TXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_TXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_TXFORMAT [23:0]
-
- - name: GBT_DATA_RXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_RXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_RXFORMAT [23:0]
-
- - name: GBT_TX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: TX Logic reset [11:0]
-
- - name: GBT_RX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: RX Logic reset [11:0]
-
- - name: GBT_TX_TC_METHOD
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX time domain crossing method [23:12]
- - range: 11..0
- name: B1100
- desc: TX time domain crossing method [11:0]
-
- - name: GBT_OUTMUX_SEL
- bitfield:
- - range: 27..16
- name: B2312
- desc: Descrambler output MUX selection [23:12]
- - range: 11..0
- name: B1100
- desc: Descrambler output MUX selection [11:0]
-
- - name: GBT_TC_EDGE
- bitfield:
- - range: 27..16
- name: B2312
- desc: Sampling edge selection for TX domain crossing [23:12]
- - range: 11..0
- name: B1100
- desc: Sampling edge selection for TX domain crossing [11:0]
-
- - name: GBT_TRANSCEIVER_POLARITY
- bitfield:
- - range: 47..24
- name: TXPOLARITY
- desc: "0: default polarity, 1: reversed polarity for transmitter of GTH channels"
- default: 0
- - range: 23..0
- name: RXPOLARITY
- desc: "0: default polarity, 1: reversed polarity for the receiver of the GTH channels"
- default: 0
-
- - name: GBT_DNLNK_FO_SEL
- offset: 0x0600
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_UPLNK_FO_SEL
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX Reset done [11:0]
-
- - name: GBT_RXRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX Reset done [11:0]
-
- - name: GBT_TXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX FSM Reset done [11:0]
-
- - name: GBT_RXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX FSM Reset done [11:0]
-
- - name: GBT_CPLL_FBCLK_LOST
- bitfield:
- - range: 27..16
- name: B2312
- desc: CPLL FBCLK LOST [23:12]
- - range: 11..0
- name: B1100
- desc: CPLL FBCLK LOST [11:0]
-
- - name: GBT_CPLL_LOCK
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL LOCK [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL LOCK [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL LOCK [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL LOCK [11:0]
-
- - name: GBT_RXCDR_LOCK
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX CDR LOCK [23:12]
- - range: 11..0
- name: B1100
- desc: RX CDR LOCK [11:0]
-
- - name: GBT_CLK_SAMPLED
- bitfield:
- - range: 27..16
- name: B2312
- desc: clk sampled [23:12]
- - range: 11..0
- name: B1100
- desc: clk sampled [11:0]
-
- - name: GBT_RX_IS_HEADER
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS HEADER [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS HEADER [11:0]
-
- - name: GBT_RX_IS_DATA
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS DATA [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS DATA [11:0]
-
- - name: GBT_RX_HEADER_FOUND
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX HEADER FOUND [23:12]
- - range: 11..0
- name: B1100
- desc: RX HEADER FOUND [11:0]
-
- - name: GBT_ALIGNMENT_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX ALIGNMENT DONE [23:12]
- - range: 11..0
- name: B1100
- desc: RX ALIGNMENT DONE [11:0]
-
- - name: GBT_OUT_MUX_STATUS
- bitfield:
- - range: 27..16
- name: B2312
- desc: GBT output mux status [23:12]
- - range: 11..0
- name: B1100
- desc: GBT output mux status [11:0]
-
- - name: GBT_ERROR
- bitfield:
- - range: 27..16
- name: B2312
- desc: Error flags [23:12]
- - range: 11..0
- name: B1100
- desc: Error flags [11:0]
-
- - name: GBT_GBT_TOPBOT_C
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot_c [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot_c [11:0]
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
- - name: HK_CTRL_CDCE
- offset: 0x0200
- type: W
- bitfield:
- - range: 2
- name: REF_SEL
- desc: REF_SEL
- - range: 1
- name: PD
- desc: PD
- - range: 0
- name: SYNC
- desc: SYNC
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_FORCE
- default: 0x1
- desc: force the use of the Local Clock in any circumstance, overrule automatic clock switch
- - range: 2
- type: R
- name: AUTOMATIC_CLOCK_SWITCH_ENABLED
- desc: 1 when the automatic clock switch is enabled in the design
- - range: 1
- type: R
- name: OSC_SEL
- desc: |
- Main MMCM Oscillator Select
- 1: TTC clock
- 0: Local clock
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: HK_MON
- bitfield:
- - range: 1
- name: CDCE_PLL_LOCK
- desc: CDCE_PLL_LOCK
- - range: 0
- name: I2C_ACK_ERROR
- desc: i2c_ack_error
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL711 locked
- - endpoints: 0,1
- name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
- - endpoints: 0,1
- name: FPGA_ENDPOINT
- type: R
- bitfield:
- - range: 0
- desc: Endpoint of the FPGA
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_2
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#2
-
- - name: INT_TEST_3
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#3
-
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
diff --git a/sources/templates/yaml/registers-3.6.yaml b/sources/templates/yaml/registers-3.6.yaml
deleted file mode 100644
index 36a65889eb177c6ecd08140b06cfad03b5cadb73..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-3.6.yaml
+++ /dev/null
@@ -1,1675 +0,0 @@
-Registers:
- version: '3.6'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: RD_POINTER
- desc: PC Read Pointer
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: READ_WRITE
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: CURRENT_ADDRESS
- desc: Current Address
-
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 8
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControls
- offset: 0x1000
- - ref: CentralRouterMonitors
- offset: 0x3000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x4000
- - ref: GBTWrapperControls
- offset: 0x5000
- - ref: GBTWrapperMonitors
- offset: 0x6000
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x7000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC709
- - 710 (0x2c6): HTG710
- - 711 (0x2c7): BNL711
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - name: INCLUDE_EPROC16
- type: R
- bitfield:
- - range: 7
- name: FRHOEPROC2
- desc: FromHost EPROC2 is included in Central Router
- - range: 6
- name: FRHOEPROC4
- desc: FromHost EPROC4 is included in Central Router
- - range: 5
- name: FRHOEPROC8
- desc: FromHost EPROC8 is included in Central Router
- - range: 4
- name: FRHOEPROC16
- desc: FromHost EPROC16 is included in Central Router
- - range: 3
- name: TOHOEPROC2
- desc: ToHost EPROC2 is included in Central Router
- - range: 2
- name: TOHOEPROC4
- desc: ToHost EPROC4 is included in Central Router
- - range: 1
- name: TOHOEPROC8
- desc: ToHost EPROC8 is included in Central Router
- - range: 0
- name: TOHOEPROC16
- desc: ToHost EPROC16 is included in Central Router
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
-
-CentralRouterControls:
- group: CRC
- desc: Central Router Controls
- endpoints: 0,1
- entries:
- - name: CR_TH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: CR_FH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: FH_IC_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - ref: TTC_FANOUT_CTRL
- desc: Controls the TTC Fanout delay values
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the busy or Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
- - name: COMMA_CHAR
- desc: Idle character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0FA
- desc: -K.28.5
- - range: 17..8
- name: P
- default: 0x305
- desc: +K.28.5
- - range: 7..0
- name: BYTE
- default: 0xBC
- desc: K28.5
-
- - name: SOC_CHAR
- desc: Start of chunk character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F9
- desc: -K.28.1
- - range: 17..8
- name: P
- default: 0x306
- desc: +K.28.1
- - range: 7..0
- name: BYTE
- default: 0x3C
- desc: K28.1
-
- - name: EOC_CHAR
- desc: End of chunk character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F6
- desc: -K.28.6
- - range: 17..8
- name: P
- default: 0x309
- desc: +K.28.6
- - range: 7..0
- name: BYTE
- default: 0xDC
- desc: K28.6
-
- - name: SOB_CHAR
- desc: Start of busy character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F5
- desc: -K.28.2
- - range: 17..8
- name: P
- default: 0x30A
- desc: +K.28.2
- - range: 7..0
- name: BYTE
- default: 0x5C
- desc: K28.2
-
- - name: EOB_CHAR
- desc: End of busy character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F3
- desc: -K.28.3
- - range: 17..8
- name: P
- default: 0x30C
- desc: +K.28.3
- - range: 7..0
- name: BYTE
- default: 0x7C
- desc: K28.3
-
-
-
- - name: FM_EMU_CONTROL1
- type: W
- bitfield:
- - range: 63..32
- name: TIMESTAMP_INIT
- desc: Init value for the timestamp
- default: 0
- - range: 31..16
- name: PACKAGE_COUNT
- desc: Number of packets to be sent out, 0 means infinite
- default: 0
- - range: 15..0
- name: PACKAGE_LENGTH
- desc: number of 32 bit words in one FM packet
- default: 117
-
- - name: FM_EMU_CONTROL2
- type: W
- bitfield:
- - range: 16
- name: EMU_ENABLE
- default: 0
- desc: Set to 1 to enable Full mode data emulator RAM
- - range: 15..0
- name: TIMESTAMP_INCR
- desc: Timestamp increment for each sent package
- default: 1
-
-CR_GBT_CTRL:
- number: 24
- type: W
- bitfield:
- - range: 63..0
- entries:
- - ref: EGROUP_TH
- - ref: EGROUP_FH
-
-EGROUP_TH:
- number: 7
- format_name: GBT{index:02}
- entries:
- - name: TH
- desc: See Central Router Doc, indices [5,6] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - 0x000000002aaa8006
- - 0x000000002aaa8078
- - 0x000000002aaa8001
- - 0x000000002aaaff80
- - 0x000000002aaae628
- - 0x000000002aaa99d0
- - 0x0000000020004000
-
-EGROUP_FH:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FH
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - 0x0000088888888006
- - 0x0000088888888078
- - 0x0000088888888001
- - 0x000008888888ff80
- - 0x000008888888e628
- - 0x00000888888899d0
- - 0x0000080000004000
-
-
-IC_FIFOS:
- number: 24
- format_name: FH_TH_IC_FIFOS
- entries:
- - name: FH
- format_name: FH_IC_FIFO_{index:02}
- type_name: FH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.FH_IC_FIFO_{index:02}.FULL
- name: WE
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TH
- format_name: TH_IC_FIFO_{index:02}
- type_name: TH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.TH_IC_FIFO_{index:02}.EMPTY
- name: RE
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- bitfield:
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- bitfield:
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
- - name: TTC_TOHOST
- format_name: TTC_TOHOST_{index:02}
- type_name: TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
-TTC_FANOUT_CTRL:
- number: 24
- format_name: TTC_FANOUT_CTRLS
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Configures the FromHost TTC pipeline in the fanout selector
- type: W
- bitfield:
- - range: 3..0
- default: 0
-
-CentralRouterMonitors:
- group: CRM
- desc: Central Router Monitors
- endpoints: 0,1
- entries:
- - ref: CR_GBT_MON
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA
- - ref: CR_DEFAULT_EPROC_ENCODING
- - ref: TTC_BUSY_ACCEPTED
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 31..0
- desc: read emu ram data
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0,1
- number: 24
- bitfield:
- - range: 63..0
- entries:
- - name: TH
- format_name: CR_{name}_GBT{index:02}_MON
- - name: FH
- format_name: CR_{name}_GBT{index:02}_MON
-
-CR_DEFAULT_EPROC_ENA:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 14..0
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
-
-CR_DEFAULT_EPROC_ENCODING:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 15..0
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
-
-TTC_BUSY_ACCEPTED:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- bitfield:
- - range: 56..0
- entries:
- - name: BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_LOGIC_RESET
- offset: 0x0400
- bitfield:
- - range: 63..0
- desc: Not internally connected (?)
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE
- offset: 0x0480
- bitfield:
- - range: 59..48
- name: S2312
- desc: RxSlide select [23:12]
- - range: 43..32
- name: S1100
- desc: RxSlide select [11:0]
- - range: 27..16
- name: M2312
- desc: RxSlide manual [23:12]
- - range: 11..0
- name: M1100
- desc: RxSlide manual [11:0]
-
- - name: GBT_TXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: TxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: TxUsrRdy [11:0]
-
- - name: GBT_RXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: RxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: RxUsrRdy [11:0]
-
- - name: GBT_GTTX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: GTTX_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: GTTX_RESET [11:0]
-
- - name: GBT_GTRX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: GTRX_RESET [23:12]
- - range: 11..0
- name: B1100
- desc: GTRX_RESET [11:0]
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL_RESET [11:0]
-
- - name: GBT_SOFT_TX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_TX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_TX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_TX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_TX_RESET_GT [11:0]
-
- - name: GBT_SOFT_RX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_RX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_RX_RESET_GT [11:0]
-
- - name: GBT_ODD_EVEN
- offset: 0x0500
- bitfield:
- - range: 27..16
- name: B2312
- desc: OddEven [23:12]
- - range: 11..0
- name: B1100
- desc: OddEven [11:0]
-
- - name: GBT_TOPBOT
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot [11:0]
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: TX_OPT
-
- - name: GBT_RX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: RX_OPT
-
- - name: GBT_DATA_TXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_TXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_TXFORMAT [23:0]
-
- - name: GBT_DATA_RXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_RXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_RXFORMAT [23:0]
-
- - name: GBT_TX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: TX Logic reset [11:0]
-
- - name: GBT_RX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: RX Logic reset [11:0]
-
- - name: GBT_TX_TC_METHOD
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX time domain crossing method [23:12]
- - range: 11..0
- name: B1100
- desc: TX time domain crossing method [11:0]
-
- - name: GBT_OUTMUX_SEL
- bitfield:
- - range: 27..16
- name: B2312
- desc: Descrambler output MUX selection [23:12]
- - range: 11..0
- name: B1100
- desc: Descrambler output MUX selection [11:0]
-
- - name: GBT_TC_EDGE
- bitfield:
- - range: 27..16
- name: B2312
- desc: Sampling edge selection for TX domain crossing [23:12]
- - range: 11..0
- name: B1100
- desc: Sampling edge selection for TX domain crossing [11:0]
-
- - name: GBT_TRANSCEIVER_POLARITY
- bitfield:
- - range: 47..24
- name: TXPOLARITY
- desc: "0: default polarity, 1: reversed polarity for transmitter of GTH channels"
- default: 0
- - range: 23..0
- name: RXPOLARITY
- desc: "0: default polarity, 1: reversed polarity for the receiver of the GTH channels"
- default: 0
-
- - name: GBT_DNLNK_FO_SEL
- offset: 0x0600
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_UPLNK_FO_SEL
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX Reset done [11:0]
-
- - name: GBT_RXRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX Reset done [11:0]
-
- - name: GBT_TXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX FSM Reset done [11:0]
-
- - name: GBT_RXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX FSM Reset done [11:0]
-
- - name: GBT_CPLL_FBCLK_LOST
- bitfield:
- - range: 27..16
- name: B2312
- desc: CPLL FBCLK LOST [23:12]
- - range: 11..0
- name: B1100
- desc: CPLL FBCLK LOST [11:0]
-
- - name: GBT_CPLL_LOCK
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL LOCK [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL LOCK [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL LOCK [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL LOCK [11:0]
-
- - name: GBT_RXCDR_LOCK
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX CDR LOCK [23:12]
- - range: 11..0
- name: B1100
- desc: RX CDR LOCK [11:0]
-
- - name: GBT_CLK_SAMPLED
- bitfield:
- - range: 27..16
- name: B2312
- desc: clk sampled [23:12]
- - range: 11..0
- name: B1100
- desc: clk sampled [11:0]
-
- - name: GBT_RX_IS_HEADER
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS HEADER [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS HEADER [11:0]
-
- - name: GBT_RX_IS_DATA
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS DATA [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS DATA [11:0]
-
- - name: GBT_RX_HEADER_FOUND
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX HEADER FOUND [23:12]
- - range: 11..0
- name: B1100
- desc: RX HEADER FOUND [11:0]
-
- - name: GBT_ALIGNMENT_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX ALIGNMENT DONE [23:12]
- - range: 11..0
- name: B1100
- desc: RX ALIGNMENT DONE [11:0]
-
- - name: GBT_OUT_MUX_STATUS
- bitfield:
- - range: 27..16
- name: B2312
- desc: GBT output mux status [23:12]
- - range: 11..0
- name: B1100
- desc: GBT output mux status [11:0]
-
- - name: GBT_ERROR
- bitfield:
- - range: 27..16
- name: B2312
- desc: Error flags [23:12]
- - range: 11..0
- name: B1100
- desc: Error flags [11:0]
-
- - name: GBT_GBT_TOPBOT_C
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot_c [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot_c [11:0]
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
- - name: HK_CTRL_CDCE
- offset: 0x0200
- type: W
- bitfield:
- - range: 2
- name: REF_SEL
- desc: REF_SEL
- - range: 1
- name: PD
- desc: PD
- - range: 0
- name: SYNC
- desc: SYNC
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_FORCE
- default: 0x1
- desc: force the use of the Local Clock in any circumstance, overrule automatic clock switch
- - range: 2
- type: R
- name: AUTOMATIC_CLOCK_SWITCH_ENABLED
- desc: 1 when the automatic clock switch is enabled in the design
- - range: 1
- type: R
- name: OSC_SEL
- desc: |
- Main MMCM Oscillator Select
- 1: TTC clock
- 0: Local clock
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: HK_MON
- bitfield:
- - range: 1
- name: CDCE_PLL_LOCK
- desc: CDCE_PLL_LOCK
- - range: 0
- name: I2C_ACK_ERROR
- desc: i2c_ack_error
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL711 locked
- - endpoints: 0,1
- name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
- - endpoints: 0,1
- name: FPGA_ENDPOINT
- type: R
- bitfield:
- - range: 0
- desc: Endpoint of the FPGA
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_2
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#2
-
- - name: INT_TEST_3
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#3
-
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
diff --git a/sources/templates/yaml/registers-3.7.yaml b/sources/templates/yaml/registers-3.7.yaml
deleted file mode 100644
index ee1fdf6f147ec827b5f20acefc1240e21ef40656..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-3.7.yaml
+++ /dev/null
@@ -1,1725 +0,0 @@
-Registers:
- version: '3.7'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: RD_POINTER
- desc: PC Read Pointer
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: READ_WRITE
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: CURRENT_ADDRESS
- desc: Current Address
-
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 8
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x4000
- - ref: GBTWrapperControls
- offset: 0x5000
- - ref: GBTWrapperMonitors
- offset: 0x6000
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x7000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC709
- - 710 (0x2c6): HTG710
- - 711 (0x2c7): BNL711
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - name: INCLUDE_EPROC16
- type: R
- bitfield:
- - range: 7
- name: FRHOEPROC2
- desc: FromHost EPROC2 is included in Central Router
- - range: 6
- name: FRHOEPROC4
- desc: FromHost EPROC4 is included in Central Router
- - range: 5
- name: FRHOEPROC8
- desc: FromHost EPROC8 is included in Central Router
- - range: 4
- name: FRHOEPROC16
- desc: FromHost EPROC16 is included in Central Router
- - range: 3
- name: TOHOEPROC2
- desc: ToHost EPROC2 is included in Central Router
- - range: 2
- name: TOHOEPROC4
- desc: ToHost EPROC4 is included in Central Router
- - range: 1
- name: TOHOEPROC8
- desc: ToHost EPROC8 is included in Central Router
- - range: 0
- name: TOHOEPROC16
- desc: ToHost EPROC16 is included in Central Router
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: CR_TH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: CR_FH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: FH_IC_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - ref: TTC_FANOUT_CTRL
- desc: Controls the TTC Fanout delay values
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the busy or Logic
- type: W
- bitfield:
- - range: 52
- name: BUSY_SW_ONOFF
- default: 0
- desc: Insert busy signal from software side
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
- - name: COMMA_CHAR
- desc: Idle character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0FA
- desc: -K.28.5
- - range: 17..8
- name: P
- default: 0x305
- desc: +K.28.5
- - range: 7..0
- name: BYTE
- default: 0xBC
- desc: K28.5
-
- - name: SOC_CHAR
- desc: Start of chunk character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F9
- desc: -K.28.1
- - range: 17..8
- name: P
- default: 0x306
- desc: +K.28.1
- - range: 7..0
- name: BYTE
- default: 0x3C
- desc: K28.1
-
- - name: EOC_CHAR
- desc: End of chunk character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F6
- desc: -K.28.6
- - range: 17..8
- name: P
- default: 0x309
- desc: +K.28.6
- - range: 7..0
- name: BYTE
- default: 0xDC
- desc: K28.6
-
- - name: SOB_CHAR
- desc: Start of busy character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F5
- desc: -K.28.2
- - range: 17..8
- name: P
- default: 0x30A
- desc: +K.28.2
- - range: 7..0
- name: BYTE
- default: 0x5C
- desc: K28.2
-
- - name: EOB_CHAR
- desc: End of busy character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F3
- desc: -K.28.3
- - range: 17..8
- name: P
- default: 0x30C
- desc: +K.28.3
- - range: 7..0
- name: BYTE
- default: 0x7C
- desc: K28.3
-
-
-
- - name: FM_EMU_CONTROL1
- type: W
- bitfield:
- - range: 63..32
- name: TIMESTAMP_INIT
- desc: Init value for the timestamp
- default: 0
- - range: 31..16
- name: PACKAGE_COUNT
- desc: Number of packets to be sent out, 0xFFFF means infinite
- default: 0
- - range: 15..0
- name: PACKAGE_LENGTH
- desc: number of 32 bit words in one FM packet
- default: 120
-
- - name: TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - name: FM_EMU_CONTROL2
- type: W
- bitfield:
- - range: 16
- name: EMU_ENABLE
- default: 0
- desc: Set to 1 to enable Full mode data emulator RAM
- - range: 15..0
- name: TIMESTAMP_INCR
- desc: Timestamp increment for each sent package
- default: 1
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x2000
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA
- - ref: CR_DEFAULT_EPROC_ENCODING
- - ref: TTC_BUSY_ACCEPTED
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 31..0
- desc: read emu ram data
-
- - ref: CR_XOFF_CTRL
- offset: 0x2800
- desc: Configure FromHost Xoff
-
-
-
-CR_GBT_CTRL:
- number: 24
- type: W
- bitfield:
- - range: 63..0
- entries:
- - ref: EGROUP_TH
- - ref: EGROUP_FH
-
-EGROUP_TH:
- number: 7
- format_name: GBT{index:02}
- entries:
- - name: TH
- desc: See Central Router Doc, indices [5,6] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - 0x000000002aaa8006
- - 0x000000002aaa8078
- - 0x000000002aaa8001
- - 0x000000002aaaff80
- - 0x000000002aaae628
- - 0x000000002aaa99d0
- - 0x0000000020004000
-
-EGROUP_FH:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FH
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - 0x0000088888888006
- - 0x0000088888888078
- - 0x0000088888888001
- - 0x000008888888ff80
- - 0x000008888888e628
- - 0x00000888888899d0
- - 0x0000080000004000
-
-CR_XOFF_CTRL:
- number: 24
- type: W
- bitfield:
- - range: 39..0
- entries:
- - name: FROMHOST_XOFF_ENABLE_{index:02}
- desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
- range: 39..0
- default: 0
- - name: FROMHOST_SOFT_XOFF_{index:02}
- desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
- range: 39..0
- default: 0
-
-
-IC_FIFOS:
- number: 24
- format_name: FH_TH_IC_FIFOS
- entries:
- - name: FH
- format_name: FH_IC_FIFO_{index:02}
- type_name: FH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.FH_IC_FIFO_{index:02}.FULL
- name: WE
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TH
- format_name: TH_IC_FIFO_{index:02}
- type_name: TH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.TH_IC_FIFO_{index:02}.EMPTY
- name: RE
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- bitfield:
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- bitfield:
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
- - name: MARK_FOR_DELETION
- format_name: MARK_FOR_DELETION_{index:02}
- type: R
- bitfield:
- - range: 0
-
-TTC_FANOUT_CTRL:
- number: 24
- format_name: TTC_FANOUT_CTRLS
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Configures the FromHost TTC pipeline in the fanout selector
- type: W
- bitfield:
- - range: 3..0
- default: 0
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0,1
- number: 24
- bitfield:
- - range: 63..0
- entries:
- - name: TH
- format_name: CR_{name}_GBT{index:02}_MON
- - name: FH
- format_name: CR_{name}_GBT{index:02}_MON
-
-CR_DEFAULT_EPROC_ENA:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 14..0
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
-
-CR_DEFAULT_EPROC_ENCODING:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 15..0
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
-
-TTC_BUSY_ACCEPTED:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- bitfield:
- - range: 56..0
- entries:
- - name: BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_LOGIC_RESET
- offset: 0x0400
- bitfield:
- - range: 63..0
- desc: Not internally connected (?)
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE
- offset: 0x0480
- bitfield:
- - range: 59..48
- name: S2312
- desc: RxSlide select [23:12]
- - range: 43..32
- name: S1100
- desc: RxSlide select [11:0]
- - range: 27..16
- name: M2312
- desc: RxSlide manual [23:12]
- - range: 11..0
- name: M1100
- desc: RxSlide manual [11:0]
-
- - name: GBT_TXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: TxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: TxUsrRdy [11:0]
-
- - name: GBT_RXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: RxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: RxUsrRdy [11:0]
-
- - name: GBT_GTTX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: GTTX_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: GTTX_RESET [11:0]
-
- - name: GBT_GTRX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: GTRX_RESET [23:12]
- - range: 11..0
- name: B1100
- desc: GTRX_RESET [11:0]
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL_RESET [11:0]
-
- - name: GBT_SOFT_TX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_TX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_TX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_TX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_TX_RESET_GT [11:0]
-
- - name: GBT_SOFT_RX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_RX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_RX_RESET_GT [11:0]
-
- - name: GBT_ODD_EVEN
- offset: 0x0500
- bitfield:
- - range: 27..16
- name: B2312
- desc: OddEven [23:12]
- - range: 11..0
- name: B1100
- desc: OddEven [11:0]
-
- - name: GBT_TOPBOT
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot [11:0]
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: TX_OPT
-
- - name: GBT_RX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: RX_OPT
-
- - name: GBT_DATA_TXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_TXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_TXFORMAT [23:0]
-
- - name: GBT_DATA_RXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_RXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_RXFORMAT [23:0]
-
- - name: GBT_TX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: TX Logic reset [11:0]
-
- - name: GBT_RX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: RX Logic reset [11:0]
-
- - name: GBT_TX_TC_METHOD
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX time domain crossing method [23:12]
- - range: 11..0
- name: B1100
- desc: TX time domain crossing method [11:0]
-
- - name: GBT_OUTMUX_SEL
- bitfield:
- - range: 27..16
- name: B2312
- desc: Descrambler output MUX selection [23:12]
- - range: 11..0
- name: B1100
- desc: Descrambler output MUX selection [11:0]
-
- - name: GBT_TC_EDGE
- bitfield:
- - range: 27..16
- name: B2312
- desc: Sampling edge selection for TX domain crossing [23:12]
- - range: 11..0
- name: B1100
- desc: Sampling edge selection for TX domain crossing [11:0]
-
- - name: GBT_TRANSCEIVER_POLARITY
- bitfield:
- - range: 47..24
- name: TXPOLARITY
- desc: "0: default polarity, 1: reversed polarity for transmitter of GTH channels"
- default: 0
- - range: 23..0
- name: RXPOLARITY
- desc: "0: default polarity, 1: reversed polarity for the receiver of the GTH channels"
- default: 0
-
- - name: GBT_DNLNK_FO_SEL
- offset: 0x0600
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_UPLNK_FO_SEL
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX Reset done [11:0]
-
- - name: GBT_RXRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX Reset done [11:0]
-
- - name: GBT_TXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX FSM Reset done [11:0]
-
- - name: GBT_RXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX FSM Reset done [11:0]
-
- - name: GBT_CPLL_FBCLK_LOST
- bitfield:
- - range: 27..16
- name: B2312
- desc: CPLL FBCLK LOST [23:12]
- - range: 11..0
- name: B1100
- desc: CPLL FBCLK LOST [11:0]
-
- - name: GBT_CPLL_LOCK
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL LOCK [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL LOCK [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL LOCK [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL LOCK [11:0]
-
- - name: GBT_RXCDR_LOCK
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX CDR LOCK [23:12]
- - range: 11..0
- name: B1100
- desc: RX CDR LOCK [11:0]
-
- - name: GBT_CLK_SAMPLED
- bitfield:
- - range: 27..16
- name: B2312
- desc: clk sampled [23:12]
- - range: 11..0
- name: B1100
- desc: clk sampled [11:0]
-
- - name: GBT_RX_IS_HEADER
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS HEADER [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS HEADER [11:0]
-
- - name: GBT_RX_IS_DATA
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS DATA [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS DATA [11:0]
-
- - name: GBT_RX_HEADER_FOUND
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX HEADER FOUND [23:12]
- - range: 11..0
- name: B1100
- desc: RX HEADER FOUND [11:0]
-
- - name: GBT_ALIGNMENT_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX ALIGNMENT DONE [23:12]
- - range: 11..0
- name: B1100
- desc: RX ALIGNMENT DONE [11:0]
-
- - name: GBT_OUT_MUX_STATUS
- bitfield:
- - range: 27..16
- name: B2312
- desc: GBT output mux status [23:12]
- - range: 11..0
- name: B1100
- desc: GBT output mux status [11:0]
-
- - name: GBT_ERROR
- bitfield:
- - range: 27..16
- name: B2312
- desc: Error flags [23:12]
- - range: 11..0
- name: B1100
- desc: Error flags [11:0]
-
- - name: GBT_GBT_TOPBOT_C
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot_c [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot_c [11:0]
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
- - name: HK_CTRL_CDCE
- offset: 0x0200
- type: W
- bitfield:
- - range: 2
- name: REF_SEL
- desc: REF_SEL
- - range: 1
- name: PD
- desc: PD
- - range: 0
- name: SYNC
- desc: SYNC
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_FORCE
- default: 0x1
- desc: force the use of the Local Clock in any circumstance, overrule automatic clock switch
- - range: 2
- type: R
- name: AUTOMATIC_CLOCK_SWITCH_ENABLED
- desc: 1 when the automatic clock switch is enabled in the design
- - range: 1
- type: R
- name: OSC_SEL
- desc: |
- Main MMCM Oscillator Select
- 1: TTC clock
- 0: Local clock
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: HK_MON
- bitfield:
- - range: 1
- name: CDCE_PLL_LOCK
- desc: CDCE_PLL_LOCK
- - range: 0
- name: I2C_ACK_ERROR
- desc: i2c_ack_error
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL711 locked
- - endpoints: 0,1
- name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
- - endpoints: 0,1
- name: FPGA_ENDPOINT
- type: R
- bitfield:
- - range: 0
- desc: Endpoint of the FPGA
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_2
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#2
-
- - name: INT_TEST_3
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#3
-
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
diff --git a/sources/templates/yaml/registers-3.8.1.yaml b/sources/templates/yaml/registers-3.8.1.yaml
deleted file mode 100644
index 0d99feca0dd1202125c82c71954bbb9addc65605..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-3.8.1.yaml
+++ /dev/null
@@ -1,1794 +0,0 @@
-Registers:
- version: '3.8.1'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: RD_POINTER
- desc: PC Read Pointer
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: READ_WRITE
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: CURRENT_ADDRESS
- desc: Current Address
-
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 8
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x4000
- - ref: GBTWrapperControls
- offset: 0x5000
- - ref: GBTWrapperMonitors
- offset: 0x6000
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x7000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC709
- - 710 (0x2c6): HTG710
- - 711 (0x2c7): BNL711
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - name: INCLUDE_EPROC16
- type: R
- bitfield:
- - range: 7
- name: FRHOEPROC2
- desc: FromHost EPROC2 is included in Central Router
- - range: 6
- name: FRHOEPROC4
- desc: FromHost EPROC4 is included in Central Router
- - range: 5
- name: FRHOEPROC8
- desc: FromHost EPROC8 is included in Central Router
- - range: 4
- name: FRHOEPROC16
- desc: FromHost EPROC16 is included in Central Router
- - range: 3
- name: TOHOEPROC2
- desc: ToHost EPROC2 is included in Central Router
- - range: 2
- name: TOHOEPROC4
- desc: ToHost EPROC4 is included in Central Router
- - range: 1
- name: TOHOEPROC8
- desc: ToHost EPROC8 is included in Central Router
- - range: 0
- name: TOHOEPROC16
- desc: ToHost EPROC16 is included in Central Router
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: CR_TH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: CR_FH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: FH_IC_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - ref: TTC_FANOUT_CTRL
- desc: Controls the TTC Fanout delay values
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the busy or Logic
- type: W
- bitfield:
- - range: 52
- name: BUSY_SW_ONOFF
- default: 0
- desc: Insert busy signal from software side
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
- - name: COMMA_CHAR
- desc: Idle character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0FA
- desc: -K.28.5
- - range: 17..8
- name: P
- default: 0x305
- desc: +K.28.5
- - range: 7..0
- name: BYTE
- default: 0xBC
- desc: K28.5
-
- - name: SOC_CHAR
- desc: Start of chunk character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F9
- desc: -K.28.1
- - range: 17..8
- name: P
- default: 0x306
- desc: +K.28.1
- - range: 7..0
- name: BYTE
- default: 0x3C
- desc: K28.1
-
- - name: EOC_CHAR
- desc: End of chunk character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F6
- desc: -K.28.6
- - range: 17..8
- name: P
- default: 0x309
- desc: +K.28.6
- - range: 7..0
- name: BYTE
- default: 0xDC
- desc: K28.6
-
- - name: SOB_CHAR
- desc: Start of busy character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F5
- desc: -K.28.2
- - range: 17..8
- name: P
- default: 0x30A
- desc: +K.28.2
- - range: 7..0
- name: BYTE
- default: 0x5C
- desc: K28.2
-
- - name: EOB_CHAR
- desc: End of busy character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F3
- desc: -K.28.3
- - range: 17..8
- name: P
- default: 0x30C
- desc: +K.28.3
- - range: 7..0
- name: BYTE
- default: 0x7C
- desc: K28.3
-
-
-
- - name: FM_EMU_CONTROL1
- type: W
- bitfield:
- - range: 63..32
- name: TIMESTAMP_INIT
- desc: Init value for the timestamp
- default: 0
- - range: 31..16
- name: PACKAGE_COUNT
- desc: Number of packets to be sent out, 0xFFFF means infinite
- default: 0
- - range: 15..0
- name: PACKAGE_LENGTH
- desc: number of 32 bit words in one FM packet
- default: 120
-
- - name: TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - name: FM_EMU_CONTROL2
- type: W
- bitfield:
- - range: 16
- name: EMU_ENABLE
- default: 0
- desc: Set to 1 to enable Full mode data emulator RAM
- - range: 15..0
- name: TIMESTAMP_INCR
- desc: Timestamp increment for each sent package
- default: 1
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x2000
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA
- - ref: CR_DEFAULT_EPROC_ENCODING
- - ref: TTC_BUSY_ACCEPTED
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 31..0
- desc: read emu ram data
-
- - ref: CR_XOFF_CTRL
- offset: 0x2800
- desc: Configure FromHost Xoff
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
-
-CR_GBT_CTRL:
- number: 24
- type: W
- bitfield:
- - range: 63..0
- entries:
- - ref: EGROUP_TH
- - ref: EGROUP_FH
-
-EGROUP_TH:
- number: 7
- format_name: GBT{index:02}
- entries:
- - name: TH
- desc: See Central Router Doc, indices [5,6] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - 0x000000002aaa8006
- - 0x000000002aaa8078
- - 0x000000002aaa8001
- - 0x000000002aaaff80
- - 0x000000002aaae628
- - 0x000000002aaa99d0
- - 0x0000000020004000
-
-EGROUP_FH:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FH
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - 0x0000088888888006
- - 0x0000088888888078
- - 0x0000088888888001
- - 0x000008888888ff80
- - 0x000008888888e628
- - 0x00000888888899d0
- - 0x0000080000004000
-
-CR_XOFF_CTRL:
- number: 24
- type: W
- bitfield:
- - range: 39..0
- entries:
- - name: FROMHOST_XOFF_ENABLE
- format_name: FROMHOST_XOFF_ENABLE_{index:02}
- desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
- range: 39..0
- default: 0
- - name: FROMHOST_SOFT_XOFF
- format_name: FROMHOST_SOFT_XOFF_{index:02}
- desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
- range: 39..0
- default: 0
-
-
-IC_FIFOS:
- number: 24
- format_name: FH_TH_IC_FIFOS
- entries:
- - name: FH
- format_name: FH_IC_FIFO_{index:02}
- type_name: FH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.FH_IC_FIFO_{index:02}.FULL
- name: WE
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TH
- format_name: TH_IC_FIFO_{index:02}
- type_name: TH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.TH_IC_FIFO_{index:02}.EMPTY
- name: RE
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range : 11
- name : TOHOST_RST
- desc : reset toHost in ttc decoder
- default : 0
- - range : 10
- name : TT_BCH_EN
- desc : trigger type enable / disable for TTC-ToHost
- default : 1
- - range : 9..2
- name : XL1ID_SW
- desc : set XL1ID value, the value to be set by XL1ID_RST signal
- default : 0x00
- - range : 1
- name : XL1ID_RST
- desc : giving a trigger signal to reset XL1ID value
- default : 0
- - range : 0
- name : MASTER_BUSY
- desc : L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range : 14..5
- name : TH_FF_COUNT
- desc : ToHostData Fifo counts
- - range : 4
- name : TH_FF_FULL
- desc : ToHostData Fifo status 1:full 0:not full
- - range : 3
- name : TH_FF_EMPTY
- desc : ToHostData Fifo status 1:empty 0:not empty
- - range : 2..0
- name : TTC_BIT_ERR
- desc : double bit, single bit and comm error in TTC data
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- bitfield:
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- bitfield:
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
- - name: MARK_FOR_DELETION
- format_name: MARK_FOR_DELETION_{index:02}
- type: R
- bitfield:
- - range: 0
-
-TTC_FANOUT_CTRL:
- number: 24
- format_name: TTC_FANOUT_CTRLS
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Configures the FromHost TTC pipeline in the fanout selector
- type: W
- bitfield:
- - range: 3..0
- default: 0
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0,1
- number: 24
- bitfield:
- - range: 63..0
- entries:
- - name: TH
- format_name: CR_{name}_GBT{index:02}_MON
- - name: FH
- format_name: CR_{name}_GBT{index:02}_MON
-
-CR_DEFAULT_EPROC_ENA:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 14..0
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
-
-CR_DEFAULT_EPROC_ENCODING:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 15..0
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
-
-TTC_BUSY_ACCEPTED:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- bitfield:
- - range: 56..0
- entries:
- - name: BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_LOGIC_RESET
- offset: 0x0400
- bitfield:
- - range: 63..0
- desc: Not internally connected (?)
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE
- offset: 0x0480
- bitfield:
- - range: 59..48
- name: S2312
- desc: RxSlide select [23:12]
- - range: 43..32
- name: S1100
- desc: RxSlide select [11:0]
- - range: 27..16
- name: M2312
- desc: RxSlide manual [23:12]
- - range: 11..0
- name: M1100
- desc: RxSlide manual [11:0]
-
- - name: GBT_TXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: TxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: TxUsrRdy [11:0]
-
- - name: GBT_RXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: RxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: RxUsrRdy [11:0]
-
- - name: GBT_GTTX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: GTTX_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: GTTX_RESET [11:0]
-
- - name: GBT_GTRX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: GTRX_RESET [23:12]
- - range: 11..0
- name: B1100
- desc: GTRX_RESET [11:0]
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL_RESET [11:0]
-
- - name: GBT_SOFT_TX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_TX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_TX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_TX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_TX_RESET_GT [11:0]
-
- - name: GBT_SOFT_RX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_RX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_RX_RESET_GT [11:0]
-
- - name: GBT_ODD_EVEN
- offset: 0x0500
- bitfield:
- - range: 27..16
- name: B2312
- desc: OddEven [23:12]
- - range: 11..0
- name: B1100
- desc: OddEven [11:0]
-
- - name: GBT_TOPBOT
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot [11:0]
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: TX_OPT
-
- - name: GBT_RX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: RX_OPT
-
- - name: GBT_DATA_TXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_TXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_TXFORMAT [23:0]
-
- - name: GBT_DATA_RXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_RXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_RXFORMAT [23:0]
-
- - name: GBT_TX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: TX Logic reset [11:0]
-
- - name: GBT_RX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: RX Logic reset [11:0]
-
- - name: GBT_TX_TC_METHOD
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX time domain crossing method [23:12]
- - range: 11..0
- name: B1100
- desc: TX time domain crossing method [11:0]
-
- - name: GBT_OUTMUX_SEL
- bitfield:
- - range: 27..16
- name: B2312
- desc: Descrambler output MUX selection [23:12]
- - range: 11..0
- name: B1100
- desc: Descrambler output MUX selection [11:0]
-
- - name: GBT_TC_EDGE
- bitfield:
- - range: 27..16
- name: B2312
- desc: Sampling edge selection for TX domain crossing [23:12]
- - range: 11..0
- name: B1100
- desc: Sampling edge selection for TX domain crossing [11:0]
-
- - name: GBT_TRANSCEIVER_POLARITY
- bitfield:
- - range: 47..24
- name: TXPOLARITY
- desc: "0: default polarity, 1: reversed polarity for transmitter of GTH channels"
- default: 0
- - range: 23..0
- name: RXPOLARITY
- desc: "0: default polarity, 1: reversed polarity for the receiver of the GTH channels"
- default: 0
-
- - name: GBT_DNLNK_FO_SEL
- offset: 0x0600
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_UPLNK_FO_SEL
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX Reset done [11:0]
-
- - name: GBT_RXRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX Reset done [11:0]
-
- - name: GBT_TXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX FSM Reset done [11:0]
-
- - name: GBT_RXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX FSM Reset done [11:0]
-
- - name: GBT_CPLL_FBCLK_LOST
- bitfield:
- - range: 27..16
- name: B2312
- desc: CPLL FBCLK LOST [23:12]
- - range: 11..0
- name: B1100
- desc: CPLL FBCLK LOST [11:0]
-
- - name: GBT_CPLL_LOCK
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL LOCK [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL LOCK [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL LOCK [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL LOCK [11:0]
-
- - name: GBT_RXCDR_LOCK
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX CDR LOCK [23:12]
- - range: 11..0
- name: B1100
- desc: RX CDR LOCK [11:0]
-
- - name: GBT_CLK_SAMPLED
- bitfield:
- - range: 27..16
- name: B2312
- desc: clk sampled [23:12]
- - range: 11..0
- name: B1100
- desc: clk sampled [11:0]
-
- - name: GBT_RX_IS_HEADER
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS HEADER [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS HEADER [11:0]
-
- - name: GBT_RX_IS_DATA
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS DATA [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS DATA [11:0]
-
- - name: GBT_RX_HEADER_FOUND
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX HEADER FOUND [23:12]
- - range: 11..0
- name: B1100
- desc: RX HEADER FOUND [11:0]
-
- - name: GBT_ALIGNMENT_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX ALIGNMENT DONE [23:12]
- - range: 11..0
- name: B1100
- desc: RX ALIGNMENT DONE [11:0]
-
- - name: GBT_OUT_MUX_STATUS
- bitfield:
- - range: 27..16
- name: B2312
- desc: GBT output mux status [23:12]
- - range: 11..0
- name: B1100
- desc: GBT output mux status [11:0]
-
- - name: GBT_ERROR
- bitfield:
- - range: 27..16
- name: B2312
- desc: Error flags [23:12]
- - range: 11..0
- name: B1100
- desc: Error flags [11:0]
-
- - name: GBT_GBT_TOPBOT_C
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot_c [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot_c [11:0]
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
- - name: HK_CTRL_CDCE
- offset: 0x0200
- type: W
- bitfield:
- - range: 2
- name: REF_SEL
- desc: REF_SEL
- - range: 1
- name: PD
- desc: PD
- - range: 0
- name: SYNC
- desc: SYNC
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_FORCE
- default: 0x1
- desc: force the use of the Local Clock in any circumstance, overrule automatic clock switch
- - range: 2
- type: R
- name: AUTOMATIC_CLOCK_SWITCH_ENABLED
- desc: 1 when the automatic clock switch is enabled in the design
- - range: 1
- type: R
- name: OSC_SEL
- desc: |
- Main MMCM Oscillator Select
- 1: TTC clock
- 0: Local clock
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: HK_MON
- bitfield:
- - range: 1
- name: CDCE_PLL_LOCK
- desc: CDCE_PLL_LOCK
- - range: 0
- name: I2C_ACK_ERROR
- desc: i2c_ack_error
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL711 locked
- - endpoints: 0,1
- name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
- - endpoints: 0,1
- name: FPGA_ENDPOINT
- type: R
- bitfield:
- - range: 0
- desc: Endpoint of the FPGA
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_2
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#2
-
- - name: INT_TEST_3
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#3
-
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
diff --git a/sources/templates/yaml/registers-3.8.yaml b/sources/templates/yaml/registers-3.8.yaml
deleted file mode 100644
index 17b78c4337008a81e8beb83cef2cb16b69d1e39b..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-3.8.yaml
+++ /dev/null
@@ -1,1725 +0,0 @@
-Registers:
- version: '3.8'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: RD_POINTER
- desc: PC Read Pointer
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: READ_WRITE
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: CURRENT_ADDRESS
- desc: Current Address
-
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 8
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x4000
- - ref: GBTWrapperControls
- offset: 0x5000
- - ref: GBTWrapperMonitors
- offset: 0x6000
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x7000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC709
- - 710 (0x2c6): HTG710
- - 711 (0x2c7): BNL711
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - name: INCLUDE_EPROC16
- type: R
- bitfield:
- - range: 7
- name: FRHOEPROC2
- desc: FromHost EPROC2 is included in Central Router
- - range: 6
- name: FRHOEPROC4
- desc: FromHost EPROC4 is included in Central Router
- - range: 5
- name: FRHOEPROC8
- desc: FromHost EPROC8 is included in Central Router
- - range: 4
- name: FRHOEPROC16
- desc: FromHost EPROC16 is included in Central Router
- - range: 3
- name: TOHOEPROC2
- desc: ToHost EPROC2 is included in Central Router
- - range: 2
- name: TOHOEPROC4
- desc: ToHost EPROC4 is included in Central Router
- - range: 1
- name: TOHOEPROC8
- desc: ToHost EPROC8 is included in Central Router
- - range: 0
- name: TOHOEPROC16
- desc: ToHost EPROC16 is included in Central Router
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: CR_TH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: CR_FH_UPDATE_CTRL
- desc: See Central Router Doc
- type: T
- value: 1
- bitfield:
- - range: any
- - name: FH_IC_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - ref: TTC_FANOUT_CTRL
- desc: Controls the TTC Fanout delay values
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the busy or Logic
- type: W
- bitfield:
- - range: 52
- name: BUSY_SW_ONOFF
- default: 0
- desc: Insert busy signal from software side
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
- - name: COMMA_CHAR
- desc: Idle character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0FA
- desc: -K.28.5
- - range: 17..8
- name: P
- default: 0x305
- desc: +K.28.5
- - range: 7..0
- name: BYTE
- default: 0xBC
- desc: K28.5
-
- - name: SOC_CHAR
- desc: Start of chunk character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F9
- desc: -K.28.1
- - range: 17..8
- name: P
- default: 0x306
- desc: +K.28.1
- - range: 7..0
- name: BYTE
- default: 0x3C
- desc: K28.1
-
- - name: EOC_CHAR
- desc: End of chunk character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F6
- desc: -K.28.6
- - range: 17..8
- name: P
- default: 0x309
- desc: +K.28.6
- - range: 7..0
- name: BYTE
- default: 0xDC
- desc: K28.6
-
- - name: SOB_CHAR
- desc: Start of busy character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F5
- desc: -K.28.2
- - range: 17..8
- name: P
- default: 0x30A
- desc: +K.28.2
- - range: 7..0
- name: BYTE
- default: 0x5C
- desc: K28.2
-
- - name: EOB_CHAR
- desc: End of busy character in GBT mode datastream
- type: W
- bitfield:
- - range: 27..18
- name: N
- default: 0x0F3
- desc: -K.28.3
- - range: 17..8
- name: P
- default: 0x30C
- desc: +K.28.3
- - range: 7..0
- name: BYTE
- default: 0x7C
- desc: K28.3
-
-
-
- - name: FM_EMU_CONTROL1
- type: W
- bitfield:
- - range: 63..32
- name: TIMESTAMP_INIT
- desc: Init value for the timestamp
- default: 0
- - range: 31..16
- name: PACKAGE_COUNT
- desc: Number of packets to be sent out, 0xFFFF means infinite
- default: 0
- - range: 15..0
- name: PACKAGE_LENGTH
- desc: number of 32 bit words in one FM packet
- default: 120
-
- - name: TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - name: FM_EMU_CONTROL2
- type: W
- bitfield:
- - range: 16
- name: EMU_ENABLE
- default: 0
- desc: Set to 1 to enable Full mode data emulator RAM
- - range: 15..0
- name: TIMESTAMP_INCR
- desc: Timestamp increment for each sent package
- default: 1
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x2000
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA
- - ref: CR_DEFAULT_EPROC_ENCODING
- - ref: TTC_BUSY_ACCEPTED
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 31..0
- desc: read emu ram data
-
- - ref: CR_XOFF_CTRL
- offset: 0x2800
- desc: Configure FromHost Xoff
-
-
-
-CR_GBT_CTRL:
- number: 24
- type: W
- bitfield:
- - range: 63..0
- entries:
- - ref: EGROUP_TH
- - ref: EGROUP_FH
-
-EGROUP_TH:
- number: 7
- format_name: GBT{index:02}
- entries:
- - name: TH
- desc: See Central Router Doc, indices [5,6] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - 0x000000002aaa8006
- - 0x000000002aaa8078
- - 0x000000002aaa8001
- - 0x000000002aaaff80
- - 0x000000002aaae628
- - 0x000000002aaa99d0
- - 0x0000000020004000
-
-EGROUP_FH:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FH
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- default:
- - 0x0000088888888006
- - 0x0000088888888078
- - 0x0000088888888001
- - 0x000008888888ff80
- - 0x000008888888e628
- - 0x00000888888899d0
- - 0x0000080000004000
-
-CR_XOFF_CTRL:
- number: 24
- type: W
- bitfield:
- - range: 39..0
- entries:
- - name: FROMHOST_XOFF_ENABLE_{index:02}
- desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
- range: 39..0
- default: 0
- - name: FROMHOST_SOFT_XOFF_{index:02}
- desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
- range: 39..0
- default: 0
-
-
-IC_FIFOS:
- number: 24
- format_name: FH_TH_IC_FIFOS
- entries:
- - name: FH
- format_name: FH_IC_FIFO_{index:02}
- type_name: FH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.FH_IC_FIFO_{index:02}.FULL
- name: WE
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: FH_IC_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TH
- format_name: TH_IC_FIFO_{index:02}
- type_name: TH_IC_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.TH_IC_FIFO_{index:02}.EMPTY
- name: RE
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: TH_IC_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- bitfield:
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- bitfield:
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
- - name: MARK_FOR_DELETION
- format_name: MARK_FOR_DELETION_{index:02}
- type: R
- bitfield:
- - range: 0
-
-TTC_FANOUT_CTRL:
- number: 24
- format_name: TTC_FANOUT_CTRLS
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Configures the FromHost TTC pipeline in the fanout selector
- type: W
- bitfield:
- - range: 3..0
- default: 0
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0,1
- number: 24
- bitfield:
- - range: 63..0
- entries:
- - name: TH
- format_name: CR_{name}_GBT{index:02}_MON
- - name: FH
- format_name: CR_{name}_GBT{index:02}_MON
-
-CR_DEFAULT_EPROC_ENA:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 14..0
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
-
-CR_DEFAULT_EPROC_ENCODING:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 15..0
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
-
-TTC_BUSY_ACCEPTED:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- bitfield:
- - range: 56..0
- entries:
- - name: BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_LOGIC_RESET
- offset: 0x0400
- bitfield:
- - range: 63..0
- desc: Not internally connected (?)
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE
- offset: 0x0480
- bitfield:
- - range: 59..48
- name: S2312
- desc: RxSlide select [23:12]
- - range: 43..32
- name: S1100
- desc: RxSlide select [11:0]
- - range: 27..16
- name: M2312
- desc: RxSlide manual [23:12]
- - range: 11..0
- name: M1100
- desc: RxSlide manual [11:0]
-
- - name: GBT_TXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: TxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: TxUsrRdy [11:0]
-
- - name: GBT_RXUSRRDY
- bitfield:
- - range: 27..16
- name: B2312
- default: 0xFFF
- desc: RxUsrRdy [23:12]
- - range: 11..0
- name: B1100
- default: 0xFFF
- desc: RxUsrRdy [11:0]
-
- - name: GBT_GTTX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: GTTX_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: GTTX_RESET [11:0]
-
- - name: GBT_GTRX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: GTRX_RESET [23:12]
- - range: 11..0
- name: B1100
- desc: GTRX_RESET [11:0]
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL_RESET [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL_RESET [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL_RESET [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL_RESET [11:0]
-
- - name: GBT_SOFT_TX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_TX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_TX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_TX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_TX_RESET_GT [11:0]
-
- - name: GBT_SOFT_RX_RESET
- bitfield:
- - range: 30..28
- name: B0503
- desc: SOFT_RX_RESET_ALL [5:3]
- - range: 27..16
- name: B2312
- desc: SOFT_RX_RESET_GT [23:12]
- - range: 14..12
- name: B0200
- desc: SOFT_RX_RESET_ALL [2:0]
- - range: 11..0
- name: B1100
- desc: SOFT_RX_RESET_GT [11:0]
-
- - name: GBT_ODD_EVEN
- offset: 0x0500
- bitfield:
- - range: 27..16
- name: B2312
- desc: OddEven [23:12]
- - range: 11..0
- name: B1100
- desc: OddEven [11:0]
-
- - name: GBT_TOPBOT
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot [11:0]
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: TX_OPT
-
- - name: GBT_RX_OPT
- bitfield:
- - range: 47..0
- default: 0x0000000000555555
- desc: RX_OPT
-
- - name: GBT_DATA_TXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_TXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_TXFORMAT [23:0]
-
- - name: GBT_DATA_RXFORMAT
- bitfield:
- - range: 55..32
- name: B4724
- desc: DATA_RXFORMAT [47:24]
- - range: 23..0
- name: B2300
- desc: DATA_RXFORMAT [23:0]
-
- - name: GBT_TX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: TX Logic reset [11:0]
-
- - name: GBT_RX_RESET
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Logic reset [23:12]
- - range: 11..0
- name: B1100
- desc: RX Logic reset [11:0]
-
- - name: GBT_TX_TC_METHOD
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX time domain crossing method [23:12]
- - range: 11..0
- name: B1100
- desc: TX time domain crossing method [11:0]
-
- - name: GBT_OUTMUX_SEL
- bitfield:
- - range: 27..16
- name: B2312
- desc: Descrambler output MUX selection [23:12]
- - range: 11..0
- name: B1100
- desc: Descrambler output MUX selection [11:0]
-
- - name: GBT_TC_EDGE
- bitfield:
- - range: 27..16
- name: B2312
- desc: Sampling edge selection for TX domain crossing [23:12]
- - range: 11..0
- name: B1100
- desc: Sampling edge selection for TX domain crossing [11:0]
-
- - name: GBT_TRANSCEIVER_POLARITY
- bitfield:
- - range: 47..24
- name: TXPOLARITY
- desc: "0: default polarity, 1: reversed polarity for transmitter of GTH channels"
- default: 0
- - range: 23..0
- name: RXPOLARITY
- desc: "0: default polarity, 1: reversed polarity for the receiver of the GTH channels"
- default: 0
-
- - name: GBT_DNLNK_FO_SEL
- offset: 0x0600
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_UPLNK_FO_SEL
- bitfield:
- - range: 31..0
- default: 0x00FFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX Reset done [11:0]
-
- - name: GBT_RXRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX Reset done [11:0]
-
- - name: GBT_TXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: TX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: TX FSM Reset done [11:0]
-
- - name: GBT_RXFSMRESET_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX FSM Reset done [23:12]
- - range: 11..0
- name: B1100
- desc: RX FSM Reset done [11:0]
-
- - name: GBT_CPLL_FBCLK_LOST
- bitfield:
- - range: 27..16
- name: B2312
- desc: CPLL FBCLK LOST [23:12]
- - range: 11..0
- name: B1100
- desc: CPLL FBCLK LOST [11:0]
-
- - name: GBT_CPLL_LOCK
- bitfield:
- - range: 30..28
- name: B0503
- desc: QPLL LOCK [5:3]
- - range: 27..16
- name: B2312
- desc: CPLL LOCK [23:12]
- - range: 14..12
- name: B0200
- desc: QPLL LOCK [2:0]
- - range: 11..0
- name: B1100
- desc: CPLL LOCK [11:0]
-
- - name: GBT_RXCDR_LOCK
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX CDR LOCK [23:12]
- - range: 11..0
- name: B1100
- desc: RX CDR LOCK [11:0]
-
- - name: GBT_CLK_SAMPLED
- bitfield:
- - range: 27..16
- name: B2312
- desc: clk sampled [23:12]
- - range: 11..0
- name: B1100
- desc: clk sampled [11:0]
-
- - name: GBT_RX_IS_HEADER
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS HEADER [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS HEADER [11:0]
-
- - name: GBT_RX_IS_DATA
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX IS DATA [23:12]
- - range: 11..0
- name: B1100
- desc: RX IS DATA [11:0]
-
- - name: GBT_RX_HEADER_FOUND
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX HEADER FOUND [23:12]
- - range: 11..0
- name: B1100
- desc: RX HEADER FOUND [11:0]
-
- - name: GBT_ALIGNMENT_DONE
- bitfield:
- - range: 27..16
- name: B2312
- desc: RX ALIGNMENT DONE [23:12]
- - range: 11..0
- name: B1100
- desc: RX ALIGNMENT DONE [11:0]
-
- - name: GBT_OUT_MUX_STATUS
- bitfield:
- - range: 27..16
- name: B2312
- desc: GBT output mux status [23:12]
- - range: 11..0
- name: B1100
- desc: GBT output mux status [11:0]
-
- - name: GBT_ERROR
- bitfield:
- - range: 27..16
- name: B2312
- desc: Error flags [23:12]
- - range: 11..0
- name: B1100
- desc: Error flags [11:0]
-
- - name: GBT_GBT_TOPBOT_C
- bitfield:
- - range: 27..16
- name: B2312
- desc: TopBot_c [23:12]
- - range: 11..0
- name: B1100
- desc: TopBot_c [11:0]
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
- - name: HK_CTRL_CDCE
- offset: 0x0200
- type: W
- bitfield:
- - range: 2
- name: REF_SEL
- desc: REF_SEL
- - range: 1
- name: PD
- desc: PD
- - range: 0
- name: SYNC
- desc: SYNC
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_FORCE
- default: 0x1
- desc: force the use of the Local Clock in any circumstance, overrule automatic clock switch
- - range: 2
- type: R
- name: AUTOMATIC_CLOCK_SWITCH_ENABLED
- desc: 1 when the automatic clock switch is enabled in the design
- - range: 1
- type: R
- name: OSC_SEL
- desc: |
- Main MMCM Oscillator Select
- 1: TTC clock
- 0: Local clock
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: HK_MON
- bitfield:
- - range: 1
- name: CDCE_PLL_LOCK
- desc: CDCE_PLL_LOCK
- - range: 0
- name: I2C_ACK_ERROR
- desc: i2c_ack_error
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL711 locked
- - endpoints: 0,1
- name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
- - endpoints: 0,1
- name: FPGA_ENDPOINT
- type: R
- bitfield:
- - range: 0
- desc: Endpoint of the FPGA
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_2
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#2
-
- - name: INT_TEST_3
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#3
-
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
diff --git a/sources/templates/yaml/registers-4.0.yaml b/sources/templates/yaml/registers-4.0.yaml
deleted file mode 100644
index 902ab188a25721e2496b6ea7e85299c21dd326ef..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-4.0.yaml
+++ /dev/null
@@ -1,1722 +0,0 @@
-Registers:
- version: '4.0'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: TTCBUSYControlsAndMonitors
- record_name: register_map_ttc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
-# - name: Generators
-# record_name: register_map_generators
-# bitfield:
-# - range: 0..0
-# type: R
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: SW_POINTER
- desc: Pointer controlled by the software, indicating read or write status for circular DMA
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: FROMHOST
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: FW_POINTER
- desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
-
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 8
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x5000
- - ref: GBTWrapperControls
- offset: 0x6000
- - ref: GBTWrapperMonitors
- offset: 0x7000
- - ref: TTCBUSYControlsAndMonitors
- offset: 0x8000
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x9000
- - ref: Generators
- offset: 0xA000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: GIT_COMMIT_TIME
- bitfield:
- - range: 39..0
- value: COMMIT_DATETIME
- desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_TAG
- bitfield:
- - range: 63..0
- value: GIT_TAG(63 downto 0)
- desc: String containing the current GIT TAG
-
- - name: GIT_COMMIT_NUMBER
- bitfield:
- - range: 31..0
- value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
- desc: Number of GIT commits after current GIT_TAG
-
- - name: GIT_HASH
- bitfield:
- - range: 31..0
- value: GIT_HASH(159 downto 128)
- desc: Short GIT hash (32 bit)
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC-709
- - 710 (0x2c6): HTG-710
- - 711 (0x2c7): BNL-711
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - ref: INCLUDE_EGROUP
-
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
- 3: FEI4 mode
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
-
-INCLUDE_EGROUP:
- number: 7
- entries:
- - format_name: INCLUDE_EGROUP_{index}
- name: INCLUDE_EGROUP
- #type_name: INCLUDE_EGROUP
- type: R
- bitfield:
- - range: 8
- name: FROMHOST_02
- desc: FromHost EPROC02 is included in this EGROUP
- - range: 7
- name: FROMHOST_04
- desc: FromHost EPROC04 is included in this EGROUP
- - range: 6
- name: FROMHOST_08
- desc: FromHost EPROC8 is included in this EGROUP
- - range: 5
- name: FROMHOST_HDLC
- desc: FromHost HDLC is included in this EGROUP
- - range: 4
- name: TOHOST_02
- desc: ToHost EPROC02 is included in this EGROUP
- - range: 3
- name: TOHOST_04
- desc: ToHost EPROC04 is included in this EGROUP
- - range: 2
- name: TOHOST_08
- desc: ToHost EPROC08 is included in this EGROUP
- - range: 1
- name: TOHOST_16
- desc: ToHost EPROC16 is included in this EGROUP
- - range: 0
- name: TOHOST_HDLC
- desc: ToHost HDLC is included in this EGROUP
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: IC_FROMHOST_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: CR_TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - ref: CR_XOFF_CTRL
- offset: 0x2800
- desc: Configure FromHost Xoff
-
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x3000
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA
- - ref: CR_DEFAULT_EPROC_ENCODING
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
-
-
-
-CR_GBT_CTRL:
- number: 24
- bitfield:
- - range: 50..0
- type: W
- entries:
- - ref: EGROUP_TOHOST
- - ref: EGROUP_FROMHOST
-
-EGROUP_TOHOST:
- number: 7
- format_name: GBT{index:02}
- name: GBT
- entries:
- - name: TOHOST
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_TOHOST_EGROUP_CTRL
- bitfield:
- - range: 58..51
- name: INSTANT_TIMEOUT_ENA
- default: 0x0
- desc: instantly initiate a timeout for the given epath
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..31
- name: MAX_CHUNK_LEN
- default: MAX_CHUNK_LEN_array
- desc: set the maximum length of a chunk, 0 disables truncation
- - range: 30..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- default:
- - PATH_ENCODING_array(0)
- - PATH_ENCODING_array(1)
- - PATH_ENCODING_array(2)
- - PATH_ENCODING_array(3)
- - PATH_ENCODING_array(4)
- - PATH_ENCODING_array(5)
- - PATH_ENCODING_array(6)
-
- - range: 14..0
- name: EPROC_ENA
- desc: Enable bits per EPROC
- default:
- - EPROC_ENA_bits_array(0)
- - EPROC_ENA_bits_array(1)
- - EPROC_ENA_bits_array(2)
- - EPROC_ENA_bits_array(3)
- - EPROC_ENA_bits_array(4)
- - EPROC_ENA_bits_array(5)
- - EPROC_ENA_bits_array(6)
-
-EGROUP_FROMHOST:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FROMHOST
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_FROMHOST_EGROUP_CTRL
- bitfield:
- - range: 54..47
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 46..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- greater than 3: TTC mode, see CentralRouter doc
- default:
- - FROMHOST_PATH_ENCODING_array(0)
- - FROMHOST_PATH_ENCODING_array(1)
- - FROMHOST_PATH_ENCODING_array(2)
- - FROMHOST_PATH_ENCODING_array(3)
- - FROMHOST_PATH_ENCODING_array(4)
- - FROMHOST_PATH_ENCODING_array(5)
- - FROMHOST_PATH_ENCODING_array(6)
- - range: 14..0
- desc: Enable bits per EPROC
- name: EPROC_ENA
-
-CR_XOFF_CTRL:
- number: 24
- type: W
- bitfield:
- - range: 39..0
- entries:
- - name: FROMHOST_XOFF_ENABLE
- format_name: FROMHOST_XOFF_ENABLE_{index:02}
- desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
- range: 39..0
- default: 0
- - name: FROMHOST_SOFT_XOFF
- format_name: FROMHOST_SOFT_XOFF_{index:02}
- desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
- range: 39..0
- default: 0
-
-
-IC_FIFOS:
- number: 24
- format_name: IC_FROMHOST_TOHOST_FIFOS
- entries:
- - name: FROMHOST
- format_name: IC_FROMHOST_FIFO_{index:02}
- type_name: IC_FROMHOST_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_FROMHOST_FIFO_{index:02}.FULL
- name: WE
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TOHOST
- format_name: IC_TOHOST_FIFO_{index:02}
- type_name: IC_TOHOST_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_TOHOST_FIFO_{index:02}.EMPTY
- name: RE
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- bitfield:
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- bitfield:
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
-
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- entries:
- - name: TOHOST
- type_name: TOHOST
- format_name: CR_{name}_GBT{index:02}_MON
- bitfield:
- - range: 58
- name: CROUTFIFO_PROG_FULL
- - range: 57
- name: WMFIFO_FULL
- - range: 56
- name: MINI_EGROUP_ALMOST_FULL
- - range: 55..48
- name: EPATH6_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP6
- - range: 47..40
- name: EPATH5_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP5
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
- - name: FROMHOST
- type_name: FROMHOST
- format_name: CR_{name}_GBT{index:02}_MON
- bitfield:
- - range: 40
- name: MINI_EGROUP_ALMOST_FULL
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
-
-CR_DEFAULT_EPROC_ENA:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 14..0
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
-
-CR_DEFAULT_EPROC_ENCODING:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 15..0
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
-
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 63..48
- name: RDDATA
- type: R
- desc: read data bus
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 0
- desc: write enable for the full mode emulator ram block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 35..0
- desc: read emu ram data
-
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_CHANNEL_DISABLE
- offset: 0x0400
- bitfield:
- - range: 47..0
- desc: Disable selected GBT or FULL mode channel
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE_SELECT
- offset: 0x0480
- desc: RxSlide select [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXSLIDE_MANUAL
- desc: RxSlide select [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXUSRRDY
- desc: TxUsrRdy [47:0]
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_RXUSRRDY
- desc: RxUsrRdy [47:0]
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_SOFT_RESET
- desc: SOFT_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTTX_RESET
- desc: GTTX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTRX_RESET
- desc: GTRX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 59..48
- name: QPLL_RESET
- desc: QPLL_RESET [11:0]
- - range: 47..0
- name: CPLL_RESET
- desc: CPLL_RESET [47:0]
-
- - name: GBT_SOFT_TX_RESET
- offset: 0x0500
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_SOFT_RX_RESET
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_ODD_EVEN
- desc: OddEven [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TOPBOT
- desc: TopBot [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_TC_DLY_VALUE3
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [143:96]
-
- - name: GBT_TX_TC_DLY_VALUE4
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [191:144]
-
- - name: GBT_DATA_TXFORMAT1
- desc: DATA_TXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_TXFORMAT2
- desc: DATA_TXFORMAT [95:48]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT1
- desc: DATA_RXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT2
- desc: DATA_RXFORMAT [95:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_RESET
- desc: TX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_RESET
- desc: RX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_METHOD
- desc: TX time domain crossing method [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUTMUX_SEL
- desc: Descrambler output MUX selection [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TC_EDGE
- desc: Sampling edge selection for TX domain crossing [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for transmitter of GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_RXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for the receiver of the GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
- - name: GBT_TOHOST_FANOUT
- offset: 0x0700
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_TOFRONTEND_FANOUT
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- desc: TX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXRESET_DONE
- desc: RX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXFSMRESET_DONE
- desc: TX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXFSMRESET_DONE
- desc: RX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_LOCK
- bitfield:
- - range: 59..48
- name: QPLL_LOCK
- desc: QPLL LOCK [11:0]
- - range: 47..0
- name: CPLL_LOCK
- desc: CPLL LOCK [47:0]
-
- - name: GBT_RXCDR_LOCK
- desc: RX CDR LOCK [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CLK_SAMPLED
- desc: clk sampled [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_HEADER
- desc: RX IS HEADER [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_DATA
- desc: RX IS DATA [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_HEADER_FOUND
- desc: RX HEADER FOUND [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUT_MUX_STATUS
- desc: GBT output mux status [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ERROR
- desc: Error flags [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GBT_TOPBOT_C
- desc: TopBot_c [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-TTCBUSYControlsAndMonitors:
- group: TTCBUSY
- desc: TTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: TTC_BUSY_ACCEPTED
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - ref: TTC_DELAY
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the BUSY Logic
- type: W
- bitfield:
- - range: 52
- name: BUSY_SW_ONOFF
- default: 0
- desc: Insert busy signal from software side
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range : 11
- name : TOHOST_RST
- desc : reset toHost in ttc decoder
- default : 0
- - range : 10
- name : TT_BCH_EN
- desc : trigger type enable / disable for TTC-ToHost
- default : 1
- - range : 9..2
- name : XL1ID_SW
- desc : set XL1ID value, the value to be set by XL1ID_RST signal
- default : 0x00
- - range : 1
- name : XL1ID_RST
- desc : giving a trigger signal to reset XL1ID value
- default : 0
- - range : 0
- name : MASTER_BUSY
- desc : L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range : 14..5
- name : TH_FF_COUNT
- desc : ToHostData Fifo counts
- - range : 4
- name : TH_FF_FULL
- desc : ToHostData Fifo status 1:full 0:not full
- - range : 3
- name : TH_FF_EMPTY
- desc : ToHostData Fifo status 1:empty 0:not empty
- - range : 2..0
- name : TTC_BIT_ERR
- desc : double bit, single bit and comm error in TTC data
-
-TTC_BUSY_ACCEPTED:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- bitfield:
- - range: 56..0
- entries:
- - name: BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
-
-
-TTC_DELAY:
- number: 48
- type: W
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Controls the TTC Fanout delay values
- bitfield:
- - range: 3..0
- default: 0
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
-
- - name: HK_MON_FMC
- type: W
- bitfield:
- - range: 1
- name: SI5345_LOL
- desc: Si5345 Loss Of Lock pin
- - range: 0
- name: SI5345_INTR
- desc: Si5345 Interrupt flagging chip change of status
-
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_SEL
- default: 0x1
- desc: |
- 1: LCLK
- 0: TTC
- - range: 2..1
- type: R
- name: MAIN_INPUT
- desc: |
- Main MMCM Oscillator Input
- 2: LCLK fixed
- 1: TTC fixed
- 0: selectable
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL-711 locked
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
-
- - name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
-
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_4
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#4
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
-
-Generators:
- group: GEN
- desc: Specific registers for Hardware based Generators
- endpoints: 0
- entries:
-
- - name: GEN_FM_CONTROL1
- type: W
- bitfield:
- - range: 63..32
- name: TIMESTAMP_INIT
- desc: Init value for the timestamp
- default: 0
- - range: 31..16
- name: PACKAGE_COUNT
- desc: Number of packets to be sent out, 0xFFFF means infinite
- default: 0
- - range: 15..0
- name: PACKAGE_LENGTH
- desc: number of 32 bit words in one FM packet
- default: 120
-
- - name: GEN_FM_CONTROL2
- type: W
- bitfield:
- - range: 16
- name: EMU_ENABLE
- default: 0
- desc: Set to 1 to enable Full mode data emulator RAM
- - range: 15..0
- name: TIMESTAMP_INCR
- desc: Timestamp increment for each sent package
- default: 1
diff --git a/sources/templates/yaml/registers-4.1.yaml b/sources/templates/yaml/registers-4.1.yaml
deleted file mode 100644
index 7cbfda333f7091c2b1865a6a893ad9c5d3949e4f..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-4.1.yaml
+++ /dev/null
@@ -1,1758 +0,0 @@
-Registers:
- version: '4.1'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: TTCBUSYControlsAndMonitors
- record_name: register_map_ttc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
-# - name: Generators
-# record_name: register_map_generators
-# bitfield:
-# - range: 0..0
-# type: R
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
- - name: BUSY_THRESHOLD_ASSERT
- type: W
- desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
- default: 0x6400000
- bitfield:
- - range: 63..0
-
- - name: BUSY_THRESHOLD_NEGATE
- type: W
- desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
- default: 0x6E00000
- bitfield:
- - range: 63..0
-
- - name: BUSY_STATUS
- type: R
- bitfield:
- - range: 1
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- - range: 0
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: SW_POINTER
- desc: Pointer controlled by the software, indicating read or write status for circular DMA
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: FROMHOST
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: FW_POINTER
- desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
-
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 16
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x5000
- - ref: GBTWrapperControls
- offset: 0x6000
- - ref: GBTWrapperMonitors
- offset: 0x7000
- - ref: TTCBUSYControlsAndMonitors
- offset: 0x8000
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x9000
- - ref: Generators
- offset: 0xA000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: GIT_COMMIT_TIME
- bitfield:
- - range: 39..0
- value: COMMIT_DATETIME
- desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_TAG
- bitfield:
- - range: 63..0
- value: GIT_TAG(63 downto 0)
- desc: String containing the current GIT TAG
-
- - name: GIT_COMMIT_NUMBER
- bitfield:
- - range: 31..0
- value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
- desc: Number of GIT commits after current GIT_TAG
-
- - name: GIT_HASH
- bitfield:
- - range: 31..0
- value: GIT_HASH(159 downto 128)
- desc: Short GIT hash (32 bit)
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC-709
- - 710 (0x2c6): HTG-710
- - 711 (0x2c7): BNL-711
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - ref: INCLUDE_EGROUP
-
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
- 3: FEI4 mode
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
-
-INCLUDE_EGROUP:
- number: 7
- entries:
- - format_name: INCLUDE_EGROUP_{index}
- name: INCLUDE_EGROUP
- #type_name: INCLUDE_EGROUP
- type: R
- bitfield:
- - range: 8
- name: FROMHOST_02
- desc: FromHost EPROC02 is included in this EGROUP
- - range: 7
- name: FROMHOST_04
- desc: FromHost EPROC04 is included in this EGROUP
- - range: 6
- name: FROMHOST_08
- desc: FromHost EPROC8 is included in this EGROUP
- - range: 5
- name: FROMHOST_HDLC
- desc: FromHost HDLC is included in this EGROUP
- - range: 4
- name: TOHOST_02
- desc: ToHost EPROC02 is included in this EGROUP
- - range: 3
- name: TOHOST_04
- desc: ToHost EPROC04 is included in this EGROUP
- - range: 2
- name: TOHOST_08
- desc: ToHost EPROC08 is included in this EGROUP
- - range: 1
- name: TOHOST_16
- desc: ToHost EPROC16 is included in this EGROUP
- - range: 0
- name: TOHOST_HDLC
- desc: ToHost HDLC is included in this EGROUP
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: IC_FROMHOST_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: CR_TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - ref: CR_XOFF_CTRL
- offset: 0x2800
- desc: Configure FromHost Xoff
-
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x3000
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA
- - ref: CR_DEFAULT_EPROC_ENCODING
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
-
-
-
-CR_GBT_CTRL:
- number: 24
- bitfield:
- - range: 50..0
- type: W
- entries:
- - ref: EGROUP_TOHOST
- - ref: EGROUP_FROMHOST
-
-EGROUP_TOHOST:
- number: 7
- format_name: GBT{index:02}
- name: GBT
- entries:
- - name: TOHOST
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_TOHOST_EGROUP_CTRL
- bitfield:
- - range: 58..51
- name: INSTANT_TIMEOUT_ENA
- default: 0x0
- desc: instantly initiate a timeout for the given epath
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..31
- name: MAX_CHUNK_LEN
- default: MAX_CHUNK_LEN_array
- desc: set the maximum length of a chunk, 0 disables truncation
- - range: 30..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- default:
- - PATH_ENCODING_array(0)
- - PATH_ENCODING_array(1)
- - PATH_ENCODING_array(2)
- - PATH_ENCODING_array(3)
- - PATH_ENCODING_array(4)
- - PATH_ENCODING_array(5)
- - PATH_ENCODING_array(6)
-
- - range: 14..0
- name: EPROC_ENA
- desc: Enable bits per EPROC
- default:
- - EPROC_ENA_bits_array(0)
- - EPROC_ENA_bits_array(1)
- - EPROC_ENA_bits_array(2)
- - EPROC_ENA_bits_array(3)
- - EPROC_ENA_bits_array(4)
- - EPROC_ENA_bits_array(5)
- - EPROC_ENA_bits_array(6)
-
-EGROUP_FROMHOST:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FROMHOST
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_FROMHOST_EGROUP_CTRL
- bitfield:
- - range: 54..47
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 46..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- greater than 3: TTC mode, see CentralRouter doc
- default:
- - FROMHOST_PATH_ENCODING_array(0)
- - FROMHOST_PATH_ENCODING_array(1)
- - FROMHOST_PATH_ENCODING_array(2)
- - FROMHOST_PATH_ENCODING_array(3)
- - FROMHOST_PATH_ENCODING_array(4)
- - FROMHOST_PATH_ENCODING_array(5)
- - FROMHOST_PATH_ENCODING_array(6)
- - range: 14..0
- desc: Enable bits per EPROC
- name: EPROC_ENA
-
-CR_XOFF_CTRL:
- number: 24
- type: W
- bitfield:
- - range: 39..0
- entries:
- - name: FROMHOST_XOFF_ENABLE
- format_name: FROMHOST_XOFF_ENABLE_{index:02}
- desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
- range: 39..0
- default: 0
- - name: FROMHOST_SOFT_XOFF
- format_name: FROMHOST_SOFT_XOFF_{index:02}
- desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
- range: 39..0
- default: 0
-
-
-IC_FIFOS:
- number: 24
- format_name: IC_FROMHOST_TOHOST_FIFOS
- entries:
- - name: FROMHOST
- format_name: IC_FROMHOST_FIFO_{index:02}
- type_name: IC_FROMHOST_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_FROMHOST_FIFO_{index:02}.FULL
- name: WE
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TOHOST
- format_name: IC_TOHOST_FIFO_{index:02}
- type_name: IC_TOHOST_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_TOHOST_FIFO_{index:02}.EMPTY
- name: RE
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- bitfield:
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- bitfield:
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
-
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- entries:
- - name: TOHOST
- type_name: TOHOST
- format_name: CR_{name}_GBT{index:02}_MON
- bitfield:
- - range: 58
- name: CROUTFIFO_PROG_FULL
- - range: 57
- name: WMFIFO_FULL
- - range: 56
- name: MINI_EGROUP_ALMOST_FULL
- - range: 55..48
- name: EPATH6_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP6
- - range: 47..40
- name: EPATH5_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP5
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
- - name: FROMHOST
- type_name: FROMHOST
- format_name: CR_{name}_GBT{index:02}_MON
- bitfield:
- - range: 40
- name: MINI_EGROUP_ALMOST_FULL
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
-
-CR_DEFAULT_EPROC_ENA:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 14..0
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
-
-CR_DEFAULT_EPROC_ENCODING:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 15..0
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
-
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 63..48
- name: RDDATA
- type: R
- desc: read data bus
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 0
- desc: write enable for the full mode emulator ram block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 35..0
- desc: read emu ram data
-
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_CHANNEL_DISABLE
- offset: 0x0400
- bitfield:
- - range: 47..0
- desc: Disable selected GBT or FULL mode channel
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE_SELECT
- offset: 0x0480
- desc: RxSlide select [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXSLIDE_MANUAL
- desc: RxSlide select [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXUSRRDY
- desc: TxUsrRdy [47:0]
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_RXUSRRDY
- desc: RxUsrRdy [47:0]
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_SOFT_RESET
- desc: SOFT_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTTX_RESET
- desc: GTTX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTRX_RESET
- desc: GTRX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 59..48
- name: QPLL_RESET
- desc: QPLL_RESET [11:0]
- - range: 47..0
- name: CPLL_RESET
- desc: CPLL_RESET [47:0]
-
- - name: GBT_SOFT_TX_RESET
- offset: 0x0500
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_SOFT_RX_RESET
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_ODD_EVEN
- desc: OddEven [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TOPBOT
- desc: TopBot [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_TC_DLY_VALUE3
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [143:96]
-
- - name: GBT_TX_TC_DLY_VALUE4
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [191:144]
-
- - name: GBT_DATA_TXFORMAT1
- desc: DATA_TXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_TXFORMAT2
- desc: DATA_TXFORMAT [95:48]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT1
- desc: DATA_RXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT2
- desc: DATA_RXFORMAT [95:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_RESET
- desc: TX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_RESET
- desc: RX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_METHOD
- desc: TX time domain crossing method [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUTMUX_SEL
- desc: Descrambler output MUX selection [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TC_EDGE
- desc: Sampling edge selection for TX domain crossing [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for transmitter of GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_RXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for the receiver of the GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
- - name: GBT_TOHOST_FANOUT
- offset: 0x0700
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_TOFRONTEND_FANOUT
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- desc: TX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXRESET_DONE
- desc: RX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXFSMRESET_DONE
- desc: TX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXFSMRESET_DONE
- desc: RX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_LOCK
- bitfield:
- - range: 59..48
- name: QPLL_LOCK
- desc: QPLL LOCK [11:0]
- - range: 47..0
- name: CPLL_LOCK
- desc: CPLL LOCK [47:0]
-
- - name: GBT_RXCDR_LOCK
- desc: RX CDR LOCK [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CLK_SAMPLED
- desc: clk sampled [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_HEADER
- desc: RX IS HEADER [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_DATA
- desc: RX IS DATA [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_HEADER_FOUND
- desc: RX HEADER FOUND [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUT_MUX_STATUS
- desc: GBT output mux status [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ERROR
- desc: Error flags [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GBT_TOPBOT_C
- desc: TopBot_c [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-TTCBUSYControlsAndMonitors:
- group: TTCBUSY
- desc: TTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: TTC_BUSY_ACCEPTED
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - ref: TTC_DELAY
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the BUSY Logic
- type: W
- bitfield:
- - range: 52
- name: BUSY_SW_ONOFF
- default: 0
- desc: Insert busy signal from software side
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
- - name: DMA_BUSY_STATUS
- type: R
- bitfield:
- - range: 1
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => fromhost_busy_40_s)
- - range: 0
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => tohost_busy_40_s)
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range : 11
- name : TOHOST_RST
- desc : reset toHost in ttc decoder
- default : 0
- - range : 10
- name : TT_BCH_EN
- desc : trigger type enable / disable for TTC-ToHost
- default : 1
- - range : 9..2
- name : XL1ID_SW
- desc : set XL1ID value, the value to be set by XL1ID_RST signal
- default : 0x00
- - range : 1
- name : XL1ID_RST
- desc : giving a trigger signal to reset XL1ID value
- default : 0
- - range : 0
- name : MASTER_BUSY
- desc : L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range : 14..5
- name : TH_FF_COUNT
- desc : ToHostData Fifo counts
- - range : 4
- name : TH_FF_FULL
- desc : ToHostData Fifo status 1:full 0:not full
- - range : 3
- name : TH_FF_EMPTY
- desc : ToHostData Fifo status 1:empty 0:not empty
- - range : 2..0
- name : TTC_BIT_ERR
- desc : double bit, single bit and comm error in TTC data
-
-TTC_BUSY_ACCEPTED:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- bitfield:
- - range: 56..0
- entries:
- - name: BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
-
-
-TTC_DELAY:
- number: 48
- type: W
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Controls the TTC Fanout delay values
- bitfield:
- - range: 3..0
- default: 0
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
-
- - name: HK_MON_FMC
- type: W
- bitfield:
- - range: 1
- name: SI5345_LOL
- desc: Si5345 Loss Of Lock pin
- - range: 0
- name: SI5345_INTR
- desc: Si5345 Interrupt flagging chip change of status
-
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_SEL
- default: 0x1
- desc: |
- 1: LCLK
- 0: TTC
- - range: 2..1
- type: R
- name: MAIN_INPUT
- desc: |
- Main MMCM Oscillator Input
- 2: LCLK fixed
- 1: TTC fixed
- 0: selectable
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL-711 locked
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
-
- - name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
-
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_4
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#4
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
-
-Generators:
- group: GEN
- desc: Specific registers for Hardware based Generators
- endpoints: 0
- entries:
-
- - name: GEN_FM_CONTROL1
- type: W
- bitfield:
- - range: 63..32
- name: TIMESTAMP_INIT
- desc: Init value for the timestamp
- default: 0
- - range: 31..16
- name: PACKAGE_COUNT
- desc: Number of packets to be sent out, 0xFFFF means infinite
- default: 0
- - range: 15..0
- name: PACKAGE_LENGTH
- desc: number of 32 bit words in one FM packet
- default: 120
-
- - name: GEN_FM_CONTROL2
- type: W
- bitfield:
- - range: 16
- name: EMU_ENABLE
- default: 0
- desc: Set to 1 to enable Full mode data emulator RAM
- - range: 15..0
- name: TIMESTAMP_INCR
- desc: Timestamp increment for each sent package
- default: 1
diff --git a/sources/templates/yaml/registers-4.10.yaml b/sources/templates/yaml/registers-4.10.yaml
deleted file mode 100755
index 47b66a13d5246d24e3ddbb9f9ba6b3eab0c91a13..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-4.10.yaml
+++ /dev/null
@@ -1,3517 +0,0 @@
-Registers:
- version: '4.10'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: TTCBUSYControlsAndMonitors
- record_name: register_map_ttc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: XOFF_BUSYControlsAndMonitors
- record_name: register_map_xoff_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: Generators
- record_name: register_map_generators
- bitfield:
- - range: 0..0
- type: R
- - name: Wishbone
- record_name: wishbone_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: MRODmonitors
- record_name: regmap_mrod_monitor
- bitfield:
- - range: 0..0
- type: R
-
-#Bar0 contains the registers dedicated to Wupper. Please only edit registers in Bar2
-#Registers in this group will not be generated with WupperCodeGen
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- #- name: DMA_FIFO_FLUSH
- # type: T
- # bitfield:
- # - range: any
- # desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- offset: 0x420
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
- - name: BUSY_THRESHOLD_ASSERT
- type: W
- desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
- default: 0x6400000
- bitfield:
- - range: 63..0
-
- - name: BUSY_THRESHOLD_NEGATE
- type: W
- desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
- default: 0x6E00000
- bitfield:
- - range: 63..0
-
- - name: BUSY_STATUS
- type: R
- bitfield:
- - range: 0
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
- - name: PC_PTR_GAP
- type: W
- desc: This is the minimum value that the pc_pointer in a descriptor has to decrease in order to flip the evencycle_pc bit
- default: 0x1000000
- bitfield:
- - range: 63..0
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: SW_POINTER
- desc: Pointer controlled by the software, indicating read or write status for circular DMA
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: FROMHOST
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: FW_POINTER
- desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
-
-
-#Bar1 contains the registers dedicated to the Wupper interrupg controller.
-#Please only edit registers in Bar2.
-#Registers in this group will not be generated with WupperCodeGen
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 16
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-#Bar 2 contains application specific registers, used in the example application.
-#Registers in this group (and it's referenced subroups) will be generated with
-#WupperCodeGen for wupper Firmware, Software and Documentation
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x5000
- - ref: GBTWrapperControls
- offset: 0x6000
- - ref: GBTWrapperMonitors
- offset: 0x7000
- - ref: TTCBUSYControlsAndMonitors
- offset: 0x8000
- - ref: XOFF_BUSYControlsAndMonitors
- offset: 0x8800
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x9000
- - ref: Generators
- offset: 0xA000
- - ref: Wishbone
- offset: 0xC000
- - ref: ITK_STRIPS_CTRL # ITk strips global controls
- offset: 0xD000
- - ref: MRODregisters
- offset: 0xF000
- - ref: MRODmonitors
- offset: 0xF800
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned({{ tree.version|version }},16))
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- #- name: BOARD_ID_SVN
- # bitfield:
- # - range: 15..0
- # value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- # desc: OBSOLETE Board ID SVN Revision
-
- - name: GIT_COMMIT_TIME
- offset: 0x30
- bitfield:
- - range: 39..0
- value: COMMIT_DATETIME
- desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_TAG
- bitfield:
- - range: 63..0
- value: GIT_TAG(63 downto 0)
- desc: String containing the current GIT TAG
-
- - name: GIT_COMMIT_NUMBER
- bitfield:
- - range: 31..0
- value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
- desc: Number of GIT commits after current GIT_TAG
-
- - name: GIT_HASH
- bitfield:
- - range: 31..0
- value: GIT_HASH(159 downto 128)
- desc: Short GIT hash (32 bit)
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT or FULL mode Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): FLX709, VC709
- - 710 (0x2c6): FLX710, HTG710
- - 711 (0x2c7): FLX711, BNL711
- - 712 (0x2c8): FLX712, BNL712
- - 128 (0x080): FLX128, VCU128
-
- #- name: GBT_MAPPING
- # bitfield:
- # - range: 7..0
- # desc: |
- # OBSOLETE CXP-to-GBT mapping:
- # 0: NORMAL CXP1 1-12 CXP2 13-24
- # 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- offset: 0xc0
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST_GENERATE_TTC_EMU
- type: R
- bitfield:
- - range: 1
- type: R
- desc: 1 when TTC emulator is generated
-
- #- range: 0
- # type: R
- # name: TTC_TEST_MODE
- # desc: OBSOLETE 1 when TTC Test mode is anabled
-
- #- name: CR_INTERNAL_LOOPBACK_MODE
- # type: R
- # bitfield:
- # - range: 0
- # desc: OBSOLETE 1 when Central Router internal loopback mode is enabled
-
- - offset: 0x100
- ref: INCLUDE_EGROUPS
-
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- #- name: DEBUG_MODE
- # type: R
- # bitfield:
- # - range: 0
- # desc: |
- # OBSOLETE
- # 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- # 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- offset: 0x190
- bitfield:
- - range: 3..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
- 3: FEI4 mode
- 4: ITK Pixel
- 5: ITK Strip
- 6: FELIG
- 7: FULL mode emulator
- 8: FELIX_MROD mode
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
- - name: BLOCKSIZE
- type: R
- desc: Number of bytes in a block
- bitfield:
- - range: 15..0
-
- - name: PCIE_ENDPOINT
- type: R
- desc: Indicator of the PCIe endpoint on BNL71x cards with two endpoints. 0 or 1
- bitfield:
- - range: 0
- value: std_logic_vector(to_unsigned(PCIE_ENDPOINT, 1))
-
- - name: CHUNK_TRAILER_32B
- type: R
- desc: Indicator that the chunk trailer is in the new 32-bit format
- bitfield:
- - range: 0
-
- - name: NUMBER_OF_PCIE_ENDPOINTS
- type: R
- desc: Number of PCIe endpoints on the card. The BNL71x cards have 2 endpoints
- bitfield:
- - range: 1..0
-
-INCLUDE_EGROUPS:
- number: 7
- entries:
- - format_name: INCLUDE_EGROUP_{index}
- name: INCLUDE_EGROUP
- type_name: INCLUDE_EGROUP
- type: R
- bitfield:
- - range: 8
- name: FROMHOST_02
- desc: FromHost EPROC02 is included in this EGROUP
- - range: 7
- name: FROMHOST_04
- desc: FromHost EPROC04 is included in this EGROUP
- - range: 6
- name: FROMHOST_08
- desc: FromHost EPROC8 is included in this EGROUP
- - range: 5
- name: FROMHOST_HDLC
- desc: FromHost HDLC is included in this EGROUP
- - range: 4
- name: TOHOST_02
- desc: ToHost EPROC02 is included in this EGROUP
- - range: 3
- name: TOHOST_04
- desc: ToHost EPROC04 is included in this EGROUP
- - range: 2
- name: TOHOST_08
- desc: ToHost EPROC08 is included in this EGROUP
- - range: 1
- name: TOHOST_16
- desc: ToHost EPROC16 is included in this EGROUP
- - range: 0
- name: TOHOST_HDLC
- desc: ToHost HDLC is included in this EGROUP
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: IC_FROMHOST_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- #- ref: IC_FIFOS
- # desc: See Central Router Doc
- # offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
- offset: 0x1700
-
- #- name: CR_FALLBACK_OPTIONS
- # desc: OBSOLETE Julias personal register with Hello Kitty options
- # type: W
- # bitfield:
- # - range: 63..0
-
- - name: CR_TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- offset: 0x1a10
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - name: CR_REVERSE_10B
- desc: Reverse 10-bit word of elink data
- type: W
- bitfield:
- - range: 1
- name: FROMHOST
- default: 1
- desc: |
- 1: Serialize 10-bit word in FromHost EPROCS MSB first
- 0: Serialize 10-bit word in FromHost EPROCS LSB first
- - range: 0
- name: TOHOST
- default: 1
- desc: |
- 1: Receive 10-bit word in ToHost EPROCS, MSB first
- 0: Receive 10-bit word in ToHost EPROCS, LSB first
-
- - name: CR_LTDB_TTC_DELAY
- desc: Controls TTC BCR delay in LTDB mode firmware
- type: W
- bitfield:
- - range: 7
- name: EGROUP4_EPATH6
- default: 1
- desc: |
- Egroup 4, Epath 6
- 1: Half a clock delay
- 0: no delay
- - range: 6
- name: EGROUP4_EPATH5
- default: 1
- desc: |
- Egroup 4, Epath 5
- 1: Half a clock delay
- 0: no delay
- - range: 5
- name: EGROUP4_EPATH4
- default: 1
- desc: |
- Egroup 4, Epath 4
- 1: Half a clock delay
- 0: no delay
- - range: 4
- name: EGROUP4_EPATH3
- default: 1
- desc: |
- Egroup 4, Epath 3
- 1: Half a clock delay
- 0: no delay
- - range: 3
- name: EGROUP4_EPATH0
- default: 1
- desc: |
- Egroup 4, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 2
- name: EGROUP3
- default: 1
- desc: |
- Egroup 3, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 1
- name: EGROUP2
- default: 1
- desc: |
- Egroup 2, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 0
- name: EGROUP1
- default: 1
- desc: |
- Egroup 1, Epath 0
- 1: Half a clock delay
- 0: no delay
-# - ref: CR_XOFF_CTRL
-# offset: 0x2800
-# desc: Configure FromHost Xoff
-
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x3000
- #- name: CR_STATIC_CONFIGURATION
- # type: R
- # bitfield:
- # - range: 0
- #- ref: CR_DEFAULT_EPROC_ENA_G
- #- ref: CR_DEFAULT_EPROC_ENCODING_G
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- offset: 0x3410
- bitfield:
- - range: 31..0
-
- - name: ELINK_REALIGNMENT
- type: W
- bitfield:
- - range: any
- name: CLEAR_REALIGNMENT_STATUS
- type: T
- value: 1
- desc: Clears the ELINK Realignment event flags
- - range: 0
- name: ENABLE
- default: 1
- desc: Enable realignment mechanism in 8b10b E-Links after illegal character reception.
-
- - ref: ELINK_REALIGNMENT_STATUS_GEN
-
- - name: FULLMODE_32B_SOP
- type: W
- desc: When set to 1, use 32-bit 0x0000003C as start of chunk, otherwise only 8-bit 0x3C (FULL mode only)
- bitfield:
- - range: 0
- default: 0
-
-
-CR_GBT_CTRL:
- number: 24
- bitfield:
- - range: 50..0
- type: W
- generate: GBT_NUM > {index:1}
- entries:
- - ref: EGROUP_TOHOST
- - ref: EGROUP_FROMHOST
-
-EGROUP_TOHOST:
- number: 7
- format_name: GBT{index:02}
- name: GBT
- entries:
- - name: TOHOST
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_TOHOST_EGROUP_CTRL
- bitfield:
- - range: 58..51
- name: INSTANT_TIMEOUT_ENA
- default: 0x0
- desc: instantly initiate a timeout for the given epath
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..31
- name: MAX_CHUNK_LEN
- default: MAX_CHUNK_LEN_array
- desc: set the maximum length of a chunk, 0 disables truncation
- - range: 30..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- default:
- - PATH_ENCODING_array(0)
- - PATH_ENCODING_array(1)
- - PATH_ENCODING_array(2)
- - PATH_ENCODING_array(3)
- - PATH_ENCODING_array(4)
- - PATH_ENCODING_array(5)
- - PATH_ENCODING_array(6)
-
- - range: 14..0
- name: EPROC_ENA
- desc: Enable bits per EPROC
- default:
- - EPROC_ENA_bits_array(0)
- - EPROC_ENA_bits_array(1)
- - EPROC_ENA_bits_array(2)
- - EPROC_ENA_bits_array(3)
- - EPROC_ENA_bits_array(4)
- - EPROC_ENA_bits_array(5)
- - EPROC_ENA_bits_array(6)
-
-EGROUP_FROMHOST:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FROMHOST
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_FROMHOST_EGROUP_CTRL
- bitfield:
- - range: 54..47
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 46..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- greater than 3: TTC mode, see CentralRouter doc
- default:
- - FROMHOST_PATH_ENCODING_array(0)
- - FROMHOST_PATH_ENCODING_array(1)
- - FROMHOST_PATH_ENCODING_array(2)
- - FROMHOST_PATH_ENCODING_array(3)
- - FROMHOST_PATH_ENCODING_array(4)
- - FROMHOST_PATH_ENCODING_array(5)
- - FROMHOST_PATH_ENCODING_array(6)
- - range: 14..0
- desc: Enable bits per EPROC
- name: EPROC_ENA
-
-# ----------------------- ITk strips link configuration start -----------------------
-
-ITK_STRIPS_CTRL:
- entries:
- - name: GLOBAL_STRIPS_CONFIG
- desc: Synchronous trigger for all LCB links on device
- type: W
- bitfield:
- - range: 15..11
- type: W
- name: TEST_MODULE_MASK
- desc: (for tests only) contains R3 mask for the simulated trigger data
- default: 0x0
- - range: 10..4
- type: W
- name: TEST_R3L1_TAG
- desc: (for tests only) contains R3 or L1 tag for the simulated trigger data
- default: 0x0
- - range: 1
- type: W
- name: TTC_GENERATE_GATING_ENABLE
- desc: Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR.
- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- (See also BC_START, and BC_STOP fields)
- default: 0x0
- - name: GLOBAL_TRICKLE_TRIGGER
- type: T
- bitfield:
- - range: any
- value: 1
- desc: writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
-
- - ref: ITK_STRIPS_GBT
-
- - name: STRIPS_R3_TRIGGER
- type: T
- bitfield:
- - range: any
- value: 1
- desc: (for tests only) simulate R3 trigger (issues 4-5 sequential triggers)
- - name: STRIPS_L1_TRIGGER
- type: T
- bitfield:
- - range: any
- desc: (for tests only) simulate L1 trigger (issues 4-5 sequential triggers)
- value: 1
- - name: STRIPS_R3L1_TRIGGER
- type: T
- bitfield:
- - range: any
- desc: (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)
- value: 1
-
-ITK_STRIPS_GBT:
- number: 4
- format_name: STRIPS
- generate: (GBT_NUM > {index:1} and FIRMWARE_MODE = 5)
- entries:
- - ref: ITK_STRIPS_LCB_LINKS
- - ref: ITK_STRIPS_R3L1_LINKS
-
-ITK_STRIPS_LCB_LINKS:
- number: 4
- format_name: ITK_STRIPS_LCB_LINKS_{index:02}
- type_name: ITK_LCB_LINK
- entries:
- - name: LCB
- format_name: CR_{parent}_{name}_{index}
- type_name: LCB_CTRL
- desc: Determines LCB link configuration
- type: W
- bitfield:
- - range: 49..38
- type: W
- name: L0A_BCR_DELAY
- default: 0x0
- desc: TTC BCR signal will be delayed by this many BCs
- - range: 37..34
- type: W
- name: L0A_FRAME_DELAY
- default: 0x0
- desc: |
- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- - range: 33..32
- type: W
- name: FRAME_PHASE
- default: 0x0
- desc: phase of LCB frame with respect to TTC BCR signal
- - range: 31..20
- type: W
- name: TRICKLE_BC_START
- default: 0x0
- desc: Determines the start of the allowed BC interval for low-priority LCB frames
- - range: 19..8
- type: W
- name: TRICKLE_BC_STOP
- default: 0x0
- desc: Determines the end of the allowed BC interval for low-priority LCB frames
- - range: 5..4
- type: W
- name: LCB_DESTINATION_MUX
- default: 0x0
- desc: |
- Determines where the elink data is sent to:
- 00: command decoder (use same command encoding format as trickle configuration)
- 01: trickle memory (see phase2 documentation for command encoding format)
- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- 11: (invalid, don't use)
- - range: 3
- type: W
- name: TRICKLE_TRIG_RUN
- default: 0x0
- desc: |
- if enabled, trickle configuration is sent out continuously to the front-end
- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- - range: 2
- type: W
- name: TTC_L0A_ENABLE
- default: 0x0
- desc: enable generating L0A frames in response to TTC system signals
- - range: 0
- type: W
- name: TTC_GENERATE_GATING_ENABLE
- default: 0x0
- desc: |
- enables generating trickle gating signal in response to TTC BCR.
- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- (See also BC_START, and BC_STOP fields)
- - name: TRICKLE_TRIGGER
- format_name: CR_{parent}_{name}_{index}
- type_name: TRICKLE_TRIGGER
- type: T
- bitfield:
- - range: any
- desc: writing to this register issues a single trickle trigger
- value: 1
- - name: TRICKLE_MEMORY_CONFIG
- format_name: CR_{parent}_{name}_{index}
- type_name: LCB_TRICKLE_CONFIG
- desc: Trickle trigger configuration
- type: W
- bitfield:
- - range: any
- type: T
- name: MOVE_WRITE_PTR
- value: 1
- desc: |
- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- - range: 47..32
- type: W
- name: WRITE_PTR
- default: 0x0
- desc: Trickle configuration memory write pointer
- - range: 31..16
- type: W
- name: VALID_DATA_START
- default: 0x0
- desc: Start address of trickle configuration in trickle memory
- - range: 15..0
- type: W
- name: VALID_DATA_END
- default: 0x0
- desc: Stop address of trickle configuration in trickle memory (last valid byte)
- - name: MODULE_MASK_F_C
- format_name: CR_{parent}_{name}_{index}
- type_name: HCC_ABC_MASK_E_C
- type: W
- desc: |
- Disables register commands addressed to masked HCC*/ABC* chips. Register commands for which
- corresponding mask bit is set to '1' will be ignored by the command encoder.
- This is useful to quickly disable trickle configuration for selected
- modules without overwriting the entire trickle configuratrion memory.
- bitfield:
- - range: 63..48
- type: W
- name: HCC_MASK
- default: 0x0
- desc: |
- HCC* module mask
- - range: 47..32
- type: W
- name: ABC_MASK_HCC_E
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0xE
- mask(i) <=> (abc_id = i)
- - range: 31..16
- type: W
- name: ABC_MASK_HCC_D
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0xD
- mask(i) <=> (abc_id = i)
- - range: 15..0
- type: W
- name: ABC_MASK_HCC_C
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0xC
- mask(i) <=> (abc_id = i)
- - name: ABC_MODULE_MASK_B_8
- format_name: CR_{parent}_{name}_{index}
- type_name: LCB_ABC_MASK_B_8
- type: W
- desc: |
- Disables register commands addressed to masked ABC* chips. Register commands for which
- corresponding mask bit is set to '1' will be ignored by the command encoder.
- This is useful to quickly disable trickle configuration for selected
- modules without overwriting the entire trickle configuratrion memory.
- bitfield:
- - range: 63..48
- type: W
- name: ABC_MASK_HCC_B
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0xB
- mask(i) <=> (abc_id = i)
- - range: 47..32
- type: W
- name: ABC_MASK_HCC_A
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0xA
- mask(i) <=> (abc_id = i)
- - range: 31..16
- type: W
- name: ABC_MASK_HCC_9
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x9
- mask(i) <=> (abc_id = i)
- - range: 15..0
- type: W
- name: ABC_MASK_HCC_8
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x8
- mask(i) <=> (abc_id = i)
- - name: ABC_MODULE_MASK_7_4
- format_name: CR_{parent}_{name}_{index}
- type_name: LCB_ABC_MASK_7_4
- type: W
- desc: |
- Disables register commands addressed to masked ABC* chips. Register commands for which
- corresponding mask bit is set to '1' will be ignored by the command encoder.
- This is useful to quickly disable trickle configuration for selected
- modules without overwriting the entire trickle configuratrion memory.
- bitfield:
- - range: 63..48
- type: W
- name: ABC_MASK_HCC_7
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x7
- mask(i) <=> (abc_id = i)
- - range: 47..32
- type: W
- name: ABC_MASK_HCC_6
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x6
- mask(i) <=> (abc_id = i)
- - range: 31..16
- type: W
- name: ABC_MASK_HCC_5
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x5
- mask(i) <=> (abc_id = i)
- - range: 15..0
- type: W
- name: ABC_MASK_HCC_4
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x4
- mask(i) <=> (abc_id = i)
- - name: ABC_MODULE_MASK_3_0
- format_name: CR_{parent}_{name}_{index}
- type_name: LCB_ABC_MASK_3_0
- type: W
- desc: |
- Disables register commands addressed to masked ABC* chips. Register commands for which
- corresponding mask bit is set to '1' will be ignored by the command encoder.
- This is useful to quickly disable trickle configuration for selected
- modules without overwriting the entire trickle configuratrion memory.
- bitfield:
- - range: 63..48
- type: W
- name: ABC_MASK_HCC_3
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x3
- mask(i) <=> (abc_id = i)
- - range: 47..32
- type: W
- name: ABC_MASK_HCC_2
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x2
- mask(i) <=> (abc_id = i)
- - range: 31..16
- type: W
- name: ABC_MASK_HCC_1
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x1
- mask(i) <=> (abc_id = i)
- - range: 15..0
- type: W
- name: ABC_MASK_HCC_0
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x0
- mask(i) <=> (abc_id = i)
-
-
-ITK_STRIPS_R3L1_LINKS:
- number: 4
- format_name: ITK_R3L1_LINK_{index:02}
- type_name: ITK_R3L1_LINK
- entries:
- - name: R3L1
- format_name: CR_{parent}_{name}_{index:1}
- type_name: R3L1_CTRL
- desc: Determines R3L1 link configuration
- type: W
- bitfield:
- - range: 3..2
- type: W
- name: FRAME_PHASE
- default: 0x0
- desc: phase of R3L1 frame with respect to TTC BCR signal
- - range: 1
- type: W
- name: L1_ENABLE
- default: 0x0
- desc: enables sending TTC L1 signals to the front-end
- - range: 0
- type: W
- name: R3_ENABLE
- default: 0x0
- desc: enables sending RoI R3 signals to the front-end
-
-
-# ----------------------- ITk strips link configuration end -----------------------
-
-#CR_XOFF_CTRL:
-# number: 24
-# type: W
-# bitfield:
-# - range: 39..0
-# entries:
-# - name: FROMHOST_XOFF_ENABLE
-# format_name: FROMHOST_XOFF_ENABLE_{index:02}
-# desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
-# range: 39..0
-# default: 0
-# - name: FROMHOST_SOFT_XOFF
-# format_name: FROMHOST_SOFT_XOFF_{index:02}
-# desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
-# range: 39..0
-# default: 0
-
-
-#IC_FIFOS:
-# number: 24
-# format_name: IC_FROMHOST_TOHOST_FIFOS
-# entries:
-# - name: FROMHOST
-# format_name: IC_FROMHOST_FIFO_{index:02}
-# type_name: IC_FROMHOST_FIFO
-# type: W
-# generate: GBT_NUM > {index:1}
-# bitfield:
-# - range: any
-# type: T
-# value: not register_map_monitor_s.register_map_cr_monitor.IC_FROMHOST_FIFO({index}).FULL
-# name: WE
-# format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
-# desc: Any write to this register will trigger a write to the FIFO
-# - range: 8
-# type: R
-# name: FULL
-# format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
-# desc: Full flag of the fifo, do not write if 1
-# - range: 7..0
-# type: W
-# name: DATAIN
-# format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
-# desc: Data input of fifo
-# - name: TOHOST
-# format_name: IC_TOHOST_FIFO_{index:02}
-# type_name: IC_TOHOST_FIFO
-# type: W
-# generate: GBT_NUM > {index:1}
-# bitfield:
-# - range: any
-# type: T
-# value: not register_map_monitor_s.register_map_cr_monitor.IC_TOHOST_FIFO({index}).EMPTY
-# name: RE
-# format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
-# desc: Any write to this register will trigger a read enable from the fifo
-# - range: 8
-# type: R
-# name: EMPTY
-# format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
-# desc: Empty flag of the fifo, do not read if 1
-# - range: 7..0
-# type: R
-# name: DATAOUT
-# format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
-# desc: Data output of fifo
-
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 7
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 6
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 5
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 4
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 9
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 8
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 7
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 6
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
-
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- entries:
- - name: TOHOST
- type_name: CR_TOHOST_GBT_MON
- format_name: CR_{name}_GBT{index:02}_MON
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 58
- name: CROUTFIFO_PROG_FULL
- - range: 57
- name: WMFIFO_FULL
- - range: 56
- name: MINI_EGROUP_ALMOST_FULL
- - range: 55..48
- name: EPATH6_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP6
- - range: 47..40
- name: EPATH5_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP5
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
- - name: FROMHOST
- type_name: CR_FROMHOST_GBT_MON
- format_name: CR_{name}_GBT{index:02}_MON
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 40
- name: MINI_EGROUP_ALMOST_FULL
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
-
-ELINK_REALIGNMENT_STATUS_GEN:
- endpoints: 0, 1
- number: 12
- entries:
- - name: ELINK_REALIGNMENT_STATUS
- type_name: ELINK_REALIGNMENT_STATUS
- format_name: ELINK_REALIGNMENT_STATUS_{index:02}
- generate: GBT_NUM > {index:1}
- desc: |
- A realignment event due to an illegal 8b10b symbol has occurred.
- 1 bit per Epath.
- Clear status by writing to ELINK_REALIGNMENT.CLEAR_REALIGNMENT_STATUS
- bitfield:
- - range: 41..0
-
-
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0, 1
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 63..48
- name: RDDATA
- type: R
- desc: read data bus
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 0
- desc: write enable for the full mode emulator ram block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 35..0
- desc: read emu ram data
-
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 23..0
- desc: FULL mode CR enable array, every bit is one path
-
- - ref: PATH_HAS_STREAM_ID
-
-PATH_HAS_STREAM_ID:
- number: 24
- generate: GBT_NUM > {index:1}
- entries:
- - name: TOHOST
- format_name: LINK_{index:02}_HAS_STREAM_ID
- type_name: HAS_STREAM_ID
- type: W
- bitfield:
- - range: 55..48
- name: EGROUP6
- default: 0x0
- desc: EPATH (Wide mode) is associated with a STREAM ID
- - range: 47..40
- name: EGROUP5
- default: 0x0
- desc: EPATH (Wide mode) is associated with a STREAM ID
- - range: 39..32
- name: EGROUP4
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 31..24
- name: EGROUP3
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 23..16
- name: EGROUP2
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 15..8
- name: EGROUP1
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 7..0
- name: EGROUP0
- default: 0x0
- desc: EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_CHANNEL_DISABLE
- offset: 0x0400
- bitfield:
- - range: 47..0
- desc: Disable selected GBT or FULL mode channel
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE_SELECT
- offset: 0x0480
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_RXSLIDE_MANUAL
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_TXUSRRDY
- desc: TxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_RXUSRRDY
- desc: RxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_SOFT_RESET
- desc: SOFT_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTTX_RESET
- desc: GTTX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTRX_RESET
- desc: GTRX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 59..48
- name: QPLL_RESET
- desc: QPLL_RESET [11:0]
- - range: 47..0
- name: CPLL_RESET
- desc: CPLL_RESET [47:0]
-
- - name: GBT_SOFT_TX_RESET
- offset: 0x0500
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_SOFT_RX_RESET
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_ODD_EVEN
- desc: OddEven [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_TOPBOT
- desc: TopBot [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_TC_DLY_VALUE3
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [143:96]
-
- - name: GBT_TX_TC_DLY_VALUE4
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [191:144]
-
- - name: GBT_DATA_TXFORMAT1
- desc: DATA_TXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_TXFORMAT2
- desc: DATA_TXFORMAT [95:48]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT1
- desc: DATA_RXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT2
- desc: DATA_RXFORMAT [95:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_RESET
- desc: TX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_RESET
- desc: RX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_METHOD
- desc: TX time domain crossing method [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUTMUX_SEL
- desc: Descrambler output MUX selection [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TC_EDGE
- desc: Sampling edge selection for TX domain crossing [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for transmitter of GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_RXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for the receiver of the GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
- - name: GBT_TOHOST_FANOUT
- offset: 0x0700
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0x0
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_TOFRONTEND_FANOUT
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0x0
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
- - name: FULLMODE_AUTO_RX_RESET
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: Enable the Automatic RX Reset mechanism
- - range: 31..0
- name: TIMEOUT
- default: 0x00100000
- desc: Number of 40 MHz clock cycles until an unaligned link results in a reset pulse
-
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- desc: TX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXRESET_DONE
- desc: RX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXFSMRESET_DONE
- desc: TX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXFSMRESET_DONE
- desc: RX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_LOCK
- bitfield:
- - range: 59..48
- name: QPLL_LOCK
- desc: QPLL LOCK [11:0]
- - range: 47..0
- name: CPLL_LOCK
- desc: CPLL LOCK [47:0]
-
- - name: GBT_RXCDR_LOCK
- desc: RX CDR LOCK [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CLK_SAMPLED
- desc: clk sampled [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_HEADER
- desc: RX IS HEADER [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_DATA
- desc: RX IS DATA [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_HEADER_FOUND
- desc: RX HEADER FOUND [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUT_MUX_STATUS
- desc: GBT output mux status [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ERROR
- desc: Error flags [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GBT_TOPBOT_C
- desc: TopBot_c [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-TTCBUSYControlsAndMonitors:
- group: TTCBUSY
- desc: TTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: TTC_BUSY_ACCEPTED_G
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 2
- name: FULL
- type: R
- desc: TTC Emulator memory full indication
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
-
- - ref: TTC_DELAY
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the BUSY Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
- - name: TTC_EMU_CONTROL
- type: W
- bitfield:
- - range: 33
- name: BUSY_IN_ENABLE
- desc: Enable internal BUSY input to stop L1A on BUSY
- default: 1
- - range: 32..27
- name: BROADCAST
- desc: Broadcast data
- - range: 26
- name: ECR
- desc: Event counter reset
- - range: 25
- name: BCR
- desc: Bunch counter reset
- - range: 24
- name: L1A
- desc: Level 1 Accept
-
- - name: TTC_EMU_L1A_PERIOD
- type: W
- desc: L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
- bitfield:
- - range: 31..0
-
- - name: TTC_EMU_ECR_PERIOD
- type: W
- desc: ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
- bitfield:
- - range: 31..0
-
- - name: TTC_EMU_BCR_PERIOD
- type: W
- desc: BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
- bitfield:
- - range: 31..0
- default: 3564
-
- - name: TTC_EMU_LONG_CHANNEL_DATA
- type: W
- desc: Long channel data for the TTC emulator
- bitfield:
- - range: 31..0
-
- - name: TTC_EMU_RESET
- desc: Any write to this register resets the TTC Emulator to the default state.
- type: W
- bitfield:
- - range: any
- value: 1
- type: T
-
- - name: TTC_L1ID_MONITOR
- desc: Monitor L1ID and XL1ID.
- type: R
- bitfield:
- - range: 31..0
-
- - name: TTC_ECR_MONITOR
- desc: Counts the number of ECRs received from the TTC system, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_TTYPE_MONITOR
- desc: Counts the number of TType received from the TTC system, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_BCR_PERIODICITY_MONITOR
- desc: Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_BCR_COUNTER
- desc: Counts the number of times BCR is issued, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range: 30..27
- name: B_CHAN_DELAY
- type: W
- desc: Number of BC to delay the L1A distribution to the frontends
- - range: 26..15
- name: BCID_ONBCR
- type: W
- desc: BCID is set to this value when BCR arrives
- - range: 14
- name: BUSY_OUTPUT_STATUS
- type: R
- desc: Actual status of the BUSY LEMO output signal
- - range: 13
- name: ECR_BCR_SWAP
- default: 0
- desc: ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
- - range: 12
- name: BUSY_OUTPUT_INHIBIT
- default: 0
- desc: forces the Busy LEMO output to BUSY-OFF
- - range: 11
- name: TOHOST_RST
- desc: reset toHost in ttc decoder
- default: 0
- - range: 10
- name: TT_BCH_EN
- desc: trigger type enable / disable for TTC-ToHost
- default: 1
- - range: 9..2
- name: XL1ID_SW
- desc: set XL1ID value, the value to be set by XL1ID_RST signal
- default: 0x00
- - range: 1
- name: XL1ID_RST
- desc: giving a trigger signal to reset XL1ID value
- default: 0
- - range: 0
- name: MASTER_BUSY
- desc: L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range: 15..5
- name: TH_FF_COUNT
- desc: ToHostData Fifo counts
- - range: 4
- name: TH_FF_FULL
- desc: ToHostData Fifo status 1:full 0:not full
- - range: 3
- name: TH_FF_EMPTY
- desc: ToHostData Fifo status 1:empty 0:not empty
- - range: 2..0
- name: TTC_BIT_ERR
- desc: double bit, single bit and comm error in TTC data
-
-TTC_BUSY_ACCEPTED_G:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- entries:
- - name: TTC_BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
- type_name: TTC_BUSY_ACCEPTED
- bitfield:
- - range: 56..0
-
-
-
-TTC_DELAY:
- number: 48
- type: W
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Controls the TTC Fanout delay values
- bitfield:
- - range: 3..0
- default: 0
-
-XOFF_BUSYControlsAndMonitors:
- group: XOFF
- desc: XOFF Controls and Monitors, see table 2 of Busy specs manual
- endpoints: 0, 1
- entries:
- - name: XOFF_FM_CH_FIFO_THRESH_LOW
- type: W
- bitfield:
- - range: 3..0
- default: 0xB
- desc: |
- Controls the low threshold of the channel fifo in FULL mode on which
- an Xon will be asserted, bitfields control 4 MSB
- - name: XOFF_FM_CH_FIFO_THRESH_HIGH
- type: W
- bitfield:
- - range: 3..0
- default: 0xB
- desc: |
- Controls the high threshold of the channel fifo in FULL mode on which
- an Xoff will be asserted, bitfields control 4 MSB
- - name: XOFF_FM_LOW_THRESH_CROSSED
- desc: FIFO filled beyond the low threshold, 1 bit per channel
- type: R
- bitfield:
- - range: 23..0
- - name: XOFF_FM_HIGH_THRESH
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- desc: Writing this register will clear all CROSS_LATCHED bits
- type: T
- value: 1
- - range: 47..24
- type: R
- name: CROSS_LATCHED
- desc: FIFO filled beyond the high threshold, 1 latch bit per channel
- - range: 23..0
- type: R
- name: CROSSED
- desc: FIFO filled beyond the high threshold, 1 bit per channel
-
- - name: XOFF_FM_SOFT_XOFF
- type: W
- desc: Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
- bitfield:
- - range: 23..0
-
- - name: XOFF_ENABLE
- type: W
- desc: Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
- bitfield:
- - range: 23..0
-
- - name: DMA_BUSY_STATUS
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR_LATCH
- desc: Any write to this register clears TOHOST_BUSY_LATCHED
- - range: 4
- type: W
- name: ENABLE
- desc: Enable the DMA buffer on the server as a source of busy
- default: 0
- - range: 3
- type: R
- name: TOHOST_BUSY_LATCHED
- desc: A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => tohost_busy_latched_40_s)
- - range: 0
- type: R
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => tohost_busy_40_s)
-
- - name: FM_BUSY_CHANNEL_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- type: T
- value: 1
- desc: Any write to this register will clear the BUSY_LATCHED bits
- - range: 47..24
- type: R
- name: BUSY_LATCHED
- desc: one Indicates that the given FULL mode channel has received BUSY-ON
- - range: 23..0
- type: R
- name: BUSY
- desc: one Indicates that the given FULL mode channel is currently in BUSY state
-
- - name: BUSY_MAIN_OUTPUT_FIFO_THRESH
- type: W
- bitfield:
- - range: 24
- name: BUSY_ENABLE
- desc: Enable busy generation if thresholds are crossed
- default: 0
- - range: 23..12
- name: LOW
- desc: Low, Negate threshold of busy generation from main output fifo
- default: 0x3FF
- - range: 11..0
- name: HIGH
- desc: High, Assert threshold of busy generation from main output fifo
- default: 0x4FF
-
- - name: BUSY_MAIN_OUTPUT_FIFO_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCHED
- value: 1
- desc: Any write to this register will clear the
- type: T
- - range: 2
- type: R
- name: HIGH_THRESH_CROSSED_LATCHED
- desc: Main output fifo has been full beyond HIGH THRESHOLD, write to clear
- - range: 1
- type: R
- name: HIGH_THRESH_CROSSED
- desc: Main output fifo is full beyond HIGH THRESHOLD
- - range: 0
- type: R
- name: LOW_THRESH_CROSSED
- desc: Main output fifo is full beyond LOW THRESHOLD
- - ref: ELINK_BUSY_ENABLE
- - ref: XOFF_STATISTICS
-
-
-ELINK_BUSY_ENABLE:
- number: 24
- endpoints: 0
- type: W
- entries:
- - name: ELINK_BUSY_ENABLE
- format_name: ELINK_BUSY_ENABLE{index:02}
- type_name: ELINK_BUSY_ENABLE
- desc: Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- bitfield:
- - range: 56..0
- default: 0
-
-XOFF_STATISTICS:
- number: 24
- endpoints: 0,1
- type: R
- entries:
- - name: XOFF_PEAK_DURATION
- format_name: XOFF_PEAK_DURATION{index:02}
- type_name: XOFF_PEAK_DURATION
- desc: Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- bitfield:
- - range: 63..0
- - name: XOFF_TOTAL_DURATION
- format_name: XOFF_TOTAL_DURATION{index:02}
- type_name: XOFF_TOTAL_DURATION
- desc: Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- bitfield:
- - range: 63..0
- - name: XOFF_COUNT
- format_name: XOFF_COUNT{index:02}
- type_name: XOFF_COUNT
- desc: Total number of XOFF events per channel that occurred since a reset.
- bitfield:
- - range: 63..0
-
-
-
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
-
- - name: HK_MON_FMC
- type: W
- bitfield:
- - range: 1
- name: SI5345_LOL
- desc: Si5345 Loss Of Lock pin
- - range: 0
- name: SI5345_INTR
- desc: Si5345 Interrupt flagging chip change of status
-
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_SEL
- default: 0x1
- desc: |
- 1: LCLK
- 0: TTC
- - range: 2..1
- type: R
- name: MAIN_INPUT
- desc: |
- Main MMCM Oscillator Input
- 2: LCLK fixed
- 1: TTC fixed
- 0: selectable
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL-711 locked
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
-
- - name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
-
-
- #- name: SPI_WR
- # type: W
- # offset: 0x0400
- # bitfield:
- # - range: any
- # type: T
- # value: OBSOLETE not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- # name: SPI_WREN
- # desc: Any write to this register triggers an SPI Write
- # - range: 32
- # type: R
- # name: SPI_FULL
- # desc: OBSOLETE SPI FIFO Full
- # - range: 31..0
- # type: W
- # name: SPI_DIN
- # desc: OBSOLETE SPI WRITE Data
- #
- #- name: SPI_RD
- # type: T
- # bitfield:
- # - range: any
- # type: T
- # value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- # name: SPI_RDEN
- # desc: OBSOLETE Any write to this register pops the last SPI data from the FIFO
- # - range: 32
- # type: R
- # name: SPI_EMPTY
- # desc: OBSOLETE SPI FIFO Empty
- # - range: 31..0
- # type: R
- # name: SPI_DOUT
- # desc: OBSOLETE SPI READ Data
-
- - name: I2C_WR
- type: W
- offset: 0x420
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
-
- #- name: DEBUG_PORT_GBT
- # offset: 0x0500
- # type: W
- # bitfield:
- # - range: 6..0
- # desc: OBSOLETE Debug GBT data bit N (119..0) on SMA HTGx#3
-
- #- name: DEBUG_PORT_CLK
- # type: W
- # bitfield:
- # - range: 3..0
- # desc: OBSOLETE Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST
- offset: 0x0800
- type: W
- value: 1
- bitfield:
- - name: TRIGGER
- type: T
- range: any
- desc: Fire a test MSIx interrupt set in IRQ
- - name: IRQ
- type: W
- range: 3..0
- desc: Set this field to a value equal to the MSIX interrupt to be fired. The write triggers the interrupt immediately.
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
-
- - name: TACH_CNT
- type: R
- desc: Readout of the Fan tachometer speed of the BNL712 board
- bitfield:
- - range: 19..0
-
- - name: RXUSRCLK_FREQ
- type: W
- bitfield:
- - range: 38
- name: VALID
- type: R
- desc: Indicates that the frequency measurement is valid
- - range: 37..32
- name: CHANNEL
- type: W
- desc: Select the Transceiver channel to measure the clock from.
- - range: 31..0
- name: VAL
- type: R
- desc: Frequency in Hz of the selected channel
-
-
-Generators:
- group: GEN
- desc: Specific registers for Hardware based Generators
- endpoints: 0
- generate: EMU_GENERATE_REGS
- entries:
- - name: FELIG_L1ID_RESET
- type: W
- desc: Any write to this register clears the FELIG L1ID
- bitfield:
- - range: any
- type: T
- value: 1
- - ref: FELIG_DATA_GEN_CONFIG_ARR
- offset: 0x20
- - ref: FELIG_ELINK_CONFIG_ARR
- - ref: FELIG_ELINK_ENABLE_ARR
-
- - name: FELIG_GLOBAL_CONTROL
- type: W
- bitfield:
- - range: 63..36
- name: FAKE_L1A_RATE
- default: 0
- desc: Sets the internal fake L1 trigger rate. [25ns/LSB]
- - range: 35..14
- name: PICXO_OFFSET_PPM
- default: 0
- desc: When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
- - range: 12..12
- name: TRACK_DATA
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 11..11
- name: RXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 10..10
- name: TXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 9..9
- name: AUTO_RESET
- default: 0
- desc: FELIG GT core control. If set the GT core automatically resets on data error.
- - range: 8..8
- name: PICXO_RESET
- default: 0
- desc: FELIG GT core control. Manual PICXO reset.
- - range: 7..7
- name: GTTX_RESET
- default: 0
- desc: FELIG GT core control. Manual GT TX reset
- - range: 6..6
- name: CPLL_RESET
- default: 0
- desc: FELIG GT core control. Manual CPLL reset.
- - range: 5..0
- name: X3_X4_OUTPUT_SELECT
- default: 0
- desc: X3/X4 SMA output source select.
-
- - ref: FELIG_LANE_CONFIG_ARR
- - ref: FELIG_MON_TTC_0_ARR
- - ref: FELIG_MON_TTC_1_ARR
- - ref: FELIG_MON_COUNTERS_ARR
- - ref: FELIG_MON_FREQ_ARR
-
- - name: FELIG_MON_FREQ_GLOBAL
- type: W
- bitfield:
- - range: 63..32
- name: XTAL_100MHZ
- default: 0
- desc: FELIG local oscillator frequency[Hz].
- - range: 31..0
- name: CLK_41_667MHZ
- desc: FELIG PCIE MGTREFCLK frequency[Hz].
-
- - ref: FELIG_MON_L1A_ID_ARR
- - ref: FELIG_MON_PICXO_ARR
-
- - name: FELIG_RESET
- type: W
- bitfield:
- - range: 63..48
- name: LB_FIFO
- default: 0
- desc: One bit per lane. When set to 1, resets all loopback FIFOs.
- - range: 47..24
- name: FRAMEGEN
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG link checking logic.
- - range: 23..0
- name: LANE
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG lane logic.
-
- - name: FELIG_RX_SLIDE_RESET
- type: W
- bitfield:
- - range: 23..0
- default: 0
- desc: One bit per lane. When set to 1, resets the gbt rx slide counter.
-
- - ref: FELIG_ITK_STRIPS_DATA_GEN_CONFIG_ARR
- - ref: FELIG_MON_ITK_STRIPS_ARR
-
- - name: FMEMU_EVENT_INFO
- type: R
- offset: 0x1800
- bitfield:
- - range: 63..32
- name: L1ID
- default: 0
- desc: 32b field to show L1ID
- - range: 31..0
- name: BCID
- default: 0
- desc: 32b field to show BCID
-
- - name: FMEMU_COUNTERS
- type: W
- bitfield:
- - range: 63..48
- name: WORD_CNT
- default: 32
- desc: Number of 32b words in one chunk
- - range: 47..32
- name: IDLE_CNT
- default: 3
- desc: Minimum number of idles between chunks
- - range: 31..16
- name: L1A_CNT
- default: 256
- desc: Number of chunks to send if not in TTC mode
- - range: 15..8
- name: BUSY_TH_HIGH
- default: 20
- desc: Assert BUSY-ON above this threshold
- - range: 7..0
- name: BUSY_TH_LOW
- default: 15
- desc: De-assert BUSY-ON below this threshold
-
- - name: FMEMU_CONTROL
- type: W
- bitfield:
- - range: 63..56
- type: W
- name: L1A_BITNR
- default: 48
- desc: Bitfield for L1A in TTC frame
- - range: 55..48
- type: W
- name: XONXOFF_BITNR
- default: 32
- desc: Bitfield for Xon/Xoff in TTC frame
- - range: 47..47
- type: W
- name: EMU_START
- default: 0
- desc: Start emulator functionality
- - range: 46..46
- type: W
- name: TTC_MODE
- default: 0
- desc: Control the emulator by TTC input or by RegMap (1/0)
- - range: 45..45
- type: W
- name: XONXOFF
- default: 1
- desc: Enable Xon/Xoff functionality (1/0)
- - range: 44..44
- type: W
- name: INLC_CRC32
- default: 0
- desc: |
- 0: No checksum
- 1: Append the data with a CRC32
- - range: 43..43
- type: W
- name: BCR
- default: 0
- desc: Reset BCID to 0
- - range: 42..42
- type: W
- name: ECR
- default: 0
- desc: Reset L1ID to 0
- - range: 41..41
- type: W
- name: CONSTANT_CHUNK_LENGTH
- default: 0
- desc: |
- Data source select
- 0: Random chunk length
- 1: Constant chunk length
- - range: 40..32
- type: R
- name: INT_STATUS_EMU
- default: 0
- desc: Read internal status emulator
- - range: 16
- type: W
- name: FFU_FM_EMU_T
- default: 0
- desc: For Future Use (trigger registers)
- - range: 0
- type: W
- name: FE_BUSY_ENABLE
- default: 1
- desc: Enable the BUSY mechanism if L1A counter passes threshold
-
- - name: FMEMU_RANDOM_RAM_ADDR
- type: W
- desc: Controls the address of the ramblock for the random number generator
- bitfield:
- - range: 9..0
- - name: FMEMU_RANDOM_RAM
- type: W
- bitfield:
- - range: any
- type: T
- name: WE
- value: 1
- desc: Any write to this register (DATA) triggers a write to the ramblock
- - range: 39..16
- name: CHANNEL_SELECT
- value: 0xFFFFFF
- desc: Enable write enable only for the selected channel
- - range: 15..0
- name: DATA
- type: W
- desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
- - name: FMEMU_RANDOM_CONTROL
- type: W
- desc: Controls the random chunk length generator
- bitfield:
- - name: SELECT_RANDOM
- range: 20
- desc: 1 enables the random chunk length, 0 uses a constant chunk length
- default: 0
- - name: SEED
- range: 19..10
- desc: Seed for the random number generator, should not be 0
- default: 0x200
- - name: POLYNOMIAL
- range: 9..0
- desc: POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
- default: 0x240
-
- - name: FMEMU_CONFIG_WRADDR
- type: W
- bitfield:
- - range: 9..0
- value: 0
- desc: write enable for the FMEmu ram block
-
- - name: FMEMU_CONFIG
- type: W
- bitfield:
- - range: any
- type: T
- name: WE
- value: 1
- desc: Any write to register WRDATA triggers a write to the ramblock
- - range: 55..32
- name: CHANNEL_SELECT
- value: 0xFFFFFF
- desc: Enable write enable only for the selected channel
- - range: 31..0
- name: WRDATA
- type: W
- desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
-
-
-#Registers that are replicated 24 times under Generators:
-FELIG_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_DATA_GEN_CONFIG
- format_name: FELIG_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_DATA_GEN_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: USERDATA
- range: 63..48
- default: 0
- desc: Sets static payload word. When PATTERN_SEL=1.
- - name: CHUNK_LENGTH
- range: 47..32
- default: 0
- desc: FELIG data generator chunk-length in bytes.
- - name: RESET
- range: 19..15
- default: 0
- desc: FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- - name: SW_BUSY
- range: 14..10
- default: 0
- desc: FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- - name: DATA_FORMAT
- range: 9..5
- default: 0
- desc: FELIG data generator format. 0:8b10b, 1:direct.
- - name: PATTERN_SEL
- range: 4..0
- default: 0
- desc: FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
-
-FELIG_ELINK_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_CONFIG
- format_name: FELIG_ELINK_CONFIG_{index:02}
- type_name: FELIG_ELINK_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: ENDIAN_MOD
- range: 39..35
- default: 0
- desc: FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- - name: INPUT_WIDTH
- range: 34..30
- default: 0
- desc: FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- - name: OUTPUT_WIDTH
- range: 9..0
- default: 0
- desc: FELIG elink data output width.
-
-FELIG_ELINK_ENABLE_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_ENABLE
- format_name: FELIG_ELINK_ENABLE_{index:02}
- type_name: FELIG_ELINK_ENABLE
- desc: FELIG specific configuration registers
- bitfield:
- - range: 39..0
- default: 0
- desc: FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
-
-FELIG_LANE_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_LANE_CONFIG
- format_name: FELIG_LANE_CONFIG_{index:02}
- type_name: FELIG_LANE_CONFIG
- desc: FELIG specific configuration registers
- bitfield:
- - name: B_CH_BIT_SEL
- range: 63..42
- default: 0
- desc: When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- - name: A_CH_BIT_SEL
- range: 41..35
- default: 0
- desc: Selects the bit from the received FELIX data from which to extract the L1A.
- - name: LB_FIFO_DELAY
- range: 34..30
- default: 0
- desc: When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- - name: ELINK_SYNC
- range: 7..7
- default: 0
- desc: When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- - name: PICXO_OFFEST_EN
- range: 6..6
- default: 0
- desc: FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- - name: PI_HOLD
- range: 5..5
- default: 0
- desc: FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- - name: GBT_LB_ENABLE
- range: 4..4
- default: 0
- desc: FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- - name: GBH_LB_ENABLE
- range: 3..3
- default: 0
- desc: FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- - name: L1A_SOURCE
- range: 2..2
- default: 0
- desc: FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- - name: GBT_EMU_SOURCE
- range: 1..1
- default: 0
- desc: FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- - name: FG_SOURCE
- range: 0..0
- default: 0
- desc: FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
-
-FELIG_MON_TTC_0_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_0
- format_name: FELIG_MON_TTC_0_{index:02}
- type_name: FELIG_MON_TTC_0
- desc: FELIG specific configuration registers
- bitfield:
- - name: L1ID
- range: 63..40
- default: 0
- desc: Live TTC data monitor.
- - name: XL1ID
- range: 39..32
- default: 0
- desc: Live TTC data monitor.
- - name: BCID
- range: 31..20
- default: 0
- desc: Live TTC data monitor.
- - name: RESERVED0
- range: 19..16
- default: 0
- desc: Live TTC data monitor.
- - name: LEN
- range: 15..8
- default: 0
- desc: Live TTC data monitor.
- - name: FMT
- range: 7..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_TTC_1_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_1
- format_name: FELIG_MON_TTC_1_{index:02}
- type_name: FELIG_MON_TTC_1
- desc: FELIG specific configuration registers
- bitfield:
- - name: RESERVED1
- range: 63..48
- default: 0
- desc: Live TTC data monitor.
- - name: TRIGGER_TYPE
- range: 47..32
- default: 0
- desc: Live TTC data monitor.
- - name: ORBIT
- range: 31..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_COUNTERS_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_COUNTERS
- format_name: FELIG_MON_COUNTERS_{index:02}
- type_name: FELIG_MON_COUNTERS
- desc: FELIG specific configuration registers
- bitfield:
- - name: SLIDE_COUNT
- range: 63..32
- default: 0
- desc: Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- - name: FC_ERROR_COUNT
- range: 31..0
- default:
- desc: When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
-
-FELIG_MON_FREQ_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_FREQ
- format_name: FELIG_MON_FREQ_{index:02}
- type_name: FELIG_MON_FREQ
- desc: FELIG specific configuration registers
- bitfield:
- - name: TX
- range: 63..32
- default: 0
- desc: FELIG regenerated TX clock frequency[Hz].
- - name: RX
- range: 31..0
- default: 0
- desc: FELIG recovered RX clock frequency[Hz].
-
-FELIG_MON_L1A_ID_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_L1A_ID
- format_name: FELIG_MON_L1A_ID_{index:02}
- type_name: FELIG_MON_L1A_ID
- desc: FELIG specific configuration registers
- bitfield:
- - range: 31..0
- default: 0
- desc: FELIG's last L1 ID.
-
-FELIG_MON_PICXO_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_PICXO
- format_name: FELIG_MON_PICXO_{index:02}
- type_name: FELIG_MON_PICXO
- desc: FELIG specific configuration registers
- bitfield:
- - name: VLOT
- range: 53..32
- default: 0
- desc: Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- - name: ERROR
- range: 20..0
- default: 0
- desc: Value indicates RX to TX frequency tracking error.
-
-FELIG_ITK_STRIPS_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG
- format_name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG
- desc: ITk Strips emulator specific configuration test registers
- bitfield:
- - name: ITKS_FIFO_CTL
- range: 19..17
- default: 0
- desc: data fifo control 2:rst 1:rd 0:wr.
- - name: ITKS_FIFO_DATA
- range: 16..0
- default: 0
- desc: itks emu data 16:last word 15-0:data word
-
-FELIG_MON_ITK_STRIPS_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_ITK_STRIPS
- format_name: FELIG_MON_ITK_STRIPS_{index:02}
- type_name: FELIG_MON_ITK_STRIPS
- desc: ITk Strips emulator specific status registers
- bitfield:
- - name: ITKS_FIFO_STATUS
- range: 2..0
- default: 0
- desc: data fifo status 2:write done 1:full 0:empty.
-
-
-
-Wishbone:
- desc: Wishbone
- endpoints: 0
- entries:
- - name: WISHBONE_CONTROL
- type: W
- bitfield:
- - range: 32
- name: WRITE_NOT_READ
- desc: wishbone write command wishbone read command
- - range: 31..0
- name: ADDRESS
- desc: Slave address for Wishbone bus
- - name: WISHBONE_WRITE
- type: T
- bitfield:
- - range: any
- type: T
- value: 1
- name: WRITE_ENABLE
- desc: Any write to this register triggers a write to the Wupper to Wishbone fifo
- - range: 32
- name: FULL
- type: R
- - range: 31..0
- name: DATA
- type: W
- - name: WISHBONE_READ
- type: T
- bitfield:
- - range: any
- type: T
- value: 1
- name: READ_ENABLE
- desc: Any write to this register triggers a read from the Wishbone to Wupper fifo
- - range: 32
- name: EMPTY
- type: R
- desc: Indicates that the Wishbone to Wupper fifo is empty
- - range: 31..0
- name: DATA
- type: R
- desc: Wishbone read data
- - name: WISHBONE_STATUS
- type: R
- bitfield:
- - range: 4
- name: INT
- desc: interrupt
- - range: 3
- name: RETRY
- desc: Interface is not ready to accept data cycle should be retried
- - range: 2
- name: STALL
- desc: When pipelined mode slave can't accept additional transactions in its queue
- - range: 1
- name: ACKNOWLEDGE
- desc: Indicates the termination of a normal bus cycle
- - range: 0
- name: ERROR
- desc: Address not mapped by the crossbar
-
-MRODregisters:
- group: MROD_CONTROL
- desc: Specific registers for MROD
- endpoints: 0
- generate: MROD_GENERATE_REGS
- entries:
- - name: MROD_CTRL
- type: W
- bitfield:
- - range: 15..8
- name: OPTIONS
- default: 0
- desc: Extra options for MROD
- - range: 7..7
- name: ENASPARE1
- default: 0
- desc: Enable spare1
- - range: 6..6
- name: ENAMANSLIDE
- default: 0
- desc: Enable Manual Slide in Rx Locking
- - range: 5..5
- name: ENAPASSALL
- default: 0
- desc: Enable PassAll in EmptySuppress
- - range: 4..4
- name: ENATXCOUNT
- default: 0
- desc: Enable SimpleCount in TxDriver for locking
- - range: 3..0
- name: GOLTESTMODE
- default: 0
- desc: |
- GOL Test Mode (emulate CSM):
- 0: Run Data Emulator when 1; 0: stop, load emulator fifo
- 1: Enable Circulate when 1; 0: send fifo data only once
- 2: Enable Triggered Mode when 1; 0: run continueously (no TTC)
- 3: Enable pattern generator
- - name: MROD_TCVRCTRL
- type: W
- bitfield:
- - range: 23..16
- name: SLIDEMAX
- default: 0xFF
- desc: Maximum RXSLIDES before fire a TCVR reset
- - range: 15..8
- name: SLIDEWAIT
- default: 32
- desc: RXclk delay in TCVR for next RX_SLIDE operation
- - range: 7..0
- name: FRAMESIZE
- default: 20
- desc: Number of 32 data words in 1 frame
- - name: MROD_EP0_CSMENABLE
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 CSM Data Enable channel 23-0
- default: 0
- - name: MROD_EP0_EMPTYSUPPR
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Set Empty Suppression channel 23-0
- default: 0
- - name: MROD_EP0_HPTDCMODE
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Set HPTDC Mode channel 23-0
- default: 0
- - name: MROD_EP0_CLRFIFOS
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Clear FIFOs channel 23-0
- default: 0
- - name: MROD_EP0_EMULOADENA
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Emulator Load Enable channel 23-0
- default: 0
- - name: MROD_EP0_TRXLOOPBACK
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Transceiver Loopback Enable channel 23-0
- default: 0
- - name: MROD_EP0_TXCVRRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Transceiver Reset all channel 23-0
- default: 0
- - name: MROD_EP0_RXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Reset channel 23-0
- default: 0
- - name: MROD_EP0_TXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Transmitter Reset channel 23-0
- default: 0
- - name: MROD_EP1_CSMENABLE
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 CSM Data Enable channel 23-0
- default: 0
- - name: MROD_EP1_EMPTYSUPPR
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Set Empty Suppression channel 23-0
- default: 0
- - name: MROD_EP1_HPTDCMODE
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Set HPTDC Mode channel 23-0
- default: 0
- - name: MROD_EP1_CLRFIFOS
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Clear FIFOs channel 23-0
- default: 0
- - name: MROD_EP1_EMULOADENA
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Emulator Load Enable channel 23-0
- default: 0
- - name: MROD_EP1_TRXLOOPBACK
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Transceiver Loopback Enable channel 23-0
- default: 0
- - name: MROD_EP1_TXCVRRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Transceiver Reset all channel 23-0
- default: 0
- - name: MROD_EP1_RXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Reset channel 23-0
- default: 0
- - name: MROD_EP1_TXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Transmitter Reset channel 23-0
- default: 0
-
-MRODmonitors:
- group: MROD_MONITOR
- desc: Specific registers for MROD
- endpoints: 0
- generate: MROD_GENERATE_REGS
- entries:
- - name: MROD_EP0_CSMH_EMPTY
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 CSM Handler FIFO Empty 23-0
- - name: MROD_EP0_CSMH_FULL
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 CSM Handler FIFO Full 23-0
- - name: MROD_EP0_RXALIGNBSY
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Aligned monitor 23-0
- - name: MROD_EP0_RXRECDATA
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Data monitor 23-0
- - name: MROD_EP0_RXRECIDLES
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Idle monitor 23-0
- - name: MROD_EP0_TXLOCKED
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Transmitter Locked monitor 23-0
- - name: MROD_EP1_CSMH_EMPTY
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 CSM Handler FIFO Empty 23-0
- - name: MROD_EP1_CSMH_FULL
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 CSM Handler FIFO Full 23-0
- - name: MROD_EP1_RXALIGNBSY
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Aligned monitor 23-0
- - name: MROD_EP1_RXRECDATA
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Data monitor 23-0
- - name: MROD_EP1_RXRECIDLES
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Idle monitor 23-0
- - name: MROD_EP1_TXLOCKED
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Transmitter Locked monitor 23-0
-
-#
diff --git a/sources/templates/yaml/registers-4.11.yaml b/sources/templates/yaml/registers-4.11.yaml
deleted file mode 100644
index 72db6fe630d9a112cd4450e8621fb13a2bffda63..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-4.11.yaml
+++ /dev/null
@@ -1,3567 +0,0 @@
-Registers:
- version: '4.11'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: TTCBUSYControlsAndMonitors
- record_name: register_map_ttc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: XOFF_BUSYControlsAndMonitors
- record_name: register_map_xoff_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: Generators
- record_name: register_map_generators
- bitfield:
- - range: 0..0
- type: R
- - name: Wishbone
- record_name: wishbone_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: MRODmonitors
- record_name: regmap_mrod_monitor
- bitfield:
- - range: 0..0
- type: R
-
-#Bar0 contains the registers dedicated to Wupper. Please only edit registers in Bar2
-#Registers in this group will not be generated with WupperCodeGen
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- #- name: DMA_FIFO_FLUSH
- # type: T
- # bitfield:
- # - range: any
- # desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- offset: 0x420
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
- - name: BUSY_THRESHOLD_ASSERT
- type: W
- desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
- default: 0x6400000
- bitfield:
- - range: 63..0
-
- - name: BUSY_THRESHOLD_NEGATE
- type: W
- desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
- default: 0x6E00000
- bitfield:
- - range: 63..0
-
- - name: BUSY_STATUS
- type: R
- bitfield:
- - range: 0
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
- - name: PC_PTR_GAP
- type: W
- desc: This is the minimum value that the pc_pointer in a descriptor has to decrease in order to flip the evencycle_pc bit
- default: 0x1000000
- bitfield:
- - range: 63..0
-
- - name: TOHOSTFIFO_EMPTY
- type: R
- desc: Empty flags of the ToHost FIFOs in Wupper
- bitfield:
- - range: 3..0
-
- - name: TOHOSTFIFO_PEMPTY
- type: R
- desc: Programmable empty flags of the ToHost FIFOs in Wupper
- bitfield:
- - range: 3..0
-
- - name: FROMHOSTFIFO_FULL
- type: R
- desc: Full flag of the FromHost FIFO in Wupper
- bitfield:
- - range: 0
-
- - name: FROMHOSTFIFO_PFULL
- type: R
- desc: Programmable full flag of the FromHost FIFO in Wupper
- bitfield:
- - range: 0
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: SW_POINTER
- desc: Pointer controlled by the software, indicating read or write status for circular DMA
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- type: R
- name: FROMHOST
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: FW_POINTER
- desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
-
-
-#Bar1 contains the registers dedicated to the Wupper interrupg controller.
-#Please only edit registers in Bar2.
-#Registers in this group will not be generated with WupperCodeGen
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 16
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-#Bar 2 contains application specific registers, used in the example application.
-#Registers in this group (and it's referenced subroups) will be generated with
-#WupperCodeGen for wupper Firmware, Software and Documentation
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x5000
- - ref: GBTWrapperControls
- offset: 0x6000
- - ref: GBTWrapperMonitors
- offset: 0x7000
- - ref: TTCBUSYControlsAndMonitors
- offset: 0x8000
- - ref: XOFF_BUSYControlsAndMonitors
- offset: 0x8800
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x9000
- - ref: Generators
- offset: 0xA000
- - ref: Wishbone
- offset: 0xC000
- - ref: ITK_STRIPS_CTRL # ITk strips global controls
- offset: 0xD000
- - ref: MRODregisters
- offset: 0xF000
- - ref: MRODmonitors
- offset: 0xF800
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned({{ tree.version|version }},16))
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- #- name: BOARD_ID_SVN
- # bitfield:
- # - range: 15..0
- # value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- # desc: OBSOLETE Board ID SVN Revision
-
- - name: GIT_COMMIT_TIME
- offset: 0x30
- bitfield:
- - range: 39..0
- value: COMMIT_DATETIME
- desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_TAG
- bitfield:
- - range: 63..0
- value: GIT_TAG(63 downto 0)
- desc: String containing the current GIT TAG
-
- - name: GIT_COMMIT_NUMBER
- bitfield:
- - range: 31..0
- value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
- desc: Number of GIT commits after current GIT_TAG
-
- - name: GIT_HASH
- bitfield:
- - range: 31..0
- value: GIT_HASH(159 downto 128)
- desc: Short GIT hash (32 bit)
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT or FULL mode Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): FLX709, VC709
- - 710 (0x2c6): FLX710, HTG710
- - 711 (0x2c7): FLX711, BNL711
- - 712 (0x2c8): FLX712, BNL712
- - 128 (0x080): FLX128, VCU128
-
- #- name: GBT_MAPPING
- # bitfield:
- # - range: 7..0
- # desc: |
- # OBSOLETE CXP-to-GBT mapping:
- # 0: NORMAL CXP1 1-12 CXP2 13-24
- # 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- offset: 0xc0
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST_GENERATE_TTC_EMU
- type: R
- bitfield:
- - range: 1
- type: R
- desc: 1 when TTC emulator is generated
-
- #- range: 0
- # type: R
- # name: TTC_TEST_MODE
- # desc: OBSOLETE 1 when TTC Test mode is anabled
-
- #- name: CR_INTERNAL_LOOPBACK_MODE
- # type: R
- # bitfield:
- # - range: 0
- # desc: OBSOLETE 1 when Central Router internal loopback mode is enabled
-
- - offset: 0x100
- ref: INCLUDE_EGROUPS
-
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- #- name: DEBUG_MODE
- # type: R
- # bitfield:
- # - range: 0
- # desc: |
- # OBSOLETE
- # 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- # 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- offset: 0x190
- bitfield:
- - range: 3..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
- 3: FEI4 mode
- 4: ITK Pixel
- 5: ITK Strip
- 6: FELIG
- 7: FULL mode emulator
- 8: FELIX_MROD mode
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
- - name: BLOCKSIZE
- type: R
- desc: Number of bytes in a block
- bitfield:
- - range: 15..0
-
- - name: PCIE_ENDPOINT
- type: R
- desc: Indicator of the PCIe endpoint on BNL71x cards with two endpoints. 0 or 1
- bitfield:
- - range: 0
- value: std_logic_vector(to_unsigned(PCIE_ENDPOINT, 1))
-
- - name: CHUNK_TRAILER_32B
- type: R
- desc: Indicator that the chunk trailer is in the new 32-bit format
- bitfield:
- - range: 0
-
- - name: NUMBER_OF_PCIE_ENDPOINTS
- type: R
- desc: Number of PCIe endpoints on the card. The BNL71x cards have 2 endpoints
- bitfield:
- - range: 1..0
-
-INCLUDE_EGROUPS:
- number: 7
- entries:
- - format_name: INCLUDE_EGROUP_{index}
- name: INCLUDE_EGROUP
- type_name: INCLUDE_EGROUP
- type: R
- bitfield:
- - range: 8
- name: FROMHOST_02
- desc: FromHost EPROC02 is included in this EGROUP
- - range: 7
- name: FROMHOST_04
- desc: FromHost EPROC04 is included in this EGROUP
- - range: 6
- name: FROMHOST_08
- desc: FromHost EPROC8 is included in this EGROUP
- - range: 5
- name: FROMHOST_HDLC
- desc: FromHost HDLC is included in this EGROUP
- - range: 4
- name: TOHOST_02
- desc: ToHost EPROC02 is included in this EGROUP
- - range: 3
- name: TOHOST_04
- desc: ToHost EPROC04 is included in this EGROUP
- - range: 2
- name: TOHOST_08
- desc: ToHost EPROC08 is included in this EGROUP
- - range: 1
- name: TOHOST_16
- desc: ToHost EPROC16 is included in this EGROUP
- - range: 0
- name: TOHOST_HDLC
- desc: ToHost HDLC is included in this EGROUP
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: IC_FROMHOST_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- #- ref: IC_FIFOS
- # desc: See Central Router Doc
- # offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
- offset: 0x1700
-
- #- name: CR_FALLBACK_OPTIONS
- # desc: OBSOLETE Julias personal register with Hello Kitty options
- # type: W
- # bitfield:
- # - range: 63..0
-
- - name: CR_TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- offset: 0x1a10
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - name: CR_REVERSE_10B
- desc: Reverse 10-bit word of elink data
- type: W
- bitfield:
- - range: 1
- name: FROMHOST
- default: 1
- desc: |
- 1: Serialize 10-bit word in FromHost EPROCS MSB first
- 0: Serialize 10-bit word in FromHost EPROCS LSB first
- - range: 0
- name: TOHOST
- default: 1
- desc: |
- 1: Receive 10-bit word in ToHost EPROCS, MSB first
- 0: Receive 10-bit word in ToHost EPROCS, LSB first
-
- - name: CR_LTDB_TTC_DELAY
- desc: Controls TTC BCR delay in LTDB mode firmware
- type: W
- bitfield:
- - range: 7
- name: EGROUP4_EPATH6
- default: 1
- desc: |
- Egroup 4, Epath 6
- 1: Half a clock delay
- 0: no delay
- - range: 6
- name: EGROUP4_EPATH5
- default: 1
- desc: |
- Egroup 4, Epath 5
- 1: Half a clock delay
- 0: no delay
- - range: 5
- name: EGROUP4_EPATH4
- default: 1
- desc: |
- Egroup 4, Epath 4
- 1: Half a clock delay
- 0: no delay
- - range: 4
- name: EGROUP4_EPATH3
- default: 1
- desc: |
- Egroup 4, Epath 3
- 1: Half a clock delay
- 0: no delay
- - range: 3
- name: EGROUP4_EPATH0
- default: 1
- desc: |
- Egroup 4, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 2
- name: EGROUP3
- default: 1
- desc: |
- Egroup 3, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 1
- name: EGROUP2
- default: 1
- desc: |
- Egroup 2, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 0
- name: EGROUP1
- default: 1
- desc: |
- Egroup 1, Epath 0
- 1: Half a clock delay
- 0: no delay
-# - ref: CR_XOFF_CTRL
-# offset: 0x2800
-# desc: Configure FromHost Xoff
-
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x3000
- #- name: CR_STATIC_CONFIGURATION
- # type: R
- # bitfield:
- # - range: 0
- #- ref: CR_DEFAULT_EPROC_ENA_G
- #- ref: CR_DEFAULT_EPROC_ENCODING_G
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- offset: 0x3410
- bitfield:
- - range: 31..0
-
- - name: ELINK_REALIGNMENT
- type: W
- bitfield:
- - range: any
- name: CLEAR_REALIGNMENT_STATUS
- type: T
- value: 1
- desc: Clears the ELINK Realignment event flags
- - range: 0
- name: ENABLE
- default: 1
- desc: Enable realignment mechanism in 8b10b E-Links after illegal character reception.
-
- - ref: ELINK_REALIGNMENT_STATUS_GEN
-
- - name: FULLMODE_32B_SOP
- type: W
- desc: When set to 1, use 32-bit 0x0000003C as start of chunk, otherwise only 8-bit 0x3C (FULL mode only)
- bitfield:
- - range: 0
- default: 0
-
- - name: FE_EMU_LOGIC
- type: W
- bitfield:
- - range: 33
- name: L1A_TRIGGERED
- desc: 1 Send a chunk on every L1A, 0 use the IDLES to determine the rate
- - range: 32
- name: ENA
- desc: Enable logic based FrontEnd emulator, instead of RAM based.
- - range: 31..16
- name: IDLES
- desc: Number of IDLE bytes between chunks.
- - range: 15..0
- name: CHUNK_LENGTH
- desc: Chunk length in bytes
-
-
-
-CR_GBT_CTRL:
- number: 24
- bitfield:
- - range: 50..0
- type: W
- generate: GBT_NUM > {index:1}
- entries:
- - ref: EGROUP_TOHOST
- - ref: EGROUP_FROMHOST
-
-EGROUP_TOHOST:
- number: 7
- format_name: GBT{index:02}
- name: GBT
- entries:
- - name: TOHOST
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_TOHOST_EGROUP_CTRL
- bitfield:
- - range: 58..51
- name: INSTANT_TIMEOUT_ENA
- default: 0x0
- desc: instantly initiate a timeout for the given epath
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..31
- name: MAX_CHUNK_LEN
- default: MAX_CHUNK_LEN_array
- desc: set the maximum length of a chunk, 0 disables truncation
- - range: 30..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- default:
- - PATH_ENCODING_array(0)
- - PATH_ENCODING_array(1)
- - PATH_ENCODING_array(2)
- - PATH_ENCODING_array(3)
- - PATH_ENCODING_array(4)
- - PATH_ENCODING_array(5)
- - PATH_ENCODING_array(6)
-
- - range: 14..0
- name: EPROC_ENA
- desc: Enable bits per EPROC
- default:
- - EPROC_ENA_bits_array(0)
- - EPROC_ENA_bits_array(1)
- - EPROC_ENA_bits_array(2)
- - EPROC_ENA_bits_array(3)
- - EPROC_ENA_bits_array(4)
- - EPROC_ENA_bits_array(5)
- - EPROC_ENA_bits_array(6)
-
-EGROUP_FROMHOST:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FROMHOST
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_FROMHOST_EGROUP_CTRL
- bitfield:
- - range: 54..47
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 46..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- greater than 3: TTC mode, see CentralRouter doc
- default:
- - FROMHOST_PATH_ENCODING_array(0)
- - FROMHOST_PATH_ENCODING_array(1)
- - FROMHOST_PATH_ENCODING_array(2)
- - FROMHOST_PATH_ENCODING_array(3)
- - FROMHOST_PATH_ENCODING_array(4)
- - FROMHOST_PATH_ENCODING_array(5)
- - FROMHOST_PATH_ENCODING_array(6)
- - range: 14..0
- desc: Enable bits per EPROC
- name: EPROC_ENA
-
-# ----------------------- ITk strips link configuration start -----------------------
-
-ITK_STRIPS_CTRL:
- entries:
- - name: GLOBAL_STRIPS_CONFIG
- desc: Synchronous trigger for all LCB links on device
- type: W
- bitfield:
- - range: 15..11
- type: W
- name: TEST_MODULE_MASK
- desc: (for tests only) contains R3 mask for the simulated trigger data
- default: 0x0
- - range: 10..4
- type: W
- name: TEST_R3L1_TAG
- desc: (for tests only) contains R3 or L1 tag for the simulated trigger data
- default: 0x0
- - range: 1
- type: W
- name: TTC_GENERATE_GATING_ENABLE
- desc: Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR.
- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- (See also BC_START, and BC_STOP fields)
- default: 0x0
- - name: GLOBAL_TRICKLE_TRIGGER
- type: T
- bitfield:
- - range: any
- value: 1
- desc: writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
-
- - ref: ITK_STRIPS_GBT
-
- - name: STRIPS_R3_TRIGGER
- type: T
- bitfield:
- - range: any
- value: 1
- desc: (for tests only) simulate R3 trigger (issues 4-5 sequential triggers)
- - name: STRIPS_L1_TRIGGER
- type: T
- bitfield:
- - range: any
- desc: (for tests only) simulate L1 trigger (issues 4-5 sequential triggers)
- value: 1
- - name: STRIPS_R3L1_TRIGGER
- type: T
- bitfield:
- - range: any
- desc: (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)
- value: 1
-
-ITK_STRIPS_GBT:
- number: 4
- format_name: STRIPS
- generate: (GBT_NUM > {index:1} and FIRMWARE_MODE = 5)
- entries:
- - ref: ITK_STRIPS_LCB_LINKS
- - ref: ITK_STRIPS_R3L1_LINKS
-
-ITK_STRIPS_LCB_LINKS:
- number: 4
- format_name: ITK_STRIPS_LCB_LINKS_{index:02}
- type_name: ITK_LCB_LINK
- entries:
- - name: LCB
- format_name: CR_{parent}_{name}_{index}
- type_name: LCB_CTRL
- desc: Determines LCB link configuration
- type: W
- bitfield:
- - range: 49..38
- type: W
- name: L0A_BCR_DELAY
- default: 0x0
- desc: TTC BCR signal will be delayed by this many BCs
- - range: 37..34
- type: W
- name: L0A_FRAME_DELAY
- default: 0x0
- desc: |
- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- - range: 33..32
- type: W
- name: FRAME_PHASE
- default: 0x0
- desc: phase of LCB frame with respect to TTC BCR signal
- - range: 31..20
- type: W
- name: TRICKLE_BC_START
- default: 0x0
- desc: Determines the start of the allowed BC interval for low-priority LCB frames
- - range: 19..8
- type: W
- name: TRICKLE_BC_STOP
- default: 0x0
- desc: Determines the end of the allowed BC interval for low-priority LCB frames
- - range: 5..4
- type: W
- name: LCB_DESTINATION_MUX
- default: 0x0
- desc: |
- Determines where the elink data is sent to:
- 00: command decoder (use same command encoding format as trickle configuration)
- 01: trickle memory (see phase2 documentation for command encoding format)
- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- 11: (invalid, don't use)
- - range: 3
- type: W
- name: TRICKLE_TRIG_RUN
- default: 0x0
- desc: |
- if enabled, trickle configuration is sent out continuously to the front-end
- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- - range: 2
- type: W
- name: TTC_L0A_ENABLE
- default: 0x0
- desc: enable generating L0A frames in response to TTC system signals
- - range: 0
- type: W
- name: TTC_GENERATE_GATING_ENABLE
- default: 0x0
- desc: |
- enables generating trickle gating signal in response to TTC BCR.
- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- (See also BC_START, and BC_STOP fields)
- - name: TRICKLE_TRIGGER
- format_name: CR_{parent}_{name}_{index}
- type_name: TRICKLE_TRIGGER
- type: T
- bitfield:
- - range: any
- desc: writing to this register issues a single trickle trigger
- value: 1
- - name: TRICKLE_MEMORY_CONFIG
- format_name: CR_{parent}_{name}_{index}
- type_name: LCB_TRICKLE_CONFIG
- desc: Trickle trigger configuration
- type: W
- bitfield:
- - range: any
- type: T
- name: MOVE_WRITE_PTR
- value: 1
- desc: |
- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- - range: 47..32
- type: W
- name: WRITE_PTR
- default: 0x0
- desc: Trickle configuration memory write pointer
- - range: 31..16
- type: W
- name: VALID_DATA_START
- default: 0x0
- desc: Start address of trickle configuration in trickle memory
- - range: 15..0
- type: W
- name: VALID_DATA_END
- default: 0x0
- desc: Stop address of trickle configuration in trickle memory (last valid byte)
- - name: MODULE_MASK_F_C
- format_name: CR_{parent}_{name}_{index}
- type_name: HCC_ABC_MASK_E_C
- type: W
- desc: |
- Disables register commands addressed to masked HCC*/ABC* chips. Register commands for which
- corresponding mask bit is set to '1' will be ignored by the command encoder.
- This is useful to quickly disable trickle configuration for selected
- modules without overwriting the entire trickle configuratrion memory.
- bitfield:
- - range: 63..48
- type: W
- name: HCC_MASK
- default: 0x0
- desc: |
- HCC* module mask
- - range: 47..32
- type: W
- name: ABC_MASK_HCC_E
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0xE
- mask(i) <=> (abc_id = i)
- - range: 31..16
- type: W
- name: ABC_MASK_HCC_D
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0xD
- mask(i) <=> (abc_id = i)
- - range: 15..0
- type: W
- name: ABC_MASK_HCC_C
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0xC
- mask(i) <=> (abc_id = i)
- - name: ABC_MODULE_MASK_B_8
- format_name: CR_{parent}_{name}_{index}
- type_name: LCB_ABC_MASK_B_8
- type: W
- desc: |
- Disables register commands addressed to masked ABC* chips. Register commands for which
- corresponding mask bit is set to '1' will be ignored by the command encoder.
- This is useful to quickly disable trickle configuration for selected
- modules without overwriting the entire trickle configuratrion memory.
- bitfield:
- - range: 63..48
- type: W
- name: ABC_MASK_HCC_B
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0xB
- mask(i) <=> (abc_id = i)
- - range: 47..32
- type: W
- name: ABC_MASK_HCC_A
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0xA
- mask(i) <=> (abc_id = i)
- - range: 31..16
- type: W
- name: ABC_MASK_HCC_9
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x9
- mask(i) <=> (abc_id = i)
- - range: 15..0
- type: W
- name: ABC_MASK_HCC_8
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x8
- mask(i) <=> (abc_id = i)
- - name: ABC_MODULE_MASK_7_4
- format_name: CR_{parent}_{name}_{index}
- type_name: LCB_ABC_MASK_7_4
- type: W
- desc: |
- Disables register commands addressed to masked ABC* chips. Register commands for which
- corresponding mask bit is set to '1' will be ignored by the command encoder.
- This is useful to quickly disable trickle configuration for selected
- modules without overwriting the entire trickle configuratrion memory.
- bitfield:
- - range: 63..48
- type: W
- name: ABC_MASK_HCC_7
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x7
- mask(i) <=> (abc_id = i)
- - range: 47..32
- type: W
- name: ABC_MASK_HCC_6
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x6
- mask(i) <=> (abc_id = i)
- - range: 31..16
- type: W
- name: ABC_MASK_HCC_5
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x5
- mask(i) <=> (abc_id = i)
- - range: 15..0
- type: W
- name: ABC_MASK_HCC_4
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x4
- mask(i) <=> (abc_id = i)
- - name: ABC_MODULE_MASK_3_0
- format_name: CR_{parent}_{name}_{index}
- type_name: LCB_ABC_MASK_3_0
- type: W
- desc: |
- Disables register commands addressed to masked ABC* chips. Register commands for which
- corresponding mask bit is set to '1' will be ignored by the command encoder.
- This is useful to quickly disable trickle configuration for selected
- modules without overwriting the entire trickle configuratrion memory.
- bitfield:
- - range: 63..48
- type: W
- name: ABC_MASK_HCC_3
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x3
- mask(i) <=> (abc_id = i)
- - range: 47..32
- type: W
- name: ABC_MASK_HCC_2
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x2
- mask(i) <=> (abc_id = i)
- - range: 31..16
- type: W
- name: ABC_MASK_HCC_1
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x1
- mask(i) <=> (abc_id = i)
- - range: 15..0
- type: W
- name: ABC_MASK_HCC_0
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x0
- mask(i) <=> (abc_id = i)
-
-
-ITK_STRIPS_R3L1_LINKS:
- number: 4
- format_name: ITK_R3L1_LINK_{index:02}
- type_name: ITK_R3L1_LINK
- entries:
- - name: R3L1
- format_name: CR_{parent}_{name}_{index:1}
- type_name: R3L1_CTRL
- desc: Determines R3L1 link configuration
- type: W
- bitfield:
- - range: 3..2
- type: W
- name: FRAME_PHASE
- default: 0x0
- desc: phase of R3L1 frame with respect to TTC BCR signal
- - range: 1
- type: W
- name: L1_ENABLE
- default: 0x0
- desc: enables sending TTC L1 signals to the front-end
- - range: 0
- type: W
- name: R3_ENABLE
- default: 0x0
- desc: enables sending RoI R3 signals to the front-end
-
-
-# ----------------------- ITk strips link configuration end -----------------------
-
-#CR_XOFF_CTRL:
-# number: 24
-# type: W
-# bitfield:
-# - range: 39..0
-# entries:
-# - name: FROMHOST_XOFF_ENABLE
-# format_name: FROMHOST_XOFF_ENABLE_{index:02}
-# desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
-# range: 39..0
-# default: 0
-# - name: FROMHOST_SOFT_XOFF
-# format_name: FROMHOST_SOFT_XOFF_{index:02}
-# desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
-# range: 39..0
-# default: 0
-
-
-#IC_FIFOS:
-# number: 24
-# format_name: IC_FROMHOST_TOHOST_FIFOS
-# entries:
-# - name: FROMHOST
-# format_name: IC_FROMHOST_FIFO_{index:02}
-# type_name: IC_FROMHOST_FIFO
-# type: W
-# generate: GBT_NUM > {index:1}
-# bitfield:
-# - range: any
-# type: T
-# value: not register_map_monitor_s.register_map_cr_monitor.IC_FROMHOST_FIFO({index}).FULL
-# name: WE
-# format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
-# desc: Any write to this register will trigger a write to the FIFO
-# - range: 8
-# type: R
-# name: FULL
-# format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
-# desc: Full flag of the fifo, do not write if 1
-# - range: 7..0
-# type: W
-# name: DATAIN
-# format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
-# desc: Data input of fifo
-# - name: TOHOST
-# format_name: IC_TOHOST_FIFO_{index:02}
-# type_name: IC_TOHOST_FIFO
-# type: W
-# generate: GBT_NUM > {index:1}
-# bitfield:
-# - range: any
-# type: T
-# value: not register_map_monitor_s.register_map_cr_monitor.IC_TOHOST_FIFO({index}).EMPTY
-# name: RE
-# format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
-# desc: Any write to this register will trigger a read enable from the fifo
-# - range: 8
-# type: R
-# name: EMPTY
-# format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
-# desc: Empty flag of the fifo, do not read if 1
-# - range: 7..0
-# type: R
-# name: DATAOUT
-# format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
-# desc: Data output of fifo
-
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 7
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 6
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 5
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 4
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 9
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 8
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 7
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 6
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
-
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- entries:
- - name: TOHOST
- type_name: CR_TOHOST_GBT_MON
- format_name: CR_{name}_GBT{index:02}_MON
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 58
- name: CROUTFIFO_PROG_FULL
- - range: 57
- name: WMFIFO_FULL
- - range: 56
- name: MINI_EGROUP_ALMOST_FULL
- - range: 55..48
- name: EPATH6_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP6
- - range: 47..40
- name: EPATH5_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP5
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
- - name: FROMHOST
- type_name: CR_FROMHOST_GBT_MON
- format_name: CR_{name}_GBT{index:02}_MON
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 40
- name: MINI_EGROUP_ALMOST_FULL
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
-
-ELINK_REALIGNMENT_STATUS_GEN:
- endpoints: 0, 1
- number: 12
- entries:
- - name: ELINK_REALIGNMENT_STATUS
- type_name: ELINK_REALIGNMENT_STATUS
- format_name: ELINK_REALIGNMENT_STATUS_{index:02}
- generate: GBT_NUM > {index:1}
- desc: |
- A realignment event due to an illegal 8b10b symbol has occurred.
- 1 bit per Epath.
- Clear status by writing to ELINK_REALIGNMENT.CLEAR_REALIGNMENT_STATUS
- bitfield:
- - range: 41..0
-
-
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0, 1
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 63..48
- name: RDDATA
- type: R
- desc: read data bus
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 0
- desc: write enable for the full mode emulator ram block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 35..0
- desc: read emu ram data
-
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 23..0
- desc: FULL mode CR enable array, every bit is one path
-
- - ref: PATH_HAS_STREAM_ID
-
-PATH_HAS_STREAM_ID:
- number: 24
- generate: GBT_NUM > {index:1}
- entries:
- - name: TOHOST
- format_name: LINK_{index:02}_HAS_STREAM_ID
- type_name: HAS_STREAM_ID
- type: W
- bitfield:
- - range: 55..48
- name: EGROUP6
- default: 0x0
- desc: EPATH (Wide mode) is associated with a STREAM ID
- - range: 47..40
- name: EGROUP5
- default: 0x0
- desc: EPATH (Wide mode) is associated with a STREAM ID
- - range: 39..32
- name: EGROUP4
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 31..24
- name: EGROUP3
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 23..16
- name: EGROUP2
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 15..8
- name: EGROUP1
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 7..0
- name: EGROUP0
- default: 0x0
- desc: EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_CHANNEL_DISABLE
- offset: 0x0400
- bitfield:
- - range: 47..0
- desc: Disable selected GBT or FULL mode channel
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE_SELECT
- offset: 0x0480
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_RXSLIDE_MANUAL
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_TXUSRRDY
- desc: TxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_RXUSRRDY
- desc: RxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_SOFT_RESET
- desc: SOFT_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTTX_RESET
- desc: GTTX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTRX_RESET
- desc: GTRX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 59..48
- name: QPLL_RESET
- desc: QPLL_RESET [11:0]
- - range: 47..0
- name: CPLL_RESET
- desc: CPLL_RESET [47:0]
-
- - name: GBT_SOFT_TX_RESET
- offset: 0x0500
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_SOFT_RX_RESET
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_ODD_EVEN
- desc: OddEven [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_TOPBOT
- desc: TopBot [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_TC_DLY_VALUE3
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [143:96]
-
- - name: GBT_TX_TC_DLY_VALUE4
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [191:144]
-
- - name: GBT_DATA_TXFORMAT1
- desc: DATA_TXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_TXFORMAT2
- desc: DATA_TXFORMAT [95:48]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT1
- desc: DATA_RXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT2
- desc: DATA_RXFORMAT [95:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_RESET
- desc: TX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_RESET
- desc: RX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_METHOD
- desc: TX time domain crossing method [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUTMUX_SEL
- desc: Descrambler output MUX selection [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TC_EDGE
- desc: Sampling edge selection for TX domain crossing [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for transmitter of GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_RXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for the receiver of the GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
- - name: GBT_TOHOST_FANOUT
- offset: 0x0700
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0x0
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_TOFRONTEND_FANOUT
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0x0
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
- - name: FULLMODE_AUTO_RX_RESET
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: Enable the Automatic RX Reset mechanism
- - range: 31..0
- name: TIMEOUT
- default: 0x00100000
- desc: Number of 40 MHz clock cycles until an unaligned link results in a reset pulse
-
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- desc: TX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXRESET_DONE
- desc: RX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXFSMRESET_DONE
- desc: TX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXFSMRESET_DONE
- desc: RX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_LOCK
- bitfield:
- - range: 59..48
- name: QPLL_LOCK
- desc: QPLL LOCK [11:0]
- - range: 47..0
- name: CPLL_LOCK
- desc: CPLL LOCK [47:0]
-
- - name: GBT_RXCDR_LOCK
- desc: RX CDR LOCK [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CLK_SAMPLED
- desc: clk sampled [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_HEADER
- desc: RX IS HEADER [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_DATA
- desc: RX IS DATA [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_HEADER_FOUND
- desc: RX HEADER FOUND [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUT_MUX_STATUS
- desc: GBT output mux status [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ERROR
- desc: Error flags [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GBT_TOPBOT_C
- desc: TopBot_c [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-TTCBUSYControlsAndMonitors:
- group: TTCBUSY
- desc: TTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: TTC_BUSY_ACCEPTED_G
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 2
- name: FULL
- type: R
- desc: TTC Emulator memory full indication
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
-
- - ref: TTC_DELAY
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the BUSY Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
- - name: TTC_EMU_CONTROL
- type: W
- bitfield:
- - range: 33
- name: BUSY_IN_ENABLE
- desc: Enable internal BUSY input to stop L1A on BUSY
- default: 1
- - range: 32..27
- name: BROADCAST
- desc: Broadcast data
- - range: 26
- name: ECR
- desc: Event counter reset
- - range: 25
- name: BCR
- desc: Bunch counter reset
- - range: 24
- name: L1A
- desc: Level 1 Accept
-
- - name: TTC_EMU_L1A_PERIOD
- type: W
- desc: L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
- bitfield:
- - range: 31..0
-
- - name: TTC_EMU_ECR_PERIOD
- type: W
- desc: ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
- bitfield:
- - range: 31..0
-
- - name: TTC_EMU_BCR_PERIOD
- type: W
- desc: BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
- bitfield:
- - range: 31..0
- default: 3564
-
- - name: TTC_EMU_LONG_CHANNEL_DATA
- type: W
- desc: Long channel data for the TTC emulator
- bitfield:
- - range: 31..0
-
- - name: TTC_EMU_RESET
- desc: Any write to this register resets the TTC Emulator to the default state.
- type: W
- bitfield:
- - range: any
- value: 1
- type: T
-
- - name: TTC_L1ID_MONITOR
- desc: Monitor L1ID and XL1ID.
- type: R
- bitfield:
- - range: 31..0
-
- - name: TTC_ECR_MONITOR
- desc: Counts the number of ECRs received from the TTC system, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_TTYPE_MONITOR
- desc: Counts the number of TType received from the TTC system, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_BCR_PERIODICITY_MONITOR
- desc: Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_BCR_COUNTER
- desc: Counts the number of times BCR is issued, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_EMU_TP_DELAY
- desc: Number of BC that the testpulse should be sent before the L1A, 0 means no test pulse is sent
- type: W
- bitfield:
- - range: 31..0
- default: 64
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range: 30..27
- name: B_CHAN_DELAY
- type: W
- desc: Number of BC to delay the L1A distribution to the frontends
- - range: 26..15
- name: BCID_ONBCR
- type: W
- desc: BCID is set to this value when BCR arrives
- - range: 14
- name: BUSY_OUTPUT_STATUS
- type: R
- desc: Actual status of the BUSY LEMO output signal
- - range: 13
- name: ECR_BCR_SWAP
- default: 0
- desc: ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
- - range: 12
- name: BUSY_OUTPUT_INHIBIT
- default: 0
- desc: forces the Busy LEMO output to BUSY-OFF
- - range: 11
- name: TOHOST_RST
- desc: reset toHost in ttc decoder
- default: 0
- - range: 10
- name: TT_BCH_EN
- desc: trigger type enable / disable for TTC-ToHost
- default: 1
- - range: 9..2
- name: XL1ID_SW
- desc: set XL1ID value, the value to be set by XL1ID_RST signal
- default: 0x00
- - range: 1
- name: XL1ID_RST
- desc: giving a trigger signal to reset XL1ID value
- default: 0
- - range: 0
- name: MASTER_BUSY
- desc: L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range: 15..5
- name: TH_FF_COUNT
- desc: ToHostData Fifo counts
- - range: 4
- name: TH_FF_FULL
- desc: ToHostData Fifo status 1:full 0:not full
- - range: 3
- name: TH_FF_EMPTY
- desc: ToHostData Fifo status 1:empty 0:not empty
- - range: 2..0
- name: TTC_BIT_ERR
- desc: double bit, single bit and comm error in TTC data
-
-TTC_BUSY_ACCEPTED_G:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- entries:
- - name: TTC_BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
- type_name: TTC_BUSY_ACCEPTED
- bitfield:
- - range: 56..0
-
-
-
-TTC_DELAY:
- number: 48
- type: W
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Controls the TTC Fanout delay values
- bitfield:
- - range: 3..0
- default: 0
-
-XOFF_BUSYControlsAndMonitors:
- group: XOFF
- desc: XOFF Controls and Monitors, see table 2 of Busy specs manual
- endpoints: 0, 1
- entries:
- - name: XOFF_FM_CH_FIFO_THRESH_LOW
- type: W
- bitfield:
- - range: 3..0
- default: 0xB
- desc: |
- Controls the low threshold of the channel fifo in FULL mode on which
- an Xon will be asserted, bitfields control 4 MSB
- - name: XOFF_FM_CH_FIFO_THRESH_HIGH
- type: W
- bitfield:
- - range: 3..0
- default: 0xB
- desc: |
- Controls the high threshold of the channel fifo in FULL mode on which
- an Xoff will be asserted, bitfields control 4 MSB
- - name: XOFF_FM_LOW_THRESH_CROSSED
- desc: FIFO filled beyond the low threshold, 1 bit per channel
- type: R
- bitfield:
- - range: 23..0
- - name: XOFF_FM_HIGH_THRESH
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- desc: Writing this register will clear all CROSS_LATCHED bits
- type: T
- value: 1
- - range: 47..24
- type: R
- name: CROSS_LATCHED
- desc: FIFO filled beyond the high threshold, 1 latch bit per channel
- - range: 23..0
- type: R
- name: CROSSED
- desc: FIFO filled beyond the high threshold, 1 bit per channel
-
- - name: XOFF_FM_SOFT_XOFF
- type: W
- desc: Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
- bitfield:
- - range: 23..0
-
- - name: XOFF_ENABLE
- type: W
- desc: Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
- bitfield:
- - range: 23..0
-
- - name: DMA_BUSY_STATUS
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR_LATCH
- desc: Any write to this register clears TOHOST_BUSY_LATCHED
- - range: 4
- type: W
- name: ENABLE
- desc: Enable the DMA buffer on the server as a source of busy
- default: 0
- - range: 3
- type: R
- name: TOHOST_BUSY_LATCHED
- desc: A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => tohost_busy_latched_40_s)
- - range: 0
- type: R
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => tohost_busy_40_s)
-
- - name: FM_BUSY_CHANNEL_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- type: T
- value: 1
- desc: Any write to this register will clear the BUSY_LATCHED bits
- - range: 47..24
- type: R
- name: BUSY_LATCHED
- desc: one Indicates that the given FULL mode channel has received BUSY-ON
- - range: 23..0
- type: R
- name: BUSY
- desc: one Indicates that the given FULL mode channel is currently in BUSY state
-
- - name: BUSY_MAIN_OUTPUT_FIFO_THRESH
- type: W
- bitfield:
- - range: 24
- name: BUSY_ENABLE
- desc: Enable busy generation if thresholds are crossed
- default: 0
- - range: 23..12
- name: LOW
- desc: Low, Negate threshold of busy generation from main output fifo
- default: 0x3FF
- - range: 11..0
- name: HIGH
- desc: High, Assert threshold of busy generation from main output fifo
- default: 0x4FF
-
- - name: BUSY_MAIN_OUTPUT_FIFO_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCHED
- value: 1
- desc: Any write to this register will clear the
- type: T
- - range: 2
- type: R
- name: HIGH_THRESH_CROSSED_LATCHED
- desc: Main output fifo has been full beyond HIGH THRESHOLD, write to clear
- - range: 1
- type: R
- name: HIGH_THRESH_CROSSED
- desc: Main output fifo is full beyond HIGH THRESHOLD
- - range: 0
- type: R
- name: LOW_THRESH_CROSSED
- desc: Main output fifo is full beyond LOW THRESHOLD
- - ref: ELINK_BUSY_ENABLE
- - ref: XOFF_STATISTICS
-
-
-ELINK_BUSY_ENABLE:
- number: 24
- endpoints: 0
- type: W
- entries:
- - name: ELINK_BUSY_ENABLE
- format_name: ELINK_BUSY_ENABLE{index:02}
- type_name: ELINK_BUSY_ENABLE
- desc: Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- bitfield:
- - range: 56..0
- default: 0
-
-XOFF_STATISTICS:
- number: 24
- endpoints: 0,1
- type: R
- entries:
- - name: XOFF_PEAK_DURATION
- format_name: XOFF_PEAK_DURATION{index:02}
- type_name: XOFF_PEAK_DURATION
- desc: Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- bitfield:
- - range: 63..0
- - name: XOFF_TOTAL_DURATION
- format_name: XOFF_TOTAL_DURATION{index:02}
- type_name: XOFF_TOTAL_DURATION
- desc: Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- bitfield:
- - range: 63..0
- - name: XOFF_COUNT
- format_name: XOFF_COUNT{index:02}
- type_name: XOFF_COUNT
- desc: Total number of XOFF events per channel that occurred since a reset.
- bitfield:
- - range: 63..0
-
-
-
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
-
- - name: HK_MON_FMC
- type: W
- bitfield:
- - range: 1
- name: SI5345_LOL
- desc: Si5345 Loss Of Lock pin
- - range: 0
- name: SI5345_INTR
- desc: Si5345 Interrupt flagging chip change of status
-
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_SEL
- default: 0x1
- desc: |
- 1: LCLK
- 0: TTC
- - range: 2..1
- type: R
- name: MAIN_INPUT
- desc: |
- Main MMCM Oscillator Input
- 2: LCLK fixed
- 1: TTC fixed
- 0: selectable
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL-711 locked
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
-
- - name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
-
-
- #- name: SPI_WR
- # type: W
- # offset: 0x0400
- # bitfield:
- # - range: any
- # type: T
- # value: OBSOLETE not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- # name: SPI_WREN
- # desc: Any write to this register triggers an SPI Write
- # - range: 32
- # type: R
- # name: SPI_FULL
- # desc: OBSOLETE SPI FIFO Full
- # - range: 31..0
- # type: W
- # name: SPI_DIN
- # desc: OBSOLETE SPI WRITE Data
- #
- #- name: SPI_RD
- # type: T
- # bitfield:
- # - range: any
- # type: T
- # value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- # name: SPI_RDEN
- # desc: OBSOLETE Any write to this register pops the last SPI data from the FIFO
- # - range: 32
- # type: R
- # name: SPI_EMPTY
- # desc: OBSOLETE SPI FIFO Empty
- # - range: 31..0
- # type: R
- # name: SPI_DOUT
- # desc: OBSOLETE SPI READ Data
-
- - name: I2C_WR
- type: W
- offset: 0x420
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
-
- #- name: DEBUG_PORT_GBT
- # offset: 0x0500
- # type: W
- # bitfield:
- # - range: 6..0
- # desc: OBSOLETE Debug GBT data bit N (119..0) on SMA HTGx#3
-
- #- name: DEBUG_PORT_CLK
- # type: W
- # bitfield:
- # - range: 3..0
- # desc: OBSOLETE Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST
- offset: 0x0800
- type: W
- value: 1
- bitfield:
- - name: TRIGGER
- type: T
- range: any
- desc: Fire a test MSIx interrupt set in IRQ
- - name: IRQ
- type: W
- range: 3..0
- desc: Set this field to a value equal to the MSIX interrupt to be fired. The write triggers the interrupt immediately.
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
-
- - name: TACH_CNT
- type: R
- desc: Readout of the Fan tachometer speed of the BNL712 board
- bitfield:
- - range: 19..0
-
- - name: RXUSRCLK_FREQ
- type: W
- bitfield:
- - range: 38
- name: VALID
- type: R
- desc: Indicates that the frequency measurement is valid
- - range: 37..32
- name: CHANNEL
- type: W
- desc: Select the Transceiver channel to measure the clock from.
- - range: 31..0
- name: VAL
- type: R
- desc: Frequency in Hz of the selected channel
-
-
-Generators:
- group: GEN
- desc: Specific registers for Hardware based Generators
- endpoints: 0
- generate: EMU_GENERATE_REGS
- entries:
- - name: FELIG_L1ID_RESET
- type: W
- desc: Any write to this register clears the FELIG L1ID
- bitfield:
- - range: any
- type: T
- value: 1
- - ref: FELIG_DATA_GEN_CONFIG_ARR
- offset: 0x20
- - ref: FELIG_ELINK_CONFIG_ARR
- - ref: FELIG_ELINK_ENABLE_ARR
-
- - name: FELIG_GLOBAL_CONTROL
- type: W
- bitfield:
- - range: 63..36
- name: FAKE_L1A_RATE
- default: 0
- desc: Sets the internal fake L1 trigger rate. [25ns/LSB]
- - range: 35..14
- name: PICXO_OFFSET_PPM
- default: 0
- desc: When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
- - range: 12..12
- name: TRACK_DATA
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 11..11
- name: RXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 10..10
- name: TXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 9..9
- name: AUTO_RESET
- default: 0
- desc: FELIG GT core control. If set the GT core automatically resets on data error.
- - range: 8..8
- name: PICXO_RESET
- default: 0
- desc: FELIG GT core control. Manual PICXO reset.
- - range: 7..7
- name: GTTX_RESET
- default: 0
- desc: FELIG GT core control. Manual GT TX reset
- - range: 6..6
- name: CPLL_RESET
- default: 0
- desc: FELIG GT core control. Manual CPLL reset.
- - range: 5..0
- name: X3_X4_OUTPUT_SELECT
- default: 0
- desc: X3/X4 SMA output source select.
-
- - ref: FELIG_LANE_CONFIG_ARR
- - ref: FELIG_MON_TTC_0_ARR
- - ref: FELIG_MON_TTC_1_ARR
- - ref: FELIG_MON_COUNTERS_ARR
- - ref: FELIG_MON_FREQ_ARR
-
- - name: FELIG_MON_FREQ_GLOBAL
- type: W
- bitfield:
- - range: 63..32
- name: XTAL_100MHZ
- default: 0
- desc: FELIG local oscillator frequency[Hz].
- - range: 31..0
- name: CLK_41_667MHZ
- desc: FELIG PCIE MGTREFCLK frequency[Hz].
-
- - ref: FELIG_MON_L1A_ID_ARR
- - ref: FELIG_MON_PICXO_ARR
-
- - name: FELIG_RESET
- type: W
- bitfield:
- - range: 63..48
- name: LB_FIFO
- default: 0
- desc: One bit per lane. When set to 1, resets all loopback FIFOs.
- - range: 47..24
- name: FRAMEGEN
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG link checking logic.
- - range: 23..0
- name: LANE
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG lane logic.
-
- - name: FELIG_RX_SLIDE_RESET
- type: W
- bitfield:
- - range: 23..0
- default: 0
- desc: One bit per lane. When set to 1, resets the gbt rx slide counter.
-
- - ref: FELIG_ITK_STRIPS_DATA_GEN_CONFIG_ARR
- - ref: FELIG_MON_ITK_STRIPS_ARR
-
- - name: FMEMU_EVENT_INFO
- type: R
- offset: 0x1800
- bitfield:
- - range: 63..32
- name: L1ID
- default: 0
- desc: 32b field to show L1ID
- - range: 31..0
- name: BCID
- default: 0
- desc: 32b field to show BCID
-
- - name: FMEMU_COUNTERS
- type: W
- bitfield:
- - range: 63..48
- name: WORD_CNT
- default: 32
- desc: Number of 32b words in one chunk
- - range: 47..32
- name: IDLE_CNT
- default: 3
- desc: Minimum number of idles between chunks
- - range: 31..16
- name: L1A_CNT
- default: 256
- desc: Number of chunks to send if not in TTC mode
- - range: 15..8
- name: BUSY_TH_HIGH
- default: 20
- desc: Assert BUSY-ON above this threshold
- - range: 7..0
- name: BUSY_TH_LOW
- default: 15
- desc: De-assert BUSY-ON below this threshold
-
- - name: FMEMU_CONTROL
- type: W
- bitfield:
- - range: 63..56
- type: W
- name: L1A_BITNR
- default: 48
- desc: Bitfield for L1A in TTC frame
- - range: 55..48
- type: W
- name: XONXOFF_BITNR
- default: 32
- desc: Bitfield for Xon/Xoff in TTC frame
- - range: 47..47
- type: W
- name: EMU_START
- default: 0
- desc: Start emulator functionality
- - range: 46..46
- type: W
- name: TTC_MODE
- default: 0
- desc: Control the emulator by TTC input or by RegMap (1/0)
- - range: 45..45
- type: W
- name: XONXOFF
- default: 1
- desc: Enable Xon/Xoff functionality (1/0)
- - range: 44..44
- type: W
- name: INLC_CRC32
- default: 0
- desc: |
- 0: No checksum
- 1: Append the data with a CRC32
- - range: 43..43
- type: W
- name: BCR
- default: 0
- desc: Reset BCID to 0
- - range: 42..42
- type: W
- name: ECR
- default: 0
- desc: Reset L1ID to 0
- - range: 41..41
- type: W
- name: CONSTANT_CHUNK_LENGTH
- default: 0
- desc: |
- Data source select
- 0: Random chunk length
- 1: Constant chunk length
- - range: 40..32
- type: R
- name: INT_STATUS_EMU
- default: 0
- desc: Read internal status emulator
- - range: 16
- type: W
- name: FFU_FM_EMU_T
- default: 0
- desc: For Future Use (trigger registers)
- - range: 0
- type: W
- name: FE_BUSY_ENABLE
- default: 1
- desc: Enable the BUSY mechanism if L1A counter passes threshold
-
- - name: FMEMU_RANDOM_RAM_ADDR
- type: W
- desc: Controls the address of the ramblock for the random number generator
- bitfield:
- - range: 9..0
- - name: FMEMU_RANDOM_RAM
- type: W
- bitfield:
- - range: any
- type: T
- name: WE
- value: 1
- desc: Any write to this register (DATA) triggers a write to the ramblock
- - range: 39..16
- name: CHANNEL_SELECT
- value: 0xFFFFFF
- desc: Enable write enable only for the selected channel
- - range: 15..0
- name: DATA
- type: W
- desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
- - name: FMEMU_RANDOM_CONTROL
- type: W
- desc: Controls the random chunk length generator
- bitfield:
- - name: SELECT_RANDOM
- range: 20
- desc: 1 enables the random chunk length, 0 uses a constant chunk length
- default: 0
- - name: SEED
- range: 19..10
- desc: Seed for the random number generator, should not be 0
- default: 0x200
- - name: POLYNOMIAL
- range: 9..0
- desc: POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
- default: 0x240
-
- - name: FMEMU_CONFIG_WRADDR
- type: W
- bitfield:
- - range: 9..0
- value: 0
- desc: write enable for the FMEmu ram block
-
- - name: FMEMU_CONFIG
- type: W
- bitfield:
- - range: any
- type: T
- name: WE
- value: 1
- desc: Any write to register WRDATA triggers a write to the ramblock
- - range: 55..32
- name: CHANNEL_SELECT
- value: 0xFFFFFF
- desc: Enable write enable only for the selected channel
- - range: 31..0
- name: WRDATA
- type: W
- desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
-
-
-#Registers that are replicated 24 times under Generators:
-FELIG_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_DATA_GEN_CONFIG
- format_name: FELIG_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_DATA_GEN_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: USERDATA
- range: 63..48
- default: 0
- desc: Sets static payload word. When PATTERN_SEL=1.
- - name: CHUNK_LENGTH
- range: 47..32
- default: 0
- desc: FELIG data generator chunk-length in bytes.
- - name: RESET
- range: 19..15
- default: 0
- desc: FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- - name: SW_BUSY
- range: 14..10
- default: 0
- desc: FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- - name: DATA_FORMAT
- range: 9..5
- default: 0
- desc: FELIG data generator format. 0:8b10b, 1:direct.
- - name: PATTERN_SEL
- range: 4..0
- default: 0
- desc: FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
-
-FELIG_ELINK_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_CONFIG
- format_name: FELIG_ELINK_CONFIG_{index:02}
- type_name: FELIG_ELINK_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: ENDIAN_MOD
- range: 39..35
- default: 0
- desc: FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- - name: INPUT_WIDTH
- range: 34..30
- default: 0
- desc: FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- - name: OUTPUT_WIDTH
- range: 9..0
- default: 0
- desc: FELIG elink data output width.
-
-FELIG_ELINK_ENABLE_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_ENABLE
- format_name: FELIG_ELINK_ENABLE_{index:02}
- type_name: FELIG_ELINK_ENABLE
- desc: FELIG specific configuration registers
- bitfield:
- - range: 39..0
- default: 0
- desc: FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
-
-FELIG_LANE_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_LANE_CONFIG
- format_name: FELIG_LANE_CONFIG_{index:02}
- type_name: FELIG_LANE_CONFIG
- desc: FELIG specific configuration registers
- bitfield:
- - name: B_CH_BIT_SEL
- range: 63..42
- default: 0
- desc: When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- - name: A_CH_BIT_SEL
- range: 41..35
- default: 0
- desc: Selects the bit from the received FELIX data from which to extract the L1A.
- - name: LB_FIFO_DELAY
- range: 34..30
- default: 0
- desc: When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- - name: ELINK_SYNC
- range: 7..7
- default: 0
- desc: When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- - name: PICXO_OFFEST_EN
- range: 6..6
- default: 0
- desc: FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- - name: PI_HOLD
- range: 5..5
- default: 0
- desc: FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- - name: GBT_LB_ENABLE
- range: 4..4
- default: 0
- desc: FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- - name: GBH_LB_ENABLE
- range: 3..3
- default: 0
- desc: FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- - name: L1A_SOURCE
- range: 2..2
- default: 0
- desc: FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- - name: GBT_EMU_SOURCE
- range: 1..1
- default: 0
- desc: FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- - name: FG_SOURCE
- range: 0..0
- default: 0
- desc: FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
-
-FELIG_MON_TTC_0_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_0
- format_name: FELIG_MON_TTC_0_{index:02}
- type_name: FELIG_MON_TTC_0
- desc: FELIG specific configuration registers
- bitfield:
- - name: L1ID
- range: 63..40
- default: 0
- desc: Live TTC data monitor.
- - name: XL1ID
- range: 39..32
- default: 0
- desc: Live TTC data monitor.
- - name: BCID
- range: 31..20
- default: 0
- desc: Live TTC data monitor.
- - name: RESERVED0
- range: 19..16
- default: 0
- desc: Live TTC data monitor.
- - name: LEN
- range: 15..8
- default: 0
- desc: Live TTC data monitor.
- - name: FMT
- range: 7..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_TTC_1_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_1
- format_name: FELIG_MON_TTC_1_{index:02}
- type_name: FELIG_MON_TTC_1
- desc: FELIG specific configuration registers
- bitfield:
- - name: RESERVED1
- range: 63..48
- default: 0
- desc: Live TTC data monitor.
- - name: TRIGGER_TYPE
- range: 47..32
- default: 0
- desc: Live TTC data monitor.
- - name: ORBIT
- range: 31..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_COUNTERS_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_COUNTERS
- format_name: FELIG_MON_COUNTERS_{index:02}
- type_name: FELIG_MON_COUNTERS
- desc: FELIG specific configuration registers
- bitfield:
- - name: SLIDE_COUNT
- range: 63..32
- default: 0
- desc: Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- - name: FC_ERROR_COUNT
- range: 31..0
- default:
- desc: When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
-
-FELIG_MON_FREQ_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_FREQ
- format_name: FELIG_MON_FREQ_{index:02}
- type_name: FELIG_MON_FREQ
- desc: FELIG specific configuration registers
- bitfield:
- - name: TX
- range: 63..32
- default: 0
- desc: FELIG regenerated TX clock frequency[Hz].
- - name: RX
- range: 31..0
- default: 0
- desc: FELIG recovered RX clock frequency[Hz].
-
-FELIG_MON_L1A_ID_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_L1A_ID
- format_name: FELIG_MON_L1A_ID_{index:02}
- type_name: FELIG_MON_L1A_ID
- desc: FELIG specific configuration registers
- bitfield:
- - range: 31..0
- default: 0
- desc: FELIG's last L1 ID.
-
-FELIG_MON_PICXO_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_PICXO
- format_name: FELIG_MON_PICXO_{index:02}
- type_name: FELIG_MON_PICXO
- desc: FELIG specific configuration registers
- bitfield:
- - name: VLOT
- range: 53..32
- default: 0
- desc: Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- - name: ERROR
- range: 20..0
- default: 0
- desc: Value indicates RX to TX frequency tracking error.
-
-FELIG_ITK_STRIPS_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG
- format_name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG
- desc: ITk Strips emulator specific configuration test registers
- bitfield:
- - name: ITKS_FIFO_CTL
- range: 19..17
- default: 0
- desc: data fifo control 2:rst 1:rd 0:wr.
- - name: ITKS_FIFO_DATA
- range: 16..0
- default: 0
- desc: itks emu data 16:last word 15-0:data word
-
-FELIG_MON_ITK_STRIPS_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_ITK_STRIPS
- format_name: FELIG_MON_ITK_STRIPS_{index:02}
- type_name: FELIG_MON_ITK_STRIPS
- desc: ITk Strips emulator specific status registers
- bitfield:
- - name: ITKS_FIFO_STATUS
- range: 2..0
- default: 0
- desc: data fifo status 2:write done 1:full 0:empty.
-
-
-
-Wishbone:
- desc: Wishbone
- endpoints: 0
- entries:
- - name: WISHBONE_CONTROL
- type: W
- bitfield:
- - range: 32
- name: WRITE_NOT_READ
- desc: wishbone write command wishbone read command
- - range: 31..0
- name: ADDRESS
- desc: Slave address for Wishbone bus
- - name: WISHBONE_WRITE
- type: T
- bitfield:
- - range: any
- type: T
- value: 1
- name: WRITE_ENABLE
- desc: Any write to this register triggers a write to the Wupper to Wishbone fifo
- - range: 32
- name: FULL
- type: R
- - range: 31..0
- name: DATA
- type: W
- - name: WISHBONE_READ
- type: T
- bitfield:
- - range: any
- type: T
- value: 1
- name: READ_ENABLE
- desc: Any write to this register triggers a read from the Wishbone to Wupper fifo
- - range: 32
- name: EMPTY
- type: R
- desc: Indicates that the Wishbone to Wupper fifo is empty
- - range: 31..0
- name: DATA
- type: R
- desc: Wishbone read data
- - name: WISHBONE_STATUS
- type: R
- bitfield:
- - range: 4
- name: INT
- desc: interrupt
- - range: 3
- name: RETRY
- desc: Interface is not ready to accept data cycle should be retried
- - range: 2
- name: STALL
- desc: When pipelined mode slave can't accept additional transactions in its queue
- - range: 1
- name: ACKNOWLEDGE
- desc: Indicates the termination of a normal bus cycle
- - range: 0
- name: ERROR
- desc: Address not mapped by the crossbar
-
-MRODregisters:
- group: MROD_CONTROL
- desc: Specific registers for MROD
- endpoints: 0
- generate: MROD_GENERATE_REGS
- entries:
- - name: MROD_CTRL
- type: W
- bitfield:
- - range: 15..8
- name: OPTIONS
- default: 0
- desc: Extra options for MROD
- - range: 7..7
- name: ENASPARE1
- default: 0
- desc: Enable spare1
- - range: 6..6
- name: ENAMANSLIDE
- default: 0
- desc: Enable Manual Slide in Rx Locking
- - range: 5..5
- name: ENAPASSALL
- default: 0
- desc: Enable PassAll in EmptySuppress
- - range: 4..4
- name: ENATXCOUNT
- default: 0
- desc: Enable SimpleCount in TxDriver for locking
- - range: 3..0
- name: GOLTESTMODE
- default: 0
- desc: |
- GOL Test Mode (emulate CSM):
- 0: Run Data Emulator when 1; 0: stop, load emulator fifo
- 1: Enable Circulate when 1; 0: send fifo data only once
- 2: Enable Triggered Mode when 1; 0: run continueously (no TTC)
- 3: Enable pattern generator
- - name: MROD_TCVRCTRL
- type: W
- bitfield:
- - range: 23..16
- name: SLIDEMAX
- default: 0xFF
- desc: Maximum RXSLIDES before fire a TCVR reset
- - range: 15..8
- name: SLIDEWAIT
- default: 32
- desc: RXclk delay in TCVR for next RX_SLIDE operation
- - range: 7..0
- name: FRAMESIZE
- default: 20
- desc: Number of 32 data words in 1 frame
- - name: MROD_EP0_CSMENABLE
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 CSM Data Enable channel 23-0
- default: 0
- - name: MROD_EP0_EMPTYSUPPR
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Set Empty Suppression channel 23-0
- default: 0
- - name: MROD_EP0_HPTDCMODE
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Set HPTDC Mode channel 23-0
- default: 0
- - name: MROD_EP0_CLRFIFOS
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Clear FIFOs channel 23-0
- default: 0
- - name: MROD_EP0_EMULOADENA
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Emulator Load Enable channel 23-0
- default: 0
- - name: MROD_EP0_TRXLOOPBACK
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Transceiver Loopback Enable channel 23-0
- default: 0
- - name: MROD_EP0_TXCVRRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Transceiver Reset all channel 23-0
- default: 0
- - name: MROD_EP0_RXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Reset channel 23-0
- default: 0
- - name: MROD_EP0_TXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Transmitter Reset channel 23-0
- default: 0
- - name: MROD_EP1_CSMENABLE
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 CSM Data Enable channel 23-0
- default: 0
- - name: MROD_EP1_EMPTYSUPPR
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Set Empty Suppression channel 23-0
- default: 0
- - name: MROD_EP1_HPTDCMODE
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Set HPTDC Mode channel 23-0
- default: 0
- - name: MROD_EP1_CLRFIFOS
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Clear FIFOs channel 23-0
- default: 0
- - name: MROD_EP1_EMULOADENA
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Emulator Load Enable channel 23-0
- default: 0
- - name: MROD_EP1_TRXLOOPBACK
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Transceiver Loopback Enable channel 23-0
- default: 0
- - name: MROD_EP1_TXCVRRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Transceiver Reset all channel 23-0
- default: 0
- - name: MROD_EP1_RXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Reset channel 23-0
- default: 0
- - name: MROD_EP1_TXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Transmitter Reset channel 23-0
- default: 0
-
-MRODmonitors:
- group: MROD_MONITOR
- desc: Specific registers for MROD
- endpoints: 0
- generate: MROD_GENERATE_REGS
- entries:
- - name: MROD_EP0_CSMH_EMPTY
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 CSM Handler FIFO Empty 23-0
- - name: MROD_EP0_CSMH_FULL
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 CSM Handler FIFO Full 23-0
- - name: MROD_EP0_RXALIGNBSY
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Aligned monitor 23-0
- - name: MROD_EP0_RXRECDATA
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Data monitor 23-0
- - name: MROD_EP0_RXRECIDLES
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Idle monitor 23-0
- - name: MROD_EP0_TXLOCKED
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Transmitter Locked monitor 23-0
- - name: MROD_EP1_CSMH_EMPTY
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 CSM Handler FIFO Empty 23-0
- - name: MROD_EP1_CSMH_FULL
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 CSM Handler FIFO Full 23-0
- - name: MROD_EP1_RXALIGNBSY
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Aligned monitor 23-0
- - name: MROD_EP1_RXRECDATA
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Data monitor 23-0
- - name: MROD_EP1_RXRECIDLES
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Idle monitor 23-0
- - name: MROD_EP1_TXLOCKED
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Transmitter Locked monitor 23-0
-
-#
diff --git a/sources/templates/yaml/registers-4.2.yaml b/sources/templates/yaml/registers-4.2.yaml
deleted file mode 100644
index 70df3f6e702ed77ef77c610aafcd615954147843..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-4.2.yaml
+++ /dev/null
@@ -1,1994 +0,0 @@
-Registers:
- version: '4.2'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: TTCBUSYControlsAndMonitors
- record_name: register_map_ttc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: XOFF_BUSYControlsAndMonitors
- record_name: register_map_xoff_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
-# - name: Generators
-# record_name: register_map_generators
-# bitfield:
-# - range: 0..0
-# type: R
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
- - name: BUSY_THRESHOLD_ASSERT
- type: W
- desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
- default: 0x6400000
- bitfield:
- - range: 63..0
-
- - name: BUSY_THRESHOLD_NEGATE
- type: W
- desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
- default: 0x6E00000
- bitfield:
- - range: 63..0
-
- - name: BUSY_STATUS
- type: R
- bitfield:
- - range: 1
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- - range: 0
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: SW_POINTER
- desc: Pointer controlled by the software, indicating read or write status for circular DMA
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: FROMHOST
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: FW_POINTER
- desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
-
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 16
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x5000
- - ref: GBTWrapperControls
- offset: 0x6000
- - ref: GBTWrapperMonitors
- offset: 0x7000
- - ref: TTCBUSYControlsAndMonitors
- offset: 0x8000
- - ref: XOFF_BUSYControlsAndMonitors
- offset: 0x8800
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x9000
- - ref: Generators
- offset: 0xA000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: GIT_COMMIT_TIME
- bitfield:
- - range: 39..0
- value: COMMIT_DATETIME
- desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_TAG
- bitfield:
- - range: 63..0
- value: GIT_TAG(63 downto 0)
- desc: String containing the current GIT TAG
-
- - name: GIT_COMMIT_NUMBER
- bitfield:
- - range: 31..0
- value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
- desc: Number of GIT commits after current GIT_TAG
-
- - name: GIT_HASH
- bitfield:
- - range: 31..0
- value: GIT_HASH(159 downto 128)
- desc: Short GIT hash (32 bit)
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC-709
- - 710 (0x2c6): HTG-710
- - 711 (0x2c7): BNL-711
- - 712 (0x2c8): BNL-712
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - ref: INCLUDE_EGROUP
-
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
- 3: FEI4 mode
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
-
-INCLUDE_EGROUP:
- number: 7
- entries:
- - format_name: INCLUDE_EGROUP_{index}
- name: INCLUDE_EGROUP
- #type_name: INCLUDE_EGROUP
- type: R
- bitfield:
- - range: 8
- name: FROMHOST_02
- desc: FromHost EPROC02 is included in this EGROUP
- - range: 7
- name: FROMHOST_04
- desc: FromHost EPROC04 is included in this EGROUP
- - range: 6
- name: FROMHOST_08
- desc: FromHost EPROC8 is included in this EGROUP
- - range: 5
- name: FROMHOST_HDLC
- desc: FromHost HDLC is included in this EGROUP
- - range: 4
- name: TOHOST_02
- desc: ToHost EPROC02 is included in this EGROUP
- - range: 3
- name: TOHOST_04
- desc: ToHost EPROC04 is included in this EGROUP
- - range: 2
- name: TOHOST_08
- desc: ToHost EPROC08 is included in this EGROUP
- - range: 1
- name: TOHOST_16
- desc: ToHost EPROC16 is included in this EGROUP
- - range: 0
- name: TOHOST_HDLC
- desc: ToHost HDLC is included in this EGROUP
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: IC_FROMHOST_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: CR_TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - name: CR_REVERSE_10B
- desc: Reverse 10-bit word of elink data
- type: W
- bitfield:
- - range: 1
- name: FROMHOST
- default: 1
- desc: |
- 1: Serialize 10-bit word in FromHost EPROCS MSB first
- 0: Serialize 10-bit word in FromHost EPROCS LSB first
- - range: 0
- name: TOHOST
- default: 1
- desc: |
- 1: Receive 10-bit word in ToHost EPROCS, MSB first
- 0: Receive 10-bit word in ToHost EPROCS, LSB first
-
-
-# - ref: CR_XOFF_CTRL
-# offset: 0x2800
-# desc: Configure FromHost Xoff
-
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x3000
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA
- - ref: CR_DEFAULT_EPROC_ENCODING
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
-
-
-
-CR_GBT_CTRL:
- number: 24
- bitfield:
- - range: 50..0
- type: W
- entries:
- - ref: EGROUP_TOHOST
- - ref: EGROUP_FROMHOST
-
-EGROUP_TOHOST:
- number: 7
- format_name: GBT{index:02}
- name: GBT
- entries:
- - name: TOHOST
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_TOHOST_EGROUP_CTRL
- bitfield:
- - range: 58..51
- name: INSTANT_TIMEOUT_ENA
- default: 0x0
- desc: instantly initiate a timeout for the given epath
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..31
- name: MAX_CHUNK_LEN
- default: MAX_CHUNK_LEN_array
- desc: set the maximum length of a chunk, 0 disables truncation
- - range: 30..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- default:
- - PATH_ENCODING_array(0)
- - PATH_ENCODING_array(1)
- - PATH_ENCODING_array(2)
- - PATH_ENCODING_array(3)
- - PATH_ENCODING_array(4)
- - PATH_ENCODING_array(5)
- - PATH_ENCODING_array(6)
-
- - range: 14..0
- name: EPROC_ENA
- desc: Enable bits per EPROC
- default:
- - EPROC_ENA_bits_array(0)
- - EPROC_ENA_bits_array(1)
- - EPROC_ENA_bits_array(2)
- - EPROC_ENA_bits_array(3)
- - EPROC_ENA_bits_array(4)
- - EPROC_ENA_bits_array(5)
- - EPROC_ENA_bits_array(6)
-
-EGROUP_FROMHOST:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FROMHOST
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_FROMHOST_EGROUP_CTRL
- bitfield:
- - range: 54..47
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 46..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- greater than 3: TTC mode, see CentralRouter doc
- default:
- - FROMHOST_PATH_ENCODING_array(0)
- - FROMHOST_PATH_ENCODING_array(1)
- - FROMHOST_PATH_ENCODING_array(2)
- - FROMHOST_PATH_ENCODING_array(3)
- - FROMHOST_PATH_ENCODING_array(4)
- - FROMHOST_PATH_ENCODING_array(5)
- - FROMHOST_PATH_ENCODING_array(6)
- - range: 14..0
- desc: Enable bits per EPROC
- name: EPROC_ENA
-
-#CR_XOFF_CTRL:
-# number: 24
-# type: W
-# bitfield:
-# - range: 39..0
-# entries:
-# - name: FROMHOST_XOFF_ENABLE
-# format_name: FROMHOST_XOFF_ENABLE_{index:02}
-# desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
-# range: 39..0
-# default: 0
-# - name: FROMHOST_SOFT_XOFF
-# format_name: FROMHOST_SOFT_XOFF_{index:02}
-# desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
-# range: 39..0
-# default: 0
-
-
-IC_FIFOS:
- number: 24
- format_name: IC_FROMHOST_TOHOST_FIFOS
- entries:
- - name: FROMHOST
- format_name: IC_FROMHOST_FIFO_{index:02}
- type_name: IC_FROMHOST_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_FROMHOST_FIFO_{index:02}.FULL
- name: WE
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TOHOST
- format_name: IC_TOHOST_FIFO_{index:02}
- type_name: IC_TOHOST_FIFO
- type: W
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_TOHOST_FIFO_{index:02}.EMPTY
- name: RE
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- bitfield:
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- bitfield:
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
-
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- entries:
- - name: TOHOST
- type_name: TOHOST
- format_name: CR_{name}_GBT{index:02}_MON
- generate: MONITOR_CR_FULL_FLAGS = true
- bitfield:
- - range: 58
- name: CROUTFIFO_PROG_FULL
- - range: 57
- name: WMFIFO_FULL
- - range: 56
- name: MINI_EGROUP_ALMOST_FULL
- - range: 55..48
- name: EPATH6_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP6
- - range: 47..40
- name: EPATH5_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP5
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
- - name: FROMHOST
- type_name: FROMHOST
- format_name: CR_{name}_GBT{index:02}_MON
- generate: MONITOR_CR_FULL_FLAGS = true
- bitfield:
- - range: 40
- name: MINI_EGROUP_ALMOST_FULL
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
-
-CR_DEFAULT_EPROC_ENA:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- generate: MONITOR_CR_FULL_FLAGS = true
- bitfield:
- - range: 14..0
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
-
-CR_DEFAULT_EPROC_ENCODING:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- generate: MONITOR_CR_FULL_FLAGS = true
- bitfield:
- - range: 15..0
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
-
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 63..48
- name: RDDATA
- type: R
- desc: read data bus
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 0
- desc: write enable for the full mode emulator ram block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 35..0
- desc: read emu ram data
-
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_CHANNEL_DISABLE
- offset: 0x0400
- bitfield:
- - range: 47..0
- desc: Disable selected GBT or FULL mode channel
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE_SELECT
- offset: 0x0480
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RXSLIDE_MANUAL
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TXUSRRDY
- desc: TxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_RXUSRRDY
- desc: RxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_SOFT_RESET
- desc: SOFT_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTTX_RESET
- desc: GTTX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTRX_RESET
- desc: GTRX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 59..48
- name: QPLL_RESET
- desc: QPLL_RESET [11:0]
- - range: 47..0
- name: CPLL_RESET
- desc: CPLL_RESET [47:0]
-
- - name: GBT_SOFT_TX_RESET
- offset: 0x0500
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_SOFT_RX_RESET
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_ODD_EVEN
- desc: OddEven [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TOPBOT
- desc: TopBot [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_TC_DLY_VALUE3
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [143:96]
-
- - name: GBT_TX_TC_DLY_VALUE4
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [191:144]
-
- - name: GBT_DATA_TXFORMAT1
- desc: DATA_TXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_TXFORMAT2
- desc: DATA_TXFORMAT [95:48]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT1
- desc: DATA_RXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT2
- desc: DATA_RXFORMAT [95:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_RESET
- desc: TX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_RESET
- desc: RX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_METHOD
- desc: TX time domain crossing method [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUTMUX_SEL
- desc: Descrambler output MUX selection [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TC_EDGE
- desc: Sampling edge selection for TX domain crossing [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for transmitter of GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_RXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for the receiver of the GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
- - name: GBT_TOHOST_FANOUT
- offset: 0x0700
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_TOFRONTEND_FANOUT
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- desc: TX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXRESET_DONE
- desc: RX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXFSMRESET_DONE
- desc: TX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXFSMRESET_DONE
- desc: RX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_LOCK
- bitfield:
- - range: 59..48
- name: QPLL_LOCK
- desc: QPLL LOCK [11:0]
- - range: 47..0
- name: CPLL_LOCK
- desc: CPLL LOCK [47:0]
-
- - name: GBT_RXCDR_LOCK
- desc: RX CDR LOCK [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CLK_SAMPLED
- desc: clk sampled [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_HEADER
- desc: RX IS HEADER [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_DATA
- desc: RX IS DATA [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_HEADER_FOUND
- desc: RX HEADER FOUND [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUT_MUX_STATUS
- desc: GBT output mux status [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ERROR
- desc: Error flags [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GBT_TOPBOT_C
- desc: TopBot_c [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-TTCBUSYControlsAndMonitors:
- group: TTCBUSY
- desc: TTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: TTC_BUSY_ACCEPTED
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - ref: TTC_DELAY
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the BUSY Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range: 12
- name: BUSY_OUTPUT_INHIBIT
- default: 0
- desc: forces the Busy LEMO output to BUSY-OFF
- - range: 11
- name: TOHOST_RST
- desc: reset toHost in ttc decoder
- default: 0
- - range: 10
- name: TT_BCH_EN
- desc: trigger type enable / disable for TTC-ToHost
- default: 1
- - range: 9..2
- name: XL1ID_SW
- desc: set XL1ID value, the value to be set by XL1ID_RST signal
- default: 0x00
- - range: 1
- name: XL1ID_RST
- desc: giving a trigger signal to reset XL1ID value
- default: 0
- - range: 0
- name: MASTER_BUSY
- desc: L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range: 14..5
- name: TH_FF_COUNT
- desc: ToHostData Fifo counts
- - range: 4
- name: TH_FF_FULL
- desc: ToHostData Fifo status 1:full 0:not full
- - range: 3
- name: TH_FF_EMPTY
- desc: ToHostData Fifo status 1:empty 0:not empty
- - range: 2..0
- name: TTC_BIT_ERR
- desc: double bit, single bit and comm error in TTC data
-
-TTC_BUSY_ACCEPTED:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- bitfield:
- - range: 56..0
- entries:
- - name: BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
-
-
-TTC_DELAY:
- number: 48
- type: W
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Controls the TTC Fanout delay values
- bitfield:
- - range: 3..0
- default: 0
-
-XOFF_BUSYControlsAndMonitors:
- group: XOFF
- desc: XOFF Controls and Monitors, see table 2 of Busy specs manual
- endpoints: 0, 1
- entries:
- - name: XOFF_FM_CH_FIFO_THRESH_LOW
- desc: Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xC
- - range: 43..40
- name: CH10
- default: 0xC
- - range: 39..36
- name: CH09
- default: 0xC
- - range: 35..32
- name: CH08
- default: 0xC
- - range: 31..28
- name: CH07
- default: 0xC
- - range: 27..24
- name: CH06
- default: 0xC
- - range: 23..20
- name: CH05
- default: 0xC
- - range: 19..16
- name: CH04
- default: 0xC
- - range: 15..12
- name: CH03
- default: 0xC
- - range: 11..8
- name: CH02
- default: 0xC
- - range: 7..4
- name: CH01
- default: 0xC
- - range: 3..0
- name: CH00
- default: 0xC
-
- - name: XOFF_FM_CH_FIFO_THRESH_HIGH
- desc: Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xD
- - range: 43..40
- name: CH10
- default: 0xD
- - range: 39..36
- name: CH09
- default: 0xD
- - range: 35..32
- name: CH08
- default: 0xD
- - range: 31..28
- name: CH07
- default: 0xD
- - range: 27..24
- name: CH06
- default: 0xD
- - range: 23..20
- name: CH05
- default: 0xD
- - range: 19..16
- name: CH04
- default: 0xD
- - range: 15..12
- name: CH03
- default: 0xD
- - range: 11..8
- name: CH02
- default: 0xD
- - range: 7..4
- name: CH01
- default: 0xD
- - range: 3..0
- name: CH00
- default: 0xD
-
- - name: XOFF_FM_LOW_THRESH_CROSSED
- desc: FIFO filled beyond the low threshold, 1 bit per channel
- type: R
- bitfield:
- - range: 11..0
- - name: XOFF_FM_HIGH_THRESH
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- desc: Writing this register will clear all CROSS_LATCHED bits
- type: T
- value: 1
- - range: 23..12
- type: R
- name: CROSS_LATCHED
- desc: FIFO filled beyond the high threshold, 1 latch bit per channel
- - range: 11..0
- type: R
- name: CROSSED
- desc: FIFO filled beyond the high threshold, 1 bit per channel
-
- - name: XOFF_FM_SOFT_XOFF
- type: W
- desc: Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
- bitfield:
- - range: 23..0
-
- - name: XOFF_ENABLE
- type: W
- desc: Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
- bitfield:
- - range: 23..0
-
- - name: DMA_BUSY_STATUS
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR_LATCH
- desc: Any write to this register clears TOHOST_BUSY_LATCHED
- - range: 3
- type: R
- name: TOHOST_BUSY_LATCHED
- desc: A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => tohost_busy_latched_40_s)
- - range: 2
- type: R
- name: FROMHOST_BUSY_LATCHED
- desc: A fromhost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => fromhost_busy_latched_40_s)
- - range: 1
- type: R
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => fromhost_busy_40_s)
- - range: 0
- type: R
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => tohost_busy_40_s)
-
- - name: FM_BUSY_CHANNEL_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- type: T
- value: 1
- desc: Any write to this register will clear the BUSY_LATCHED bits
- - range: 23..12
- type: R
- name: BUSY_LATCHED
- desc: one Indicates that the given FULL mode channel has received BUSY-ON
- - range: 11..0
- type: R
- name: BUSY
- desc: one Indicates that the given FULL mode channel is currently in BUSY state
-
- - name: BUSY_MAIN_OUTPUT_FIFO_THRESH
- type: W
- bitfield:
- - range: 24
- name: BUSY_ENABLE
- desc: Enable busy generation if thresholds are crossed
- default: 0
- - range: 23..12
- name: LOW
- desc: Low, Negate threshold of busy generation from main output fifo
- default: 0x3FF
- - range: 11..0
- name: HIGH
- desc: High, Assert threshold of busy generation from main output fifo
- default: 0x4FF
-
- - name: BUSY_MAIN_OUTPUT_FIFO_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCHED
- value: 1
- desc: Any write to this register will clear the
- type: T
- - range: 2
- type: R
- name: HIGH_THRESH_CROSSED_LATCHED
- desc: Main output fifo has been full beyond HIGH THRESHOLD, write to clear
- - range: 1
- type: R
- name: HIGH_THRESH_CROSSED
- desc: Main output fifo is full beyond HIGH THRESHOLD
- - range: 0
- type: R
- name: LOW_THRESH_CROSSED
- desc: Main output fifo is full beyond LOW THRESHOLD
-
-
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
-
- - name: HK_MON_FMC
- type: W
- bitfield:
- - range: 1
- name: SI5345_LOL
- desc: Si5345 Loss Of Lock pin
- - range: 0
- name: SI5345_INTR
- desc: Si5345 Interrupt flagging chip change of status
-
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_SEL
- default: 0x1
- desc: |
- 1: LCLK
- 0: TTC
- - range: 2..1
- type: R
- name: MAIN_INPUT
- desc: |
- Main MMCM Oscillator Input
- 2: LCLK fixed
- 1: TTC fixed
- 0: selectable
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL-711 locked
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
-
- - name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
-
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_4
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#4
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
-
-Generators:
- group: GEN
- desc: Specific registers for Hardware based Generators
- endpoints: 0
- entries:
-
- - name: GEN_FM_CONTROL1
- type: W
- bitfield:
- - range: 63..32
- name: TIMESTAMP_INIT
- desc: Init value for the timestamp
- default: 0
- - range: 31..16
- name: PACKAGE_COUNT
- desc: Number of packets to be sent out, 0xFFFF means infinite
- default: 0
- - range: 15..0
- name: PACKAGE_LENGTH
- desc: number of 32 bit words in one FM packet
- default: 120
-
- - name: GEN_FM_CONTROL2
- type: W
- bitfield:
- - range: 16
- name: EMU_ENABLE
- default: 0
- desc: Set to 1 to enable Full mode data emulator RAM
- - range: 15..0
- name: TIMESTAMP_INCR
- desc: Timestamp increment for each sent package
- default: 1
diff --git a/sources/templates/yaml/registers-4.3.yaml b/sources/templates/yaml/registers-4.3.yaml
deleted file mode 100644
index 5bea9c94b209d78e92f1ce8656a66432ff3df815..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-4.3.yaml
+++ /dev/null
@@ -1,2337 +0,0 @@
-Registers:
- version: '4.3'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: TTCBUSYControlsAndMonitors
- record_name: register_map_ttc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: XOFF_BUSYControlsAndMonitors
- record_name: register_map_xoff_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: Generators
- record_name: register_map_generators
- bitfield:
- - range: 0..0
- type: R
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
- - name: BUSY_THRESHOLD_ASSERT
- type: W
- desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
- default: 0x6400000
- bitfield:
- - range: 63..0
-
- - name: BUSY_THRESHOLD_NEGATE
- type: W
- desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
- default: 0x6E00000
- bitfield:
- - range: 63..0
-
- - name: BUSY_STATUS
- type: R
- bitfield:
- - range: 1
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- - range: 0
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: SW_POINTER
- desc: Pointer controlled by the software, indicating read or write status for circular DMA
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: FROMHOST
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: FW_POINTER
- desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
-
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 16
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x5000
- - ref: GBTWrapperControls
- offset: 0x6000
- - ref: GBTWrapperMonitors
- offset: 0x7000
- - ref: TTCBUSYControlsAndMonitors
- offset: 0x8000
- - ref: XOFF_BUSYControlsAndMonitors
- offset: 0x8800
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x9000
- - ref: Generators
- offset: 0xA000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: GIT_COMMIT_TIME
- bitfield:
- - range: 39..0
- value: COMMIT_DATETIME
- desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_TAG
- bitfield:
- - range: 63..0
- value: GIT_TAG(63 downto 0)
- desc: String containing the current GIT TAG
-
- - name: GIT_COMMIT_NUMBER
- bitfield:
- - range: 31..0
- value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
- desc: Number of GIT commits after current GIT_TAG
-
- - name: GIT_HASH
- bitfield:
- - range: 31..0
- value: GIT_HASH(159 downto 128)
- desc: Short GIT hash (32 bit)
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC-709
- - 710 (0x2c6): HTG-710
- - 711 (0x2c7): BNL-711
- - 712 (0x2c8): BNL-712
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - ref: INCLUDE_EGROUP
-
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
- 3: FEI4 mode
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
-
-INCLUDE_EGROUP:
- number: 7
- entries:
- - format_name: INCLUDE_EGROUP_{index}
- name: INCLUDE_EGROUP
- #type_name: INCLUDE_EGROUP
- type: R
- bitfield:
- - range: 8
- name: FROMHOST_02
- desc: FromHost EPROC02 is included in this EGROUP
- - range: 7
- name: FROMHOST_04
- desc: FromHost EPROC04 is included in this EGROUP
- - range: 6
- name: FROMHOST_08
- desc: FromHost EPROC8 is included in this EGROUP
- - range: 5
- name: FROMHOST_HDLC
- desc: FromHost HDLC is included in this EGROUP
- - range: 4
- name: TOHOST_02
- desc: ToHost EPROC02 is included in this EGROUP
- - range: 3
- name: TOHOST_04
- desc: ToHost EPROC04 is included in this EGROUP
- - range: 2
- name: TOHOST_08
- desc: ToHost EPROC08 is included in this EGROUP
- - range: 1
- name: TOHOST_16
- desc: ToHost EPROC16 is included in this EGROUP
- - range: 0
- name: TOHOST_HDLC
- desc: ToHost HDLC is included in this EGROUP
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: IC_FROMHOST_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: CR_TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - name: CR_REVERSE_10B
- desc: Reverse 10-bit word of elink data
- type: W
- bitfield:
- - range: 1
- name: FROMHOST
- default: 1
- desc: |
- 1: Serialize 10-bit word in FromHost EPROCS MSB first
- 0: Serialize 10-bit word in FromHost EPROCS LSB first
- - range: 0
- name: TOHOST
- default: 1
- desc: |
- 1: Receive 10-bit word in ToHost EPROCS, MSB first
- 0: Receive 10-bit word in ToHost EPROCS, LSB first
-
-
-# - ref: CR_XOFF_CTRL
-# offset: 0x2800
-# desc: Configure FromHost Xoff
-
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x3000
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA
- - ref: CR_DEFAULT_EPROC_ENCODING
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
-
-
-
-CR_GBT_CTRL:
- number: 24
- bitfield:
- - range: 50..0
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- entries:
- - ref: EGROUP_TOHOST
- - ref: EGROUP_FROMHOST
-
-EGROUP_TOHOST:
- number: 7
- format_name: GBT{index:02}
- name: GBT
- entries:
- - name: TOHOST
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_TOHOST_EGROUP_CTRL
- bitfield:
- - range: 58..51
- name: INSTANT_TIMEOUT_ENA
- default: 0x0
- desc: instantly initiate a timeout for the given epath
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..31
- name: MAX_CHUNK_LEN
- default: MAX_CHUNK_LEN_array
- desc: set the maximum length of a chunk, 0 disables truncation
- - range: 30..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- default:
- - PATH_ENCODING_array(0)
- - PATH_ENCODING_array(1)
- - PATH_ENCODING_array(2)
- - PATH_ENCODING_array(3)
- - PATH_ENCODING_array(4)
- - PATH_ENCODING_array(5)
- - PATH_ENCODING_array(6)
-
- - range: 14..0
- name: EPROC_ENA
- desc: Enable bits per EPROC
- default:
- - EPROC_ENA_bits_array(0)
- - EPROC_ENA_bits_array(1)
- - EPROC_ENA_bits_array(2)
- - EPROC_ENA_bits_array(3)
- - EPROC_ENA_bits_array(4)
- - EPROC_ENA_bits_array(5)
- - EPROC_ENA_bits_array(6)
-
-EGROUP_FROMHOST:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FROMHOST
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_FROMHOST_EGROUP_CTRL
- bitfield:
- - range: 54..47
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 46..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- greater than 3: TTC mode, see CentralRouter doc
- default:
- - FROMHOST_PATH_ENCODING_array(0)
- - FROMHOST_PATH_ENCODING_array(1)
- - FROMHOST_PATH_ENCODING_array(2)
- - FROMHOST_PATH_ENCODING_array(3)
- - FROMHOST_PATH_ENCODING_array(4)
- - FROMHOST_PATH_ENCODING_array(5)
- - FROMHOST_PATH_ENCODING_array(6)
- - range: 14..0
- desc: Enable bits per EPROC
- name: EPROC_ENA
-
-#CR_XOFF_CTRL:
-# number: 24
-# type: W
-# bitfield:
-# - range: 39..0
-# entries:
-# - name: FROMHOST_XOFF_ENABLE
-# format_name: FROMHOST_XOFF_ENABLE_{index:02}
-# desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
-# range: 39..0
-# default: 0
-# - name: FROMHOST_SOFT_XOFF
-# format_name: FROMHOST_SOFT_XOFF_{index:02}
-# desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
-# range: 39..0
-# default: 0
-
-
-IC_FIFOS:
- number: 24
- format_name: IC_FROMHOST_TOHOST_FIFOS
- entries:
- - name: FROMHOST
- format_name: IC_FROMHOST_FIFO_{index:02}
- type_name: IC_FROMHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_FROMHOST_FIFO_{index:02}.FULL
- name: WE
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TOHOST
- format_name: IC_TOHOST_FIFO_{index:02}
- type_name: IC_TOHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_TOHOST_FIFO_{index:02}.EMPTY
- name: RE
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
-
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- entries:
- - name: TOHOST
- type_name: TOHOST
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 58
- name: CROUTFIFO_PROG_FULL
- - range: 57
- name: WMFIFO_FULL
- - range: 56
- name: MINI_EGROUP_ALMOST_FULL
- - range: 55..48
- name: EPATH6_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP6
- - range: 47..40
- name: EPATH5_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP5
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
- - name: FROMHOST
- type_name: FROMHOST
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 40
- name: MINI_EGROUP_ALMOST_FULL
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
-
-CR_DEFAULT_EPROC_ENA:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 14..0
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
-
-CR_DEFAULT_EPROC_ENCODING:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 15..0
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
-
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 63..48
- name: RDDATA
- type: R
- desc: read data bus
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 0
- desc: write enable for the full mode emulator ram block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 35..0
- desc: read emu ram data
-
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_CHANNEL_DISABLE
- offset: 0x0400
- bitfield:
- - range: 47..0
- desc: Disable selected GBT or FULL mode channel
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE_SELECT
- offset: 0x0480
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RXSLIDE_MANUAL
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TXUSRRDY
- desc: TxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_RXUSRRDY
- desc: RxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_SOFT_RESET
- desc: SOFT_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTTX_RESET
- desc: GTTX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTRX_RESET
- desc: GTRX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 59..48
- name: QPLL_RESET
- desc: QPLL_RESET [11:0]
- - range: 47..0
- name: CPLL_RESET
- desc: CPLL_RESET [47:0]
-
- - name: GBT_SOFT_TX_RESET
- offset: 0x0500
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_SOFT_RX_RESET
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_ODD_EVEN
- desc: OddEven [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TOPBOT
- desc: TopBot [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_TC_DLY_VALUE3
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [143:96]
-
- - name: GBT_TX_TC_DLY_VALUE4
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [191:144]
-
- - name: GBT_DATA_TXFORMAT1
- desc: DATA_TXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_TXFORMAT2
- desc: DATA_TXFORMAT [95:48]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT1
- desc: DATA_RXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT2
- desc: DATA_RXFORMAT [95:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_RESET
- desc: TX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_RESET
- desc: RX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_METHOD
- desc: TX time domain crossing method [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUTMUX_SEL
- desc: Descrambler output MUX selection [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TC_EDGE
- desc: Sampling edge selection for TX domain crossing [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for transmitter of GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_RXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for the receiver of the GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
- - name: GBT_TOHOST_FANOUT
- offset: 0x0700
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_TOFRONTEND_FANOUT
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- desc: TX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXRESET_DONE
- desc: RX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXFSMRESET_DONE
- desc: TX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXFSMRESET_DONE
- desc: RX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_LOCK
- bitfield:
- - range: 59..48
- name: QPLL_LOCK
- desc: QPLL LOCK [11:0]
- - range: 47..0
- name: CPLL_LOCK
- desc: CPLL LOCK [47:0]
-
- - name: GBT_RXCDR_LOCK
- desc: RX CDR LOCK [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CLK_SAMPLED
- desc: clk sampled [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_HEADER
- desc: RX IS HEADER [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_DATA
- desc: RX IS DATA [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_HEADER_FOUND
- desc: RX HEADER FOUND [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUT_MUX_STATUS
- desc: GBT output mux status [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ERROR
- desc: Error flags [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GBT_TOPBOT_C
- desc: TopBot_c [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-TTCBUSYControlsAndMonitors:
- group: TTCBUSY
- desc: TTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: TTC_BUSY_ACCEPTED
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - ref: TTC_DELAY
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the BUSY Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range: 12
- name: BUSY_OUTPUT_INHIBIT
- default: 0
- desc: forces the Busy LEMO output to BUSY-OFF
- - range: 11
- name: TOHOST_RST
- desc: reset toHost in ttc decoder
- default: 0
- - range: 10
- name: TT_BCH_EN
- desc: trigger type enable / disable for TTC-ToHost
- default: 1
- - range: 9..2
- name: XL1ID_SW
- desc: set XL1ID value, the value to be set by XL1ID_RST signal
- default: 0x00
- - range: 1
- name: XL1ID_RST
- desc: giving a trigger signal to reset XL1ID value
- default: 0
- - range: 0
- name: MASTER_BUSY
- desc: L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range: 15..5
- name: TH_FF_COUNT
- desc: ToHostData Fifo counts
- - range: 4
- name: TH_FF_FULL
- desc: ToHostData Fifo status 1:full 0:not full
- - range: 3
- name: TH_FF_EMPTY
- desc: ToHostData Fifo status 1:empty 0:not empty
- - range: 2..0
- name: TTC_BIT_ERR
- desc: double bit, single bit and comm error in TTC data
-
-TTC_BUSY_ACCEPTED:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- bitfield:
- - range: 56..0
- entries:
- - name: BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
-
-
-TTC_DELAY:
- number: 48
- type: W
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Controls the TTC Fanout delay values
- bitfield:
- - range: 3..0
- default: 0
-
-XOFF_BUSYControlsAndMonitors:
- group: XOFF
- desc: XOFF Controls and Monitors, see table 2 of Busy specs manual
- endpoints: 0, 1
- entries:
- - name: XOFF_FM_CH_FIFO_THRESH_LOW
- desc: Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xC
- - range: 43..40
- name: CH10
- default: 0xC
- - range: 39..36
- name: CH09
- default: 0xC
- - range: 35..32
- name: CH08
- default: 0xC
- - range: 31..28
- name: CH07
- default: 0xC
- - range: 27..24
- name: CH06
- default: 0xC
- - range: 23..20
- name: CH05
- default: 0xC
- - range: 19..16
- name: CH04
- default: 0xC
- - range: 15..12
- name: CH03
- default: 0xC
- - range: 11..8
- name: CH02
- default: 0xC
- - range: 7..4
- name: CH01
- default: 0xC
- - range: 3..0
- name: CH00
- default: 0xC
-
- - name: XOFF_FM_CH_FIFO_THRESH_HIGH
- desc: Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xD
- - range: 43..40
- name: CH10
- default: 0xD
- - range: 39..36
- name: CH09
- default: 0xD
- - range: 35..32
- name: CH08
- default: 0xD
- - range: 31..28
- name: CH07
- default: 0xD
- - range: 27..24
- name: CH06
- default: 0xD
- - range: 23..20
- name: CH05
- default: 0xD
- - range: 19..16
- name: CH04
- default: 0xD
- - range: 15..12
- name: CH03
- default: 0xD
- - range: 11..8
- name: CH02
- default: 0xD
- - range: 7..4
- name: CH01
- default: 0xD
- - range: 3..0
- name: CH00
- default: 0xD
-
- - name: XOFF_FM_LOW_THRESH_CROSSED
- desc: FIFO filled beyond the low threshold, 1 bit per channel
- type: R
- bitfield:
- - range: 11..0
- - name: XOFF_FM_HIGH_THRESH
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- desc: Writing this register will clear all CROSS_LATCHED bits
- type: T
- value: 1
- - range: 23..12
- type: R
- name: CROSS_LATCHED
- desc: FIFO filled beyond the high threshold, 1 latch bit per channel
- - range: 11..0
- type: R
- name: CROSSED
- desc: FIFO filled beyond the high threshold, 1 bit per channel
-
- - name: XOFF_FM_SOFT_XOFF
- type: W
- desc: Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
- bitfield:
- - range: 23..0
-
- - name: XOFF_ENABLE
- type: W
- desc: Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
- bitfield:
- - range: 23..0
-
- - name: DMA_BUSY_STATUS
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR_LATCH
- desc: Any write to this register clears TOHOST_BUSY_LATCHED
- - range: 3
- type: R
- name: TOHOST_BUSY_LATCHED
- desc: A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => tohost_busy_latched_40_s)
- - range: 2
- type: R
- name: FROMHOST_BUSY_LATCHED
- desc: A fromhost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => fromhost_busy_latched_40_s)
- - range: 1
- type: R
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => fromhost_busy_40_s)
- - range: 0
- type: R
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => tohost_busy_40_s)
-
- - name: FM_BUSY_CHANNEL_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- type: T
- value: 1
- desc: Any write to this register will clear the BUSY_LATCHED bits
- - range: 23..12
- type: R
- name: BUSY_LATCHED
- desc: one Indicates that the given FULL mode channel has received BUSY-ON
- - range: 11..0
- type: R
- name: BUSY
- desc: one Indicates that the given FULL mode channel is currently in BUSY state
-
- - name: BUSY_MAIN_OUTPUT_FIFO_THRESH
- type: W
- bitfield:
- - range: 24
- name: BUSY_ENABLE
- desc: Enable busy generation if thresholds are crossed
- default: 0
- - range: 23..12
- name: LOW
- desc: Low, Negate threshold of busy generation from main output fifo
- default: 0x3FF
- - range: 11..0
- name: HIGH
- desc: High, Assert threshold of busy generation from main output fifo
- default: 0x4FF
-
- - name: BUSY_MAIN_OUTPUT_FIFO_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCHED
- value: 1
- desc: Any write to this register will clear the
- type: T
- - range: 2
- type: R
- name: HIGH_THRESH_CROSSED_LATCHED
- desc: Main output fifo has been full beyond HIGH THRESHOLD, write to clear
- - range: 1
- type: R
- name: HIGH_THRESH_CROSSED
- desc: Main output fifo is full beyond HIGH THRESHOLD
- - range: 0
- type: R
- name: LOW_THRESH_CROSSED
- desc: Main output fifo is full beyond LOW THRESHOLD
-
-
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
-
- - name: HK_MON_FMC
- type: W
- bitfield:
- - range: 1
- name: SI5345_LOL
- desc: Si5345 Loss Of Lock pin
- - range: 0
- name: SI5345_INTR
- desc: Si5345 Interrupt flagging chip change of status
-
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_SEL
- default: 0x1
- desc: |
- 1: LCLK
- 0: TTC
- - range: 2..1
- type: R
- name: MAIN_INPUT
- desc: |
- Main MMCM Oscillator Input
- 2: LCLK fixed
- 1: TTC fixed
- 0: selectable
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL-711 locked
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
-
- - name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
-
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_4
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#4
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
-
-Generators:
- group: GEN
- desc: Specific registers for Hardware based Generators
- endpoints: 0
- generate: EMU_GENERATE_REGS = true
- entries:
-
- - name: GEN_FM_CONTROL1
- type: W
- bitfield:
- - range: 63..32
- name: TIMESTAMP_INIT
- desc: Init value for the timestamp
- default: 0
- - range: 31..16
- name: PACKAGE_COUNT
- desc: Number of packets to be sent out, 0xFFFF means infinite
- default: 0
- - range: 15..0
- name: PACKAGE_LENGTH
- desc: number of 32 bit words in one FM packet
- default: 120
-
- - name: GEN_FM_CONTROL2
- type: W
- bitfield:
- - range: 16
- name: EMU_ENABLE
- default: 0
- desc: Set to 1 to enable Full mode data emulator RAM
- - range: 15..0
- name: TIMESTAMP_INCR
- desc: Timestamp increment for each sent package
- default: 1
-
- - ref: FELIG_DATA_GEN_CONFIG_ARR
- - ref: FELIG_ELINK_CONFIG_ARR
- - ref: FELIG_ELINK_ENABLE_ARR
-
- - name: FELIG_GLOBAL_CONTROL
- type: W
- bitfield:
- - range: 63..36
- name: FAKE_L1A_RATE
- default: 0
- desc: Sets the internal fake L1 trigger rate. [25ns/LSB]
- - range: 35..14
- name: PICXO_OFFSET_PPM
- default: 0
- desc: When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
- - range: 12..12
- name: TRACK_DATA
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 11..11
- name: RXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 10..10
- name: TXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 9..9
- name: AUTO_RESET
- default: 0
- desc: FELIG GT core control. If set the GT core automatically resets on data error.
- - range: 8..8
- name: PICXO_RESET
- default: 0
- desc: FELIG GT core control. Manual PICXO reset.
- - range: 7..7
- name: GTTX_RESET
- default: 0
- desc: FELIG GT core control. Manual GT TX reset
- - range: 6..6
- name: CPLL_RESET
- default: 0
- desc: FELIG GT core control. Manual CPLL reset.
- - range: 5..0
- name: X3_X4_OUTPUT_SELECT
- default: 0
- desc: X3/X4 SMA output source select.
-
- - ref: FELIG_LANE_CONFIG_ARR
- - ref: FELIG_MON_TTC_0_ARR
- - ref: FELIG_MON_TTC_1_ARR
- - ref: FELIG_MON_COUNTERS_ARR
- - ref: FELIG_MON_FREQ_ARR
-
- - name: FELIG_MON_FREQ_GLOBAL
- type: W
- bitfield:
- - range: 63..32
- name: XTAL_100MHZ
- default: 0
- desc: FELIG local oscillator frequency[Hz].
- - range: 31..0
- name: CLK_41_667MHZ
- desc: FELIG PCIE MGTREFCLK frequency[Hz].
-
- - ref: FELIG_MON_L1A_ID_ARR
- - ref: FELIG_MON_PICXO_ARR
-
- - name: FELIG_RESET
- type: W
- bitfield:
- - range: 63..48
- name: LB_FIFO
- default: 0
- desc: One bit per lane. When set to 1, resets all loopback FIFOs.
- - range: 47..24
- name: FRAMEGEN
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG link checking logic.
- - range: 23..0
- name: LANE
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG lane logic.
-
- - name: FELIG_RX_SLIDE_RESET
- type: W
- bitfield:
- - range: 23..0
- default: 0
- desc: One bit per lane. When set to 1, resets the gbt rx slide counter.
-
-#Registers that are replicated 24 times under Generators:
-FELIG_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_DATA_GEN_CONFIG
- format_name: FELIG_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_DATA_GEN_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: USERDATA
- range: 63..48
- default: 0
- desc: Sets static payload word. When PATTERN_SEL=1.
- - name: CHUNK_LENGTH
- range: 47..32
- default: 0
- desc: FELIG data generator chunk-length in bytes.
- - name: RESET
- range: 19..15
- default: 0
- desc: FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- - name: SW_BUSY
- range: 14..10
- default: 0
- desc: FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- - name: DATA_FORMAT
- range: 9..5
- default: 0
- desc: FELIG data generator format. 0:8b10b, 1:direct.
- - name: PATTERN_SEL
- range: 4..0
- default: 0
- desc: FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
-
-FELIG_ELINK_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_CONFIG
- format_name: FELIG_ELINK_CONFIG_{index:02}
- type_name: FELIG_ELINK_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: ENDIAN_MOD
- range: 39..35
- default: 0
- desc: FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- - name: INPUT_WIDTH
- range: 34..30
- default: 0
- desc: FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- - name: OUTPUT_WIDTH
- range: 9..0
- default: 0
- desc: FELIG elink data output width.
-
-FELIG_ELINK_ENABLE_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_ENABLE
- format_name: FELIG_ELINK_ENABLE_{index:02}
- type_name: FELIG_ELINK_ENABLE
- desc: FELIG specific configuration registers
- bitfield:
- - range: 39..0
- default: 0
- desc: FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
-
-FELIG_LANE_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_LANE_CONFIG
- format_name: FELIG_LANE_CONFIG_{index:02}
- type_name: FELIG_LANE_CONFIG
- desc: FELIG specific configuration registers
- bitfield:
- - name: B_CH_BIT_SEL
- range: 63..42
- default: 0
- desc: When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- - name: A_CH_BIT_SEL
- range: 41..35
- default: 0
- desc: Selects the bit from the received FELIX data from which to extract the L1A.
- - name: LB_FIFO_DELAY
- range: 34..30
- default: 0
- desc: When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- - name: ELINK_SYNC
- range: 7..7
- default: 0
- desc: When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- - name: PICXO_OFFEST_EN
- range: 6..6
- default: 0
- desc: FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- - name: PI_HOLD
- range: 5..5
- default: 0
- desc: FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- - name: GBT_LB_ENABLE
- range: 4..4
- default: 0
- desc: FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- - name: GBH_LB_ENABLE
- range: 3..3
- default: 0
- desc: FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- - name: L1A_SOURCE
- range: 2..2
- default: 0
- desc: FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- - name: GBT_EMU_SOURCE
- range: 1..1
- default: 0
- desc: FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- - name: FG_SOURCE
- range: 0..0
- default: 0
- desc: FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
-
-FELIG_MON_TTC_0_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_0
- format_name: FELIG_MON_TTC_0_{index:02}
- type_name: FELIG_MON_TTC_0
- desc: FELIG specific configuration registers
- bitfield:
- - name: L1ID
- range: 63..40
- default: 0
- desc: Live TTC data monitor.
- - name: XL1ID
- range: 39..32
- default: 0
- desc: Live TTC data monitor.
- - name: BCID
- range: 31..20
- default: 0
- desc: Live TTC data monitor.
- - name: RESERVED0
- range: 19..16
- default: 0
- desc: Live TTC data monitor.
- - name: LEN
- range: 15..8
- default: 0
- desc: Live TTC data monitor.
- - name: FMT
- range: 7..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_TTC_1_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_1
- format_name: FELIG_MON_TTC_1_{index:02}
- type_name: FELIG_MON_TTC_1
- desc: FELIG specific configuration registers
- bitfield:
- - name: RESERVED1
- range: 63..48
- default: 0
- desc: Live TTC data monitor.
- - name: TRIGGER_TYPE
- range: 47..32
- default: 0
- desc: Live TTC data monitor.
- - name: ORBIT
- range: 31..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_COUNTERS_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_COUNTERS
- format_name: FELIG_MON_COUNTERS_{index:02}
- type_name: FELIG_MON_COUNTERS
- desc: FELIG specific configuration registers
- bitfield:
- - name: SLIDE_COUNT
- range: 63..32
- default: 0
- desc: Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- - name: FC_ERROR_COUNT
- range: 31..0
- default:
- desc: When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
-
-FELIG_MON_FREQ_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_FREQ
- format_name: FELIG_MON_FREQ_{index:02}
- type_name: FELIG_MON_FREQ
- desc: FELIG specific configuration registers
- bitfield:
- - name: TX
- range: 63..32
- default: 0
- desc: FELIG regenerated TX clock frequency[Hz].
- - name: RX
- range: 31..0
- default: 0
- desc: FELIG recovered RX clock frequency[Hz].
-
-FELIG_MON_L1A_ID_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_L1A_ID
- format_name: FELIG_MON_L1A_ID_{index:02}
- type_name: FELIG_MON_L1A_ID
- desc: FELIG specific configuration registers
- bitfield:
- - range: 31..0
- default: 0
- desc: FELIG's last L1 ID.
-
-FELIG_MON_PICXO_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_PICXO
- format_name: FELIG_MON_PICXO_{index:02}
- type_name: FELIG_MON_PICXO
- desc: FELIG specific configuration registers
- bitfield:
- - name: VLOT
- range: 53..32
- default: 0
- desc: Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- - name: ERROR
- range: 20..0
- default: 0
- desc: Value indicates RX to TX frequency tracking error.
-
diff --git a/sources/templates/yaml/registers-4.4.yaml b/sources/templates/yaml/registers-4.4.yaml
deleted file mode 100644
index 188db3f78cd1ec1af07a4d4d52db095f9ae588f1..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-4.4.yaml
+++ /dev/null
@@ -1,2451 +0,0 @@
-Registers:
- version: '4.4'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: TTCBUSYControlsAndMonitors
- record_name: register_map_ttc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: XOFF_BUSYControlsAndMonitors
- record_name: register_map_xoff_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: Generators
- record_name: register_map_generators
- bitfield:
- - range: 0..0
- type: R
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
- - name: BUSY_THRESHOLD_ASSERT
- type: W
- desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
- default: 0x6400000
- bitfield:
- - range: 63..0
-
- - name: BUSY_THRESHOLD_NEGATE
- type: W
- desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
- default: 0x6E00000
- bitfield:
- - range: 63..0
-
- - name: BUSY_STATUS
- type: R
- bitfield:
- - range: 1
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- - range: 0
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: SW_POINTER
- desc: Pointer controlled by the software, indicating read or write status for circular DMA
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: FROMHOST
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: FW_POINTER
- desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
-
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 16
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x5000
- - ref: GBTWrapperControls
- offset: 0x6000
- - ref: GBTWrapperMonitors
- offset: 0x7000
- - ref: TTCBUSYControlsAndMonitors
- offset: 0x8000
- - ref: XOFF_BUSYControlsAndMonitors
- offset: 0x8800
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x9000
- - ref: Generators
- offset: 0xA000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: GIT_COMMIT_TIME
- bitfield:
- - range: 39..0
- value: COMMIT_DATETIME
- desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_TAG
- bitfield:
- - range: 63..0
- value: GIT_TAG(63 downto 0)
- desc: String containing the current GIT TAG
-
- - name: GIT_COMMIT_NUMBER
- bitfield:
- - range: 31..0
- value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
- desc: Number of GIT commits after current GIT_TAG
-
- - name: GIT_HASH
- bitfield:
- - range: 31..0
- value: GIT_HASH(159 downto 128)
- desc: Short GIT hash (32 bit)
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC-709
- - 710 (0x2c6): HTG-710
- - 711 (0x2c7): BNL-711
- - 712 (0x2c8): BNL-712
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - ref: INCLUDE_EGROUP
-
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
- 3: FEI4 mode
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
- - name: BLOCKSIZE
- type: R
- desc: Number of bytes in a block
- bitfield:
- - range: 15..0
-
- - name: PCIE_ENDPOINT
- type: R
- desc: Indicator of the PCIe endpoint on BNL71x cards with two endpoints. 0 or 1
- bitfield:
- - range: 0
- value: std_logic_vector(to_unsigned(PCIE_ENDPOINT, 1))
-
-
-INCLUDE_EGROUP:
- number: 7
- entries:
- - format_name: INCLUDE_EGROUP_{index}
- name: INCLUDE_EGROUP
- #type_name: INCLUDE_EGROUP
- type: R
- bitfield:
- - range: 8
- name: FROMHOST_02
- desc: FromHost EPROC02 is included in this EGROUP
- - range: 7
- name: FROMHOST_04
- desc: FromHost EPROC04 is included in this EGROUP
- - range: 6
- name: FROMHOST_08
- desc: FromHost EPROC8 is included in this EGROUP
- - range: 5
- name: FROMHOST_HDLC
- desc: FromHost HDLC is included in this EGROUP
- - range: 4
- name: TOHOST_02
- desc: ToHost EPROC02 is included in this EGROUP
- - range: 3
- name: TOHOST_04
- desc: ToHost EPROC04 is included in this EGROUP
- - range: 2
- name: TOHOST_08
- desc: ToHost EPROC08 is included in this EGROUP
- - range: 1
- name: TOHOST_16
- desc: ToHost EPROC16 is included in this EGROUP
- - range: 0
- name: TOHOST_HDLC
- desc: ToHost HDLC is included in this EGROUP
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: IC_FROMHOST_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: CR_TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - name: CR_REVERSE_10B
- desc: Reverse 10-bit word of elink data
- type: W
- bitfield:
- - range: 1
- name: FROMHOST
- default: 1
- desc: |
- 1: Serialize 10-bit word in FromHost EPROCS MSB first
- 0: Serialize 10-bit word in FromHost EPROCS LSB first
- - range: 0
- name: TOHOST
- default: 1
- desc: |
- 1: Receive 10-bit word in ToHost EPROCS, MSB first
- 0: Receive 10-bit word in ToHost EPROCS, LSB first
-
- - name: CR_LTDB_TTC_DELAY
- desc: Controls TTC BCR delay in LTDB mode firmware
- type: W
- bitfield:
- - range: 7
- name: EGROUP4_EPATH6
- default: 1
- desc: |
- Egroup 4, Epath 6
- 1: Half a clock delay
- 0: no delay
- - range: 6
- name: EGROUP4_EPATH5
- default: 1
- desc: |
- Egroup 4, Epath 5
- 1: Half a clock delay
- 0: no delay
- - range: 5
- name: EGROUP4_EPATH4
- default: 1
- desc: |
- Egroup 4, Epath 4
- 1: Half a clock delay
- 0: no delay
- - range: 4
- name: EGROUP4_EPATH3
- default: 1
- desc: |
- Egroup 4, Epath 3
- 1: Half a clock delay
- 0: no delay
- - range: 3
- name: EGROUP4_EPATH0
- default: 1
- desc: |
- Egroup 4, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 2
- name: EGROUP3
- default: 1
- desc: |
- Egroup 3, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 1
- name: EGROUP2
- default: 1
- desc: |
- Egroup 2, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 0
- name: EGROUP1
- default: 1
- desc: |
- Egroup 1, Epath 0
- 1: Half a clock delay
- 0: no delay
-# - ref: CR_XOFF_CTRL
-# offset: 0x2800
-# desc: Configure FromHost Xoff
-
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x3000
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA
- - ref: CR_DEFAULT_EPROC_ENCODING
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
-
-
-
-CR_GBT_CTRL:
- number: 24
- bitfield:
- - range: 50..0
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- entries:
- - ref: EGROUP_TOHOST
- - ref: EGROUP_FROMHOST
-
-EGROUP_TOHOST:
- number: 7
- format_name: GBT{index:02}
- name: GBT
- entries:
- - name: TOHOST
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_TOHOST_EGROUP_CTRL
- bitfield:
- - range: 58..51
- name: INSTANT_TIMEOUT_ENA
- default: 0x0
- desc: instantly initiate a timeout for the given epath
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..31
- name: MAX_CHUNK_LEN
- default: MAX_CHUNK_LEN_array
- desc: set the maximum length of a chunk, 0 disables truncation
- - range: 30..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- default:
- - PATH_ENCODING_array(0)
- - PATH_ENCODING_array(1)
- - PATH_ENCODING_array(2)
- - PATH_ENCODING_array(3)
- - PATH_ENCODING_array(4)
- - PATH_ENCODING_array(5)
- - PATH_ENCODING_array(6)
-
- - range: 14..0
- name: EPROC_ENA
- desc: Enable bits per EPROC
- default:
- - EPROC_ENA_bits_array(0)
- - EPROC_ENA_bits_array(1)
- - EPROC_ENA_bits_array(2)
- - EPROC_ENA_bits_array(3)
- - EPROC_ENA_bits_array(4)
- - EPROC_ENA_bits_array(5)
- - EPROC_ENA_bits_array(6)
-
-EGROUP_FROMHOST:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FROMHOST
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_FROMHOST_EGROUP_CTRL
- bitfield:
- - range: 54..47
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 46..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- greater than 3: TTC mode, see CentralRouter doc
- default:
- - FROMHOST_PATH_ENCODING_array(0)
- - FROMHOST_PATH_ENCODING_array(1)
- - FROMHOST_PATH_ENCODING_array(2)
- - FROMHOST_PATH_ENCODING_array(3)
- - FROMHOST_PATH_ENCODING_array(4)
- - FROMHOST_PATH_ENCODING_array(5)
- - FROMHOST_PATH_ENCODING_array(6)
- - range: 14..0
- desc: Enable bits per EPROC
- name: EPROC_ENA
-
-#CR_XOFF_CTRL:
-# number: 24
-# type: W
-# bitfield:
-# - range: 39..0
-# entries:
-# - name: FROMHOST_XOFF_ENABLE
-# format_name: FROMHOST_XOFF_ENABLE_{index:02}
-# desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
-# range: 39..0
-# default: 0
-# - name: FROMHOST_SOFT_XOFF
-# format_name: FROMHOST_SOFT_XOFF_{index:02}
-# desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
-# range: 39..0
-# default: 0
-
-
-IC_FIFOS:
- number: 24
- format_name: IC_FROMHOST_TOHOST_FIFOS
- entries:
- - name: FROMHOST
- format_name: IC_FROMHOST_FIFO_{index:02}
- type_name: IC_FROMHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_FROMHOST_FIFO_{index:02}.FULL
- name: WE
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TOHOST
- format_name: IC_TOHOST_FIFO_{index:02}
- type_name: IC_TOHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_TOHOST_FIFO_{index:02}.EMPTY
- name: RE
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 7
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 6
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 5
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 4
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 9
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 8
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 7
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 6
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
-
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- entries:
- - name: TOHOST
- type_name: TOHOST
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 58
- name: CROUTFIFO_PROG_FULL
- - range: 57
- name: WMFIFO_FULL
- - range: 56
- name: MINI_EGROUP_ALMOST_FULL
- - range: 55..48
- name: EPATH6_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP6
- - range: 47..40
- name: EPATH5_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP5
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
- - name: FROMHOST
- type_name: FROMHOST
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 40
- name: MINI_EGROUP_ALMOST_FULL
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
-
-CR_DEFAULT_EPROC_ENA:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 14..0
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
-
-CR_DEFAULT_EPROC_ENCODING:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 15..0
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
-
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 63..48
- name: RDDATA
- type: R
- desc: read data bus
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 0
- desc: write enable for the full mode emulator ram block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 35..0
- desc: read emu ram data
-
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_CHANNEL_DISABLE
- offset: 0x0400
- bitfield:
- - range: 47..0
- desc: Disable selected GBT or FULL mode channel
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE_SELECT
- offset: 0x0480
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RXSLIDE_MANUAL
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TXUSRRDY
- desc: TxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_RXUSRRDY
- desc: RxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_SOFT_RESET
- desc: SOFT_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTTX_RESET
- desc: GTTX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTRX_RESET
- desc: GTRX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 59..48
- name: QPLL_RESET
- desc: QPLL_RESET [11:0]
- - range: 47..0
- name: CPLL_RESET
- desc: CPLL_RESET [47:0]
-
- - name: GBT_SOFT_TX_RESET
- offset: 0x0500
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_SOFT_RX_RESET
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_ODD_EVEN
- desc: OddEven [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TOPBOT
- desc: TopBot [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_TC_DLY_VALUE3
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [143:96]
-
- - name: GBT_TX_TC_DLY_VALUE4
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [191:144]
-
- - name: GBT_DATA_TXFORMAT1
- desc: DATA_TXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_TXFORMAT2
- desc: DATA_TXFORMAT [95:48]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT1
- desc: DATA_RXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT2
- desc: DATA_RXFORMAT [95:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_RESET
- desc: TX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_RESET
- desc: RX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_METHOD
- desc: TX time domain crossing method [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUTMUX_SEL
- desc: Descrambler output MUX selection [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TC_EDGE
- desc: Sampling edge selection for TX domain crossing [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for transmitter of GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_RXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for the receiver of the GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
- - name: GBT_TOHOST_FANOUT
- offset: 0x0700
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_TOFRONTEND_FANOUT
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- desc: TX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXRESET_DONE
- desc: RX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXFSMRESET_DONE
- desc: TX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXFSMRESET_DONE
- desc: RX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_LOCK
- bitfield:
- - range: 59..48
- name: QPLL_LOCK
- desc: QPLL LOCK [11:0]
- - range: 47..0
- name: CPLL_LOCK
- desc: CPLL LOCK [47:0]
-
- - name: GBT_RXCDR_LOCK
- desc: RX CDR LOCK [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CLK_SAMPLED
- desc: clk sampled [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_HEADER
- desc: RX IS HEADER [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_DATA
- desc: RX IS DATA [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_HEADER_FOUND
- desc: RX HEADER FOUND [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUT_MUX_STATUS
- desc: GBT output mux status [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ERROR
- desc: Error flags [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GBT_TOPBOT_C
- desc: TopBot_c [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-TTCBUSYControlsAndMonitors:
- group: TTCBUSY
- desc: TTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: TTC_BUSY_ACCEPTED
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - ref: TTC_DELAY
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the BUSY Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range: 13
- name: ECR_BCR_SWAP
- default: 0
- desc: ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
- - range: 12
- name: BUSY_OUTPUT_INHIBIT
- default: 0
- desc: forces the Busy LEMO output to BUSY-OFF
- - range: 11
- name: TOHOST_RST
- desc: reset toHost in ttc decoder
- default: 0
- - range: 10
- name: TT_BCH_EN
- desc: trigger type enable / disable for TTC-ToHost
- default: 1
- - range: 9..2
- name: XL1ID_SW
- desc: set XL1ID value, the value to be set by XL1ID_RST signal
- default: 0x00
- - range: 1
- name: XL1ID_RST
- desc: giving a trigger signal to reset XL1ID value
- default: 0
- - range: 0
- name: MASTER_BUSY
- desc: L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range: 15..5
- name: TH_FF_COUNT
- desc: ToHostData Fifo counts
- - range: 4
- name: TH_FF_FULL
- desc: ToHostData Fifo status 1:full 0:not full
- - range: 3
- name: TH_FF_EMPTY
- desc: ToHostData Fifo status 1:empty 0:not empty
- - range: 2..0
- name: TTC_BIT_ERR
- desc: double bit, single bit and comm error in TTC data
-
-TTC_BUSY_ACCEPTED:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- bitfield:
- - range: 56..0
- entries:
- - name: BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
-
-
-TTC_DELAY:
- number: 48
- type: W
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Controls the TTC Fanout delay values
- bitfield:
- - range: 3..0
- default: 0
-
-XOFF_BUSYControlsAndMonitors:
- group: XOFF
- desc: XOFF Controls and Monitors, see table 2 of Busy specs manual
- endpoints: 0, 1
- entries:
- - name: XOFF_FM_CH_FIFO_THRESH_LOW
- desc: Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xC
- - range: 43..40
- name: CH10
- default: 0xC
- - range: 39..36
- name: CH09
- default: 0xC
- - range: 35..32
- name: CH08
- default: 0xC
- - range: 31..28
- name: CH07
- default: 0xC
- - range: 27..24
- name: CH06
- default: 0xC
- - range: 23..20
- name: CH05
- default: 0xC
- - range: 19..16
- name: CH04
- default: 0xC
- - range: 15..12
- name: CH03
- default: 0xC
- - range: 11..8
- name: CH02
- default: 0xC
- - range: 7..4
- name: CH01
- default: 0xC
- - range: 3..0
- name: CH00
- default: 0xC
-
- - name: XOFF_FM_CH_FIFO_THRESH_HIGH
- desc: Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xD
- - range: 43..40
- name: CH10
- default: 0xD
- - range: 39..36
- name: CH09
- default: 0xD
- - range: 35..32
- name: CH08
- default: 0xD
- - range: 31..28
- name: CH07
- default: 0xD
- - range: 27..24
- name: CH06
- default: 0xD
- - range: 23..20
- name: CH05
- default: 0xD
- - range: 19..16
- name: CH04
- default: 0xD
- - range: 15..12
- name: CH03
- default: 0xD
- - range: 11..8
- name: CH02
- default: 0xD
- - range: 7..4
- name: CH01
- default: 0xD
- - range: 3..0
- name: CH00
- default: 0xD
-
- - name: XOFF_FM_LOW_THRESH_CROSSED
- desc: FIFO filled beyond the low threshold, 1 bit per channel
- type: R
- bitfield:
- - range: 11..0
- - name: XOFF_FM_HIGH_THRESH
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- desc: Writing this register will clear all CROSS_LATCHED bits
- type: T
- value: 1
- - range: 23..12
- type: R
- name: CROSS_LATCHED
- desc: FIFO filled beyond the high threshold, 1 latch bit per channel
- - range: 11..0
- type: R
- name: CROSSED
- desc: FIFO filled beyond the high threshold, 1 bit per channel
-
- - name: XOFF_FM_SOFT_XOFF
- type: W
- desc: Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
- bitfield:
- - range: 23..0
-
- - name: XOFF_ENABLE
- type: W
- desc: Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
- bitfield:
- - range: 23..0
-
- - name: DMA_BUSY_STATUS
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR_LATCH
- desc: Any write to this register clears TOHOST_BUSY_LATCHED
- - range: 3
- type: R
- name: TOHOST_BUSY_LATCHED
- desc: A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => tohost_busy_latched_40_s)
- - range: 2
- type: R
- name: FROMHOST_BUSY_LATCHED
- desc: A fromhost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => fromhost_busy_latched_40_s)
- - range: 1
- type: R
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => fromhost_busy_40_s)
- - range: 0
- type: R
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => tohost_busy_40_s)
-
- - name: FM_BUSY_CHANNEL_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- type: T
- value: 1
- desc: Any write to this register will clear the BUSY_LATCHED bits
- - range: 23..12
- type: R
- name: BUSY_LATCHED
- desc: one Indicates that the given FULL mode channel has received BUSY-ON
- - range: 11..0
- type: R
- name: BUSY
- desc: one Indicates that the given FULL mode channel is currently in BUSY state
-
- - name: BUSY_MAIN_OUTPUT_FIFO_THRESH
- type: W
- bitfield:
- - range: 24
- name: BUSY_ENABLE
- desc: Enable busy generation if thresholds are crossed
- default: 0
- - range: 23..12
- name: LOW
- desc: Low, Negate threshold of busy generation from main output fifo
- default: 0x3FF
- - range: 11..0
- name: HIGH
- desc: High, Assert threshold of busy generation from main output fifo
- default: 0x4FF
-
- - name: BUSY_MAIN_OUTPUT_FIFO_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCHED
- value: 1
- desc: Any write to this register will clear the
- type: T
- - range: 2
- type: R
- name: HIGH_THRESH_CROSSED_LATCHED
- desc: Main output fifo has been full beyond HIGH THRESHOLD, write to clear
- - range: 1
- type: R
- name: HIGH_THRESH_CROSSED
- desc: Main output fifo is full beyond HIGH THRESHOLD
- - range: 0
- type: R
- name: LOW_THRESH_CROSSED
- desc: Main output fifo is full beyond LOW THRESHOLD
-
-
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
-
- - name: HK_MON_FMC
- type: W
- bitfield:
- - range: 1
- name: SI5345_LOL
- desc: Si5345 Loss Of Lock pin
- - range: 0
- name: SI5345_INTR
- desc: Si5345 Interrupt flagging chip change of status
-
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_SEL
- default: 0x1
- desc: |
- 1: LCLK
- 0: TTC
- - range: 2..1
- type: R
- name: MAIN_INPUT
- desc: |
- Main MMCM Oscillator Input
- 2: LCLK fixed
- 1: TTC fixed
- 0: selectable
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL-711 locked
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
-
- - name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
-
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_4
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#4
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
-
- - name: TACH_CNT
- type: R
- desc: Readout of the Fan tachometer speed of the BNL712 board
- bitfield:
- - range: 19..0
-
-Generators:
- group: GEN
- desc: Specific registers for Hardware based Generators
- endpoints: 0
- generate: EMU_GENERATE_REGS = true
- entries:
-
- - name: GEN_FM_CONTROL1
- type: W
- bitfield:
- - range: 63..32
- name: TIMESTAMP_INIT
- desc: Init value for the timestamp
- default: 0
- - range: 31..16
- name: PACKAGE_COUNT
- desc: Number of packets to be sent out, 0xFFFF means infinite
- default: 0
- - range: 15..0
- name: PACKAGE_LENGTH
- desc: number of 32 bit words in one FM packet
- default: 120
-
- - name: GEN_FM_CONTROL2
- type: W
- bitfield:
- - range: 16
- name: EMU_ENABLE
- default: 0
- desc: Set to 1 to enable Full mode data emulator RAM
- - range: 15..0
- name: TIMESTAMP_INCR
- desc: Timestamp increment for each sent package
- default: 1
-
- - ref: FELIG_DATA_GEN_CONFIG_ARR
- - ref: FELIG_ELINK_CONFIG_ARR
- - ref: FELIG_ELINK_ENABLE_ARR
-
- - name: FELIG_GLOBAL_CONTROL
- type: W
- bitfield:
- - range: 63..36
- name: FAKE_L1A_RATE
- default: 0
- desc: Sets the internal fake L1 trigger rate. [25ns/LSB]
- - range: 35..14
- name: PICXO_OFFSET_PPM
- default: 0
- desc: When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
- - range: 12..12
- name: TRACK_DATA
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 11..11
- name: RXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 10..10
- name: TXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 9..9
- name: AUTO_RESET
- default: 0
- desc: FELIG GT core control. If set the GT core automatically resets on data error.
- - range: 8..8
- name: PICXO_RESET
- default: 0
- desc: FELIG GT core control. Manual PICXO reset.
- - range: 7..7
- name: GTTX_RESET
- default: 0
- desc: FELIG GT core control. Manual GT TX reset
- - range: 6..6
- name: CPLL_RESET
- default: 0
- desc: FELIG GT core control. Manual CPLL reset.
- - range: 5..0
- name: X3_X4_OUTPUT_SELECT
- default: 0
- desc: X3/X4 SMA output source select.
-
- - ref: FELIG_LANE_CONFIG_ARR
- - ref: FELIG_MON_TTC_0_ARR
- - ref: FELIG_MON_TTC_1_ARR
- - ref: FELIG_MON_COUNTERS_ARR
- - ref: FELIG_MON_FREQ_ARR
-
- - name: FELIG_MON_FREQ_GLOBAL
- type: W
- bitfield:
- - range: 63..32
- name: XTAL_100MHZ
- default: 0
- desc: FELIG local oscillator frequency[Hz].
- - range: 31..0
- name: CLK_41_667MHZ
- desc: FELIG PCIE MGTREFCLK frequency[Hz].
-
- - ref: FELIG_MON_L1A_ID_ARR
- - ref: FELIG_MON_PICXO_ARR
-
- - name: FELIG_RESET
- type: W
- bitfield:
- - range: 63..48
- name: LB_FIFO
- default: 0
- desc: One bit per lane. When set to 1, resets all loopback FIFOs.
- - range: 47..24
- name: FRAMEGEN
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG link checking logic.
- - range: 23..0
- name: LANE
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG lane logic.
-
- - name: FELIG_RX_SLIDE_RESET
- type: W
- bitfield:
- - range: 23..0
- default: 0
- desc: One bit per lane. When set to 1, resets the gbt rx slide counter.
-
-#Registers that are replicated 24 times under Generators:
-FELIG_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_DATA_GEN_CONFIG
- format_name: FELIG_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_DATA_GEN_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: USERDATA
- range: 63..48
- default: 0
- desc: Sets static payload word. When PATTERN_SEL=1.
- - name: CHUNK_LENGTH
- range: 47..32
- default: 0
- desc: FELIG data generator chunk-length in bytes.
- - name: RESET
- range: 19..15
- default: 0
- desc: FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- - name: SW_BUSY
- range: 14..10
- default: 0
- desc: FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- - name: DATA_FORMAT
- range: 9..5
- default: 0
- desc: FELIG data generator format. 0:8b10b, 1:direct.
- - name: PATTERN_SEL
- range: 4..0
- default: 0
- desc: FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
-
-FELIG_ELINK_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_CONFIG
- format_name: FELIG_ELINK_CONFIG_{index:02}
- type_name: FELIG_ELINK_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: ENDIAN_MOD
- range: 39..35
- default: 0
- desc: FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- - name: INPUT_WIDTH
- range: 34..30
- default: 0
- desc: FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- - name: OUTPUT_WIDTH
- range: 9..0
- default: 0
- desc: FELIG elink data output width.
-
-FELIG_ELINK_ENABLE_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_ENABLE
- format_name: FELIG_ELINK_ENABLE_{index:02}
- type_name: FELIG_ELINK_ENABLE
- desc: FELIG specific configuration registers
- bitfield:
- - range: 39..0
- default: 0
- desc: FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
-
-FELIG_LANE_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_LANE_CONFIG
- format_name: FELIG_LANE_CONFIG_{index:02}
- type_name: FELIG_LANE_CONFIG
- desc: FELIG specific configuration registers
- bitfield:
- - name: B_CH_BIT_SEL
- range: 63..42
- default: 0
- desc: When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- - name: A_CH_BIT_SEL
- range: 41..35
- default: 0
- desc: Selects the bit from the received FELIX data from which to extract the L1A.
- - name: LB_FIFO_DELAY
- range: 34..30
- default: 0
- desc: When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- - name: ELINK_SYNC
- range: 7..7
- default: 0
- desc: When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- - name: PICXO_OFFEST_EN
- range: 6..6
- default: 0
- desc: FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- - name: PI_HOLD
- range: 5..5
- default: 0
- desc: FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- - name: GBT_LB_ENABLE
- range: 4..4
- default: 0
- desc: FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- - name: GBH_LB_ENABLE
- range: 3..3
- default: 0
- desc: FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- - name: L1A_SOURCE
- range: 2..2
- default: 0
- desc: FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- - name: GBT_EMU_SOURCE
- range: 1..1
- default: 0
- desc: FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- - name: FG_SOURCE
- range: 0..0
- default: 0
- desc: FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
-
-FELIG_MON_TTC_0_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_0
- format_name: FELIG_MON_TTC_0_{index:02}
- type_name: FELIG_MON_TTC_0
- desc: FELIG specific configuration registers
- bitfield:
- - name: L1ID
- range: 63..40
- default: 0
- desc: Live TTC data monitor.
- - name: XL1ID
- range: 39..32
- default: 0
- desc: Live TTC data monitor.
- - name: BCID
- range: 31..20
- default: 0
- desc: Live TTC data monitor.
- - name: RESERVED0
- range: 19..16
- default: 0
- desc: Live TTC data monitor.
- - name: LEN
- range: 15..8
- default: 0
- desc: Live TTC data monitor.
- - name: FMT
- range: 7..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_TTC_1_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_1
- format_name: FELIG_MON_TTC_1_{index:02}
- type_name: FELIG_MON_TTC_1
- desc: FELIG specific configuration registers
- bitfield:
- - name: RESERVED1
- range: 63..48
- default: 0
- desc: Live TTC data monitor.
- - name: TRIGGER_TYPE
- range: 47..32
- default: 0
- desc: Live TTC data monitor.
- - name: ORBIT
- range: 31..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_COUNTERS_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_COUNTERS
- format_name: FELIG_MON_COUNTERS_{index:02}
- type_name: FELIG_MON_COUNTERS
- desc: FELIG specific configuration registers
- bitfield:
- - name: SLIDE_COUNT
- range: 63..32
- default: 0
- desc: Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- - name: FC_ERROR_COUNT
- range: 31..0
- default:
- desc: When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
-
-FELIG_MON_FREQ_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_FREQ
- format_name: FELIG_MON_FREQ_{index:02}
- type_name: FELIG_MON_FREQ
- desc: FELIG specific configuration registers
- bitfield:
- - name: TX
- range: 63..32
- default: 0
- desc: FELIG regenerated TX clock frequency[Hz].
- - name: RX
- range: 31..0
- default: 0
- desc: FELIG recovered RX clock frequency[Hz].
-
-FELIG_MON_L1A_ID_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_L1A_ID
- format_name: FELIG_MON_L1A_ID_{index:02}
- type_name: FELIG_MON_L1A_ID
- desc: FELIG specific configuration registers
- bitfield:
- - range: 31..0
- default: 0
- desc: FELIG's last L1 ID.
-
-FELIG_MON_PICXO_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_PICXO
- format_name: FELIG_MON_PICXO_{index:02}
- type_name: FELIG_MON_PICXO
- desc: FELIG specific configuration registers
- bitfield:
- - name: VLOT
- range: 53..32
- default: 0
- desc: Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- - name: ERROR
- range: 20..0
- default: 0
- desc: Value indicates RX to TX frequency tracking error.
-
diff --git a/sources/templates/yaml/registers-4.5.yaml b/sources/templates/yaml/registers-4.5.yaml
deleted file mode 100644
index cb2e461843c50d8194709e0b419a1823d183e8ab..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-4.5.yaml
+++ /dev/null
@@ -1,2593 +0,0 @@
-Registers:
- version: '4.5'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: TTCBUSYControlsAndMonitors
- record_name: register_map_ttc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: XOFF_BUSYControlsAndMonitors
- record_name: register_map_xoff_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: Generators
- record_name: register_map_generators
- bitfield:
- - range: 0..0
- type: R
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
- - name: BUSY_THRESHOLD_ASSERT
- type: W
- desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
- default: 0x6400000
- bitfield:
- - range: 63..0
-
- - name: BUSY_THRESHOLD_NEGATE
- type: W
- desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
- default: 0x6E00000
- bitfield:
- - range: 63..0
-
- - name: BUSY_STATUS
- type: R
- bitfield:
- - range: 1
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- - range: 0
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: SW_POINTER
- desc: Pointer controlled by the software, indicating read or write status for circular DMA
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: FROMHOST
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: FW_POINTER
- desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
-
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 16
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x5000
- - ref: GBTWrapperControls
- offset: 0x6000
- - ref: GBTWrapperMonitors
- offset: 0x7000
- - ref: TTCBUSYControlsAndMonitors
- offset: 0x8000
- - ref: XOFF_BUSYControlsAndMonitors
- offset: 0x8800
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x9000
- - ref: Generators
- offset: 0xA000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: GIT_COMMIT_TIME
- bitfield:
- - range: 39..0
- value: COMMIT_DATETIME
- desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_TAG
- bitfield:
- - range: 63..0
- value: GIT_TAG(63 downto 0)
- desc: String containing the current GIT TAG
-
- - name: GIT_COMMIT_NUMBER
- bitfield:
- - range: 31..0
- value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
- desc: Number of GIT commits after current GIT_TAG
-
- - name: GIT_HASH
- bitfield:
- - range: 31..0
- value: GIT_HASH(159 downto 128)
- desc: Short GIT hash (32 bit)
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC-709
- - 710 (0x2c6): HTG-710
- - 711 (0x2c7): BNL-711
- - 712 (0x2c8): BNL-712
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - ref: INCLUDE_EGROUP
-
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 3..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
- 3: FEI4 mode
- 4: ITK Pixel
- 5: ITK Strip
- 6: FELIG
- 7: FULL mode emulator
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
- - name: BLOCKSIZE
- type: R
- desc: Number of bytes in a block
- bitfield:
- - range: 15..0
-
- - name: PCIE_ENDPOINT
- type: R
- desc: Indicator of the PCIe endpoint on BNL71x cards with two endpoints. 0 or 1
- bitfield:
- - range: 0
- value: std_logic_vector(to_unsigned(PCIE_ENDPOINT, 1))
-
-
-INCLUDE_EGROUP:
- number: 7
- entries:
- - format_name: INCLUDE_EGROUP_{index}
- name: INCLUDE_EGROUP
- #type_name: INCLUDE_EGROUP
- type: R
- bitfield:
- - range: 8
- name: FROMHOST_02
- desc: FromHost EPROC02 is included in this EGROUP
- - range: 7
- name: FROMHOST_04
- desc: FromHost EPROC04 is included in this EGROUP
- - range: 6
- name: FROMHOST_08
- desc: FromHost EPROC8 is included in this EGROUP
- - range: 5
- name: FROMHOST_HDLC
- desc: FromHost HDLC is included in this EGROUP
- - range: 4
- name: TOHOST_02
- desc: ToHost EPROC02 is included in this EGROUP
- - range: 3
- name: TOHOST_04
- desc: ToHost EPROC04 is included in this EGROUP
- - range: 2
- name: TOHOST_08
- desc: ToHost EPROC08 is included in this EGROUP
- - range: 1
- name: TOHOST_16
- desc: ToHost EPROC16 is included in this EGROUP
- - range: 0
- name: TOHOST_HDLC
- desc: ToHost HDLC is included in this EGROUP
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: IC_FROMHOST_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: CR_TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - name: CR_REVERSE_10B
- desc: Reverse 10-bit word of elink data
- type: W
- bitfield:
- - range: 1
- name: FROMHOST
- default: 1
- desc: |
- 1: Serialize 10-bit word in FromHost EPROCS MSB first
- 0: Serialize 10-bit word in FromHost EPROCS LSB first
- - range: 0
- name: TOHOST
- default: 1
- desc: |
- 1: Receive 10-bit word in ToHost EPROCS, MSB first
- 0: Receive 10-bit word in ToHost EPROCS, LSB first
-
- - name: CR_LTDB_TTC_DELAY
- desc: Controls TTC BCR delay in LTDB mode firmware
- type: W
- bitfield:
- - range: 7
- name: EGROUP4_EPATH6
- default: 0
- desc: |
- Egroup 4, Epath 6
- 1: Half a clock delay
- 0: no delay
- - range: 6
- name: EGROUP4_EPATH5
- default: 0
- desc: |
- Egroup 4, Epath 5
- 1: Half a clock delay
- 0: no delay
- - range: 5
- name: EGROUP4_EPATH4
- default: 0
- desc: |
- Egroup 4, Epath 4
- 1: Half a clock delay
- 0: no delay
- - range: 4
- name: EGROUP4_EPATH3
- default: 0
- desc: |
- Egroup 4, Epath 3
- 1: Half a clock delay
- 0: no delay
- - range: 3
- name: EGROUP4_EPATH0
- default: 0
- desc: |
- Egroup 4, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 2
- name: EGROUP3
- default: 0
- desc: |
- Egroup 3, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 1
- name: EGROUP2
- default: 0
- desc: |
- Egroup 2, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 0
- name: EGROUP1
- default: 0
- desc: |
- Egroup 1, Epath 0
- 1: Half a clock delay
- 0: no delay
-# - ref: CR_XOFF_CTRL
-# offset: 0x2800
-# desc: Configure FromHost Xoff
-
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x3000
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA
- - ref: CR_DEFAULT_EPROC_ENCODING
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
- - ref: CR_BLOCK_COUNTERS
-
-
-CR_GBT_CTRL:
- number: 24
- bitfield:
- - range: 50..0
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- entries:
- - ref: EGROUP_TOHOST
- - ref: EGROUP_FROMHOST
-
-EGROUP_TOHOST:
- number: 7
- format_name: GBT{index:02}
- name: GBT
- entries:
- - name: TOHOST
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_TOHOST_EGROUP_CTRL
- bitfield:
- - range: 58..51
- name: INSTANT_TIMEOUT_ENA
- default: 0x0
- desc: instantly initiate a timeout for the given epath
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..31
- name: MAX_CHUNK_LEN
- default: MAX_CHUNK_LEN_array
- desc: set the maximum length of a chunk, 0 disables truncation
- - range: 30..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- default:
- - PATH_ENCODING_array(0)
- - PATH_ENCODING_array(1)
- - PATH_ENCODING_array(2)
- - PATH_ENCODING_array(3)
- - PATH_ENCODING_array(4)
- - PATH_ENCODING_array(5)
- - PATH_ENCODING_array(6)
-
- - range: 14..0
- name: EPROC_ENA
- desc: Enable bits per EPROC
- default:
- - EPROC_ENA_bits_array(0)
- - EPROC_ENA_bits_array(1)
- - EPROC_ENA_bits_array(2)
- - EPROC_ENA_bits_array(3)
- - EPROC_ENA_bits_array(4)
- - EPROC_ENA_bits_array(5)
- - EPROC_ENA_bits_array(6)
-
-EGROUP_FROMHOST:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FROMHOST
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_FROMHOST_EGROUP_CTRL
- bitfield:
- - range: 54..47
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 46..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- greater than 3: TTC mode, see CentralRouter doc
- default:
- - FROMHOST_PATH_ENCODING_array(0)
- - FROMHOST_PATH_ENCODING_array(1)
- - FROMHOST_PATH_ENCODING_array(2)
- - FROMHOST_PATH_ENCODING_array(3)
- - FROMHOST_PATH_ENCODING_array(4)
- - FROMHOST_PATH_ENCODING_array(5)
- - FROMHOST_PATH_ENCODING_array(6)
- - range: 14..0
- desc: Enable bits per EPROC
- name: EPROC_ENA
-
-#CR_XOFF_CTRL:
-# number: 24
-# type: W
-# bitfield:
-# - range: 39..0
-# entries:
-# - name: FROMHOST_XOFF_ENABLE
-# format_name: FROMHOST_XOFF_ENABLE_{index:02}
-# desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
-# range: 39..0
-# default: 0
-# - name: FROMHOST_SOFT_XOFF
-# format_name: FROMHOST_SOFT_XOFF_{index:02}
-# desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
-# range: 39..0
-# default: 0
-
-
-IC_FIFOS:
- number: 24
- format_name: IC_FROMHOST_TOHOST_FIFOS
- entries:
- - name: FROMHOST
- format_name: IC_FROMHOST_FIFO_{index:02}
- type_name: IC_FROMHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_FROMHOST_FIFO_{index:02}.FULL
- name: WE
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TOHOST
- format_name: IC_TOHOST_FIFO_{index:02}
- type_name: IC_TOHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_TOHOST_FIFO_{index:02}.EMPTY
- name: RE
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 7
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 6
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 5
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 4
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 9
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 8
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 7
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 6
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
-
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- entries:
- - name: TOHOST
- type_name: TOHOST
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 58
- name: CROUTFIFO_PROG_FULL
- - range: 57
- name: WMFIFO_FULL
- - range: 56
- name: MINI_EGROUP_ALMOST_FULL
- - range: 55..48
- name: EPATH6_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP6
- - range: 47..40
- name: EPATH5_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP5
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
- - name: FROMHOST
- type_name: FROMHOST
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 40
- name: MINI_EGROUP_ALMOST_FULL
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
-
-CR_DEFAULT_EPROC_ENA:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 14..0
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
-
-CR_DEFAULT_EPROC_ENCODING:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 15..0
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
-
-CR_BLOCK_COUNTERS:
- desc: Counters to count blocks per GBT channel
- endpoints: 0,1
- number: 24
- entries:
- - name: BLOCK_COUNT
- type_name: CR_BLOCK_COUNT
- format_name: CR_{name}_GBT{index:02}
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- type: W
- bitfield:
- - range: any
- type: T
- name: RESET
- desc: Any write clears the counter value
- value: 1
- - range: 31..0
- type: R
- name: VAL
- desc: Counts the number of blocks that were transferred ToHost in the specified GBT
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 63..48
- name: RDDATA
- type: R
- desc: read data bus
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 0
- desc: write enable for the full mode emulator ram block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 35..0
- desc: read emu ram data
-
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_CHANNEL_DISABLE
- offset: 0x0400
- bitfield:
- - range: 47..0
- desc: Disable selected GBT or FULL mode channel
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE_SELECT
- offset: 0x0480
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RXSLIDE_MANUAL
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TXUSRRDY
- desc: TxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_RXUSRRDY
- desc: RxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_SOFT_RESET
- desc: SOFT_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTTX_RESET
- desc: GTTX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTRX_RESET
- desc: GTRX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 59..48
- name: QPLL_RESET
- desc: QPLL_RESET [11:0]
- - range: 47..0
- name: CPLL_RESET
- desc: CPLL_RESET [47:0]
-
- - name: GBT_SOFT_TX_RESET
- offset: 0x0500
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_SOFT_RX_RESET
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_ODD_EVEN
- desc: OddEven [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TOPBOT
- desc: TopBot [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_TC_DLY_VALUE3
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [143:96]
-
- - name: GBT_TX_TC_DLY_VALUE4
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [191:144]
-
- - name: GBT_DATA_TXFORMAT1
- desc: DATA_TXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_TXFORMAT2
- desc: DATA_TXFORMAT [95:48]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT1
- desc: DATA_RXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT2
- desc: DATA_RXFORMAT [95:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_RESET
- desc: TX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_RESET
- desc: RX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_METHOD
- desc: TX time domain crossing method [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUTMUX_SEL
- desc: Descrambler output MUX selection [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TC_EDGE
- desc: Sampling edge selection for TX domain crossing [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for transmitter of GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_RXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for the receiver of the GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
- - name: GBT_TOHOST_FANOUT
- offset: 0x0700
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_TOFRONTEND_FANOUT
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- desc: TX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXRESET_DONE
- desc: RX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXFSMRESET_DONE
- desc: TX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXFSMRESET_DONE
- desc: RX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_LOCK
- bitfield:
- - range: 59..48
- name: QPLL_LOCK
- desc: QPLL LOCK [11:0]
- - range: 47..0
- name: CPLL_LOCK
- desc: CPLL LOCK [47:0]
-
- - name: GBT_RXCDR_LOCK
- desc: RX CDR LOCK [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CLK_SAMPLED
- desc: clk sampled [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_HEADER
- desc: RX IS HEADER [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_DATA
- desc: RX IS DATA [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_HEADER_FOUND
- desc: RX HEADER FOUND [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUT_MUX_STATUS
- desc: GBT output mux status [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ERROR
- desc: Error flags [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GBT_TOPBOT_C
- desc: TopBot_c [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-TTCBUSYControlsAndMonitors:
- group: TTCBUSY
- desc: TTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: TTC_BUSY_ACCEPTED
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - ref: TTC_DELAY
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the BUSY Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range: 13
- name: ECR_BCR_SWAP
- default: 0
- desc: ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
- - range: 12
- name: BUSY_OUTPUT_INHIBIT
- default: 0
- desc: forces the Busy LEMO output to BUSY-OFF
- - range: 11
- name: TOHOST_RST
- desc: reset toHost in ttc decoder
- default: 0
- - range: 10
- name: TT_BCH_EN
- desc: trigger type enable / disable for TTC-ToHost
- default: 1
- - range: 9..2
- name: XL1ID_SW
- desc: set XL1ID value, the value to be set by XL1ID_RST signal
- default: 0x00
- - range: 1
- name: XL1ID_RST
- desc: giving a trigger signal to reset XL1ID value
- default: 0
- - range: 0
- name: MASTER_BUSY
- desc: L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range: 15..5
- name: TH_FF_COUNT
- desc: ToHostData Fifo counts
- - range: 4
- name: TH_FF_FULL
- desc: ToHostData Fifo status 1:full 0:not full
- - range: 3
- name: TH_FF_EMPTY
- desc: ToHostData Fifo status 1:empty 0:not empty
- - range: 2..0
- name: TTC_BIT_ERR
- desc: double bit, single bit and comm error in TTC data
-
-TTC_BUSY_ACCEPTED:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- bitfield:
- - range: 56..0
- entries:
- - name: BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
-
-
-TTC_DELAY:
- number: 48
- type: W
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Controls the TTC Fanout delay values
- bitfield:
- - range: 3..0
- default: 0
-
-XOFF_BUSYControlsAndMonitors:
- group: XOFF
- desc: XOFF Controls and Monitors, see table 2 of Busy specs manual
- endpoints: 0, 1
- entries:
- - name: XOFF_FM_CH_FIFO_THRESH_LOW
- desc: Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xC
- - range: 43..40
- name: CH10
- default: 0xC
- - range: 39..36
- name: CH09
- default: 0xC
- - range: 35..32
- name: CH08
- default: 0xC
- - range: 31..28
- name: CH07
- default: 0xC
- - range: 27..24
- name: CH06
- default: 0xC
- - range: 23..20
- name: CH05
- default: 0xC
- - range: 19..16
- name: CH04
- default: 0xC
- - range: 15..12
- name: CH03
- default: 0xC
- - range: 11..8
- name: CH02
- default: 0xC
- - range: 7..4
- name: CH01
- default: 0xC
- - range: 3..0
- name: CH00
- default: 0xC
-
- - name: XOFF_FM_CH_FIFO_THRESH_HIGH
- desc: Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xD
- - range: 43..40
- name: CH10
- default: 0xD
- - range: 39..36
- name: CH09
- default: 0xD
- - range: 35..32
- name: CH08
- default: 0xD
- - range: 31..28
- name: CH07
- default: 0xD
- - range: 27..24
- name: CH06
- default: 0xD
- - range: 23..20
- name: CH05
- default: 0xD
- - range: 19..16
- name: CH04
- default: 0xD
- - range: 15..12
- name: CH03
- default: 0xD
- - range: 11..8
- name: CH02
- default: 0xD
- - range: 7..4
- name: CH01
- default: 0xD
- - range: 3..0
- name: CH00
- default: 0xD
-
- - name: XOFF_FM_LOW_THRESH_CROSSED
- desc: FIFO filled beyond the low threshold, 1 bit per channel
- type: R
- bitfield:
- - range: 11..0
- - name: XOFF_FM_HIGH_THRESH
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- desc: Writing this register will clear all CROSS_LATCHED bits
- type: T
- value: 1
- - range: 23..12
- type: R
- name: CROSS_LATCHED
- desc: FIFO filled beyond the high threshold, 1 latch bit per channel
- - range: 11..0
- type: R
- name: CROSSED
- desc: FIFO filled beyond the high threshold, 1 bit per channel
-
- - name: XOFF_FM_SOFT_XOFF
- type: W
- desc: Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
- bitfield:
- - range: 23..0
-
- - name: XOFF_ENABLE
- type: W
- desc: Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
- bitfield:
- - range: 23..0
-
- - name: DMA_BUSY_STATUS
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR_LATCH
- desc: Any write to this register clears TOHOST_BUSY_LATCHED
- - range: 3
- type: R
- name: TOHOST_BUSY_LATCHED
- desc: A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => tohost_busy_latched_40_s)
- - range: 2
- type: R
- name: FROMHOST_BUSY_LATCHED
- desc: A fromhost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => fromhost_busy_latched_40_s)
- - range: 1
- type: R
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => fromhost_busy_40_s)
- - range: 0
- type: R
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => tohost_busy_40_s)
-
- - name: FM_BUSY_CHANNEL_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- type: T
- value: 1
- desc: Any write to this register will clear the BUSY_LATCHED bits
- - range: 23..12
- type: R
- name: BUSY_LATCHED
- desc: one Indicates that the given FULL mode channel has received BUSY-ON
- - range: 11..0
- type: R
- name: BUSY
- desc: one Indicates that the given FULL mode channel is currently in BUSY state
-
- - name: BUSY_MAIN_OUTPUT_FIFO_THRESH
- type: W
- bitfield:
- - range: 24
- name: BUSY_ENABLE
- desc: Enable busy generation if thresholds are crossed
- default: 0
- - range: 23..12
- name: LOW
- desc: Low, Negate threshold of busy generation from main output fifo
- default: 0x3FF
- - range: 11..0
- name: HIGH
- desc: High, Assert threshold of busy generation from main output fifo
- default: 0x4FF
-
- - name: BUSY_MAIN_OUTPUT_FIFO_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCHED
- value: 1
- desc: Any write to this register will clear the
- type: T
- - range: 2
- type: R
- name: HIGH_THRESH_CROSSED_LATCHED
- desc: Main output fifo has been full beyond HIGH THRESHOLD, write to clear
- - range: 1
- type: R
- name: HIGH_THRESH_CROSSED
- desc: Main output fifo is full beyond HIGH THRESHOLD
- - range: 0
- type: R
- name: LOW_THRESH_CROSSED
- desc: Main output fifo is full beyond LOW THRESHOLD
-
-
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
-
- - name: HK_MON_FMC
- type: W
- bitfield:
- - range: 1
- name: SI5345_LOL
- desc: Si5345 Loss Of Lock pin
- - range: 0
- name: SI5345_INTR
- desc: Si5345 Interrupt flagging chip change of status
-
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_SEL
- default: 0x1
- desc: |
- 1: LCLK
- 0: TTC
- - range: 2..1
- type: R
- name: MAIN_INPUT
- desc: |
- Main MMCM Oscillator Input
- 2: LCLK fixed
- 1: TTC fixed
- 0: selectable
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL-711 locked
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
-
- - name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
-
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_4
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#4
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
-
- - name: TACH_CNT
- type: R
- desc: Readout of the Fan tachometer speed of the BNL712 board
- bitfield:
- - range: 19..0
-
-Generators:
- group: GEN
- desc: Specific registers for Hardware based Generators
- endpoints: 0
- generate: EMU_GENERATE_REGS = true
- entries:
-
- - ref: FELIG_DATA_GEN_CONFIG_ARR
- offset: 0x20
- - ref: FELIG_ELINK_CONFIG_ARR
- - ref: FELIG_ELINK_ENABLE_ARR
-
- - name: FELIG_GLOBAL_CONTROL
- type: W
- bitfield:
- - range: 63..36
- name: FAKE_L1A_RATE
- default: 0
- desc: Sets the internal fake L1 trigger rate. [25ns/LSB]
- - range: 35..14
- name: PICXO_OFFSET_PPM
- default: 0
- desc: When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
- - range: 12..12
- name: TRACK_DATA
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 11..11
- name: RXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 10..10
- name: TXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 9..9
- name: AUTO_RESET
- default: 0
- desc: FELIG GT core control. If set the GT core automatically resets on data error.
- - range: 8..8
- name: PICXO_RESET
- default: 0
- desc: FELIG GT core control. Manual PICXO reset.
- - range: 7..7
- name: GTTX_RESET
- default: 0
- desc: FELIG GT core control. Manual GT TX reset
- - range: 6..6
- name: CPLL_RESET
- default: 0
- desc: FELIG GT core control. Manual CPLL reset.
- - range: 5..0
- name: X3_X4_OUTPUT_SELECT
- default: 0
- desc: X3/X4 SMA output source select.
-
- - ref: FELIG_LANE_CONFIG_ARR
- - ref: FELIG_MON_TTC_0_ARR
- - ref: FELIG_MON_TTC_1_ARR
- - ref: FELIG_MON_COUNTERS_ARR
- - ref: FELIG_MON_FREQ_ARR
-
- - name: FELIG_MON_FREQ_GLOBAL
- type: W
- bitfield:
- - range: 63..32
- name: XTAL_100MHZ
- default: 0
- desc: FELIG local oscillator frequency[Hz].
- - range: 31..0
- name: CLK_41_667MHZ
- desc: FELIG PCIE MGTREFCLK frequency[Hz].
-
- - ref: FELIG_MON_L1A_ID_ARR
- - ref: FELIG_MON_PICXO_ARR
-
- - name: FELIG_RESET
- type: W
- bitfield:
- - range: 63..48
- name: LB_FIFO
- default: 0
- desc: One bit per lane. When set to 1, resets all loopback FIFOs.
- - range: 47..24
- name: FRAMEGEN
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG link checking logic.
- - range: 23..0
- name: LANE
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG lane logic.
-
- - name: FELIG_RX_SLIDE_RESET
- type: W
- bitfield:
- - range: 23..0
- default: 0
- desc: One bit per lane. When set to 1, resets the gbt rx slide counter.
-
- - name: FMEMU_EVENT_INFO
- type: W
- offset: 0x1800
- bitfield:
- - range: 63..32
- name: L1ID
- default: 0
- desc: 32b field to show L1ID
- - range: 31..0
- name: BCID
- default: 0
- desc: 32b field to show BCID
-
- - name: FMEMU_COUNTERS
- type: W
- bitfield:
- - range: 63..48
- name: WORD_CNT
- default: 32
- desc: Number of 32b words in one chunk
- - range: 47..32
- name: IDLE_CNT
- default: 3
- desc: Minimum number of idles between chunks
- - range: 31..16
- name: L1A_CNT
- default: 256
- desc: Number of chunks to send if not in TTC mode
- - range: 15..8
- name: BUSY_TH_HIGH
- default: 20
- desc: Assert BUSY-ON above this threshold
- - range: 7..0
- name: BUSY_TH_LOW
- default: 15
- desc: De-assert BUSY-ON below this threshold
-
- - name: FMEMU_CONTROL
- type: W
- bitfield:
- - range: 63..56
- type: W
- name: L1A_BITNR
- default: 32
- desc: Bitfield for L1A in TTC frame
- - range: 55..48
- type: W
- name: XONXOFF_BITNR
- default: 32
- desc: Bitfield for Xon/Xoff in TTC frame
- - range: 47..47
- type: W
- name: EMU_START
- default: 0
- desc: Start emulator functionality
- - range: 46..46
- type: W
- name: TTC_MODE
- default: 0
- desc: Control the emulator by TTC input or by RegMap (1/0)
- - range: 45..45
- type: W
- name: XONXOFF
- default: 0
- desc: Debug Xon/Xoff functionality (1/0)
- - range: 44..44
- type: W
- name: INLC_CRC32
- default: 0
- desc: |
- 0: No checksum
- 1: Append the data with a CRC32
- - range: 43..43
- type: W
- name: BCR
- default: 0
- desc: Reset BCID to 0
- - range: 42..42
- type: W
- name: ECR
- default: 0
- desc: Reset L1ID to 0
- - range: 41..41
- type: W
- name: DATA_SRC_SEL
- default: 0
- desc: |
- Data source select
- 0: Data input comes from EMURAM
- 1: Data input comes from PCIe
- - range: 40..32
- type: R
- name: INT_STATUS_EMU
- default: 0
- desc: Read internal status emulator
- - range: 31..16
- type: W
- name: FFU_FM_EMU_T
- default: 0
- desc: For Future Use (trigger registers)
- - range: 15..0
- type: W
- name: FFU_FM_EMU_W
- default: 0
- desc: For Future Use (write registers)
-
- - name: FMEMU_RANDOM_RAM_ADDR
- type: W
- desc: Controls the address of the ramblock for the random number generator
- bitfield:
- - range: 9..0
- - name: FMEMU_RANDOM_RAM
- type: W
- bitfield:
- - range: any
- type: T
- name: WE
- value: 1
- desc: Any write to this register (DATA) triggers a write to the ramblock
- - range: 39..16
- name: CHANNEL_SELECT
- value: 0xFFFFFF
- desc: Enable write enable only for the selected channel
- - range: 15..0
- name: DATA
- type: W
- desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
- - name: FMEMU_RANDOM_CONTROL
- type: W
- desc: Controls the random chunk length generator
- bitfield:
- - name: SELECT_RANDOM
- range: 20
- desc: 1 enables the random chunk length, 0 uses a constant chunk length
- default: 0
- - name: SEED
- range: 19..10
- desc: Seed for the random number generator, should not be 0
- default: 0x200
- - name: POLYNOMIAL
- range: 9..0
- desc: POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
- default: 0x240
-
-
-#Registers that are replicated 24 times under Generators:
-FELIG_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_DATA_GEN_CONFIG
- format_name: FELIG_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_DATA_GEN_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: USERDATA
- range: 63..48
- default: 0
- desc: Sets static payload word. When PATTERN_SEL=1.
- - name: CHUNK_LENGTH
- range: 47..32
- default: 0
- desc: FELIG data generator chunk-length in bytes.
- - name: RESET
- range: 19..15
- default: 0
- desc: FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- - name: SW_BUSY
- range: 14..10
- default: 0
- desc: FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- - name: DATA_FORMAT
- range: 9..5
- default: 0
- desc: FELIG data generator format. 0:8b10b, 1:direct.
- - name: PATTERN_SEL
- range: 4..0
- default: 0
- desc: FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
-
-FELIG_ELINK_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_CONFIG
- format_name: FELIG_ELINK_CONFIG_{index:02}
- type_name: FELIG_ELINK_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: ENDIAN_MOD
- range: 39..35
- default: 0
- desc: FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- - name: INPUT_WIDTH
- range: 34..30
- default: 0
- desc: FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- - name: OUTPUT_WIDTH
- range: 9..0
- default: 0
- desc: FELIG elink data output width.
-
-FELIG_ELINK_ENABLE_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_ENABLE
- format_name: FELIG_ELINK_ENABLE_{index:02}
- type_name: FELIG_ELINK_ENABLE
- desc: FELIG specific configuration registers
- bitfield:
- - range: 39..0
- default: 0
- desc: FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
-
-FELIG_LANE_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_LANE_CONFIG
- format_name: FELIG_LANE_CONFIG_{index:02}
- type_name: FELIG_LANE_CONFIG
- desc: FELIG specific configuration registers
- bitfield:
- - name: B_CH_BIT_SEL
- range: 63..42
- default: 0
- desc: When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- - name: A_CH_BIT_SEL
- range: 41..35
- default: 0
- desc: Selects the bit from the received FELIX data from which to extract the L1A.
- - name: LB_FIFO_DELAY
- range: 34..30
- default: 0
- desc: When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- - name: ELINK_SYNC
- range: 7..7
- default: 0
- desc: When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- - name: PICXO_OFFEST_EN
- range: 6..6
- default: 0
- desc: FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- - name: PI_HOLD
- range: 5..5
- default: 0
- desc: FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- - name: GBT_LB_ENABLE
- range: 4..4
- default: 0
- desc: FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- - name: GBH_LB_ENABLE
- range: 3..3
- default: 0
- desc: FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- - name: L1A_SOURCE
- range: 2..2
- default: 0
- desc: FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- - name: GBT_EMU_SOURCE
- range: 1..1
- default: 0
- desc: FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- - name: FG_SOURCE
- range: 0..0
- default: 0
- desc: FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
-
-FELIG_MON_TTC_0_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_0
- format_name: FELIG_MON_TTC_0_{index:02}
- type_name: FELIG_MON_TTC_0
- desc: FELIG specific configuration registers
- bitfield:
- - name: L1ID
- range: 63..40
- default: 0
- desc: Live TTC data monitor.
- - name: XL1ID
- range: 39..32
- default: 0
- desc: Live TTC data monitor.
- - name: BCID
- range: 31..20
- default: 0
- desc: Live TTC data monitor.
- - name: RESERVED0
- range: 19..16
- default: 0
- desc: Live TTC data monitor.
- - name: LEN
- range: 15..8
- default: 0
- desc: Live TTC data monitor.
- - name: FMT
- range: 7..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_TTC_1_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_1
- format_name: FELIG_MON_TTC_1_{index:02}
- type_name: FELIG_MON_TTC_1
- desc: FELIG specific configuration registers
- bitfield:
- - name: RESERVED1
- range: 63..48
- default: 0
- desc: Live TTC data monitor.
- - name: TRIGGER_TYPE
- range: 47..32
- default: 0
- desc: Live TTC data monitor.
- - name: ORBIT
- range: 31..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_COUNTERS_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_COUNTERS
- format_name: FELIG_MON_COUNTERS_{index:02}
- type_name: FELIG_MON_COUNTERS
- desc: FELIG specific configuration registers
- bitfield:
- - name: SLIDE_COUNT
- range: 63..32
- default: 0
- desc: Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- - name: FC_ERROR_COUNT
- range: 31..0
- default:
- desc: When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
-
-FELIG_MON_FREQ_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_FREQ
- format_name: FELIG_MON_FREQ_{index:02}
- type_name: FELIG_MON_FREQ
- desc: FELIG specific configuration registers
- bitfield:
- - name: TX
- range: 63..32
- default: 0
- desc: FELIG regenerated TX clock frequency[Hz].
- - name: RX
- range: 31..0
- default: 0
- desc: FELIG recovered RX clock frequency[Hz].
-
-FELIG_MON_L1A_ID_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_L1A_ID
- format_name: FELIG_MON_L1A_ID_{index:02}
- type_name: FELIG_MON_L1A_ID
- desc: FELIG specific configuration registers
- bitfield:
- - range: 31..0
- default: 0
- desc: FELIG's last L1 ID.
-
-FELIG_MON_PICXO_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_PICXO
- format_name: FELIG_MON_PICXO_{index:02}
- type_name: FELIG_MON_PICXO
- desc: FELIG specific configuration registers
- bitfield:
- - name: VLOT
- range: 53..32
- default: 0
- desc: Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- - name: ERROR
- range: 20..0
- default: 0
- desc: Value indicates RX to TX frequency tracking error.
-
diff --git a/sources/templates/yaml/registers-4.6.yaml b/sources/templates/yaml/registers-4.6.yaml
deleted file mode 100644
index 4695257e216c71c37573c7a16759fd872916e40c..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-4.6.yaml
+++ /dev/null
@@ -1,2619 +0,0 @@
-Registers:
- version: '4.6'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: TTCBUSYControlsAndMonitors
- record_name: register_map_ttc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: XOFF_BUSYControlsAndMonitors
- record_name: register_map_xoff_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: Generators
- record_name: register_map_generators
- bitfield:
- - range: 0..0
- type: R
-
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
- - name: BUSY_THRESHOLD_ASSERT
- type: W
- desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
- default: 0x6400000
- bitfield:
- - range: 63..0
-
- - name: BUSY_THRESHOLD_NEGATE
- type: W
- desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
- default: 0x6E00000
- bitfield:
- - range: 63..0
-
- - name: BUSY_STATUS
- type: R
- bitfield:
- - range: 1
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- - range: 0
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
- - name: PC_PTR_GAP
- type: W
- desc: This is the minimum value that the pc_pointer in a descriptor has to decrease in order to flip the evencycle_pc bit
- default: 0x1000000
- bitfield:
- - range: 63..0
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: SW_POINTER
- desc: Pointer controlled by the software, indicating read or write status for circular DMA
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: FROMHOST
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: FW_POINTER
- desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
-
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 16
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x5000
- - ref: GBTWrapperControls
- offset: 0x6000
- - ref: GBTWrapperMonitors
- offset: 0x7000
- - ref: TTCBUSYControlsAndMonitors
- offset: 0x8000
- - ref: XOFF_BUSYControlsAndMonitors
- offset: 0x8800
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x9000
- - ref: Generators
- offset: 0xA000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: REG_MAP_VERSION
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: GIT_COMMIT_TIME
- bitfield:
- - range: 39..0
- value: COMMIT_DATETIME
- desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_TAG
- bitfield:
- - range: 63..0
- value: GIT_TAG(63 downto 0)
- desc: String containing the current GIT TAG
-
- - name: GIT_COMMIT_NUMBER
- bitfield:
- - range: 31..0
- value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
- desc: Number of GIT commits after current GIT_TAG
-
- - name: GIT_HASH
- bitfield:
- - range: 31..0
- value: GIT_HASH(159 downto 128)
- desc: Short GIT hash (32 bit)
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC-709
- - 710 (0x2c6): HTG-710
- - 711 (0x2c7): BNL-711
- - 712 (0x2c8): BNL-712
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - ref: INCLUDE_EGROUP
-
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 3..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
- 3: FEI4 mode
- 4: ITK Pixel
- 5: ITK Strip
- 6: FELIG
- 7: FULL mode emulator
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
- - name: BLOCKSIZE
- type: R
- desc: Number of bytes in a block
- bitfield:
- - range: 15..0
-
- - name: PCIE_ENDPOINT
- type: R
- desc: Indicator of the PCIe endpoint on BNL71x cards with two endpoints. 0 or 1
- bitfield:
- - range: 0
- value: std_logic_vector(to_unsigned(PCIE_ENDPOINT, 1))
-
-
-INCLUDE_EGROUP:
- number: 7
- entries:
- - format_name: INCLUDE_EGROUP_{index}
- name: INCLUDE_EGROUP
- #type_name: INCLUDE_EGROUP
- type: R
- bitfield:
- - range: 8
- name: FROMHOST_02
- desc: FromHost EPROC02 is included in this EGROUP
- - range: 7
- name: FROMHOST_04
- desc: FromHost EPROC04 is included in this EGROUP
- - range: 6
- name: FROMHOST_08
- desc: FromHost EPROC8 is included in this EGROUP
- - range: 5
- name: FROMHOST_HDLC
- desc: FromHost HDLC is included in this EGROUP
- - range: 4
- name: TOHOST_02
- desc: ToHost EPROC02 is included in this EGROUP
- - range: 3
- name: TOHOST_04
- desc: ToHost EPROC04 is included in this EGROUP
- - range: 2
- name: TOHOST_08
- desc: ToHost EPROC08 is included in this EGROUP
- - range: 1
- name: TOHOST_16
- desc: ToHost EPROC16 is included in this EGROUP
- - range: 0
- name: TOHOST_HDLC
- desc: ToHost HDLC is included in this EGROUP
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: IC_FROMHOST_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: CR_TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - name: CR_REVERSE_10B
- desc: Reverse 10-bit word of elink data
- type: W
- bitfield:
- - range: 1
- name: FROMHOST
- default: 1
- desc: |
- 1: Serialize 10-bit word in FromHost EPROCS MSB first
- 0: Serialize 10-bit word in FromHost EPROCS LSB first
- - range: 0
- name: TOHOST
- default: 1
- desc: |
- 1: Receive 10-bit word in ToHost EPROCS, MSB first
- 0: Receive 10-bit word in ToHost EPROCS, LSB first
-
- - name: CR_LTDB_TTC_DELAY
- desc: Controls TTC BCR delay in LTDB mode firmware
- type: W
- bitfield:
- - range: 7
- name: EGROUP4_EPATH6
- default: 0
- desc: |
- Egroup 4, Epath 6
- 1: Half a clock delay
- 0: no delay
- - range: 6
- name: EGROUP4_EPATH5
- default: 0
- desc: |
- Egroup 4, Epath 5
- 1: Half a clock delay
- 0: no delay
- - range: 5
- name: EGROUP4_EPATH4
- default: 0
- desc: |
- Egroup 4, Epath 4
- 1: Half a clock delay
- 0: no delay
- - range: 4
- name: EGROUP4_EPATH3
- default: 0
- desc: |
- Egroup 4, Epath 3
- 1: Half a clock delay
- 0: no delay
- - range: 3
- name: EGROUP4_EPATH0
- default: 0
- desc: |
- Egroup 4, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 2
- name: EGROUP3
- default: 0
- desc: |
- Egroup 3, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 1
- name: EGROUP2
- default: 0
- desc: |
- Egroup 2, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 0
- name: EGROUP1
- default: 0
- desc: |
- Egroup 1, Epath 0
- 1: Half a clock delay
- 0: no delay
-# - ref: CR_XOFF_CTRL
-# offset: 0x2800
-# desc: Configure FromHost Xoff
-
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x3000
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA
- - ref: CR_DEFAULT_EPROC_ENCODING
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
- - ref: CR_BLOCK_COUNTERS
-
-
-CR_GBT_CTRL:
- number: 24
- bitfield:
- - range: 50..0
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- entries:
- - ref: EGROUP_TOHOST
- - ref: EGROUP_FROMHOST
-
-EGROUP_TOHOST:
- number: 7
- format_name: GBT{index:02}
- name: GBT
- entries:
- - name: TOHOST
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_TOHOST_EGROUP_CTRL
- bitfield:
- - range: 58..51
- name: INSTANT_TIMEOUT_ENA
- default: 0x0
- desc: instantly initiate a timeout for the given epath
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..31
- name: MAX_CHUNK_LEN
- default: MAX_CHUNK_LEN_array
- desc: set the maximum length of a chunk, 0 disables truncation
- - range: 30..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- default:
- - PATH_ENCODING_array(0)
- - PATH_ENCODING_array(1)
- - PATH_ENCODING_array(2)
- - PATH_ENCODING_array(3)
- - PATH_ENCODING_array(4)
- - PATH_ENCODING_array(5)
- - PATH_ENCODING_array(6)
-
- - range: 14..0
- name: EPROC_ENA
- desc: Enable bits per EPROC
- default:
- - EPROC_ENA_bits_array(0)
- - EPROC_ENA_bits_array(1)
- - EPROC_ENA_bits_array(2)
- - EPROC_ENA_bits_array(3)
- - EPROC_ENA_bits_array(4)
- - EPROC_ENA_bits_array(5)
- - EPROC_ENA_bits_array(6)
-
-EGROUP_FROMHOST:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FROMHOST
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_FROMHOST_EGROUP_CTRL
- bitfield:
- - range: 54..47
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 46..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- greater than 3: TTC mode, see CentralRouter doc
- default:
- - FROMHOST_PATH_ENCODING_array(0)
- - FROMHOST_PATH_ENCODING_array(1)
- - FROMHOST_PATH_ENCODING_array(2)
- - FROMHOST_PATH_ENCODING_array(3)
- - FROMHOST_PATH_ENCODING_array(4)
- - FROMHOST_PATH_ENCODING_array(5)
- - FROMHOST_PATH_ENCODING_array(6)
- - range: 14..0
- desc: Enable bits per EPROC
- name: EPROC_ENA
-
-#CR_XOFF_CTRL:
-# number: 24
-# type: W
-# bitfield:
-# - range: 39..0
-# entries:
-# - name: FROMHOST_XOFF_ENABLE
-# format_name: FROMHOST_XOFF_ENABLE_{index:02}
-# desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
-# range: 39..0
-# default: 0
-# - name: FROMHOST_SOFT_XOFF
-# format_name: FROMHOST_SOFT_XOFF_{index:02}
-# desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
-# range: 39..0
-# default: 0
-
-
-IC_FIFOS:
- number: 24
- format_name: IC_FROMHOST_TOHOST_FIFOS
- entries:
- - name: FROMHOST
- format_name: IC_FROMHOST_FIFO_{index:02}
- type_name: IC_FROMHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_FROMHOST_FIFO_{index:02}.FULL
- name: WE
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TOHOST
- format_name: IC_TOHOST_FIFO_{index:02}
- type_name: IC_TOHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_TOHOST_FIFO_{index:02}.EMPTY
- name: RE
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 7
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 6
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 5
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 4
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 9
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 8
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 7
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 6
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
-
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- entries:
- - name: TOHOST
- type_name: TOHOST
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 58
- name: CROUTFIFO_PROG_FULL
- - range: 57
- name: WMFIFO_FULL
- - range: 56
- name: MINI_EGROUP_ALMOST_FULL
- - range: 55..48
- name: EPATH6_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP6
- - range: 47..40
- name: EPATH5_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP5
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
- - name: FROMHOST
- type_name: FROMHOST
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 40
- name: MINI_EGROUP_ALMOST_FULL
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
-
-CR_DEFAULT_EPROC_ENA:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 14..0
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
-
-CR_DEFAULT_EPROC_ENCODING:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 15..0
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
-
-CR_BLOCK_COUNTERS:
- desc: Counters to count blocks per GBT channel
- endpoints: 0,1
- number: 24
- entries:
- - name: BLOCK_COUNT
- type_name: CR_BLOCK_COUNT
- format_name: CR_{name}_GBT{index:02}
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- type: W
- bitfield:
- - range: any
- type: T
- name: RESET
- desc: Any write clears the counter value
- value: 1
- - range: 31..0
- type: R
- name: VAL
- desc: Counts the number of blocks that were transferred ToHost in the specified GBT
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 63..48
- name: RDDATA
- type: R
- desc: read data bus
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 0
- desc: write enable for the full mode emulator ram block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 35..0
- desc: read emu ram data
-
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_CHANNEL_DISABLE
- offset: 0x0400
- bitfield:
- - range: 47..0
- desc: Disable selected GBT or FULL mode channel
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE_SELECT
- offset: 0x0480
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RXSLIDE_MANUAL
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TXUSRRDY
- desc: TxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_RXUSRRDY
- desc: RxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_SOFT_RESET
- desc: SOFT_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTTX_RESET
- desc: GTTX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTRX_RESET
- desc: GTRX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 59..48
- name: QPLL_RESET
- desc: QPLL_RESET [11:0]
- - range: 47..0
- name: CPLL_RESET
- desc: CPLL_RESET [47:0]
-
- - name: GBT_SOFT_TX_RESET
- offset: 0x0500
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_SOFT_RX_RESET
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_ODD_EVEN
- desc: OddEven [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TOPBOT
- desc: TopBot [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_TC_DLY_VALUE3
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [143:96]
-
- - name: GBT_TX_TC_DLY_VALUE4
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [191:144]
-
- - name: GBT_DATA_TXFORMAT1
- desc: DATA_TXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_TXFORMAT2
- desc: DATA_TXFORMAT [95:48]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT1
- desc: DATA_RXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT2
- desc: DATA_RXFORMAT [95:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_RESET
- desc: TX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_RESET
- desc: RX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_METHOD
- desc: TX time domain crossing method [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUTMUX_SEL
- desc: Descrambler output MUX selection [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TC_EDGE
- desc: Sampling edge selection for TX domain crossing [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for transmitter of GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_RXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for the receiver of the GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
- - name: GBT_TOHOST_FANOUT
- offset: 0x0700
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_TOFRONTEND_FANOUT
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- desc: TX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXRESET_DONE
- desc: RX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXFSMRESET_DONE
- desc: TX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXFSMRESET_DONE
- desc: RX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_LOCK
- bitfield:
- - range: 59..48
- name: QPLL_LOCK
- desc: QPLL LOCK [11:0]
- - range: 47..0
- name: CPLL_LOCK
- desc: CPLL LOCK [47:0]
-
- - name: GBT_RXCDR_LOCK
- desc: RX CDR LOCK [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CLK_SAMPLED
- desc: clk sampled [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_HEADER
- desc: RX IS HEADER [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_DATA
- desc: RX IS DATA [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_HEADER_FOUND
- desc: RX HEADER FOUND [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUT_MUX_STATUS
- desc: GBT output mux status [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ERROR
- desc: Error flags [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GBT_TOPBOT_C
- desc: TopBot_c [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-TTCBUSYControlsAndMonitors:
- group: TTCBUSY
- desc: TTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: TTC_BUSY_ACCEPTED
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Enable TTC data generator (10 bit counter)
-
- - ref: TTC_DELAY
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the BUSY Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range: 14
- name: BUSY_OUTPUT_STATUS
- type: R
- desc: Actual status of the BUSY LEMO output signal
- - range: 13
- name: ECR_BCR_SWAP
- default: 0
- desc: ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
- - range: 12
- name: BUSY_OUTPUT_INHIBIT
- default: 0
- desc: forces the Busy LEMO output to BUSY-OFF
- - range: 11
- name: TOHOST_RST
- desc: reset toHost in ttc decoder
- default: 0
- - range: 10
- name: TT_BCH_EN
- desc: trigger type enable / disable for TTC-ToHost
- default: 1
- - range: 9..2
- name: XL1ID_SW
- desc: set XL1ID value, the value to be set by XL1ID_RST signal
- default: 0x00
- - range: 1
- name: XL1ID_RST
- desc: giving a trigger signal to reset XL1ID value
- default: 0
- - range: 0
- name: MASTER_BUSY
- desc: L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range: 15..5
- name: TH_FF_COUNT
- desc: ToHostData Fifo counts
- - range: 4
- name: TH_FF_FULL
- desc: ToHostData Fifo status 1:full 0:not full
- - range: 3
- name: TH_FF_EMPTY
- desc: ToHostData Fifo status 1:empty 0:not empty
- - range: 2..0
- name: TTC_BIT_ERR
- desc: double bit, single bit and comm error in TTC data
-
-TTC_BUSY_ACCEPTED:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- bitfield:
- - range: 56..0
- entries:
- - name: BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
-
-
-TTC_DELAY:
- number: 48
- type: W
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Controls the TTC Fanout delay values
- bitfield:
- - range: 3..0
- default: 0
-
-XOFF_BUSYControlsAndMonitors:
- group: XOFF
- desc: XOFF Controls and Monitors, see table 2 of Busy specs manual
- endpoints: 0, 1
- entries:
- - name: XOFF_FM_CH_FIFO_THRESH_LOW
- desc: Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xB
- - range: 43..40
- name: CH10
- default: 0xB
- - range: 39..36
- name: CH09
- default: 0xB
- - range: 35..32
- name: CH08
- default: 0xB
- - range: 31..28
- name: CH07
- default: 0xB
- - range: 27..24
- name: CH06
- default: 0xB
- - range: 23..20
- name: CH05
- default: 0xB
- - range: 19..16
- name: CH04
- default: 0xB
- - range: 15..12
- name: CH03
- default: 0xB
- - range: 11..8
- name: CH02
- default: 0xB
- - range: 7..4
- name: CH01
- default: 0xB
- - range: 3..0
- name: CH00
- default: 0xB
-
- - name: XOFF_FM_CH_FIFO_THRESH_HIGH
- desc: Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xB
- - range: 43..40
- name: CH10
- default: 0xB
- - range: 39..36
- name: CH09
- default: 0xB
- - range: 35..32
- name: CH08
- default: 0xB
- - range: 31..28
- name: CH07
- default: 0xB
- - range: 27..24
- name: CH06
- default: 0xB
- - range: 23..20
- name: CH05
- default: 0xB
- - range: 19..16
- name: CH04
- default: 0xB
- - range: 15..12
- name: CH03
- default: 0xB
- - range: 11..8
- name: CH02
- default: 0xB
- - range: 7..4
- name: CH01
- default: 0xB
- - range: 3..0
- name: CH00
- default: 0xB
-
- - name: XOFF_FM_LOW_THRESH_CROSSED
- desc: FIFO filled beyond the low threshold, 1 bit per channel
- type: R
- bitfield:
- - range: 11..0
- - name: XOFF_FM_HIGH_THRESH
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- desc: Writing this register will clear all CROSS_LATCHED bits
- type: T
- value: 1
- - range: 23..12
- type: R
- name: CROSS_LATCHED
- desc: FIFO filled beyond the high threshold, 1 latch bit per channel
- - range: 11..0
- type: R
- name: CROSSED
- desc: FIFO filled beyond the high threshold, 1 bit per channel
-
- - name: XOFF_FM_SOFT_XOFF
- type: W
- desc: Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
- bitfield:
- - range: 23..0
-
- - name: XOFF_ENABLE
- type: W
- desc: Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
- bitfield:
- - range: 23..0
-
- - name: DMA_BUSY_STATUS
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR_LATCH
- desc: Any write to this register clears TOHOST_BUSY_LATCHED
- - range: 4
- type: W
- name: ENABLE
- desc: Enable the DMA buffer on the server as a source of busy
- default: 0
- - range: 3
- type: R
- name: TOHOST_BUSY_LATCHED
- desc: A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => tohost_busy_latched_40_s)
- - range: 2
- type: R
- name: FROMHOST_BUSY_LATCHED
- desc: A fromhost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => fromhost_busy_latched_40_s)
- - range: 1
- type: R
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => fromhost_busy_40_s)
- - range: 0
- type: R
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => tohost_busy_40_s)
-
- - name: FM_BUSY_CHANNEL_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- type: T
- value: 1
- desc: Any write to this register will clear the BUSY_LATCHED bits
- - range: 23..12
- type: R
- name: BUSY_LATCHED
- desc: one Indicates that the given FULL mode channel has received BUSY-ON
- - range: 11..0
- type: R
- name: BUSY
- desc: one Indicates that the given FULL mode channel is currently in BUSY state
-
- - name: BUSY_MAIN_OUTPUT_FIFO_THRESH
- type: W
- bitfield:
- - range: 24
- name: BUSY_ENABLE
- desc: Enable busy generation if thresholds are crossed
- default: 0
- - range: 23..12
- name: LOW
- desc: Low, Negate threshold of busy generation from main output fifo
- default: 0x3FF
- - range: 11..0
- name: HIGH
- desc: High, Assert threshold of busy generation from main output fifo
- default: 0x4FF
-
- - name: BUSY_MAIN_OUTPUT_FIFO_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCHED
- value: 1
- desc: Any write to this register will clear the
- type: T
- - range: 2
- type: R
- name: HIGH_THRESH_CROSSED_LATCHED
- desc: Main output fifo has been full beyond HIGH THRESHOLD, write to clear
- - range: 1
- type: R
- name: HIGH_THRESH_CROSSED
- desc: Main output fifo is full beyond HIGH THRESHOLD
- - range: 0
- type: R
- name: LOW_THRESH_CROSSED
- desc: Main output fifo is full beyond LOW THRESHOLD
- - ref: ELINK_BUSY_ENABLE
-
-
-ELINK_BUSY_ENABLE:
- desc: Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- number: 24
- endpoints: 0
- type: W
- bitfield:
- - range: 56..0
- entries:
- - name: ELINK_BUSY_ENABLE
- format_name: ELINK_BUSY_ENABLE{index:02}
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
-
- - name: HK_MON_FMC
- type: W
- bitfield:
- - range: 1
- name: SI5345_LOL
- desc: Si5345 Loss Of Lock pin
- - range: 0
- name: SI5345_INTR
- desc: Si5345 Interrupt flagging chip change of status
-
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_SEL
- default: 0x1
- desc: |
- 1: LCLK
- 0: TTC
- - range: 2..1
- type: R
- name: MAIN_INPUT
- desc: |
- Main MMCM Oscillator Input
- 2: LCLK fixed
- 1: TTC fixed
- 0: selectable
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL-711 locked
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
-
- - name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
-
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_4
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#4
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
-
- - name: TACH_CNT
- type: R
- desc: Readout of the Fan tachometer speed of the BNL712 board
- bitfield:
- - range: 19..0
-
-Generators:
- group: GEN
- desc: Specific registers for Hardware based Generators
- endpoints: 0
- generate: EMU_GENERATE_REGS = true
- entries:
-
- - ref: FELIG_DATA_GEN_CONFIG_ARR
- offset: 0x20
- - ref: FELIG_ELINK_CONFIG_ARR
- - ref: FELIG_ELINK_ENABLE_ARR
-
- - name: FELIG_GLOBAL_CONTROL
- type: W
- bitfield:
- - range: 63..36
- name: FAKE_L1A_RATE
- default: 0
- desc: Sets the internal fake L1 trigger rate. [25ns/LSB]
- - range: 35..14
- name: PICXO_OFFSET_PPM
- default: 0
- desc: When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
- - range: 12..12
- name: TRACK_DATA
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 11..11
- name: RXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 10..10
- name: TXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 9..9
- name: AUTO_RESET
- default: 0
- desc: FELIG GT core control. If set the GT core automatically resets on data error.
- - range: 8..8
- name: PICXO_RESET
- default: 0
- desc: FELIG GT core control. Manual PICXO reset.
- - range: 7..7
- name: GTTX_RESET
- default: 0
- desc: FELIG GT core control. Manual GT TX reset
- - range: 6..6
- name: CPLL_RESET
- default: 0
- desc: FELIG GT core control. Manual CPLL reset.
- - range: 5..0
- name: X3_X4_OUTPUT_SELECT
- default: 0
- desc: X3/X4 SMA output source select.
-
- - ref: FELIG_LANE_CONFIG_ARR
- - ref: FELIG_MON_TTC_0_ARR
- - ref: FELIG_MON_TTC_1_ARR
- - ref: FELIG_MON_COUNTERS_ARR
- - ref: FELIG_MON_FREQ_ARR
-
- - name: FELIG_MON_FREQ_GLOBAL
- type: W
- bitfield:
- - range: 63..32
- name: XTAL_100MHZ
- default: 0
- desc: FELIG local oscillator frequency[Hz].
- - range: 31..0
- name: CLK_41_667MHZ
- desc: FELIG PCIE MGTREFCLK frequency[Hz].
-
- - ref: FELIG_MON_L1A_ID_ARR
- - ref: FELIG_MON_PICXO_ARR
-
- - name: FELIG_RESET
- type: W
- bitfield:
- - range: 63..48
- name: LB_FIFO
- default: 0
- desc: One bit per lane. When set to 1, resets all loopback FIFOs.
- - range: 47..24
- name: FRAMEGEN
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG link checking logic.
- - range: 23..0
- name: LANE
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG lane logic.
-
- - name: FELIG_RX_SLIDE_RESET
- type: W
- bitfield:
- - range: 23..0
- default: 0
- desc: One bit per lane. When set to 1, resets the gbt rx slide counter.
-
- - name: FMEMU_EVENT_INFO
- type: W
- offset: 0x1800
- bitfield:
- - range: 63..32
- name: L1ID
- default: 0
- desc: 32b field to show L1ID
- - range: 31..0
- name: BCID
- default: 0
- desc: 32b field to show BCID
-
- - name: FMEMU_COUNTERS
- type: W
- bitfield:
- - range: 63..48
- name: WORD_CNT
- default: 32
- desc: Number of 32b words in one chunk
- - range: 47..32
- name: IDLE_CNT
- default: 3
- desc: Minimum number of idles between chunks
- - range: 31..16
- name: L1A_CNT
- default: 256
- desc: Number of chunks to send if not in TTC mode
- - range: 15..8
- name: BUSY_TH_HIGH
- default: 20
- desc: Assert BUSY-ON above this threshold
- - range: 7..0
- name: BUSY_TH_LOW
- default: 15
- desc: De-assert BUSY-ON below this threshold
-
- - name: FMEMU_CONTROL
- type: W
- bitfield:
- - range: 63..56
- type: W
- name: L1A_BITNR
- default: 32
- desc: Bitfield for L1A in TTC frame
- - range: 55..48
- type: W
- name: XONXOFF_BITNR
- default: 32
- desc: Bitfield for Xon/Xoff in TTC frame
- - range: 47..47
- type: W
- name: EMU_START
- default: 0
- desc: Start emulator functionality
- - range: 46..46
- type: W
- name: TTC_MODE
- default: 0
- desc: Control the emulator by TTC input or by RegMap (1/0)
- - range: 45..45
- type: W
- name: XONXOFF
- default: 0
- desc: Debug Xon/Xoff functionality (1/0)
- - range: 44..44
- type: W
- name: INLC_CRC32
- default: 0
- desc: |
- 0: No checksum
- 1: Append the data with a CRC32
- - range: 43..43
- type: W
- name: BCR
- default: 0
- desc: Reset BCID to 0
- - range: 42..42
- type: W
- name: ECR
- default: 0
- desc: Reset L1ID to 0
- - range: 41..41
- type: W
- name: DATA_SRC_SEL
- default: 0
- desc: |
- Data source select
- 0: Data input comes from EMURAM
- 1: Data input comes from PCIe
- - range: 40..32
- type: R
- name: INT_STATUS_EMU
- default: 0
- desc: Read internal status emulator
- - range: 31..16
- type: W
- name: FFU_FM_EMU_T
- default: 0
- desc: For Future Use (trigger registers)
- - range: 15..0
- type: W
- name: FFU_FM_EMU_W
- default: 0
- desc: For Future Use (write registers)
-
- - name: FMEMU_RANDOM_RAM_ADDR
- type: W
- desc: Controls the address of the ramblock for the random number generator
- bitfield:
- - range: 9..0
- - name: FMEMU_RANDOM_RAM
- type: W
- bitfield:
- - range: any
- type: T
- name: WE
- value: 1
- desc: Any write to this register (DATA) triggers a write to the ramblock
- - range: 39..16
- name: CHANNEL_SELECT
- value: 0xFFFFFF
- desc: Enable write enable only for the selected channel
- - range: 15..0
- name: DATA
- type: W
- desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
- - name: FMEMU_RANDOM_CONTROL
- type: W
- desc: Controls the random chunk length generator
- bitfield:
- - name: SELECT_RANDOM
- range: 20
- desc: 1 enables the random chunk length, 0 uses a constant chunk length
- default: 0
- - name: SEED
- range: 19..10
- desc: Seed for the random number generator, should not be 0
- default: 0x200
- - name: POLYNOMIAL
- range: 9..0
- desc: POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
- default: 0x240
-
-
-#Registers that are replicated 24 times under Generators:
-FELIG_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_DATA_GEN_CONFIG
- format_name: FELIG_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_DATA_GEN_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: USERDATA
- range: 63..48
- default: 0
- desc: Sets static payload word. When PATTERN_SEL=1.
- - name: CHUNK_LENGTH
- range: 47..32
- default: 0
- desc: FELIG data generator chunk-length in bytes.
- - name: RESET
- range: 19..15
- default: 0
- desc: FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- - name: SW_BUSY
- range: 14..10
- default: 0
- desc: FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- - name: DATA_FORMAT
- range: 9..5
- default: 0
- desc: FELIG data generator format. 0:8b10b, 1:direct.
- - name: PATTERN_SEL
- range: 4..0
- default: 0
- desc: FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
-
-FELIG_ELINK_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_CONFIG
- format_name: FELIG_ELINK_CONFIG_{index:02}
- type_name: FELIG_ELINK_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: ENDIAN_MOD
- range: 39..35
- default: 0
- desc: FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- - name: INPUT_WIDTH
- range: 34..30
- default: 0
- desc: FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- - name: OUTPUT_WIDTH
- range: 9..0
- default: 0
- desc: FELIG elink data output width.
-
-FELIG_ELINK_ENABLE_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_ENABLE
- format_name: FELIG_ELINK_ENABLE_{index:02}
- type_name: FELIG_ELINK_ENABLE
- desc: FELIG specific configuration registers
- bitfield:
- - range: 39..0
- default: 0
- desc: FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
-
-FELIG_LANE_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_LANE_CONFIG
- format_name: FELIG_LANE_CONFIG_{index:02}
- type_name: FELIG_LANE_CONFIG
- desc: FELIG specific configuration registers
- bitfield:
- - name: B_CH_BIT_SEL
- range: 63..42
- default: 0
- desc: When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- - name: A_CH_BIT_SEL
- range: 41..35
- default: 0
- desc: Selects the bit from the received FELIX data from which to extract the L1A.
- - name: LB_FIFO_DELAY
- range: 34..30
- default: 0
- desc: When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- - name: ELINK_SYNC
- range: 7..7
- default: 0
- desc: When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- - name: PICXO_OFFEST_EN
- range: 6..6
- default: 0
- desc: FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- - name: PI_HOLD
- range: 5..5
- default: 0
- desc: FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- - name: GBT_LB_ENABLE
- range: 4..4
- default: 0
- desc: FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- - name: GBH_LB_ENABLE
- range: 3..3
- default: 0
- desc: FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- - name: L1A_SOURCE
- range: 2..2
- default: 0
- desc: FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- - name: GBT_EMU_SOURCE
- range: 1..1
- default: 0
- desc: FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- - name: FG_SOURCE
- range: 0..0
- default: 0
- desc: FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
-
-FELIG_MON_TTC_0_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_0
- format_name: FELIG_MON_TTC_0_{index:02}
- type_name: FELIG_MON_TTC_0
- desc: FELIG specific configuration registers
- bitfield:
- - name: L1ID
- range: 63..40
- default: 0
- desc: Live TTC data monitor.
- - name: XL1ID
- range: 39..32
- default: 0
- desc: Live TTC data monitor.
- - name: BCID
- range: 31..20
- default: 0
- desc: Live TTC data monitor.
- - name: RESERVED0
- range: 19..16
- default: 0
- desc: Live TTC data monitor.
- - name: LEN
- range: 15..8
- default: 0
- desc: Live TTC data monitor.
- - name: FMT
- range: 7..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_TTC_1_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_1
- format_name: FELIG_MON_TTC_1_{index:02}
- type_name: FELIG_MON_TTC_1
- desc: FELIG specific configuration registers
- bitfield:
- - name: RESERVED1
- range: 63..48
- default: 0
- desc: Live TTC data monitor.
- - name: TRIGGER_TYPE
- range: 47..32
- default: 0
- desc: Live TTC data monitor.
- - name: ORBIT
- range: 31..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_COUNTERS_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_COUNTERS
- format_name: FELIG_MON_COUNTERS_{index:02}
- type_name: FELIG_MON_COUNTERS
- desc: FELIG specific configuration registers
- bitfield:
- - name: SLIDE_COUNT
- range: 63..32
- default: 0
- desc: Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- - name: FC_ERROR_COUNT
- range: 31..0
- default:
- desc: When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
-
-FELIG_MON_FREQ_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_FREQ
- format_name: FELIG_MON_FREQ_{index:02}
- type_name: FELIG_MON_FREQ
- desc: FELIG specific configuration registers
- bitfield:
- - name: TX
- range: 63..32
- default: 0
- desc: FELIG regenerated TX clock frequency[Hz].
- - name: RX
- range: 31..0
- default: 0
- desc: FELIG recovered RX clock frequency[Hz].
-
-FELIG_MON_L1A_ID_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_L1A_ID
- format_name: FELIG_MON_L1A_ID_{index:02}
- type_name: FELIG_MON_L1A_ID
- desc: FELIG specific configuration registers
- bitfield:
- - range: 31..0
- default: 0
- desc: FELIG's last L1 ID.
-
-FELIG_MON_PICXO_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_PICXO
- format_name: FELIG_MON_PICXO_{index:02}
- type_name: FELIG_MON_PICXO
- desc: FELIG specific configuration registers
- bitfield:
- - name: VLOT
- range: 53..32
- default: 0
- desc: Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- - name: ERROR
- range: 20..0
- default: 0
- desc: Value indicates RX to TX frequency tracking error.
-
diff --git a/sources/templates/yaml/registers-4.7.1.yaml b/sources/templates/yaml/registers-4.7.1.yaml
deleted file mode 100644
index ca9e644c1f28c8b7bd6951289532df7bee8560b4..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-4.7.1.yaml
+++ /dev/null
@@ -1,3153 +0,0 @@
-Registers:
- version: '4.7.1'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: TTCBUSYControlsAndMonitors
- record_name: register_map_ttc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: XOFF_BUSYControlsAndMonitors
- record_name: register_map_xoff_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: Generators
- record_name: register_map_generators
- bitfield:
- - range: 0..0
- type: R
-
-#Bar0 contains the registers dedicated to Wupper. Please only edit registers in Bar2
-#Registers in this group will not be generated with WupperCodeGen
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
- - name: BUSY_THRESHOLD_ASSERT
- type: W
- desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
- default: 0x6400000
- bitfield:
- - range: 63..0
-
- - name: BUSY_THRESHOLD_NEGATE
- type: W
- desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
- default: 0x6E00000
- bitfield:
- - range: 63..0
-
- - name: BUSY_STATUS
- type: R
- bitfield:
- - range: 1
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- - range: 0
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
- - name: PC_PTR_GAP
- type: W
- desc: This is the minimum value that the pc_pointer in a descriptor has to decrease in order to flip the evencycle_pc bit
- default: 0x1000000
- bitfield:
- - range: 63..0
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: SW_POINTER
- desc: Pointer controlled by the software, indicating read or write status for circular DMA
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: FROMHOST
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: FW_POINTER
- desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
-
-
-#Bar1 contains the registers dedicated to the Wupper interrupg controller.
-#Please only edit registers in Bar2.
-#Registers in this group will not be generated with WupperCodeGen
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 16
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-#Bar 2 contains application specific registers, used in the example application.
-#Registers in this group (and it's referenced subroups) will be generated with
-#WupperCodeGen for wupper Firmware, Software and Documentation
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x5000
- - ref: GBTWrapperControls
- offset: 0x6000
- - ref: GBTWrapperMonitors
- offset: 0x7000
- - ref: TTCBUSYControlsAndMonitors
- offset: 0x8000
- - ref: XOFF_BUSYControlsAndMonitors
- offset: 0x8800
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x9000
- - ref: Generators
- offset: 0xA000
- - ref: ITK_STRIPS_CTRL # ITk strips global controls
- offset: 0xD000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned({{ tree.version|version }},16))
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: GIT_COMMIT_TIME
- bitfield:
- - range: 39..0
- value: COMMIT_DATETIME
- desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_TAG
- bitfield:
- - range: 63..0
- value: GIT_TAG(63 downto 0)
- desc: String containing the current GIT TAG
-
- - name: GIT_COMMIT_NUMBER
- bitfield:
- - range: 31..0
- value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
- desc: Number of GIT commits after current GIT_TAG
-
- - name: GIT_HASH
- bitfield:
- - range: 31..0
- value: GIT_HASH(159 downto 128)
- desc: Short GIT hash (32 bit)
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC-709
- - 710 (0x2c6): HTG-710
- - 711 (0x2c7): BNL-711
- - 712 (0x2c8): BNL-712
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - ref: INCLUDE_EGROUP
-
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 3..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
- 3: FEI4 mode
- 4: ITK Pixel
- 5: ITK Strip
- 6: FELIG
- 7: FULL mode emulator
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
- - name: BLOCKSIZE
- type: R
- desc: Number of bytes in a block
- bitfield:
- - range: 15..0
-
- - name: PCIE_ENDPOINT
- type: R
- desc: Indicator of the PCIe endpoint on BNL71x cards with two endpoints. 0 or 1
- bitfield:
- - range: 0
- value: std_logic_vector(to_unsigned(PCIE_ENDPOINT, 1))
-
-
-INCLUDE_EGROUP:
- number: 7
- entries:
- - format_name: INCLUDE_EGROUP_{index}
- name: INCLUDE_EGROUP
- #type_name: INCLUDE_EGROUP
- type: R
- bitfield:
- - range: 8
- name: FROMHOST_02
- desc: FromHost EPROC02 is included in this EGROUP
- - range: 7
- name: FROMHOST_04
- desc: FromHost EPROC04 is included in this EGROUP
- - range: 6
- name: FROMHOST_08
- desc: FromHost EPROC8 is included in this EGROUP
- - range: 5
- name: FROMHOST_HDLC
- desc: FromHost HDLC is included in this EGROUP
- - range: 4
- name: TOHOST_02
- desc: ToHost EPROC02 is included in this EGROUP
- - range: 3
- name: TOHOST_04
- desc: ToHost EPROC04 is included in this EGROUP
- - range: 2
- name: TOHOST_08
- desc: ToHost EPROC08 is included in this EGROUP
- - range: 1
- name: TOHOST_16
- desc: ToHost EPROC16 is included in this EGROUP
- - range: 0
- name: TOHOST_HDLC
- desc: ToHost HDLC is included in this EGROUP
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: IC_FROMHOST_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: CR_TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - name: CR_REVERSE_10B
- desc: Reverse 10-bit word of elink data
- type: W
- bitfield:
- - range: 1
- name: FROMHOST
- default: 1
- desc: |
- 1: Serialize 10-bit word in FromHost EPROCS MSB first
- 0: Serialize 10-bit word in FromHost EPROCS LSB first
- - range: 0
- name: TOHOST
- default: 1
- desc: |
- 1: Receive 10-bit word in ToHost EPROCS, MSB first
- 0: Receive 10-bit word in ToHost EPROCS, LSB first
-
- - name: CR_LTDB_TTC_DELAY
- desc: Controls TTC BCR delay in LTDB mode firmware
- type: W
- bitfield:
- - range: 7
- name: EGROUP4_EPATH6
- default: 0
- desc: |
- Egroup 4, Epath 6
- 1: Half a clock delay
- 0: no delay
- - range: 6
- name: EGROUP4_EPATH5
- default: 0
- desc: |
- Egroup 4, Epath 5
- 1: Half a clock delay
- 0: no delay
- - range: 5
- name: EGROUP4_EPATH4
- default: 0
- desc: |
- Egroup 4, Epath 4
- 1: Half a clock delay
- 0: no delay
- - range: 4
- name: EGROUP4_EPATH3
- default: 0
- desc: |
- Egroup 4, Epath 3
- 1: Half a clock delay
- 0: no delay
- - range: 3
- name: EGROUP4_EPATH0
- default: 0
- desc: |
- Egroup 4, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 2
- name: EGROUP3
- default: 0
- desc: |
- Egroup 3, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 1
- name: EGROUP2
- default: 0
- desc: |
- Egroup 2, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 0
- name: EGROUP1
- default: 0
- desc: |
- Egroup 1, Epath 0
- 1: Half a clock delay
- 0: no delay
-# - ref: CR_XOFF_CTRL
-# offset: 0x2800
-# desc: Configure FromHost Xoff
-
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x3000
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA
- - ref: CR_DEFAULT_EPROC_ENCODING
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
- - ref: CR_BLOCK_COUNTERS
-
-
-CR_GBT_CTRL:
- number: 24
- bitfield:
- - range: 50..0
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- entries:
- - ref: EGROUP_TOHOST
- - ref: EGROUP_FROMHOST
-
-EGROUP_TOHOST:
- number: 7
- format_name: GBT{index:02}
- name: GBT
- entries:
- - name: TOHOST
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_TOHOST_EGROUP_CTRL
- bitfield:
- - range: 58..51
- name: INSTANT_TIMEOUT_ENA
- default: 0x0
- desc: instantly initiate a timeout for the given epath
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..31
- name: MAX_CHUNK_LEN
- default: MAX_CHUNK_LEN_array
- desc: set the maximum length of a chunk, 0 disables truncation
- - range: 30..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- default:
- - PATH_ENCODING_array(0)
- - PATH_ENCODING_array(1)
- - PATH_ENCODING_array(2)
- - PATH_ENCODING_array(3)
- - PATH_ENCODING_array(4)
- - PATH_ENCODING_array(5)
- - PATH_ENCODING_array(6)
-
- - range: 14..0
- name: EPROC_ENA
- desc: Enable bits per EPROC
- default:
- - EPROC_ENA_bits_array(0)
- - EPROC_ENA_bits_array(1)
- - EPROC_ENA_bits_array(2)
- - EPROC_ENA_bits_array(3)
- - EPROC_ENA_bits_array(4)
- - EPROC_ENA_bits_array(5)
- - EPROC_ENA_bits_array(6)
-
-
-EGROUP_FROMHOST:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FROMHOST
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_FROMHOST_EGROUP_CTRL
- bitfield:
- - range: 54..47
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 46..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- greater than 3: TTC mode, see CentralRouter doc
- default:
- - FROMHOST_PATH_ENCODING_array(0)
- - FROMHOST_PATH_ENCODING_array(1)
- - FROMHOST_PATH_ENCODING_array(2)
- - FROMHOST_PATH_ENCODING_array(3)
- - FROMHOST_PATH_ENCODING_array(4)
- - FROMHOST_PATH_ENCODING_array(5)
- - FROMHOST_PATH_ENCODING_array(6)
- - range: 14..0
- desc: Enable bits per EPROC
- name: EPROC_ENA
-
-# ----------------------- ITk strips link configuration start -----------------------
-
-# Global trickle trigger (all LCB links on this device)
-
-# Maximum LCB links count:
-
-# x24 lpGBT links
-# x4 LCB links per stave
-# x4 R3L1 links per stave
-# => 96 LCB links
-# => 96 R3L1 links
-
-
-
-ITK_STRIPS_CTRL:
- entries:
- - name: GLOBAL_STRIPS_CONFIG
- desc: Synchronous trigger for all LCB links on device
- type: W
- bitfield:
- - range: 15..11
- type: W
- name: TEST_MODULE_MASK
- desc: (for tests only) contains R3 mask for the simulated trigger data
- default: 0x0
- - range: 10..4
- type: W
- name: TEST_R3L1_TAG
- desc: (for tests only) contains R3 or L1 tag for the simulated trigger data
- default: 0x0
- - range: 1
- type: W
- name: TTC_GENERATE_GATING_ENABLE
- desc: Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR.
- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- (See also BC_START, and BC_STOP fields)
- default: 0x0
- - name: GLOBAL_TRICKLE_TRIGGER
- type: T
- bitfield:
- - range: any
- value: 1
- desc: writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
- - ref: ITK_STRIPS_GBT
- - name: STRIPS_R3_TRIGGER
- type: T
- bitfield:
- - range: any
- value: 1
- desc: (for tests only) simulate R3 trigger (issues 4-5 sequential triggers)
- - name: STRIPS_L1_TRIGGER
- type: T
- bitfield:
- - range: any
- desc: (for tests only) simulate L1 trigger (issues 4-5 sequential triggers)
- value: 1
- - name: STRIPS_R3L1_TRIGGER
- type: T
- bitfield:
- - range: any
- desc: (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)
- value: 1
-
-ITK_STRIPS_GBT:
- number: 2 # Change back to 24 once dma_controller.vhd is fixed
- format_name: "STRIPS"
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- entries:
- - ref: ITK_STRIPS_LCB_LINKS
- - ref: ITK_STRIPS_R3L1_LINKS
-
-# Describes an array of LCB control links in a single egroup
-ITK_STRIPS_LCB_LINKS:
- number: 4
- format_name: "{parent}_GBT{index:02}_LCB"
- type_name: ITK_LCB_LINKS
- entries:
- - ref: ITK_STRIPS_LCB_LINK
-
-# Describes an array of R3L1 control links
-ITK_STRIPS_R3L1_LINKS:
- number: 4
- format_name: "{parent}_GBT{index:02}_R3L1"
- type_name: ITK_R3L1_LINKS
- entries:
- - ref: ITK_STRIPS_R3L1_LINK
-
-ITK_STRIPS_LCB_LINK:
- format_name: "{parent}_{index:1}"
- type_name: ITK_LCB_LINK
- entries:
- - name: CTRL
- format_name: CR_{parent}_{name}
- type_name: LCB_CTRL
- desc: Determines LCB link configuration
- type: W
- bitfield:
- - range: 49..38
- type: W
- name: L0A_BCR_DELAY
- default: 0x0
- desc: TTC BCR signal will be delayed by this many BCs
- - range: 37..34
- type: W
- name: L0A_FRAME_DELAY
- default: 0x0
- desc: |
- By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
- and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
- - range: 33..32
- type: W
- name: FRAME_PHASE
- default: 0x0
- desc: phase of LCB frame with respect to TTC BCR signal
- - range: 31..20
- type: W
- name: TRICKLE_BC_START
- default: 0x0
- desc: Determines the start of the allowed BC interval for low-priority LCB frames
- - range: 19..8
- type: W
- name: TRICKLE_BC_STOP
- default: 0x0
- desc: Determines the end of the allowed BC interval for low-priority LCB frames
- - range: 5..4
- type: W
- name: LCB_DESTINATION_MUX
- default: 0x0
- desc: |
- Determines where the elink data is sent to:
- 00: command decoder (use same command encoding format as trickle configuration)
- 01: trickle memory (see phase2 documentation for command encoding format)
- 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
- 11: (invalid, don't use)
- - range: 3
- type: W
- name: TRICKLE_TRIG_RUN
- default: 0x0
- desc: |
- if enabled, trickle configuration is sent out continuously to the front-end
- (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
- continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
- - range: 2
- type: W
- name: TTC_L0A_ENABLE
- default: 0x0
- desc: enable generating L0A frames in response to TTC system signals
- - range: 0
- type: W
- name: TTC_GENERATE_GATING_ENABLE
- default: 0x0
- desc: |
- enables generating trickle gating signal in response to TTC BCR.
- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- (See also BC_START, and BC_STOP fields)
- - name: TRICKLE_TRIGGER
- format_name: CR_{parent}_{name}
- type_name: TRICKLE_TRIGGER
- type: T
- bitfield:
- - range: any
- desc: writing to this register issues a single trickle trigger
- value: 1
- - name: TRICKLE_MEMORY_CONFIG
- format_name: CR_{parent}_{name}
- type_name: LCB_TRICKLE_CONFIG
- desc: Trickle trigger configuration
- type: W
- bitfield:
- - range: any
- type: T
- name: MOVE_WRITE_PTR
- value: 1
- desc: |
- Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
- - range: 47..32
- type: W
- name: WRITE_PTR
- default: 0x0
- desc: Trickle configuration memory write pointer
- - range: 31..16
- type: W
- name: VALID_DATA_START
- default: 0x0
- desc: Start address of trickle configuration in trickle memory
- - range: 15..0
- type: W
- name: VALID_DATA_END
- default: 0x0
- desc: Stop address of trickle configuration in trickle memory (last valid byte)
- - name: MODULE_MASK_F_C
- format_name: CR_{parent}_{name}
- type_name: HCC_ABC_MASK_E_C
- type: W
- desc: |
- Disables register commands addressed to masked HCC*/ABC* chips. Register commands for which
- corresponding mask bit is set to '1' will be ignored by the command encoder.
- This is useful to quickly disable trickle configuration for selected
- modules without overwriting the entire trickle configuratrion memory.
- bitfield:
- - range: 63..48
- type: W
- name: HCC_MASK
- default: 0x0
- desc: |
- HCC* module mask
- - range: 47..32
- type: W
- name: ABC_MASK_HCC_E
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0xE
- mask(i) <=> (abc_id = i)
- - range: 31..16
- type: W
- name: ABC_MASK_HCC_D
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0xD
- mask(i) <=> (abc_id = i)
- - range: 15..0
- type: W
- name: ABC_MASK_HCC_C
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0xC
- mask(i) <=> (abc_id = i)
- - name: ABC_MODULE_MASK_B_8
- format_name: CR_{parent}_{name}
- type_name: LCB_ABC_MASK_B_8
- type: W
- desc: |
- Disables register commands addressed to masked ABC* chips. Register commands for which
- corresponding mask bit is set to '1' will be ignored by the command encoder.
- This is useful to quickly disable trickle configuration for selected
- modules without overwriting the entire trickle configuratrion memory.
- bitfield:
- - range: 63..48
- type: W
- name: ABC_MASK_HCC_B
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0xB
- mask(i) <=> (abc_id = i)
- - range: 47..32
- type: W
- name: ABC_MASK_HCC_A
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0xA
- mask(i) <=> (abc_id = i)
- - range: 31..16
- type: W
- name: ABC_MASK_HCC_9
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x9
- mask(i) <=> (abc_id = i)
- - range: 15..0
- type: W
- name: ABC_MASK_HCC_8
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x8
- mask(i) <=> (abc_id = i)
- - name: ABC_MODULE_MASK_7_4
- format_name: CR_{parent}_{name}
- type_name: LCB_ABC_MASK_7_4
- type: W
- desc: |
- Disables register commands addressed to masked ABC* chips. Register commands for which
- corresponding mask bit is set to '1' will be ignored by the command encoder.
- This is useful to quickly disable trickle configuration for selected
- modules without overwriting the entire trickle configuratrion memory.
- bitfield:
- - range: 63..48
- type: W
- name: ABC_MASK_HCC_7
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x7
- mask(i) <=> (abc_id = i)
- - range: 47..32
- type: W
- name: ABC_MASK_HCC_6
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x6
- mask(i) <=> (abc_id = i)
- - range: 31..16
- type: W
- name: ABC_MASK_HCC_5
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x5
- mask(i) <=> (abc_id = i)
- - range: 15..0
- type: W
- name: ABC_MASK_HCC_4
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x4
- mask(i) <=> (abc_id = i)
- - name: ABC_MODULE_MASK_3_0
- format_name: CR_{parent}_{name}
- type_name: LCB_ABC_MASK_3_0
- type: W
- desc: |
- Disables register commands addressed to masked ABC* chips. Register commands for which
- corresponding mask bit is set to '1' will be ignored by the command encoder.
- This is useful to quickly disable trickle configuration for selected
- modules without overwriting the entire trickle configuratrion memory.
- bitfield:
- - range: 63..48
- type: W
- name: ABC_MASK_HCC_3
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x3
- mask(i) <=> (abc_id = i)
- - range: 47..32
- type: W
- name: ABC_MASK_HCC_2
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x2
- mask(i) <=> (abc_id = i)
- - range: 31..16
- type: W
- name: ABC_MASK_HCC_1
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x1
- mask(i) <=> (abc_id = i)
- - range: 15..0
- type: W
- name: ABC_MASK_HCC_0
- default: 0x0
- desc: |
- Masks register commands with destination hcc_id = 0x0
- mask(i) <=> (abc_id = i)
- # - name: LINK_STATS
- # format_name: CR_{parent}_{name}
- # type_name: LCB_STATS
- # desc: LCB link statistics
- # type: R
- # bitfield:
- # - range: 48..32
- # type: R
- # name: TTC_FRAME_RECEIVED_COUNT
- # default: 0x0
- # desc: The number of received BCR and L0 frames from TTC system since last reset
- # - range: 31..16
- # type: R
- # name: TTC_FRAME_SENT_COUNT
- # default: 0x0
- # desc: The number of TTC BCR and L0 frames forwarded to the front-end since last reset
- # - range: 15..0
- # type: R
- # name: CMD_DECODER_ERROR_COUNT
- # default: 0x0
- # desc: The number of errors encountered by LCB command decoder since last reset
- # - name: ELINK_RECENT_DATA
- # format_name: CR_{parent}_{name}
- # desc: Most recent data sent into this elink from host (MSB = oldest)
- # type: R
- # bitfield:
- # - range: any
- # type: R
- # name: value
- # default: 0x0
- # - name: ELINK_BYTE_COUNT
- # format_name: CR_{parent}_{name}
- # desc: The number of bytes written to the elink since last reset
- # type: R
- # bitfield:
- # - range: any
- # type: R
- # name: value
- # default: 0x0
-
-ITK_STRIPS_R3L1_LINK:
- format_name: "{parent}_{index:1}"
- type_name: ITK_R3L1_LINK
- entries:
- - name: CTRL
- format_name: CR_{parent}_{name}
- type_name: R3L1_CTRL
- desc: Determines R3L1 link configuration
- type: W
- bitfield:
- - range: 3..2
- type: W
- name: FRAME_PHASE
- default: 0x0
- desc: phase of R3L1 frame with respect to TTC BCR signal
- - range: 1
- type: W
- name: L1_ENABLE
- default: 0x0
- desc: enables sending TTC L1 signals to the front-end
- - range: 0
- type: W
- name: R3_ENABLE
- default: 0x0
- desc: enables sending RoI R3 signals to the front-end
- # - name: LINK_STATUS
- # format_name: CR_{parent}_{name}
- # type_name: R3L1_STATUS
- # desc: R3L1 link status
- # type: R
- # bitfield:
- # - range: 1
- # type: R
- # name: L1_FIFO_OVERFLOW
- # default: 0x0
- # desc: Whether overflow condition occured in L1 frame FIFO
- # - range: 0
- # type: R
- # name: R3_FIFO_OVERFLOW
- # default: 0x0
- # desc: Whether overflow condition occured in R3 frame FIFO
- # - name: LINK_STATS
- # format_name: CR_{parent}_{name}
- # type_name: R3L1_STATS
- # desc: R3L1 link statistics
- # type: R
- # bitfield:
- # - range: 63..48
- # type: R
- # name: L1_RECEIVED_COUNT
- # default: 0x0
- # desc: The number of L1 frames received from TTC system since last reset
- # - range: 47..32
- # type: R
- # name: R3_RECEIVED_COUNT
- # default: 0x0
- # desc: The number of R3 frames received from RoI system since last reset
- # - range: 31..16
- # type: R
- # name: L1_SENT_COUNT
- # default: 0x0
- # desc: The number of L1 frames sent to front-end since last reset
- # - range: 15..0
- # type: R
- # name: R3_SENT_COUNT
- # default: 0x0
- # desc: The number of R3 frames sent to front-end since last reset
- # - name: ELINK_RECENT_DATA
- # format_name: CR_{parent}_{name}
- # desc: Most recent data sent into this elink from host (MSB = oldest)
- # type: R
- # bitfield:
- # - range: any
- # type: R
- # name: value
- # default: 0x0
- # - name: ELINK_BYTE_COUNT
- # format_name: CR_{parent}_{name}
- # desc: The number of bytes written to the elink since last reset
- # type: R
- # bitfield:
- # - range: any
- # type: R
- # name: value
- # default: 0x0
-
-# ----------------------- ITk strips link configuration end -----------------------
-
-#CR_XOFF_CTRL:
-# number: 24
-# type: W
-# bitfield:
-# - range: 39..0
-# entries:
-# - name: FROMHOST_XOFF_ENABLE
-# format_name: FROMHOST_XOFF_ENABLE_{index:02}
-# desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
-# range: 39..0
-# default: 0
-# - name: FROMHOST_SOFT_XOFF
-# format_name: FROMHOST_SOFT_XOFF_{index:02}
-# desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
-# range: 39..0
-# default: 0
-
-
-IC_FIFOS:
- number: 24
- format_name: IC_FROMHOST_TOHOST_FIFOS
- entries:
- - name: FROMHOST
- format_name: IC_FROMHOST_FIFO_{index:02}
- type_name: IC_FROMHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_FROMHOST_FIFO_{index:02}.FULL
- name: WE
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TOHOST
- format_name: IC_TOHOST_FIFO_{index:02}
- type_name: IC_TOHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_TOHOST_FIFO_{index:02}.EMPTY
- name: RE
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 7
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 6
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 5
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 4
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 9
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 8
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 7
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 6
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
-
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- entries:
- - name: TOHOST
- type_name: TOHOST
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 58
- name: CROUTFIFO_PROG_FULL
- - range: 57
- name: WMFIFO_FULL
- - range: 56
- name: MINI_EGROUP_ALMOST_FULL
- - range: 55..48
- name: EPATH6_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP6
- - range: 47..40
- name: EPATH5_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP5
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
- - name: FROMHOST
- type_name: FROMHOST
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 40
- name: MINI_EGROUP_ALMOST_FULL
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
-
-CR_DEFAULT_EPROC_ENA:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 14..0
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
-
-CR_DEFAULT_EPROC_ENCODING:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- bitfield:
- - range: 15..0
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
-
-CR_BLOCK_COUNTERS:
- desc: Counters to count blocks per GBT channel
- endpoints: 0,1
- number: 24
- entries:
- - name: BLOCK_COUNT
- type_name: CR_BLOCK_COUNT
- format_name: CR_{name}_GBT{index:02}
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- type: W
- bitfield:
- - range: any
- type: T
- name: RESET
- desc: Any write clears the counter value
- value: 1
- - range: 31..0
- type: R
- name: VAL
- desc: Counts the number of blocks that were transferred ToHost in the specified GBT
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 63..48
- name: RDDATA
- type: R
- desc: read data bus
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 0
- desc: write enable for the full mode emulator ram block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 35..0
- desc: read emu ram data
-
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_CHANNEL_DISABLE
- offset: 0x0400
- bitfield:
- - range: 47..0
- desc: Disable selected GBT or FULL mode channel
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE_SELECT
- offset: 0x0480
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RXSLIDE_MANUAL
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TXUSRRDY
- desc: TxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_RXUSRRDY
- desc: RxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_SOFT_RESET
- desc: SOFT_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTTX_RESET
- desc: GTTX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTRX_RESET
- desc: GTRX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 59..48
- name: QPLL_RESET
- desc: QPLL_RESET [11:0]
- - range: 47..0
- name: CPLL_RESET
- desc: CPLL_RESET [47:0]
-
- - name: GBT_SOFT_TX_RESET
- offset: 0x0500
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_SOFT_RX_RESET
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_ODD_EVEN
- desc: OddEven [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TOPBOT
- desc: TopBot [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_TC_DLY_VALUE3
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [143:96]
-
- - name: GBT_TX_TC_DLY_VALUE4
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [191:144]
-
- - name: GBT_DATA_TXFORMAT1
- desc: DATA_TXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_TXFORMAT2
- desc: DATA_TXFORMAT [95:48]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT1
- desc: DATA_RXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT2
- desc: DATA_RXFORMAT [95:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_RESET
- desc: TX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_RESET
- desc: RX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_METHOD
- desc: TX time domain crossing method [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUTMUX_SEL
- desc: Descrambler output MUX selection [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TC_EDGE
- desc: Sampling edge selection for TX domain crossing [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for transmitter of GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_RXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for the receiver of the GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
- - name: GBT_TOHOST_FANOUT
- offset: 0x0700
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_TOFRONTEND_FANOUT
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- desc: TX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXRESET_DONE
- desc: RX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXFSMRESET_DONE
- desc: TX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXFSMRESET_DONE
- desc: RX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_LOCK
- bitfield:
- - range: 59..48
- name: QPLL_LOCK
- desc: QPLL LOCK [11:0]
- - range: 47..0
- name: CPLL_LOCK
- desc: CPLL LOCK [47:0]
-
- - name: GBT_RXCDR_LOCK
- desc: RX CDR LOCK [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CLK_SAMPLED
- desc: clk sampled [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_HEADER
- desc: RX IS HEADER [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_DATA
- desc: RX IS DATA [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_HEADER_FOUND
- desc: RX HEADER FOUND [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUT_MUX_STATUS
- desc: GBT output mux status [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ERROR
- desc: Error flags [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GBT_TOPBOT_C
- desc: TopBot_c [47:0]
- generate: GBT_GENERATE_ALL_REGS = true
- bitfield:
- - range: 47..0
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-TTCBUSYControlsAndMonitors:
- group: TTCBUSY
- desc: TTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: TTC_BUSY_ACCEPTED
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 2
- name: FULL
- type: R
- desc: TTC Emulator memory full indication
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
-
- - ref: TTC_DELAY
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the BUSY Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
- - name: TTC_EMU_CONTROL
- type: W
- bitfield:
- - range: any
- name: WE
- type: T
- desc: Any write to this register executes a write enable
- value: 1
- - range: 35
- name: LAST_LINE
- desc: Last line of the sequence
- - range: 34
- name: REPEAT
- desc: Repeat the sequence
- - range: 32
- name: BROADCAST5
- desc: Broadcast 5
- - range: 31
- name: BROADCAST4
- desc: Broadcast 4
- - range: 30
- name: BROADCAST3
- desc: Broadcast 3
- - range: 29
- name: BROADCAST2
- desc: Broadcast 2
- - range: 28
- name: BROADCAST1
- desc: Broadcast 1
- - range: 27
- name: BROADCAST0
- desc: Broadcast 0
- - range: 26
- name: ECR
- desc: Event counter reset
- - range: 25
- name: BCR
- desc: Bunch counter reset
- - range: 24
- name: L1A
- desc: Level 1 Accept
- - range: 21..0
- name: STEP_COUNTER
- desc: Step counter value
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range: 26..15
- name: BCID_ONBCR
- type: W
- desc: BCID is set to this value when BCR arrives
- - range: 14
- name: BUSY_OUTPUT_STATUS
- type: R
- desc: Actual status of the BUSY LEMO output signal
- - range: 13
- name: ECR_BCR_SWAP
- default: 0
- desc: ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
- - range: 12
- name: BUSY_OUTPUT_INHIBIT
- default: 0
- desc: forces the Busy LEMO output to BUSY-OFF
- - range: 11
- name: TOHOST_RST
- desc: reset toHost in ttc decoder
- default: 0
- - range: 10
- name: TT_BCH_EN
- desc: trigger type enable / disable for TTC-ToHost
- default: 1
- - range: 9..2
- name: XL1ID_SW
- desc: set XL1ID value, the value to be set by XL1ID_RST signal
- default: 0x00
- - range: 1
- name: XL1ID_RST
- desc: giving a trigger signal to reset XL1ID value
- default: 0
- - range: 0
- name: MASTER_BUSY
- desc: L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range: 15..5
- name: TH_FF_COUNT
- desc: ToHostData Fifo counts
- - range: 4
- name: TH_FF_FULL
- desc: ToHostData Fifo status 1:full 0:not full
- - range: 3
- name: TH_FF_EMPTY
- desc: ToHostData Fifo status 1:empty 0:not empty
- - range: 2..0
- name: TTC_BIT_ERR
- desc: double bit, single bit and comm error in TTC data
-
-TTC_BUSY_ACCEPTED:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- bitfield:
- - range: 56..0
- entries:
- - name: BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
-
-
-TTC_DELAY:
- number: 48
- type: W
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Controls the TTC Fanout delay values
- bitfield:
- - range: 3..0
- default: 0
-
-XOFF_BUSYControlsAndMonitors:
- group: XOFF
- desc: XOFF Controls and Monitors, see table 2 of Busy specs manual
- endpoints: 0, 1
- entries:
- - name: XOFF_FM_CH_FIFO_THRESH_LOW
- desc: Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xB
- - range: 43..40
- name: CH10
- default: 0xB
- - range: 39..36
- name: CH09
- default: 0xB
- - range: 35..32
- name: CH08
- default: 0xB
- - range: 31..28
- name: CH07
- default: 0xB
- - range: 27..24
- name: CH06
- default: 0xB
- - range: 23..20
- name: CH05
- default: 0xB
- - range: 19..16
- name: CH04
- default: 0xB
- - range: 15..12
- name: CH03
- default: 0xB
- - range: 11..8
- name: CH02
- default: 0xB
- - range: 7..4
- name: CH01
- default: 0xB
- - range: 3..0
- name: CH00
- default: 0xB
-
- - name: XOFF_FM_CH_FIFO_THRESH_HIGH
- desc: Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xB
- - range: 43..40
- name: CH10
- default: 0xB
- - range: 39..36
- name: CH09
- default: 0xB
- - range: 35..32
- name: CH08
- default: 0xB
- - range: 31..28
- name: CH07
- default: 0xB
- - range: 27..24
- name: CH06
- default: 0xB
- - range: 23..20
- name: CH05
- default: 0xB
- - range: 19..16
- name: CH04
- default: 0xB
- - range: 15..12
- name: CH03
- default: 0xB
- - range: 11..8
- name: CH02
- default: 0xB
- - range: 7..4
- name: CH01
- default: 0xB
- - range: 3..0
- name: CH00
- default: 0xB
-
- - name: XOFF_FM_LOW_THRESH_CROSSED
- desc: FIFO filled beyond the low threshold, 1 bit per channel
- type: R
- bitfield:
- - range: 11..0
- - name: XOFF_FM_HIGH_THRESH
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- desc: Writing this register will clear all CROSS_LATCHED bits
- type: T
- value: 1
- - range: 23..12
- type: R
- name: CROSS_LATCHED
- desc: FIFO filled beyond the high threshold, 1 latch bit per channel
- - range: 11..0
- type: R
- name: CROSSED
- desc: FIFO filled beyond the high threshold, 1 bit per channel
-
- - name: XOFF_FM_SOFT_XOFF
- type: W
- desc: Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
- bitfield:
- - range: 23..0
-
- - name: XOFF_ENABLE
- type: W
- desc: Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
- bitfield:
- - range: 23..0
-
- - name: DMA_BUSY_STATUS
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR_LATCH
- desc: Any write to this register clears TOHOST_BUSY_LATCHED
- - range: 4
- type: W
- name: ENABLE
- desc: Enable the DMA buffer on the server as a source of busy
- default: 0
- - range: 3
- type: R
- name: TOHOST_BUSY_LATCHED
- desc: A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => tohost_busy_latched_40_s)
- - range: 2
- type: R
- name: FROMHOST_BUSY_LATCHED
- desc: A fromhost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => fromhost_busy_latched_40_s)
- - range: 1
- type: R
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => fromhost_busy_40_s)
- - range: 0
- type: R
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => tohost_busy_40_s)
-
- - name: FM_BUSY_CHANNEL_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- type: T
- value: 1
- desc: Any write to this register will clear the BUSY_LATCHED bits
- - range: 23..12
- type: R
- name: BUSY_LATCHED
- desc: one Indicates that the given FULL mode channel has received BUSY-ON
- - range: 11..0
- type: R
- name: BUSY
- desc: one Indicates that the given FULL mode channel is currently in BUSY state
-
- - name: BUSY_MAIN_OUTPUT_FIFO_THRESH
- type: W
- bitfield:
- - range: 24
- name: BUSY_ENABLE
- desc: Enable busy generation if thresholds are crossed
- default: 0
- - range: 23..12
- name: LOW
- desc: Low, Negate threshold of busy generation from main output fifo
- default: 0x3FF
- - range: 11..0
- name: HIGH
- desc: High, Assert threshold of busy generation from main output fifo
- default: 0x4FF
-
- - name: BUSY_MAIN_OUTPUT_FIFO_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCHED
- value: 1
- desc: Any write to this register will clear the
- type: T
- - range: 2
- type: R
- name: HIGH_THRESH_CROSSED_LATCHED
- desc: Main output fifo has been full beyond HIGH THRESHOLD, write to clear
- - range: 1
- type: R
- name: HIGH_THRESH_CROSSED
- desc: Main output fifo is full beyond HIGH THRESHOLD
- - range: 0
- type: R
- name: LOW_THRESH_CROSSED
- desc: Main output fifo is full beyond LOW THRESHOLD
- - ref: ELINK_BUSY_ENABLE
-
-
-ELINK_BUSY_ENABLE:
- desc: Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- number: 24
- endpoints: 0
- type: W
- bitfield:
- - range: 56..0
- entries:
- - name: ELINK_BUSY_ENABLE
- format_name: ELINK_BUSY_ENABLE{index:02}
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
-
- - name: HK_MON_FMC
- type: W
- bitfield:
- - range: 1
- name: SI5345_LOL
- desc: Si5345 Loss Of Lock pin
- - range: 0
- name: SI5345_INTR
- desc: Si5345 Interrupt flagging chip change of status
-
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_SEL
- default: 0x1
- desc: |
- 1: LCLK
- 0: TTC
- - range: 2..1
- type: R
- name: MAIN_INPUT
- desc: |
- Main MMCM Oscillator Input
- 2: LCLK fixed
- 1: TTC fixed
- 0: selectable
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL-711 locked
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
-
- - name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
-
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_4
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#4
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
-
- - name: TACH_CNT
- type: R
- desc: Readout of the Fan tachometer speed of the BNL712 board
- bitfield:
- - range: 19..0
-
-Generators:
- group: GEN
- desc: Specific registers for Hardware based Generators
- endpoints: 0
- generate: EMU_GENERATE_REGS = true
- entries:
-
- - ref: FELIG_DATA_GEN_CONFIG_ARR
- offset: 0x20
- - ref: FELIG_ELINK_CONFIG_ARR
- - ref: FELIG_ELINK_ENABLE_ARR
-
- - name: FELIG_GLOBAL_CONTROL
- type: W
- bitfield:
- - range: 63..36
- name: FAKE_L1A_RATE
- default: 0
- desc: Sets the internal fake L1 trigger rate. [25ns/LSB]
- - range: 35..14
- name: PICXO_OFFSET_PPM
- default: 0
- desc: When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
- - range: 12..12
- name: TRACK_DATA
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 11..11
- name: RXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 10..10
- name: TXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 9..9
- name: AUTO_RESET
- default: 0
- desc: FELIG GT core control. If set the GT core automatically resets on data error.
- - range: 8..8
- name: PICXO_RESET
- default: 0
- desc: FELIG GT core control. Manual PICXO reset.
- - range: 7..7
- name: GTTX_RESET
- default: 0
- desc: FELIG GT core control. Manual GT TX reset
- - range: 6..6
- name: CPLL_RESET
- default: 0
- desc: FELIG GT core control. Manual CPLL reset.
- - range: 5..0
- name: X3_X4_OUTPUT_SELECT
- default: 0
- desc: X3/X4 SMA output source select.
-
- - ref: FELIG_LANE_CONFIG_ARR
- - ref: FELIG_MON_TTC_0_ARR
- - ref: FELIG_MON_TTC_1_ARR
- - ref: FELIG_MON_COUNTERS_ARR
- - ref: FELIG_MON_FREQ_ARR
-
- - name: FELIG_MON_FREQ_GLOBAL
- type: W
- bitfield:
- - range: 63..32
- name: XTAL_100MHZ
- default: 0
- desc: FELIG local oscillator frequency[Hz].
- - range: 31..0
- name: CLK_41_667MHZ
- desc: FELIG PCIE MGTREFCLK frequency[Hz].
-
- - ref: FELIG_MON_L1A_ID_ARR
- - ref: FELIG_MON_PICXO_ARR
-
- - name: FELIG_RESET
- type: W
- bitfield:
- - range: 63..48
- name: LB_FIFO
- default: 0
- desc: One bit per lane. When set to 1, resets all loopback FIFOs.
- - range: 47..24
- name: FRAMEGEN
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG link checking logic.
- - range: 23..0
- name: LANE
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG lane logic.
-
- - name: FELIG_RX_SLIDE_RESET
- type: W
- bitfield:
- - range: 23..0
- default: 0
- desc: One bit per lane. When set to 1, resets the gbt rx slide counter.
-
- - name: FMEMU_EVENT_INFO
- type: W
- offset: 0x1800
- bitfield:
- - range: 63..32
- name: L1ID
- default: 0
- desc: 32b field to show L1ID
- - range: 31..0
- name: BCID
- default: 0
- desc: 32b field to show BCID
-
- - name: FMEMU_COUNTERS
- type: W
- bitfield:
- - range: 63..48
- name: WORD_CNT
- default: 32
- desc: Number of 32b words in one chunk
- - range: 47..32
- name: IDLE_CNT
- default: 3
- desc: Minimum number of idles between chunks
- - range: 31..16
- name: L1A_CNT
- default: 256
- desc: Number of chunks to send if not in TTC mode
- - range: 15..8
- name: BUSY_TH_HIGH
- default: 20
- desc: Assert BUSY-ON above this threshold
- - range: 7..0
- name: BUSY_TH_LOW
- default: 15
- desc: De-assert BUSY-ON below this threshold
-
- - name: FMEMU_CONTROL
- type: W
- bitfield:
- - range: 63..56
- type: W
- name: L1A_BITNR
- default: 32
- desc: Bitfield for L1A in TTC frame
- - range: 55..48
- type: W
- name: XONXOFF_BITNR
- default: 32
- desc: Bitfield for Xon/Xoff in TTC frame
- - range: 47..47
- type: W
- name: EMU_START
- default: 0
- desc: Start emulator functionality
- - range: 46..46
- type: W
- name: TTC_MODE
- default: 0
- desc: Control the emulator by TTC input or by RegMap (1/0)
- - range: 45..45
- type: W
- name: XONXOFF
- default: 0
- desc: Debug Xon/Xoff functionality (1/0)
- - range: 44..44
- type: W
- name: INLC_CRC32
- default: 0
- desc: |
- 0: No checksum
- 1: Append the data with a CRC32
- - range: 43..43
- type: W
- name: BCR
- default: 0
- desc: Reset BCID to 0
- - range: 42..42
- type: W
- name: ECR
- default: 0
- desc: Reset L1ID to 0
- - range: 41..41
- type: W
- name: DATA_SRC_SEL
- default: 0
- desc: |
- Data source select
- 0: Data input comes from EMURAM
- 1: Data input comes from PCIe
- - range: 40..32
- type: R
- name: INT_STATUS_EMU
- default: 0
- desc: Read internal status emulator
- - range: 31..16
- type: W
- name: FFU_FM_EMU_T
- default: 0
- desc: For Future Use (trigger registers)
- - range: 15..0
- type: W
- name: FFU_FM_EMU_W
- default: 0
- desc: For Future Use (write registers)
-
- - name: FMEMU_RANDOM_RAM_ADDR
- type: W
- desc: Controls the address of the ramblock for the random number generator
- bitfield:
- - range: 9..0
- - name: FMEMU_RANDOM_RAM
- type: W
- bitfield:
- - range: any
- type: T
- name: WE
- value: 1
- desc: Any write to this register (DATA) triggers a write to the ramblock
- - range: 39..16
- name: CHANNEL_SELECT
- value: 0xFFFFFF
- desc: Enable write enable only for the selected channel
- - range: 15..0
- name: DATA
- type: W
- desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
- - name: FMEMU_RANDOM_CONTROL
- type: W
- desc: Controls the random chunk length generator
- bitfield:
- - name: SELECT_RANDOM
- range: 20
- desc: 1 enables the random chunk length, 0 uses a constant chunk length
- default: 0
- - name: SEED
- range: 19..10
- desc: Seed for the random number generator, should not be 0
- default: 0x200
- - name: POLYNOMIAL
- range: 9..0
- desc: POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
- default: 0x240
-
-
-#Registers that are replicated 24 times under Generators:
-FELIG_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_DATA_GEN_CONFIG
- format_name: FELIG_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_DATA_GEN_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: USERDATA
- range: 63..48
- default: 0
- desc: Sets static payload word. When PATTERN_SEL=1.
- - name: CHUNK_LENGTH
- range: 47..32
- default: 0
- desc: FELIG data generator chunk-length in bytes.
- - name: RESET
- range: 19..15
- default: 0
- desc: FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- - name: SW_BUSY
- range: 14..10
- default: 0
- desc: FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- - name: DATA_FORMAT
- range: 9..5
- default: 0
- desc: FELIG data generator format. 0:8b10b, 1:direct.
- - name: PATTERN_SEL
- range: 4..0
- default: 0
- desc: FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
-
-FELIG_ELINK_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_CONFIG
- format_name: FELIG_ELINK_CONFIG_{index:02}
- type_name: FELIG_ELINK_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: ENDIAN_MOD
- range: 39..35
- default: 0
- desc: FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- - name: INPUT_WIDTH
- range: 34..30
- default: 0
- desc: FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- - name: OUTPUT_WIDTH
- range: 9..0
- default: 0
- desc: FELIG elink data output width.
-
-FELIG_ELINK_ENABLE_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_ENABLE
- format_name: FELIG_ELINK_ENABLE_{index:02}
- type_name: FELIG_ELINK_ENABLE
- desc: FELIG specific configuration registers
- bitfield:
- - range: 39..0
- default: 0
- desc: FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
-
-FELIG_LANE_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_LANE_CONFIG
- format_name: FELIG_LANE_CONFIG_{index:02}
- type_name: FELIG_LANE_CONFIG
- desc: FELIG specific configuration registers
- bitfield:
- - name: B_CH_BIT_SEL
- range: 63..42
- default: 0
- desc: When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- - name: A_CH_BIT_SEL
- range: 41..35
- default: 0
- desc: Selects the bit from the received FELIX data from which to extract the L1A.
- - name: LB_FIFO_DELAY
- range: 34..30
- default: 0
- desc: When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- - name: ELINK_SYNC
- range: 7..7
- default: 0
- desc: When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- - name: PICXO_OFFEST_EN
- range: 6..6
- default: 0
- desc: FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- - name: PI_HOLD
- range: 5..5
- default: 0
- desc: FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- - name: GBT_LB_ENABLE
- range: 4..4
- default: 0
- desc: FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- - name: GBH_LB_ENABLE
- range: 3..3
- default: 0
- desc: FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- - name: L1A_SOURCE
- range: 2..2
- default: 0
- desc: FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- - name: GBT_EMU_SOURCE
- range: 1..1
- default: 0
- desc: FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- - name: FG_SOURCE
- range: 0..0
- default: 0
- desc: FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
-
-FELIG_MON_TTC_0_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_0
- format_name: FELIG_MON_TTC_0_{index:02}
- type_name: FELIG_MON_TTC_0
- desc: FELIG specific configuration registers
- bitfield:
- - name: L1ID
- range: 63..40
- default: 0
- desc: Live TTC data monitor.
- - name: XL1ID
- range: 39..32
- default: 0
- desc: Live TTC data monitor.
- - name: BCID
- range: 31..20
- default: 0
- desc: Live TTC data monitor.
- - name: RESERVED0
- range: 19..16
- default: 0
- desc: Live TTC data monitor.
- - name: LEN
- range: 15..8
- default: 0
- desc: Live TTC data monitor.
- - name: FMT
- range: 7..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_TTC_1_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_1
- format_name: FELIG_MON_TTC_1_{index:02}
- type_name: FELIG_MON_TTC_1
- desc: FELIG specific configuration registers
- bitfield:
- - name: RESERVED1
- range: 63..48
- default: 0
- desc: Live TTC data monitor.
- - name: TRIGGER_TYPE
- range: 47..32
- default: 0
- desc: Live TTC data monitor.
- - name: ORBIT
- range: 31..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_COUNTERS_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_COUNTERS
- format_name: FELIG_MON_COUNTERS_{index:02}
- type_name: FELIG_MON_COUNTERS
- desc: FELIG specific configuration registers
- bitfield:
- - name: SLIDE_COUNT
- range: 63..32
- default: 0
- desc: Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- - name: FC_ERROR_COUNT
- range: 31..0
- default:
- desc: When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
-
-FELIG_MON_FREQ_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_FREQ
- format_name: FELIG_MON_FREQ_{index:02}
- type_name: FELIG_MON_FREQ
- desc: FELIG specific configuration registers
- bitfield:
- - name: TX
- range: 63..32
- default: 0
- desc: FELIG regenerated TX clock frequency[Hz].
- - name: RX
- range: 31..0
- default: 0
- desc: FELIG recovered RX clock frequency[Hz].
-
-FELIG_MON_L1A_ID_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_L1A_ID
- format_name: FELIG_MON_L1A_ID_{index:02}
- type_name: FELIG_MON_L1A_ID
- desc: FELIG specific configuration registers
- bitfield:
- - range: 31..0
- default: 0
- desc: FELIG's last L1 ID.
-
-FELIG_MON_PICXO_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_PICXO
- format_name: FELIG_MON_PICXO_{index:02}
- type_name: FELIG_MON_PICXO
- desc: FELIG specific configuration registers
- bitfield:
- - name: VLOT
- range: 53..32
- default: 0
- desc: Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- - name: ERROR
- range: 20..0
- default: 0
- desc: Value indicates RX to TX frequency tracking error.
-
diff --git a/sources/templates/yaml/registers-4.7.yaml b/sources/templates/yaml/registers-4.7.yaml
deleted file mode 100644
index 23b41ca3841dd3bfecf814c7661c7c3a6df9b178..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-4.7.yaml
+++ /dev/null
@@ -1,2777 +0,0 @@
-Registers:
- version: '4.7'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: TTCBUSYControlsAndMonitors
- record_name: register_map_ttc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: XOFF_BUSYControlsAndMonitors
- record_name: register_map_xoff_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: Generators
- record_name: register_map_generators
- bitfield:
- - range: 0..0
- type: R
- - name: Wishbone
- record_name: wishbone_monitor
- bitfield:
- - range: 0..0
- type: R
-
-#Bar0 contains the registers dedicated to Wupper. Please only edit registers in Bar2
-#Registers in this group will not be generated with WupperCodeGen
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
- - name: BUSY_THRESHOLD_ASSERT
- type: W
- desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
- default: 0x6400000
- bitfield:
- - range: 63..0
-
- - name: BUSY_THRESHOLD_NEGATE
- type: W
- desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
- default: 0x6E00000
- bitfield:
- - range: 63..0
-
- - name: BUSY_STATUS
- type: R
- bitfield:
- - range: 1
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- - range: 0
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
- - name: PC_PTR_GAP
- type: W
- desc: This is the minimum value that the pc_pointer in a descriptor has to decrease in order to flip the evencycle_pc bit
- default: 0x1000000
- bitfield:
- - range: 63..0
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: SW_POINTER
- desc: Pointer controlled by the software, indicating read or write status for circular DMA
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: FROMHOST
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: FW_POINTER
- desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
-
-
-#Bar1 contains the registers dedicated to the Wupper interrupg controller.
-#Please only edit registers in Bar2.
-#Registers in this group will not be generated with WupperCodeGen
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 16
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-#Bar 2 contains application specific registers, used in the example application.
-#Registers in this group (and it's referenced subroups) will be generated with
-#WupperCodeGen for wupper Firmware, Software and Documentation
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x5000
- - ref: GBTWrapperControls
- offset: 0x6000
- - ref: GBTWrapperMonitors
- offset: 0x7000
- - ref: TTCBUSYControlsAndMonitors
- offset: 0x8000
- - ref: XOFF_BUSYControlsAndMonitors
- offset: 0x8800
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x9000
- - ref: Generators
- offset: 0xA000
- - ref: Wishbone
- offset: 0xC000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned({{ tree.version|version }},16))
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: GIT_COMMIT_TIME
- bitfield:
- - range: 39..0
- value: COMMIT_DATETIME
- desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_TAG
- bitfield:
- - range: 63..0
- value: GIT_TAG(63 downto 0)
- desc: String containing the current GIT TAG
-
- - name: GIT_COMMIT_NUMBER
- bitfield:
- - range: 31..0
- value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
- desc: Number of GIT commits after current GIT_TAG
-
- - name: GIT_HASH
- bitfield:
- - range: 31..0
- value: GIT_HASH(159 downto 128)
- desc: Short GIT hash (32 bit)
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC-709
- - 710 (0x2c6): HTG-710
- - 711 (0x2c7): BNL-711
- - 712 (0x2c8): BNL-712
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - ref: INCLUDE_EGROUPS
-
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 3..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
- 3: FEI4 mode
- 4: ITK Pixel
- 5: ITK Strip
- 6: FELIG
- 7: FULL mode emulator
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
- - name: BLOCKSIZE
- type: R
- desc: Number of bytes in a block
- bitfield:
- - range: 15..0
-
- - name: PCIE_ENDPOINT
- type: R
- desc: Indicator of the PCIe endpoint on BNL71x cards with two endpoints. 0 or 1
- bitfield:
- - range: 0
- value: std_logic_vector(to_unsigned(PCIE_ENDPOINT, 1))
-
-
-INCLUDE_EGROUPS:
- number: 7
- entries:
- - format_name: INCLUDE_EGROUP_{index}
- name: INCLUDE_EGROUP
- type_name: INCLUDE_EGROUP
- type: R
- bitfield:
- - range: 8
- name: FROMHOST_02
- desc: FromHost EPROC02 is included in this EGROUP
- - range: 7
- name: FROMHOST_04
- desc: FromHost EPROC04 is included in this EGROUP
- - range: 6
- name: FROMHOST_08
- desc: FromHost EPROC8 is included in this EGROUP
- - range: 5
- name: FROMHOST_HDLC
- desc: FromHost HDLC is included in this EGROUP
- - range: 4
- name: TOHOST_02
- desc: ToHost EPROC02 is included in this EGROUP
- - range: 3
- name: TOHOST_04
- desc: ToHost EPROC04 is included in this EGROUP
- - range: 2
- name: TOHOST_08
- desc: ToHost EPROC08 is included in this EGROUP
- - range: 1
- name: TOHOST_16
- desc: ToHost EPROC16 is included in this EGROUP
- - range: 0
- name: TOHOST_HDLC
- desc: ToHost HDLC is included in this EGROUP
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: IC_FROMHOST_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: CR_TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - name: CR_REVERSE_10B
- desc: Reverse 10-bit word of elink data
- type: W
- bitfield:
- - range: 1
- name: FROMHOST
- default: 1
- desc: |
- 1: Serialize 10-bit word in FromHost EPROCS MSB first
- 0: Serialize 10-bit word in FromHost EPROCS LSB first
- - range: 0
- name: TOHOST
- default: 1
- desc: |
- 1: Receive 10-bit word in ToHost EPROCS, MSB first
- 0: Receive 10-bit word in ToHost EPROCS, LSB first
-
- - name: CR_LTDB_TTC_DELAY
- desc: Controls TTC BCR delay in LTDB mode firmware
- type: W
- bitfield:
- - range: 7
- name: EGROUP4_EPATH6
- default: 0
- desc: |
- Egroup 4, Epath 6
- 1: Half a clock delay
- 0: no delay
- - range: 6
- name: EGROUP4_EPATH5
- default: 0
- desc: |
- Egroup 4, Epath 5
- 1: Half a clock delay
- 0: no delay
- - range: 5
- name: EGROUP4_EPATH4
- default: 0
- desc: |
- Egroup 4, Epath 4
- 1: Half a clock delay
- 0: no delay
- - range: 4
- name: EGROUP4_EPATH3
- default: 0
- desc: |
- Egroup 4, Epath 3
- 1: Half a clock delay
- 0: no delay
- - range: 3
- name: EGROUP4_EPATH0
- default: 0
- desc: |
- Egroup 4, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 2
- name: EGROUP3
- default: 0
- desc: |
- Egroup 3, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 1
- name: EGROUP2
- default: 0
- desc: |
- Egroup 2, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 0
- name: EGROUP1
- default: 0
- desc: |
- Egroup 1, Epath 0
- 1: Half a clock delay
- 0: no delay
-# - ref: CR_XOFF_CTRL
-# offset: 0x2800
-# desc: Configure FromHost Xoff
-
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x3000
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA_G
- - ref: CR_DEFAULT_EPROC_ENCODING_G
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
- - ref: CR_BLOCK_COUNTERS
-
-
-CR_GBT_CTRL:
- number: 24
- bitfield:
- - range: 50..0
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- entries:
- - ref: EGROUP_TOHOST
- - ref: EGROUP_FROMHOST
-
-EGROUP_TOHOST:
- number: 7
- format_name: GBT{index:02}
- name: GBT
- entries:
- - name: TOHOST
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_TOHOST_EGROUP_CTRL
- bitfield:
- - range: 58..51
- name: INSTANT_TIMEOUT_ENA
- default: 0x0
- desc: instantly initiate a timeout for the given epath
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..31
- name: MAX_CHUNK_LEN
- default: MAX_CHUNK_LEN_array
- desc: set the maximum length of a chunk, 0 disables truncation
- - range: 30..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- default:
- - PATH_ENCODING_array(0)
- - PATH_ENCODING_array(1)
- - PATH_ENCODING_array(2)
- - PATH_ENCODING_array(3)
- - PATH_ENCODING_array(4)
- - PATH_ENCODING_array(5)
- - PATH_ENCODING_array(6)
-
- - range: 14..0
- name: EPROC_ENA
- desc: Enable bits per EPROC
- default:
- - EPROC_ENA_bits_array(0)
- - EPROC_ENA_bits_array(1)
- - EPROC_ENA_bits_array(2)
- - EPROC_ENA_bits_array(3)
- - EPROC_ENA_bits_array(4)
- - EPROC_ENA_bits_array(5)
- - EPROC_ENA_bits_array(6)
-
-EGROUP_FROMHOST:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FROMHOST
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_FROMHOST_EGROUP_CTRL
- bitfield:
- - range: 54..47
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 46..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- greater than 3: TTC mode, see CentralRouter doc
- default:
- - FROMHOST_PATH_ENCODING_array(0)
- - FROMHOST_PATH_ENCODING_array(1)
- - FROMHOST_PATH_ENCODING_array(2)
- - FROMHOST_PATH_ENCODING_array(3)
- - FROMHOST_PATH_ENCODING_array(4)
- - FROMHOST_PATH_ENCODING_array(5)
- - FROMHOST_PATH_ENCODING_array(6)
- - range: 14..0
- desc: Enable bits per EPROC
- name: EPROC_ENA
-
-#CR_XOFF_CTRL:
-# number: 24
-# type: W
-# bitfield:
-# - range: 39..0
-# entries:
-# - name: FROMHOST_XOFF_ENABLE
-# format_name: FROMHOST_XOFF_ENABLE_{index:02}
-# desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
-# range: 39..0
-# default: 0
-# - name: FROMHOST_SOFT_XOFF
-# format_name: FROMHOST_SOFT_XOFF_{index:02}
-# desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
-# range: 39..0
-# default: 0
-
-
-IC_FIFOS:
- number: 24
- format_name: IC_FROMHOST_TOHOST_FIFOS
- entries:
- - name: FROMHOST
- format_name: IC_FROMHOST_FIFO_{index:02}
- type_name: IC_FROMHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_FROMHOST_FIFO({index}).FULL
- name: WE
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TOHOST
- format_name: IC_TOHOST_FIFO_{index:02}
- type_name: IC_TOHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_TOHOST_FIFO({index}).EMPTY
- name: RE
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 7
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 6
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 5
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 4
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 9
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 8
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 7
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 6
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
-
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- entries:
- - name: TOHOST
- type_name: CR_TOHOST_GBT_MON
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 58
- name: CROUTFIFO_PROG_FULL
- - range: 57
- name: WMFIFO_FULL
- - range: 56
- name: MINI_EGROUP_ALMOST_FULL
- - range: 55..48
- name: EPATH6_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP6
- - range: 47..40
- name: EPATH5_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP5
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
- - name: FROMHOST
- type_name: CR_FROMHOST_GBT_MON
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 40
- name: MINI_EGROUP_ALMOST_FULL
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
-
-CR_DEFAULT_EPROC_ENA_G:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
- type_name: CR_DEFAULT_EPROC_ENA
- bitfield:
- - range: 14..0
-
-
-CR_DEFAULT_EPROC_ENCODING_G:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
- type_name: CR_DEFAULT_EPROC_ENCODING
- bitfield:
- - range: 15..0
-
-
-CR_BLOCK_COUNTERS:
- desc: Counters to count blocks per GBT channel
- endpoints: 0,1
- number: 24
- entries:
- - name: BLOCK_COUNT
- type_name: CR_BLOCK_COUNT
- format_name: CR_{name}_GBT{index:02}
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- type: W
- bitfield:
- - range: any
- type: T
- name: RESET
- desc: Any write clears the counter value
- value: 1
- - range: 31..0
- type: R
- name: VAL
- desc: Counts the number of blocks that were transferred ToHost in the specified GBT
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 63..48
- name: RDDATA
- type: R
- desc: read data bus
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 0
- desc: write enable for the full mode emulator ram block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 35..0
- desc: read emu ram data
-
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_CHANNEL_DISABLE
- offset: 0x0400
- bitfield:
- - range: 47..0
- desc: Disable selected GBT or FULL mode channel
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE_SELECT
- offset: 0x0480
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_RXSLIDE_MANUAL
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_TXUSRRDY
- desc: TxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_RXUSRRDY
- desc: RxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_SOFT_RESET
- desc: SOFT_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTTX_RESET
- desc: GTTX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTRX_RESET
- desc: GTRX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 59..48
- name: QPLL_RESET
- desc: QPLL_RESET [11:0]
- - range: 47..0
- name: CPLL_RESET
- desc: CPLL_RESET [47:0]
-
- - name: GBT_SOFT_TX_RESET
- offset: 0x0500
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_SOFT_RX_RESET
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_ODD_EVEN
- desc: OddEven [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_TOPBOT
- desc: TopBot [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_TC_DLY_VALUE3
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [143:96]
-
- - name: GBT_TX_TC_DLY_VALUE4
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [191:144]
-
- - name: GBT_DATA_TXFORMAT1
- desc: DATA_TXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_TXFORMAT2
- desc: DATA_TXFORMAT [95:48]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT1
- desc: DATA_RXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT2
- desc: DATA_RXFORMAT [95:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_RESET
- desc: TX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_RESET
- desc: RX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_METHOD
- desc: TX time domain crossing method [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUTMUX_SEL
- desc: Descrambler output MUX selection [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TC_EDGE
- desc: Sampling edge selection for TX domain crossing [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for transmitter of GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_RXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for the receiver of the GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
- - name: GBT_TOHOST_FANOUT
- offset: 0x0700
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_TOFRONTEND_FANOUT
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- desc: TX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXRESET_DONE
- desc: RX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXFSMRESET_DONE
- desc: TX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXFSMRESET_DONE
- desc: RX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_LOCK
- bitfield:
- - range: 59..48
- name: QPLL_LOCK
- desc: QPLL LOCK [11:0]
- - range: 47..0
- name: CPLL_LOCK
- desc: CPLL LOCK [47:0]
-
- - name: GBT_RXCDR_LOCK
- desc: RX CDR LOCK [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CLK_SAMPLED
- desc: clk sampled [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_HEADER
- desc: RX IS HEADER [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_DATA
- desc: RX IS DATA [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_HEADER_FOUND
- desc: RX HEADER FOUND [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUT_MUX_STATUS
- desc: GBT output mux status [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ERROR
- desc: Error flags [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GBT_TOPBOT_C
- desc: TopBot_c [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-TTCBUSYControlsAndMonitors:
- group: TTCBUSY
- desc: TTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: TTC_BUSY_ACCEPTED_G
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 2
- name: FULL
- type: R
- desc: TTC Emulator memory full indication
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
-
- - ref: TTC_DELAY
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the BUSY Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
- - name: TTC_EMU_CONTROL
- type: W
- bitfield:
- - range: any
- name: WE
- type: T
- desc: Any write to this register executes a write enable
- value: 1
- - range: 35
- name: LAST_LINE
- desc: Last line of the sequence
- - range: 34
- name: REPEAT
- desc: Repeat the sequence
- - range: 32
- name: BROADCAST5
- desc: Broadcast 5
- - range: 31
- name: BROADCAST4
- desc: Broadcast 4
- - range: 30
- name: BROADCAST3
- desc: Broadcast 3
- - range: 29
- name: BROADCAST2
- desc: Broadcast 2
- - range: 28
- name: BROADCAST1
- desc: Broadcast 1
- - range: 27
- name: BROADCAST0
- desc: Broadcast 0
- - range: 26
- name: ECR
- desc: Event counter reset
- - range: 25
- name: BCR
- desc: Bunch counter reset
- - range: 24
- name: L1A
- desc: Level 1 Accept
- - range: 21..0
- name: STEP_COUNTER
- desc: Step counter value
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range: 26..15
- name: BCID_ONBCR
- type: W
- desc: BCID is set to this value when BCR arrives
- - range: 14
- name: BUSY_OUTPUT_STATUS
- type: R
- desc: Actual status of the BUSY LEMO output signal
- - range: 13
- name: ECR_BCR_SWAP
- default: 0
- desc: ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
- - range: 12
- name: BUSY_OUTPUT_INHIBIT
- default: 0
- desc: forces the Busy LEMO output to BUSY-OFF
- - range: 11
- name: TOHOST_RST
- desc: reset toHost in ttc decoder
- default: 0
- - range: 10
- name: TT_BCH_EN
- desc: trigger type enable / disable for TTC-ToHost
- default: 1
- - range: 9..2
- name: XL1ID_SW
- desc: set XL1ID value, the value to be set by XL1ID_RST signal
- default: 0x00
- - range: 1
- name: XL1ID_RST
- desc: giving a trigger signal to reset XL1ID value
- default: 0
- - range: 0
- name: MASTER_BUSY
- desc: L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range: 15..5
- name: TH_FF_COUNT
- desc: ToHostData Fifo counts
- - range: 4
- name: TH_FF_FULL
- desc: ToHostData Fifo status 1:full 0:not full
- - range: 3
- name: TH_FF_EMPTY
- desc: ToHostData Fifo status 1:empty 0:not empty
- - range: 2..0
- name: TTC_BIT_ERR
- desc: double bit, single bit and comm error in TTC data
-
-TTC_BUSY_ACCEPTED_G:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- entries:
- - name: TTC_BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
- type_name: TTC_BUSY_ACCEPTED
- bitfield:
- - range: 56..0
-
-
-
-TTC_DELAY:
- number: 48
- type: W
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Controls the TTC Fanout delay values
- bitfield:
- - range: 3..0
- default: 0
-
-XOFF_BUSYControlsAndMonitors:
- group: XOFF
- desc: XOFF Controls and Monitors, see table 2 of Busy specs manual
- endpoints: 0, 1
- entries:
- - name: XOFF_FM_CH_FIFO_THRESH_LOW
- desc: Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xB
- - range: 43..40
- name: CH10
- default: 0xB
- - range: 39..36
- name: CH09
- default: 0xB
- - range: 35..32
- name: CH08
- default: 0xB
- - range: 31..28
- name: CH07
- default: 0xB
- - range: 27..24
- name: CH06
- default: 0xB
- - range: 23..20
- name: CH05
- default: 0xB
- - range: 19..16
- name: CH04
- default: 0xB
- - range: 15..12
- name: CH03
- default: 0xB
- - range: 11..8
- name: CH02
- default: 0xB
- - range: 7..4
- name: CH01
- default: 0xB
- - range: 3..0
- name: CH00
- default: 0xB
-
- - name: XOFF_FM_CH_FIFO_THRESH_HIGH
- desc: Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xB
- - range: 43..40
- name: CH10
- default: 0xB
- - range: 39..36
- name: CH09
- default: 0xB
- - range: 35..32
- name: CH08
- default: 0xB
- - range: 31..28
- name: CH07
- default: 0xB
- - range: 27..24
- name: CH06
- default: 0xB
- - range: 23..20
- name: CH05
- default: 0xB
- - range: 19..16
- name: CH04
- default: 0xB
- - range: 15..12
- name: CH03
- default: 0xB
- - range: 11..8
- name: CH02
- default: 0xB
- - range: 7..4
- name: CH01
- default: 0xB
- - range: 3..0
- name: CH00
- default: 0xB
-
- - name: XOFF_FM_LOW_THRESH_CROSSED
- desc: FIFO filled beyond the low threshold, 1 bit per channel
- type: R
- bitfield:
- - range: 11..0
- - name: XOFF_FM_HIGH_THRESH
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- desc: Writing this register will clear all CROSS_LATCHED bits
- type: T
- value: 1
- - range: 23..12
- type: R
- name: CROSS_LATCHED
- desc: FIFO filled beyond the high threshold, 1 latch bit per channel
- - range: 11..0
- type: R
- name: CROSSED
- desc: FIFO filled beyond the high threshold, 1 bit per channel
-
- - name: XOFF_FM_SOFT_XOFF
- type: W
- desc: Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
- bitfield:
- - range: 23..0
-
- - name: XOFF_ENABLE
- type: W
- desc: Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
- bitfield:
- - range: 23..0
-
- - name: DMA_BUSY_STATUS
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR_LATCH
- desc: Any write to this register clears TOHOST_BUSY_LATCHED
- - range: 4
- type: W
- name: ENABLE
- desc: Enable the DMA buffer on the server as a source of busy
- default: 0
- - range: 3
- type: R
- name: TOHOST_BUSY_LATCHED
- desc: A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- - range: 2
- type: R
- name: FROMHOST_BUSY_LATCHED
- desc: A fromhost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- - range: 1
- type: R
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- - range: 0
- type: R
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
- - name: FM_BUSY_CHANNEL_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- type: T
- value: 1
- desc: Any write to this register will clear the BUSY_LATCHED bits
- - range: 23..12
- type: R
- name: BUSY_LATCHED
- desc: one Indicates that the given FULL mode channel has received BUSY-ON
- - range: 11..0
- type: R
- name: BUSY
- desc: one Indicates that the given FULL mode channel is currently in BUSY state
-
- - name: BUSY_MAIN_OUTPUT_FIFO_THRESH
- type: W
- bitfield:
- - range: 24
- name: BUSY_ENABLE
- desc: Enable busy generation if thresholds are crossed
- default: 0
- - range: 23..12
- name: LOW
- desc: Low, Negate threshold of busy generation from main output fifo
- default: 0x3FF
- - range: 11..0
- name: HIGH
- desc: High, Assert threshold of busy generation from main output fifo
- default: 0x4FF
-
- - name: BUSY_MAIN_OUTPUT_FIFO_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCHED
- value: 1
- desc: Any write to this register will clear the
- type: T
- - range: 2
- type: R
- name: HIGH_THRESH_CROSSED_LATCHED
- desc: Main output fifo has been full beyond HIGH THRESHOLD, write to clear
- - range: 1
- type: R
- name: HIGH_THRESH_CROSSED
- desc: Main output fifo is full beyond HIGH THRESHOLD
- - range: 0
- type: R
- name: LOW_THRESH_CROSSED
- desc: Main output fifo is full beyond LOW THRESHOLD
- - ref: ELINK_BUSY_ENABLE
-
-
-ELINK_BUSY_ENABLE:
- number: 24
- endpoints: 0
- type: W
- entries:
- - name: ELINK_BUSY_ENABLE
- format_name: ELINK_BUSY_ENABLE{index:02}
- type_name: ELINK_BUSY_ENABLE
- desc: Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- bitfield:
- - range: 56..0
- default: 0
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
-
- - name: HK_MON_FMC
- type: W
- bitfield:
- - range: 1
- name: SI5345_LOL
- desc: Si5345 Loss Of Lock pin
- - range: 0
- name: SI5345_INTR
- desc: Si5345 Interrupt flagging chip change of status
-
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_SEL
- default: 0x1
- desc: |
- 1: LCLK
- 0: TTC
- - range: 2..1
- type: R
- name: MAIN_INPUT
- desc: |
- Main MMCM Oscillator Input
- 2: LCLK fixed
- 1: TTC fixed
- 0: selectable
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL-711 locked
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
-
- - name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
-
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST_4
- offset: 0x0800
- type: T
- value: 1
- bitfield:
- - range: any
- desc: Fire a test MSIx interrupt \#4
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
-
- - name: TACH_CNT
- type: R
- desc: Readout of the Fan tachometer speed of the BNL712 board
- bitfield:
- - range: 19..0
-
-Generators:
- group: GEN
- desc: Specific registers for Hardware based Generators
- endpoints: 0
- generate: EMU_GENERATE_REGS
- entries:
-
- - ref: FELIG_DATA_GEN_CONFIG_ARR
- offset: 0x20
- - ref: FELIG_ELINK_CONFIG_ARR
- - ref: FELIG_ELINK_ENABLE_ARR
-
- - name: FELIG_GLOBAL_CONTROL
- type: W
- bitfield:
- - range: 63..36
- name: FAKE_L1A_RATE
- default: 0
- desc: Sets the internal fake L1 trigger rate. [25ns/LSB]
- - range: 35..14
- name: PICXO_OFFSET_PPM
- default: 0
- desc: When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
- - range: 12..12
- name: TRACK_DATA
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 11..11
- name: RXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 10..10
- name: TXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 9..9
- name: AUTO_RESET
- default: 0
- desc: FELIG GT core control. If set the GT core automatically resets on data error.
- - range: 8..8
- name: PICXO_RESET
- default: 0
- desc: FELIG GT core control. Manual PICXO reset.
- - range: 7..7
- name: GTTX_RESET
- default: 0
- desc: FELIG GT core control. Manual GT TX reset
- - range: 6..6
- name: CPLL_RESET
- default: 0
- desc: FELIG GT core control. Manual CPLL reset.
- - range: 5..0
- name: X3_X4_OUTPUT_SELECT
- default: 0
- desc: X3/X4 SMA output source select.
-
- - ref: FELIG_LANE_CONFIG_ARR
- - ref: FELIG_MON_TTC_0_ARR
- - ref: FELIG_MON_TTC_1_ARR
- - ref: FELIG_MON_COUNTERS_ARR
- - ref: FELIG_MON_FREQ_ARR
-
- - name: FELIG_MON_FREQ_GLOBAL
- type: W
- bitfield:
- - range: 63..32
- name: XTAL_100MHZ
- default: 0
- desc: FELIG local oscillator frequency[Hz].
- - range: 31..0
- name: CLK_41_667MHZ
- desc: FELIG PCIE MGTREFCLK frequency[Hz].
-
- - ref: FELIG_MON_L1A_ID_ARR
- - ref: FELIG_MON_PICXO_ARR
-
- - name: FELIG_RESET
- type: W
- bitfield:
- - range: 63..48
- name: LB_FIFO
- default: 0
- desc: One bit per lane. When set to 1, resets all loopback FIFOs.
- - range: 47..24
- name: FRAMEGEN
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG link checking logic.
- - range: 23..0
- name: LANE
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG lane logic.
-
- - name: FELIG_RX_SLIDE_RESET
- type: W
- bitfield:
- - range: 23..0
- default: 0
- desc: One bit per lane. When set to 1, resets the gbt rx slide counter.
-
- - name: FMEMU_EVENT_INFO
- type: W
- offset: 0x1800
- bitfield:
- - range: 63..32
- name: L1ID
- default: 0
- desc: 32b field to show L1ID
- - range: 31..0
- name: BCID
- default: 0
- desc: 32b field to show BCID
-
- - name: FMEMU_COUNTERS
- type: W
- bitfield:
- - range: 63..48
- name: WORD_CNT
- default: 32
- desc: Number of 32b words in one chunk
- - range: 47..32
- name: IDLE_CNT
- default: 3
- desc: Minimum number of idles between chunks
- - range: 31..16
- name: L1A_CNT
- default: 256
- desc: Number of chunks to send if not in TTC mode
- - range: 15..8
- name: BUSY_TH_HIGH
- default: 20
- desc: Assert BUSY-ON above this threshold
- - range: 7..0
- name: BUSY_TH_LOW
- default: 15
- desc: De-assert BUSY-ON below this threshold
-
- - name: FMEMU_CONTROL
- type: W
- bitfield:
- - range: 63..56
- type: W
- name: L1A_BITNR
- default: 32
- desc: Bitfield for L1A in TTC frame
- - range: 55..48
- type: W
- name: XONXOFF_BITNR
- default: 32
- desc: Bitfield for Xon/Xoff in TTC frame
- - range: 47..47
- type: W
- name: EMU_START
- default: 0
- desc: Start emulator functionality
- - range: 46..46
- type: W
- name: TTC_MODE
- default: 0
- desc: Control the emulator by TTC input or by RegMap (1/0)
- - range: 45..45
- type: W
- name: XONXOFF
- default: 0
- desc: Debug Xon/Xoff functionality (1/0)
- - range: 44..44
- type: W
- name: INLC_CRC32
- default: 0
- desc: |
- 0: No checksum
- 1: Append the data with a CRC32
- - range: 43..43
- type: W
- name: BCR
- default: 0
- desc: Reset BCID to 0
- - range: 42..42
- type: W
- name: ECR
- default: 0
- desc: Reset L1ID to 0
- - range: 41..41
- type: W
- name: DATA_SRC_SEL
- default: 0
- desc: |
- Data source select
- 0: Data input comes from EMURAM
- 1: Data input comes from PCIe
- - range: 40..32
- type: R
- name: INT_STATUS_EMU
- default: 0
- desc: Read internal status emulator
- - range: 31..16
- type: W
- name: FFU_FM_EMU_T
- default: 0
- desc: For Future Use (trigger registers)
- - range: 15..0
- type: W
- name: FFU_FM_EMU_W
- default: 0
- desc: For Future Use (write registers)
-
- - name: FMEMU_RANDOM_RAM_ADDR
- type: W
- desc: Controls the address of the ramblock for the random number generator
- bitfield:
- - range: 9..0
- - name: FMEMU_RANDOM_RAM
- type: W
- bitfield:
- - range: any
- type: T
- name: WE
- value: 1
- desc: Any write to this register (DATA) triggers a write to the ramblock
- - range: 39..16
- name: CHANNEL_SELECT
- value: 0xFFFFFF
- desc: Enable write enable only for the selected channel
- - range: 15..0
- name: DATA
- type: W
- desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
- - name: FMEMU_RANDOM_CONTROL
- type: W
- desc: Controls the random chunk length generator
- bitfield:
- - name: SELECT_RANDOM
- range: 20
- desc: 1 enables the random chunk length, 0 uses a constant chunk length
- default: 0
- - name: SEED
- range: 19..10
- desc: Seed for the random number generator, should not be 0
- default: 0x200
- - name: POLYNOMIAL
- range: 9..0
- desc: POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
- default: 0x240
-
- - name: FMEMU_CONFIG_WRADDR
- type: W
- bitfield:
- - range: 9..0
- value: 0
- desc: write enable for the FMEmu ram block
-
- - name: FMEMU_CONFIG
- type: W
- bitfield:
- - range: any
- type: T
- name: WE
- value: 1
- desc: Any write to register WRDATA triggers a write to the ramblock
- - range: 55..32
- name: CHANNEL_SELECT
- value: 0xFFFFFF
- desc: Enable write enable only for the selected channel
- - range: 31..0
- name: WRDATA
- type: W
- desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
-
-
-#Registers that are replicated 24 times under Generators:
-FELIG_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_DATA_GEN_CONFIG
- format_name: FELIG_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_DATA_GEN_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: USERDATA
- range: 63..48
- default: 0
- desc: Sets static payload word. When PATTERN_SEL=1.
- - name: CHUNK_LENGTH
- range: 47..32
- default: 0
- desc: FELIG data generator chunk-length in bytes.
- - name: RESET
- range: 19..15
- default: 0
- desc: FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- - name: SW_BUSY
- range: 14..10
- default: 0
- desc: FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- - name: DATA_FORMAT
- range: 9..5
- default: 0
- desc: FELIG data generator format. 0:8b10b, 1:direct.
- - name: PATTERN_SEL
- range: 4..0
- default: 0
- desc: FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
-
-FELIG_ELINK_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_CONFIG
- format_name: FELIG_ELINK_CONFIG_{index:02}
- type_name: FELIG_ELINK_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: ENDIAN_MOD
- range: 39..35
- default: 0
- desc: FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- - name: INPUT_WIDTH
- range: 34..30
- default: 0
- desc: FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- - name: OUTPUT_WIDTH
- range: 9..0
- default: 0
- desc: FELIG elink data output width.
-
-FELIG_ELINK_ENABLE_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_ENABLE
- format_name: FELIG_ELINK_ENABLE_{index:02}
- type_name: FELIG_ELINK_ENABLE
- desc: FELIG specific configuration registers
- bitfield:
- - range: 39..0
- default: 0
- desc: FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
-
-FELIG_LANE_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_LANE_CONFIG
- format_name: FELIG_LANE_CONFIG_{index:02}
- type_name: FELIG_LANE_CONFIG
- desc: FELIG specific configuration registers
- bitfield:
- - name: B_CH_BIT_SEL
- range: 63..42
- default: 0
- desc: When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- - name: A_CH_BIT_SEL
- range: 41..35
- default: 0
- desc: Selects the bit from the received FELIX data from which to extract the L1A.
- - name: LB_FIFO_DELAY
- range: 34..30
- default: 0
- desc: When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- - name: ELINK_SYNC
- range: 7..7
- default: 0
- desc: When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- - name: PICXO_OFFEST_EN
- range: 6..6
- default: 0
- desc: FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- - name: PI_HOLD
- range: 5..5
- default: 0
- desc: FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- - name: GBT_LB_ENABLE
- range: 4..4
- default: 0
- desc: FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- - name: GBH_LB_ENABLE
- range: 3..3
- default: 0
- desc: FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- - name: L1A_SOURCE
- range: 2..2
- default: 0
- desc: FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- - name: GBT_EMU_SOURCE
- range: 1..1
- default: 0
- desc: FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- - name: FG_SOURCE
- range: 0..0
- default: 0
- desc: FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
-
-FELIG_MON_TTC_0_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_0
- format_name: FELIG_MON_TTC_0_{index:02}
- type_name: FELIG_MON_TTC_0
- desc: FELIG specific configuration registers
- bitfield:
- - name: L1ID
- range: 63..40
- default: 0
- desc: Live TTC data monitor.
- - name: XL1ID
- range: 39..32
- default: 0
- desc: Live TTC data monitor.
- - name: BCID
- range: 31..20
- default: 0
- desc: Live TTC data monitor.
- - name: RESERVED0
- range: 19..16
- default: 0
- desc: Live TTC data monitor.
- - name: LEN
- range: 15..8
- default: 0
- desc: Live TTC data monitor.
- - name: FMT
- range: 7..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_TTC_1_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_1
- format_name: FELIG_MON_TTC_1_{index:02}
- type_name: FELIG_MON_TTC_1
- desc: FELIG specific configuration registers
- bitfield:
- - name: RESERVED1
- range: 63..48
- default: 0
- desc: Live TTC data monitor.
- - name: TRIGGER_TYPE
- range: 47..32
- default: 0
- desc: Live TTC data monitor.
- - name: ORBIT
- range: 31..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_COUNTERS_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_COUNTERS
- format_name: FELIG_MON_COUNTERS_{index:02}
- type_name: FELIG_MON_COUNTERS
- desc: FELIG specific configuration registers
- bitfield:
- - name: SLIDE_COUNT
- range: 63..32
- default: 0
- desc: Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- - name: FC_ERROR_COUNT
- range: 31..0
- default:
- desc: When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
-
-FELIG_MON_FREQ_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_FREQ
- format_name: FELIG_MON_FREQ_{index:02}
- type_name: FELIG_MON_FREQ
- desc: FELIG specific configuration registers
- bitfield:
- - name: TX
- range: 63..32
- default: 0
- desc: FELIG regenerated TX clock frequency[Hz].
- - name: RX
- range: 31..0
- default: 0
- desc: FELIG recovered RX clock frequency[Hz].
-
-FELIG_MON_L1A_ID_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_L1A_ID
- format_name: FELIG_MON_L1A_ID_{index:02}
- type_name: FELIG_MON_L1A_ID
- desc: FELIG specific configuration registers
- bitfield:
- - range: 31..0
- default: 0
- desc: FELIG's last L1 ID.
-
-FELIG_MON_PICXO_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_PICXO
- format_name: FELIG_MON_PICXO_{index:02}
- type_name: FELIG_MON_PICXO
- desc: FELIG specific configuration registers
- bitfield:
- - name: VLOT
- range: 53..32
- default: 0
- desc: Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- - name: ERROR
- range: 20..0
- default: 0
- desc: Value indicates RX to TX frequency tracking error.
-
-Wishbone:
- desc: Wishbone
- endpoints: 0
- entries:
- - name: WISHBONE_CONTROL
- type: W
- bitfield:
- - range: 32
- name: WRITE_NOT_READ
- desc: wishbone write command wishbone read command
- - range: 31..0
- name: ADDRESS
- desc: Slave address for Wishbone bus
- - name: WISHBONE_WRITE
- type: T
- bitfield:
- - range: any
- type: T
- value: 1
- name: WRITE_ENABLE
- desc: Any write to this register triggers a write to the Wupper to Wishbone fifo
- - range: 32
- name: FULL
- type: R
- - range: 31..0
- name: DATA
- type: W
- - name: WISHBONE_READ
- type: T
- bitfield:
- - range: any
- type: T
- value: 1
- name: READ_ENABLE
- desc: Any write to this register triggers a read from the Wishbone to Wupper fifo
- - range: 32
- name: EMPTY
- type: R
- desc: Indicates that the Wishbone to Wupper fifo is empty
- - range: 31..0
- name: DATA
- type: R
- desc: Wishbone read data
- - name: WISHBONE_STATUS
- type: R
- bitfield:
- - range: 4
- name: INT
- desc: interrupt
- - range: 3
- name: RETRY
- desc: Interface is not ready to accept data cycle should be retried
- - range: 2
- name: STALL
- desc: When pipelined mode slave can't accept additional transactions in its queue
- - range: 1
- name: ACKNOWLEDGE
- desc: Indicates the termination of a normal bus cycle
- - range: 0
- name: ERROR
- desc: Address not mapped by the crossbar
diff --git a/sources/templates/yaml/registers-4.8.yaml b/sources/templates/yaml/registers-4.8.yaml
deleted file mode 100644
index 5ed82fd457811d8c59b68db30eba578be1182208..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-4.8.yaml
+++ /dev/null
@@ -1,2797 +0,0 @@
-Registers:
- version: '4.8'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: TTCBUSYControlsAndMonitors
- record_name: register_map_ttc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: XOFF_BUSYControlsAndMonitors
- record_name: register_map_xoff_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: Generators
- record_name: register_map_generators
- bitfield:
- - range: 0..0
- type: R
- - name: Wishbone
- record_name: wishbone_monitor
- bitfield:
- - range: 0..0
- type: R
-
-#Bar0 contains the registers dedicated to Wupper. Please only edit registers in Bar2
-#Registers in this group will not be generated with WupperCodeGen
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_FIFO_FLUSH
- type: T
- bitfield:
- - range: any
- desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
- - name: BUSY_THRESHOLD_ASSERT
- type: W
- desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
- default: 0x6400000
- bitfield:
- - range: 63..0
-
- - name: BUSY_THRESHOLD_NEGATE
- type: W
- desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
- default: 0x6E00000
- bitfield:
- - range: 63..0
-
- - name: BUSY_STATUS
- type: R
- bitfield:
- - range: 1
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- - range: 0
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
- - name: PC_PTR_GAP
- type: W
- desc: This is the minimum value that the pc_pointer in a descriptor has to decrease in order to flip the evencycle_pc bit
- default: 0x1000000
- bitfield:
- - range: 63..0
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: SW_POINTER
- desc: Pointer controlled by the software, indicating read or write status for circular DMA
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: FROMHOST
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: FW_POINTER
- desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
-
-
-#Bar1 contains the registers dedicated to the Wupper interrupg controller.
-#Please only edit registers in Bar2.
-#Registers in this group will not be generated with WupperCodeGen
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 16
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-#Bar 2 contains application specific registers, used in the example application.
-#Registers in this group (and it's referenced subroups) will be generated with
-#WupperCodeGen for wupper Firmware, Software and Documentation
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x5000
- - ref: GBTWrapperControls
- offset: 0x6000
- - ref: GBTWrapperMonitors
- offset: 0x7000
- - ref: TTCBUSYControlsAndMonitors
- offset: 0x8000
- - ref: XOFF_BUSYControlsAndMonitors
- offset: 0x8800
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x9000
- - ref: Generators
- offset: 0xA000
- - ref: Wishbone
- offset: 0xC000
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned({{ tree.version|version }},16))
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: BOARD_ID_SVN
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- desc: Board ID SVN Revision
-
- - name: GIT_COMMIT_TIME
- bitfield:
- - range: 39..0
- value: COMMIT_DATETIME
- desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_TAG
- bitfield:
- - range: 63..0
- value: GIT_TAG(63 downto 0)
- desc: String containing the current GIT TAG
-
- - name: GIT_COMMIT_NUMBER
- bitfield:
- - range: 31..0
- value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
- desc: Number of GIT commits after current GIT_TAG
-
- - name: GIT_HASH
- bitfield:
- - range: 31..0
- value: GIT_HASH(159 downto 128)
- desc: Short GIT hash (32 bit)
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): VC-709
- - 710 (0x2c6): HTG-710
- - 711 (0x2c7): BNL-711
- - 712 (0x2c8): BNL-712
-
- - name: GBT_MAPPING
- bitfield:
- - range: 7..0
- desc: |
- CXP-to-GBT mapping:
- 0: NORMAL CXP1 1-12 CXP2 13-24
- 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST
- type: R
- bitfield:
- - range: 1
- type: R
- name: GENERATE_TTC_EMU
- desc: 1 when TTC emulator is generated
- - range: 0
- type: R
- name: TTC_TEST_MODE
- desc: 1 when TTC Test mode is anabled
-
- - name: CR_INTERNAL_LOOPBACK_MODE
- type: R
- bitfield:
- - range: 0
- desc: 1 when Central Router internal loopback mode is enabled
-
- - ref: INCLUDE_EGROUPS
-
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: DEBUG_MODE
- type: R
- bitfield:
- - range: 0
- desc: |
- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- bitfield:
- - range: 3..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
- 3: FEI4 mode
- 4: ITK Pixel
- 5: ITK Strip
- 6: FELIG
- 7: FULL mode emulator
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
- - name: BLOCKSIZE
- type: R
- desc: Number of bytes in a block
- bitfield:
- - range: 15..0
-
- - name: PCIE_ENDPOINT
- type: R
- desc: Indicator of the PCIe endpoint on BNL71x cards with two endpoints. 0 or 1
- bitfield:
- - range: 0
- value: std_logic_vector(to_unsigned(PCIE_ENDPOINT, 1))
-
- - name: CHUNK_TRAILER_32B
- type: R
- desc: Indicator that the chunk trailer is in the new 32-bit format
- bitfield:
- - range: 0
-
-INCLUDE_EGROUPS:
- number: 7
- entries:
- - format_name: INCLUDE_EGROUP_{index}
- name: INCLUDE_EGROUP
- type_name: INCLUDE_EGROUP
- type: R
- bitfield:
- - range: 8
- name: FROMHOST_02
- desc: FromHost EPROC02 is included in this EGROUP
- - range: 7
- name: FROMHOST_04
- desc: FromHost EPROC04 is included in this EGROUP
- - range: 6
- name: FROMHOST_08
- desc: FromHost EPROC8 is included in this EGROUP
- - range: 5
- name: FROMHOST_HDLC
- desc: FromHost HDLC is included in this EGROUP
- - range: 4
- name: TOHOST_02
- desc: ToHost EPROC02 is included in this EGROUP
- - range: 3
- name: TOHOST_04
- desc: ToHost EPROC04 is included in this EGROUP
- - range: 2
- name: TOHOST_08
- desc: ToHost EPROC08 is included in this EGROUP
- - range: 1
- name: TOHOST_16
- desc: ToHost EPROC16 is included in this EGROUP
- - range: 0
- name: TOHOST_HDLC
- desc: ToHost HDLC is included in this EGROUP
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: IC_FROMHOST_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- - name: CR_FALLBACK_OPTIONS
- desc: Julias personal register with Hello Kitty options
- type: W
- bitfield:
- - range: 63..0
-
- - name: CR_TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - name: CR_REVERSE_10B
- desc: Reverse 10-bit word of elink data
- type: W
- bitfield:
- - range: 1
- name: FROMHOST
- default: 1
- desc: |
- 1: Serialize 10-bit word in FromHost EPROCS MSB first
- 0: Serialize 10-bit word in FromHost EPROCS LSB first
- - range: 0
- name: TOHOST
- default: 1
- desc: |
- 1: Receive 10-bit word in ToHost EPROCS, MSB first
- 0: Receive 10-bit word in ToHost EPROCS, LSB first
-
- - name: CR_LTDB_TTC_DELAY
- desc: Controls TTC BCR delay in LTDB mode firmware
- type: W
- bitfield:
- - range: 7
- name: EGROUP4_EPATH6
- default: 1
- desc: |
- Egroup 4, Epath 6
- 1: Half a clock delay
- 0: no delay
- - range: 6
- name: EGROUP4_EPATH5
- default: 1
- desc: |
- Egroup 4, Epath 5
- 1: Half a clock delay
- 0: no delay
- - range: 5
- name: EGROUP4_EPATH4
- default: 1
- desc: |
- Egroup 4, Epath 4
- 1: Half a clock delay
- 0: no delay
- - range: 4
- name: EGROUP4_EPATH3
- default: 1
- desc: |
- Egroup 4, Epath 3
- 1: Half a clock delay
- 0: no delay
- - range: 3
- name: EGROUP4_EPATH0
- default: 1
- desc: |
- Egroup 4, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 2
- name: EGROUP3
- default: 1
- desc: |
- Egroup 3, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 1
- name: EGROUP2
- default: 1
- desc: |
- Egroup 2, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 0
- name: EGROUP1
- default: 1
- desc: |
- Egroup 1, Epath 0
- 1: Half a clock delay
- 0: no delay
-# - ref: CR_XOFF_CTRL
-# offset: 0x2800
-# desc: Configure FromHost Xoff
-
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x3000
- - name: CR_STATIC_CONFIGURATION
- type: R
- bitfield:
- - range: 0
- - ref: CR_DEFAULT_EPROC_ENA_G
- - ref: CR_DEFAULT_EPROC_ENCODING_G
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
-
-CR_GBT_CTRL:
- number: 24
- bitfield:
- - range: 50..0
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- entries:
- - ref: EGROUP_TOHOST
- - ref: EGROUP_FROMHOST
-
-EGROUP_TOHOST:
- number: 7
- format_name: GBT{index:02}
- name: GBT
- entries:
- - name: TOHOST
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_TOHOST_EGROUP_CTRL
- bitfield:
- - range: 58..51
- name: INSTANT_TIMEOUT_ENA
- default: 0x0
- desc: instantly initiate a timeout for the given epath
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..31
- name: MAX_CHUNK_LEN
- default: MAX_CHUNK_LEN_array
- desc: set the maximum length of a chunk, 0 disables truncation
- - range: 30..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- default:
- - PATH_ENCODING_array(0)
- - PATH_ENCODING_array(1)
- - PATH_ENCODING_array(2)
- - PATH_ENCODING_array(3)
- - PATH_ENCODING_array(4)
- - PATH_ENCODING_array(5)
- - PATH_ENCODING_array(6)
-
- - range: 14..0
- name: EPROC_ENA
- desc: Enable bits per EPROC
- default:
- - EPROC_ENA_bits_array(0)
- - EPROC_ENA_bits_array(1)
- - EPROC_ENA_bits_array(2)
- - EPROC_ENA_bits_array(3)
- - EPROC_ENA_bits_array(4)
- - EPROC_ENA_bits_array(5)
- - EPROC_ENA_bits_array(6)
-
-EGROUP_FROMHOST:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FROMHOST
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_FROMHOST_EGROUP_CTRL
- bitfield:
- - range: 54..47
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 46..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- greater than 3: TTC mode, see CentralRouter doc
- default:
- - FROMHOST_PATH_ENCODING_array(0)
- - FROMHOST_PATH_ENCODING_array(1)
- - FROMHOST_PATH_ENCODING_array(2)
- - FROMHOST_PATH_ENCODING_array(3)
- - FROMHOST_PATH_ENCODING_array(4)
- - FROMHOST_PATH_ENCODING_array(5)
- - FROMHOST_PATH_ENCODING_array(6)
- - range: 14..0
- desc: Enable bits per EPROC
- name: EPROC_ENA
-
-IC_FIFOS:
- number: 24
- format_name: IC_FROMHOST_TOHOST_FIFOS
- entries:
- - name: FROMHOST
- format_name: IC_FROMHOST_FIFO_{index:02}
- type_name: IC_FROMHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_FROMHOST_FIFO({index}).FULL
- name: WE
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TOHOST
- format_name: IC_TOHOST_FIFO_{index:02}
- type_name: IC_TOHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_TOHOST_FIFO({index}).EMPTY
- name: RE
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 7
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 6
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 5
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 4
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 9
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 8
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 7
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 6
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
-
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- entries:
- - name: TOHOST
- type_name: CR_TOHOST_GBT_MON
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 58
- name: CROUTFIFO_PROG_FULL
- - range: 57
- name: WMFIFO_FULL
- - range: 56
- name: MINI_EGROUP_ALMOST_FULL
- - range: 55..48
- name: EPATH6_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP6
- - range: 47..40
- name: EPATH5_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP5
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
- - name: FROMHOST
- type_name: CR_FROMHOST_GBT_MON
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 40
- name: MINI_EGROUP_ALMOST_FULL
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
-
-CR_DEFAULT_EPROC_ENA_G:
- desc: Static CR default enable bits
- endpoints: 0,1
- number: 8
- type: R
- entries:
- - name: ENABLE
- format_name: CR_DEFAULT_EPROC_ENA{index}
- type_name: CR_DEFAULT_EPROC_ENA
- bitfield:
- - range: 14..0
-
-
-CR_DEFAULT_EPROC_ENCODING_G:
- desc: Static CR default encoding bits
- endpoints: 0,1
- number: 8
- type: R
- entries:
- - name: ENCODING
- format_name: CR_DEFAULT_EPROC_ENCODING{index}
- type_name: CR_DEFAULT_EPROC_ENCODING
- bitfield:
- - range: 15..0
-
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0, 1
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 63..48
- name: RDDATA
- type: R
- desc: read data bus
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 0
- desc: write enable for the full mode emulator ram block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 35..0
- desc: read emu ram data
-
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
- - ref: PATH_HAS_STREAM_ID
-
-PATH_HAS_STREAM_ID:
- number: 24
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- entries:
- - name: TOHOST
- format_name: LINK_{index:02}_HAS_STREAM_ID
- type_name: HAS_STREAM_ID
- type: W
- bitfield:
- - range: 55..48
- name: EGROUP6
- default: 0x0
- desc: EPATH (Wide mode) is associated with a STREAM ID
- - range: 47..40
- name: EGROUP5
- default: 0x0
- desc: EPATH (Wide mode) is associated with a STREAM ID
- - range: 39..32
- name: EGROUP4
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 31..24
- name: EGROUP3
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 23..16
- name: EGROUP2
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 15..8
- name: EGROUP1
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 7..0
- name: EGROUP0
- default: 0x0
- desc: EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_CHANNEL_DISABLE
- offset: 0x0400
- bitfield:
- - range: 47..0
- desc: Disable selected GBT or FULL mode channel
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE_SELECT
- offset: 0x0480
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_RXSLIDE_MANUAL
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_TXUSRRDY
- desc: TxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_RXUSRRDY
- desc: RxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_SOFT_RESET
- desc: SOFT_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTTX_RESET
- desc: GTTX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTRX_RESET
- desc: GTRX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 59..48
- name: QPLL_RESET
- desc: QPLL_RESET [11:0]
- - range: 47..0
- name: CPLL_RESET
- desc: CPLL_RESET [47:0]
-
- - name: GBT_SOFT_TX_RESET
- offset: 0x0500
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_SOFT_RX_RESET
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_ODD_EVEN
- desc: OddEven [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_TOPBOT
- desc: TopBot [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_TC_DLY_VALUE3
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [143:96]
-
- - name: GBT_TX_TC_DLY_VALUE4
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [191:144]
-
- - name: GBT_DATA_TXFORMAT1
- desc: DATA_TXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_TXFORMAT2
- desc: DATA_TXFORMAT [95:48]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT1
- desc: DATA_RXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT2
- desc: DATA_RXFORMAT [95:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_RESET
- desc: TX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_RESET
- desc: RX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_METHOD
- desc: TX time domain crossing method [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUTMUX_SEL
- desc: Descrambler output MUX selection [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TC_EDGE
- desc: Sampling edge selection for TX domain crossing [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for transmitter of GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_RXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for the receiver of the GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
- - name: GBT_TOHOST_FANOUT
- offset: 0x0700
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_TOFRONTEND_FANOUT
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- desc: TX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXRESET_DONE
- desc: RX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXFSMRESET_DONE
- desc: TX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXFSMRESET_DONE
- desc: RX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_LOCK
- bitfield:
- - range: 59..48
- name: QPLL_LOCK
- desc: QPLL LOCK [11:0]
- - range: 47..0
- name: CPLL_LOCK
- desc: CPLL LOCK [47:0]
-
- - name: GBT_RXCDR_LOCK
- desc: RX CDR LOCK [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CLK_SAMPLED
- desc: clk sampled [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_HEADER
- desc: RX IS HEADER [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_DATA
- desc: RX IS DATA [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_HEADER_FOUND
- desc: RX HEADER FOUND [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUT_MUX_STATUS
- desc: GBT output mux status [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ERROR
- desc: Error flags [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GBT_TOPBOT_C
- desc: TopBot_c [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-TTCBUSYControlsAndMonitors:
- group: TTCBUSY
- desc: TTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: TTC_BUSY_ACCEPTED_G
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 2
- name: FULL
- type: R
- desc: TTC Emulator memory full indication
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
-
- - ref: TTC_DELAY
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the BUSY Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
- - name: TTC_EMU_CONTROL
- type: W
- bitfield:
- - range: any
- name: WE
- type: T
- desc: Any write to this register executes a write enable
- value: 1
- - range: 35
- name: LAST_LINE
- desc: Last line of the sequence
- - range: 34
- name: REPEAT
- desc: Repeat the sequence
- - range: 32
- name: BROADCAST5
- desc: Broadcast 5
- - range: 31
- name: BROADCAST4
- desc: Broadcast 4
- - range: 30
- name: BROADCAST3
- desc: Broadcast 3
- - range: 29
- name: BROADCAST2
- desc: Broadcast 2
- - range: 28
- name: BROADCAST1
- desc: Broadcast 1
- - range: 27
- name: BROADCAST0
- desc: Broadcast 0
- - range: 26
- name: ECR
- desc: Event counter reset
- - range: 25
- name: BCR
- desc: Bunch counter reset
- - range: 24
- name: L1A
- desc: Level 1 Accept
- - range: 21..0
- name: STEP_COUNTER
- desc: Step counter value
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range: 26..15
- name: BCID_ONBCR
- type: W
- desc: BCID is set to this value when BCR arrives
- - range: 14
- name: BUSY_OUTPUT_STATUS
- type: R
- desc: Actual status of the BUSY LEMO output signal
- - range: 13
- name: ECR_BCR_SWAP
- default: 0
- desc: ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
- - range: 12
- name: BUSY_OUTPUT_INHIBIT
- default: 0
- desc: forces the Busy LEMO output to BUSY-OFF
- - range: 11
- name: TOHOST_RST
- desc: reset toHost in ttc decoder
- default: 0
- - range: 10
- name: TT_BCH_EN
- desc: trigger type enable / disable for TTC-ToHost
- default: 1
- - range: 9..2
- name: XL1ID_SW
- desc: set XL1ID value, the value to be set by XL1ID_RST signal
- default: 0x00
- - range: 1
- name: XL1ID_RST
- desc: giving a trigger signal to reset XL1ID value
- default: 0
- - range: 0
- name: MASTER_BUSY
- desc: L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range: 15..5
- name: TH_FF_COUNT
- desc: ToHostData Fifo counts
- - range: 4
- name: TH_FF_FULL
- desc: ToHostData Fifo status 1:full 0:not full
- - range: 3
- name: TH_FF_EMPTY
- desc: ToHostData Fifo status 1:empty 0:not empty
- - range: 2..0
- name: TTC_BIT_ERR
- desc: double bit, single bit and comm error in TTC data
-
-TTC_BUSY_ACCEPTED_G:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- entries:
- - name: TTC_BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
- type_name: TTC_BUSY_ACCEPTED
- bitfield:
- - range: 56..0
-
-
-
-TTC_DELAY:
- number: 48
- type: W
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Controls the TTC Fanout delay values
- bitfield:
- - range: 3..0
- default: 0
-
-XOFF_BUSYControlsAndMonitors:
- group: XOFF
- desc: XOFF Controls and Monitors, see table 2 of Busy specs manual
- endpoints: 0, 1
- entries:
- - name: XOFF_FM_CH_FIFO_THRESH_LOW
- desc: Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xB
- - range: 43..40
- name: CH10
- default: 0xB
- - range: 39..36
- name: CH09
- default: 0xB
- - range: 35..32
- name: CH08
- default: 0xB
- - range: 31..28
- name: CH07
- default: 0xB
- - range: 27..24
- name: CH06
- default: 0xB
- - range: 23..20
- name: CH05
- default: 0xB
- - range: 19..16
- name: CH04
- default: 0xB
- - range: 15..12
- name: CH03
- default: 0xB
- - range: 11..8
- name: CH02
- default: 0xB
- - range: 7..4
- name: CH01
- default: 0xB
- - range: 3..0
- name: CH00
- default: 0xB
-
- - name: XOFF_FM_CH_FIFO_THRESH_HIGH
- desc: Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xB
- - range: 43..40
- name: CH10
- default: 0xB
- - range: 39..36
- name: CH09
- default: 0xB
- - range: 35..32
- name: CH08
- default: 0xB
- - range: 31..28
- name: CH07
- default: 0xB
- - range: 27..24
- name: CH06
- default: 0xB
- - range: 23..20
- name: CH05
- default: 0xB
- - range: 19..16
- name: CH04
- default: 0xB
- - range: 15..12
- name: CH03
- default: 0xB
- - range: 11..8
- name: CH02
- default: 0xB
- - range: 7..4
- name: CH01
- default: 0xB
- - range: 3..0
- name: CH00
- default: 0xB
-
- - name: XOFF_FM_LOW_THRESH_CROSSED
- desc: FIFO filled beyond the low threshold, 1 bit per channel
- type: R
- bitfield:
- - range: 11..0
- - name: XOFF_FM_HIGH_THRESH
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- desc: Writing this register will clear all CROSS_LATCHED bits
- type: T
- value: 1
- - range: 23..12
- type: R
- name: CROSS_LATCHED
- desc: FIFO filled beyond the high threshold, 1 latch bit per channel
- - range: 11..0
- type: R
- name: CROSSED
- desc: FIFO filled beyond the high threshold, 1 bit per channel
-
- - name: XOFF_FM_SOFT_XOFF
- type: W
- desc: Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
- bitfield:
- - range: 23..0
-
- - name: XOFF_ENABLE
- type: W
- desc: Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
- bitfield:
- - range: 23..0
-
- - name: DMA_BUSY_STATUS
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR_LATCH
- desc: Any write to this register clears TOHOST_BUSY_LATCHED
- - range: 4
- type: W
- name: ENABLE
- desc: Enable the DMA buffer on the server as a source of busy
- default: 0
- - range: 3
- type: R
- name: TOHOST_BUSY_LATCHED
- desc: A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- - range: 2
- type: R
- name: FROMHOST_BUSY_LATCHED
- desc: A fromhost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- - range: 1
- type: R
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- - range: 0
- type: R
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
- - name: FM_BUSY_CHANNEL_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- type: T
- value: 1
- desc: Any write to this register will clear the BUSY_LATCHED bits
- - range: 23..12
- type: R
- name: BUSY_LATCHED
- desc: one Indicates that the given FULL mode channel has received BUSY-ON
- - range: 11..0
- type: R
- name: BUSY
- desc: one Indicates that the given FULL mode channel is currently in BUSY state
-
- - name: BUSY_MAIN_OUTPUT_FIFO_THRESH
- type: W
- bitfield:
- - range: 24
- name: BUSY_ENABLE
- desc: Enable busy generation if thresholds are crossed
- default: 0
- - range: 23..12
- name: LOW
- desc: Low, Negate threshold of busy generation from main output fifo
- default: 0x3FF
- - range: 11..0
- name: HIGH
- desc: High, Assert threshold of busy generation from main output fifo
- default: 0x4FF
-
- - name: BUSY_MAIN_OUTPUT_FIFO_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCHED
- value: 1
- desc: Any write to this register will clear the
- type: T
- - range: 2
- type: R
- name: HIGH_THRESH_CROSSED_LATCHED
- desc: Main output fifo has been full beyond HIGH THRESHOLD, write to clear
- - range: 1
- type: R
- name: HIGH_THRESH_CROSSED
- desc: Main output fifo is full beyond HIGH THRESHOLD
- - range: 0
- type: R
- name: LOW_THRESH_CROSSED
- desc: Main output fifo is full beyond LOW THRESHOLD
- - ref: ELINK_BUSY_ENABLE
-
-
-ELINK_BUSY_ENABLE:
- number: 24
- endpoints: 0
- type: W
- entries:
- - name: ELINK_BUSY_ENABLE
- format_name: ELINK_BUSY_ENABLE{index:02}
- type_name: ELINK_BUSY_ENABLE
- desc: Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- bitfield:
- - range: 56..0
- default: 0
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
-
- - name: HK_MON_FMC
- type: W
- bitfield:
- - range: 1
- name: SI5345_LOL
- desc: Si5345 Loss Of Lock pin
- - range: 0
- name: SI5345_INTR
- desc: Si5345 Interrupt flagging chip change of status
-
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_SEL
- default: 0x1
- desc: |
- 1: LCLK
- 0: TTC
- - range: 2..1
- type: R
- name: MAIN_INPUT
- desc: |
- Main MMCM Oscillator Input
- 2: LCLK fixed
- 1: TTC fixed
- 0: selectable
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL-711 locked
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
-
- - name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
-
-
- - name: SPI_WR
- type: W
- offset: 0x0400
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- name: SPI_WREN
- desc: Any write to this register triggers an SPI Write
- - range: 32
- type: R
- name: SPI_FULL
- desc: SPI FIFO Full
- - range: 31..0
- type: W
- name: SPI_DIN
- desc: SPI WRITE Data
-
- - name: SPI_RD
- type: T
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- name: SPI_RDEN
- desc: Any write to this register pops the last SPI data from the FIFO
- - range: 32
- type: R
- name: SPI_EMPTY
- desc: SPI FIFO Empty
- - range: 31..0
- type: R
- name: SPI_DOUT
- desc: SPI READ Data
-
- - name: I2C_WR
- type: W
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
-
- - name: DEBUG_PORT_GBT
- offset: 0x0500
- type: W
- bitfield:
- - range: 6..0
- desc: Debug GBT data bit N (119..0) on SMA HTGx#3
-
- - name: DEBUG_PORT_CLK
- type: W
- bitfield:
- - range: 3..0
- desc: Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST
- offset: 0x0800
- type: W
- value: 1
- bitfield:
- - name: TRIGGER
- type: T
- range: any
- desc: Fire a test MSIx interrupt set in IRQ
- - name: IRQ
- type: W
- range: 3..0
- desc: Set this field to a value equal to the MSIX interrupt to be fired. The write triggers the interrupt immediately.
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
-
- - name: TACH_CNT
- type: R
- desc: Readout of the Fan tachometer speed of the BNL712 board
- bitfield:
- - range: 19..0
-
- - name: RXUSRCLK_FREQ
- type: W
- bitfield:
- - range: 38
- name: VALID
- type: R
- desc: Indicates that the frequency measurement is valid
- - range: 37..32
- name: CHANNEL
- type: W
- desc: Select the Transceiver channel to measure the clock from.
- - range: 31..0
- name: VAL
- type: R
- desc: Frequency in Hz of the selected channel
-
-
- - name: RXUSRCLK_FREQ
- type: W
- bitfield:
- - range: 38
- name: VALID
- type: R
- desc: Indicates that the frequency measurement is valid
- - range: 37..32
- name: CHANNEL
- type: W
- desc: Select the Transceiver channel to measure the clock from.
- - range: 31..0
- name: VAL
- type: R
- desc: Frequency in Hz of the selected channel
-
-
-Generators:
- group: GEN
- desc: Specific registers for Hardware based Generators
- endpoints: 0
- generate: EMU_GENERATE_REGS
- entries:
-
- - ref: FELIG_DATA_GEN_CONFIG_ARR
- offset: 0x20
- - ref: FELIG_ELINK_CONFIG_ARR
- - ref: FELIG_ELINK_ENABLE_ARR
-
- - name: FELIG_GLOBAL_CONTROL
- type: W
- bitfield:
- - range: 63..36
- name: FAKE_L1A_RATE
- default: 0
- desc: Sets the internal fake L1 trigger rate. [25ns/LSB]
- - range: 35..14
- name: PICXO_OFFSET_PPM
- default: 0
- desc: When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
- - range: 12..12
- name: TRACK_DATA
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 11..11
- name: RXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 10..10
- name: TXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 9..9
- name: AUTO_RESET
- default: 0
- desc: FELIG GT core control. If set the GT core automatically resets on data error.
- - range: 8..8
- name: PICXO_RESET
- default: 0
- desc: FELIG GT core control. Manual PICXO reset.
- - range: 7..7
- name: GTTX_RESET
- default: 0
- desc: FELIG GT core control. Manual GT TX reset
- - range: 6..6
- name: CPLL_RESET
- default: 0
- desc: FELIG GT core control. Manual CPLL reset.
- - range: 5..0
- name: X3_X4_OUTPUT_SELECT
- default: 0
- desc: X3/X4 SMA output source select.
-
- - ref: FELIG_LANE_CONFIG_ARR
- - ref: FELIG_MON_TTC_0_ARR
- - ref: FELIG_MON_TTC_1_ARR
- - ref: FELIG_MON_COUNTERS_ARR
- - ref: FELIG_MON_FREQ_ARR
-
- - name: FELIG_MON_FREQ_GLOBAL
- type: W
- bitfield:
- - range: 63..32
- name: XTAL_100MHZ
- default: 0
- desc: FELIG local oscillator frequency[Hz].
- - range: 31..0
- name: CLK_41_667MHZ
- desc: FELIG PCIE MGTREFCLK frequency[Hz].
-
- - ref: FELIG_MON_L1A_ID_ARR
- - ref: FELIG_MON_PICXO_ARR
-
- - name: FELIG_RESET
- type: W
- bitfield:
- - range: 63..48
- name: LB_FIFO
- default: 0
- desc: One bit per lane. When set to 1, resets all loopback FIFOs.
- - range: 47..24
- name: FRAMEGEN
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG link checking logic.
- - range: 23..0
- name: LANE
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG lane logic.
-
- - name: FELIG_RX_SLIDE_RESET
- type: W
- bitfield:
- - range: 23..0
- default: 0
- desc: One bit per lane. When set to 1, resets the gbt rx slide counter.
-
- - name: FMEMU_EVENT_INFO
- type: W
- offset: 0x1800
- bitfield:
- - range: 63..32
- name: L1ID
- default: 0
- desc: 32b field to show L1ID
- - range: 31..0
- name: BCID
- default: 0
- desc: 32b field to show BCID
-
- - name: FMEMU_COUNTERS
- type: W
- bitfield:
- - range: 63..48
- name: WORD_CNT
- default: 32
- desc: Number of 32b words in one chunk
- - range: 47..32
- name: IDLE_CNT
- default: 3
- desc: Minimum number of idles between chunks
- - range: 31..16
- name: L1A_CNT
- default: 256
- desc: Number of chunks to send if not in TTC mode
- - range: 15..8
- name: BUSY_TH_HIGH
- default: 20
- desc: Assert BUSY-ON above this threshold
- - range: 7..0
- name: BUSY_TH_LOW
- default: 15
- desc: De-assert BUSY-ON below this threshold
-
- - name: FMEMU_CONTROL
- type: W
- bitfield:
- - range: 63..56
- type: W
- name: L1A_BITNR
- default: 32
- desc: Bitfield for L1A in TTC frame
- - range: 55..48
- type: W
- name: XONXOFF_BITNR
- default: 32
- desc: Bitfield for Xon/Xoff in TTC frame
- - range: 47..47
- type: W
- name: EMU_START
- default: 0
- desc: Start emulator functionality
- - range: 46..46
- type: W
- name: TTC_MODE
- default: 0
- desc: Control the emulator by TTC input or by RegMap (1/0)
- - range: 45..45
- type: W
- name: XONXOFF
- default: 0
- desc: Debug Xon/Xoff functionality (1/0)
- - range: 44..44
- type: W
- name: INLC_CRC32
- default: 0
- desc: |
- 0: No checksum
- 1: Append the data with a CRC32
- - range: 43..43
- type: W
- name: BCR
- default: 0
- desc: Reset BCID to 0
- - range: 42..42
- type: W
- name: ECR
- default: 0
- desc: Reset L1ID to 0
- - range: 41..41
- type: W
- name: DATA_SRC_SEL
- default: 0
- desc: |
- Data source select
- 0: Data input comes from EMURAM
- 1: Data input comes from PCIe
- - range: 40..32
- type: R
- name: INT_STATUS_EMU
- default: 0
- desc: Read internal status emulator
- - range: 31..16
- type: W
- name: FFU_FM_EMU_T
- default: 0
- desc: For Future Use (trigger registers)
- - range: 15..0
- type: W
- name: FFU_FM_EMU_W
- default: 0
- desc: For Future Use (write registers)
-
- - name: FMEMU_RANDOM_RAM_ADDR
- type: W
- desc: Controls the address of the ramblock for the random number generator
- bitfield:
- - range: 9..0
- - name: FMEMU_RANDOM_RAM
- type: W
- bitfield:
- - range: any
- type: T
- name: WE
- value: 1
- desc: Any write to this register (DATA) triggers a write to the ramblock
- - range: 39..16
- name: CHANNEL_SELECT
- value: 0xFFFFFF
- desc: Enable write enable only for the selected channel
- - range: 15..0
- name: DATA
- type: W
- desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
- - name: FMEMU_RANDOM_CONTROL
- type: W
- desc: Controls the random chunk length generator
- bitfield:
- - name: SELECT_RANDOM
- range: 20
- desc: 1 enables the random chunk length, 0 uses a constant chunk length
- default: 0
- - name: SEED
- range: 19..10
- desc: Seed for the random number generator, should not be 0
- default: 0x200
- - name: POLYNOMIAL
- range: 9..0
- desc: POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
- default: 0x240
-
-
-#Registers that are replicated 24 times under Generators:
-FELIG_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_DATA_GEN_CONFIG
- format_name: FELIG_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_DATA_GEN_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: USERDATA
- range: 63..48
- default: 0
- desc: Sets static payload word. When PATTERN_SEL=1.
- - name: CHUNK_LENGTH
- range: 47..32
- default: 0
- desc: FELIG data generator chunk-length in bytes.
- - name: RESET
- range: 19..15
- default: 0
- desc: FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- - name: SW_BUSY
- range: 14..10
- default: 0
- desc: FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- - name: DATA_FORMAT
- range: 9..5
- default: 0
- desc: FELIG data generator format. 0:8b10b, 1:direct.
- - name: PATTERN_SEL
- range: 4..0
- default: 0
- desc: FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
-
-FELIG_ELINK_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_CONFIG
- format_name: FELIG_ELINK_CONFIG_{index:02}
- type_name: FELIG_ELINK_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: ENDIAN_MOD
- range: 39..35
- default: 0
- desc: FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- - name: INPUT_WIDTH
- range: 34..30
- default: 0
- desc: FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- - name: OUTPUT_WIDTH
- range: 9..0
- default: 0
- desc: FELIG elink data output width.
-
-FELIG_ELINK_ENABLE_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_ENABLE
- format_name: FELIG_ELINK_ENABLE_{index:02}
- type_name: FELIG_ELINK_ENABLE
- desc: FELIG specific configuration registers
- bitfield:
- - range: 39..0
- default: 0
- desc: FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
-
-FELIG_LANE_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_LANE_CONFIG
- format_name: FELIG_LANE_CONFIG_{index:02}
- type_name: FELIG_LANE_CONFIG
- desc: FELIG specific configuration registers
- bitfield:
- - name: B_CH_BIT_SEL
- range: 63..42
- default: 0
- desc: When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- - name: A_CH_BIT_SEL
- range: 41..35
- default: 0
- desc: Selects the bit from the received FELIX data from which to extract the L1A.
- - name: LB_FIFO_DELAY
- range: 34..30
- default: 0
- desc: When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- - name: ELINK_SYNC
- range: 7..7
- default: 0
- desc: When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- - name: PICXO_OFFEST_EN
- range: 6..6
- default: 0
- desc: FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- - name: PI_HOLD
- range: 5..5
- default: 0
- desc: FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- - name: GBT_LB_ENABLE
- range: 4..4
- default: 0
- desc: FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- - name: GBH_LB_ENABLE
- range: 3..3
- default: 0
- desc: FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- - name: L1A_SOURCE
- range: 2..2
- default: 0
- desc: FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- - name: GBT_EMU_SOURCE
- range: 1..1
- default: 0
- desc: FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- - name: FG_SOURCE
- range: 0..0
- default: 0
- desc: FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
-
-FELIG_MON_TTC_0_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_0
- format_name: FELIG_MON_TTC_0_{index:02}
- type_name: FELIG_MON_TTC_0
- desc: FELIG specific configuration registers
- bitfield:
- - name: L1ID
- range: 63..40
- default: 0
- desc: Live TTC data monitor.
- - name: XL1ID
- range: 39..32
- default: 0
- desc: Live TTC data monitor.
- - name: BCID
- range: 31..20
- default: 0
- desc: Live TTC data monitor.
- - name: RESERVED0
- range: 19..16
- default: 0
- desc: Live TTC data monitor.
- - name: LEN
- range: 15..8
- default: 0
- desc: Live TTC data monitor.
- - name: FMT
- range: 7..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_TTC_1_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_1
- format_name: FELIG_MON_TTC_1_{index:02}
- type_name: FELIG_MON_TTC_1
- desc: FELIG specific configuration registers
- bitfield:
- - name: RESERVED1
- range: 63..48
- default: 0
- desc: Live TTC data monitor.
- - name: TRIGGER_TYPE
- range: 47..32
- default: 0
- desc: Live TTC data monitor.
- - name: ORBIT
- range: 31..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_COUNTERS_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_COUNTERS
- format_name: FELIG_MON_COUNTERS_{index:02}
- type_name: FELIG_MON_COUNTERS
- desc: FELIG specific configuration registers
- bitfield:
- - name: SLIDE_COUNT
- range: 63..32
- default: 0
- desc: Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- - name: FC_ERROR_COUNT
- range: 31..0
- default:
- desc: When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
-
-FELIG_MON_FREQ_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_FREQ
- format_name: FELIG_MON_FREQ_{index:02}
- type_name: FELIG_MON_FREQ
- desc: FELIG specific configuration registers
- bitfield:
- - name: TX
- range: 63..32
- default: 0
- desc: FELIG regenerated TX clock frequency[Hz].
- - name: RX
- range: 31..0
- default: 0
- desc: FELIG recovered RX clock frequency[Hz].
-
-FELIG_MON_L1A_ID_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_L1A_ID
- format_name: FELIG_MON_L1A_ID_{index:02}
- type_name: FELIG_MON_L1A_ID
- desc: FELIG specific configuration registers
- bitfield:
- - range: 31..0
- default: 0
- desc: FELIG's last L1 ID.
-
-FELIG_MON_PICXO_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_PICXO
- format_name: FELIG_MON_PICXO_{index:02}
- type_name: FELIG_MON_PICXO
- desc: FELIG specific configuration registers
- bitfield:
- - name: VLOT
- range: 53..32
- default: 0
- desc: Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- - name: ERROR
- range: 20..0
- default: 0
- desc: Value indicates RX to TX frequency tracking error.
-
-Wishbone:
- desc: Wishbone
- endpoints: 0
- entries:
- - name: WISHBONE_CONTROL
- type: W
- bitfield:
- - range: 32
- name: WRITE_NOT_READ
- desc: wishbone write command wishbone read command
- - range: 31..0
- name: ADDRESS
- desc: Slave address for Wishbone bus
- - name: WISHBONE_WRITE
- type: T
- bitfield:
- - range: any
- type: T
- value: 1
- name: WRITE_ENABLE
- desc: Any write to this register triggers a write to the Wupper to Wishbone fifo
- - range: 32
- name: FULL
- type: R
- - range: 31..0
- name: DATA
- type: W
- - name: WISHBONE_READ
- type: T
- bitfield:
- - range: any
- type: T
- value: 1
- name: READ_ENABLE
- desc: Any write to this register triggers a read from the Wishbone to Wupper fifo
- - range: 32
- name: EMPTY
- type: R
- desc: Indicates that the Wishbone to Wupper fifo is empty
- - range: 31..0
- name: DATA
- type: R
- desc: Wishbone read data
- - name: WISHBONE_STATUS
- type: R
- bitfield:
- - range: 4
- name: INT
- desc: interrupt
- - range: 3
- name: RETRY
- desc: Interface is not ready to accept data cycle should be retried
- - range: 2
- name: STALL
- desc: When pipelined mode slave can't accept additional transactions in its queue
- - range: 1
- name: ACKNOWLEDGE
- desc: Indicates the termination of a normal bus cycle
- - range: 0
- name: ERROR
- desc: Address not mapped by the crossbar
diff --git a/sources/templates/yaml/registers-4.9.yaml b/sources/templates/yaml/registers-4.9.yaml
deleted file mode 100644
index 0924ca023923c198f43c4847651100d6392a458a..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-4.9.yaml
+++ /dev/null
@@ -1,2919 +0,0 @@
-Registers:
- version: '4.9'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: CentralRouterControlsAndMonitors
- record_name: register_map_cr_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: GBTWrapperMonitors
- record_name: register_map_gbt_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: TTCBUSYControlsAndMonitors
- record_name: register_map_ttc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: XOFF_BUSYControlsAndMonitors
- record_name: register_map_xoff_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: Generators
- record_name: register_map_generators
- bitfield:
- - range: 0..0
- type: R
- - name: Wishbone
- record_name: wishbone_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: DecodingControlsAndMonitors
- record_name: register_map_decoding_monitor
- bitfield:
- - range: 0..0
- type: R
-
-#Bar0 contains the registers dedicated to Wupper. Please only edit registers in Bar2
-#Registers in this group will not be generated with WupperCodeGen
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- #- name: DMA_FIFO_FLUSH
- # type: T
- # bitfield:
- # - range: any
- # desc: Flush (reset). Any write clears the DMA Main output FIFO
- - name: DMA_RESET
- offset: 0x420
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
- - name: BUSY_THRESHOLD_ASSERT
- type: W
- desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
- default: 0x6400000
- bitfield:
- - range: 63..0
-
- - name: BUSY_THRESHOLD_NEGATE
- type: W
- desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
- default: 0x6E00000
- bitfield:
- - range: 63..0
-
- - name: BUSY_STATUS
- type: R
- bitfield:
- - range: 1
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- - range: 0
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
- - name: PC_PTR_GAP
- type: W
- desc: This is the minimum value that the pc_pointer in a descriptor has to decrease in order to flip the evencycle_pc bit
- default: 0x1000000
- bitfield:
- - range: 63..0
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: SW_POINTER
- desc: Pointer controlled by the software, indicating read or write status for circular DMA
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- name: FROMHOST
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: FW_POINTER
- desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
-
-
-#Bar1 contains the registers dedicated to the Wupper interrupg controller.
-#Please only edit registers in Bar2.
-#Registers in this group will not be generated with WupperCodeGen
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 16
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-#Bar 2 contains application specific registers, used in the example application.
-#Registers in this group (and it's referenced subroups) will be generated with
-#WupperCodeGen for wupper Firmware, Software and Documentation
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CentralRouterControlsAndMonitors
- offset: 0x1000
- - ref: GBTEmulatorControlsAndMonitors
- offset: 0x5000
- - ref: GBTWrapperControls
- offset: 0x6000
- - ref: GBTWrapperMonitors
- offset: 0x7000
- - ref: TTCBUSYControlsAndMonitors
- offset: 0x8000
- - ref: XOFF_BUSYControlsAndMonitors
- offset: 0x8800
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x9000
- - ref: Generators
- offset: 0xA000
- - ref: Wishbone
- offset: 0xC000
- - ref: DecodingControlsAndMonitors
- offset: 0xD000
- #- ref: EncodingControlsAndMonitors
- # offset: 0xE000
-
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned({{ tree.version|version }},16))
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- #- name: BOARD_ID_SVN
- # bitfield:
- # - range: 15..0
- # value: std_logic_vector(to_unsigned(SVN_VERSION,16))
- # desc: OBSOLETE Board ID SVN Revision
-
- - name: GIT_COMMIT_TIME
- offset: 0x30
- bitfield:
- - range: 39..0
- value: COMMIT_DATETIME
- desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_TAG
- bitfield:
- - range: 63..0
- value: GIT_TAG(63 downto 0)
- desc: String containing the current GIT TAG
-
- - name: GIT_COMMIT_NUMBER
- bitfield:
- - range: 31..0
- value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
- desc: Number of GIT commits after current GIT_TAG
-
- - name: GIT_HASH
- bitfield:
- - range: 31..0
- value: GIT_HASH(159 downto 128)
- desc: Short GIT hash (32 bit)
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT or FULL mode Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): FLX709, VC709
- - 710 (0x2c6): FLX710, HTG710
- - 711 (0x2c7): FLX711, BNL711
- - 712 (0x2c8): FLX712, BNL712
- - 128 (0x080): FLX128, VCU128
-
- #- name: GBT_MAPPING
- # bitfield:
- # - range: 7..0
- # desc: |
- # OBSOLETE CXP-to-GBT mapping:
- # 0: NORMAL CXP1 1-12 CXP2 13-24
- # 1: ALTERNATE CXP1 1-4,9-12,17-20
-
- - name: GENERATE_GBT
- offset: 0xc0
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: TTC_EMU_CONST_GENERATE_TTC_EMU
- type: R
- bitfield:
- - range: 1
- type: R
- desc: 1 when TTC emulator is generated
-
- #- range: 0
- # type: R
- # name: TTC_TEST_MODE
- # desc: OBSOLETE 1 when TTC Test mode is anabled
-
- #- name: CR_INTERNAL_LOOPBACK_MODE
- # type: R
- # bitfield:
- # - range: 0
- # desc: OBSOLETE 1 when Central Router internal loopback mode is enabled
-
- - offset: 0x100
- ref: INCLUDE_EGROUPS
-
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- #- name: DEBUG_MODE
- # type: R
- # bitfield:
- # - range: 0
- # desc: |
- # OBSOLETE
- # 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- # 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
-
- - name: FIRMWARE_MODE
- type: R
- offset: 0x190
- bitfield:
- - range: 3..0
- desc: |
- 0: GBT mode
- 1: FULL mode
- 2: LTDB mode (GBT mode with only IC and TTC links)
- 3: FEI4 mode
- 4: ITK Pixel
- 5: ITK Strip
- 6: FELIG
- 7: FULL mode emulator
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
- - name: BLOCKSIZE
- type: R
- desc: Number of bytes in a block
- bitfield:
- - range: 15..0
-
- - name: PCIE_ENDPOINT
- type: R
- desc: Indicator of the PCIe endpoint on BNL71x cards with two endpoints. 0 or 1
- bitfield:
- - range: 0
- value: std_logic_vector(to_unsigned(PCIE_ENDPOINT, 1))
-
- - name: CHUNK_TRAILER_32B
- type: R
- desc: Indicator that the chunk trailer is in the new 32-bit format
- bitfield:
- - range: 0
-
- - name: PCIE_ENDPOINTS
- type: R
- desc: Number of PCIe endpoints on the card. The BNL71x cards have 2 endpoints
- bitfield:
- - range: 1..0
-
-INCLUDE_EGROUPS:
- number: 7
- entries:
- - format_name: INCLUDE_EGROUP_{index}
- name: INCLUDE_EGROUP
- type_name: INCLUDE_EGROUP
- type: R
- bitfield:
- - range: 8
- name: FROMHOST_02
- desc: FromHost EPROC02 is included in this EGROUP
- - range: 7
- name: FROMHOST_04
- desc: FromHost EPROC04 is included in this EGROUP
- - range: 6
- name: FROMHOST_08
- desc: FromHost EPROC8 is included in this EGROUP
- - range: 5
- name: FROMHOST_HDLC
- desc: FromHost HDLC is included in this EGROUP
- - range: 4
- name: TOHOST_02
- desc: ToHost EPROC02 is included in this EGROUP
- - range: 3
- name: TOHOST_04
- desc: ToHost EPROC04 is included in this EGROUP
- - range: 2
- name: TOHOST_08
- desc: ToHost EPROC08 is included in this EGROUP
- - range: 1
- name: TOHOST_16
- desc: ToHost EPROC16 is included in this EGROUP
- - range: 0
- name: TOHOST_HDLC
- desc: ToHost HDLC is included in this EGROUP
-
-
-CentralRouterControlsAndMonitors:
- group: CRC
- desc: Central Router Controls and Monitors
- endpoints: 0,1
- entries:
- - name: IC_FROMHOST_PACKET_RDY
- type: W
- bitfield:
- - range: 23..0
- desc: Rising edge indicates the complete packet can be read
-
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
-
- - ref: CR_GBT_CTRL
- desc: See Central Router Doc
- offset: 0x0100
-
- - ref: IC_FIFOS
- desc: See Central Router Doc
- offset: 0x1400
-
- - ref: MINI_EGROUP_CTRL
- desc: Controls EC and TTC channels of Mini Egroups
-
- #- name: CR_FALLBACK_OPTIONS
- # desc: OBSOLETE Julias personal register with Hello Kitty options
- # type: W
- # bitfield:
- # - range: 63..0
-
- - name: CR_TTC_TOHOST
- desc: Enables the ToHost Mini Egroup in TTC mode
- offset: 0x1a10
- type: W
- bitfield:
- - range: 63
- name: EMU_FAKE_READY_ENABLE
- default: 0
- - range: 60..48
- name: EMU_FAKE_READY_VALUE
- default: 0x1000
- - range: 15..4
- name: TIMEOUT_VALUE
- default: 0xFFF
- - range: 2
- name: EMU_ENABLE
- default: 0
- - range: 1
- name: TIMEOUT_ENABLE
- default: 1
- - range: 0
- name: ENABLE
- default: 1
-
- - name: CR_REVERSE_10B
- desc: Reverse 10-bit word of elink data
- type: W
- bitfield:
- - range: 1
- name: FROMHOST
- default: 1
- desc: |
- 1: Serialize 10-bit word in FromHost EPROCS MSB first
- 0: Serialize 10-bit word in FromHost EPROCS LSB first
- - range: 0
- name: TOHOST
- default: 1
- desc: |
- 1: Receive 10-bit word in ToHost EPROCS, MSB first
- 0: Receive 10-bit word in ToHost EPROCS, LSB first
-
- - name: CR_LTDB_TTC_DELAY
- desc: Controls TTC BCR delay in LTDB mode firmware
- type: W
- bitfield:
- - range: 7
- name: EGROUP4_EPATH6
- default: 1
- desc: |
- Egroup 4, Epath 6
- 1: Half a clock delay
- 0: no delay
- - range: 6
- name: EGROUP4_EPATH5
- default: 1
- desc: |
- Egroup 4, Epath 5
- 1: Half a clock delay
- 0: no delay
- - range: 5
- name: EGROUP4_EPATH4
- default: 1
- desc: |
- Egroup 4, Epath 4
- 1: Half a clock delay
- 0: no delay
- - range: 4
- name: EGROUP4_EPATH3
- default: 1
- desc: |
- Egroup 4, Epath 3
- 1: Half a clock delay
- 0: no delay
- - range: 3
- name: EGROUP4_EPATH0
- default: 1
- desc: |
- Egroup 4, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 2
- name: EGROUP3
- default: 1
- desc: |
- Egroup 3, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 1
- name: EGROUP2
- default: 1
- desc: |
- Egroup 2, Epath 0
- 1: Half a clock delay
- 0: no delay
- - range: 0
- name: EGROUP1
- default: 1
- desc: |
- Egroup 1, Epath 0
- 1: Half a clock delay
- 0: no delay
-# - ref: CR_XOFF_CTRL
-# offset: 0x2800
-# desc: Configure FromHost Xoff
-
-
-#Central Router monitors
- - ref: CR_GBT_MON
- offset: 0x3000
- #- name: CR_STATIC_CONFIGURATION
- # type: R
- # bitfield:
- # - range: 0
- #- ref: CR_DEFAULT_EPROC_ENA_G
- #- ref: CR_DEFAULT_EPROC_ENCODING_G
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- offset: 0x3410
- bitfield:
- - range: 31..0
-
-CR_GBT_CTRL:
- number: 24
- bitfield:
- - range: 50..0
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- entries:
- - ref: EGROUP_TOHOST
- - ref: EGROUP_FROMHOST
-
-EGROUP_TOHOST:
- number: 7
- format_name: GBT{index:02}
- name: GBT
- entries:
- - name: TOHOST
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_TOHOST_EGROUP_CTRL
- bitfield:
- - range: 58..51
- name: INSTANT_TIMEOUT_ENA
- default: 0x0
- desc: instantly initiate a timeout for the given epath
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..31
- name: MAX_CHUNK_LEN
- default: MAX_CHUNK_LEN_array
- desc: set the maximum length of a chunk, 0 disables truncation
- - range: 30..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- default:
- - PATH_ENCODING_array(0)
- - PATH_ENCODING_array(1)
- - PATH_ENCODING_array(2)
- - PATH_ENCODING_array(3)
- - PATH_ENCODING_array(4)
- - PATH_ENCODING_array(5)
- - PATH_ENCODING_array(6)
-
- - range: 14..0
- name: EPROC_ENA
- desc: Enable bits per EPROC
- default:
- - EPROC_ENA_bits_array(0)
- - EPROC_ENA_bits_array(1)
- - EPROC_ENA_bits_array(2)
- - EPROC_ENA_bits_array(3)
- - EPROC_ENA_bits_array(4)
- - EPROC_ENA_bits_array(5)
- - EPROC_ENA_bits_array(6)
-
-EGROUP_FROMHOST:
- number: 5
- format_name: GBT{index:02}
- entries:
- - name: FROMHOST
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
- type_name: CR_FROMHOST_EGROUP_CTRL
- bitfield:
- - range: 54..47
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 46..15
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 8 EPATHS per EGROUP
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- greater than 3: TTC mode, see CentralRouter doc
- default:
- - FROMHOST_PATH_ENCODING_array(0)
- - FROMHOST_PATH_ENCODING_array(1)
- - FROMHOST_PATH_ENCODING_array(2)
- - FROMHOST_PATH_ENCODING_array(3)
- - FROMHOST_PATH_ENCODING_array(4)
- - FROMHOST_PATH_ENCODING_array(5)
- - FROMHOST_PATH_ENCODING_array(6)
- - range: 14..0
- desc: Enable bits per EPROC
- name: EPROC_ENA
-
-IC_FIFOS:
- number: 24
- format_name: IC_FROMHOST_TOHOST_FIFOS
- entries:
- - name: FROMHOST
- format_name: IC_FROMHOST_FIFO_{index:02}
- type_name: IC_FROMHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_FROMHOST_FIFO({index}).FULL
- name: WE
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a write to the FIFO
- - range: 8
- type: R
- name: FULL
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Full flag of the fifo, do not write if 1
- - range: 7..0
- type: W
- name: DATAIN
- format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
- desc: Data input of fifo
- - name: TOHOST
- format_name: IC_TOHOST_FIFO_{index:02}
- type_name: IC_TOHOST_FIFO
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: any
- type: T
- value: not register_map_monitor_s.register_map_cr_monitor.IC_TOHOST_FIFO({index}).EMPTY
- name: RE
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Any write to this register will trigger a read enable from the fifo
- - range: 8
- type: R
- name: EMPTY
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Empty flag of the fifo, do not read if 1
- - range: 7..0
- type: R
- name: DATAOUT
- format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
- desc: Data output of fifo
-
-
-MINI_EGROUP_CTRL:
- number: 24
- format_name: MINI_EGROUP_CTRLS
- entries:
- - name: EC_TOHOST
- format_name: EC_TOHOST_{index:02}
- type_name: EC_TOHOST
- desc: Configures the ToHost Mini egroup in EC mode
- type: W
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 7
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 6
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 5
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 4
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 3
- name: BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 2..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- desc: Enables the EC channel
- default: 1
- - name: EC_FROMHOST
- format_name: EC_FROMHOST_{index:02}
- type_name: EC_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup in EC mode
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 9
- name: SCA_AUX_BIT_SWAPPING
- desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 8
- name: SCA_AUX_ENABLE
- desc: Enables the SCA AUX channel
- default: 1
- - range: 7
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 6
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 5
- name: BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: ENABLE
- default: 1
-
-
-CR_GBT_MON:
- desc: See Central Router Doc
- endpoints: 0
- number: 24
- entries:
- - name: TOHOST
- type_name: CR_TOHOST_GBT_MON
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 58
- name: CROUTFIFO_PROG_FULL
- - range: 57
- name: WMFIFO_FULL
- - range: 56
- name: MINI_EGROUP_ALMOST_FULL
- - range: 55..48
- name: EPATH6_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP6
- - range: 47..40
- name: EPATH5_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP5
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
- - name: FROMHOST
- type_name: CR_FROMHOST_GBT_MON
- format_name: CR_{name}_GBT{index:02}_MON
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- bitfield:
- - range: 40
- name: MINI_EGROUP_ALMOST_FULL
- - range: 39..32
- name: EPATH4_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP4
- - range: 31..24
- name: EPATH3_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP3
- - range: 23..16
- name: EPATH2_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP2
- - range: 15..8
- name: EPATH1_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP1
- - range: 7..0
- name: EPATH0_ALMOST_FULL
- desc: Almost full bits of the EPATH fifos in EGROUP0
-
-#CR_DEFAULT_EPROC_ENA_G:
-# desc: OBSOLETE Static CR default enable bits
-# endpoints: 0,1
-# number: 8
-# type: R
-# entries:
-# - name: ENABLE
-# format_name: CR_DEFAULT_EPROC_ENA{index}
-# type_name: CR_DEFAULT_EPROC_ENA
-# bitfield:
-# - range: 14..0
-#
-#
-#CR_DEFAULT_EPROC_ENCODING_G:
-# desc: OBSOLETE Static CR default encoding bits
-# endpoints: 0,1
-# number: 8
-# type: R
-# entries:
-# - name: ENCODING
-# format_name: CR_DEFAULT_EPROC_ENCODING{index}
-# type_name: CR_DEFAULT_EPROC_ENCODING
-# bitfield:
-# - range: 15..0
-
-
-GBTEmulatorControlsAndMonitors:
- group: GEC
- desc: GBT Emulator Controls and Monitors
- endpoints: 0, 1
- entries:
- - name: GBT_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
- - range: 0
- name: TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: GBT_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 6..0
- desc: write enable array, every bit is one emulator RAM block
-
- - name: GBT_EMU_CONFIG
- type: W
- bitfield:
- - range: 63..48
- name: RDDATA
- type: R
- desc: read data bus
- - range: 45..32
- name: WRADDR
- desc: write address bus
- - range: 15..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_ENA_TOHOST
- type: W
- bitfield:
- - range: 0
- desc: Enable FULL mode dummy emulator ToHost
-
- - name: GBT_FM_EMU_CONFIG_WE_ARRAY
- type: W
- bitfield:
- - range: 0
- desc: write enable for the full mode emulator ram block
-
- - name: GBT_FM_EMU_CONFIG
- type: W
- bitfield:
- - range: 53..40
- name: WRADDR
- desc: write address bus
- - range: 35..0
- name: WRDATA
- desc: write data bus
-
- - name: GBT_FM_EMU_READ
- type: R
- bitfield:
- - range: 35..0
- desc: read emu ram data
-
-
- - name: CR_FM_PATH_ENA
- type: W
- bitfield:
- - range: 11..0
- desc: FULL mode CR enable array, every bit is one path
-
- - ref: PATH_HAS_STREAM_ID
-
-PATH_HAS_STREAM_ID:
- number: 24
- generate: register_map_monitor_s.register_map_gen_board_info.NUM_OF_CHANNELS > {index:1}
- entries:
- - name: TOHOST
- format_name: LINK_{index:02}_HAS_STREAM_ID
- type_name: HAS_STREAM_ID
- type: W
- bitfield:
- - range: 55..48
- name: EGROUP6
- default: 0x0
- desc: EPATH (Wide mode) is associated with a STREAM ID
- - range: 47..40
- name: EGROUP5
- default: 0x0
- desc: EPATH (Wide mode) is associated with a STREAM ID
- - range: 39..32
- name: EGROUP4
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 31..24
- name: EGROUP3
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 23..16
- name: EGROUP2
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 15..8
- name: EGROUP1
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 7..0
- name: EGROUP0
- default: 0x0
- desc: EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
-
-
-GBTWrapperControls:
- group: GWC
- desc: GBT Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: GBT_CHANNEL_DISABLE
- offset: 0x0400
- bitfield:
- - range: 47..0
- desc: Disable selected GBT or FULL mode channel
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE_SELECT
- offset: 0x0480
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_RXSLIDE_MANUAL
- desc: RxSlide select [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_TXUSRRDY
- desc: TxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_RXUSRRDY
- desc: RxUsrRdy [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_SOFT_RESET
- desc: SOFT_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTTX_RESET
- desc: GTTX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTRX_RESET
- desc: GTRX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 59..48
- name: QPLL_RESET
- desc: QPLL_RESET [11:0]
- - range: 47..0
- name: CPLL_RESET
- desc: CPLL_RESET [47:0]
-
- - name: GBT_SOFT_TX_RESET
- offset: 0x0500
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_SOFT_RX_RESET
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_ODD_EVEN
- desc: OddEven [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_TOPBOT
- desc: TopBot [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_TC_DLY_VALUE3
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [143:96]
-
- - name: GBT_TX_TC_DLY_VALUE4
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [191:144]
-
- - name: GBT_DATA_TXFORMAT1
- desc: DATA_TXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_TXFORMAT2
- desc: DATA_TXFORMAT [95:48]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT1
- desc: DATA_RXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT2
- desc: DATA_RXFORMAT [95:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_RESET
- desc: TX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_RESET
- desc: RX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_METHOD
- desc: TX time domain crossing method [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUTMUX_SEL
- desc: Descrambler output MUX selection [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TC_EDGE
- desc: Sampling edge selection for TX domain crossing [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for transmitter of GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_RXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for the receiver of the GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
- - name: GBT_TOHOST_FANOUT
- offset: 0x0700
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_TOFRONTEND_FANOUT
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0xFFFFFFFFFFFF
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
-
-GBTWrapperMonitors:
- group: GWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- desc: TX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXRESET_DONE
- desc: RX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXFSMRESET_DONE
- desc: TX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXFSMRESET_DONE
- desc: RX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_LOCK
- bitfield:
- - range: 59..48
- name: QPLL_LOCK
- desc: QPLL LOCK [11:0]
- - range: 47..0
- name: CPLL_LOCK
- desc: CPLL LOCK [47:0]
-
- - name: GBT_RXCDR_LOCK
- desc: RX CDR LOCK [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CLK_SAMPLED
- desc: clk sampled [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_HEADER
- desc: RX IS HEADER [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_DATA
- desc: RX IS DATA [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_HEADER_FOUND
- desc: RX HEADER FOUND [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUT_MUX_STATUS
- desc: GBT output mux status [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ERROR
- desc: Error flags [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GBT_TOPBOT_C
- desc: TopBot_c [47:0]
- generate: GBT_GENERATE_ALL_REGS
- bitfield:
- - range: 47..0
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
-TTCBUSYControlsAndMonitors:
- group: TTCBUSY
- desc: TTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: TTC_BUSY_ACCEPTED_G
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 2
- name: FULL
- type: R
- desc: TTC Emulator memory full indication
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
-
- - ref: TTC_DELAY
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the BUSY Logic
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
- - name: TTC_EMU_CONTROL
- type: W
- bitfield:
- - range: 32..27
- name: BROADCAST
- desc: Broadcast data
- - range: 26
- name: ECR
- desc: Event counter reset
- - range: 25
- name: BCR
- desc: Bunch counter reset
- - range: 24
- name: L1A
- desc: Level 1 Accept
-
- - name: TTC_EMU_L1A_PERIOD
- type: W
- desc: L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
- bitfield:
- - range: 31..0
-
- - name: TTC_EMU_ECR_PERIOD
- type: W
- desc: ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
- bitfield:
- - range: 31..0
-
- - name: TTC_EMU_BCR_PERIOD
- type: W
- desc: BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
- bitfield:
- - range: 31..0
- default: 3564
-
- - name: TTC_EMU_LONG_CHANNEL_DATA
- type: W
- desc: Long channel data for the TTC emulator
- bitfield:
- - range: 31..0
-
- - name: TTC_EMU_RESET
- desc: Any write to this register resets the TTC Emulator to the default state.
- type: W
- bitfield:
- - range: any
- value: 1
- type: T
-
- - name: TTC_L1ID_MONITOR
- desc: Monitor L1ID and XL1ID.
- type: R
- bitfield:
- - range: 31..0
-
- - name: TTC_ECR_MONITOR
- desc: Counts the number of ECRs received from the TTC system, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_TTYPE_MONITOR
- desc: Counts the number of TType received from the TTC system, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_BCR_PERIODICITY_MONITOR
- desc: Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range: 26..15
- name: BCID_ONBCR
- type: W
- desc: BCID is set to this value when BCR arrives
- - range: 14
- name: BUSY_OUTPUT_STATUS
- type: R
- desc: Actual status of the BUSY LEMO output signal
- - range: 13
- name: ECR_BCR_SWAP
- default: 0
- desc: ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
- - range: 12
- name: BUSY_OUTPUT_INHIBIT
- default: 0
- desc: forces the Busy LEMO output to BUSY-OFF
- - range: 11
- name: TOHOST_RST
- desc: reset toHost in ttc decoder
- default: 0
- - range: 10
- name: TT_BCH_EN
- desc: trigger type enable / disable for TTC-ToHost
- default: 1
- - range: 9..2
- name: XL1ID_SW
- desc: set XL1ID value, the value to be set by XL1ID_RST signal
- default: 0x00
- - range: 1
- name: XL1ID_RST
- desc: giving a trigger signal to reset XL1ID value
- default: 0
- - range: 0
- name: MASTER_BUSY
- desc: L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range: 15..5
- name: TH_FF_COUNT
- desc: ToHostData Fifo counts
- - range: 4
- name: TH_FF_FULL
- desc: ToHostData Fifo status 1:full 0:not full
- - range: 3
- name: TH_FF_EMPTY
- desc: ToHostData Fifo status 1:empty 0:not empty
- - range: 2..0
- name: TTC_BIT_ERR
- desc: double bit, single bit and comm error in TTC data
-
-TTC_BUSY_ACCEPTED_G:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- entries:
- - name: TTC_BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
- type_name: TTC_BUSY_ACCEPTED
- bitfield:
- - range: 56..0
-
-
-
-TTC_DELAY:
- number: 48
- type: W
- entries:
- - name: TTC_DELAY
- format_name: TTC_DELAY_{index:02}
- type_name: TTC_DELAY
- desc: Controls the TTC Fanout delay values
- bitfield:
- - range: 3..0
- default: 0
-
-XOFF_BUSYControlsAndMonitors:
- group: XOFF
- desc: XOFF Controls and Monitors, see table 2 of Busy specs manual
- endpoints: 0, 1
- entries:
- - name: XOFF_FM_CH_FIFO_THRESH_LOW
- desc: Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xB
- - range: 43..40
- name: CH10
- default: 0xB
- - range: 39..36
- name: CH09
- default: 0xB
- - range: 35..32
- name: CH08
- default: 0xB
- - range: 31..28
- name: CH07
- default: 0xB
- - range: 27..24
- name: CH06
- default: 0xB
- - range: 23..20
- name: CH05
- default: 0xB
- - range: 19..16
- name: CH04
- default: 0xB
- - range: 15..12
- name: CH03
- default: 0xB
- - range: 11..8
- name: CH02
- default: 0xB
- - range: 7..4
- name: CH01
- default: 0xB
- - range: 3..0
- name: CH00
- default: 0xB
-
- - name: XOFF_FM_CH_FIFO_THRESH_HIGH
- desc: Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB
- type: W
- bitfield:
- - range: 47..44
- name: CH11
- default: 0xB
- - range: 43..40
- name: CH10
- default: 0xB
- - range: 39..36
- name: CH09
- default: 0xB
- - range: 35..32
- name: CH08
- default: 0xB
- - range: 31..28
- name: CH07
- default: 0xB
- - range: 27..24
- name: CH06
- default: 0xB
- - range: 23..20
- name: CH05
- default: 0xB
- - range: 19..16
- name: CH04
- default: 0xB
- - range: 15..12
- name: CH03
- default: 0xB
- - range: 11..8
- name: CH02
- default: 0xB
- - range: 7..4
- name: CH01
- default: 0xB
- - range: 3..0
- name: CH00
- default: 0xB
-
- - name: XOFF_FM_LOW_THRESH_CROSSED
- desc: FIFO filled beyond the low threshold, 1 bit per channel
- type: R
- bitfield:
- - range: 23..0
- - name: XOFF_FM_HIGH_THRESH
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- desc: Writing this register will clear all CROSS_LATCHED bits
- type: T
- value: 1
- - range: 47..24
- type: R
- name: CROSS_LATCHED
- desc: FIFO filled beyond the high threshold, 1 latch bit per channel
- - range: 23..0
- type: R
- name: CROSSED
- desc: FIFO filled beyond the high threshold, 1 bit per channel
-
- - name: XOFF_FM_SOFT_XOFF
- type: W
- desc: Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
- bitfield:
- - range: 23..0
-
- - name: XOFF_ENABLE
- type: W
- desc: Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
- bitfield:
- - range: 23..0
-
- - name: DMA_BUSY_STATUS
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR_LATCH
- desc: Any write to this register clears TOHOST_BUSY_LATCHED
- - range: 4
- type: W
- name: ENABLE
- desc: Enable the DMA buffer on the server as a source of busy
- default: 0
- - range: 3
- type: R
- name: TOHOST_BUSY_LATCHED
- desc: A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => tohost_busy_latched_40_s)
- - range: 2
- type: R
- name: FROMHOST_BUSY_LATCHED
- desc: A fromhost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => fromhost_busy_latched_40_s)
- - range: 1
- type: R
- name: FROMHOST_BUSY
- desc: A fromhost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => fromhost_busy_40_s)
- - range: 0
- type: R
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => tohost_busy_40_s)
-
- - name: FM_BUSY_CHANNEL_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- type: T
- value: 1
- desc: Any write to this register will clear the BUSY_LATCHED bits
- - range: 47..24
- type: R
- name: BUSY_LATCHED
- desc: one Indicates that the given FULL mode channel has received BUSY-ON
- - range: 23..0
- type: R
- name: BUSY
- desc: one Indicates that the given FULL mode channel is currently in BUSY state
-
- - name: BUSY_MAIN_OUTPUT_FIFO_THRESH
- type: W
- bitfield:
- - range: 24
- name: BUSY_ENABLE
- desc: Enable busy generation if thresholds are crossed
- default: 0
- - range: 23..12
- name: LOW
- desc: Low, Negate threshold of busy generation from main output fifo
- default: 0x3FF
- - range: 11..0
- name: HIGH
- desc: High, Assert threshold of busy generation from main output fifo
- default: 0x4FF
-
- - name: BUSY_MAIN_OUTPUT_FIFO_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCHED
- value: 1
- desc: Any write to this register will clear the
- type: T
- - range: 2
- type: R
- name: HIGH_THRESH_CROSSED_LATCHED
- desc: Main output fifo has been full beyond HIGH THRESHOLD, write to clear
- - range: 1
- type: R
- name: HIGH_THRESH_CROSSED
- desc: Main output fifo is full beyond HIGH THRESHOLD
- - range: 0
- type: R
- name: LOW_THRESH_CROSSED
- desc: Main output fifo is full beyond LOW THRESHOLD
- - ref: ELINK_BUSY_ENABLE
-
-
-ELINK_BUSY_ENABLE:
- number: 24
- endpoints: 0
- type: W
- entries:
- - name: ELINK_BUSY_ENABLE
- format_name: ELINK_BUSY_ENABLE{index:02}
- type_name: ELINK_BUSY_ENABLE
- desc: Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- bitfield:
- - range: 56..0
- default: 0
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
-
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
-
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, only connected on FLX711
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x0
- desc: Si5345 active low output enable (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
-
- - name: HK_MON_FMC
- type: W
- bitfield:
- - range: 1
- name: SI5345_LOL
- desc: Si5345 Loss Of Lock pin
- - range: 0
- name: SI5345_INTR
- desc: Si5345 Interrupt flagging chip change of status
-
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: 3
- type: W
- name: LCLK_SEL
- default: 0x1
- desc: |
- 1: LCLK
- 0: TTC
- - range: 2..1
- type: R
- name: MAIN_INPUT
- desc: |
- Main MMCM Oscillator Input
- 2: LCLK fixed
- 1: TTC fixed
- 0: selectable
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
-
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL-711 locked
-
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
-
- - name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
-
-
- #- name: SPI_WR
- # type: W
- # offset: 0x0400
- # bitfield:
- # - range: any
- # type: T
- # value: OBSOLETE not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
- # name: SPI_WREN
- # desc: Any write to this register triggers an SPI Write
- # - range: 32
- # type: R
- # name: SPI_FULL
- # desc: OBSOLETE SPI FIFO Full
- # - range: 31..0
- # type: W
- # name: SPI_DIN
- # desc: OBSOLETE SPI WRITE Data
- #
- #- name: SPI_RD
- # type: T
- # bitfield:
- # - range: any
- # type: T
- # value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
- # name: SPI_RDEN
- # desc: OBSOLETE Any write to this register pops the last SPI data from the FIFO
- # - range: 32
- # type: R
- # name: SPI_EMPTY
- # desc: OBSOLETE SPI FIFO Empty
- # - range: 31..0
- # type: R
- # name: SPI_DOUT
- # desc: OBSOLETE SPI READ Data
-
- - name: I2C_WR
- type: W
- offset: 0x420
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
-
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
-
-
- #- name: DEBUG_PORT_GBT
- # offset: 0x0500
- # type: W
- # bitfield:
- # - range: 6..0
- # desc: OBSOLETE Debug GBT data bit N (119..0) on SMA HTGx#3
-
- #- name: DEBUG_PORT_CLK
- # type: W
- # bitfield:
- # - range: 3..0
- # desc: OBSOLETE Debug clock and L1A port on SMA HTGx#4
-
- - name: INT_TEST
- offset: 0x0800
- type: W
- value: 1
- bitfield:
- - name: TRIGGER
- type: T
- range: any
- desc: Fire a test MSIx interrupt set in IRQ
- - name: IRQ
- type: W
- range: 3..0
- desc: Set this field to a value equal to the MSIX interrupt to be fired. The write triggers the interrupt immediately.
-
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
-
- - name: TACH_CNT
- type: R
- desc: Readout of the Fan tachometer speed of the BNL712 board
- bitfield:
- - range: 19..0
-
- - name: RXUSRCLK_FREQ
- type: W
- bitfield:
- - range: 38
- name: VALID
- type: R
- desc: Indicates that the frequency measurement is valid
- - range: 37..32
- name: CHANNEL
- type: W
- desc: Select the Transceiver channel to measure the clock from.
- - range: 31..0
- name: VAL
- type: R
- desc: Frequency in Hz of the selected channel
-
-
-Generators:
- group: GEN
- desc: Specific registers for Hardware based Generators
- endpoints: 0
- generate: EMU_GENERATE_REGS
- entries:
-
- - ref: FELIG_DATA_GEN_CONFIG_ARR
- offset: 0x20
- - ref: FELIG_ELINK_CONFIG_ARR
- - ref: FELIG_ELINK_ENABLE_ARR
-
- - name: FELIG_GLOBAL_CONTROL
- type: W
- bitfield:
- - range: 63..36
- name: FAKE_L1A_RATE
- default: 0
- desc: Sets the internal fake L1 trigger rate. [25ns/LSB]
- - range: 35..14
- name: PICXO_OFFSET_PPM
- default: 0
- desc: When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
- - range: 12..12
- name: TRACK_DATA
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 11..11
- name: RXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 10..10
- name: TXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 9..9
- name: AUTO_RESET
- default: 0
- desc: FELIG GT core control. If set the GT core automatically resets on data error.
- - range: 8..8
- name: PICXO_RESET
- default: 0
- desc: FELIG GT core control. Manual PICXO reset.
- - range: 7..7
- name: GTTX_RESET
- default: 0
- desc: FELIG GT core control. Manual GT TX reset
- - range: 6..6
- name: CPLL_RESET
- default: 0
- desc: FELIG GT core control. Manual CPLL reset.
- - range: 5..0
- name: X3_X4_OUTPUT_SELECT
- default: 0
- desc: X3/X4 SMA output source select.
-
- - ref: FELIG_LANE_CONFIG_ARR
- - ref: FELIG_MON_TTC_0_ARR
- - ref: FELIG_MON_TTC_1_ARR
- - ref: FELIG_MON_COUNTERS_ARR
- - ref: FELIG_MON_FREQ_ARR
-
- - name: FELIG_MON_FREQ_GLOBAL
- type: W
- bitfield:
- - range: 63..32
- name: XTAL_100MHZ
- default: 0
- desc: FELIG local oscillator frequency[Hz].
- - range: 31..0
- name: CLK_41_667MHZ
- desc: FELIG PCIE MGTREFCLK frequency[Hz].
-
- - ref: FELIG_MON_L1A_ID_ARR
- - ref: FELIG_MON_PICXO_ARR
-
- - name: FELIG_RESET
- type: W
- bitfield:
- - range: 63..48
- name: LB_FIFO
- default: 0
- desc: One bit per lane. When set to 1, resets all loopback FIFOs.
- - range: 47..24
- name: FRAMEGEN
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG link checking logic.
- - range: 23..0
- name: LANE
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG lane logic.
-
- - name: FELIG_RX_SLIDE_RESET
- type: W
- bitfield:
- - range: 23..0
- default: 0
- desc: One bit per lane. When set to 1, resets the gbt rx slide counter.
-
- - ref: FELIG_ITK_STRIPS_DATA_GEN_CONFIG_ARR
- - ref: FELIG_MON_ITK_STRIPS_ARR
-
- - name: FMEMU_EVENT_INFO
- type: W
- offset: 0x1800
- bitfield:
- - range: 63..32
- name: L1ID
- default: 0
- desc: 32b field to show L1ID
- - range: 31..0
- name: BCID
- default: 0
- desc: 32b field to show BCID
-
- - name: FMEMU_COUNTERS
- type: W
- bitfield:
- - range: 63..48
- name: WORD_CNT
- default: 32
- desc: Number of 32b words in one chunk
- - range: 47..32
- name: IDLE_CNT
- default: 3
- desc: Minimum number of idles between chunks
- - range: 31..16
- name: L1A_CNT
- default: 256
- desc: Number of chunks to send if not in TTC mode
- - range: 15..8
- name: BUSY_TH_HIGH
- default: 20
- desc: Assert BUSY-ON above this threshold
- - range: 7..0
- name: BUSY_TH_LOW
- default: 15
- desc: De-assert BUSY-ON below this threshold
-
- - name: FMEMU_CONTROL
- type: W
- bitfield:
- - range: 63..56
- type: W
- name: L1A_BITNR
- default: 32
- desc: Bitfield for L1A in TTC frame
- - range: 55..48
- type: W
- name: XONXOFF_BITNR
- default: 32
- desc: Bitfield for Xon/Xoff in TTC frame
- - range: 47..47
- type: W
- name: EMU_START
- default: 0
- desc: Start emulator functionality
- - range: 46..46
- type: W
- name: TTC_MODE
- default: 0
- desc: Control the emulator by TTC input or by RegMap (1/0)
- - range: 45..45
- type: W
- name: XONXOFF
- default: 0
- desc: Debug Xon/Xoff functionality (1/0)
- - range: 44..44
- type: W
- name: INLC_CRC32
- default: 0
- desc: |
- 0: No checksum
- 1: Append the data with a CRC32
- - range: 43..43
- type: W
- name: BCR
- default: 0
- desc: Reset BCID to 0
- - range: 42..42
- type: W
- name: ECR
- default: 0
- desc: Reset L1ID to 0
- - range: 41..41
- type: W
- name: DATA_SRC_SEL
- default: 0
- desc: |
- Data source select
- 0: Data input comes from EMURAM
- 1: Data input comes from PCIe
- - range: 40..32
- type: R
- name: INT_STATUS_EMU
- default: 0
- desc: Read internal status emulator
- - range: 31..16
- type: W
- name: FFU_FM_EMU_T
- default: 0
- desc: For Future Use (trigger registers)
- - range: 15..0
- type: W
- name: FFU_FM_EMU_W
- default: 0
- desc: For Future Use (write registers)
-
- - name: FMEMU_RANDOM_RAM_ADDR
- type: W
- desc: Controls the address of the ramblock for the random number generator
- bitfield:
- - range: 9..0
- - name: FMEMU_RANDOM_RAM
- type: W
- bitfield:
- - range: any
- type: T
- name: WE
- value: 1
- desc: Any write to this register (DATA) triggers a write to the ramblock
- - range: 39..16
- name: CHANNEL_SELECT
- value: 0xFFFFFF
- desc: Enable write enable only for the selected channel
- - range: 15..0
- name: DATA
- type: W
- desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
- - name: FMEMU_RANDOM_CONTROL
- type: W
- desc: Controls the random chunk length generator
- bitfield:
- - name: SELECT_RANDOM
- range: 20
- desc: 1 enables the random chunk length, 0 uses a constant chunk length
- default: 0
- - name: SEED
- range: 19..10
- desc: Seed for the random number generator, should not be 0
- default: 0x200
- - name: POLYNOMIAL
- range: 9..0
- desc: POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
- default: 0x240
-
-
-#Registers that are replicated 24 times under Generators:
-FELIG_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_DATA_GEN_CONFIG
- format_name: FELIG_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_DATA_GEN_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: USERDATA
- range: 63..48
- default: 0
- desc: Sets static payload word. When PATTERN_SEL=1.
- - name: CHUNK_LENGTH
- range: 47..32
- default: 0
- desc: FELIG data generator chunk-length in bytes.
- - name: RESET
- range: 19..15
- default: 0
- desc: FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- - name: SW_BUSY
- range: 14..10
- default: 0
- desc: FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
- - name: DATA_FORMAT
- range: 9..5
- default: 0
- desc: FELIG data generator format. 0:8b10b, 1:direct.
- - name: PATTERN_SEL
- range: 4..0
- default: 0
- desc: FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
-
-FELIG_ELINK_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_CONFIG
- format_name: FELIG_ELINK_CONFIG_{index:02}
- type_name: FELIG_ELINK_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: ENDIAN_MOD
- range: 39..35
- default: 0
- desc: FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- - name: INPUT_WIDTH
- range: 34..30
- default: 0
- desc: FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- - name: OUTPUT_WIDTH
- range: 9..0
- default: 0
- desc: FELIG elink data output width.
-
-FELIG_ELINK_ENABLE_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ELINK_ENABLE
- format_name: FELIG_ELINK_ENABLE_{index:02}
- type_name: FELIG_ELINK_ENABLE
- desc: FELIG specific configuration registers
- bitfield:
- - range: 39..0
- default: 0
- desc: FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
-
-FELIG_LANE_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_LANE_CONFIG
- format_name: FELIG_LANE_CONFIG_{index:02}
- type_name: FELIG_LANE_CONFIG
- desc: FELIG specific configuration registers
- bitfield:
- - name: B_CH_BIT_SEL
- range: 63..42
- default: 0
- desc: When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- - name: A_CH_BIT_SEL
- range: 41..35
- default: 0
- desc: Selects the bit from the received FELIX data from which to extract the L1A.
- - name: LB_FIFO_DELAY
- range: 34..30
- default: 0
- desc: When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- - name: ELINK_SYNC
- range: 7..7
- default: 0
- desc: When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- - name: PICXO_OFFEST_EN
- range: 6..6
- default: 0
- desc: FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- - name: PI_HOLD
- range: 5..5
- default: 0
- desc: FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- - name: GBT_LB_ENABLE
- range: 4..4
- default: 0
- desc: FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- - name: GBH_LB_ENABLE
- range: 3..3
- default: 0
- desc: FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- - name: L1A_SOURCE
- range: 2..2
- default: 0
- desc: FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- - name: GBT_EMU_SOURCE
- range: 1..1
- default: 0
- desc: FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- - name: FG_SOURCE
- range: 0..0
- default: 0
- desc: FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
-
-FELIG_MON_TTC_0_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_0
- format_name: FELIG_MON_TTC_0_{index:02}
- type_name: FELIG_MON_TTC_0
- desc: FELIG specific configuration registers
- bitfield:
- - name: L1ID
- range: 63..40
- default: 0
- desc: Live TTC data monitor.
- - name: XL1ID
- range: 39..32
- default: 0
- desc: Live TTC data monitor.
- - name: BCID
- range: 31..20
- default: 0
- desc: Live TTC data monitor.
- - name: RESERVED0
- range: 19..16
- default: 0
- desc: Live TTC data monitor.
- - name: LEN
- range: 15..8
- default: 0
- desc: Live TTC data monitor.
- - name: FMT
- range: 7..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_TTC_1_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_TTC_1
- format_name: FELIG_MON_TTC_1_{index:02}
- type_name: FELIG_MON_TTC_1
- desc: FELIG specific configuration registers
- bitfield:
- - name: RESERVED1
- range: 63..48
- default: 0
- desc: Live TTC data monitor.
- - name: TRIGGER_TYPE
- range: 47..32
- default: 0
- desc: Live TTC data monitor.
- - name: ORBIT
- range: 31..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_COUNTERS_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_COUNTERS
- format_name: FELIG_MON_COUNTERS_{index:02}
- type_name: FELIG_MON_COUNTERS
- desc: FELIG specific configuration registers
- bitfield:
- - name: SLIDE_COUNT
- range: 63..32
- default: 0
- desc: Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- - name: FC_ERROR_COUNT
- range: 31..0
- default:
- desc: When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
-
-FELIG_MON_FREQ_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_FREQ
- format_name: FELIG_MON_FREQ_{index:02}
- type_name: FELIG_MON_FREQ
- desc: FELIG specific configuration registers
- bitfield:
- - name: TX
- range: 63..32
- default: 0
- desc: FELIG regenerated TX clock frequency[Hz].
- - name: RX
- range: 31..0
- default: 0
- desc: FELIG recovered RX clock frequency[Hz].
-
-FELIG_MON_L1A_ID_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_L1A_ID
- format_name: FELIG_MON_L1A_ID_{index:02}
- type_name: FELIG_MON_L1A_ID
- desc: FELIG specific configuration registers
- bitfield:
- - range: 31..0
- default: 0
- desc: FELIG's last L1 ID.
-
-FELIG_MON_PICXO_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_PICXO
- format_name: FELIG_MON_PICXO_{index:02}
- type_name: FELIG_MON_PICXO
- desc: FELIG specific configuration registers
- bitfield:
- - name: VLOT
- range: 53..32
- default: 0
- desc: Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- - name: ERROR
- range: 20..0
- default: 0
- desc: Value indicates RX to TX frequency tracking error.
-
-FELIG_ITK_STRIPS_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- entries:
- - name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG
- format_name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG
- desc: ITk Strips emulator specific configuration test registers
- bitfield:
- - name: ITKS_FIFO_CTL
- range: 19..17
- default: 0
- desc: data fifo control 2:rst 1:rd 0:wr.
- - name: ITKS_FIFO_DATA
- range: 16..0
- default: 0
- desc: itks emu data 16:last word 15-0:data word
-
-FELIG_MON_ITK_STRIPS_ARR:
- number: 24
- type: R
- entries:
- - name: FELIG_MON_ITK_STRIPS
- format_name: FELIG_MON_ITK_STRIPS_{index:02}
- type_name: FELIG_MON_ITK_STRIPS
- desc: ITk Strips emulator specific status registers
- bitfield:
- - name: ITKS_FIFO_STATUS
- range: 2..0
- default: 0
- desc: data fifo status 2:write done 1:full 0:empty.
-
-
-
-Wishbone:
- desc: Wishbone
- endpoints: 0
- entries:
- - name: WISHBONE_CONTROL
- type: W
- bitfield:
- - range: 32
- name: WRITE_NOT_READ
- desc: wishbone write command wishbone read command
- - range: 31..0
- name: ADDRESS
- desc: Slave address for Wishbone bus
- - name: WISHBONE_WRITE
- type: T
- bitfield:
- - range: any
- type: T
- value: 1
- name: WRITE_ENABLE
- desc: Any write to this register triggers a write to the Wupper to Wishbone fifo
- - range: 32
- name: FULL
- type: R
- - range: 31..0
- name: DATA
- type: W
- - name: WISHBONE_READ
- type: T
- bitfield:
- - range: any
- type: T
- value: 1
- name: READ_ENABLE
- desc: Any write to this register triggers a read from the Wishbone to Wupper fifo
- - range: 32
- name: EMPTY
- type: R
- desc: Indicates that the Wishbone to Wupper fifo is empty
- - range: 31..0
- name: DATA
- type: R
- desc: Wishbone read data
- - name: WISHBONE_STATUS
- type: R
- bitfield:
- - range: 4
- name: INT
- desc: interrupt
- - range: 3
- name: RETRY
- desc: Interface is not ready to accept data cycle should be retried
- - range: 2
- name: STALL
- desc: When pipelined mode slave can't accept additional transactions in its queue
- - range: 1
- name: ACKNOWLEDGE
- desc: Indicates the termination of a normal bus cycle
- - range: 0
- name: ERROR
- desc: Address not mapped by the crossbar
-
-DecodingControlsAndMonitors:
- desc: Decoding block
- endpoints: 0,1
- entries:
- - ref: DECODING_LINK_STATUS_ARR
-
-DECODING_LINK_STATUS_ARR:
- number: 24
- type: R
- entries:
- - name: DECODING_LINK_ALIGNED
- format_name: DECODING_LINK_ALIGNED_{index:02}
- type_name: DECODING_LINK_ALIGNED
- desc: Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- bitfield:
- - range: 57..0
-
-
-#EncodingControlsAndMonitors:
-# desc: Encoding block
-# endpoints: 0,1
-# entries:
-
-
-
diff --git a/sources/templates/yaml/registers-5.0.yaml b/sources/templates/yaml/registers-5.0.yaml
deleted file mode 100644
index 360acb9e0bfbc0fa1c01a44be05de48445d87fa2..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-5.0.yaml
+++ /dev/null
@@ -1,4248 +0,0 @@
-Registers:
- version: '5.0'
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: CRToHostControlsAndMonitors
- record_name: register_map_crtohost_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: CRFromHostControlsAndMonitors
- record_name: register_map_crfromhost_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: DecodingControlsAndMonitors
- record_name: register_map_decoding_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: EncodingControlsAndMonitors
- record_name: register_map_encoding_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: FrontendEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: LinkWrapperMonitors
- record_name: register_map_link_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: TTCBUSYControlsAndMonitors
- record_name: register_map_ttc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: LTITTCBUSYControlsAndMonitors
- record_name: register_map_ltittc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: XOFF_BUSYControlsAndMonitors
- record_name: register_map_xoff_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: Generators
- record_name: register_map_generators
- bitfield:
- - range: 0..0
- type: R
- - name: Wishbone
- record_name: wishbone_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: MRODmonitors
- record_name: regmap_mrod_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: IPBus
- record_name: ipbus_monitor
- bitfield:
- - range: 0..0
- type: R
-
-#Bar0 contains the registers dedicated to Wupper. Please only edit registers in Bar2
-#Registers in this group will not be generated with WupperCodeGen
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_RESET
- offset: 0x420
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
- - name: BUSY_THRESHOLD_ASSERT
- type: W
- desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
- default: 0x6400000
- bitfield:
- - range: 63..0
-
- - name: BUSY_THRESHOLD_NEGATE
- type: W
- desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
- default: 0x6E00000
- bitfield:
- - range: 63..0
-
- - name: BUSY_STATUS
- type: R
- bitfield:
- - range: 0
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
- - name: PC_PTR_GAP
- type: W
- desc: This is the minimum value that the pc_pointer in a descriptor has to decrease in order to flip the evencycle_pc bit
- default: 0x1000000
- bitfield:
- - range: 63..0
-
- - name: TOHOSTFIFO_EMPTY
- type: R
- desc: Empty flags of the ToHost FIFOs in Wupper
- bitfield:
- - range: 3..0
-
- - name: TOHOSTFIFO_PEMPTY
- type: R
- desc: Programmable empty flags of the ToHost FIFOs in Wupper
- bitfield:
- - range: 3..0
-
- - name: FROMHOSTFIFO_FULL
- type: R
- desc: Full flag of the FromHost FIFO in Wupper
- bitfield:
- - range: 0
-
- - name: FROMHOSTFIFO_PFULL
- type: R
- desc: Programmable full flag of the FromHost FIFO in Wupper
- bitfield:
- - range: 0
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: SW_POINTER
- desc: Pointer controlled by the software, indicating read or write status for circular DMA
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- type: R
- name: FROMHOST
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: FW_POINTER
- desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
-
-
-#Bar1 contains the registers dedicated to the Wupper interrupg controller.
-#Please only edit registers in Bar2.
-#Registers in this group will not be generated with WupperCodeGen
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 16
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-#Bar 2 contains application specific registers, used in the example application.
-#Registers in this group (and it's referenced subroups) will be generated with
-#WupperCodeGen for wupper Firmware, Software and Documentation
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CRToHostControlsAndMonitors
- offset: 0x0800
- - ref: CRFromHostControlsAndMonitors
- offset: 0x1000
- - ref: DecodingControlsAndMonitors
- offset: 0x1800
- - ref: EncodingControlsAndMonitors
- offset: 0x3000
- - ref: FrontendEmulatorControlsAndMonitors
- offset: 0x4000
- - ref: LinkWrapperControls
- offset: 0x5000
- - ref: LinkWrapperMonitors
- offset: 0x6000
- - ref: TTCBUSYControlsAndMonitors
- offset: 0x7000
- - ref: XOFF_BUSYControlsAndMonitors
- offset: 0x8000
- - ref: LTITTCBUSYControlsAndMonitors
- offset: 0x8800
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x9000
- - ref: Generators
- offset: 0xA000
- - ref: Wishbone
- offset: 0xC000
- - ref: IPBus
- offset: 0xC800
- - ref: ITK_STRIPS_CTRL # ITk strips global controls
- offset: 0xD000
- - ref: MRODregisters
- offset: 0xF000
- - ref: MRODmonitors
- offset: 0xF800
-
-
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned({{ tree.version|version }},16))
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_COMMIT_TIME
- offset: 0x30
- bitfield:
- - range: 39..0
- value: COMMIT_DATETIME
- desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_TAG
- bitfield:
- - range: 63..0
- value: GIT_TAG(63 downto 0)
- desc: String containing the current GIT TAG
-
- - name: GIT_COMMIT_NUMBER
- bitfield:
- - range: 31..0
- value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
- desc: Number of GIT commits after current GIT_TAG
-
- - name: GIT_HASH
- bitfield:
- - range: 31..0
- value: GIT_HASH(159 downto 128)
- desc: Short GIT hash (32 bit)
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 35..32
- name: TRICKLE_DESCRIPTOR_INDEX
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,4))
- desc: Index of the (first if more than one) Trickle descriptor
- - range: 31..28
- name: FROMHOST_DESCRIPTOR_INDEX
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS-1,4))
- desc: Index of the (first if more than one) FromHost descriptor
- - range: 27..24
- name: TRICKLE_DESCRIPTORS
- value: std_logic_vector(to_unsigned(1,4))
- desc: Number of Trickle descriptors
- - range: 23..20
- name: FROMHOST_DESCRIPTORS
- value: std_logic_vector(to_unsigned(1,4))
- desc: Number of FromHost descriptors
- - range: 19..16
- name: TOHOST_DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS-1,4))
- desc: Number of ToHost descriptors
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors Tohost + FromHost excluding trickle descriptor
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT or FULL mode Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): FLX709, VC709
- - 710 (0x2c6): FLX710, HTG710
- - 711 (0x2c7): FLX711, BNL711
- - 712 (0x2c8): FLX712, BNL712
- - 128 (0x080): FLX128, VCU128
- - 180 (0x0B4): FLX180, VMK180
- - 181 (0x0B5): FLX181, BNL181
- - 182 (0x0B6): FLX182, BNL182
-
- - name: GENERATE_GBT
- offset: 0xc0
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: GENERATE_TTC_EMU
- type: R
- bitfield:
- - range: 1
- type: R
- desc: 1 when TTC emulator is generated
-
- - offset: 0x100
- ref: INCLUDE_EGROUPS
-
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: FIRMWARE_MODE
- type: R
- offset: 0x190
- bitfield:
- - range: 4..0
- desc: |
- 0: GBT mode
- 1: FULL-GBT
- 2: LTDB mode (GBT mode with only IC and TTC links)
- 3: FEI4 mode
- 4: ITK Pixel
- 5: ITK Strip
- 6: FELIG GBT
- 7: FULL mode emulator
- 8: FELIX_MROD mode
- 9: lpGBT mode
- 10: 25G Interlaken
- 11: FELIG LPGBT
- 12: HGTD_LUMI
- 13: BCMPRIME
- 14: FELIG_PIXEL
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
- - name: BLOCKSIZE
- type: R
- desc: Number of bytes in a block
- bitfield:
- - range: 15..0
-
- - name: PCIE_ENDPOINT
- type: R
- desc: Indicator of the PCIe endpoint on BNL71x cards with two endpoints. 0 or 1
- bitfield:
- - range: 0
- value: std_logic_vector(to_unsigned(PCIE_ENDPOINT, 1))
-
- - name: CHUNK_TRAILER_32B
- type: R
- desc: Indicator that the chunk trailer is in the new 32-bit format
- bitfield:
- - range: 0
-
- - name: NUMBER_OF_PCIE_ENDPOINTS
- type: R
- desc: Number of PCIe endpoints on the card. The BNL71x cards have 2 endpoints
- bitfield:
- - range: 1..0
-
- - name: AXI_STREAMS_TOHOST
- type: R
- bitfield:
- - range: 23..16
- name: IC_INDEX
- desc: The AXIs ID (EPath-ID) of the ToHost IC E-Link
- - range: 15..8
- name: EC_INDEX
- desc: The AXIs ID (EPath-ID) of the ToHost EC E-Link
- - range: 7..0
- name: NUMBER_OF_STREAMS
- desc: Total number of AXIs IDs (EPath-IDs) per physical link ToHost
-
- - name: AXI_STREAMS_FROMHOST
- type: R
- bitfield:
- - range: 23..16
- name: IC_INDEX
- desc: The AXIs ID (EPath-ID) of the FromHost IC E-Link
- - range: 15..8
- name: EC_INDEX
- desc: The AXIs ID (EPath-ID) of the FromHost EC E-Link
- - range: 7..0
- name: NUMBER_OF_STREAMS
- desc: Total number of AXIs IDs (EPath-IDs) per physical link FromHost
-
- - name: FROMHOST_DATA_FORMAT
- type: R
- desc: |
- 0: The data format is as it was in phase1, supporting only multiples of 2 bytes
- 1: FromHost header uses a 5-bit length field as described in FLX-1355
- 2: FromHost header is 32-bit and the packet length is 256-bit (32 bytes) including the header FLX-1601
- 3: FromHost header is 32-bit and the packet length is 512-bit (32 bytes) including the header FLX-1601
- bitfield:
- - range: 1..0
-
- - name: FULLMODE_HALFRATE
- type: R
- desc: If set to 1 the FULL mode firmware is running at 4.8Gb instead of the default 9.6Gb
- bitfield:
- - range: 0
-
- - name: SUPPORT_HDLC_DELAY
- type: R
- desc: The HDLC encoders can offload a 1us delay as described in FLX-1826
- bitfield:
- - range: 0
-
-
-INCLUDE_EGROUPS:
- number: 7
- entries:
- - format_name: INCLUDE_EGROUP_{index}
- name: INCLUDE_EGROUP
- type_name: INCLUDE_EGROUP
- type: R
- bitfield:
- - range: 9
- name: TOHOST_32
- desc: ToHost EPATH32 is included in this EGROUP
- - range: 8
- name: FROMHOST_02
- desc: FromHost EPATH02 is included in this EGROUP
- - range: 7
- name: FROMHOST_04
- desc: FromHost EPATH04 is included in this EGROUP
- - range: 6
- name: FROMHOST_08
- desc: FromHost EPATH8 is included in this EGROUP
- - range: 5
- name: FROMHOST_HDLC
- desc: FromHost HDLC is included in this EGROUP
- - range: 4
- name: TOHOST_02
- desc: ToHost EPATH02 is included in this EGROUP
- - range: 3
- name: TOHOST_04
- desc: ToHost EPATH04 is included in this EGROUP
- - range: 2
- name: TOHOST_08
- desc: ToHost EPATH08 is included in this EGROUP
- - range: 1
- name: TOHOST_16
- desc: ToHost EPATH16 is included in this EGROUP
- - range: 0
- name: TOHOST_HDLC
- desc: ToHost HDLC is included in this EGROUP
-
-
-CRToHostControlsAndMonitors:
- group: CRTHC
- desc: Central Router ToHost Controls and Monitors
- endpoints: 0,1
- entries:
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
- - name: CRTOHOST_FIFO_STATUS
- type: W
- descr: Status of the width matching FIFOs in the CRToHost block
- bitfield:
- - range: any
- name: CLEAR
- type: T
- desc: Any write to this register clears the latched FULL flags
- value: 1
- - range: 47..24
- type: R
- name: FULL
- desc: Every bit represents the full flag of a channel FIFO
- - range: 23..0
- type: R
- name: FULL_LATCHED
- desc: like FULL but a latched state, clear by writing to this register
- - name: CRTOHOST_DMA_DESCRIPTOR_1
- type: W
- bitfield:
- - range: any
- name: WR_EN
- type: T
- value: 1
- desc: Any write to this register assigns the DMA ID to the AXIS_ID set in CRTOHOST_DMA_DESCRIPTOR_2.AXIS_ID
- - range: 2..0
- name: DESCR
- desc: Target descriptor
- - name: CRTOHOST_DMA_DESCRIPTOR_2
- type: W
- bitfield:
- - range: 13..11
- name: DESCR_READ
- type: R
- desc: Read back the value of the descriptor assigned to AXIS_ID
- - range: 10..0
- name: AXIS_ID
- desc: ID of the AXI stream (E-Path ID) to associate with CRTOHOST_DMA_DESCRIPTOR_1.DESCR
- type: W
- - ref: CRTOHOST_INSTANT_TIMEOUT_ENA_GEN
- - name: DISCARD_DATA_FOR_DESCR
- type: W
- bitfield:
- - range: 15..8
- name: FIFO_FULL
- desc: Discard data for a given DMA channel when Wupper FIFO is full, even if DMA is enabled
- default: 0
- - range: 7..0
- name: DMA_DISABLED
- desc: Discard data for a given DMA channel when Wupper FIFO is full, and the descriptor is not enabled
- default: 0xFF
-
-CRTOHOST_INSTANT_TIMEOUT_ENA_GEN:
- number: 24
- type: W
- entries:
- - name: CRTOHOST_INSTANT_TIMEOUT_ENA
- format_name: CRTOHOST_INSTANT_TIMEOUT_ENA_{index:02}
- type_name: CRTOHOST_INSTANT_TIMEOUT_ENA
- desc: Enable instant timeout after the first data arrives in CRToHost.
- type: W
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 41..0
-
-CRFromHostControlsAndMonitors:
- group: CRFHC
- desc: Central Router FromHost Controls and Monitors
- endpoints: 0,1
- entries:
- - name: CRFROMHOST_FIFO_STATUS
- type: W
- descr: Status of the width matching FIFOs in the CRFromHost block
- bitfield:
- - range: any
- name: CLEAR
- type: T
- desc: Any write to this register clears the latched FULL flags
- value: 1
- - range: 47..24
- type: R
- name: FULL
- desc: Every bit represents the full flag of a channel FIFO
- - range: 23..0
- type: R
- name: FULL_LATCHED
- desc: like FULL but a latched state, clear by writing to this register
- - ref: BROADCAST_ENABLE_GEN
- - name: CRFROMHOST_RESET
- descr: Self clearing reset for CRFromHost and Encoding
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
-
-
-BROADCAST_ENABLE_GEN:
- number: 24
- type: W
- entries:
- - name: BROADCAST_ENABLE
- format_name: BROADCAST_ENABLE_{index:02}
- type_name: BROADCAST_ENABLE
- desc: Enable path to be included in a broadcast message.
- type: W
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 41..0
-
-DecodingControlsAndMonitors:
- desc: Decoding block
- endpoints: 0,1
- entries:
- - name: ELINK_REALIGNMENT
- type: W
- fw_modes: 0,2,3,4,5,6,9,11,12,13
- bitfield:
- - range: any
- name: CLEAR_REALIGNMENT_STATUS
- type: T
- value: 1
- desc: Clears the ELINK Realignment event flags
- - range: 0
- name: ENABLE
- default: 1
- desc: Enable realignment mechanism in 8b10b E-Links after illegal character reception.
-
- - ref: ELINK_REALIGNMENT_STATUS_GEN
- - ref: ELINK_REALIGNMENT_COUNT_GEN
- - ref: PATH_HAS_STREAM_ID
- offset: 0x800
- - ref: DECODING_LINK_STATUS_ARR
- - ref: DECODING_EGROUP_CTRL_GEN
- - ref: MINI_EGROUP_TOHOST_GEN
- - name: TTC_TOHOST_ENABLE
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 0
- default: 1
- - name: DECODING_REVERSE_10B
- desc: |
- Reverse 10-bit word of elink data for 8b10b E-links
- 1: Receive 10-bit word in ToHost E-Paths, MSB first
- 0: Receive 10-bit word in ToHost E-Paths, LSB first
- type: W
- fw_modes: 0,2,3,4,5,6,9,11,12,13
- bitfield:
- - range: 0
- default: 1
- - name: DECODING_ENDIANNESS_FULL_MODE
- desc: |
- Specify the byte order in FULL mode
- 1: Big-endian
- 0: Little-endian
- type: W
- fw_modes: 1
- bitfield:
- - range: 0
- type: W
- default: 0
-
-# - ref: RD53B_PROCESSOR_GEN
- - ref: YARR_DEBUG_ALLEGROUP_TOHOST_GEN
- desc: Count receive packets of a given value
- - ref: PATH_ERRORS
- - name: INTERLAKEN_CONTROL
- desc: Configures Interlaken decoder
- type: W
- fw_modes: 10
- bitfield:
- - range: 12
- type: R
- name: HEALTH_INTERFACE
- default: 1
- desc: Automatically detect the lane number in the interlaken descrambler
- - range: 11..0
- name: PACKET_LENGTH
- desc: Lenth of an interlaken metaframe
- default: 2024
- - ref: INTERLAKEN_STATUS_GEN
- - ref: SUPER_CHUNK_FACTOR_GEN
- offset: 0x15E0
- - ref: DECODING_LINK_CB_GEN
- - name: DECODING_MASK64B66BKBLOCK
- desc: Mask User K-Block based on its block number (see sp011)
- type: W
- fw_modes: 4
- bitfield:
- - range: 3..0
- default: 10
- - name: DECODING_DISEGROUP
- desc: Disable egroups for debugging purposes
- type: W
- bitfield:
- - range: 6..0
- default: 0
-
- - name: FULLMODE_32B_SOP
- type: W
- desc: When set to 1, use 32-bit 0x0000003C as start of chunk, otherwise only 8-bit 0x3C (FULL mode only)
- fw_modes: 1
- bitfield:
- - range: 0
- default: 0
-
- - name: DECODING_HGTD_ALTIROC
- type: W
- desc: Set to 1 to use HGTD Altiroc K characters in the 8b10b decoders (LPGBT firmware mode)
- fw_modes: 9
- bitfield:
- - range: 0
- default: 0
-
- - name: DECODING_HGTD_LUMI_CONF
- type: W
- desc: HGTD Luminosity firmware configuration
- fw_modes: 12
- bitfield:
- - range: 36
- name: DEBUG_DATASOURCE
- default: 0
- desc: enable local data source for debugging
- - range: 35
- name: RAW_MODE
- default: 0
- desc: enable RAW mode (just forwarding 6b8b data)
- - range: 34..25
- name: LHC_TURNS
- default: 100
- desc: number of LHC turns to aggregate
- - range: 24..16
- name: TRIG_LAT
- default: 0
- desc: trigger latency for per-event luminosity
- - range: 15..0
- name: SYNC_WORD
- default: 0x4778
- desc: sync word for luminosity stream
-
-ELINK_REALIGNMENT_STATUS_GEN:
- endpoints: 0, 1
- number: 12
- fw_modes: 0,2,3,4,5,6,9,11,12,13
- entries:
- - name: ELINK_REALIGNMENT_STATUS
- type_name: ELINK_REALIGNMENT_STATUS
- format_name: ELINK_REALIGNMENT_STATUS_{index:02}
- generate: GBT_NUM > {index:1}
- desc: |
- A realignment event due to an illegal 8b10b symbol has occurred.
- 1 bit per Epath.
- Clear status by writing to ELINK_REALIGNMENT.CLEAR_REALIGNMENT_STATUS
- bitfield:
- - range: 41..0
-
-ELINK_REALIGNMENT_COUNT_GEN:
- endpoints: 0, 1
- number: 12
- fw_modes: 0,2,3,4,5,6,9,11,12,13
- entries:
- - name: ELINK_REALIGNMENT_COUNT
- type_name: ELINK_REALIGNMENT_COUNT
- format_name: ELINK_REALIGNMENT_COUNT_{index:02}
- generate: GBT_NUM > {index:1}
- desc: |
- A realignment event due to an illegal 8b10b symbol on any E-Link in the link increments the counter.
- Clear status by writing to ELINK_REALIGNMENT.CLEAR_REALIGNMENT_STATUS
- bitfield:
- - range: 31..0
-
-PATH_HAS_STREAM_ID:
- number: 24
- generate: GBT_NUM > {index:1}
- entries:
- - name: HAS_STREAM_ID
- format_name: LINK_{index:02}_HAS_STREAM_ID
- type_name: HAS_STREAM_ID
- type: W
- bitfield:
- - range: 55..48
- name: EGROUP6
- default: 0x0
- desc: EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- - range: 47..40
- name: EGROUP5
- default: 0x0
- desc: EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- - range: 39..32
- name: EGROUP4
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 31..24
- name: EGROUP3
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 23..16
- name: EGROUP2
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 15..8
- name: EGROUP1
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 7..0
- name: EGROUP0
- default: 0x0
- desc: EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
-
-DECODING_LINK_STATUS_ARR:
- number: 24
- type: R
- entries:
- - name: DECODING_LINK_ALIGNED
- format_name: DECODING_LINK_ALIGNED_{index:02}
- type_name: DECODING_LINK_ALIGNED
- desc: Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- bitfield:
- - range: 57..0
-
-DECODING_EGROUP_CTRL_GEN:
- number: 12
- format_name: DECODING_EGROUP_GEN
- generate: GBT_NUM > {index:1}
- entries:
- - ref: DECODING_EGROUP
-
-DECODING_EGROUP:
- number: 7
- format_name: LINK{index:02}
- type_name: DECODING_EGROUP
- entries:
- - name: EGROUP
- format_name: DECODING_{parent}_{name}{index:1}_CTRL
- type_name: DECODING_EGROUP_CTRL
- desc: Contols Egroup for lpGBT and GBT based links
- type: W
- bitfield:
- - range: 59
- name: ENABLE_TRUNCATION
- type: W
- desc: Enable truncation mechanism in HDLC decoder for chunks > 12 bytes
- default: 0
- - range: 58..51
- name: EPATH_ALMOST_FULL
- type: R
- desc: FIFO full indication
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..11
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 4 bits per E-path
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- 3: TTC
- 4: ITk Strips 8b10b
- 5: ITk Pixel
- 6: Endeavour
- 7-15: reserved
- default: 0x11111111
- - range: 10..8
- name: EPATH_WIDTH
- default: 0
- desc: Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- - range: 7..0
- name: EPATH_ENA
- desc: Enable bits per EPATH
- default: 0
-
-MINI_EGROUP_TOHOST_GEN:
- number: 24
- type: W
- fw_modes: 0,2,3,4,5,9,12,13
- entries:
- - name: MINI_EGROUP_TOHOST
- format_name: MINI_EGROUP_TOHOST_{index:02}
- type_name: MINI_EGROUP_TOHOST
- desc: Configures the ToHost Mini egroup
- type: W
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 15
- name: ENABLE_AUX_TRUNCATION
- type: W
- desc: Enable truncation mechanism in HDLC decoder for chunks > 12 bytes
- default: 0
- - range: 14
- name: ENABLE_IC_TRUNCATION
- type: W
- desc: Enable truncation mechanism in HDLC decoder for chunks > 12 bytes
- default: 0
- - range: 13
- name: ENABLE_EC_TRUNCATION
- type: W
- desc: Enable truncation mechanism in HDLC decoder for chunks > 12 bytes
- default: 0
- - range: 12
- type: R
- name: AUX_ALMOST_FULL
- desc: Indicator that the AUX path FIFO is almost full
- - range: 11
- name: AUX_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 10
- name: AUX_ENABLE
- desc: Enables the AUX channel
- default: 1
- - range: 9
- type: R
- name: IC_ALMOST_FULL
- desc: Indicator that the IC path FIFO is almost full
- - range: 8
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 7
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 6
- type: R
- name: EC_ALMOST_FULL
- desc: Indicator that the EC path FIFO is almost full
- - range: 5
- name: EC_BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 4..1
- name: EC_ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: EC_ENABLE
- desc: Enables the EC channel
- default: 1
-
-
-#RD53B_PROCESSOR_GEN:
-# number: 64
-# entries:
-# - name: RD53B_PROCESSOR
-# format_name: RD53B_PROCESSOR_{index:02}
-# type_name: RD53B_PROCESSOR
-# bitfield:
-# - range: 3
-# name: ENABLE_MULTICHIP
-# - range: 2
-# name: ENABLE_BINARYTREE
-# - range: 1
-# name: ENABLE_TOT
-# - range: 0
-# name: DROP_TOT
-
-SUPER_CHUNK_FACTOR_GEN:
- number: 12
- entries:
- - name: SUPER_CHUNK_FACTOR_LINK
- format_name: SUPER_CHUNK_FACTOR_LINK_{index:02}
- type_name: SUPER_CHUNK_FACTOR_LINK
- type: W
- desc: number of chunks glued together
- bitfield:
- - range: 7..0
- default: 1
-
-DECODING_LINK_CB_GEN:
- number: 12
- fw_modes: 4
- entries:
- - name: DECODING_LINK_CB
- format_name: DECODING_LINK_{index:02}_CB
- type_name: DECODING_LINK_CB
- type: W
- bitfield:
- - name: DESKEWED
- range: 61..4
- type: R
- desc: |
- Every bit corresponds to an E-link on one (lp)GBT frame.
- Register indicates whether the E-link has been de-skewed in the channel.
- E-link are grouped in a channel according to CBOPT
- - name: CBOPT
- range: 3..0
- desc: |
- Channel bonding option
- 0: no bonding
- 3: Bonding 0/1/2 3/4/5
- other values: reserved
- default: 0
-
-YARR_DEBUG_ALLEGROUP_TOHOST_GEN:
- number: 12
- fw_modes: 4,5
- entries:
- - name: YARR_DEBUG_ALLEGROUP_TOHOST
- format_name: YARR_DEBUG_ALLEGROUP_TOHOST_{index:02}
- type_name: YARR_DEBUG_ALLEGROUP_TOHOST
- type: W
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 63..32
- name: REF_PACKET
- type: W
- desc: Reference packet to be matched
- default: 0x02000000
- - range: 31..0
- name: CNT_RX_PACKET
- type: R
- desc: Count packets of a given value
-
-YARR_DEBUG_ALLEGROUP_FROMHOST_GEN:
- fw_modes: 4,5
- number: 12
- entries:
- - name: YARR_DEBUG_ALLEGROUP_FROMHOST1
- format_name: YARR_DEBUG_ALLEGROUP_FROMHOST1_{index:02}
- type_name: YARR_DEBUG_ALLEGROUP_FROMHOST1
- type: W
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 48
- type: W
- name: RD53A_AZ_EN
- desc: Auto zeroing module enable
- default: 0
- - range: 47..16
- type: R
- name: CNT_TRIG_CMD
- desc: Number of issued triggers via cmd
- - range: 15..8
- type: R
- name: ERR_GENCALTRIG_DLY
- desc: Number of mismatches between CNT_GENCALTRIG_DLY and REF_DLY_GENCALTRIG
- - range: 7..0
- type: W
- name: REF_DLY_GENCALTRIG
- desc: Reference distance between GenCal and First Trigger
- default: 0x0F
- - name: YARR_DEBUG_ALLEGROUP_FROMHOST2
- format_name: YARR_DEBUG_ALLEGROUP_FROMHOST2_{index:02}
- type_name: YARR_DEBUG_ALLEGROUP_FROMHOST2
- type: W
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 47..16
- type: R
- name: CNT_CMD
- desc: Number of issued commands
- - range: 15..0
- type: W
- name: REF_CMD
- desc: Cmd type to be counted. See RD53 Manual for list of allowed commands
- default: 0x6666
-
-PATH_ERRORS:
- number: 24
- generate: GBT_NUM > {index:1}
- entries:
- - name: LINK_ERRORS
- fw_modes: 0,4,5,9
- format_name: LINK_{index:02}_ERRORS
- type_name: LINK_ERRORS
- type: W
- bitfield:
- - range: 35
- name: CLEAR_COUNTERS
- type: W
- desc: Set to 1 to clear all counter values for all egroups in the link. Set to 0 to start counting errors.
- - range: 34..32
- name: EGROUP_SELECT
- desc: Errors for Egroup1
- type: W
- - range: 31..0
- name: COUNT
- desc: Errors for the selected egroup
- type: R
-
-
-INTERLAKEN_STATUS_GEN:
- number: 12
- generate: GBT_NUM > {index:1}
- entries:
- - name: INTERLAKEN_STATUS
- fw_modes: 4
- format_name: INTERLAKEN_LANE_{index:02}_STATUS
- type_name: INTERLAKEN_STATUS
- type: W
- fw_modes: 10
- bitfield:
- - range: any
- type: T
- name: CLEAR_STATUS
- value: 1
- - range: 8
- type: R
- name: DECODER_ERROR_SYNC
- desc: Sticky error bit, clear with CLEAR_STATUS
- - range: 7
- type: R
- name: DESCRAMBLER_ERROR_BADSYNC
- desc: Sticky error bit, clear with CLEAR_STATUS
- - range: 6
- type: R
- name: DESCRAMBLER_ERROR_STATEMISMATCH
- desc: Sticky error bit, clear with CLEAR_STATUS
- - range: 5
- type: R
- name: DESCRAMBLER_ERROR_NOSYNC
- desc: Sticky error bit, clear with CLEAR_STATUS
- - range: 4
- type: R
- name: BURST_CRC24_ERROR
- desc: Sticky CRC error bit, clear with CLEAR_STATUS
- - range: 3
- type: R
- name: META_CRC32_ERROR
- desc: Sticky CRC error bit, clear with CLEAR_STATUS
- - range: 2
- type: R
- name: HEALTH_LANE
- desc: Health bit for this lane
- - range: 1
- type: R
- name: DESCRAMBLER_ALIGNED
- desc: This channels descrambler is aligned
- - range: 0
- type: R
- name: DECODER_ALIGNED
- desc: This channels decoder is aligned
-
-
-
-EncodingControlsAndMonitors:
- desc: Encoding block
- endpoints: 0,1
- entries:
- - name: ENCODING_REVERSE_10B
- desc: Reverse 10-bit word of elink data for 8b10b E-links. 1 MSB first, 0 LSB first
- type: W
- fw_modes: 0,1,2,3,6,9,10,11,12
- bitfield:
- - range: 0
- default: 1
- - ref: ENCODING_EGROUP_CTRL_GEN
- - ref: MINI_EGROUP_FROMHOST_GEN
- - ref: ENCODING_EGROUP_CTRL_FEI4_GEN
- - ref: YARR_DEBUG_ALLEGROUP_FROMHOST_GEN
- desc: Count triggers, compare distance between GenCal and Trigger with reference. Check YARR doc
- - name: YARR_FROMHOST_CALTRIGSEQ_WE
- fw_modes: 4,5
- desc: enable to store CalPulse+Trigger Sequence into memory
- type: W
- bitfield:
- - range: 0
- default: 0
- - name: YARR_FROMHOST_CALTRIGSEQ_WRDATA
- fw_modes: 4,5
- desc: CalPulse+Trigger Sequence to be stored in memory
- type: W
- bitfield:
- - range: 15..0
- - name: YARR_FROMHOST_CALTRIGSEQ_WRADDR
- fw_modes: 4,5
- desc: memory address to store CalPulse+Trigger Sequence
- type: W
- bitfield:
- - range: 4..0
- - name: HGTD_ALTIROC_FASTCMD
- fw_modes: 9
- desc: Controls the HGTD Altiroc FASTCMD TTC encoder functionality (TTC option 8).
- type: W
- bitfield:
- - range: 14
- name: ALTIROC3_IDLE
- desc: 0 for ALTIROC2 10101100, 1 for ALTIROC3 11110000
- default: 0
- - range: 13
- name: USE_CAL
- desc: When set to 1, CAL will be sent on L1A, then after TRIG_DELAY BC clocks a TRIGGER. When 0, TRIGGER will be sent on L1A.
- default: 1
- - range: 12
- name: SYNCLUMI
- desc: Set to 1 to trigger a SYNCLUMI command, rising edge of this bit. Clear in software
- default: 0
- - range: 11
- name: GBRST
- desc: Set to 1 to trigger a GBRST command, rising edge of this bit. Clear in software
- default: 0
- - range: 10..0
- name: TRIG_DELAY
- desc: Number of BC clocks between CAL and TRIGGER command if USE_CAL is set to 1
- default: 5
- - name: ITKSTRIP_LCB_R3L1_ELINK_SWAP
- fw_modes: 5
- desc: Setting a bit, moves the LCB E-Link to the odd E-Link position and R3L1 to the even one on the lpGBT downlink. 4 bits per lpGBT link
- type: W
- bitfield:
- - range: 47..0
-
-
-
-ENCODING_EGROUP_CTRL_GEN:
- number: 12
- type: W
- generate: GBT_NUM > {index:1}
- entries:
- - ref: ENCODING_EGROUP
-
-
-ENCODING_EGROUP:
- number: 5
- format_name: LINK{index:02}
- entries:
- - name: ENCODING_EGROUP_CTRL
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: ENCODING_{parent}_EGROUP{index:1}_CTRL
- type_name: ENCODING_EGROUP_CTRL
- bitfield:
- - range: 63
- name: ENABLE_DELAY
- desc: Enable inter-packet delay generation in HDLC encoder
- default: 0x0
- - range: 62..59
- name: TTC_OPTION
- desc: Selects TTC bits sent to the E-link
- - range: 58..51
- name: EPATH_ALMOST_FULL
- type: R
- desc: Indiator that the EPATH FIFO is almost full
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..40
- name: EPATH_WIDTH
- default: 0x0
- desc: |
- Width of the Elinks in the egroup
- 0: 2 bit 80 Mb/s
- 1: 4 bit 160 Mb/s
- 2: 8 bit 320 Mb/s
- - range: 39..8
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 4 bits per E-Path
- 0: No encoding
- 1: 8b10b mode
- 2: HDLC mode
- 3: ITk Strip LCB
- 4: ITk Pixel
- 5: Endeavour
- 6: reserved
- 7: reserved
- greater than 7: TTC mode, see firmware Phase 2 specification doc
- default: 0x11111111
- - range: 7..0
- desc: Enable bits per E-PATH
- name: EPATH_ENA
-
-MINI_EGROUP_FROMHOST_GEN:
- number: 24
- type: W
- generate: GBT_NUM > {index:1}
- fw_modes: 0,1,2,3,4,5,9,10,12,13
- entries:
- - name: MINI_EGROUP_FROMHOST
- format_name: MINI_EGROUP_FROMHOST_{index:02}
- type_name: MINI_EGROUP_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 17..14
- name: AUX_ENCODING
- desc: Configures encoding of the AUX channel
- default: 0x2
- - range: 13
- name: ENABLE_DELAY
- desc: Enable inter-packet delay generation in HDLC encoder
- default: 0x0
- - range: 12
- name: AUX_ALMOST_FULL
- type: R
- desc: Indicator that the AUX Path FIFO is almost full
- - range: 11
- name: AUX_BIT_SWAPPING
- desc: "0: two input bits of AUX e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 10
- name: AUX_ENABLE
- desc: Enables the AUX channel
- default: 1
- - range: 9
- name: IC_ALMOST_FULL
- type: R
- desc: Indicator that the IC Path FIFO is almost full
- - range: 8
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 7
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 6
- name: EC_ALMOST_FULL
- type: R
- desc: Indicator that the EC Path FIFO is almost full
- - range: 5
- name: EC_BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: EC_ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: EC_ENABLE
- default: 1
-
-ENCODING_EGROUP_CTRL_FEI4_GEN:
- number: 12
- type: W
- fw_modes: 3
- generate: GBT_NUM > {index:1} and FIRMWARE_MODE = FIRMWARE_MODE_FEI4
- entries:
- - ref: ENCODING_EGROUP_FEI4
-
-
-ENCODING_EGROUP_FEI4:
- number: 5
- format_name: LINK{index:02}
- entries:
- - name: ENCODING_EGROUP_FEI4_CTRL
- desc: FEI4 encoder configuration registers.
- format_name: ENCODING_{parent}_EGROUP{index:1}_FEI4_CTRL
- type_name: ENCODING_EGROUP_FEI4_CTRL
- bitfield:
- - range: 11..9
- name: PHASE_DELAY1
- desc: phase delay of output data, with 320 Bb/s e-link 8 phases per BC
- - range: 8
- name: MANCHESTER_ENABLE1
- desc: enable manchester encoding
- - range: 7
- name: AUTOMATIC_MERGE_DISABLE1
- desc: Disable automatic merging
- - range: 6
- name: TTC_SELECT1
- desc: TTC/FromHost select (if automatic merging is disabled)
- - range: 5..3
- name: PHASE_DELAY0
- desc: phase delay of output data, with 320 Bb/s e-link 8 phases per BC
- - range: 2
- name: MANCHESTER_ENABLE0
- desc: enable manchester encoding
- - range: 1
- name: AUTOMATIC_MERGE_DISABLE0
- desc: Disable automatic merging
- - range: 0
- name: TTC_SELECT0
- desc: TTC/FromHost select (if automatic merging is disabled)
-
-FrontendEmulatorControlsAndMonitors:
- group: FEC
- desc: Frontend Emulator Controls and Monitors
- endpoints: 0, 1
- entries:
- - name: FE_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: EMU_TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
-
- - range: 0
- name: EMU_TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: FE_EMU_CONFIG
- type: W
- bitfield:
- - range: 54..47
- name: WE
- desc: write enable array, every bit is one emulator RAM block
- - range: 46..33
- name: WRADDR
- desc: write address bus
- - range: 32..0
- name: WRDATA
- desc: write data bus
-
- - name: FE_EMU_READ
- type: W
- bitfield:
- - range: 35..33
- name: SEL
- desc: Select ramblock to read back
- - range: 32..0
- name: DATA
- type: R
- desc: Read back ramblock at FE_EMU_CONFIG.WRADDR
-
- - name: FE_EMU_LOGIC
- type: W
- bitfield:
- - range: 33
- name: L1A_TRIGGERED
- desc: 1 Send a chunk on every L1A, 0 use the IDLES to determine the rate
- - range: 32
- name: ENA
- desc: Enable logic based FrontEnd emulator, instead of RAM based.
- - range: 31..16
- name: IDLES
- desc: Number of IDLE bytes between chunks.
- - range: 15..0
- name: CHUNK_LENGTH
- desc: Chunk length in bytes
-
- #Continue decoding here, as the decoding space is full.
- - ref: DECODING_BCM_PRIME_L1A_CONTROLS_GEN
- offset: 0x200
-
- - name: DECODING_BCM_PRIME_ONLY_L1A
- type: W
- desc: If enabled, the BCM_PRIME firmware, will only readout data when an L1A is sent.
- fw_modes: 13
- bitfield:
- - range: 0
- - name: DECODING_BCM_PRIME_EMU_BCID
- type: W
- fw_modes: 13
- desc: If enabled, the BCM_PRIME firmware will use internally generated BCIDs instead of the TTC one.
- bitfield:
- - range: 0
-
- - name: DECODING_BCM_PRIME_PUBLISH_ZEROS
- type: W
- fw_modes: 13
- desc: If enabled, the BCM_PRIME firmware publish empty data-events if they are matched with L1A
- bitfield:
- - range: 0
-
-
-
-DECODING_BCM_PRIME_L1A_CONTROLS_GEN:
- number: 24
- fw_modes: 13
- type: W
-
- entries:
- - name: DECODING_BCM_PRIME_L1A
- format_name: DECODING_BCM_PRIME_LINK_{index:02}_L1A
- type_name: DECODING_BCM_PRIME_L1A
-
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 9..5
- name: DELAY
- default: 5
- desc: The data in fiber is delayed N clock cycles to match with TTC L1A
- - range: 4..0
- name: WINDOW
- default: 5
- desc: The L1A signal is extended to cover multiple BCID's
-
-LinkWrapperControls:
- group: LWC
- desc: Link Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: LINK_FULLMODE_LTI
- fw_modes: 1, 7
- desc: Set to 1 to enable LTI format TTC distribution (8b10b at 9.6Gb) in the FULLMODE flavour, one bit per channel. Set to 0 for 4.8Gb GBT distribution
- type: W
- bitfield:
- - range: 23..0
- default: 0
-
- - name: GBT_CHANNEL_DISABLE
- offset: 0x0400
- bitfield:
- - range: 47..0
- desc: Disable selected lpGBT, GBT or FULL mode channel
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE_SELECT
- offset: 0x0480
- desc: RxSlide select [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXSLIDE_MANUAL
- desc: RxSlide select [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXUSRRDY
- desc: TxUsrRdy [47:0]
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_RXUSRRDY
- desc: RxUsrRdy [47:0]
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_SOFT_RESET
- desc: SOFT_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTTX_RESET
- desc: GTTX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTRX_RESET
- desc: GTRX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 59..48
- name: QPLL_RESET
- desc: QPLL_RESET [11:0]
- - range: 47..0
- name: CPLL_RESET
- desc: CPLL_RESET [47:0]
-
- - name: GBT_SOFT_TX_RESET
- offset: 0x0500
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_SOFT_RX_RESET
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_ODD_EVEN
- desc: OddEven [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TOPBOT
- desc: TopBot [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_TC_DLY_VALUE3
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [143:96]
-
- - name: GBT_TX_TC_DLY_VALUE4
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [191:144]
-
- - name: GBT_DATA_TXFORMAT1
- desc: DATA_TXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_TXFORMAT2
- desc: DATA_TXFORMAT [95:48]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT1
- desc: DATA_RXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT2
- desc: DATA_RXFORMAT [95:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_RESET
- desc: TX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_RESET
- desc: RX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_METHOD
- desc: TX time domain crossing method [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUTMUX_SEL
- desc: Descrambler output MUX selection [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TC_EDGE
- desc: Sampling edge selection for TX domain crossing [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for transmitter of GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_RXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for the receiver of the GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
- - name: LPGBT_FEC
- desc: |
- 0: FEC5
- 1: FEC12
- bitfield:
- - range: 47..0
- default: 0
-
- - name: LPGBT_DATARATE
- desc: |
- 0: 10.24 Gbps
- 1: 5.12 Gbps
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_TOHOST_FANOUT
- offset: 0x0700
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0x0
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_TOFRONTEND_FANOUT
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0x0
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
- - name: FULLMODE_AUTO_RX_RESET
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: Enable the Automatic RX Reset mechanism
- - range: 31..0
- name: TIMEOUT
- default: 0x00100000
- desc: Number of 40 MHz clock cycles until an unaligned link results in a reset pulse
-
- - ref: TCLINK_CNTRL_GEN
-
-TCLINK_CNTRL_GEN:
- desc: TClink status and control registers that dont have a default value
- number: 24
- endpoints: 0
- entries:
- - name: TCLINK_CONTROL
- format_name: TCLINK_CONTROL_{index:02}
- type_name: TCLINK_CONTROL
- type: W
- desc: tclink control register
- bitfield:
- - range: 63..16
- name: OFFSET_ERROR
- desc: Error-offset for phase-control Recommended to freeze with an initial value read
- - range: 15
- name: CLOSE_LOOP
- desc: Close TCLink loop (enables compensation)
- - range: 14..8
- name: TX_PI_PHASE_CALIB
- desc: UI alignment Tx PI calibrated phase
- - range: 7
- name: TX_UI_ALIGN_CALIB
- desc: UI alignment Tx PI activate
- - range: 6
- name: TX_FINE_REALIGN
- desc: Repeats fine alignment procedure
- - range: 5
- name: PS_STROBE
- desc: Shifts phase of transmitter serial data
- - range: 4
- name: PS_INC_NDEC
- desc: Shifts phase of transmitter serial data
- - range: 3
- name: MASTER_MGT_RX_READY
- desc: MGT rx is ready (used as reset)
-
-
-LinkWrapperMonitors:
- group: LWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- desc: TX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXRESET_DONE
- desc: RX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXFSMRESET_DONE
- desc: TX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXFSMRESET_DONE
- desc: RX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_LOCK
- bitfield:
- - range: 59..48
- name: QPLL_LOCK
- desc: QPLL LOCK [11:0]
- - range: 47..0
- name: CPLL_LOCK
- desc: CPLL LOCK [47:0]
-
- - name: GBT_RXCDR_LOCK
- desc: RX CDR LOCK [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CLK_SAMPLED
- desc: clk sampled [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_HEADER
- desc: RX IS HEADER [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_DATA
- desc: RX IS DATA [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_HEADER_FOUND
- desc: RX HEADER FOUND [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUT_MUX_STATUS
- desc: GBT output mux status [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ERROR
- desc: Error flags [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GBT_TOPBOT_C
- desc: TopBot_c [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
- - ref: GT_FEC_ERR_CNT_GEN
- - ref: GT_AUTO_RX_RESET_CNT_GEN
- - ref: TCLINK_MON_GEN
- - name: GBT_PLL_LOL_LATCHED
- type: W
- bitfield:
- - range: any
- name: CLEAR
- value: 1
- desc: Any write to this bitfield clears the latched LOL bits
- type: T
- - range: 59..48
- name: QPLL_LOL_LATCHED
- desc: Asserted when CPLL lock is lost, clear by writing to CLEAR
- type: R
- - range: 47..0
- name: CPLL_LOL_LATCHED
- desc: Asserted when CPLL lock is lost, clear by writing to CLEAR
- type: R
-
- - name: GBT_ALIGNMENT_LOST
- type: W
- bitfield:
- - range: any
- name: CLEAR
- value: 1
- desc: Any write to this bitfield clears the latched ALIGNMENT_LOST bits
- type: T
- - range: 47..0
- type: R
- name: ALIGNMENT_LOST
- desc: Asserted when GBT_ALIGNMENT_DONE bit is 0, clear by writing to CLEAR
-
-
-
-GT_FEC_ERR_CNT_GEN:
- desc: Counts the number of FEC errors in the (lp)GBT frame
- number: 24
- endpoints: 0
- entries:
- - name: GT_FEC_ERR_CNT
- format_name: GT_FEC_ERR_CNT_{index:02}
- type_name: GT_FEC_ERR_CNT
- desc: Counts the number of FEC errors in the given channel.
- fw_modes: 0,2,3,4,5,6,9,11,12,13
- type: R
- bitfield:
- - range: 31..0
-
-GT_AUTO_RX_RESET_CNT_GEN:
- desc: Counts the number of AUTO RX RESET events that happend on the FULLMODE, GBT or lpGBT link
- number: 24
- endpoints: 0
- entries:
- - name: GT_AUTO_RX_RESET_CNT
- format_name: GT_AUTO_RX_RESET_CNT_{index:02}
- type_name: GT_AUTO_RX_RESET_CNT
- type: W
- bitfield:
- - range: any
- value: 1
- type: T
- name: CLEAR
- desc: Any write to this register clears the counter value
- - range: 31..0
- name: VALUE
- type: R
-
-TCLINK_MON_GEN:
- desc: TClink status and control registers that dont have a default value
- number: 24
- endpoints: 0
- entries:
- - name: TCLINK_MONITOR_1
- format_name: TCLINK_MONITOR_1_{index:02}
- type_name: TCLINK_MONITOR_1
- type: R
- desc: tclink monitor register
- bitfield:
- - range: 62..15
- name: ERROR_CONTROLLER
- desc: Error-signal for controller Signed complement 2 number.
- - range: 14
- name: LOOP_CLOSED
- desc: TCLink loop is closed (compensation is enabled)
- - range: 13
- name: TX_ALIGNED
- desc: Transmitter alignment procedure finished Use as reset for transmitter user logic
- - range: 12
- name: PS_DONE
- desc: Phase shift is done
- - range: 11..5
- name: TX_PI_PHASE
- desc: Tx PI phase after alignment
- - name: TCLINK_MONITOR_2
- format_name: TCLINK_MONITOR_2_{index:02}
- type_name: TCLINK_MONITOR_2
- desc: Phase detector monitoring bits
- type: R
- bitfield:
- - range: 63..32
- name: PHASE_DETECTOR
- desc: Phase detector response
- - range: 31..0
- name: TX_FIFO_FILL_PD
- desc: Phase detector current value
- - name: TCLINK_MONITOR_3
- format_name: TCLINK_MONITOR_3_{index:02}
- type_name: TCLINK_MONITOR_3
- desc: tclink monitoring bits
- type: W
- bitfield:
- - range: 58..54
- name: LOOP_NOT_CLOSED_REASON
- type: R
- desc: Reason why the TCLink loop is not closed
- - range: 53..38
- name: PHASE_ACC
- type: R
- desc: phase accumulated output (integrated output)
- - range: 37
- name: OPERATION_ERROR
- type: R
- desc: error output indicating that a clk_en_i pulse has arrived before the done_i signal arrived from the previous strobe_o request
- - range: 36..27
- name: DEBUG_TESTER_ADDR_READ
- type: W
- desc: read address for reading stocked TCLink phase accumulated results
- - range: 26..11
- name: DEBUG_TESTER_DATA_READ
- type: R
- desc: data of stocked TCLink phase accumulated results
- - range: 10..7
- name: PS_PHASE_STEP
- type: R
- desc: number of units to shift the phase of the receiver clock
-
-
-TTCBUSYControlsAndMonitors:
- group: TTCBUSY
- desc: TTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: TTC_BUSY_ACCEPTED_G
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 2
- name: FULL
- type: R
- desc: TTC Emulator memory full indication
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
-
- - name: TTC_DELAY
- type: W
- desc: Controls the TTC Fanout delay value, in 25ns (1BC) units
- bitfield:
- - range: 3..0
- default: 0
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the BUSY Logic
- offset: 0x4b0
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
- - name: TTC_EMU_CONTROL
- type: W
- bitfield:
- - range: 33
- name: BUSY_IN_ENABLE
- desc: Enable internal BUSY input to stop L1A on BUSY
- default: 1
- - range: 32..27
- name: BROADCAST
- desc: Broadcast data
- - range: 26
- name: ECR
- desc: Event counter reset
- - range: 25
- name: BCR
- desc: Bunch counter reset
- - range: 24
- name: L1A
- desc: Level 1 Accept
-
- - name: TTC_EMU_L1A_PERIOD
- type: W
- desc: L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
- bitfield:
- - range: 31..0
-
- - name: TTC_EMU_ECR_PERIOD
- type: W
- desc: ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
- bitfield:
- - range: 31..0
-
- - name: TTC_EMU_BCR_PERIOD
- type: W
- desc: BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
- bitfield:
- - range: 31..0
- default: 3564
-
- - name: TTC_EMU_LONG_CHANNEL_DATA
- type: W
- desc: Long channel data for the TTC emulator
- bitfield:
- - range: 31..0
-
- - name: TTC_EMU_RESET
- desc: Any write to this register resets the TTC Emulator to the default state.
- type: W
- bitfield:
- - range: any
- value: 1
- type: T
-
- - name: TTC_L1ID_MONITOR
- desc: Monitor L1ID and XL1ID.
- type: R
- bitfield:
- - range: 31..0
-
- - name: TTC_ECR_MONITOR
- desc: Counts the number of ECRs received from the TTC system, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_TTYPE_MONITOR
- desc: Counts the number of TType received from the TTC system, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_BCR_PERIODICITY_MONITOR
- desc: Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_BCR_COUNTER
- desc: Counts the number of times BCR is issued, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_EMU_TP_DELAY
- desc: Number of BC that the testpulse should be sent before the L1A, 0 means no test pulse is sent
- type: W
- bitfield:
- - range: 31..0
- default: 64
-
- - name: TTC_L1A_DELAY
- desc: In Phase1 the L0A bit is generated from L1A, but with a variable delay between 0 and 63 BC cycles from L0A to L1A
- type: W
- bitfield:
- - range: 5..0
- default: 0
-
- - name: TTC_CDRLOCK_MONITOR
- desc: Monitor TTC CDR locked and ADN2814 LOL and LOS signals
- type: W
- bitfield:
- - range: any
- type: T
- name: CLEAR
- value: 1
- desc: Clears the latching cdrlock, LOL and LOS bitfields
- - range: 5
- type: R
- name: CDRLOCK_LOST
- desc: asserted when CDRLOCKED has been 0, Clear by writing to CLEAR bitfield
- - range: 4
- type: R
- name: CDRLOCKED
- desc: Set to 1 if the clock can be successfully recovered from the TTC signal
- - range: 3
- type: R
- name: ADN_LOL_LATCHED
- desc: Latched Loss of lock from ADN2814, Clear by writing to CLEAR bitfield
- - range: 2
- type: R
- name: ADN_LOS_LATCHED
- desc: Latched Loss of signal from ADN2814, Clear by writing to CLEAR bitfield
- - range: 1
- type: R
- name: ADN_LOL
- desc: Loss of lock from ADN2814
- - range: 0
- type: R
- name: ADN_LOS
- desc: Loss of signal from ADN2814
-
-
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range: 30..27
- name: B_CHAN_DELAY
- type: W
- desc: Number of BC to delay the L1A distribution to the frontends
- - range: 26..15
- name: BCID_ONBCR
- type: W
- desc: BCID is set to this value when BCR arrives
- - range: 14
- name: BUSY_OUTPUT_STATUS
- type: R
- desc: Actual status of the BUSY LEMO output signal
- - range: 13
- name: ECR_BCR_SWAP
- default: 0
- desc: ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
- - range: 12
- name: BUSY_OUTPUT_INHIBIT
- default: 0
- desc: forces the Busy LEMO output to BUSY-OFF
- - range: 11
- name: TOHOST_RST
- desc: reset toHost in ttc decoder
- default: 0
- - range: 10
- name: TT_BCH_EN
- desc: trigger type enable / disable for TTC-ToHost
- default: 1
- - range: 9..2
- name: XL1ID_SW
- desc: set XL1ID value, the value to be set by XL1ID_RST signal
- default: 0x00
- - range: 1
- name: XL1ID_RST
- desc: giving a trigger signal to reset XL1ID value
- default: 0
- - range: 0
- name: MASTER_BUSY
- desc: L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range: 15..5
- name: TH_FF_COUNT
- desc: ToHostData Fifo counts
- - range: 4
- name: TH_FF_FULL
- desc: ToHostData Fifo status 1:full 0:not full
- - range: 3
- name: TH_FF_EMPTY
- desc: ToHostData Fifo status 1:empty 0:not empty
- - range: 2..0
- name: TTC_BIT_ERR
- desc: double bit, single bit and comm error in TTC data
-
-TTC_BUSY_ACCEPTED_G:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- entries:
- - name: TTC_BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
- type_name: TTC_BUSY_ACCEPTED
- bitfield:
- - range: 56..0
-
-LTITTCBUSYControlsAndMonitors:
- group: LTITTCBUSY
- desc: LTITTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
- - name: LTITTC_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE
- bitfield:
- - range: 0..0
-
- - name: LTITTC_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST
- bitfield:
- - range: 0..0
-
- - name: LTITTC_PLL_LOCK
- bitfield:
- - range: 1..1
- name: QPLL_LOCK
- desc: QPLL LOCK
- - range: 0..0
- name: CPLL_LOCK
- desc: CPLL LOCK
-
- - name: LTITTC_RXCDR_LOCK
- desc: RX CDR LOCK
- bitfield:
- - range: 0..0
-
- - name: LTITTC_RXRESET_DONE
- desc: RX Reset done
- bitfield:
- - range: 0..0
-
- - name: LTITTC_RX_BYTEISALIGNED
- bitfield:
- - range: 0..0
- desc: LTITTC link not aligned
-
- - name: LTITTC_RX_DISP_ERROR
- bitfield:
- - range: 3..0
- desc: Rx disp error in byte 3,2,1,0 of LTITTC link
-
- - name: LTITTC_RX_NOTINTABLE
- bitfield:
- - range: 3..0
- desc: Character in byte 3,2,1,0 of LTITTC link not in 8b10b table
-
- - ref: LTITTC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: LTITTC_BUSY_ACCEPTED_G
-
- - name: LTITTC_SL0ID_MONITOR
- desc: Counts Set L0ID input bits
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: LTITTC_SORB_MONITOR
- desc: Counts SetOrbit input bits
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: LTITTC_GRST_MONITOR
- desc: Counts GRST input bits
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: LTITTC_SYNC_MONITOR
- desc: Counts the Sync input bits
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: LTITTC_TTYPE_MONITOR
- desc: Counts the number of TType received from the LTITTC system, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 46..15
- type: R
- name: VALUE
- - range: 15..0
- type: W
- name: REFVALUE
-
- - name: LTITTC_L0ID_ERR_MONITOR
- desc: Counts the number of times the internal l0id /= input L0ID
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: LTITTC_BCR_ERR_MONITOR
- desc: Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: LTITTC_CRC_ERR_MONITOR
- desc: Counts the number of time the internally computed crc /= input CRC
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
-
-
-LTITTC_CTRLMON:
- group: TDCM
- format_name: LTITTC_CTRLMON
- entries:
- - name: LTITTC_CTRL
- format_name: LTITTC_CTRL
- type_name: LTITTC_CTRLS
- type: W
- bitfield:
- - range: 11..9
- name: LTITTC_GTH_LOOPBACK_CONTROL
- desc: GTH_LOOPBACK_CONTROL for LTITTC Link
- default: 0
- - range: 8
- name: LTITTC_SOFT_RESET
- desc: SOFT_RESET
- default: 0
- - range: 7
- name: LTITTC_QPLL_RESET
- desc: QPLL_RESET
- default: 0
- - range: 6
- name: LTITTC_CPLL_RESET
- desc: CPLL_RESET
- default: 0
- - range: 5
- name: LTITTC_SOFT_TX_RESET
- desc: SOFT_TX_RESET_ALL
- default: 0
- - range: 4
- name: LTITTC_SOFT_RX_RESET
- desc: SOFT_RX_RESET_ALL
- default: 0
- - range: 3..2
- name: LTITTC_GENERAL_CTRL
- desc: Alignment chk reset (not self clearing)
- default: 0
- - range: 1
- name: LTITTC_CHANNEL_DISABLE
- desc: clear toHostData
- default: 0
- - range: 0
- name: TOHOST_RST
- desc: clear toHostData
- default: 0
- - name: LTITTC_MON
- format_name: LTITTC_MON
- type_name: LTITTC_MONS
- type: R
- bitfield:
- - range: 3
- name: BUSY_OUTPUT_STATUS
- desc: Actual status of the BUSY LEMO output signal
- - range: 2..0
- name: LTITTC_BIT_ERR
- desc: Alignment comma not received correctly. Place holder
-
-
-LTITTC_BUSY_ACCEPTED_G:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- entries:
- - name: LTITTC_BUSY_ACCEPTED
- format_name: LTITTC_BUSY_ACCEPTED{index:02}
- type_name: LTITTC_BUSY_ACCEPTED
- bitfield:
- - range: 56..0
-
-XOFF_BUSYControlsAndMonitors:
- group: XOFF
- desc: XOFF Controls and Monitors, see table 2 of Busy specs manual
- endpoints: 0, 1
- entries:
- - name: XOFF_FM_CH_FIFO_THRESH_LOW
- type: W
- bitfield:
- - range: 3..0
- default: 0xB
- desc: |
- Controls the low threshold of the channel fifo in FULL mode on which
- an Xon will be asserted, bitfields control 4 MSB
- - name: XOFF_FM_CH_FIFO_THRESH_HIGH
- type: W
- bitfield:
- - range: 3..0
- default: 0xB
- desc: |
- Controls the high threshold of the channel fifo in FULL mode on which
- an Xoff will be asserted, bitfields control 4 MSB
- - name: XOFF_FM_LOW_THRESH_CROSSED
- desc: FIFO filled beyond the low threshold, 1 bit per channel
- type: R
- bitfield:
- - range: 23..0
- - name: XOFF_FM_HIGH_THRESH
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- desc: Writing this register will clear all CROSS_LATCHED bits
- type: T
- value: 1
- - range: 47..24
- type: R
- name: CROSS_LATCHED
- desc: FIFO filled beyond the high threshold, 1 latch bit per channel
- - range: 23..0
- type: R
- name: CROSSED
- desc: FIFO filled beyond the high threshold, 1 bit per channel
-
- - name: XOFF_FM_SOFT_XOFF
- type: W
- desc: Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
- bitfield:
- - range: 23..0
-
- - name: XOFF_ENABLE
- type: W
- desc: Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
- bitfield:
- - range: 23..0
-
- - name: DMA_BUSY_STATUS
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR_LATCH
- desc: Any write to this register clears TOHOST_BUSY_LATCHED
- - range: 4
- type: W
- name: ENABLE
- desc: Enable the DMA buffer on the server as a source of busy
- default: 0
- - range: 3
- type: R
- name: TOHOST_BUSY_LATCHED
- desc: A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => tohost_busy_latched_40_s)
- - range: 0
- type: R
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => tohost_busy_40_s)
-
- - name: FM_BUSY_CHANNEL_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- type: T
- value: 1
- desc: Any write to this register will clear the BUSY_LATCHED bits
- - range: 47..24
- type: R
- name: BUSY_LATCHED
- desc: one Indicates that the given FULL mode channel has received BUSY-ON
- - range: 23..0
- type: R
- name: BUSY
- desc: one Indicates that the given FULL mode channel is currently in BUSY state
-
- - name: BUSY_MAIN_OUTPUT_FIFO_THRESH
- type: W
- bitfield:
- - range: 24
- name: BUSY_ENABLE
- desc: Enable busy generation if thresholds are crossed
- default: 0
- - range: 23..12
- name: LOW
- desc: Low, Negate threshold of busy generation from main output fifo
- default: 0x3FF
- - range: 11..0
- name: HIGH
- desc: High, Assert threshold of busy generation from main output fifo
- default: 0x4FF
-
- - name: BUSY_MAIN_OUTPUT_FIFO_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCHED
- value: 1
- desc: Any write to this register will clear the
- type: T
- - range: 2
- type: R
- name: HIGH_THRESH_CROSSED_LATCHED
- desc: Main output fifo has been full beyond HIGH THRESHOLD, write to clear
- - range: 1
- type: R
- name: HIGH_THRESH_CROSSED
- desc: Main output fifo is full beyond HIGH THRESHOLD
- - range: 0
- type: R
- name: LOW_THRESH_CROSSED
- desc: Main output fifo is full beyond LOW THRESHOLD
- - ref: ELINK_BUSY_ENABLE
- - ref: XOFF_STATISTICS
-
- - name: BUSY_TOHOST_ENABLE
- type: W
- desc: Enable the busy ToHost Virtual Elink
- bitfield:
- - range: 0
- default: 0
-
-
-
-ELINK_BUSY_ENABLE:
- number: 24
- endpoints: 0
- type: W
- entries:
- - name: ELINK_BUSY_ENABLE
- format_name: ELINK_BUSY_ENABLE{index:02}
- type_name: ELINK_BUSY_ENABLE
- desc: Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- bitfield:
- - range: 56..0
- default: 0
-
-XOFF_STATISTICS:
- number: 24
- endpoints: 0,1
- type: R
- entries:
- - name: XOFF_PEAK_DURATION
- format_name: XOFF_PEAK_DURATION{index:02}
- type_name: XOFF_PEAK_DURATION
- desc: Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- bitfield:
- - range: 63..0
- - name: XOFF_TOTAL_DURATION
- format_name: XOFF_TOTAL_DURATION{index:02}
- type_name: XOFF_TOTAL_DURATION
- desc: Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- bitfield:
- - range: 63..0
- - name: XOFF_COUNT
- format_name: XOFF_COUNT{index:02}
- type_name: XOFF_COUNT
- desc: Total number of XOFF events per channel that occurred since a reset.
- bitfield:
- - range: 63..0
-
-
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- desc: Write to this bitfield clears the latched SI5345_LOL status, SI5345_LOL_LATCHED
- - range: 14
- name: SI5345_LOL_LATCHED
- type: R
- desc: Latched version of SI5345_LOL, clear by writing to CLEAR bitfield
- - range: 13..12
- name: SI5345_INTR_B
- type: R
- desc: Connects to SI5345_INTR_B pins
- - range: 11..10
- name: SI5345_FINC_B
- type: W
- desc: Connects to FINC_B pins of SI5345
- default: 1
- - range: 9..8
- name: SI5345_FDEC_B
- type: W
- desc: Connects to FDEC_B pins of SI5345
- default: 1
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, not connected on VC709
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x1
- desc: Si5345 active low reset (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
-
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- desc: Clears the LOL_LATCHED status
- - range: 4
- name: LOL_LATCHED
- type: R
- desc: Main MMCM has lost lock, clear by writing to the CLEAR bitfield
- - range: 3
- type: W
- name: LCLK_SEL
- default: 0x1
- desc: |
- 1: LCLK
- 0: TTC
- - range: 2..1
- type: R
- name: MAIN_INPUT
- desc: |
- Main MMCM Oscillator Input
- 2: LCLK fixed
- 1: TTC fixed
- 0: selectable
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL-711 locked
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
- - name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
- - name: I2C_WR
- type: W
- offset: 0x420
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 34..27
- name: DATA_BYTE3
- type: W
- desc: Data byte 3 used when RW16BIT is set
- - range: 26
- name: RW16BIT
- type: W
- desc: Set to 1 to Write 3 bytes (ADDR + 16 data bits) or read 16 data bits.
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
- - name: INT_TEST
- offset: 0x0800
- type: W
- value: 1
- bitfield:
- - name: TRIGGER
- type: T
- range: any
- desc: Fire a test MSIx interrupt set in IRQ
- - name: IRQ
- type: W
- range: 3..0
- desc: Set this field to a value equal to the MSIX interrupt to be fired. The write triggers the interrupt immediately.
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
- - name: TACH_CNT
- type: R
- desc: Readout of the Fan tachometer speed of the BNL712 board
- bitfield:
- - range: 19..0
- - name: RXUSRCLK_FREQ
- type: W
- bitfield:
- - range: 38
- name: VALID
- type: R
- desc: Indicates that the frequency measurement is valid
- - range: 37..32
- name: CHANNEL
- type: W
- desc: Select the Transceiver channel to measure the clock from.
- - range: 31..0
- name: VAL
- type: R
- desc: Frequency in Hz of the selected channel
-
-
-Generators:
- group: GEN
- desc: Specific registers for Hardware based Generators
- endpoints: 0
- entries:
- - name: FELIG_L1ID_RESET
- fw_modes: 6,11
- type: W
- desc: Any write to this register clears the FELIG L1ID
- bitfield:
- - range: any
- type: T
- value: 1
- - ref: FELIG_DATA_GEN_CONFIG_ARR
- offset: 0x20
- - ref: FELIG_ELINK_CONFIG_ARR
- - ref: FELIG_ELINK_ENABLE_ARR
-
- - name: FELIG_GLOBAL_CONTROL
- type: W
- fw_modes: 6,11
- bitfield:
- - range: 63..36
- name: FAKE_L1A_RATE
- default: 0
- desc: Sets the internal fake L1 trigger rate. [25ns/LSB]
- - range: 35..14
- name: PICXO_OFFSET_PPM
- default: 0
- desc: When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
- - range: 12..12
- name: TRACK_DATA
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 11..11
- name: RXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 10..10
- name: TXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 9..9
- name: AUTO_RESET
- default: 0
- desc: FELIG GT core control. If set the GT core automatically resets on data error.
- - range: 8..8
- name: PICXO_RESET
- default: 0
- desc: FELIG GT core control. Manual PICXO reset.
- - range: 7..7
- name: GTTX_RESET
- default: 0
- desc: FELIG GT core control. Manual GT TX reset
- - range: 6..6
- name: CPLL_RESET
- default: 0
- desc: FELIG GT core control. Manual CPLL reset.
- - range: 5..0
- name: X3_X4_OUTPUT_SELECT
- default: 0
- desc: X3/X4 SMA output source select.
- - ref: FELIG_LANE_CONFIG_ARR
- - ref: FELIG_MON_TTC_0_ARR
- - ref: FELIG_MON_TTC_1_ARR
- - ref: FELIG_MON_COUNTERS_ARR
- - ref: FELIG_MON_FREQ_ARR
- - name: FELIG_MON_FREQ_GLOBAL
- fw_modes: 6,11
- type: W
- bitfield:
- - range: 63..32
- name: XTAL_100MHZ
- default: 0
- desc: FELIG local oscillator frequency[Hz].
- - range: 31..0
- name: CLK_41_667MHZ
- desc: FELIG PCIE MGTREFCLK frequency[Hz].
- - ref: FELIG_MON_L1A_ID_ARR
- - ref: FELIG_MON_PICXO_ARR
- - name: FELIG_RESET
- fw_modes: 6,11
- type: W
- bitfield:
- - range: 63..48
- name: LB_FIFO
- default: 0
- desc: One bit per lane. When set to 1, resets all loopback FIFOs.
- - range: 47..24
- name: FRAMEGEN
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG link checking logic.
- - range: 23..0
- name: LANE
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG lane logic.
-
- - name: FELIG_RX_SLIDE_RESET
- fw_modes: 6,11
- type: W
- bitfield:
- - range: 23..0
- default: 0
- desc: One bit per lane. When set to 1, resets the gbt rx slide counter.
-
- - ref: FELIG_ITK_STRIPS_DATA_GEN_CONFIG_ARR
- - ref: FELIG_MON_ITK_STRIPS_ARR
- - ref: FELIG_DATA_GEN_CONFIG_USERDATA_ARR
-
- - name: FMEMU_EVENT_INFO
- fw_modes: 7
- type: R
- offset: 0x1800
- bitfield:
- - range: 63..32
- name: L1ID
- default: 0
- desc: 32b field to show L1ID
- - range: 31..0
- name: BCID
- default: 0
- desc: 32b field to show BCID
-
- - name: FMEMU_COUNTERS
- fw_modes: 7
- type: W
- bitfield:
- - range: 63..48
- name: WORD_CNT
- default: 32
- desc: Number of 32b words in one chunk
- - range: 47..32
- name: IDLE_CNT
- default: 3
- desc: Minimum number of idles between chunks
- - range: 31..16
- name: L1A_CNT
- default: 256
- desc: Number of chunks to send if not in TTC mode
- - range: 15..8
- name: BUSY_TH_HIGH
- default: 20
- desc: Assert BUSY-ON above this threshold
- - range: 7..0
- name: BUSY_TH_LOW
- default: 15
- desc: De-assert BUSY-ON below this threshold
-
- - name: FMEMU_CONTROL
- fw_modes: 7
- type: W
- bitfield:
- - range: 63..56
- type: W
- name: L1A_BITNR
- default: 48
- desc: Bitfield for L1A in TTC frame
- - range: 55..48
- type: W
- name: XONXOFF_BITNR
- default: 32
- desc: Bitfield for Xon/Xoff in TTC frame
- - range: 47..47
- type: W
- name: EMU_START
- default: 0
- desc: Start emulator functionality
- - range: 46..46
- type: W
- name: TTC_MODE
- default: 0
- desc: Control the emulator by TTC input or by RegMap (1/0)
- - range: 45..45
- type: W
- name: XONXOFF
- default: 1
- desc: Enable Xon/Xoff functionality (1/0)
- - range: 44..44
- type: W
- name: INLC_CRC32
- default: 0
- desc: |
- 0: No checksum
- 1: Append the data with a CRC32
- - range: 43..43
- type: W
- name: BCR
- default: 0
- desc: Reset BCID to 0
- - range: 42..42
- type: W
- name: ECR
- default: 0
- desc: Reset L1ID to 0
- - range: 41..41
- type: W
- name: CONSTANT_CHUNK_LENGTH
- default: 0
- desc: |
- Data source select
- 0: Random chunk length
- 1: Constant chunk length
- - range: 40..32
- type: R
- name: INT_STATUS_EMU
- default: 0
- desc: Read internal status emulator
- - range: 16
- type: W
- name: FFU_FM_EMU_T
- default: 0
- desc: For Future Use (trigger registers)
- - range: 0
- type: W
- name: FE_BUSY_ENABLE
- default: 1
- desc: Enable the BUSY mechanism if L1A counter passes threshold
-
- - name: FMEMU_RANDOM_RAM_ADDR
- fw_modes: 7
- type: W
- desc: Controls the address of the ramblock for the random number generator
- bitfield:
- - range: 9..0
- - name: FMEMU_RANDOM_RAM
- fw_modes: 7
- type: W
- bitfield:
- - range: any
- type: T
- name: WE
- value: 1
- desc: Any write to this register (DATA) triggers a write to the ramblock
- - range: 39..16
- name: CHANNEL_SELECT
- value: 0xFFFFFF
- desc: Enable write enable only for the selected channel
- - range: 15..0
- name: DATA
- type: W
- desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
- - name: FMEMU_RANDOM_CONTROL
- fw_modes: 7
- type: W
- desc: Controls the random chunk length generator
- bitfield:
- - name: SELECT_RANDOM
- range: 20
- desc: 1 enables the random chunk length, 0 uses a constant chunk length
- default: 0
- - name: SEED
- range: 19..10
- desc: Seed for the random number generator, should not be 0
- default: 0x200
- - name: POLYNOMIAL
- range: 9..0
- desc: POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
- default: 0x240
-
- - name: FMEMU_CONFIG_WRADDR
- fw_modes: 7
- type: W
- bitfield:
- - range: 9..0
- value: 0
- desc: write enable for the FMEmu ram block
-
- - name: FMEMU_CONFIG
- fw_modes: 7
- type: W
- bitfield:
- - range: any
- type: T
- name: WE
- value: 1
- desc: Any write to register WRDATA triggers a write to the ramblock
- - range: 55..32
- name: CHANNEL_SELECT
- value: 0xFFFFFF
- desc: Enable write enable only for the selected channel
- - range: 31..0
- name: WRDATA
- type: W
- desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
-
-
-#Registers that are replicated 24 times under Generators:
-FELIG_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- fw_modes: 6,11
- entries:
- - name: FELIG_DATA_GEN_CONFIG
- format_name: FELIG_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_DATA_GEN_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: CHUNK_LENGTH
- range: 50..35
- default: 0
- desc: FELIG data generator chunk-length in bytes.
- - name: RESET
- range: 34..28
- default: 0
- desc: FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- - name: SW_BUSY
- range: 27..21
- default: 0
- desc: FELIG elink busy state. One bit per group, 0:normal operation, 1:elink enter busy state.
- - name: DATA_FORMAT
- range: 20..7
- default: 0
- desc: FELIG data generator format, 2 bits per e-group. 00 8b10b, 01 direct, 10 Aurora
- - name: PATTERN_SEL
- range: 6..0
- default: 0
- desc: FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
-
-
-FELIG_ELINK_CONFIG_ARR:
- number: 24
- type: W
- fw_modes: 6,11
- entries:
- - name: FELIG_ELINK_CONFIG
- format_name: FELIG_ELINK_CONFIG_{index:02}
- type_name: FELIG_ELINK_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: ENDIAN_MOD
- range: 34..28
- default: 0
- desc: FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- - name: INPUT_WIDTH
- range: 27..21
- default: 0
- desc: FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- - name: OUTPUT_WIDTH
- range: 20..0
- default: 0
- desc: FELIG elink data output width. 3 bits per egroup. 0:2b, 1:4b, 2:8b, 3:16b, 4:32b
-
-FELIG_ELINK_ENABLE_ARR:
- number: 24
- type: W
- fw_modes: 6,11
- entries:
- - name: FELIG_ELINK_ENABLE
- format_name: FELIG_ELINK_ENABLE_{index:02}
- type_name: FELIG_ELINK_ENABLE
- desc: FELIG specific configuration registers
- bitfield:
- - range: 39..0
- default: 0
- desc: FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
-
-FELIG_LANE_CONFIG_ARR:
- number: 24
- type: W
- fw_modes: 6,11
- entries:
- - name: FELIG_LANE_CONFIG
- format_name: FELIG_LANE_CONFIG_{index:02}
- type_name: FELIG_LANE_CONFIG
- desc: FELIG specific configuration registers
- bitfield:
- - name: B_CH_BIT_SEL
- range: 63..42
- default: 0
- desc: When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- - name: A_CH_BIT_SEL
- range: 41..35
- default: 0
- desc: Selects the bit from the received FELIX data from which to extract the L1A.
- - name: LB_FIFO_DELAY
- range: 34..30
- default: 0
- desc: When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- - name: ELINK_SYNC
- range: 7..7
- default: 0
- desc: When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- - name: PICXO_OFFEST_EN
- range: 6..6
- default: 0
- desc: FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- - name: PI_HOLD
- range: 5..5
- default: 0
- desc: FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- - name: GBT_LB_ENABLE
- range: 4..4
- default: 0
- desc: FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- - name: GBH_LB_ENABLE
- range: 3..3
- default: 0
- desc: FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- - name: L1A_SOURCE
- range: 2..2
- default: 0
- desc: FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- - name: GBT_EMU_SOURCE
- range: 1..1
- default: 0
- desc: FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- - name: FG_SOURCE
- range: 0..0
- default: 0
- desc: FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
-
-FELIG_MON_TTC_0_ARR:
- number: 24
- type: R
- fw_modes: 6,11
- entries:
- - name: FELIG_MON_TTC_0
- format_name: FELIG_MON_TTC_0_{index:02}
- type_name: FELIG_MON_TTC_0
- desc: FELIG specific configuration registers
- bitfield:
- - name: L1ID
- range: 63..40
- default: 0
- desc: Live TTC data monitor.
- - name: XL1ID
- range: 39..32
- default: 0
- desc: Live TTC data monitor.
- - name: BCID
- range: 31..20
- default: 0
- desc: Live TTC data monitor.
- - name: RESERVED0
- range: 19..16
- default: 0
- desc: Live TTC data monitor.
- - name: LEN
- range: 15..8
- default: 0
- desc: Live TTC data monitor.
- - name: FMT
- range: 7..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_TTC_1_ARR:
- number: 24
- type: R
- fw_modes: 6,11
- entries:
- - name: FELIG_MON_TTC_1
- format_name: FELIG_MON_TTC_1_{index:02}
- type_name: FELIG_MON_TTC_1
- desc: FELIG specific configuration registers
- bitfield:
- - name: RESERVED1
- range: 63..48
- default: 0
- desc: Live TTC data monitor.
- - name: TRIGGER_TYPE
- range: 47..32
- default: 0
- desc: Live TTC data monitor.
- - name: ORBIT
- range: 31..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_COUNTERS_ARR:
- number: 24
- type: R
- fw_modes: 6,11
- entries:
- - name: FELIG_MON_COUNTERS
- format_name: FELIG_MON_COUNTERS_{index:02}
- type_name: FELIG_MON_COUNTERS
- desc: FELIG specific configuration registers
- bitfield:
- - name: SLIDE_COUNT
- range: 63..32
- default: 0
- desc: Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- - name: FC_ERROR_COUNT
- range: 31..0
- default:
- desc: When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
-
-FELIG_MON_FREQ_ARR:
- number: 24
- type: R
- fw_modes: 6,11
- entries:
- - name: FELIG_MON_FREQ
- format_name: FELIG_MON_FREQ_{index:02}
- type_name: FELIG_MON_FREQ
- desc: FELIG specific configuration registers
- bitfield:
- - name: TX
- range: 63..32
- default: 0
- desc: FELIG regenerated TX clock frequency[Hz].
- - name: RX
- range: 31..0
- default: 0
- desc: FELIG recovered RX clock frequency[Hz].
-
-FELIG_MON_L1A_ID_ARR:
- number: 24
- type: R
- fw_modes: 6,11
- entries:
- - name: FELIG_MON_L1A_ID
- format_name: FELIG_MON_L1A_ID_{index:02}
- type_name: FELIG_MON_L1A_ID
- desc: FELIG specific configuration registers
- bitfield:
- - range: 31..0
- default: 0
- desc: FELIG's last L1 ID.
-
-FELIG_MON_PICXO_ARR:
- number: 24
- type: R
- fw_modes: 6,11
- entries:
- - name: FELIG_MON_PICXO
- format_name: FELIG_MON_PICXO_{index:02}
- type_name: FELIG_MON_PICXO
- desc: FELIG specific configuration registers
- bitfield:
- - name: VLOT
- range: 53..32
- default: 0
- desc: Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- - name: ERROR
- range: 20..0
- default: 0
- desc: Value indicates RX to TX frequency tracking error.
-
-FELIG_ITK_STRIPS_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- fw_modes: 6,11
- entries:
- - name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG
- format_name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG
- desc: ITk Strips emulator specific configuration test registers
- bitfield:
- - name: ITKS_FIFO_CTL
- range: 19..17
- default: 0
- desc: data fifo control 2:rst 1:rd 0:wr.
- - name: ITKS_FIFO_DATA
- range: 16..0
- default: 0
- desc: itks emu data 16:last word 15-0:data word
-
-FELIG_MON_ITK_STRIPS_ARR:
- number: 24
- type: R
- fw_modes: 6,11
- entries:
- - name: FELIG_MON_ITK_STRIPS
- format_name: FELIG_MON_ITK_STRIPS_{index:02}
- type_name: FELIG_MON_ITK_STRIPS
- desc: ITk Strips emulator specific status registers
- bitfield:
- - name: ITKS_FIFO_STATUS
- range: 2..0
- default: 0
- desc: data fifo status 2:write done 1:full 0:empty.
-
-#Registers that are replicated 24 times under Generators:
-FELIG_DATA_GEN_CONFIG_USERDATA_ARR:
- number: 24
- type: W
- fw_modes: 6
- entries:
- - name: FELIG_DATA_GEN_CONFIG_USERDATA
- format_name: FELIG_DATA_GEN_CONFIG_{index:02}_USERDATA
- type_name: FELIG_DATA_GEN_CONFIG_USERDATA
- desc: Sets static payload word. When FELIG_DATA_GEN_CONFIG.PATTERN_SEL=1.
- bitfield:
- - range: 15..0
- default: 0
-
-Wishbone:
- desc: Wishbone
- endpoints: 0
- fw_modes: 1
- entries:
- - name: WISHBONE_CONTROL
- type: W
- bitfield:
- - range: 32
- name: WRITE_NOT_READ
- desc: wishbone write command wishbone read command
- - range: 31..0
- name: ADDRESS
- desc: Slave address for Wishbone bus
- - name: WISHBONE_WRITE
- type: T
- bitfield:
- - range: any
- type: T
- value: 1
- name: WRITE_ENABLE
- desc: Any write to this register triggers a write to the Wupper to Wishbone fifo
- - range: 32
- name: FULL
- type: R
- - range: 31..0
- name: DATA
- type: W
- - name: WISHBONE_READ
- type: T
- bitfield:
- - range: any
- type: T
- value: 1
- name: READ_ENABLE
- desc: Any write to this register triggers a read from the Wishbone to Wupper fifo
- - range: 32
- name: EMPTY
- type: R
- desc: Indicates that the Wishbone to Wupper fifo is empty
- - range: 31..0
- name: DATA
- type: R
- desc: Wishbone read data
- - name: WISHBONE_STATUS
- type: R
- bitfield:
- - range: 4
- name: INT
- desc: interrupt
- - range: 3
- name: RETRY
- desc: Interface is not ready to accept data cycle should be retried
- - range: 2
- name: STALL
- desc: When pipelined mode slave can't accept additional transactions in its queue
- - range: 1
- name: ACKNOWLEDGE
- desc: Indicates the termination of a normal bus cycle
- - range: 0
- name: ERROR
- desc: Address not mapped by the crossbar
-
-# ----------------------- ITk strips link configuration start -----------------------
-
-ITK_STRIPS_CTRL:
- entries:
- - name: GLOBAL_STRIPS_CONFIG
- desc: Configuration affecting all Strips links on this FELIX device
- type: W
- fw_modes: 5
- bitfield:
- - range: 63..59
- type: W
- name: TEST_MODULE_MASK
- desc: (for tests only) contains R3 mask for the simulated trigger data
- default: 0x0
- - range: 58..52
- type: W
- name: TEST_R3L1_TAG
- desc: (for tests only) contains R3 or L1 tag for the simulated trigger data
- default: 0x0
- - range: 51
- type: W
- name: TTC_GENERATE_GATING_ENABLE
- desc: Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR.
- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- (See also BC_START, and BC_STOP fields)
- default: 0x0
- - range: 50
- type: W
- name: TTC_GATING_OVERRIDE
- desc: Overrides and disables gating signal generation when set to '1'
- (use if the elink is deadlocked and commands don't reach it).
- default: 0x0
- - range: 4
- type: W
- name: INVERT_AMAC_IN
- desc: Invert the polarity of all FELIX AMAC_IN elinks
- default: 0x0
- - range: 3
- type: W
- name: INVERT_AMAC_OUT
- desc: Invert the polarity of all FELIX AMAC_OUT elinks
- default: 0x0
- - range: 2
- type: W
- name: INVERT_DIN
- desc: Invert the polarity of all FELIX 8-bit IN 8b10b elinks
- default: 0x0
- - range: 1
- type: W
- name: INVERT_R3L1_OUT
- desc: Invert the polarity of all FELIX R3L1 elinks
- default: 0x0
- - range: 0
- type: W
- name: INVERT_LCB_OUT
- desc: Invert the polarity of all FELIX LCB elinks
- default: 0x0
-
- - name: GLOBAL_TRICKLE_TRIGGER
- fw_modes: 5
- type: T
- bitfield:
- - range: any
- value: 1
- desc: writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
-
- - name: STRIPS_R3_TRIGGER
- fw_modes: 5
- type: T
- bitfield:
- - range: any
- value: 1
- desc: (for tests only) simulate R3 trigger (issues 4-5 sequential triggers)
- - name: STRIPS_L1_TRIGGER
- fw_modes: 5
- type: T
- bitfield:
- - range: any
- desc: (for tests only) simulate L1 trigger (issues 4-5 sequential triggers)
- value: 1
- - name: STRIPS_R3L1_TRIGGER
- fw_modes: 5
- type: T
- bitfield:
- - range: any
- desc: (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)
- value: 1
-
-# ----------------------- ITk strips link configuration end -----------------------
-
-
-MRODregisters:
- group: MROD_CONTROL
- fw_modes: 8
- desc: Specific registers for MROD
- endpoints: 0
- entries:
- - name: MROD_CTRL
- type: W
- bitfield:
- - range: 15..8
- name: OPTIONS
- default: 0
- desc: Extra options for MROD
- - range: 7..7
- name: ENASPARE1
- default: 0
- desc: Enable spare1
- - range: 6..6
- name: ENAMANSLIDE
- default: 0
- desc: Enable Manual Slide in Rx Locking
- - range: 5..5
- name: ENAPASSALL
- default: 0
- desc: Enable PassAll in EmptySuppress
- - range: 4..4
- name: ENATXCOUNT
- default: 0
- desc: Enable SimpleCount in TxDriver for locking
- - range: 3..0
- name: GOLTESTMODE
- default: 0
- desc: |
- GOL Test Mode (emulate CSM):
- 0: Run Data Emulator when 1; 0: stop, load emulator fifo
- 1: Enable Circulate when 1; 0: send fifo data only once
- 2: Enable Triggered Mode when 1; 0: run continueously (no TTC)
- 3: Enable pattern generator
- - name: MROD_TCVRCTRL
- type: W
- bitfield:
- - range: 23..16
- name: SLIDEMAX
- default: 0xFF
- desc: Maximum RXSLIDES before fire a TCVR reset
- - range: 15..8
- name: SLIDEWAIT
- default: 32
- desc: RXclk delay in TCVR for next RX_SLIDE operation
- - range: 7..0
- name: FRAMESIZE
- default: 20
- desc: Number of 32 data words in 1 frame
- - name: MROD_EP0_CSMENABLE
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 CSM Data Enable channel 23-0
- default: 0
- - name: MROD_EP0_EMPTYSUPPR
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Set Empty Suppression channel 23-0
- default: 0
- - name: MROD_EP0_HPTDCMODE
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Set HPTDC Mode channel 23-0
- default: 0
- - name: MROD_EP0_CLRFIFOS
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Clear FIFOs channel 23-0
- default: 0
- - name: MROD_EP0_EMULOADENA
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Emulator Load Enable channel 23-0
- default: 0
- - name: MROD_EP0_TRXLOOPBACK
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Transceiver Loopback Enable channel 23-0
- default: 0
- - name: MROD_EP0_TXCVRRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Transceiver Reset all channel 23-0
- default: 0
- - name: MROD_EP0_RXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Reset channel 23-0
- default: 0
- - name: MROD_EP0_TXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Transmitter Reset channel 23-0
- default: 0
- - name: MROD_EP1_CSMENABLE
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 CSM Data Enable channel 23-0
- default: 0
- - name: MROD_EP1_EMPTYSUPPR
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Set Empty Suppression channel 23-0
- default: 0
- - name: MROD_EP1_HPTDCMODE
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Set HPTDC Mode channel 23-0
- default: 0
- - name: MROD_EP1_CLRFIFOS
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Clear FIFOs channel 23-0
- default: 0
- - name: MROD_EP1_EMULOADENA
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Emulator Load Enable channel 23-0
- default: 0
- - name: MROD_EP1_TRXLOOPBACK
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Transceiver Loopback Enable channel 23-0
- default: 0
- - name: MROD_EP1_TXCVRRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Transceiver Reset all channel 23-0
- default: 0
- - name: MROD_EP1_RXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Reset channel 23-0
- default: 0
- - name: MROD_EP1_TXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Transmitter Reset channel 23-0
- default: 0
-
-MRODmonitors:
- group: MROD_MONITOR
- desc: Specific registers for MROD
- endpoints: 0
- fw_modes: 8
- entries:
- - name: MROD_EP0_CSMH_EMPTY
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 CSM Handler FIFO Empty 23-0
- - name: MROD_EP0_CSMH_FULL
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 CSM Handler FIFO Full 23-0
- - name: MROD_EP0_RXALIGNBSY
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Aligned monitor 23-0
- - name: MROD_EP0_RXRECDATA
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Data monitor 23-0
- - name: MROD_EP0_RXRECIDLES
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Idle monitor 23-0
- - name: MROD_EP0_TXLOCKED
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Transmitter Locked monitor 23-0
- - name: MROD_EP1_CSMH_EMPTY
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 CSM Handler FIFO Empty 23-0
- - name: MROD_EP1_CSMH_FULL
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 CSM Handler FIFO Full 23-0
- - name: MROD_EP1_RXALIGNBSY
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Aligned monitor 23-0
- - name: MROD_EP1_RXRECDATA
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Data monitor 23-0
- - name: MROD_EP1_RXRECIDLES
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Idle monitor 23-0
- - name: MROD_EP1_TXLOCKED
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Transmitter Locked monitor 23-0
-
-IPBus:
- desc: IPbus bridge registers
- endpoints: 0
- fw_modes: 1
- entries:
- - name: IPBUS_WRITE_ADDRESS
- type: W
- desc: Address of the IPBus Write RAM
- bitfield:
- - range: 31..0
- - name: IPBUS_WRITE_DATA
- type: T
- desc: IPbus data to write to RAM
- bitfield:
- - range: any
- type: T
- value: 1
- name: WRITE_ENABLE
- desc: Any write to this register triggers a write to the Wupper to IPBus inout RAM
- - range: 63..0
- name: DATA
- type: W
- - name: IPBUS_READ_ADDRESS
- type: W
- desc: Address of the IPBus Read RAM
- bitfield:
- - range: 31..0
- - name: IPBUS_READ_DATA
- type: R
- desc: IPbus data from Read RAM
- bitfield:
- - range: 63..0
- - name: IPBUS_PKT_DONE
- type: R
- desc: IPbus packet ready to read
- bitfield:
- - range: 0
-
diff --git a/sources/templates/yaml/registers-5.1.yaml b/sources/templates/yaml/registers-5.1.yaml
deleted file mode 100644
index c7fc38e595feefe82d14e9185165525a19d1a078..0000000000000000000000000000000000000000
--- a/sources/templates/yaml/registers-5.1.yaml
+++ /dev/null
@@ -1,4307 +0,0 @@
-Registers:
- version: '5.1'
-#The warning message below can be disregarded, this is the part that gets into the generated files.
-#***This file is actually the one that you are allowed to edit!
- warning: |
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- DO NOT EDIT THIS FILE
-
- This file was generated from template '{{ metadata.template }}'
- and register map {{ metadata.config }}, version {{ tree.version }}
- by the script '{{ metadata.name }}', version: {{ metadata.version }},
- using the following commandline:
-
- {{ metadata.cmdline }}
-
- Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
-
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
- ***************************************************************************
-
- type: R
- step: 0x010
- default: 0
- endpoints: 0,1
- entries:
- - ref: Bar0
- offset: 0x0000
- - ref: Bar1
- offset: 0x0000
- - ref: Bar2
- offset: 0x0000
- - ref: Monitorsections
- offset: 0x0000
-
-Monitorsections:
- endpoints: 0,1
- entries:
- - name: GenericBoardInformation
- record_name: register_map_gen_board_info
- bitfield:
- - range: 0..0
- type: R
- - name: CRToHostControlsAndMonitors
- record_name: register_map_crtohost_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: CRFromHostControlsAndMonitors
- record_name: register_map_crfromhost_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: DecodingControlsAndMonitors
- record_name: register_map_decoding_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: EncodingControlsAndMonitors
- record_name: register_map_encoding_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: FrontendEmulatorControlsAndMonitors
- record_name: register_map_gbtemu_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: LinkWrapperMonitors
- record_name: register_map_link_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: TTCBUSYControlsAndMonitors
- record_name: register_map_ttc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: LTITTCBUSYControlsAndMonitors
- record_name: register_map_ltittc_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: XOFF_BUSYControlsAndMonitors
- record_name: register_map_xoff_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: HouseKeepingControlsAndMonitors
- record_name: register_map_hk_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: Generators
- record_name: register_map_generators
- bitfield:
- - range: 0..0
- type: R
- - name: Wishbone
- record_name: wishbone_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: MRODmonitors
- record_name: regmap_mrod_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: IPBus
- record_name: ipbus_monitor
- bitfield:
- - range: 0..0
- type: R
-
-#Bar0 contains the registers dedicated to Wupper. Please only edit registers in Bar2
-#Registers in this group will not be generated with WupperCodeGen
-Bar0:
- endpoints: 0,1
- entries:
- - ref: DMA_DESC
- - ref: DMA_DESC_STATUS
- offset: 0x0200
- - name: BAR0_VALUE
- offset: 0x0300
- bitfield:
- - range: 31..0
- desc: Copy of BAR0 offset reg.
- - name: BAR1_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR1 offset reg.
- - name: BAR2_VALUE
- bitfield:
- - range: 31..0
- desc: Copy of BAR2 offset reg.
- - name: DMA_DESC_ENABLE
- offset: 0x0400
- bitfield:
- - range: 7..0
- type: W
- desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
- - name: DMA_RESET
- offset: 0x420
- type: T
- bitfield:
- - range: any
- desc: Reset Wupper Core (DMA Controller FSMs)
- - name: SOFT_RESET
- type: T
- bitfield:
- - range: any
- desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
- - name: REGISTER_RESET
- type: T
- bitfield:
- - range: any
- desc: Resets the register map to default values. Any write triggers this reset.
- - name: FROMHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 22..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the FromHost programmable full flag
- - range: 6..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the FromHost programmalbe full flag
- - name: TOHOST_FULL_THRESH
- type: W
- bitfield:
- - range: 27..16
- name: THRESHOLD_ASSERT
- desc: Assert value of the ToHost programmable full flag
- - range: 11..0
- name: THRESHOLD_NEGATE
- desc: Negate value of the ToHost programmalbe full flag
-
- - name: BUSY_THRESHOLD_ASSERT
- type: W
- desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
- default: 0x6400000
- bitfield:
- - range: 63..0
-
- - name: BUSY_THRESHOLD_NEGATE
- type: W
- desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
- default: 0x6E00000
- bitfield:
- - range: 63..0
-
- - name: BUSY_STATUS
- type: R
- bitfield:
- - range: 0
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
-
- - name: PC_PTR_GAP
- type: W
- desc: This is the minimum value that the pc_pointer in a descriptor has to decrease in order to flip the evencycle_pc bit
- default: 0x1000000
- bitfield:
- - range: 63..0
-
- - name: TOHOSTFIFO_EMPTY
- type: R
- desc: Empty flags of the ToHost FIFOs in Wupper
- bitfield:
- - range: 3..0
-
- - name: TOHOSTFIFO_PEMPTY
- type: R
- desc: Programmable empty flags of the ToHost FIFOs in Wupper
- bitfield:
- - range: 3..0
-
- - name: FROMHOSTFIFO_FULL
- type: R
- desc: Full flag of the FromHost FIFO in Wupper
- bitfield:
- - range: 0
-
- - name: FROMHOSTFIFO_PFULL
- type: R
- desc: Programmable full flag of the FromHost FIFO in Wupper
- bitfield:
- - range: 0
-
-
-DMA_DESC:
- number: 8
- type: W
- entries:
- - name: DMA_DESC_{index}
- bitfield:
- - range: 127..64
- name: END_ADDRESS
- desc: End Address
- - range: 63..0
- name: START_ADDRESS
- desc: Start Address
- - name: DMA_DESC_{index}a
- bitfield:
- - range: 127..64
- name: SW_POINTER
- desc: Pointer controlled by the software, indicating read or write status for circular DMA
- - range: 12
- name: WRAP_AROUND
- desc: Wrap around
- - range: 11
- type: R
- name: FROMHOST
- desc: "1: fromHost/ 0: toHost"
- - range: 10..0
- name: NUM_WORDS
- desc: Number of 32 bit words
-
-DMA_DESC_STATUS:
- number: 8
- entries:
- - name: DMA_DESC_STATUS_{index}
- bitfield:
- - range: 66
- name: EVEN_PC
- desc: Even address cycle PC
- - range: 65
- name: EVEN_DMA
- desc: Even address cycle DMA
- - range: 64
- name: DESC_DONE
- desc: Descriptor Done
- - range: 63..0
- name: FW_POINTER
- desc: Pointer controlled by the firmware, indicating where the DMA is busy reading or writing
-
-
-#Bar1 contains the registers dedicated to the Wupper interrupt controller.
-#Please only edit registers in Bar2.
-#Registers in this group will not be generated with WupperCodeGen
-Bar1:
- endpoints: 0,1
- type: W
- entries:
- - ref: INT_VEC
- - name: INT_TAB_ENABLE
- offset: 0x100
- bitfield:
- - range: 7..0
- desc: |
- Interrupt Table enable
- Selectively enable Interrupts
-
-INT_VEC:
- number: 16
- type: W
- entries:
- - name: INT_VEC_{index}
- bitfield:
- - range: 127..96
- name: INT_CTRL
- desc: Interrupt Control
- - range: 95..64
- name: INT_DATA
- desc: Interrupt Data
- - range: 64..0
- name: INT_ADDRESS
- desc: Interrupt Address
-
-#Bar 2 contains application specific registers, used in the example application.
-#Registers in this group (and it's referenced subroups) will be generated with
-#WupperCodeGen for wupper Firmware, Software and Documentation
-Bar2:
- entries:
- - ref: GenericBoardInformation
- offset: 0x0000
- - ref: CRToHostControlsAndMonitors
- offset: 0x0800
- - ref: CRFromHostControlsAndMonitors
- offset: 0x1000
- - ref: DecodingControlsAndMonitors
- offset: 0x1800
- - ref: EncodingControlsAndMonitors
- offset: 0x3000
- - ref: FrontendEmulatorControlsAndMonitors
- offset: 0x4000
- - ref: LinkWrapperControls
- offset: 0x5000
- - ref: LinkWrapperMonitors
- offset: 0x6000
- - ref: TTCBUSYControlsAndMonitors
- offset: 0x7000
- - ref: XOFF_BUSYControlsAndMonitors
- offset: 0x8000
- - ref: LTITTCBUSYControlsAndMonitors
- offset: 0x8800
- - ref: HouseKeepingControlsAndMonitors
- offset: 0x9000
- - ref: Generators
- offset: 0xA000
- - ref: Wishbone
- offset: 0xC000
- - ref: IPBus
- offset: 0xC800
- - ref: ITK_STRIPS_CTRL # ITk strips global controls
- offset: 0xD000
- - ref: MRODregisters
- offset: 0xF000
- - ref: MRODmonitors
- offset: 0xF800
-
-
-
-GenericBoardInformation:
- group: GEN
- desc: Generic Board Information
- endpoints: 0,1
- entries:
- - name: REG_MAP_VERSION
- bitfield:
- - range: 15..0
- value: std_logic_vector(to_unsigned({{ tree.version|version }},16))
- desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
-
- - name: BOARD_ID_TIMESTAMP
- bitfield:
- - range: 39..0
- value: BUILD_DATETIME
- desc: Board ID Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_COMMIT_TIME
- offset: 0x30
- bitfield:
- - range: 39..0
- value: COMMIT_DATETIME
- desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
-
- - name: GIT_TAG
- bitfield:
- - range: 63..0
- value: GIT_TAG(63 downto 0)
- desc: String containing the current GIT TAG
-
- - name: GIT_COMMIT_NUMBER
- bitfield:
- - range: 31..0
- value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
- desc: Number of GIT commits after current GIT_TAG
-
- - name: GIT_HASH
- bitfield:
- - range: 31..0
- value: GIT_HASH(159 downto 128)
- desc: Short GIT hash (32 bit)
-
- - name: STATUS_LEDS
- type: W
- bitfield:
- - range: 7..0
- default: 0xAB
- desc: Board GPIO Leds
-
- - name: GENERIC_CONSTANTS
- bitfield:
- - range: 35..32
- name: TRICKLE_DESCRIPTOR_INDEX
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,4))
- desc: Index of the (first if more than one) Trickle descriptor
- - range: 31..28
- name: FROMHOST_DESCRIPTOR_INDEX
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS-1,4))
- desc: Index of the (first if more than one) FromHost descriptor
- - range: 27..24
- name: TRICKLE_DESCRIPTORS
- value: std_logic_vector(to_unsigned(1,4))
- desc: Number of Trickle descriptors
- - range: 23..20
- name: FROMHOST_DESCRIPTORS
- value: std_logic_vector(to_unsigned(1,4))
- desc: Number of FromHost descriptors
- - range: 19..16
- name: TOHOST_DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS-1,4))
- desc: Number of ToHost descriptors
- - range: 15..8
- name: INTERRUPTS
- value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
- desc: Number of Interrupts
- - range: 7..0
- name: DESCRIPTORS
- value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
- desc: Number of Descriptors Tohost + FromHost excluding trickle descriptor
-
- - name: NUM_OF_CHANNELS
- bitfield:
- - range: 7..0
- desc: Number of GBT or FULL mode Channels
-
- - name: CARD_TYPE
- bitfield:
- - range: 63..0
- value: std_logic_vector(to_unsigned(CARD_TYPE,64))
- desc: |
- Card Type:
- - 709 (0x2c5): FLX709, VC709
- - 710 (0x2c6): FLX710, HTG710
- - 711 (0x2c7): FLX711, BNL711
- - 712 (0x2c8): FLX712, BNL712
- - 128 (0x080): FLX128, VCU128
- - 180 (0x0B4): FLX180, VMK180
- - 181 (0x0B5): FLX181, BNL181
- - 182 (0x0B6): FLX182, BNL182
-
- - name: GENERATE_GBT
- offset: 0xc0
- bitfield:
- - range: 0
- desc: 1 when the GBT Wrapper is included in the design
-
- - name: OPTO_TRX_NUM
- bitfield:
- - range: 7..0
- desc: Number of optical transceivers in the design
-
- - name: GENERATE_TTC_EMU
- type: R
- bitfield:
- - range: 1
- type: R
- desc: 1 when TTC emulator is generated
-
- - offset: 0x100
- ref: INCLUDE_EGROUPS
-
-
- - name: WIDE_MODE
- type: R
- bitfield:
- - range: 0
- desc: GBT is configured in Wide mode
-
- - name: FIRMWARE_MODE
- type: R
- offset: 0x190
- bitfield:
- - range: 4..0
- desc: |
- 0: GBT mode
- 1: FULL-GBT
- 2: LTDB mode (GBT mode with only IC and TTC links)
- 3: FEI4 mode
- 4: ITK Pixel
- 5: ITK Strip
- 6: FELIG GBT
- 7: FULL mode emulator
- 8: FELIX_MROD mode
- 9: lpGBT mode
- 10: 25G Interlaken
- 11: FELIG LPGBT
- 12: HGTD_LUMI
- 13: BCMPRIME
- 14: FELIG_PIXEL
- 15: FELIG_STRIP
-
- - name: GTREFCLK_SOURCE
- type: R
- bitfield:
- - range: 1..0
- desc: |
- 0: Transceiver reference Clock source from Si5345
- 1: Transceiver reference Clock source from Si5324
- 2: Transceiver reference Clock from internal BUFG (GREFCLK)
-
- - name: CR_GENERICS
- type: R
- bitfield:
- - range: 2
- name: XOFF_INCLUDED
- desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
- - range: 1
- name: DIRECT_MODE_INCLUDED
- desc: Indicates that the Direct mode functionality was built in the Central Router
- - range: 0
- name: FROM_HOST_INCLUDED
- desc: Indicates that the From Host path of the Central router was included in the design
-
- - name: BLOCKSIZE
- type: R
- desc: Number of bytes in a block
- bitfield:
- - range: 15..0
-
- - name: PCIE_ENDPOINT
- type: R
- desc: Indicator of the PCIe endpoint on BNL71x cards with two endpoints. 0 or 1
- bitfield:
- - range: 0
- value: std_logic_vector(to_unsigned(PCIE_ENDPOINT, 1))
-
- - name: CHUNK_TRAILER_32B
- type: R
- desc: Indicator that the chunk trailer is in the new 32-bit format
- bitfield:
- - range: 0
-
- - name: NUMBER_OF_PCIE_ENDPOINTS
- type: R
- desc: Number of PCIe endpoints on the card. The BNL71x cards have 2 endpoints
- bitfield:
- - range: 1..0
-
- - name: AXI_STREAMS_TOHOST
- type: R
- bitfield:
- - range: 23..16
- name: IC_INDEX
- desc: The AXIs ID (EPath-ID) of the ToHost IC E-Link
- - range: 15..8
- name: EC_INDEX
- desc: The AXIs ID (EPath-ID) of the ToHost EC E-Link
- - range: 7..0
- name: NUMBER_OF_STREAMS
- desc: Total number of AXIs IDs (EPath-IDs) per physical link ToHost
-
- - name: AXI_STREAMS_FROMHOST
- type: R
- bitfield:
- - range: 23..16
- name: IC_INDEX
- desc: The AXIs ID (EPath-ID) of the FromHost IC E-Link
- - range: 15..8
- name: EC_INDEX
- desc: The AXIs ID (EPath-ID) of the FromHost EC E-Link
- - range: 7..0
- name: NUMBER_OF_STREAMS
- desc: Total number of AXIs IDs (EPath-IDs) per physical link FromHost
-
- - name: FROMHOST_DATA_FORMAT
- type: R
- desc: |
- 0: The data format is as it was in phase1, supporting only multiples of 2 bytes
- 1: FromHost header uses a 5-bit length field as described in FLX-1355
- 2: FromHost header is 32-bit and the packet length is 256-bit (32 bytes) including the header FLX-1601
- 3: FromHost header is 32-bit and the packet length is 512-bit (64 bytes) including the header FLX-1601
- 4: FromHost header is 32-bit and the packet length is 256-bit (32 bytes) including the header FLX-2294. All header bitfields are 8 bit
- 5: FromHost header is 32-bit and the packet length is 512-bit (64 bytes) including the header FLX-2294. All header bitfields are 8 bit
- 6: FromHost header is 32-bit and the packet length is 1024-bit (128 bytes) including the header FLX-2294. All header bitfields are 8 bit
- bitfield:
- - range: 2..0
-
- - name: FULLMODE_HALFRATE
- type: R
- desc: If set to 1 the FULL mode firmware is running at 4.8Gb instead of the default 9.6Gb
- bitfield:
- - range: 0
-
- - name: SUPPORT_HDLC_DELAY
- type: R
- desc: The HDLC encoders can offload a 1us delay as described in FLX-1826
- bitfield:
- - range: 0
-
- - name: TOHOST_DATA_FORMAT
- type: R
- desc: |
- 0: Use subchunk trailer format
- 1: Use subchunk header format
- 2: Use blockless header format
- bitfield:
- - range: 1..0
-
-
-INCLUDE_EGROUPS:
- number: 7
- entries:
- - format_name: INCLUDE_EGROUP_{index}
- name: INCLUDE_EGROUP
- type_name: INCLUDE_EGROUP
- type: R
- bitfield:
- - range: 9
- name: TOHOST_32
- desc: ToHost EPATH32 is included in this EGROUP
- - range: 8
- name: FROMHOST_02
- desc: FromHost EPATH02 is included in this EGROUP
- - range: 7
- name: FROMHOST_04
- desc: FromHost EPATH04 is included in this EGROUP
- - range: 6
- name: FROMHOST_08
- desc: FromHost EPATH8 is included in this EGROUP
- - range: 5
- name: FROMHOST_HDLC
- desc: FromHost HDLC is included in this EGROUP
- - range: 4
- name: TOHOST_02
- desc: ToHost EPATH02 is included in this EGROUP
- - range: 3
- name: TOHOST_04
- desc: ToHost EPATH04 is included in this EGROUP
- - range: 2
- name: TOHOST_08
- desc: ToHost EPATH08 is included in this EGROUP
- - range: 1
- name: TOHOST_16
- desc: ToHost EPATH16 is included in this EGROUP
- - range: 0
- name: TOHOST_HDLC
- desc: ToHost HDLC is included in this EGROUP
-
-
-CRToHostControlsAndMonitors:
- group: CRTHC
- desc: Central Router ToHost Controls and Monitors
- endpoints: 0,1
- entries:
- - name: TIMEOUT_CTRL
- type: W
- descr: Controls the timout mechanism in the ToHost central router.
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: 1 enables the timout trailer generation for ToHost mode
- - range: 31..0
- name: TIMEOUT
- default: 0xFFFFFFFF
- desc: Number of 40 MHz clock cycles after which a timeout occurs.
- - name: MAX_TIMEOUT
- type: R
- desc: Maximum allowed timeout value
- bitfield:
- - range: 31..0
- - name: CRTOHOST_FIFO_STATUS
- type: W
- descr: Status of the width matching FIFOs in the CRToHost block
- bitfield:
- - range: any
- name: CLEAR
- type: T
- desc: Any write to this register clears the latched FULL flags
- value: 1
- - range: 47..24
- type: R
- name: FULL
- desc: Every bit represents the full flag of a channel FIFO
- - range: 23..0
- type: R
- name: FULL_LATCHED
- desc: like FULL but a latched state, clear by writing to this register
- - name: CRTOHOST_DMA_DESCRIPTOR_1
- type: W
- bitfield:
- - range: any
- name: WR_EN
- type: T
- value: 1
- desc: Any write to this register assigns the DMA ID to the AXIS_ID set in CRTOHOST_DMA_DESCRIPTOR_2.AXIS_ID
- - range: 2..0
- name: DESCR
- desc: Target descriptor
- - name: CRTOHOST_DMA_DESCRIPTOR_2
- type: W
- bitfield:
- - range: 13..11
- name: DESCR_READ
- type: R
- desc: Read back the value of the descriptor assigned to AXIS_ID
- - range: 10..0
- name: AXIS_ID
- desc: ID of the AXI stream (E-Path ID) to associate with CRTOHOST_DMA_DESCRIPTOR_1.DESCR
- type: W
- - ref: CRTOHOST_INSTANT_TIMEOUT_ENA_GEN
- - name: DISCARD_DATA_FOR_DESCR
- type: W
- bitfield:
- - range: 15..8
- name: FIFO_FULL
- desc: Discard data for a given DMA channel when Wupper FIFO is full, even if DMA is enabled
- default: 0
- - range: 7..0
- name: DMA_DISABLED
- desc: Discard data for a given DMA channel when Wupper FIFO is full, and the descriptor is not enabled
- default: 0xFF
-
-CRTOHOST_INSTANT_TIMEOUT_ENA_GEN:
- number: 24
- type: W
- entries:
- - name: CRTOHOST_INSTANT_TIMEOUT_ENA
- format_name: CRTOHOST_INSTANT_TIMEOUT_ENA_{index:02}
- type_name: CRTOHOST_INSTANT_TIMEOUT_ENA
- desc: Enable instant timeout after the first data arrives in CRToHost.
- type: W
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 41..0
-
-CRFromHostControlsAndMonitors:
- group: CRFHC
- desc: Central Router FromHost Controls and Monitors
- endpoints: 0,1
- entries:
- - name: CRFROMHOST_FIFO_STATUS
- type: W
- descr: Status of the width matching FIFOs in the CRFromHost block
- bitfield:
- - range: any
- name: CLEAR
- type: T
- desc: Any write to this register clears the latched FULL flags
- value: 1
- - range: 47..24
- type: R
- name: FULL
- desc: Every bit represents the full flag of a channel FIFO
- - range: 23..0
- type: R
- name: FULL_LATCHED
- desc: like FULL but a latched state, clear by writing to this register
- - ref: BROADCAST_ENABLE_GEN
- - name: CRFROMHOST_RESET
- descr: Self clearing reset for CRFromHost and Encoding
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
-
-
-BROADCAST_ENABLE_GEN:
- number: 24
- type: W
- entries:
- - name: BROADCAST_ENABLE
- format_name: BROADCAST_ENABLE_{index:02}
- type_name: BROADCAST_ENABLE
- desc: Enable path to be included in a broadcast message.
- type: W
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 41..0
-
-DecodingControlsAndMonitors:
- desc: Decoding block
- endpoints: 0,1
- entries:
- - name: ELINK_REALIGNMENT
- type: W
- fw_modes: 0,2,3,4,5,6,9,11,12,13,14,15
- bitfield:
- - range: any
- name: CLEAR_REALIGNMENT_STATUS
- type: T
- value: 1
- desc: Clears the ELINK Realignment event flags
- - range: 0
- name: ENABLE
- default: 1
- desc: Enable realignment mechanism in 8b10b E-Links after illegal character reception.
-
- - ref: ELINK_REALIGNMENT_STATUS_GEN
- - ref: ELINK_REALIGNMENT_COUNT_GEN
- - ref: PATH_HAS_STREAM_ID
- offset: 0x800
- - ref: DECODING_LINK_STATUS_ARR
- - ref: DECODING_EGROUP_CTRL_GEN
- - ref: MINI_EGROUP_TOHOST_GEN
- - name: TTC_TOHOST_ENABLE
- desc: Enables the ToHost Mini Egroup in TTC mode
- type: W
- bitfield:
- - range: 0
- default: 1
- - name: DECODING_REVERSE_10B
- desc: |
- Reverse 10-bit word of elink data for 8b10b E-links
- 1: Receive 10-bit word in ToHost E-Paths, MSB first
- 0: Receive 10-bit word in ToHost E-Paths, LSB first
- type: W
- fw_modes: 0,2,3,4,5,6,9,11,12,13,14,15
- bitfield:
- - range: 0
- default: 1
- - name: DECODING_ENDIANNESS_FULL_MODE
- desc: |
- Specify the byte order in FULL mode
- 1: Big-endian
- 0: Little-endian
- type: W
- fw_modes: 1
- bitfield:
- - range: 0
- type: W
- default: 0
-
-# - ref: RD53B_PROCESSOR_GEN
- - ref: YARR_DEBUG_ALLEGROUP_TOHOST_GEN
- desc: Count receive packets of a given value
- - ref: PATH_ERRORS
- - name: INTERLAKEN_CONTROL
- desc: Configures Interlaken decoder
- type: W
- fw_modes: 10
- bitfield:
- - range: 12
- type: R
- name: HEALTH_INTERFACE
- default: 1
- desc: Automatically detect the lane number in the interlaken descrambler
- - range: 11..0
- name: PACKET_LENGTH
- desc: Lenth of an interlaken metaframe
- default: 2024
- - ref: INTERLAKEN_STATUS_GEN
- - ref: SUPER_CHUNK_FACTOR_GEN
- offset: 0x15E0
- - ref: DECODING_LINK_CB_GEN
- - name: DECODING_MASK64B66BKBLOCK
- desc: Mask User K-Block based on its block number (see sp011)
- type: W
- fw_modes: 4
- bitfield:
- - range: 3..0
- default: 10
- - name: DECODING_DISEGROUP
- desc: Disable egroups for debugging purposes
- type: W
- bitfield:
- - range: 6..0
- default: 0
-
- - name: FULLMODE_32B_SOP
- type: W
- desc: When set to 1, use 32-bit 0x0000003C as start of chunk, otherwise only 8-bit 0x3C (FULL mode only)
- fw_modes: 1
- bitfield:
- - range: 0
- default: 0
-
- - name: DECODING_HGTD_ALTIROC
- type: W
- desc: Set to 1 to use HGTD Altiroc K characters in the 8b10b decoders (LPGBT firmware mode)
- fw_modes: 9
- bitfield:
- - range: 0
- default: 0
-
- - name: DECODING_HGTD_LUMI_CONF
- type: W
- desc: HGTD Luminosity firmware configuration
- fw_modes: 12
- bitfield:
- - range: 36
- name: DEBUG_DATASOURCE
- default: 0
- desc: enable local data source for debugging
- - range: 35
- name: RAW_MODE
- default: 0
- desc: enable RAW mode (just forwarding 6b8b data)
- - range: 34..25
- name: LHC_TURNS
- default: 100
- desc: number of LHC turns to aggregate
- - range: 24..16
- name: TRIG_LAT
- default: 0
- desc: trigger latency for per-event luminosity
- - range: 15..0
- name: SYNC_WORD
- default: 0x4778
- desc: sync word for luminosity stream
-
-ELINK_REALIGNMENT_STATUS_GEN:
- endpoints: 0, 1
- number: 12
- fw_modes: 0,2,3,4,5,6,9,11,12,13,14,15
- entries:
- - name: ELINK_REALIGNMENT_STATUS
- type_name: ELINK_REALIGNMENT_STATUS
- format_name: ELINK_REALIGNMENT_STATUS_{index:02}
- generate: GBT_NUM > {index:1}
- desc: |
- A realignment event due to an illegal 8b10b symbol has occurred.
- 1 bit per Epath.
- Clear status by writing to ELINK_REALIGNMENT.CLEAR_REALIGNMENT_STATUS
- bitfield:
- - range: 41..0
-
-ELINK_REALIGNMENT_COUNT_GEN:
- endpoints: 0, 1
- number: 12
- fw_modes: 0,2,3,4,5,6,9,11,12,13,14,15
- entries:
- - name: ELINK_REALIGNMENT_COUNT
- type_name: ELINK_REALIGNMENT_COUNT
- format_name: ELINK_REALIGNMENT_COUNT_{index:02}
- generate: GBT_NUM > {index:1}
- desc: |
- A realignment event due to an illegal 8b10b symbol on any E-Link in the link increments the counter.
- Clear status by writing to ELINK_REALIGNMENT.CLEAR_REALIGNMENT_STATUS
- bitfield:
- - range: 31..0
-
-PATH_HAS_STREAM_ID:
- number: 24
- generate: GBT_NUM > {index:1}
- entries:
- - name: HAS_STREAM_ID
- format_name: LINK_{index:02}_HAS_STREAM_ID
- type_name: HAS_STREAM_ID
- type: W
- bitfield:
- - range: 55..48
- name: EGROUP6
- default: 0x0
- desc: EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- - range: 47..40
- name: EGROUP5
- default: 0x0
- desc: EPATH (Wide mode or lpGBT) is associated with a STREAM ID
- - range: 39..32
- name: EGROUP4
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 31..24
- name: EGROUP3
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 23..16
- name: EGROUP2
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 15..8
- name: EGROUP1
- default: 0x0
- desc: EPATH is associated with a STREAM ID
- - range: 7..0
- name: EGROUP0
- default: 0x0
- desc: EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
-
-DECODING_LINK_STATUS_ARR:
- number: 24
- type: R
- entries:
- - name: DECODING_LINK_ALIGNED
- format_name: DECODING_LINK_ALIGNED_{index:02}
- type_name: DECODING_LINK_ALIGNED
- desc: Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used
- bitfield:
- - range: 57..0
-
-DECODING_EGROUP_CTRL_GEN:
- number: 12
- format_name: DECODING_EGROUP_GEN
- generate: GBT_NUM > {index:1}
- entries:
- - ref: DECODING_EGROUP
-
-DECODING_EGROUP:
- number: 7
- format_name: LINK{index:02}
- type_name: DECODING_EGROUP
- entries:
- - name: EGROUP
- format_name: DECODING_{parent}_{name}{index:1}_CTRL
- type_name: DECODING_EGROUP_CTRL
- desc: Contols Egroup for lpGBT and GBT based links
- type: W
- bitfield:
- - range: 59
- name: ENABLE_TRUNCATION
- type: W
- desc: Enable truncation mechanism in HDLC decoder for chunks > 12 bytes
- default: 0
- - range: 58..51
- name: EPATH_ALMOST_FULL
- type: R
- desc: FIFO full indication
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..11
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 4 bits per E-path
- 0: direct mode
- 1: 8b10b mode
- 2: HDLC mode
- 3: TTC
- 4: ITk Strips 8b10b
- 5: ITk Pixel
- 6: Endeavour
- 7-15: reserved
- default: 0x11111111
- - range: 10..8
- name: EPATH_WIDTH
- default: 0
- desc: Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32
- - range: 7..0
- name: EPATH_ENA
- desc: Enable bits per EPATH
- default: 0
-
-MINI_EGROUP_TOHOST_GEN:
- number: 24
- type: W
- fw_modes: 0,2,3,4,5,9,12,13
- entries:
- - name: MINI_EGROUP_TOHOST
- format_name: MINI_EGROUP_TOHOST_{index:02}
- type_name: MINI_EGROUP_TOHOST
- desc: Configures the ToHost Mini egroup
- type: W
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 15
- name: ENABLE_AUX_TRUNCATION
- type: W
- desc: Enable truncation mechanism in HDLC decoder for chunks > 12 bytes
- default: 0
- - range: 14
- name: ENABLE_IC_TRUNCATION
- type: W
- desc: Enable truncation mechanism in HDLC decoder for chunks > 12 bytes
- default: 0
- - range: 13
- name: ENABLE_EC_TRUNCATION
- type: W
- desc: Enable truncation mechanism in HDLC decoder for chunks > 12 bytes
- default: 0
- - range: 12
- type: R
- name: AUX_ALMOST_FULL
- desc: Indicator that the AUX path FIFO is almost full
- - range: 11
- name: AUX_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 10
- name: AUX_ENABLE
- desc: Enables the AUX channel
- default: 1
- - range: 9
- type: R
- name: IC_ALMOST_FULL
- desc: Indicator that the IC path FIFO is almost full
- - range: 8
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 7
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 6
- type: R
- name: EC_ALMOST_FULL
- desc: Indicator that the EC path FIFO is almost full
- - range: 5
- name: EC_BIT_SWAPPING
- desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 4..1
- name: EC_ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: EC_ENABLE
- desc: Enables the EC channel
- default: 1
-
-
-#RD53B_PROCESSOR_GEN:
-# number: 64
-# entries:
-# - name: RD53B_PROCESSOR
-# format_name: RD53B_PROCESSOR_{index:02}
-# type_name: RD53B_PROCESSOR
-# bitfield:
-# - range: 3
-# name: ENABLE_MULTICHIP
-# - range: 2
-# name: ENABLE_BINARYTREE
-# - range: 1
-# name: ENABLE_TOT
-# - range: 0
-# name: DROP_TOT
-
-SUPER_CHUNK_FACTOR_GEN:
- number: 12
- entries:
- - name: SUPER_CHUNK_FACTOR_LINK
- format_name: SUPER_CHUNK_FACTOR_LINK_{index:02}
- type_name: SUPER_CHUNK_FACTOR_LINK
- type: W
- desc: number of chunks glued together
- bitfield:
- - range: 7..0
- default: 1
-
-DECODING_LINK_CB_GEN:
- number: 12
- fw_modes: 4
- entries:
- - name: DECODING_LINK_CB
- format_name: DECODING_LINK_{index:02}_CB
- type_name: DECODING_LINK_CB
- type: W
- bitfield:
- - name: DESKEWED
- range: 61..4
- type: R
- desc: |
- Every bit corresponds to an E-link on one (lp)GBT frame.
- Register indicates whether the E-link has been de-skewed in the channel.
- E-link are grouped in a channel according to CBOPT
- - name: CBOPT
- range: 3..0
- desc: |
- Channel bonding option
- 0: no bonding
- 3: Bonding 0/1/2 3/4/5
- other values: reserved
- default: 0
-
-YARR_DEBUG_ALLEGROUP_TOHOST_GEN:
- number: 12
- fw_modes: 4,5
- entries:
- - name: YARR_DEBUG_ALLEGROUP_TOHOST
- format_name: YARR_DEBUG_ALLEGROUP_TOHOST_{index:02}
- type_name: YARR_DEBUG_ALLEGROUP_TOHOST
- type: W
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 63..32
- name: REF_PACKET
- type: W
- desc: Reference packet to be matched
- default: 0x02000000
- - range: 31..0
- name: CNT_RX_PACKET
- type: R
- desc: Count packets of a given value
-
-YARR_DEBUG_ALLEGROUP_FROMHOST_GEN:
- fw_modes: 4,5
- number: 12
- entries:
- - name: YARR_DEBUG_ALLEGROUP_FROMHOST1
- format_name: YARR_DEBUG_ALLEGROUP_FROMHOST1_{index:02}
- type_name: YARR_DEBUG_ALLEGROUP_FROMHOST1
- type: W
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 48
- type: W
- name: RD53A_AZ_EN
- desc: Auto zeroing module enable
- default: 0
- - range: 47..16
- type: R
- name: CNT_TRIG_CMD
- desc: Number of issued triggers via cmd
- - range: 15..8
- type: R
- name: ERR_GENCALTRIG_DLY
- desc: Number of mismatches between CNT_GENCALTRIG_DLY and REF_DLY_GENCALTRIG
- - range: 7..0
- type: W
- name: REF_DLY_GENCALTRIG
- desc: Reference distance between GenCal and First Trigger
- default: 0x0F
- - name: YARR_DEBUG_ALLEGROUP_FROMHOST2
- format_name: YARR_DEBUG_ALLEGROUP_FROMHOST2_{index:02}
- type_name: YARR_DEBUG_ALLEGROUP_FROMHOST2
- type: W
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 47..16
- type: R
- name: CNT_CMD
- desc: Number of issued commands
- - range: 15..0
- type: W
- name: REF_CMD
- desc: Cmd type to be counted. See RD53 Manual for list of allowed commands
- default: 0x6666
-
-PATH_ERRORS:
- number: 24
- generate: GBT_NUM > {index:1}
- entries:
- - name: LINK_ERRORS
- fw_modes: 0,4,5,9
- format_name: LINK_{index:02}_ERRORS
- type_name: LINK_ERRORS
- type: W
- bitfield:
- - range: 35
- name: CLEAR_COUNTERS
- type: W
- desc: Set to 1 to clear all counter values for all egroups in the link. Set to 0 to start counting errors.
- - range: 34..32
- name: EGROUP_SELECT
- desc: Errors for Egroup1
- type: W
- - range: 31..0
- name: COUNT
- desc: Errors for the selected egroup
- type: R
-
-
-INTERLAKEN_STATUS_GEN:
- number: 12
- generate: GBT_NUM > {index:1}
- entries:
- - name: INTERLAKEN_STATUS
- fw_modes: 4
- format_name: INTERLAKEN_LANE_{index:02}_STATUS
- type_name: INTERLAKEN_STATUS
- type: W
- fw_modes: 10
- bitfield:
- - range: any
- type: T
- name: CLEAR_STATUS
- value: 1
- - range: 8
- type: R
- name: DECODER_ERROR_SYNC
- desc: Sticky error bit, clear with CLEAR_STATUS
- - range: 7
- type: R
- name: DESCRAMBLER_ERROR_BADSYNC
- desc: Sticky error bit, clear with CLEAR_STATUS
- - range: 6
- type: R
- name: DESCRAMBLER_ERROR_STATEMISMATCH
- desc: Sticky error bit, clear with CLEAR_STATUS
- - range: 5
- type: R
- name: DESCRAMBLER_ERROR_NOSYNC
- desc: Sticky error bit, clear with CLEAR_STATUS
- - range: 4
- type: R
- name: BURST_CRC24_ERROR
- desc: Sticky CRC error bit, clear with CLEAR_STATUS
- - range: 3
- type: R
- name: META_CRC32_ERROR
- desc: Sticky CRC error bit, clear with CLEAR_STATUS
- - range: 2
- type: R
- name: HEALTH_LANE
- desc: Health bit for this lane
- - range: 1
- type: R
- name: DESCRAMBLER_ALIGNED
- desc: This channels descrambler is aligned
- - range: 0
- type: R
- name: DECODER_ALIGNED
- desc: This channels decoder is aligned
-
-
-
-EncodingControlsAndMonitors:
- desc: Encoding block
- endpoints: 0,1
- entries:
- - name: ENCODING_REVERSE_10B
- desc: Reverse 10-bit word of elink data for 8b10b E-links. 1 MSB first, 0 LSB first
- type: W
- fw_modes: 0,1,2,3,6,9,10,11,12,13,14,15
- bitfield:
- - range: 0
- default: 1
- - ref: ENCODING_EGROUP_CTRL_GEN
- - ref: MINI_EGROUP_FROMHOST_GEN
- - ref: ENCODING_EGROUP_CTRL_FEI4_GEN
- - ref: YARR_DEBUG_ALLEGROUP_FROMHOST_GEN
- desc: Count triggers, compare distance between GenCal and Trigger with reference. Check YARR doc
- - name: YARR_FROMHOST_CALTRIGSEQ_WE
- fw_modes: 4,5
- desc: enable to store CalPulse+Trigger Sequence into memory
- type: W
- bitfield:
- - range: 0
- default: 0
- - name: YARR_FROMHOST_CALTRIGSEQ_WRDATA
- fw_modes: 4,5
- desc: CalPulse+Trigger Sequence to be stored in memory
- type: W
- bitfield:
- - range: 15..0
- - name: YARR_FROMHOST_CALTRIGSEQ_WRADDR
- fw_modes: 4,5
- desc: memory address to store CalPulse+Trigger Sequence
- type: W
- bitfield:
- - range: 4..0
- - name: HGTD_ALTIROC_FASTCMD
- fw_modes: 9
- desc: Controls the HGTD Altiroc FASTCMD TTC encoder functionality (TTC option 8).
- type: W
- bitfield:
- - range: 14
- name: ALTIROC3_IDLE
- desc: 0 for ALTIROC2 10101100, 1 for ALTIROC3 11110000
- default: 0
- - range: 13
- name: USE_CAL
- desc: When set to 1, CAL will be sent on L1A, then after TRIG_DELAY BC clocks a TRIGGER. When 0, TRIGGER will be sent on L1A.
- default: 1
- - range: 12
- name: SYNCLUMI
- desc: Set to 1 to trigger a SYNCLUMI command, rising edge of this bit. Clear in software
- default: 0
- - range: 11
- name: GBRST
- desc: Set to 1 to trigger a GBRST command, rising edge of this bit. Clear in software
- default: 0
- - range: 10..0
- name: TRIG_DELAY
- desc: Number of BC clocks between CAL and TRIGGER command if USE_CAL is set to 1
- default: 5
- - name: ITKSTRIP_LCB_R3L1_ELINK_SWAP
- fw_modes: 5
- desc: Setting a bit, moves the LCB E-Link to the odd E-Link position and R3L1 to the even one on the lpGBT downlink. 4 bits per lpGBT link
- type: W
- bitfield:
- - range: 47..0
-
- - name: ENCODING_ITKPIX_TRIGGER_GENERATOR
- fw_modes: 4
- desc: Controls the trigger generator for ItkPix
- type: W
- bitfield:
- - range: 28
- name: NO_INJECT
- default: 0
- - range: 27
- name: EDGE_MODE
- default: 1
- - range: 26..22
- name: EDGE_DELAY
- default: 0
- - range: 21..14
- name: EDGE_DURATION
- default: 20
- - range: 13..6
- name: TRIG_DELAY
- default: 58
- - range: 5..0
- name: TRIG_MULTIPLIER
- default: 16
- - name: LTI_FE_OUTPUT_SELECTOR
- fw_modes: 1, 10
- type: W
- desc: |
- 0: Low latency LTI-FE distribution
- 1: 40 MHz sync LTI-FE distribution
- bitfield:
- - range: 1..0
-
-
-ENCODING_EGROUP_CTRL_GEN:
- number: 12
- type: W
- generate: GBT_NUM > {index:1}
- entries:
- - ref: ENCODING_EGROUP
-
-
-ENCODING_EGROUP:
- number: 5
- format_name: LINK{index:02}
- entries:
- - name: ENCODING_EGROUP_CTRL
- desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
- format_name: ENCODING_{parent}_EGROUP{index:1}_CTRL
- type_name: ENCODING_EGROUP_CTRL
- bitfield:
- - range: 63
- name: ENABLE_DELAY
- desc: Enable inter-packet delay generation in HDLC encoder
- default: 0x0
- - range: 62..59
- name: TTC_OPTION
- desc: Selects TTC bits sent to the E-link
- - range: 58..51
- name: EPATH_ALMOST_FULL
- type: R
- desc: Indiator that the EPATH FIFO is almost full
- - range: 50..43
- name: REVERSE_ELINKS
- default: 0x0
- desc: enables bit reversing for the elink in the given epath
- - range: 42..40
- name: EPATH_WIDTH
- default: 0x0
- desc: |
- Width of the Elinks in the egroup
- 0: 2 bit 80 Mb/s
- 1: 4 bit 160 Mb/s
- 2: 8 bit 320 Mb/s
- - range: 39..8
- name: PATH_ENCODING
- desc: |
- Encoding for every EPATH, 4 bits per E-Path
- 0: No encoding
- 1: 8b10b mode
- 2: HDLC mode
- 3: ITk Strip LCB
- 4: ITk Pixel
- 5: Endeavour
- 6: reserved
- 7: reserved
- greater than 7: TTC mode, see firmware Phase 2 specification doc
- default: 0x11111111
- - range: 7..0
- desc: Enable bits per E-PATH
- name: EPATH_ENA
-
-MINI_EGROUP_FROMHOST_GEN:
- number: 24
- type: W
- generate: GBT_NUM > {index:1}
- fw_modes: 0,1,2,3,4,5,9,10,12,13
- entries:
- - name: MINI_EGROUP_FROMHOST
- format_name: MINI_EGROUP_FROMHOST_{index:02}
- type_name: MINI_EGROUP_FROMHOST
- type: W
- desc: Configures the FromHost Mini egroup
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 17..14
- name: AUX_ENCODING
- desc: Configures encoding of the AUX channel
- default: 0x2
- - range: 13
- name: ENABLE_DELAY
- desc: Enable inter-packet delay generation in HDLC encoder
- default: 0x0
- - range: 12
- name: AUX_ALMOST_FULL
- type: R
- desc: Indicator that the AUX Path FIFO is almost full
- - range: 11
- name: AUX_BIT_SWAPPING
- desc: "0: two input bits of AUX e-link are as documented, 1: two input bits are swapped"
- default: 1
- - range: 10
- name: AUX_ENABLE
- desc: Enables the AUX channel
- default: 1
- - range: 9
- name: IC_ALMOST_FULL
- type: R
- desc: Indicator that the IC Path FIFO is almost full
- - range: 8
- name: IC_BIT_SWAPPING
- desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
- default: 0
- - range: 7
- name: IC_ENABLE
- desc: Enables the IC channel
- default: 1
- - range: 6
- name: EC_ALMOST_FULL
- type: R
- desc: Indicator that the EC Path FIFO is almost full
- - range: 5
- name: EC_BIT_SWAPPING
- desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
- default: 0
- - range: 4..1
- name: EC_ENCODING
- desc: Configures encoding of the EC channel
- default: 0x2
- - range: 0
- name: EC_ENABLE
- default: 1
-
-ENCODING_EGROUP_CTRL_FEI4_GEN:
- number: 12
- type: W
- fw_modes: 3
- generate: GBT_NUM > {index:1} and FIRMWARE_MODE = FIRMWARE_MODE_FEI4
- entries:
- - ref: ENCODING_EGROUP_FEI4
-
-
-ENCODING_EGROUP_FEI4:
- number: 5
- format_name: LINK{index:02}
- entries:
- - name: ENCODING_EGROUP_FEI4_CTRL
- desc: FEI4 encoder configuration registers.
- format_name: ENCODING_{parent}_EGROUP{index:1}_FEI4_CTRL
- type_name: ENCODING_EGROUP_FEI4_CTRL
- bitfield:
- - range: 11..9
- name: PHASE_DELAY1
- desc: phase delay of output data, with 320 Bb/s e-link 8 phases per BC
- - range: 8
- name: MANCHESTER_ENABLE1
- desc: enable manchester encoding
- - range: 7
- name: AUTOMATIC_MERGE_DISABLE1
- desc: Disable automatic merging
- - range: 6
- name: TTC_SELECT1
- desc: TTC/FromHost select (if automatic merging is disabled)
- - range: 5..3
- name: PHASE_DELAY0
- desc: phase delay of output data, with 320 Bb/s e-link 8 phases per BC
- - range: 2
- name: MANCHESTER_ENABLE0
- desc: enable manchester encoding
- - range: 1
- name: AUTOMATIC_MERGE_DISABLE0
- desc: Disable automatic merging
- - range: 0
- name: TTC_SELECT0
- desc: TTC/FromHost select (if automatic merging is disabled)
-
-FrontendEmulatorControlsAndMonitors:
- group: FEC
- desc: Frontend Emulator Controls and Monitors
- endpoints: 0, 1
- entries:
- - name: FE_EMU_ENA
- type: W
- bitfield:
- - range: 1
- name: EMU_TOFRONTEND
- desc: Enable GBT dummy emulator ToFrontEnd
-
- - range: 0
- name: EMU_TOHOST
- desc: Enable GBT dummy emulator ToHost
-
- - name: FE_EMU_CONFIG
- type: W
- bitfield:
- - range: 54..47
- name: WE
- desc: write enable array, every bit is one emulator RAM block
- - range: 46..33
- name: WRADDR
- desc: write address bus
- - range: 32..0
- name: WRDATA
- desc: write data bus
-
- - name: FE_EMU_READ
- type: W
- bitfield:
- - range: 35..33
- name: SEL
- desc: Select ramblock to read back
- - range: 32..0
- name: DATA
- type: R
- desc: Read back ramblock at FE_EMU_CONFIG.WRADDR
-
- - name: FE_EMU_LOGIC
- type: W
- bitfield:
- - range: 33
- name: L1A_TRIGGERED
- desc: 1 Send a chunk on every L1A, 0 use the IDLES to determine the rate
- - range: 32
- name: ENA
- desc: Enable logic based FrontEnd emulator, instead of RAM based.
- - range: 31..16
- name: IDLES
- desc: Number of IDLE bytes between chunks.
- - range: 15..0
- name: CHUNK_LENGTH
- desc: Chunk length in bytes
-
- #Continue decoding here, as the decoding space is full.
- - ref: DECODING_BCM_PRIME_L1A_CONTROLS_GEN
- offset: 0x200
-
- - name: DECODING_BCM_PRIME_ONLY_L1A
- type: W
- desc: If enabled, the BCM_PRIME firmware, will only readout data when an L1A is sent.
- fw_modes: 13
- bitfield:
- - range: 0
- - name: DECODING_BCM_PRIME_EMU_BCID
- type: W
- fw_modes: 13
- desc: If enabled, the BCM_PRIME firmware will use internally generated BCIDs instead of the TTC one.
- bitfield:
- - range: 0
-
- - name: DECODING_BCM_PRIME_PUBLISH_ZEROS
- type: W
- fw_modes: 13
- desc: If enabled, the BCM_PRIME firmware publish empty data-events if they are matched with L1A
- bitfield:
- - range: 0
-
-
-
-DECODING_BCM_PRIME_L1A_CONTROLS_GEN:
- number: 24
- fw_modes: 13
- type: W
-
- entries:
- - name: DECODING_BCM_PRIME_L1A
- format_name: DECODING_BCM_PRIME_LINK_{index:02}_L1A
- type_name: DECODING_BCM_PRIME_L1A
-
- generate: GBT_NUM > {index:1}
- bitfield:
- - range: 9..5
- name: DELAY
- default: 5
- desc: The data in fiber is delayed N clock cycles to match with TTC L1A
- - range: 4..0
- name: WINDOW
- default: 5
- desc: The L1A signal is extended to cover multiple BCID's
-
-LinkWrapperControls:
- group: LWC
- desc: Link Wrapper Controls
- type: W
- endpoints: 0
- entries:
- - name: LINK_FULLMODE_LTI
- fw_modes: 1, 7
- desc: Set to 1 to enable LTI format TTC distribution (8b10b at 9.6Gb) in the FULLMODE flavour, one bit per channel. Set to 0 for 4.8Gb GBT distribution
- type: W
- bitfield:
- - range: 23..0
- default: 0
-
- - name: GBT_CHANNEL_DISABLE
- offset: 0x0400
- bitfield:
- - range: 47..0
- desc: Disable selected lpGBT, GBT or FULL mode channel
-
- - name: GBT_GENERAL_CTRL
- bitfield:
- - range: 63..0
- desc: Alignment chk reset (not self clearing)
-
- - name: GBT_MODE_CTRL
- bitfield:
- - range: 2
- name: RX_ALIGN_TB_SW
- desc: RX_ALIGN_TB_SW
- - range: 1
- name: RX_ALIGN_SW
- desc: RX_ALIGN_SW
- - range: 0
- name: DESMUX_USE_SW
- desc: DESMUX_USE_SW
-
- - name: GBT_RXSLIDE_SELECT
- offset: 0x0480
- desc: RxSlide select [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXSLIDE_MANUAL
- desc: RxSlide select [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXUSRRDY
- desc: TxUsrRdy [47:0]
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_RXUSRRDY
- desc: RxUsrRdy [47:0]
- bitfield:
- - range: 47..0
- default: 0xFFFFFFFFFFFF
-
- - name: GBT_SOFT_RESET
- desc: SOFT_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTTX_RESET
- desc: GTTX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GTRX_RESET
- desc: GTRX_RESET [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_RESET
- bitfield:
- - range: 59..48
- name: QPLL_RESET
- desc: QPLL_RESET [11:0]
- - range: 47..0
- name: CPLL_RESET
- desc: CPLL_RESET [47:0]
-
- - name: GBT_SOFT_TX_RESET
- offset: 0x0500
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_SOFT_RX_RESET
- bitfield:
- - range: 59..48
- name: RESET_ALL
- desc: SOFT_TX_RESET_ALL [11:0]
- - range: 47..0
- name: RESET_GT
- desc: SOFT_TX_RESET_GT [47:0]
-
- - name: GBT_ODD_EVEN
- desc: OddEven [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TOPBOT
- desc: TopBot [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_DLY_VALUE1
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [47:0]
-
- - name: GBT_TX_TC_DLY_VALUE2
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [95:48]
-
- - name: GBT_TX_TC_DLY_VALUE3
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [143:96]
-
- - name: GBT_TX_TC_DLY_VALUE4
- bitfield:
- - range: 47..0
- default: 0x333333333333
- desc: TX_TC_DLY_VALUE [191:144]
-
- - name: GBT_DATA_TXFORMAT1
- desc: DATA_TXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_TXFORMAT2
- desc: DATA_TXFORMAT [95:48]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT1
- desc: DATA_RXFORMAT [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_DATA_RXFORMAT2
- desc: DATA_RXFORMAT [95:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_RESET
- desc: TX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_RESET
- desc: RX Logic reset [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TX_TC_METHOD
- desc: TX time domain crossing method [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUTMUX_SEL
- desc: Descrambler output MUX selection [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TC_EDGE
- desc: Sampling edge selection for TX domain crossing [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for transmitter of GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_RXPOLARITY
- desc: |
- 0: default polarity
- 1: reversed polarity for the receiver of the GTH channels
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GTH_LOOPBACK_CONTROL
- bitfield:
- - range: 2..0
- default: 0x0
- desc: |
- Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
- 000: Normal operation
- 001: Near-End PCS Loopback
- 010: Near-End PMA Loopback
- 011: Reserved
- 100: Far-End PMA Loopback
- 101: Reserved
- 110: Far-End PCS Loopback
-
- - name: LPGBT_FEC
- desc: |
- 0: FEC5
- 1: FEC12
- bitfield:
- - range: 47..0
- default: 0
-
- - name: LPGBT_DATARATE
- desc: |
- 0: 10.24 Gbps
- 1: 5.12 Gbps
- bitfield:
- - range: 47..0
- default: 0
-
- - name: GBT_TOHOST_FANOUT
- offset: 0x0700
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0x0
- desc: |
- ToHost FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
- 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
-
- - name: GBT_TOFRONTEND_FANOUT
- bitfield:
- - range: 48
- name: LOCK
- default: 0x0
- desc: Locks this particular register. If set prevents software from touching it.
- - range: 47..0
- name: SEL
- default: 0x0
- desc: |
- ToFrontEnd FanOut/Selector. Every bitfield is a channel:
- 1 : GBT_EMU, select GBT Emulator for a specific GBT link
- 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
-
- - name: FULLMODE_AUTO_RX_RESET
- bitfield:
- - range: 32
- name: ENABLE
- default: 1
- desc: Enable the Automatic RX Reset mechanism
- - range: 31..0
- name: TIMEOUT
- default: 0x00100000
- desc: Number of 40 MHz clock cycles until an unaligned link results in a reset pulse
-
- - ref: TCLINK_CNTRL_GEN
-
-TCLINK_CNTRL_GEN:
- desc: TClink status and control registers that dont have a default value
- number: 24
- endpoints: 0
- entries:
- - name: TCLINK_CONTROL
- format_name: TCLINK_CONTROL_{index:02}
- type_name: TCLINK_CONTROL
- type: W
- desc: tclink control register
- bitfield:
- - range: 63..16
- name: OFFSET_ERROR
- desc: Error-offset for phase-control Recommended to freeze with an initial value read
- - range: 15
- name: CLOSE_LOOP
- desc: Close TCLink loop (enables compensation)
- - range: 14..8
- name: TX_PI_PHASE_CALIB
- desc: UI alignment Tx PI calibrated phase
- - range: 7
- name: TX_UI_ALIGN_CALIB
- desc: UI alignment Tx PI activate
- - range: 6
- name: TX_FINE_REALIGN
- desc: Repeats fine alignment procedure
- - range: 5
- name: PS_STROBE
- desc: Shifts phase of transmitter serial data
- - range: 4
- name: PS_INC_NDEC
- desc: Shifts phase of transmitter serial data
- - range: 3
- name: MASTER_MGT_RX_READY
- desc: MGT rx is ready (used as reset)
-
-
-LinkWrapperMonitors:
- group: LWM
- desc: GBT Wrapper Monitors
- endpoints: 0
- entries:
- - name: GBT_VERSION
- offset: 0x0600
- bitfield:
- - range: 63..48
- name: DATE
- desc: Date
- - range: 47..32
- name: GBT_VERSION
- desc: GBT Version
- - range: 31..16
- name: GTH_IP_VERSION
- desc: GTH IP Version
- - range: 15..3
- name: RESERVED
- desc: Reserved
- - range: 2
- name: GTHREFCLK_SEL
- desc: GTHREFCLK SEL
- - range: 1
- name: RX_CLK_SEL
- desc: RX CLK SEL
- - range: 0
- name: PLL_SEL
- desc: PLL SEL
-
- - name: GBT_TXRESET_DONE
- offset: 0x0680
- desc: TX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXRESET_DONE
- desc: RX Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_TXFSMRESET_DONE
- desc: TX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RXFSMRESET_DONE
- desc: RX FSM Reset done [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_PLL_LOCK
- bitfield:
- - range: 59..48
- name: QPLL_LOCK
- desc: QPLL LOCK [11:0]
- - range: 47..0
- name: CPLL_LOCK
- desc: CPLL LOCK [47:0]
-
- - name: GBT_RXCDR_LOCK
- desc: RX CDR LOCK [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_CLK_SAMPLED
- desc: clk sampled [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_HEADER
- desc: RX IS HEADER [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_IS_DATA
- desc: RX IS DATA [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_RX_HEADER_FOUND
- desc: RX HEADER FOUND [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_OUT_MUX_STATUS
- desc: GBT output mux status [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_ERROR
- desc: Error flags [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_GBT_TOPBOT_C
- desc: TopBot_c [47:0]
- bitfield:
- - range: 47..0
-
- - name: GBT_FM_RX_DISP_ERROR1
- offset: 0x0800
- bitfield:
- - range: 47..0
- desc: Rx disparity error [47:0]
-
- - name: GBT_FM_RX_DISP_ERROR2
- bitfield:
- - range: 47..0
- desc: Rx disparity error [96:48]
-
- - name: GBT_FM_RX_NOTINTABLE1
- bitfield:
- - range: 47..0
- desc: Rx not in table [47:0]
-
- - name: GBT_FM_RX_NOTINTABLE2
- bitfield:
- - range: 47..0
- desc: Rx not in table [96:48]
-
- - ref: GT_FEC_ERR_CNT_GEN
- - ref: GT_AUTO_RX_RESET_CNT_GEN
- - ref: TCLINK_MON_GEN
- - name: GBT_PLL_LOL_LATCHED
- type: W
- bitfield:
- - range: any
- name: CLEAR
- value: 1
- desc: Any write to this bitfield clears the latched LOL bits
- type: T
- - range: 59..48
- name: QPLL_LOL_LATCHED
- desc: Asserted when CPLL lock is lost, clear by writing to CLEAR
- type: R
- - range: 47..0
- name: CPLL_LOL_LATCHED
- desc: Asserted when CPLL lock is lost, clear by writing to CLEAR
- type: R
-
- - name: GBT_ALIGNMENT_LOST
- type: W
- bitfield:
- - range: any
- name: CLEAR
- value: 1
- desc: Any write to this bitfield clears the latched ALIGNMENT_LOST bits
- type: T
- - range: 47..0
- type: R
- name: ALIGNMENT_LOST
- desc: Asserted when GBT_ALIGNMENT_DONE bit is 0, clear by writing to CLEAR
-
-
-
-GT_FEC_ERR_CNT_GEN:
- desc: Counts the number of FEC errors in the (lp)GBT frame
- number: 24
- endpoints: 0
- entries:
- - name: GT_FEC_ERR_CNT
- format_name: GT_FEC_ERR_CNT_{index:02}
- type_name: GT_FEC_ERR_CNT
- desc: Counts the number of FEC errors in the given channel.
- fw_modes: 0,2,3,4,5,6,9,11,12,13,14,15
- type: R
- bitfield:
- - range: 31..0
-
-GT_AUTO_RX_RESET_CNT_GEN:
- desc: Counts the number of AUTO RX RESET events that happend on the FULLMODE, GBT or lpGBT link
- number: 24
- endpoints: 0
- entries:
- - name: GT_AUTO_RX_RESET_CNT
- format_name: GT_AUTO_RX_RESET_CNT_{index:02}
- type_name: GT_AUTO_RX_RESET_CNT
- type: W
- bitfield:
- - range: any
- value: 1
- type: T
- name: CLEAR
- desc: Any write to this register clears the counter value
- - range: 31..0
- name: VALUE
- type: R
-
-TCLINK_MON_GEN:
- desc: TClink status and control registers that dont have a default value
- number: 24
- endpoints: 0
- entries:
- - name: TCLINK_MONITOR_1
- format_name: TCLINK_MONITOR_1_{index:02}
- type_name: TCLINK_MONITOR_1
- type: R
- desc: tclink monitor register
- bitfield:
- - range: 62..15
- name: ERROR_CONTROLLER
- desc: Error-signal for controller Signed complement 2 number.
- - range: 14
- name: LOOP_CLOSED
- desc: TCLink loop is closed (compensation is enabled)
- - range: 13
- name: TX_ALIGNED
- desc: Transmitter alignment procedure finished Use as reset for transmitter user logic
- - range: 12
- name: PS_DONE
- desc: Phase shift is done
- - range: 11..5
- name: TX_PI_PHASE
- desc: Tx PI phase after alignment
- - name: TCLINK_MONITOR_2
- format_name: TCLINK_MONITOR_2_{index:02}
- type_name: TCLINK_MONITOR_2
- desc: Phase detector monitoring bits
- type: R
- bitfield:
- - range: 63..32
- name: PHASE_DETECTOR
- desc: Phase detector response
- - range: 31..0
- name: TX_FIFO_FILL_PD
- desc: Phase detector current value
- - name: TCLINK_MONITOR_3
- format_name: TCLINK_MONITOR_3_{index:02}
- type_name: TCLINK_MONITOR_3
- desc: tclink monitoring bits
- type: W
- bitfield:
- - range: 58..54
- name: LOOP_NOT_CLOSED_REASON
- type: R
- desc: Reason why the TCLink loop is not closed
- - range: 53..38
- name: PHASE_ACC
- type: R
- desc: phase accumulated output (integrated output)
- - range: 37
- name: OPERATION_ERROR
- type: R
- desc: error output indicating that a clk_en_i pulse has arrived before the done_i signal arrived from the previous strobe_o request
- - range: 36..27
- name: DEBUG_TESTER_ADDR_READ
- type: W
- desc: read address for reading stocked TCLink phase accumulated results
- - range: 26..11
- name: DEBUG_TESTER_DATA_READ
- type: R
- desc: data of stocked TCLink phase accumulated results
- - range: 10..7
- name: PS_PHASE_STEP
- type: R
- desc: number of units to shift the phase of the receiver clock
-
-
-TTCBUSYControlsAndMonitors:
- group: TTCBUSY
- desc: TTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
-
- - ref: TTC_DEC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: TTC_BUSY_ACCEPTED_G
-
- - name: TTC_EMU
- type: W
- bitfield:
- - range: 2
- name: FULL
- type: R
- desc: TTC Emulator memory full indication
- - range: 1
- name: SEL
- desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
- - range: 0
- name: ENA
- desc: Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
-
- - name: TTC_DELAY
- type: W
- desc: Controls the TTC Fanout delay value, in 25ns (1BC) units
- bitfield:
- - range: 3..0
- default: 0
-
- - name: TTC_BUSY_TIMING_CTRL
- descr: Controls the BUSY Logic
- offset: 0x4b0
- type: W
- bitfield:
- - range: 51..32
- name: PRESCALE
- default: 0x0000F
- desc: Prescales the 40MHz clock to create an internal slow clock
- - range: 31..16
- name: BUSY_WIDTH
- default: 0x000F
- desc: Minimum number of 40MHz clocks that the busy is asserted
- - range: 15..0
- name: LIMIT_TIME
- default: 0x000F
- desc: Number of prescaled clocks a given busy must be asserted before it is recognized
-
- - name: TTC_BUSY_CLEAR
- desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
- type: T
- value: 1
- bitfield:
- - range: any
-
- - name: TTC_EMU_CONTROL
- type: W
- bitfield:
- - range: 33
- name: BUSY_IN_ENABLE
- desc: Enable internal BUSY input to stop L1A on BUSY
- default: 1
- - range: 32..27
- name: BROADCAST
- desc: Broadcast data
- - range: 26
- name: ECR
- desc: Event counter reset
- - range: 25
- name: BCR
- desc: Bunch counter reset
- - range: 24
- name: L1A
- desc: Level 1 Accept
-
- - name: TTC_EMU_L1A_PERIOD
- type: W
- desc: L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
- bitfield:
- - range: 31..0
-
- - name: TTC_EMU_ECR_PERIOD
- type: W
- desc: ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
- bitfield:
- - range: 31..0
-
- - name: TTC_EMU_BCR_PERIOD
- type: W
- desc: BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
- bitfield:
- - range: 31..0
- default: 3564
-
- - name: TTC_EMU_LONG_CHANNEL_DATA
- type: W
- desc: Long channel data for the TTC emulator
- bitfield:
- - range: 31..0
-
- - name: TTC_EMU_RESET
- desc: Any write to this register resets the TTC Emulator to the default state.
- type: W
- bitfield:
- - range: any
- value: 1
- type: T
-
- - name: TTC_L1ID_MONITOR
- desc: Monitor L1ID and XL1ID.
- type: R
- bitfield:
- - range: 31..0
-
- - name: TTC_ECR_MONITOR
- desc: Counts the number of ECRs received from the TTC system, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_TTYPE_MONITOR
- desc: Counts the number of TType received from the TTC system, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_BCR_PERIODICITY_MONITOR
- desc: Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_BCR_COUNTER
- desc: Counts the number of times BCR is issued, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: TTC_EMU_TP_DELAY
- desc: Number of BC that the testpulse should be sent before the L1A, 0 means no test pulse is sent
- type: W
- bitfield:
- - range: 31..0
- default: 64
-
- - name: TTC_L1A_DELAY
- desc: In Phase1 the L0A bit is generated from L1A, but with a variable delay between 0 and 63 BC cycles from L0A to L1A
- type: W
- bitfield:
- - range: 5..0
- default: 0
-
- - name: TTC_CDRLOCK_MONITOR
- desc: Monitor TTC CDR locked and ADN2814 LOL and LOS signals
- type: W
- bitfield:
- - range: any
- type: T
- name: CLEAR
- value: 1
- desc: Clears the latching cdrlock, LOL and LOS bitfields
- - range: 5
- type: R
- name: CDRLOCK_LOST
- desc: asserted when CDRLOCKED has been 0, Clear by writing to CLEAR bitfield
- - range: 4
- type: R
- name: CDRLOCKED
- desc: Set to 1 if the clock can be successfully recovered from the TTC signal
- - range: 3
- type: R
- name: ADN_LOL_LATCHED
- desc: Latched Loss of lock from ADN2814, Clear by writing to CLEAR bitfield
- - range: 2
- type: R
- name: ADN_LOS_LATCHED
- desc: Latched Loss of signal from ADN2814, Clear by writing to CLEAR bitfield
- - range: 1
- type: R
- name: ADN_LOL
- desc: Loss of lock from ADN2814
- - range: 0
- type: R
- name: ADN_LOS
- desc: Loss of signal from ADN2814
-
-
- - name: TTC_ASYNCUSERDATA
- desc: Write AsyncUserData to the LTI-FE link if legacy TTC or TTC Emulator are selected
- type: W
- bitfield:
- - range: any
- type: T
- name: WR_EN
- value: 1
- desc: Any write to this registers triggers a FIFO write into AsyncUserData
- - range: 63..0
- type: W
- name: DATA
-
-
-TTC_DEC_CTRLMON:
- group: TDCM
- format_name: TTC_DEC_CTRLMON
- entries:
- - name: TTC_DEC_CTRL
- format_name: TTC_DEC_CTRL
- type_name: TTC_DEC_CTRLS
- type: W
- bitfield:
- - range: 30..27
- name: B_CHAN_DELAY
- type: W
- desc: Number of BC to delay the L1A distribution to the frontends
- - range: 26..15
- name: BCID_ONBCR
- type: W
- desc: BCID is set to this value when BCR arrives
- - range: 14
- name: BUSY_OUTPUT_STATUS
- type: R
- desc: Actual status of the BUSY LEMO output signal
- - range: 13
- name: ECR_BCR_SWAP
- default: 0
- desc: ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
- - range: 12
- name: BUSY_OUTPUT_INHIBIT
- default: 0
- desc: forces the Busy LEMO output to BUSY-OFF
- - range: 11
- name: TOHOST_RST
- desc: reset toHost in ttc decoder
- default: 0
- - range: 10
- name: TT_BCH_EN
- desc: trigger type enable / disable for TTC-ToHost
- default: 0
- - range: 9..2
- name: XL1ID_SW
- desc: set XL1ID value, the value to be set by XL1ID_RST signal
- default: 0x00
- - range: 1
- name: XL1ID_RST
- desc: giving a trigger signal to reset XL1ID value
- default: 0
- - range: 0
- name: MASTER_BUSY
- desc: L1A trigger throttling
- default: 0
- - name: TTC_DEC_MON
- format_name: TTC_DEC_MON
- type_name: TTC_DEC_MONS
- type: R
- bitfield:
- - range: 15..5
- name: TH_FF_COUNT
- desc: ToHostData Fifo counts
- - range: 4
- name: TH_FF_FULL
- desc: ToHostData Fifo status 1:full 0:not full
- - range: 3
- name: TH_FF_EMPTY
- desc: ToHostData Fifo status 1:empty 0:not empty
- - range: 2..0
- name: TTC_BIT_ERR
- desc: double bit, single bit and comm error in TTC data
-
-TTC_BUSY_ACCEPTED_G:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- entries:
- - name: TTC_BUSY_ACCEPTED
- format_name: TTC_BUSY_ACCEPTED{index:02}
- type_name: TTC_BUSY_ACCEPTED
- bitfield:
- - range: 56..0
-
-LTITTCBUSYControlsAndMonitors:
- group: LTITTCBUSY
- desc: LTITTC and BUSY Controls and Monitors
- endpoints: 0
- entries:
- - name: LTITTC_ALIGNMENT_DONE
- desc: RX ALIGNMENT DONE
- bitfield:
- - range: 0..0
-
- - name: LTITTC_CPLL_FBCLK_LOST
- desc: CPLL FBCLK LOST
- bitfield:
- - range: 0..0
-
- - name: LTITTC_PLL_LOCK
- bitfield:
- - range: 1..1
- name: QPLL_LOCK
- desc: QPLL LOCK
- - range: 0..0
- name: CPLL_LOCK
- desc: CPLL LOCK
-
- - name: LTITTC_RXCDR_LOCK
- desc: RX CDR LOCK
- bitfield:
- - range: 0..0
-
- - name: LTITTC_RXRESET_DONE
- desc: RX Reset done
- bitfield:
- - range: 0..0
-
- - name: LTITTC_RX_BYTEISALIGNED
- bitfield:
- - range: 0..0
- desc: LTITTC link not aligned
-
- - name: LTITTC_RX_DISP_ERROR
- bitfield:
- - range: 3..0
- desc: Rx disp error in byte 3,2,1,0 of LTITTC link
-
- - name: LTITTC_RX_NOTINTABLE
- bitfield:
- - range: 3..0
- desc: Character in byte 3,2,1,0 of LTITTC link not in 8b10b table
-
- - ref: LTITTC_CTRLMON
- desc: control and monitor bits for TTC decoder
-
- - ref: LTITTC_BUSY_ACCEPTED_G
-
- - name: LTITTC_SL0ID_MONITOR
- desc: Counts Set L0ID input bits
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: LTITTC_SORB_MONITOR
- desc: Counts SetOrbit input bits
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: LTITTC_GRST_MONITOR
- desc: Counts GRST input bits
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: LTITTC_SYNC_MONITOR
- desc: Counts the Sync input bits
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: LTITTC_TTYPE_MONITOR
- desc: Counts the number of TType received from the LTITTC system, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 46..15
- type: R
- name: VALUE
- - range: 15..0
- type: W
- name: REFVALUE
-
- - name: LTITTC_L0ID_ERR_MONITOR
- desc: Counts the number of times the internal l0id /= input L0ID
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: LTITTC_BCR_ERR_MONITOR
- desc: Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
- - name: LTITTC_CRC_ERR_MONITOR
- desc: Counts the number of time the internally computed crc /= input CRC
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- - range: 31..0
- type: R
- name: VALUE
-
-
-
-LTITTC_CTRLMON:
- group: TDCM
- format_name: LTITTC_CTRLMON
- entries:
- - name: LTITTC_CTRL
- format_name: LTITTC_CTRL
- type_name: LTITTC_CTRLS
- type: W
- bitfield:
- - range: 11..9
- name: LTITTC_GTH_LOOPBACK_CONTROL
- desc: GTH_LOOPBACK_CONTROL for LTITTC Link
- default: 0
- - range: 8
- name: LTITTC_SOFT_RESET
- desc: SOFT_RESET
- default: 0
- - range: 7
- name: LTITTC_QPLL_RESET
- desc: QPLL_RESET
- default: 0
- - range: 6
- name: LTITTC_CPLL_RESET
- desc: CPLL_RESET
- default: 0
- - range: 5
- name: LTITTC_SOFT_TX_RESET
- desc: SOFT_TX_RESET_ALL
- default: 0
- - range: 4
- name: LTITTC_SOFT_RX_RESET
- desc: SOFT_RX_RESET_ALL
- default: 0
- - range: 3..2
- name: LTITTC_GENERAL_CTRL
- desc: Alignment chk reset (not self clearing)
- default: 0
- - range: 1
- name: LTITTC_CHANNEL_DISABLE
- desc: clear toHostData
- default: 0
- - range: 0
- name: TOHOST_RST
- desc: clear toHostData
- default: 0
- - name: LTITTC_MON
- format_name: LTITTC_MON
- type_name: LTITTC_MONS
- type: R
- bitfield:
- - range: 3
- name: BUSY_OUTPUT_STATUS
- desc: Actual status of the BUSY LEMO output signal
- - range: 2..0
- name: LTITTC_BIT_ERR
- desc: Alignment comma not received correctly. Place holder
-
-
-LTITTC_BUSY_ACCEPTED_G:
- desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
- number: 24
- endpoints: 0,1
- type: R
- entries:
- - name: LTITTC_BUSY_ACCEPTED
- format_name: LTITTC_BUSY_ACCEPTED{index:02}
- type_name: LTITTC_BUSY_ACCEPTED
- bitfield:
- - range: 56..0
-
-XOFF_BUSYControlsAndMonitors:
- group: XOFF
- desc: XOFF Controls and Monitors, see table 2 of Busy specs manual
- endpoints: 0, 1
- entries:
- - name: XOFF_FM_CH_FIFO_THRESH_LOW
- type: W
- bitfield:
- - range: 3..0
- default: 0xB
- desc: |
- Controls the low threshold of the channel fifo in FULL mode on which
- an Xon will be asserted, bitfields control 4 MSB
- - name: XOFF_FM_CH_FIFO_THRESH_HIGH
- type: W
- bitfield:
- - range: 3..0
- default: 0xB
- desc: |
- Controls the high threshold of the channel fifo in FULL mode on which
- an Xoff will be asserted, bitfields control 4 MSB
- - name: XOFF_FM_LOW_THRESH_CROSSED
- desc: FIFO filled beyond the low threshold, 1 bit per channel
- type: R
- bitfield:
- - range: 23..0
- - name: XOFF_FM_HIGH_THRESH
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- desc: Writing this register will clear all CROSS_LATCHED bits
- type: T
- value: 1
- - range: 47..24
- type: R
- name: CROSS_LATCHED
- desc: FIFO filled beyond the high threshold, 1 latch bit per channel
- - range: 23..0
- type: R
- name: CROSSED
- desc: FIFO filled beyond the high threshold, 1 bit per channel
-
- - name: XOFF_FM_SOFT_XOFF
- type: W
- desc: Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
- bitfield:
- - range: 23..0
-
- - name: XOFF_ENABLE
- type: W
- desc: Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
- bitfield:
- - range: 23..0
-
- - name: DMA_BUSY_STATUS
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR_LATCH
- desc: Any write to this register clears TOHOST_BUSY_LATCHED
- - range: 4
- type: W
- name: ENABLE
- desc: Enable the DMA buffer on the server as a source of busy
- default: 0
- - range: 3
- type: R
- name: TOHOST_BUSY_LATCHED
- desc: A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
- value: (others => tohost_busy_latched_40_s)
- - range: 0
- type: R
- name: TOHOST_BUSY
- desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
- value: (others => tohost_busy_40_s)
-
- - name: FM_BUSY_CHANNEL_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCH
- type: T
- value: 1
- desc: Any write to this register will clear the BUSY_LATCHED bits
- - range: 47..24
- type: R
- name: BUSY_LATCHED
- desc: one Indicates that the given FULL mode channel has received BUSY-ON
- - range: 23..0
- type: R
- name: BUSY
- desc: one Indicates that the given FULL mode channel is currently in BUSY state
-
- - name: BUSY_MAIN_OUTPUT_FIFO_THRESH
- type: W
- bitfield:
- - range: 24
- name: BUSY_ENABLE
- desc: Enable busy generation if thresholds are crossed
- default: 0
- - range: 23..12
- name: LOW
- desc: Low, Negate threshold of busy generation from main output fifo
- default: 0x3FF
- - range: 11..0
- name: HIGH
- desc: High, Assert threshold of busy generation from main output fifo
- default: 0x4FF
-
- - name: BUSY_MAIN_OUTPUT_FIFO_STATUS
- type: W
- bitfield:
- - range: any
- name: CLEAR_LATCHED
- value: 1
- desc: Any write to this register will clear the
- type: T
- - range: 2
- type: R
- name: HIGH_THRESH_CROSSED_LATCHED
- desc: Main output fifo has been full beyond HIGH THRESHOLD, write to clear
- - range: 1
- type: R
- name: HIGH_THRESH_CROSSED
- desc: Main output fifo is full beyond HIGH THRESHOLD
- - range: 0
- type: R
- name: LOW_THRESH_CROSSED
- desc: Main output fifo is full beyond LOW THRESHOLD
- - ref: ELINK_BUSY_ENABLE
- - ref: XOFF_STATISTICS
-
- - name: BUSY_TOHOST_ENABLE
- type: W
- desc: Enable the busy ToHost Virtual Elink
- bitfield:
- - range: 0
- default: 0
-
-
-
-ELINK_BUSY_ENABLE:
- number: 24
- endpoints: 0
- type: W
- entries:
- - name: ELINK_BUSY_ENABLE
- format_name: ELINK_BUSY_ENABLE{index:02}
- type_name: ELINK_BUSY_ENABLE
- desc: Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
- bitfield:
- - range: 56..0
- default: 0
-
-XOFF_STATISTICS:
- number: 24
- endpoints: 0,1
- type: R
- entries:
- - name: XOFF_PEAK_DURATION
- format_name: XOFF_PEAK_DURATION{index:02}
- type_name: XOFF_PEAK_DURATION
- desc: Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
- bitfield:
- - range: 63..0
- - name: XOFF_TOTAL_DURATION
- format_name: XOFF_TOTAL_DURATION{index:02}
- type_name: XOFF_TOTAL_DURATION
- desc: Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
- bitfield:
- - range: 63..0
- - name: XOFF_COUNT
- format_name: XOFF_COUNT{index:02}
- type_name: XOFF_COUNT
- desc: Total number of XOFF events per channel that occurred since a reset.
- bitfield:
- - range: 63..0
-
-
-
-HouseKeepingControlsAndMonitors:
- group: HKC
- desc: House Keeping Controls and Monitors
- endpoints: 0
- entries:
- - name: HK_CTRL_I2C
- type: W
- bitfield:
- - range: 1
- name: CONFIG_TRIG
- desc: i2c_config_trig
- - range: 0
- name: CLKFREQ_SEL
- desc: i2c_clkfreq_sel
- - name: HK_CTRL_FMC
- type: W
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- desc: Write to this bitfield clears the latched SI5345_LOL status, SI5345_LOL_LATCHED
- - range: 14
- name: SI5345_LOL_LATCHED
- type: R
- desc: Latched version of SI5345_LOL, clear by writing to CLEAR bitfield
- - range: 13..12
- name: SI5345_INTR_B
- type: R
- desc: Connects to SI5345_INTR_B pins
- - range: 11..10
- name: SI5345_FINC_B
- type: W
- desc: Connects to FINC_B pins of SI5345
- default: 1
- - range: 9..8
- name: SI5345_FDEC_B
- type: W
- desc: Connects to FDEC_B pins of SI5345
- default: 1
- - range: 7
- name: SI5345_LOL
- type: R
- desc: Loss of lock pin, not connected on VC709
- - range: 6..5
- name: SI5345_INSEL
- default: 0x0
- desc: |
- Selects the input clock source
- 0 : FPGA (FMC LA01)
- 1 : FMC OSC (40.079 MHz)
- 2 : FPGA (FMC LA18)
- - range: 4..3
- name: SI5345_A
- default: 0x0
- desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
- - range: 2
- name: SI5345_OE
- default: 0x1
- desc: Si5345 active low output enable (0:enable)
- - range: 1
- name: SI5345_RSTN
- default: 0x1
- desc: Si5345 active low reset (0:reset)
- - range: 0
- name: SI5345_SEL
- default: 0x1
- desc: |
- Si5345 programming mode
- 1 : I2C mode (default)
- 0 : SPI mode
-
- - name: MMCM_MAIN
- type: W
- offset: 0x0300
- bitfield:
- - range: any
- type: T
- value: 1
- name: CLEAR
- desc: Clears the LOL_LATCHED status
- - range: 4
- name: LOL_LATCHED
- type: R
- desc: Main MMCM has lost lock, clear by writing to the CLEAR bitfield
- - range: 3
- type: W
- name: LCLK_SEL
- default: 0x1
- desc: |
- 1: LCLK
- 0: TTC
- - range: 2..1
- type: R
- name: MAIN_INPUT
- desc: |
- Main MMCM Oscillator Input
- 2: LCLK fixed
- 1: TTC fixed
- 0: selectable
- - range: 0
- type: R
- name: PLL_LOCK
- desc: Main MMCM PLL Lock Status
- - name: LMK_LOCKED
- type: R
- bitfield:
- - range: 0
- desc: LMK Chip on BNL-711 locked
- - name: FPGA_CORE_TEMP
- type: R
- bitfield:
- - range: 11..0
- desc: |
- XADC temperature monitor for the FPGA CORE
- for FLX709, FLX710
- temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
- for FLX711
- temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
- - name: FPGA_CORE_VCCINT
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
- - name: FPGA_CORE_VCCAUX
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
- - name: FPGA_CORE_VCCBRAM
- type: R
- bitfield:
- - range: 11..0
- desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
- - name: FPGA_DNA
- type: R
- bitfield:
- - range: 63..0
- desc: Unique identifier of the FPGA
- - name: I2C_WR
- type: W
- offset: 0x420
- bitfield:
- - range: any
- name: I2C_WREN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
- desc: Any write to this register triggers an I2C read or write sequence
- - range: 34..27
- name: DATA_BYTE3
- type: W
- desc: Data byte 3 used when RW16BIT is set
- - range: 26
- name: RW16BIT
- type: W
- desc: Set to 1 to Write 3 bytes (ADDR + 16 data bits) or read 16 data bits.
- - range: 25
- type: R
- name: I2C_FULL
- desc: I2C FIFO full
- - range: 24
- name: WRITE_2BYTES
- type: W
- desc: Write two bytes
- - range: 23..16
- name: DATA_BYTE2
- type: W
- desc: Data byte 2
- - range: 15..8
- name: DATA_BYTE1
- type: W
- desc: Data byte 1
- - range: 7..1
- name: SLAVE_ADDRESS
- type: W
- desc: Slave address
- - range: 0
- name: READ_NOT_WRITE
- type: W
- desc: READ/<o>WRITE</o>
- - name: I2C_RD
- type: T
- bitfield:
- - range: any
- name: I2C_RDEN
- type: T
- value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
- desc: Any write to this register pops the last I2C data from the FIFO
- - range: 8
- type: R
- name: I2C_EMPTY
- desc: I2C FIFO Empty
- - range: 7..0
- type: R
- name: I2C_DOUT
- desc: I2C READ Data
- - name: INT_TEST
- offset: 0x0800
- type: W
- value: 1
- bitfield:
- - name: TRIGGER
- type: T
- range: any
- desc: Fire a test MSIx interrupt set in IRQ
- - name: IRQ
- type: W
- range: 3..0
- desc: Set this field to a value equal to the MSIX interrupt to be fired. The write triggers the interrupt immediately.
- - name: CONFIG_FLASH_WR
- type: W
- bitfield:
- - range: 57
- type: W
- name: FAST_WRITE
- desc: Write command only. Only used for fast programming.
- - range: 56
- type: W
- name: FAST_READ
- desc: Status reading without command writing. Only used for fast programming.
- - range: 55
- type: W
- name: PAR_CTRL
- desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
- - range: 54..53
- type: W
- name: PAR_WR
- desc: Choose Flash partition. Valid when PAR_CTRL is 1.
- - range: 52
- type: W
- name: FLASH_SEL
- desc: 1 takes control over flash, 0 gives JTAG control over flash
- - range: 51
- type: W
- name: DO_INIT
- desc: Untested feature, don't use it yet.
- - range: 50
- type: W
- name: DO_READSTATUS
- desc: Reads status from flash
- - range: 49
- type: W
- name: DO_CLEARSTATUS
- desc: Clears status reading from flash, back to normal flash operation
- - range: 48
- type: W
- name: DO_ERASEBLOCK
- desc: Erased the current block of the flash, this register has to be cleared by software
- - range: 47
- name: DO_UNLOCK_BLOCK
- type: W
- desc: Unlock writes to the current block, this register has to be cleared by software
- - range: 46
- name: DO_READ
- type: W
- desc: Reads the 16 bits from current address, this register has to be cleared by software
- - range: 45
- name: DO_WRITE
- type: W
- desc: Writes the 16 bits to current address, this register has to be cleared by software
- - range: 44
- name: DO_READDEVICEID
- type: W
- desc: DIN should return 0x0089, this register has to be cleared by software
- - range: 43
- name: DO_RESET
- type: W
- desc: Can be used in the future, currently disconnected in firmware
- - range: 42..16
- name: ADDRESS
- type: W
- desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
- - range: 15..0
- name: WRITE_DATA
- type: W
- desc: Value of data to write towards flash
- - name: CONFIG_FLASH_RD
- type: R
- bitfield:
- - range: 19..18
- name: PAR_RD
- type: R
- desc: Show which Flash partition is selected.
- - range: 17
- name: FLASH_REQ_DONE
- type: R
- desc: Request done
- - range: 16
- name: FLASH_BUSY
- type: R
- desc: Flash operation busy
- - range: 15..0
- name: READ_DATA
- type: R
- desc: Value of data read from flash
- - name: SI5324_STATUS
- type: R
- bitfield:
- - range: 15..8
- name: LOL
- desc: Loss of Lock Si5324
- - range: 8..0
- name: LOS
- desc: Loss of Signal Si5324
- - name: TACH_CNT
- type: R
- desc: Readout of the Fan tachometer speed of the BNL712 board
- bitfield:
- - range: 19..0
- - name: RXUSRCLK_FREQ
- type: W
- bitfield:
- - range: 38
- name: VALID
- type: R
- desc: Indicates that the frequency measurement is valid
- - range: 37..32
- name: CHANNEL
- type: W
- desc: Select the Transceiver channel to measure the clock from.
- - range: 31..0
- name: VAL
- type: R
- desc: Frequency in Hz of the selected channel
-
-
-Generators:
- group: GNR
- desc: Specific registers for Hardware based Generators
- endpoints: 0
- entries:
- - name: FELIG_L1ID_RESET
- fw_modes: 6,11,14,15
- type: W
- desc: Any write to this register clears the FELIG L1ID
- bitfield:
- - range: any
- type: T
- value: 1
- - ref: FELIG_DATA_GEN_CONFIG_ARR
- offset: 0x20
- - ref: FELIG_ELINK_CONFIG_ARR
- - ref: FELIG_ELINK_ENABLE_ARR
-
- - name: FELIG_GLOBAL_CONTROL
- type: W
- fw_modes: 6,11,14,15
- bitfield:
- - range: 63..36
- name: FAKE_L1A_RATE
- default: 0
- desc: Sets the internal fake L1 trigger rate. [25ns/LSB]
- - range: 35..14
- name: PICXO_OFFSET_PPM
- default: 0
- desc: When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
- - range: 12..12
- name: TRACK_DATA
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 11..11
- name: RXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 10..10
- name: TXUSERRDY
- default: 0
- desc: FELIG GT core control. Must be set to enable normal operation.
- - range: 9..9
- name: AUTO_RESET
- default: 0
- desc: FELIG GT core control. If set the GT core automatically resets on data error.
- - range: 8..8
- name: PICXO_RESET
- default: 0
- desc: FELIG GT core control. Manual PICXO reset.
- - range: 7..7
- name: GTTX_RESET
- default: 0
- desc: FELIG GT core control. Manual GT TX reset
- - range: 6..6
- name: CPLL_RESET
- default: 0
- desc: FELIG GT core control. Manual CPLL reset.
- - range: 5..0
- name: X3_X4_OUTPUT_SELECT
- default: 0
- desc: X3/X4 SMA output source select.
- - ref: FELIG_LANE_CONFIG_ARR
- - ref: FELIG_MON_TTC_0_ARR
- - ref: FELIG_MON_TTC_1_ARR
- - ref: FELIG_MON_COUNTERS_ARR
- - ref: FELIG_MON_FREQ_ARR
- - name: FELIG_MON_FREQ_GLOBAL
- fw_modes: 6,11,14,15
- type: W
- bitfield:
- - range: 63..32
- name: XTAL_100MHZ
- default: 0
- desc: FELIG local oscillator frequency[Hz].
- - range: 31..0
- name: CLK_41_667MHZ
- desc: FELIG PCIE MGTREFCLK frequency[Hz].
- - ref: FELIG_MON_L1A_ID_ARR
- - ref: FELIG_MON_PICXO_ARR
- - name: FELIG_RESET
- fw_modes: 6,11,14,15
- type: W
- bitfield:
- - range: 63..48
- name: LB_FIFO
- default: 0
- desc: One bit per lane. When set to 1, resets all loopback FIFOs.
- - range: 47..24
- name: FRAMEGEN
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG link checking logic.
- - range: 23..0
- name: LANE
- default: 0
- desc: One bit per lane. When set to 1, resets all FELIG lane logic.
-
- - name: FELIG_RX_SLIDE_RESET
- fw_modes: 6,11,14,15
- type: W
- bitfield:
- - range: 23..0
- default: 0
- desc: One bit per lane. When set to 1, resets the gbt rx slide counter.
-
- - ref: FELIG_ITK_STRIPS_DATA_GEN_CONFIG_ARR
- - ref: FELIG_MON_ITK_STRIPS_ARR
- - ref: FELIG_DATA_GEN_CONFIG_USERDATA_ARR
-
- - name: FMEMU_EVENT_INFO
- fw_modes: 7
- type: R
- offset: 0x1800
- bitfield:
- - range: 63..32
- name: L1ID
- default: 0
- desc: 32b field to show L1ID
- - range: 31..0
- name: BCID
- default: 0
- desc: 32b field to show BCID
-
- - name: FMEMU_COUNTERS
- fw_modes: 7
- type: W
- bitfield:
- - range: 63..48
- name: WORD_CNT
- default: 32
- desc: Number of 32b words in one chunk
- - range: 47..32
- name: IDLE_CNT
- default: 3
- desc: Minimum number of idles between chunks
- - range: 31..16
- name: L1A_CNT
- default: 256
- desc: Number of chunks to send if not in TTC mode
- - range: 15..8
- name: BUSY_TH_HIGH
- default: 20
- desc: Assert BUSY-ON above this threshold
- - range: 7..0
- name: BUSY_TH_LOW
- default: 15
- desc: De-assert BUSY-ON below this threshold
-
- - name: FMEMU_CONTROL
- fw_modes: 7
- type: W
- bitfield:
- - range: 63..56
- type: W
- name: L1A_BITNR
- default: 48
- desc: Bitfield for L1A in TTC frame
- - range: 55..48
- type: W
- name: XONXOFF_BITNR
- default: 32
- desc: Bitfield for Xon/Xoff in TTC frame
- - range: 47..47
- type: W
- name: EMU_START
- default: 0
- desc: Start emulator functionality
- - range: 46..46
- type: W
- name: TTC_MODE
- default: 0
- desc: Control the emulator by TTC input or by RegMap (1/0)
- - range: 45..45
- type: W
- name: XONXOFF
- default: 1
- desc: Enable Xon/Xoff functionality (1/0)
- - range: 44..44
- type: W
- name: INLC_CRC32
- default: 0
- desc: |
- 0: No checksum
- 1: Append the data with a CRC32
- - range: 43..43
- type: W
- name: BCR
- default: 0
- desc: Reset BCID to 0
- - range: 42..42
- type: W
- name: ECR
- default: 0
- desc: Reset L1ID to 0
- - range: 41..41
- type: W
- name: CONSTANT_CHUNK_LENGTH
- default: 0
- desc: |
- Data source select
- 0: Random chunk length
- 1: Constant chunk length
- - range: 40..32
- type: R
- name: INT_STATUS_EMU
- default: 0
- desc: Read internal status emulator
- - range: 16
- type: W
- name: FFU_FM_EMU_T
- default: 0
- desc: For Future Use (trigger registers)
- - range: 0
- type: W
- name: FE_BUSY_ENABLE
- default: 1
- desc: Enable the BUSY mechanism if L1A counter passes threshold
-
- - name: FMEMU_RANDOM_RAM_ADDR
- fw_modes: 7
- type: W
- desc: Controls the address of the ramblock for the random number generator
- bitfield:
- - range: 9..0
- - name: FMEMU_RANDOM_RAM
- fw_modes: 7
- type: W
- bitfield:
- - range: any
- type: T
- name: WE
- value: 1
- desc: Any write to this register (DATA) triggers a write to the ramblock
- - range: 39..16
- name: CHANNEL_SELECT
- value: 0xFFFFFF
- desc: Enable write enable only for the selected channel
- - range: 15..0
- name: DATA
- type: W
- desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
- - name: FMEMU_RANDOM_CONTROL
- fw_modes: 7
- type: W
- desc: Controls the random chunk length generator
- bitfield:
- - name: SELECT_RANDOM
- range: 20
- desc: 1 enables the random chunk length, 0 uses a constant chunk length
- default: 0
- - name: SEED
- range: 19..10
- desc: Seed for the random number generator, should not be 0
- default: 0x200
- - name: POLYNOMIAL
- range: 9..0
- desc: POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
- default: 0x240
-
- - name: FMEMU_CONFIG_WRADDR
- fw_modes: 7
- type: W
- bitfield:
- - range: 9..0
- value: 0
- desc: write enable for the FMEmu ram block
-
- - name: FMEMU_CONFIG
- fw_modes: 7
- type: W
- bitfield:
- - range: any
- type: T
- name: WE
- value: 1
- desc: Any write to register WRDATA triggers a write to the ramblock
- - range: 55..32
- name: CHANNEL_SELECT
- value: 0xFFFFFF
- desc: Enable write enable only for the selected channel
- - range: 31..0
- name: WRDATA
- type: W
- desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
-
-
-#Registers that are replicated 24 times under Generators:
-FELIG_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- fw_modes: 6,11,14,15
- entries:
- - name: FELIG_DATA_GEN_CONFIG
- format_name: FELIG_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_DATA_GEN_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: CHUNK_LENGTH
- range: 50..35
- default: 0
- desc: FELIG data generator chunk-length in bytes.
- - name: RESET
- range: 34..28
- default: 0
- desc: FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
- - name: SW_BUSY
- range: 27..21
- default: 0
- desc: FELIG elink busy state. One bit per group, 0:normal operation, 1:elink enter busy state.
- - name: DATA_FORMAT
- range: 20..7
- default: 0
- desc: FELIG data generator format, 2 bits per e-group. 00 8b10b, 01 direct, 10 Aurora
- - name: PATTERN_SEL
- range: 6..0
- default: 0
- desc: FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
-
-
-FELIG_ELINK_CONFIG_ARR:
- number: 24
- type: W
- fw_modes: 6,11,14,15
- entries:
- - name: FELIG_ELINK_CONFIG
- format_name: FELIG_ELINK_CONFIG_{index:02}
- type_name: FELIG_ELINK_CONFIG
- desc: FELIG specific configuration test registers
- bitfield:
- - name: ENDIAN_MOD
- range: 34..28
- default: 0
- desc: FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
- - name: INPUT_WIDTH
- range: 27..21
- default: 0
- desc: FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
- - name: OUTPUT_WIDTH
- range: 20..0
- default: 0
- desc: FELIG elink data output width. 3 bits per egroup. 0:2b, 1:4b, 2:8b, 3:16b, 4:32b
-
-FELIG_ELINK_ENABLE_ARR:
- number: 24
- type: W
- fw_modes: 6,11,14,15
- entries:
- - name: FELIG_ELINK_ENABLE
- format_name: FELIG_ELINK_ENABLE_{index:02}
- type_name: FELIG_ELINK_ENABLE
- desc: FELIG specific configuration registers
- bitfield:
- - range: 39..0
- default: 0
- desc: FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
-
-FELIG_LANE_CONFIG_ARR:
- number: 24
- type: W
- fw_modes: 6,11,14,15
- entries:
- - name: FELIG_LANE_CONFIG
- format_name: FELIG_LANE_CONFIG_{index:02}
- type_name: FELIG_LANE_CONFIG
- desc: FELIG specific configuration registers
- bitfield:
- - name: B_CH_BIT_SEL
- range: 63..42
- default: 0
- desc: When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
- - name: A_CH_BIT_SEL
- range: 41..35
- default: 0
- desc: Selects the bit from the received FELIX data from which to extract the L1A.
- - name: LB_FIFO_DELAY
- range: 34..30
- default: 0
- desc: When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
- - name: ELINK_SYNC
- range: 7..7
- default: 0
- desc: When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
- - name: PICXO_OFFEST_EN
- range: 6..6
- default: 0
- desc: FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
- - name: PI_HOLD
- range: 5..5
- default: 0
- desc: FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
- - name: GBT_LB_ENABLE
- range: 4..4
- default: 0
- desc: FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
- - name: GBH_LB_ENABLE
- range: 3..3
- default: 0
- desc: FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
- - name: L1A_SOURCE
- range: 2..2
- default: 0
- desc: FELIG L1A data source select. 0:from local counter, 1:from FELIX.
- - name: GBT_EMU_SOURCE
- range: 1..1
- default: 0
- desc: FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
- - name: FG_SOURCE
- range: 0..0
- default: 0
- desc: FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
-
-FELIG_MON_TTC_0_ARR:
- number: 24
- type: R
- fw_modes: 6,11,14,15
- entries:
- - name: FELIG_MON_TTC_0
- format_name: FELIG_MON_TTC_0_{index:02}
- type_name: FELIG_MON_TTC_0
- desc: FELIG specific configuration registers
- bitfield:
- - name: L1ID
- range: 63..40
- default: 0
- desc: Live TTC data monitor.
- - name: XL1ID
- range: 39..32
- default: 0
- desc: Live TTC data monitor.
- - name: BCID
- range: 31..20
- default: 0
- desc: Live TTC data monitor.
- - name: RESERVED0
- range: 19..16
- default: 0
- desc: Live TTC data monitor.
- - name: LEN
- range: 15..8
- default: 0
- desc: Live TTC data monitor.
- - name: FMT
- range: 7..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_TTC_1_ARR:
- number: 24
- type: R
- fw_modes: 6,11,14,15
- entries:
- - name: FELIG_MON_TTC_1
- format_name: FELIG_MON_TTC_1_{index:02}
- type_name: FELIG_MON_TTC_1
- desc: FELIG specific configuration registers
- bitfield:
- - name: RESERVED1
- range: 63..48
- default: 0
- desc: Live TTC data monitor.
- - name: TRIGGER_TYPE
- range: 47..32
- default: 0
- desc: Live TTC data monitor.
- - name: ORBIT
- range: 31..0
- default: 0
- desc: Live TTC data monitor.
-
-FELIG_MON_COUNTERS_ARR:
- number: 24
- type: R
- fw_modes: 6,11,14,15
- entries:
- - name: FELIG_MON_COUNTERS
- format_name: FELIG_MON_COUNTERS_{index:02}
- type_name: FELIG_MON_COUNTERS
- desc: FELIG specific configuration registers
- bitfield:
- - name: SLIDE_COUNT
- range: 63..32
- default: 0
- desc: Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
- - name: FC_ERROR_COUNT
- range: 31..0
- default:
- desc: When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
-
-FELIG_MON_FREQ_ARR:
- number: 24
- type: R
- fw_modes: 6,11,14,15
- entries:
- - name: FELIG_MON_FREQ
- format_name: FELIG_MON_FREQ_{index:02}
- type_name: FELIG_MON_FREQ
- desc: FELIG specific configuration registers
- bitfield:
- - name: TX
- range: 63..32
- default: 0
- desc: FELIG regenerated TX clock frequency[Hz].
- - name: RX
- range: 31..0
- default: 0
- desc: FELIG recovered RX clock frequency[Hz].
-
-FELIG_MON_L1A_ID_ARR:
- number: 24
- type: R
- fw_modes: 6,11,14,15
- entries:
- - name: FELIG_MON_L1A_ID
- format_name: FELIG_MON_L1A_ID_{index:02}
- type_name: FELIG_MON_L1A_ID
- desc: FELIG specific configuration registers
- bitfield:
- - range: 31..0
- default: 0
- desc: FELIG's last L1 ID.
-
-FELIG_MON_PICXO_ARR:
- number: 24
- type: R
- fw_modes: 6,11,14,15
- entries:
- - name: FELIG_MON_PICXO
- format_name: FELIG_MON_PICXO_{index:02}
- type_name: FELIG_MON_PICXO
- desc: FELIG specific configuration registers
- bitfield:
- - name: VLOT
- range: 53..32
- default: 0
- desc: Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
- - name: ERROR
- range: 20..0
- default: 0
- desc: Value indicates RX to TX frequency tracking error.
-
-FELIG_ITK_STRIPS_DATA_GEN_CONFIG_ARR:
- number: 24
- type: W
- fw_modes: 6,11,14,15
- entries:
- - name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG
- format_name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG_{index:02}
- type_name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG
- desc: ITk Strips emulator specific configuration test registers
- bitfield:
- - name: ITKS_FIFO_CTL
- range: 19..17
- default: 0
- desc: data fifo control 2:rst 1:rd 0:wr.
- - name: ITKS_FIFO_DATA
- range: 16..0
- default: 0
- desc: itks emu data 16:last word 15-0:data word
-
-FELIG_MON_ITK_STRIPS_ARR:
- number: 24
- type: R
- fw_modes: 6,11,14,15
- entries:
- - name: FELIG_MON_ITK_STRIPS
- format_name: FELIG_MON_ITK_STRIPS_{index:02}
- type_name: FELIG_MON_ITK_STRIPS
- desc: ITk Strips emulator specific status registers
- bitfield:
- - name: ITKS_FIFO_STATUS
- range: 2..0
- default: 0
- desc: data fifo status 2:write done 1:full 0:empty.
-
-#Registers that are replicated 24 times under Generators:
-FELIG_DATA_GEN_CONFIG_USERDATA_ARR:
- number: 24
- type: W
- fw_modes: 6
- entries:
- - name: FELIG_DATA_GEN_CONFIG_USERDATA
- format_name: FELIG_DATA_GEN_CONFIG_{index:02}_USERDATA
- type_name: FELIG_DATA_GEN_CONFIG_USERDATA
- desc: Sets static payload word. When FELIG_DATA_GEN_CONFIG.PATTERN_SEL=1.
- bitfield:
- - range: 15..0
- default: 0
-
-Wishbone:
- desc: Wishbone
- endpoints: 0
- fw_modes: 1
- entries:
- - name: WISHBONE_CONTROL
- type: W
- bitfield:
- - range: 32
- name: WRITE_NOT_READ
- desc: wishbone write command wishbone read command
- - range: 31..0
- name: ADDRESS
- desc: Slave address for Wishbone bus
- - name: WISHBONE_WRITE
- type: T
- bitfield:
- - range: any
- type: T
- value: 1
- name: WRITE_ENABLE
- desc: Any write to this register triggers a write to the Wupper to Wishbone fifo
- - range: 32
- name: FULL
- type: R
- - range: 31..0
- name: DATA
- type: W
- - name: WISHBONE_READ
- type: T
- bitfield:
- - range: any
- type: T
- value: 1
- name: READ_ENABLE
- desc: Any write to this register triggers a read from the Wishbone to Wupper fifo
- - range: 32
- name: EMPTY
- type: R
- desc: Indicates that the Wishbone to Wupper fifo is empty
- - range: 31..0
- name: DATA
- type: R
- desc: Wishbone read data
- - name: WISHBONE_STATUS
- type: R
- bitfield:
- - range: 4
- name: INT
- desc: interrupt
- - range: 3
- name: RETRY
- desc: Interface is not ready to accept data cycle should be retried
- - range: 2
- name: STALL
- desc: When pipelined mode slave can't accept additional transactions in its queue
- - range: 1
- name: ACKNOWLEDGE
- desc: Indicates the termination of a normal bus cycle
- - range: 0
- name: ERROR
- desc: Address not mapped by the crossbar
-
-# ----------------------- ITk strips link configuration start -----------------------
-
-ITK_STRIPS_CTRL:
- entries:
- - name: GLOBAL_STRIPS_CONFIG
- desc: Configuration affecting all Strips links on this FELIX device
- type: W
- fw_modes: 5
- bitfield:
- - range: 63..59
- type: W
- name: TEST_MODULE_MASK
- desc: (for tests only) contains R3 mask for the simulated trigger data
- default: 0x0
- - range: 58..52
- type: W
- name: TEST_R3L1_TAG
- desc: (for tests only) contains R3 or L1 tag for the simulated trigger data
- default: 0x0
- - range: 51
- type: W
- name: TTC_GENERATE_GATING_ENABLE
- desc: Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR.
- TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
- (See also BC_START, and BC_STOP fields)
- default: 0x0
- - range: 50
- type: W
- name: TTC_GATING_OVERRIDE
- desc: Overrides and disables gating signal generation when set to '1'
- (use if the elink is deadlocked and commands don't reach it).
- default: 0x0
- - range: 4
- type: W
- name: INVERT_AMAC_IN
- desc: Invert the polarity of all FELIX AMAC_IN elinks
- default: 0x0
- - range: 3
- type: W
- name: INVERT_AMAC_OUT
- desc: Invert the polarity of all FELIX AMAC_OUT elinks
- default: 0x0
- - range: 2
- type: W
- name: INVERT_DIN
- desc: Invert the polarity of all FELIX 8-bit IN 8b10b elinks
- default: 0x0
- - range: 1
- type: W
- name: INVERT_R3L1_OUT
- desc: Invert the polarity of all FELIX R3L1 elinks
- default: 0x0
- - range: 0
- type: W
- name: INVERT_LCB_OUT
- desc: Invert the polarity of all FELIX LCB elinks
- default: 0x0
-
- - name: GLOBAL_TRICKLE_TRIGGER
- fw_modes: 5
- type: T
- bitfield:
- - range: any
- value: 1
- desc: writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
-
- - name: STRIPS_R3_TRIGGER
- fw_modes: 5
- type: T
- bitfield:
- - range: any
- value: 1
- desc: (for tests only) simulate R3 trigger (issues 4-5 sequential triggers)
- - name: STRIPS_L1_TRIGGER
- fw_modes: 5
- type: T
- bitfield:
- - range: any
- desc: (for tests only) simulate L1 trigger (issues 4-5 sequential triggers)
- value: 1
- - name: STRIPS_R3L1_TRIGGER
- fw_modes: 5
- type: T
- bitfield:
- - range: any
- desc: (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)
- value: 1
-
-# ----------------------- ITk strips link configuration end -----------------------
-
-
-MRODregisters:
- group: MROD_CONTROL
- fw_modes: 8
- desc: Specific registers for MROD
- endpoints: 0
- entries:
- - name: MROD_CTRL
- type: W
- bitfield:
- - range: 15..8
- name: OPTIONS
- default: 0
- desc: Extra options for MROD
- - range: 7..7
- name: ENASPARE1
- default: 0
- desc: Enable spare1
- - range: 6..6
- name: ENAMANSLIDE
- default: 0
- desc: Enable Manual Slide in Rx Locking
- - range: 5..5
- name: ENAPASSALL
- default: 0
- desc: Enable PassAll in EmptySuppress
- - range: 4..4
- name: ENATXCOUNT
- default: 0
- desc: Enable SimpleCount in TxDriver for locking
- - range: 3..0
- name: GOLTESTMODE
- default: 0
- desc: |
- GOL Test Mode (emulate CSM):
- 0: Run Data Emulator when 1; 0: stop, load emulator fifo
- 1: Enable Circulate when 1; 0: send fifo data only once
- 2: Enable Triggered Mode when 1; 0: run continueously (no TTC)
- 3: Enable pattern generator
- - name: MROD_TCVRCTRL
- type: W
- bitfield:
- - range: 23..16
- name: SLIDEMAX
- default: 0xFF
- desc: Maximum RXSLIDES before fire a TCVR reset
- - range: 15..8
- name: SLIDEWAIT
- default: 32
- desc: RXclk delay in TCVR for next RX_SLIDE operation
- - range: 7..0
- name: FRAMESIZE
- default: 20
- desc: Number of 32 data words in 1 frame
- - name: MROD_EP0_CSMENABLE
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 CSM Data Enable channel 23-0
- default: 0
- - name: MROD_EP0_EMPTYSUPPR
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Set Empty Suppression channel 23-0
- default: 0
- - name: MROD_EP0_HPTDCMODE
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Set HPTDC Mode channel 23-0
- default: 0
- - name: MROD_EP0_CLRFIFOS
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Clear FIFOs channel 23-0
- default: 0
- - name: MROD_EP0_EMULOADENA
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Emulator Load Enable channel 23-0
- default: 0
- - name: MROD_EP0_TRXLOOPBACK
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Transceiver Loopback Enable channel 23-0
- default: 0
- - name: MROD_EP0_TXCVRRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Transceiver Reset all channel 23-0
- default: 0
- - name: MROD_EP0_RXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Reset channel 23-0
- default: 0
- - name: MROD_EP0_TXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP0 Transmitter Reset channel 23-0
- default: 0
- - name: MROD_EP1_CSMENABLE
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 CSM Data Enable channel 23-0
- default: 0
- - name: MROD_EP1_EMPTYSUPPR
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Set Empty Suppression channel 23-0
- default: 0
- - name: MROD_EP1_HPTDCMODE
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Set HPTDC Mode channel 23-0
- default: 0
- - name: MROD_EP1_CLRFIFOS
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Clear FIFOs channel 23-0
- default: 0
- - name: MROD_EP1_EMULOADENA
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Emulator Load Enable channel 23-0
- default: 0
- - name: MROD_EP1_TRXLOOPBACK
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Transceiver Loopback Enable channel 23-0
- default: 0
- - name: MROD_EP1_TXCVRRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Transceiver Reset all channel 23-0
- default: 0
- - name: MROD_EP1_RXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Reset channel 23-0
- default: 0
- - name: MROD_EP1_TXRESET
- type: W
- bitfield:
- - range: 23..0
- desc: EP1 Transmitter Reset channel 23-0
- default: 0
-
-MRODmonitors:
- group: MROD_MONITOR
- desc: Specific registers for MROD
- endpoints: 0
- fw_modes: 8
- entries:
- - name: MROD_EP0_CSMH_EMPTY
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 CSM Handler FIFO Empty 23-0
- - name: MROD_EP0_CSMH_FULL
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 CSM Handler FIFO Full 23-0
- - name: MROD_EP0_RXALIGNBSY
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Aligned monitor 23-0
- - name: MROD_EP0_RXRECDATA
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Data monitor 23-0
- - name: MROD_EP0_RXRECIDLES
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Receiver Idle monitor 23-0
- - name: MROD_EP0_TXLOCKED
- type: R
- bitfield:
- - range: 23..0
- desc: EP0 Transmitter Locked monitor 23-0
- - name: MROD_EP1_CSMH_EMPTY
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 CSM Handler FIFO Empty 23-0
- - name: MROD_EP1_CSMH_FULL
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 CSM Handler FIFO Full 23-0
- - name: MROD_EP1_RXALIGNBSY
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Aligned monitor 23-0
- - name: MROD_EP1_RXRECDATA
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Data monitor 23-0
- - name: MROD_EP1_RXRECIDLES
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Receiver Idle monitor 23-0
- - name: MROD_EP1_TXLOCKED
- type: R
- bitfield:
- - range: 23..0
- desc: EP1 Transmitter Locked monitor 23-0
-
-IPBus:
- desc: IPbus bridge registers
- endpoints: 0
- fw_modes: 1
- entries:
- - name: IPBUS_WRITE_ADDRESS
- type: W
- desc: Address of the IPBus Write RAM
- bitfield:
- - range: 31..0
- - name: IPBUS_WRITE_DATA
- type: T
- desc: IPbus data to write to RAM
- bitfield:
- - range: any
- type: T
- value: 1
- name: WRITE_ENABLE
- desc: Any write to this register triggers a write to the Wupper to IPBus inout RAM
- - range: 63..0
- name: DATA
- type: W
- - name: IPBUS_READ_ADDRESS
- type: W
- desc: Address of the IPBus Read RAM
- bitfield:
- - range: 31..0
- - name: IPBUS_READ_DATA
- type: R
- desc: IPbus data from Read RAM
- bitfield:
- - range: 63..0
- - name: IPBUS_PKT_DONE
- type: R
- desc: IPbus packet ready to read
- bitfield:
- - range: 0
-
diff --git a/sources/templates/yaml/regmap b/sources/templates/yaml/regmap
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--- /dev/null
+++ b/sources/templates/yaml/regmap
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+Subproject commit a8c53d194c4d29df1b5155596e9960a537fc9548