From 2e7697d0316ebe9d0c03897d4b3040a2703ba690 Mon Sep 17 00:00:00 2001
From: Frans Schreuder <f.schreuder@nikhef.nl>
Date: Fri, 26 Nov 2021 11:19:34 +0100
Subject: [PATCH] Applied license headers
---
.../CRFromHostAxis/CRFromHostAxis_tb.vhd | 18 +
.../CRFromHostAxis/SimpleFromHostFifo.vhd | 18 +
simulation/Endeavour/amac_chip.vhd | 19 +
simulation/Endeavour/amac_demo_tb.vhd | 19 +
simulation/Endeavour/tb_amac_decoder.vhd | 17 +
simulation/Endeavour/tb_amac_deglitcher.vhd | 17 +
simulation/Endeavour/tb_amac_encoder.vhd | 17 +
.../FELIX_Top/Decoding_pixel_tb_noUVVM.vhd | 17 +
.../FELIX_Top/Encoding_pixel_tb_noUVVM.vhd | 17 +
simulation/FELIX_Top/package_pixel.vhd | 17 +
.../FELIX_fullmode_top/felix_fullmode_tb.vhd | 17 +
.../FELIX_fullmode_top/pcie_ep_wrap_sim.vhd | 17 +
simulation/ItkStrip/tb_clk40_detect.vhd | 17 +
simulation/ItkStrip/tb_r3l1_regmap.vhd | 17 +
.../tb_strips_configuration_decoder.vhd | 18 +
simulation/UVVMtests/DecodingEpath_tb.vhd | 17 +
.../UVVMtests/tb/BusyVirtualElink_tb.vhd | 17 +
.../UVVMtests/tb/ByteToAxiStream_tb.vhd | 17 +
simulation/UVVMtests/tb/CRToHost_tb.vhd | 17 +
.../UVVMtests/tb/DecEgroup_8b10b_framegen.vhd | 17 +
.../UVVMtests/tb/DecEgroup_8b10b_tb.vhd | 17 +
.../UVVMtests/tb/DecodingGearBox_tb.vhd | 17 +
simulation/UVVMtests/tb/Decoding_pixel_tb.vhd | 18 +
simulation/UVVMtests/tb/EncodingEpath_tb.vhd | 19 +
simulation/UVVMtests/tb/FELIXDataSink.vhd | 18 +
simulation/UVVMtests/tb/FELIXDataSource.vhd | 18 +
simulation/UVVMtests/tb/FULLModeToHost_tb.vhd | 18 +
simulation/UVVMtests/tb/GBTCrCoding_tb.vhd | 20 +
simulation/UVVMtests/tb/GBTLinkToHost_tb.vhd | 18 +
.../UVVMtests/tb/TTCToHostVirtualElink_tb.vhd | 17 +
simulation/UVVMtests/tb/XcodingEpath_tb.vhd | 19 +
sources/64b66b/64b66b_DecodingGearBox.vhd | 18 +
sources/64b66b/64b66b_clockmanagement.vhd | 17 +
sources/64b66b/64b66b_decoding.vhd | 18 +
sources/64b66b/64b66b_top.vhd | 18 +
sources/64b66b/Aggregator_64b66b.vhd | 17 +
sources/64b66b/CntRcvdPckts_64b66b.vhd | 17 +
sources/64b66b/RemapEpaths.vhd | 17 +
sources/64b66b/gearbox32to64_64b66b.vhd | 17 +
sources/64b66b/split64bword.vhd | 17 +
sources/AxisUtils/Axis64Fifo.vhd | 17 +
sources/AxisUtils/Axis8Fifo.vhd | 19 +
sources/CRFromHost/CRFromHost.vhd | 22 +
sources/CRFromHostAxis/CRFromHostAxis.vhd | 18 +
.../CRFromHostDataManagerAxis.vhd | 18 +
.../CRFromHostAxis/CRFromHostGroupFifo.vhd | 18 +
sources/CRFromHostAxis/CRFromHostLinkFifo.vhd | 18 +
.../CRFromHostTransferManager.vhd | 18 +
sources/CRToHost/CRToHost.vhd | 23 +
sources/CRToHost/CRToHostdm.vhd | 21 +
sources/CRToHost/MUXn.vhd | 18 +
.../CRToHost/ToHostAxiStream64Controller.vhd | 17 +
sources/Endeavour/EndeavourDecoder.vhd | 21 +
sources/Endeavour/EndeavourDeglitcher.vhd | 19 +
sources/Endeavour/EndeavourEncoder.vhd | 20 +
sources/Endeavour/EndeavourPackage.vhd | 17 +
.../axis_32_fanout_selector.vhd | 17 +
.../FanoutSelectors/gbt_fanout_selector.vhd | 19 +
.../gth_fullmode_wrapper_48g_ku.vhd | 20 +
.../gth_fullmode_wrapper_48g_v7.vhd | 19 +
.../gth_fullmode_wrapper_48g_vup.vhd | 20 +
.../gth_fullmode_wrapper_vup.vhd | 19 +
.../GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd | 23 +
sources/ItkStrip/r3l1_regmap.vhd | 17 +
sources/ItkStrip/r3l1_regmap_package.vhd | 17 +
.../ItkStrip/strips_configuration_decoder.vhd | 17 +
sources/LinkWrapper/link_wrapper.vhd | 19 +
sources/LpGBT/LpGBT_FELIX/BIT_ERROR_CALC.vhd | 18 +
.../LpGBT/LpGBT_FELIX/FELIX_LpGBT_Wrapper.vhd | 20 +
sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE.vhd | 20 +
.../LpGBT_FELIX/FLX_LpGBT_BE_Wrapper.vhd | 21 +
sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE.vhd | 18 +
.../LpGBT_FELIX/FLX_LpGBT_FE_Wrapper.vhd | 19 +
.../LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_BE.vhd | 20 +
.../LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_FE.vhd | 19 +
sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_PRBS.vhd | 19 +
.../LpGBT/LpGBT_FELIX/PRBS31_32BIT_Chk.vhd | 19 +
.../LpGBT/LpGBT_FELIX/PRBS31_32BIT_Gen.vhd | 18 +
sources/LpGBT/LpGBT_FELIX/RefClk_Gen.vhd | 20 +
sources/LpGBT/LpGBT_FELIX/Regs_RW.vhd | 19 +
.../LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd | 18 +
sources/RD53A/ENCRD53A.vhd | 18 +
sources/RD53A/RD53A_CntIssuedCommand.vhd | 17 +
sources/RD53A/RD53A_CntIssuedCommand8b.vhd | 17 +
sources/RD53A/RD53A_CntIssuedGivenCommand.vhd | 17 +
sources/RD53A/RD53A_CntIssuedTrigger.vhd | 17 +
sources/RD53A/RD53A_DebuggingModule.vhd | 17 +
.../RD53A/RD53A_MsrGenCalToTrigLatency.vhd | 17 +
sources/RD53A/RD53A_MsrTrigFreq.vhd | 17 +
sources/RD53A/az_controller.vhd | 18 +
sources/RD53A/cmd_top.vhd | 18 +
sources/RD53A/newtriggerunit.vhd | 17 +
sources/RD53A/rd53a_package.vhd | 18 +
sources/RD53A/sync_timer.vhd | 18 +
sources/centralRouter/EPROC_OUT8_FEI4.vhd | 17 +
.../RD53A_DL_Eproc/EPROC_OUT4_RD53A.vhd | 17 +
.../RD53A_DL_Eproc/RD53A_DL_EProc.vhd | 17 +
.../RD53A_DL_Eproc/fifoController.vhd | 17 +
.../centralRouter/RD53A_DL_Eproc/merger.vhd | 17 +
.../RD53A_DL_Eproc/pkg_RD53A.vhd | 17 +
.../RD53A_DL_Eproc/serializer.vhd | 17 +
.../RD53A_DL_Eproc/syncEncoder.vhd | 17 +
.../RD53A_DL_Eproc/trigEncoder.vhd | 17 +
.../RD53A_DL_Eproc/ttcEncoder.vhd | 17 +
sources/decoding/AlignmentPulseGen.vhd | 17 +
sources/decoding/ByteToAxiStream.vhd | 19 +
sources/decoding/ByteToAxiStream32b.vhd | 17 +
sources/decoding/DecEgroup_8b10b.vhd | 18 +
sources/decoding/Decoder8b10b.vhd | 20 +
sources/decoding/DecoderHDLC.vhd | 18 +
sources/decoding/DecodingEgroupGBT.vhd | 18 +
sources/decoding/DecodingEpathGBT.vhd | 18 +
sources/decoding/DecodingGearBox.vhd | 17 +
sources/decoding/DecodingPixelLinkLPGBT.vhd | 18 +
sources/decoding/dec_8b10b.vhd | 17 +
sources/decoding/decoding.vhd | 21 +
sources/encoding/AxiStreamToByte.vhd | 18 +
sources/encoding/Encoder8b10b.vhd | 21 +
sources/encoding/Encoder8b10b_tb.vhd | 17 +
sources/encoding/EncoderFEI4.vhd | 19 +
sources/encoding/EncoderHDLC.vhd | 23 +
sources/encoding/EncoderTTC.vhd | 19 +
sources/encoding/EncodingEgroupGBT.vhd | 19 +
sources/encoding/EncodingEgroupLPGBT.vhd | 19 +
sources/encoding/EncodingEpathGBT.vhd | 19 +
sources/encoding/EncodingEpathGBT_tb.vhd | 17 +
sources/encoding/EncodingEpathLPGBT.vhd | 20 +
sources/encoding/EncodingGearBox.vhd | 20 +
sources/encoding/ExtendedTestPulse.vhd | 19 +
sources/encoding/FIFO_bit_stuffing.vhd | 17 +
sources/encoding/enc_8b10b.vhd | 19 +
sources/encoding/encoding.vhd | 21 +
sources/encoding/fifo_v1.vhd | 17 +
sources/spi/spi_master.vhd | 1239 +++++++++--------
sources/ttc/ttc_busy/BusyVirtualElink.vhd | 17 +
.../ttc/ttc_busy/TTCToHostVirtualElink.vhd | 17 +
136 files changed, 3073 insertions(+), 619 deletions(-)
mode change 100755 => 100644 simulation/ItkStrip/tb_clk40_detect.vhd
mode change 100755 => 100644 simulation/ItkStrip/tb_r3l1_regmap.vhd
mode change 100755 => 100644 simulation/ItkStrip/tb_strips_configuration_decoder.vhd
mode change 100755 => 100644 sources/ItkStrip/r3l1_regmap.vhd
mode change 100755 => 100644 sources/ItkStrip/r3l1_regmap_package.vhd
mode change 100755 => 100644 sources/ItkStrip/strips_configuration_decoder.vhd
diff --git a/simulation/CRFromHostAxis/CRFromHostAxis_tb.vhd b/simulation/CRFromHostAxis/CRFromHostAxis_tb.vhd
index 2e806e98f..a122b0fdc 100644
--- a/simulation/CRFromHostAxis/CRFromHostAxis_tb.vhd
+++ b/simulation/CRFromHostAxis/CRFromHostAxis_tb.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
diff --git a/simulation/CRFromHostAxis/SimpleFromHostFifo.vhd b/simulation/CRFromHostAxis/SimpleFromHostFifo.vhd
index 2c05dbdad..33b3f23d3 100644
--- a/simulation/CRFromHostAxis/SimpleFromHostFifo.vhd
+++ b/simulation/CRFromHostAxis/SimpleFromHostFifo.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
diff --git a/simulation/Endeavour/amac_chip.vhd b/simulation/Endeavour/amac_chip.vhd
index f9f7a4580..92feb13ce 100644
--- a/simulation/Endeavour/amac_chip.vhd
+++ b/simulation/Endeavour/amac_chip.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! jacopo pinzino
+--! Frans Schreuder
+--! Elena Zhivun
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
diff --git a/simulation/Endeavour/amac_demo_tb.vhd b/simulation/Endeavour/amac_demo_tb.vhd
index f805b3943..2b391d742 100644
--- a/simulation/Endeavour/amac_demo_tb.vhd
+++ b/simulation/Endeavour/amac_demo_tb.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! jacopo pinzino
+--! Frans Schreuder
+--! Elena Zhivun
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
diff --git a/simulation/Endeavour/tb_amac_decoder.vhd b/simulation/Endeavour/tb_amac_decoder.vhd
index 1bfdcfbfb..30f30f952 100644
--- a/simulation/Endeavour/tb_amac_decoder.vhd
+++ b/simulation/Endeavour/tb_amac_decoder.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Elena Zhivun
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
diff --git a/simulation/Endeavour/tb_amac_deglitcher.vhd b/simulation/Endeavour/tb_amac_deglitcher.vhd
index a5a6d73c3..2017add50 100644
--- a/simulation/Endeavour/tb_amac_deglitcher.vhd
+++ b/simulation/Endeavour/tb_amac_deglitcher.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Elena Zhivun
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
diff --git a/simulation/Endeavour/tb_amac_encoder.vhd b/simulation/Endeavour/tb_amac_encoder.vhd
index 0043125ae..b2272cfa1 100644
--- a/simulation/Endeavour/tb_amac_encoder.vhd
+++ b/simulation/Endeavour/tb_amac_encoder.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Elena Zhivun
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
diff --git a/simulation/FELIX_Top/Decoding_pixel_tb_noUVVM.vhd b/simulation/FELIX_Top/Decoding_pixel_tb_noUVVM.vhd
index 5d45cf320..72b94ddd5 100644
--- a/simulation/FELIX_Top/Decoding_pixel_tb_noUVVM.vhd
+++ b/simulation/FELIX_Top/Decoding_pixel_tb_noUVVM.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
diff --git a/simulation/FELIX_Top/Encoding_pixel_tb_noUVVM.vhd b/simulation/FELIX_Top/Encoding_pixel_tb_noUVVM.vhd
index db8c12f55..72900e597 100644
--- a/simulation/FELIX_Top/Encoding_pixel_tb_noUVVM.vhd
+++ b/simulation/FELIX_Top/Encoding_pixel_tb_noUVVM.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--from ~/Phase2/dacanc/EPROCRD53ADownlinktest/triggerunit_TianXingZheng/forVivado2015_4/triggerunit/triggerunit.srcs/sim_1/new/FELIX_top_testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
diff --git a/simulation/FELIX_Top/package_pixel.vhd b/simulation/FELIX_Top/package_pixel.vhd
index 67c762d06..78b85bc26 100644
--- a/simulation/FELIX_Top/package_pixel.vhd
+++ b/simulation/FELIX_Top/package_pixel.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
diff --git a/simulation/FELIX_fullmode_top/felix_fullmode_tb.vhd b/simulation/FELIX_fullmode_top/felix_fullmode_tb.vhd
index 7522e38d4..e7c5a25e3 100644
--- a/simulation/FELIX_fullmode_top/felix_fullmode_tb.vhd
+++ b/simulation/FELIX_fullmode_top/felix_fullmode_tb.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!------------------------------------------------------------------------------
--!
diff --git a/simulation/FELIX_fullmode_top/pcie_ep_wrap_sim.vhd b/simulation/FELIX_fullmode_top/pcie_ep_wrap_sim.vhd
index ff9595ebf..279504c28 100644
--- a/simulation/FELIX_fullmode_top/pcie_ep_wrap_sim.vhd
+++ b/simulation/FELIX_fullmode_top/pcie_ep_wrap_sim.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!------------------------------------------------------------------------------
--!
diff --git a/simulation/ItkStrip/tb_clk40_detect.vhd b/simulation/ItkStrip/tb_clk40_detect.vhd
old mode 100755
new mode 100644
index 0c099be91..9f4b6663a
--- a/simulation/ItkStrip/tb_clk40_detect.vhd
+++ b/simulation/ItkStrip/tb_clk40_detect.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Elena Zhivun
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--------------------------------------------------------------------------------
-- Title : CLK40 transition detection testbench
-- Project : Default Project Name
diff --git a/simulation/ItkStrip/tb_r3l1_regmap.vhd b/simulation/ItkStrip/tb_r3l1_regmap.vhd
old mode 100755
new mode 100644
index 63f3d802a..332b8d008
--- a/simulation/ItkStrip/tb_r3l1_regmap.vhd
+++ b/simulation/ItkStrip/tb_r3l1_regmap.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Elena Zhivun
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
diff --git a/simulation/ItkStrip/tb_strips_configuration_decoder.vhd b/simulation/ItkStrip/tb_strips_configuration_decoder.vhd
old mode 100755
new mode 100644
index ce5f75d3a..d9109759b
--- a/simulation/ItkStrip/tb_strips_configuration_decoder.vhd
+++ b/simulation/ItkStrip/tb_strips_configuration_decoder.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Elena Zhivun
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
diff --git a/simulation/UVVMtests/DecodingEpath_tb.vhd b/simulation/UVVMtests/DecodingEpath_tb.vhd
index b85e3fefb..c3920aa14 100644
--- a/simulation/UVVMtests/DecodingEpath_tb.vhd
+++ b/simulation/UVVMtests/DecodingEpath_tb.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
diff --git a/simulation/UVVMtests/tb/BusyVirtualElink_tb.vhd b/simulation/UVVMtests/tb/BusyVirtualElink_tb.vhd
index 7fd99faa4..c6205b5be 100644
--- a/simulation/UVVMtests/tb/BusyVirtualElink_tb.vhd
+++ b/simulation/UVVMtests/tb/BusyVirtualElink_tb.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
diff --git a/simulation/UVVMtests/tb/ByteToAxiStream_tb.vhd b/simulation/UVVMtests/tb/ByteToAxiStream_tb.vhd
index f64687c9c..a79d5556d 100644
--- a/simulation/UVVMtests/tb/ByteToAxiStream_tb.vhd
+++ b/simulation/UVVMtests/tb/ByteToAxiStream_tb.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
diff --git a/simulation/UVVMtests/tb/CRToHost_tb.vhd b/simulation/UVVMtests/tb/CRToHost_tb.vhd
index 7a0cae48b..33c93f893 100644
--- a/simulation/UVVMtests/tb/CRToHost_tb.vhd
+++ b/simulation/UVVMtests/tb/CRToHost_tb.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
diff --git a/simulation/UVVMtests/tb/DecEgroup_8b10b_framegen.vhd b/simulation/UVVMtests/tb/DecEgroup_8b10b_framegen.vhd
index 05946cfef..f0089ffff 100644
--- a/simulation/UVVMtests/tb/DecEgroup_8b10b_framegen.vhd
+++ b/simulation/UVVMtests/tb/DecEgroup_8b10b_framegen.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee, xpm;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
diff --git a/simulation/UVVMtests/tb/DecEgroup_8b10b_tb.vhd b/simulation/UVVMtests/tb/DecEgroup_8b10b_tb.vhd
index 8c6d6adfa..12a5e8f31 100644
--- a/simulation/UVVMtests/tb/DecEgroup_8b10b_tb.vhd
+++ b/simulation/UVVMtests/tb/DecEgroup_8b10b_tb.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
diff --git a/simulation/UVVMtests/tb/DecodingGearBox_tb.vhd b/simulation/UVVMtests/tb/DecodingGearBox_tb.vhd
index 632179efb..e97b95455 100644
--- a/simulation/UVVMtests/tb/DecodingGearBox_tb.vhd
+++ b/simulation/UVVMtests/tb/DecodingGearBox_tb.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- ATLAS
-- FELIX UVVM test automation project
diff --git a/simulation/UVVMtests/tb/Decoding_pixel_tb.vhd b/simulation/UVVMtests/tb/Decoding_pixel_tb.vhd
index d767814fa..887bb7ffe 100644
--- a/simulation/UVVMtests/tb/Decoding_pixel_tb.vhd
+++ b/simulation/UVVMtests/tb/Decoding_pixel_tb.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marco
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- ATLAS
-- FELIX UVVM test automation project
diff --git a/simulation/UVVMtests/tb/EncodingEpath_tb.vhd b/simulation/UVVMtests/tb/EncodingEpath_tb.vhd
index 88a259050..69ee68c12 100644
--- a/simulation/UVVMtests/tb/EncodingEpath_tb.vhd
+++ b/simulation/UVVMtests/tb/EncodingEpath_tb.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Kazuki Todome
+--! Nico Giangiacomi
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- ATLAS
-- FELIX UVVM test automation project
diff --git a/simulation/UVVMtests/tb/FELIXDataSink.vhd b/simulation/UVVMtests/tb/FELIXDataSink.vhd
index 7f0ee26dc..44b1f6c62 100644
--- a/simulation/UVVMtests/tb/FELIXDataSink.vhd
+++ b/simulation/UVVMtests/tb/FELIXDataSink.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Filiberto Bonini
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- ATLAS
-- FELIX UVVM test automation project
diff --git a/simulation/UVVMtests/tb/FELIXDataSource.vhd b/simulation/UVVMtests/tb/FELIXDataSource.vhd
index bdba0d6cc..c87112a2f 100644
--- a/simulation/UVVMtests/tb/FELIXDataSource.vhd
+++ b/simulation/UVVMtests/tb/FELIXDataSource.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- ATLAS
-- FELIX UVVM test automation project
diff --git a/simulation/UVVMtests/tb/FULLModeToHost_tb.vhd b/simulation/UVVMtests/tb/FULLModeToHost_tb.vhd
index 495bdbb84..67fdc8124 100644
--- a/simulation/UVVMtests/tb/FULLModeToHost_tb.vhd
+++ b/simulation/UVVMtests/tb/FULLModeToHost_tb.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Filiberto Bonini
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- ATLAS
-- FELIX UVVM test automation project
diff --git a/simulation/UVVMtests/tb/GBTCrCoding_tb.vhd b/simulation/UVVMtests/tb/GBTCrCoding_tb.vhd
index 0ea82630e..e1a17c2db 100644
--- a/simulation/UVVMtests/tb/GBTCrCoding_tb.vhd
+++ b/simulation/UVVMtests/tb/GBTCrCoding_tb.vhd
@@ -1,3 +1,23 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Filiberto Bonini
+--! Nico Giangiacomi
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- file: GBTCrCoding_tb.vhd.
-- Testbench to excercise CrFromHost, CRToHost, encoding, decoding in GBT mode
diff --git a/simulation/UVVMtests/tb/GBTLinkToHost_tb.vhd b/simulation/UVVMtests/tb/GBTLinkToHost_tb.vhd
index f1a29330c..7e0c9be6a 100644
--- a/simulation/UVVMtests/tb/GBTLinkToHost_tb.vhd
+++ b/simulation/UVVMtests/tb/GBTLinkToHost_tb.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Filiberto Bonini
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- ATLAS
-- FELIX UVVM test automation project
diff --git a/simulation/UVVMtests/tb/TTCToHostVirtualElink_tb.vhd b/simulation/UVVMtests/tb/TTCToHostVirtualElink_tb.vhd
index bcf540783..9428bd29d 100644
--- a/simulation/UVVMtests/tb/TTCToHostVirtualElink_tb.vhd
+++ b/simulation/UVVMtests/tb/TTCToHostVirtualElink_tb.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
diff --git a/simulation/UVVMtests/tb/XcodingEpath_tb.vhd b/simulation/UVVMtests/tb/XcodingEpath_tb.vhd
index a2cedbcad..0ea618ae6 100644
--- a/simulation/UVVMtests/tb/XcodingEpath_tb.vhd
+++ b/simulation/UVVMtests/tb/XcodingEpath_tb.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Filiberto Bonini
+--! Nico Giangiacomi
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- ATLAS
-- FELIX UVVM test automation project
diff --git a/sources/64b66b/64b66b_DecodingGearBox.vhd b/sources/64b66b/64b66b_DecodingGearBox.vhd
index e1f7935ae..448919575 100644
--- a/sources/64b66b/64b66b_DecodingGearBox.vhd
+++ b/sources/64b66b/64b66b_DecodingGearBox.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
--! Company: Nikhef, Argonne National Laboratory
--! Engineer: Frans Schreuder (initially written by), Marco Trovato
diff --git a/sources/64b66b/64b66b_clockmanagement.vhd b/sources/64b66b/64b66b_clockmanagement.vhd
index d437d2220..944327e5a 100644
--- a/sources/64b66b/64b66b_clockmanagement.vhd
+++ b/sources/64b66b/64b66b_clockmanagement.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
diff --git a/sources/64b66b/64b66b_decoding.vhd b/sources/64b66b/64b66b_decoding.vhd
index 6968700f5..23717d680 100644
--- a/sources/64b66b/64b66b_decoding.vhd
+++ b/sources/64b66b/64b66b_decoding.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company: Argonne National Laboratory
-- Engineer: Marco Trovato
diff --git a/sources/64b66b/64b66b_top.vhd b/sources/64b66b/64b66b_top.vhd
index c3b04c771..9e355383e 100644
--- a/sources/64b66b/64b66b_top.vhd
+++ b/sources/64b66b/64b66b_top.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use work.axi_stream_package.all;
diff --git a/sources/64b66b/Aggregator_64b66b.vhd b/sources/64b66b/Aggregator_64b66b.vhd
index 54146eaef..4a1578cc7 100644
--- a/sources/64b66b/Aggregator_64b66b.vhd
+++ b/sources/64b66b/Aggregator_64b66b.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--implementation: apriori agnostic on which RD53A lane will carry the header so
--it will be easier to port to RD53B
--data comes directly from 64b66b decoder after bonding. Considering placing FIFOs that--will allow full control of the incoming data by controlling the rd_en
diff --git a/sources/64b66b/CntRcvdPckts_64b66b.vhd b/sources/64b66b/CntRcvdPckts_64b66b.vhd
index ac86a9956..26e9f8e0f 100644
--- a/sources/64b66b/CntRcvdPckts_64b66b.vhd
+++ b/sources/64b66b/CntRcvdPckts_64b66b.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library work, IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
diff --git a/sources/64b66b/RemapEpaths.vhd b/sources/64b66b/RemapEpaths.vhd
index 3dc0221a8..99037ccc2 100644
--- a/sources/64b66b/RemapEpaths.vhd
+++ b/sources/64b66b/RemapEpaths.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
diff --git a/sources/64b66b/gearbox32to64_64b66b.vhd b/sources/64b66b/gearbox32to64_64b66b.vhd
index 7984e2477..eda5bc55f 100644
--- a/sources/64b66b/gearbox32to64_64b66b.vhd
+++ b/sources/64b66b/gearbox32to64_64b66b.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
------------------------------------------------------------------------------------
----! Company: Argonne National Laboratory
----! Engineer: Marco Trovato
diff --git a/sources/64b66b/split64bword.vhd b/sources/64b66b/split64bword.vhd
index bd11d3284..a49591d5c 100644
--- a/sources/64b66b/split64bword.vhd
+++ b/sources/64b66b/split64bword.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
diff --git a/sources/AxisUtils/Axis64Fifo.vhd b/sources/AxisUtils/Axis64Fifo.vhd
index 28bc8367c..2b4f8f779 100644
--- a/sources/AxisUtils/Axis64Fifo.vhd
+++ b/sources/AxisUtils/Axis64Fifo.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
diff --git a/sources/AxisUtils/Axis8Fifo.vhd b/sources/AxisUtils/Axis8Fifo.vhd
index fdaef7dde..57fc401d1 100644
--- a/sources/AxisUtils/Axis8Fifo.vhd
+++ b/sources/AxisUtils/Axis8Fifo.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Nico Giangiacomi
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
diff --git a/sources/CRFromHost/CRFromHost.vhd b/sources/CRFromHost/CRFromHost.vhd
index 3770577f8..7d7de05d7 100644
--- a/sources/CRFromHost/CRFromHost.vhd
+++ b/sources/CRFromHost/CRFromHost.vhd
@@ -1,3 +1,25 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Julia Narevicius
+--! Andrea Borga
+--! Enrico Gamberini
+--! Thei Wijnen
+--! Filiberto Bonini
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
--! Company: EDAQ WIS, Nikhef.
--! Engineer: juna, fschreud
diff --git a/sources/CRFromHostAxis/CRFromHostAxis.vhd b/sources/CRFromHostAxis/CRFromHostAxis.vhd
index 1967c9cc3..d76258bcc 100644
--- a/sources/CRFromHostAxis/CRFromHostAxis.vhd
+++ b/sources/CRFromHostAxis/CRFromHostAxis.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
diff --git a/sources/CRFromHostAxis/CRFromHostDataManagerAxis.vhd b/sources/CRFromHostAxis/CRFromHostDataManagerAxis.vhd
index f91ddc97b..d8e19a351 100644
--- a/sources/CRFromHostAxis/CRFromHostDataManagerAxis.vhd
+++ b/sources/CRFromHostAxis/CRFromHostDataManagerAxis.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--! Marius Wensing
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
diff --git a/sources/CRFromHostAxis/CRFromHostGroupFifo.vhd b/sources/CRFromHostAxis/CRFromHostGroupFifo.vhd
index 40624d519..bf1ed20d0 100644
--- a/sources/CRFromHostAxis/CRFromHostGroupFifo.vhd
+++ b/sources/CRFromHostAxis/CRFromHostGroupFifo.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
diff --git a/sources/CRFromHostAxis/CRFromHostLinkFifo.vhd b/sources/CRFromHostAxis/CRFromHostLinkFifo.vhd
index c61b7930b..957b17b9e 100644
--- a/sources/CRFromHostAxis/CRFromHostLinkFifo.vhd
+++ b/sources/CRFromHostAxis/CRFromHostLinkFifo.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
diff --git a/sources/CRFromHostAxis/CRFromHostTransferManager.vhd b/sources/CRFromHostAxis/CRFromHostTransferManager.vhd
index bfe1bcaf8..fd04fa3dd 100644
--- a/sources/CRFromHostAxis/CRFromHostTransferManager.vhd
+++ b/sources/CRFromHostAxis/CRFromHostTransferManager.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--! Marius Wensing
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
diff --git a/sources/CRToHost/CRToHost.vhd b/sources/CRToHost/CRToHost.vhd
index a0f5c48ad..00d98f60e 100644
--- a/sources/CRToHost/CRToHost.vhd
+++ b/sources/CRToHost/CRToHost.vhd
@@ -1,3 +1,26 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Julia Narevicius
+--! Andrea Borga
+--! Enrico Gamberini
+--! Thei Wijnen
+--! Filiberto Bonini
+--! mtrovato
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
--! Company: EDAQ WIS, Nikhef.
--! Engineer: juna, fschreud
diff --git a/sources/CRToHost/CRToHostdm.vhd b/sources/CRToHost/CRToHostdm.vhd
index 5099abd7e..555500656 100644
--- a/sources/CRToHost/CRToHostdm.vhd
+++ b/sources/CRToHost/CRToHostdm.vhd
@@ -1,3 +1,24 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Julia Narevicius
+--! Enrico Gamberini
+--! Thei Wijnen
+--! mtrovato
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
diff --git a/sources/CRToHost/MUXn.vhd b/sources/CRToHost/MUXn.vhd
index 404661ed8..7cb48c519 100644
--- a/sources/CRToHost/MUXn.vhd
+++ b/sources/CRToHost/MUXn.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Julia Narevicius
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
diff --git a/sources/CRToHost/ToHostAxiStream64Controller.vhd b/sources/CRToHost/ToHostAxiStream64Controller.vhd
index d66672e96..8d1ca473b 100644
--- a/sources/CRToHost/ToHostAxiStream64Controller.vhd
+++ b/sources/CRToHost/ToHostAxiStream64Controller.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
--! Company: Nikhef
--! Engineer: Frans Schreuder
diff --git a/sources/Endeavour/EndeavourDecoder.vhd b/sources/Endeavour/EndeavourDecoder.vhd
index f920d04c5..a1f575d49 100644
--- a/sources/Endeavour/EndeavourDecoder.vhd
+++ b/sources/Endeavour/EndeavourDecoder.vhd
@@ -1,3 +1,24 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Jacopo Pinzino
+--! jacopo pinzino
+--! Nico Giangiacomi
+--! Frans Schreuder
+--! Elena Zhivun
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer: jacopo pinzino
diff --git a/sources/Endeavour/EndeavourDeglitcher.vhd b/sources/Endeavour/EndeavourDeglitcher.vhd
index ccd885451..3de552388 100644
--- a/sources/Endeavour/EndeavourDeglitcher.vhd
+++ b/sources/Endeavour/EndeavourDeglitcher.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! jacopo pinzino
+--! Frans Schreuder
+--! Elena Zhivun
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer: jacopo pinzino
diff --git a/sources/Endeavour/EndeavourEncoder.vhd b/sources/Endeavour/EndeavourEncoder.vhd
index aebc0446a..d5ab9086b 100644
--- a/sources/Endeavour/EndeavourEncoder.vhd
+++ b/sources/Endeavour/EndeavourEncoder.vhd
@@ -1,3 +1,23 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Jacopo Pinzino
+--! jacopo pinzino
+--! Elena Zhivun
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer: jacopo pinzino, Elena Zhivun <ezhivun@bnl.gov>
diff --git a/sources/Endeavour/EndeavourPackage.vhd b/sources/Endeavour/EndeavourPackage.vhd
index 0bb273cba..1de840ae9 100644
--- a/sources/Endeavour/EndeavourPackage.vhd
+++ b/sources/Endeavour/EndeavourPackage.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Elena Zhivun
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
diff --git a/sources/FanoutSelectors/axis_32_fanout_selector.vhd b/sources/FanoutSelectors/axis_32_fanout_selector.vhd
index e5f13ce30..7697622c7 100644
--- a/sources/FanoutSelectors/axis_32_fanout_selector.vhd
+++ b/sources/FanoutSelectors/axis_32_fanout_selector.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
diff --git a/sources/FanoutSelectors/gbt_fanout_selector.vhd b/sources/FanoutSelectors/gbt_fanout_selector.vhd
index 88e9dde70..eafbe2b91 100644
--- a/sources/FanoutSelectors/gbt_fanout_selector.vhd
+++ b/sources/FanoutSelectors/gbt_fanout_selector.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--! Marius Wensing
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
diff --git a/sources/FullModeWrapper/gth_fullmode_wrapper_48g_ku.vhd b/sources/FullModeWrapper/gth_fullmode_wrapper_48g_ku.vhd
index e2bc47ebb..040d4b174 100644
--- a/sources/FullModeWrapper/gth_fullmode_wrapper_48g_ku.vhd
+++ b/sources/FullModeWrapper/gth_fullmode_wrapper_48g_ku.vhd
@@ -1,3 +1,23 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Weihao Wu
+--! Kai Chen
+--! Alessandro Palombi
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--Modified by Kai Chen
-- 2015/01/14
-- For FELIX: 4-chanel 4.8Gbps QPLL GTH
diff --git a/sources/FullModeWrapper/gth_fullmode_wrapper_48g_v7.vhd b/sources/FullModeWrapper/gth_fullmode_wrapper_48g_v7.vhd
index f2545ea79..bccb36ad8 100644
--- a/sources/FullModeWrapper/gth_fullmode_wrapper_48g_v7.vhd
+++ b/sources/FullModeWrapper/gth_fullmode_wrapper_48g_v7.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Weihao Wu
+--! Alessandro Palombi
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--Modified by Kai Chen
-- 2015/01/14
-- For FELIX: 4-chanel 4.8Gbps QPLL GTH
diff --git a/sources/FullModeWrapper/gth_fullmode_wrapper_48g_vup.vhd b/sources/FullModeWrapper/gth_fullmode_wrapper_48g_vup.vhd
index 8daea40b1..1a5da299b 100644
--- a/sources/FullModeWrapper/gth_fullmode_wrapper_48g_vup.vhd
+++ b/sources/FullModeWrapper/gth_fullmode_wrapper_48g_vup.vhd
@@ -1,3 +1,23 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Weihao Wu
+--! Kai Chen
+--! Rene
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--Modified by Kai Chen
-- 2015/01/14
-- For FELIX: 4-chanel 4.8Gbps QPLL GTH
diff --git a/sources/FullModeWrapper/gth_fullmode_wrapper_vup.vhd b/sources/FullModeWrapper/gth_fullmode_wrapper_vup.vhd
index cc7edd637..daf491316 100644
--- a/sources/FullModeWrapper/gth_fullmode_wrapper_vup.vhd
+++ b/sources/FullModeWrapper/gth_fullmode_wrapper_vup.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Weihao Wu
+--! Kai Chen
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--Modified by Kai Chen
-- 2015/01/14
-- For FELIX: 4-chanel 4.8Gbps QPLL GTH
diff --git a/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd b/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd
index 68f821d62..6b9f16b93 100644
--- a/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd
+++ b/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd
@@ -1,3 +1,26 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Andrea Borga
+--! Israel Grayzman
+--! RHabraken
+--! Kai Chen
+--! Shelfali Saxena
+--! mtrovato
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!----------------------------FA------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
diff --git a/sources/ItkStrip/r3l1_regmap.vhd b/sources/ItkStrip/r3l1_regmap.vhd
old mode 100755
new mode 100644
index ffe0785c9..5b5b3fcbf
--- a/sources/ItkStrip/r3l1_regmap.vhd
+++ b/sources/ItkStrip/r3l1_regmap.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Elena Zhivun
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
diff --git a/sources/ItkStrip/r3l1_regmap_package.vhd b/sources/ItkStrip/r3l1_regmap_package.vhd
old mode 100755
new mode 100644
index 8e43c78ad..834f307d2
--- a/sources/ItkStrip/r3l1_regmap_package.vhd
+++ b/sources/ItkStrip/r3l1_regmap_package.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Elena Zhivun
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
diff --git a/sources/ItkStrip/strips_configuration_decoder.vhd b/sources/ItkStrip/strips_configuration_decoder.vhd
old mode 100755
new mode 100644
index 2138a011e..e03eac95f
--- a/sources/ItkStrip/strips_configuration_decoder.vhd
+++ b/sources/ItkStrip/strips_configuration_decoder.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Elena Zhivun
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--------------------------------------------------------------------------------
-- Title : ITk Strips package
-- Project : FELIX
diff --git a/sources/LinkWrapper/link_wrapper.vhd b/sources/LinkWrapper/link_wrapper.vhd
index 509f8c864..e882a0c7e 100644
--- a/sources/LinkWrapper/link_wrapper.vhd
+++ b/sources/LinkWrapper/link_wrapper.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Alessandro Palombi
+--! mtrovato
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
diff --git a/sources/LpGBT/LpGBT_FELIX/BIT_ERROR_CALC.vhd b/sources/LpGBT/LpGBT_FELIX/BIT_ERROR_CALC.vhd
index 364d1ad90..fde833973 100644
--- a/sources/LpGBT/LpGBT_FELIX/BIT_ERROR_CALC.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/BIT_ERROR_CALC.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Kai Chen
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
diff --git a/sources/LpGBT/LpGBT_FELIX/FELIX_LpGBT_Wrapper.vhd b/sources/LpGBT/LpGBT_FELIX/FELIX_LpGBT_Wrapper.vhd
index 07fdbe42f..b13fc790a 100644
--- a/sources/LpGBT/LpGBT_FELIX/FELIX_LpGBT_Wrapper.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/FELIX_LpGBT_Wrapper.vhd
@@ -1,3 +1,23 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Kai Chen
+--! dmatakia
+--! Frans Schreuder
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE.vhd
index 9a46d67cf..eeaf31b31 100644
--- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE.vhd
@@ -1,3 +1,23 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Kai Chen
+--! mtrovato
+--! Elena Zhivun
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE_Wrapper.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE_Wrapper.vhd
index c1a266691..7aa2e8cb0 100644
--- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE_Wrapper.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE_Wrapper.vhd
@@ -1,3 +1,24 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! dmatakia
+--! Kai Chen
+--! Elena Zhivun
+--! mtrovato
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE.vhd
index 64d6ead11..68905cc9c 100644
--- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Kai Chen
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE_Wrapper.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE_Wrapper.vhd
index 06b489f89..6b23c35ec 100644
--- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE_Wrapper.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE_Wrapper.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! dmatakia
+--! Kai Chen
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_BE.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_BE.vhd
index 1434c0292..88ab307e8 100644
--- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_BE.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_BE.vhd
@@ -1,3 +1,23 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Andrea Borga
+--! Kai Chen
+--! mtrovato
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_FE.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_FE.vhd
index b872d2ee2..4c4bbd389 100644
--- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_FE.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_FE.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Andrea Borga
+--! Kai Chen
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_PRBS.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_PRBS.vhd
index 7ece16cfe..687546437 100644
--- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_PRBS.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_PRBS.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Kai Chen
+--! dmatakia
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
diff --git a/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Chk.vhd b/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Chk.vhd
index 97b62b3b0..1b1b6185b 100644
--- a/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Chk.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Chk.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Andrea Borga
+--! Kai Chen
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
diff --git a/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Gen.vhd b/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Gen.vhd
index 2c3670bc6..f719f7315 100644
--- a/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Gen.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Gen.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Kai Chen
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
diff --git a/sources/LpGBT/LpGBT_FELIX/RefClk_Gen.vhd b/sources/LpGBT/LpGBT_FELIX/RefClk_Gen.vhd
index aef364c44..d699cd5a7 100644
--- a/sources/LpGBT/LpGBT_FELIX/RefClk_Gen.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/RefClk_Gen.vhd
@@ -1,3 +1,23 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Kai Chen
+--! Frans Schreuder
+--! Elena Zhivun
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
diff --git a/sources/LpGBT/LpGBT_FELIX/Regs_RW.vhd b/sources/LpGBT/LpGBT_FELIX/Regs_RW.vhd
index 266a80b56..d2ed7d713 100644
--- a/sources/LpGBT/LpGBT_FELIX/Regs_RW.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/Regs_RW.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Kai Chen
+--! mtrovato
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
diff --git a/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd b/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd
index d6c8a1b7b..7dbdafc69 100644
--- a/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
-------------------------------------------------------
--! @file
--! @author Julian Mendez <julian.mendez@cern.ch> (CERN - EP-ESE-BE)
diff --git a/sources/RD53A/ENCRD53A.vhd b/sources/RD53A/ENCRD53A.vhd
index 4f18d0b15..ca502899f 100644
--- a/sources/RD53A/ENCRD53A.vhd
+++ b/sources/RD53A/ENCRD53A.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Alexander Paramonov, Marco Trovato, Tianxing Zheng
diff --git a/sources/RD53A/RD53A_CntIssuedCommand.vhd b/sources/RD53A/RD53A_CntIssuedCommand.vhd
index 17f44a926..e0ef134bb 100644
--- a/sources/RD53A/RD53A_CntIssuedCommand.vhd
+++ b/sources/RD53A/RD53A_CntIssuedCommand.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library work, IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
diff --git a/sources/RD53A/RD53A_CntIssuedCommand8b.vhd b/sources/RD53A/RD53A_CntIssuedCommand8b.vhd
index c5fff48bc..148ad9721 100644
--- a/sources/RD53A/RD53A_CntIssuedCommand8b.vhd
+++ b/sources/RD53A/RD53A_CntIssuedCommand8b.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library work, IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
diff --git a/sources/RD53A/RD53A_CntIssuedGivenCommand.vhd b/sources/RD53A/RD53A_CntIssuedGivenCommand.vhd
index fb5fc8d10..a94429319 100644
--- a/sources/RD53A/RD53A_CntIssuedGivenCommand.vhd
+++ b/sources/RD53A/RD53A_CntIssuedGivenCommand.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library work, IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
diff --git a/sources/RD53A/RD53A_CntIssuedTrigger.vhd b/sources/RD53A/RD53A_CntIssuedTrigger.vhd
index 67c6285f0..9dd36355c 100644
--- a/sources/RD53A/RD53A_CntIssuedTrigger.vhd
+++ b/sources/RD53A/RD53A_CntIssuedTrigger.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library work, IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
diff --git a/sources/RD53A/RD53A_DebuggingModule.vhd b/sources/RD53A/RD53A_DebuggingModule.vhd
index 46d5a9897..d7dc36c51 100644
--- a/sources/RD53A/RD53A_DebuggingModule.vhd
+++ b/sources/RD53A/RD53A_DebuggingModule.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library work, IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
diff --git a/sources/RD53A/RD53A_MsrGenCalToTrigLatency.vhd b/sources/RD53A/RD53A_MsrGenCalToTrigLatency.vhd
index fcf34f708..f455ac0a1 100644
--- a/sources/RD53A/RD53A_MsrGenCalToTrigLatency.vhd
+++ b/sources/RD53A/RD53A_MsrGenCalToTrigLatency.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library work, IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
diff --git a/sources/RD53A/RD53A_MsrTrigFreq.vhd b/sources/RD53A/RD53A_MsrTrigFreq.vhd
index e1e9594f6..4dac54268 100644
--- a/sources/RD53A/RD53A_MsrTrigFreq.vhd
+++ b/sources/RD53A/RD53A_MsrTrigFreq.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library work, IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
diff --git a/sources/RD53A/az_controller.vhd b/sources/RD53A/az_controller.vhd
index 206c899c1..06b4d8eff 100644
--- a/sources/RD53A/az_controller.vhd
+++ b/sources/RD53A/az_controller.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Marco Trovato
diff --git a/sources/RD53A/cmd_top.vhd b/sources/RD53A/cmd_top.vhd
index 8dcc8c6f7..72212e4cb 100644
--- a/sources/RD53A/cmd_top.vhd
+++ b/sources/RD53A/cmd_top.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Alexander Paramonov, Marco Trovato, Tianxing Zheng
diff --git a/sources/RD53A/newtriggerunit.vhd b/sources/RD53A/newtriggerunit.vhd
index cf09f8866..9eaf4ebb8 100644
--- a/sources/RD53A/newtriggerunit.vhd
+++ b/sources/RD53A/newtriggerunit.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Alexander Paramonov, Marco Trovato, Tianxing Zheng
diff --git a/sources/RD53A/rd53a_package.vhd b/sources/RD53A/rd53a_package.vhd
index 85958cb3f..b98867c31 100644
--- a/sources/RD53A/rd53a_package.vhd
+++ b/sources/RD53A/rd53a_package.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
diff --git a/sources/RD53A/sync_timer.vhd b/sources/RD53A/sync_timer.vhd
index 11847744f..c674a85cd 100644
--- a/sources/RD53A/sync_timer.vhd
+++ b/sources/RD53A/sync_timer.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Alexander Paramonov, Marco Trovato, Tianxing Zheng
diff --git a/sources/centralRouter/EPROC_OUT8_FEI4.vhd b/sources/centralRouter/EPROC_OUT8_FEI4.vhd
index ef1873652..80c9f6c84 100644
--- a/sources/centralRouter/EPROC_OUT8_FEI4.vhd
+++ b/sources/centralRouter/EPROC_OUT8_FEI4.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
--! Company: University of Wuppertal
--! Engineer: Carsten Duelsen <carsten.dulsen@cern.ch>
diff --git a/sources/centralRouter/RD53A_DL_Eproc/EPROC_OUT4_RD53A.vhd b/sources/centralRouter/RD53A_DL_Eproc/EPROC_OUT4_RD53A.vhd
index 5851c29a4..03c59691f 100644
--- a/sources/centralRouter/RD53A_DL_Eproc/EPROC_OUT4_RD53A.vhd
+++ b/sources/centralRouter/RD53A_DL_Eproc/EPROC_OUT4_RD53A.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
diff --git a/sources/centralRouter/RD53A_DL_Eproc/RD53A_DL_EProc.vhd b/sources/centralRouter/RD53A_DL_Eproc/RD53A_DL_EProc.vhd
index e02909206..295ea0d09 100644
--- a/sources/centralRouter/RD53A_DL_Eproc/RD53A_DL_EProc.vhd
+++ b/sources/centralRouter/RD53A_DL_Eproc/RD53A_DL_EProc.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
diff --git a/sources/centralRouter/RD53A_DL_Eproc/fifoController.vhd b/sources/centralRouter/RD53A_DL_Eproc/fifoController.vhd
index dc580df35..45b2719a2 100644
--- a/sources/centralRouter/RD53A_DL_Eproc/fifoController.vhd
+++ b/sources/centralRouter/RD53A_DL_Eproc/fifoController.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
diff --git a/sources/centralRouter/RD53A_DL_Eproc/merger.vhd b/sources/centralRouter/RD53A_DL_Eproc/merger.vhd
index 272b18623..74faf86a2 100644
--- a/sources/centralRouter/RD53A_DL_Eproc/merger.vhd
+++ b/sources/centralRouter/RD53A_DL_Eproc/merger.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
diff --git a/sources/centralRouter/RD53A_DL_Eproc/pkg_RD53A.vhd b/sources/centralRouter/RD53A_DL_Eproc/pkg_RD53A.vhd
index 8b26edd7b..057d01a07 100644
--- a/sources/centralRouter/RD53A_DL_Eproc/pkg_RD53A.vhd
+++ b/sources/centralRouter/RD53A_DL_Eproc/pkg_RD53A.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.all;
diff --git a/sources/centralRouter/RD53A_DL_Eproc/serializer.vhd b/sources/centralRouter/RD53A_DL_Eproc/serializer.vhd
index dccc0b5df..609295f3c 100644
--- a/sources/centralRouter/RD53A_DL_Eproc/serializer.vhd
+++ b/sources/centralRouter/RD53A_DL_Eproc/serializer.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
diff --git a/sources/centralRouter/RD53A_DL_Eproc/syncEncoder.vhd b/sources/centralRouter/RD53A_DL_Eproc/syncEncoder.vhd
index 69f4784e7..368d9bb19 100644
--- a/sources/centralRouter/RD53A_DL_Eproc/syncEncoder.vhd
+++ b/sources/centralRouter/RD53A_DL_Eproc/syncEncoder.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
diff --git a/sources/centralRouter/RD53A_DL_Eproc/trigEncoder.vhd b/sources/centralRouter/RD53A_DL_Eproc/trigEncoder.vhd
index 58f480e54..b59d10cb0 100644
--- a/sources/centralRouter/RD53A_DL_Eproc/trigEncoder.vhd
+++ b/sources/centralRouter/RD53A_DL_Eproc/trigEncoder.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
diff --git a/sources/centralRouter/RD53A_DL_Eproc/ttcEncoder.vhd b/sources/centralRouter/RD53A_DL_Eproc/ttcEncoder.vhd
index 32c3019ee..37c95fa44 100644
--- a/sources/centralRouter/RD53A_DL_Eproc/ttcEncoder.vhd
+++ b/sources/centralRouter/RD53A_DL_Eproc/ttcEncoder.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
diff --git a/sources/decoding/AlignmentPulseGen.vhd b/sources/decoding/AlignmentPulseGen.vhd
index c64228680..29bae513d 100644
--- a/sources/decoding/AlignmentPulseGen.vhd
+++ b/sources/decoding/AlignmentPulseGen.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
diff --git a/sources/decoding/ByteToAxiStream.vhd b/sources/decoding/ByteToAxiStream.vhd
index a4f6f1544..649370885 100644
--- a/sources/decoding/ByteToAxiStream.vhd
+++ b/sources/decoding/ByteToAxiStream.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--! Carsten Dülsen
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
diff --git a/sources/decoding/ByteToAxiStream32b.vhd b/sources/decoding/ByteToAxiStream32b.vhd
index 63a68399e..3fd94e239 100644
--- a/sources/decoding/ByteToAxiStream32b.vhd
+++ b/sources/decoding/ByteToAxiStream32b.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
diff --git a/sources/decoding/DecEgroup_8b10b.vhd b/sources/decoding/DecEgroup_8b10b.vhd
index 1fa78ffc9..333abec2b 100644
--- a/sources/decoding/DecEgroup_8b10b.vhd
+++ b/sources/decoding/DecEgroup_8b10b.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Carsten Dülsen
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
diff --git a/sources/decoding/Decoder8b10b.vhd b/sources/decoding/Decoder8b10b.vhd
index 706ff32f7..3b2cd3d1e 100644
--- a/sources/decoding/Decoder8b10b.vhd
+++ b/sources/decoding/Decoder8b10b.vhd
@@ -1,3 +1,23 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Julia Narevicius
+--! Israel Grayzman
+--! Carsten Dülsen
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
diff --git a/sources/decoding/DecoderHDLC.vhd b/sources/decoding/DecoderHDLC.vhd
index a107dcafc..6ce9336f5 100644
--- a/sources/decoding/DecoderHDLC.vhd
+++ b/sources/decoding/DecoderHDLC.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
-------------------------------------------------------
--! @file
--! @author Julian Mendez <julian.mendez@cern.ch> (CERN - EP-ESE-BE)
diff --git a/sources/decoding/DecodingEgroupGBT.vhd b/sources/decoding/DecodingEgroupGBT.vhd
index 4c4b029cf..5d35253e5 100644
--- a/sources/decoding/DecodingEgroupGBT.vhd
+++ b/sources/decoding/DecodingEgroupGBT.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
diff --git a/sources/decoding/DecodingEpathGBT.vhd b/sources/decoding/DecodingEpathGBT.vhd
index 1ac5313ea..706ca77f5 100644
--- a/sources/decoding/DecodingEpathGBT.vhd
+++ b/sources/decoding/DecodingEpathGBT.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
diff --git a/sources/decoding/DecodingGearBox.vhd b/sources/decoding/DecodingGearBox.vhd
index 2eba4fcf2..a7ceeca8d 100644
--- a/sources/decoding/DecodingGearBox.vhd
+++ b/sources/decoding/DecodingGearBox.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
-- Use standard library
diff --git a/sources/decoding/DecodingPixelLinkLPGBT.vhd b/sources/decoding/DecodingPixelLinkLPGBT.vhd
index 5260e830a..b38e0d34e 100644
--- a/sources/decoding/DecodingPixelLinkLPGBT.vhd
+++ b/sources/decoding/DecodingPixelLinkLPGBT.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.axi_stream_package.all;
diff --git a/sources/decoding/dec_8b10b.vhd b/sources/decoding/dec_8b10b.vhd
index e969ffc7a..43bf91fcc 100644
--- a/sources/decoding/dec_8b10b.vhd
+++ b/sources/decoding/dec_8b10b.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
-- Chuck Benz, Hollis, NH Copyright (c)2002
--
-- The information and description contained herein is the
diff --git a/sources/decoding/decoding.vhd b/sources/decoding/decoding.vhd
index 95775521f..f7d63289d 100644
--- a/sources/decoding/decoding.vhd
+++ b/sources/decoding/decoding.vhd
@@ -1,3 +1,24 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Filiberto Bonini
+--! Marius Wensing
+--! mtrovato
+--! Elena Zhivun
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
diff --git a/sources/encoding/AxiStreamToByte.vhd b/sources/encoding/AxiStreamToByte.vhd
index c62147e95..b669f4b56 100644
--- a/sources/encoding/AxiStreamToByte.vhd
+++ b/sources/encoding/AxiStreamToByte.vhd
@@ -1,3 +1,21 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Nico Giangiacomi
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company: University of Bologna
-- Engineer: Nico Giangiacomi (nico.giangiacomi@cern.ch)
diff --git a/sources/encoding/Encoder8b10b.vhd b/sources/encoding/Encoder8b10b.vhd
index 2daea0171..f3a1df0a6 100644
--- a/sources/encoding/Encoder8b10b.vhd
+++ b/sources/encoding/Encoder8b10b.vhd
@@ -1,3 +1,24 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Julia Narevicius
+--! Israel Grayzman
+--! Fabrizio Alfonsi
+--! Nico Giangiacomi
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
--! Company: University and INFN Bologna
--! Engineer: Nico Giangiacomi
diff --git a/sources/encoding/Encoder8b10b_tb.vhd b/sources/encoding/Encoder8b10b_tb.vhd
index 20fce2fed..acc6211df 100644
--- a/sources/encoding/Encoder8b10b_tb.vhd
+++ b/sources/encoding/Encoder8b10b_tb.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
--! Company: University and INFN Bologna
--! Engineer: Nico Giangiacomi
diff --git a/sources/encoding/EncoderFEI4.vhd b/sources/encoding/EncoderFEI4.vhd
index 855e6cc99..0d196dd37 100644
--- a/sources/encoding/EncoderFEI4.vhd
+++ b/sources/encoding/EncoderFEI4.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Frans Schreuder
+--! Nico Giangiacomi
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
--! Company: University of Wuppertal
--! Engineer: Carsten Duelsen <carsten.dulsen@cern.ch>
diff --git a/sources/encoding/EncoderHDLC.vhd b/sources/encoding/EncoderHDLC.vhd
index b04128d91..ee52ae051 100644
--- a/sources/encoding/EncoderHDLC.vhd
+++ b/sources/encoding/EncoderHDLC.vhd
@@ -1,3 +1,26 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Julia Narevicius
+--! Israel Grayzman
+--! Fabrizio Alfonsi
+--! falfonsi
+--! Nico Giangiacomi
+--! Frans Schreuder
+--! Marius Wensing
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
diff --git a/sources/encoding/EncoderTTC.vhd b/sources/encoding/EncoderTTC.vhd
index b64373f47..e74744ccf 100644
--- a/sources/encoding/EncoderTTC.vhd
+++ b/sources/encoding/EncoderTTC.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Kazuki Todome
+--! Nico Giangiacomi
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
--! Company: University and INFN Bologna
--! Engineer: Nico Giangiacomi
diff --git a/sources/encoding/EncodingEgroupGBT.vhd b/sources/encoding/EncodingEgroupGBT.vhd
index 086047837..15d539f24 100644
--- a/sources/encoding/EncodingEgroupGBT.vhd
+++ b/sources/encoding/EncodingEgroupGBT.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Frans Schreuder
+--! Nico Giangiacomi
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company: University of Bologna
-- Engineer: Nico Giangiacomi
diff --git a/sources/encoding/EncodingEgroupLPGBT.vhd b/sources/encoding/EncodingEgroupLPGBT.vhd
index 7bc5c9392..a655b11a5 100644
--- a/sources/encoding/EncodingEgroupLPGBT.vhd
+++ b/sources/encoding/EncodingEgroupLPGBT.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--! Nico Giangiacomi
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
diff --git a/sources/encoding/EncodingEpathGBT.vhd b/sources/encoding/EncodingEpathGBT.vhd
index 952c9782a..ea3c7433a 100644
--- a/sources/encoding/EncodingEpathGBT.vhd
+++ b/sources/encoding/EncodingEpathGBT.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Frans Schreuder
+--! Nico Giangiacomi
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company: University of Bologna
-- Engineer: Nico Giangiacomi
diff --git a/sources/encoding/EncodingEpathGBT_tb.vhd b/sources/encoding/EncodingEpathGBT_tb.vhd
index 6f98963a4..b2f803667 100644
--- a/sources/encoding/EncodingEpathGBT_tb.vhd
+++ b/sources/encoding/EncodingEpathGBT_tb.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Nico Giangiacomi
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
diff --git a/sources/encoding/EncodingEpathLPGBT.vhd b/sources/encoding/EncodingEpathLPGBT.vhd
index 37214d9b2..9e7f74759 100644
--- a/sources/encoding/EncodingEpathLPGBT.vhd
+++ b/sources/encoding/EncodingEpathLPGBT.vhd
@@ -1,3 +1,23 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Frans Schreuder
+--! Nico Giangiacomi
+--! mtrovato
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.axi_stream_package.all;
diff --git a/sources/encoding/EncodingGearBox.vhd b/sources/encoding/EncodingGearBox.vhd
index 9baba3a41..9a57dc837 100644
--- a/sources/encoding/EncodingGearBox.vhd
+++ b/sources/encoding/EncodingGearBox.vhd
@@ -1,3 +1,23 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Nico Giangiacomi
+--! Kazuki Todome
+--! mtrovato
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company: University of Bologna
-- Engineer: Nico Giangiacomi
diff --git a/sources/encoding/ExtendedTestPulse.vhd b/sources/encoding/ExtendedTestPulse.vhd
index e51552147..a9b3317a5 100644
--- a/sources/encoding/ExtendedTestPulse.vhd
+++ b/sources/encoding/ExtendedTestPulse.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Israel Grayzman
+--! Nico Giangiacomi
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: Israel Grayzman (israel.grayzman@weizmann.ac.il)
diff --git a/sources/encoding/FIFO_bit_stuffing.vhd b/sources/encoding/FIFO_bit_stuffing.vhd
index 801a01f57..ed2df1bb0 100644
--- a/sources/encoding/FIFO_bit_stuffing.vhd
+++ b/sources/encoding/FIFO_bit_stuffing.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! falfonsi
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
-------------------------------------------------------
--! @file
--! @author Julian Mendez <julian.mendez@cern.ch> (CERN - EP-ESE-BE)
diff --git a/sources/encoding/enc_8b10b.vhd b/sources/encoding/enc_8b10b.vhd
index 91fbcf946..b212229a8 100644
--- a/sources/encoding/enc_8b10b.vhd
+++ b/sources/encoding/enc_8b10b.vhd
@@ -1,3 +1,22 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Israel Grayzman
+--! Nico Giangiacomi
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
-- Chuck Benz, Hollis, NH Copyright (c)2002
--
-- The information and description contained herein is the
diff --git a/sources/encoding/encoding.vhd b/sources/encoding/encoding.vhd
index b0a67516b..b4218dea5 100644
--- a/sources/encoding/encoding.vhd
+++ b/sources/encoding/encoding.vhd
@@ -1,3 +1,24 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Marius Wensing
+--! Nico Giangiacomi
+--! Elena Zhivun
+--! mtrovato
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
diff --git a/sources/encoding/fifo_v1.vhd b/sources/encoding/fifo_v1.vhd
index 430ca796a..485d9f76f 100644
--- a/sources/encoding/fifo_v1.vhd
+++ b/sources/encoding/fifo_v1.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! falfonsi
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
-- This file is part of VHDL-FIFO.
--
-- VHDL-FIFO is free software: you can redistribute it and/or modify
diff --git a/sources/spi/spi_master.vhd b/sources/spi/spi_master.vhd
index 033da2d23..60ce180bc 100644
--- a/sources/spi/spi_master.vhd
+++ b/sources/spi/spi_master.vhd
@@ -1,619 +1,620 @@
------------------------------------------------------------------------------------------------------------------------
--- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
---
--- Create Date: 12:18:12 04/25/2011
--- Module Name: SPI_MASTER - RTL
--- Project Name: SPI MASTER / SLAVE INTERFACE
--- Target Devices: Spartan-6
--- Tool versions: ISE 13.1
--- Description:
---
--- This block is the SPI master interface, implemented in one single entity.
--- All internal core operations are synchronous to the 'sclk_i', and a spi base clock is generated by dividing sclk_i downto
--- a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
--- All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
--- 'sclk_i' clock.
--- For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line.
--- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
--- clock domains.
--- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
--- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), lookahead prefetch signaling
--- ('PREFETCH'), and spi base clock division from sclk_i ('SPI_2X_CLK_DIV').
---
--- SPI CLOCK GENERATION
--- ====================
---
--- The clock generation for the SPI SCK is derived from the high-speed 'sclk_i' clock. The core divides this reference
--- clock to form the SPI base clock, by the 'SPI_2X_CLK_DIV' generic parameter. The user must set the divider value for the
--- SPI_2X clock, which is 2x the desired SCK frequency.
--- All registers in the core are clocked by the high-speed clocks, and clock enables are used to run the FSM and other logic
--- at lower rates. This architecture preserves FPGA clock resources like global clock buffers, and avoids path delays caused
--- by combinatorial clock dividers outputs.
--- The core has async clock domain circuitry to handle asynchronous clocks for the SPI and parallel interfaces.
---
--- PARALLEL WRITE INTERFACE
--- ========================
--- The parallel interface has an input port 'di_i' and an output port 'do_o'.
--- Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. 'di_req_o' is a look ahead data request line,
--- that is set 'PREFETCH' clock cycles in advance to synchronize a pipelined memory or fifo to present the
--- next input data at 'di_i' in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
--- For a pipelined sync RAM, a PREFETCH of 2 cycles allows an address generator to present the new adress to the RAM in one
--- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the shifter.
--- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
--- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last SPI clock cycle,
--- if continuous transmission is intended. If 'wren_i' is not valid 2 SPI clock cycles after the last transmitted bit, the interface
--- enters idle state and deasserts SSEL.
--- When the interface is idle, 'wren_i' write strobe loads the data and starts transmission. 'di_req_o' will strobe when entering
--- idle state, if a previously loaded data has already been transferred.
---
--- PARALLEL WRITE SEQUENCE
--- =======================
--- __ __ __ __ __ __ __
--- pclk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- parallel interface clock
--- ___________
--- di_req_o ________/ \_____________________... -- 'di_req_o' asserted on rising edge of 'pclk_i'
--- ______________ ___________________________...
--- di_i __old_data____X______new_data_____________... -- user circuit loads data on 'di_i' at next 'pclk_i' rising edge
--- _______
--- wren_i __________________________/ \_______... -- user strobes 'wren_i' for one cycle of 'pclk_i'
---
---
--- PARALLEL READ INTERFACE
--- =======================
--- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received,
--- the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_clk'.
--- The signal 'do_valid_o' is set one 'spi_clk' clock after, to directly drive a synchronous memory or fifo write enable.
--- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'pclk_i'.
--- When the interface is idle, data at the 'do_o' port holds the last word received.
---
--- PARALLEL READ SEQUENCE
--- ======================
--- ______ ______ ______ ______
--- spi_clk bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- internal spi 2x base clock
--- _ __ __ __ __ __ __ __ __
--- pclk_i \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock (may be async to sclk_i)
--- _____________ _____________________________________... -- 1) rx data is transferred to 'do_buffer_reg'
--- do_o ___old_data__X__________new_data___________________... -- after last rx bit, at rising 'spi_clk'.
--- ____________
--- do_valid_o ____________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'pclk_i' cycles
--- -- on the 3rd 'pclk_i' rising edge.
---
---
--- The propagation delay of spi_sck_o and spi_mosi_o, referred to the internal clock, is balanced by similar path delays,
--- but the sampling delay of spi_miso_i imposes a setup time referred to the sck signal that limits the high frequency
--- of the interface, for full duplex operation.
---
--- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
--- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
---
------------------------------- COPYRIGHT NOTICE -----------------------------------------------------------------------
---
--- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
---
--- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
---
--- Copyright (C) 2011 Jonny Doin
--- -----------------------------
---
--- This source file may be used and distributed without restriction provided that this copyright statement is not
--- removed from the file and that any derivative work contains the original copyright notice and the associated
--- disclaimer.
---
--- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
--- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
--- (at your option) any later version.
---
--- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
--- details.
---
--- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
--- it from http://www.gnu.org/licenses/lgpl.txt
---
------------------------------- REVISION HISTORY -----------------------------------------------------------------------
---
--- 2011/04/28 v0.01.0010 [JD] shifter implemented as a sequential process. timing problems and async issues in synthesis.
--- 2011/05/01 v0.01.0030 [JD] changed original shifter design to a fully pipelined RTL fsmd. solved all synthesis issues.
--- 2011/05/05 v0.01.0034 [JD] added an internal buffer register for rx_data, to allow greater liberty in data load/store.
--- 2011/05/08 v0.10.0038 [JD] increased one state to have SSEL start one cycle before SCK. Implemented full CPOL/CPHA
--- logic, based on generics, and do_valid_o signal.
--- 2011/05/13 v0.20.0045 [JD] streamlined signal names, added PREFETCH parameter, added assertions.
--- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries.
--- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core.
--- 2011/06/05 v0.96.0053 [JD] changed async clear to sync resets.
--- 2011/06/07 v0.97.0065 [JD] added cross-clock buffers, fixed fsm async glitches.
--- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
--- synthesis LUT overhead in Spartan-6 architecture.
--- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
--- 2011/06/12 v0.97.0079 [JD] streamlined wr_ack for all cases and eliminated unnecessary register resets.
--- 2011/06/14 v0.97.0083 [JD] (bug CPHA effect) : redesigned SCK output circuit.
--- (minor bug) : removed fsm registers from (not rst_i) chip enable.
--- 2011/06/15 v0.97.0086 [JD] removed master MISO input register, to relax MISO data setup time (to get higher speed).
--- 2011/07/09 v1.00.0095 [JD] changed all clocking scheme to use a single high-speed clock with clock enables to control lower
--- frequency sequential circuits, to preserve clocking resources and avoid path delay glitches.
--- 2011/07/10 v1.00.0098 [JD] implemented SCK clock divider circuit to generate spi clock directly from system clock.
--- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz,
--- 7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
--- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
--- 2011/07/17 v1.11.0080 [JD] BUG: CPOL='1', CPHA='1' @50MHz causes MOSI to be shifted one bit earlier.
--- BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end.
--- 2011/07/18 v1.12.0105 [JD] CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'.
--- for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz.
--- 2011/07/24 v1.13.0125 [JD] FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches.
--- Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz.
--- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
--- for each state, to avoid reported inference problems in some synthesis engines.
--- Streamlined port names and indentation blocks.
--- 2011/08/01 v1.15.0135 [JD] Fixed latch inference for spi_mosi_o driver at the fsm.
--- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
--- 2011/08/04 v1.15.0136 [JD] Fixed assertions (PREFETCH >= 1) and minor comment bugs.
---
------------------------------------------------------------------------------------------------------------------------
--- TODO
--- ====
---
------------------------------------------------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-
---================================================================================================================
--- SYNTHESIS CONSIDERATIONS
--- ========================
--- There are several output ports that are used to simulate and verify the core operation.
--- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
--- circuitry.
--- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
--- synthesis tool will remove the receive logic from the generated circuitry.
--- Alternatively, you can remove these ports and related circuitry once the core is verified and
--- integrated to your circuit.
---================================================================================================================
-
-entity spi_master is
- Generic (
- N : positive := 32; -- 32bit serial word length is default
- CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
- CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
- PREFETCH : positive := 2; -- prefetch lookahead cycles
- SPI_2X_CLK_DIV : positive := 5); -- for a 100MHz sclk_i, yields a 10MHz SCK
- Port (
- sclk_i : in std_logic := 'X'; -- high-speed serial interface system clock
- pclk_i : in std_logic := 'X'; -- high-speed parallel interface system clock
- rst_i : in std_logic := 'X'; -- reset core
- ---- serial interface ----
- spi_ssel_o : out std_logic; -- spi bus slave select line
- spi_sck_o : out std_logic; -- spi bus sck
- spi_mosi_o : out std_logic; -- spi bus mosi output
- spi_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
- ---- parallel interface ----
- di_req_o : out std_logic; -- preload lookahead data request line
- di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit)
- wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle
- wr_ack_o : out std_logic; -- write acknowledge
- do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge.
- do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked on rising spi_clk after last bit)
- --- debug ports: can be removed or left unconnected for the application circuit ---
- sck_ena_o : out std_logic; -- debug: internal sck enable signal
- sck_ena_ce_o : out std_logic; -- debug: internal sck clock enable signal
- do_transfer_o : out std_logic; -- debug: internal transfer driver
- wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
- rx_bit_reg_o : out std_logic; -- debug: internal rx bit
- state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
- core_clk_o : out std_logic;
- core_n_clk_o : out std_logic;
- core_ce_o : out std_logic;
- core_n_ce_o : out std_logic;
- sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
- );
-end spi_master;
-
---================================================================================================================
--- this architecture is a pipelined register-transfer description.
--- all signals are clocked at the rising edge of the system clock 'sclk_i'.
---================================================================================================================
-architecture rtl of spi_master is
- -- core clocks, generated from 'sclk_i': initialized at GSR to differential values
- signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
- signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
- signal core_ce : std_logic := '0'; -- core clock enable, positive logic
- signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
- -- spi bus clock, generated from the CPOL selected core clock polarity
- signal spi_2x_ce : std_logic := '1'; -- spi_2x clock enable
- signal spi_clk : std_logic := '0'; -- spi bus output clock
- signal spi_clk_reg : std_logic; -- output pipeline delay for spi sck (do NOT global initialize)
- -- core fsm clock enables
- signal fsm_ce : std_logic := '1'; -- fsm clock enable
- signal sck_ena_ce : std_logic := '1'; -- SCK clock enable
- signal samp_ce : std_logic := '1'; -- data sampling clock enable
- --
- -- GLOBAL RESET:
- -- all signals are initialized to zero at GSR (global set/reset) by giving explicit
- -- initialization values at declaration. This is needed for all Xilinx FPGAs, and
- -- especially for the Spartan-6 and newer CLB architectures, where a async reset can
- -- reduce the usability of the slice registers, due to the need to share the control
- -- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
- -- By using GSR for the initialization, and reducing async RESET local init to the bare
- -- essential, the model achieves better LUT/FF packing and CLB usability.
- --
- -- internal state signals for register and combinatorial stages
- signal state_next : natural range N+1 downto 0 := 0;
- signal state_reg : natural range N+1 downto 0 := 0;
- -- shifter signals for register and combinatorial stages
- signal sh_next : std_logic_vector (N-1 downto 0);
- signal sh_reg : std_logic_vector (N-1 downto 0);
- -- input bit sampled buffer
- signal rx_bit_reg : std_logic := '0';
- -- buffered di_i data signals for register and combinatorial stages
- signal di_reg : std_logic_vector (N-1 downto 0);
- -- internal wren_i stretcher for fsm combinatorial stage
- signal wren : std_logic;
- signal wr_ack_next : std_logic := '0';
- signal wr_ack_reg : std_logic := '0';
- -- internal SSEL enable control signals
- signal ssel_ena_next : std_logic := '0';
- signal ssel_ena_reg : std_logic := '0';
- -- internal SCK enable control signals
- signal sck_ena_next : std_logic;
- signal sck_ena_reg : std_logic;
- -- buffered do_o data signals for register and combinatorial stages
- signal do_buffer_next : std_logic_vector (N-1 downto 0);
- signal do_buffer_reg : std_logic_vector (N-1 downto 0);
- -- internal signal to flag transfer to do_buffer_reg
- signal do_transfer_next : std_logic := '0';
- signal do_transfer_reg : std_logic := '0';
- -- internal input data request signal
- signal di_req_next : std_logic := '0';
- signal di_req_reg : std_logic := '0';
- -- cross-clock do_transfer_reg -> do_valid_o_reg pipeline
- signal do_valid_A : std_logic := '0';
- signal do_valid_B : std_logic := '0';
- signal do_valid_C : std_logic := '0';
- signal do_valid_D : std_logic := '0';
- signal do_valid_next : std_logic := '0';
- signal do_valid_o_reg : std_logic := '0';
- -- cross-clock di_req_reg -> di_req_o_reg pipeline
- signal di_req_o_A : std_logic := '0';
- signal di_req_o_B : std_logic := '0';
- signal di_req_o_C : std_logic := '0';
- signal di_req_o_D : std_logic := '0';
- signal di_req_o_next : std_logic := '1';
- signal di_req_o_reg : std_logic := '1';
-begin
- --=============================================================================================
- -- GENERICS CONSTRAINTS CHECKING
- --=============================================================================================
- -- minimum word width is 8 bits
- assert N >= 8
- report "Generic parameter 'N' (shift register size) needs to be 8 bits minimum"
- severity FAILURE;
- -- minimum prefetch lookahead check
- assert PREFETCH >= 1
- report "Generic parameter 'PREFETCH' (lookahead count) needs to be 1 minimum"
- severity FAILURE;
- -- maximum prefetch lookahead check
- assert PREFETCH <= N-5
- report "Generic parameter 'PREFETCH' (lookahead count) out of range, needs to be N-5 maximum"
- severity FAILURE;
- -- SPI_2X_CLK_DIV clock divider value must not be zero
- assert SPI_2X_CLK_DIV > 0
- report "Generic parameter 'SPI_2X_CLK_DIV' must not be zero"
- severity FAILURE;
-
- --=============================================================================================
- -- CLOCK GENERATION
- --=============================================================================================
- -- In order to preserve global clocking resources, the core clocking scheme is completely based
- -- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
- -- the spi clock generator and the input sampling clock.
- -- The clock generation block derives 2 continuous antiphase signals from the 2x spi base clock
- -- for the core clocking.
- -- The 2 clock phases are generated by separate and synchronous FFs, and should have only
- -- differential interconnect delay skew.
- -- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock
- -- enables are used to control clocking of all internal synchronous circuitry.
- -- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
- -- based on the configuration of CPOL and CPHA.
- -- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
- -- modes, by a single high-speed global clock, preserving clock resources and clock to data skew.
- -----------------------------------------------------------------------------------------------
- -- generate the 2x spi base clock enable from the serial high-speed input clock
- spi_2x_ce_gen_proc: process (sclk_i) is
- variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0 := 0;
- begin
- if sclk_i'event and sclk_i = '1' then
- if clk_cnt = SPI_2X_CLK_DIV-1 then
- spi_2x_ce <= '1';
- clk_cnt := 0;
- else
- spi_2x_ce <= '0';
- clk_cnt := clk_cnt + 1;
- end if;
- end if;
- end process spi_2x_ce_gen_proc;
- -----------------------------------------------------------------------------------------------
- -- generate the core antiphase clocks and clock enables from the 2x base CE.
- core_clock_gen_proc : process (sclk_i) is
- begin
- if sclk_i'event and sclk_i = '1' then
- if spi_2x_ce = '1' then
- -- generate the 2 antiphase core clocks
- core_clk <= core_n_clk;
- core_n_clk <= not core_n_clk;
- -- generate the 2 phase core clock enables
- core_ce <= core_n_clk;
- core_n_ce <= not core_n_clk;
- else
- core_ce <= '0';
- core_n_ce <= '0';
- end if;
- end if;
- end process core_clock_gen_proc;
-
- --=============================================================================================
- -- GENERATE BLOCKS
- --=============================================================================================
- -- spi clk generator: generate spi_clk from core_clk depending on CPOL
- spi_sck_cpol_0_proc: if CPOL = '0' generate
- begin
- spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW
- end generate;
-
- spi_sck_cpol_1_proc: if CPOL = '1' generate
- begin
- spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
- end generate;
- -----------------------------------------------------------------------------------------------
- -- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
- -- always sample data at the half-cycle of the fsm update cell
- samp_ce_cpha_0_proc: if CPHA = '0' generate
- begin
- samp_ce <= core_ce;
- end generate;
-
- samp_ce_cpha_1_proc: if CPHA = '1' generate
- begin
- samp_ce <= core_n_ce;
- end generate;
- -----------------------------------------------------------------------------------------------
- -- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
- fsm_ce_cpha_0_proc: if CPHA = '0' generate
- begin
- fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable
- end generate;
-
- fsm_ce_cpha_1_proc: if CPHA = '1' generate
- begin
- fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
- end generate;
- -----------------------------------------------------------------------------------------------
- -- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock
- sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
-
- --=============================================================================================
- -- REGISTERED INPUTS
- --=============================================================================================
- -- rx bit flop: capture rx bit after SAMPLE edge of sck
- rx_bit_proc : process (sclk_i, spi_miso_i) is
- begin
- if sclk_i'event and sclk_i = '1' then
- if samp_ce = '1' then
- rx_bit_reg <= spi_miso_i;
- end if;
- end if;
- end process rx_bit_proc;
-
- --=============================================================================================
- -- CROSS-CLOCK PIPELINE TRANSFER LOGIC
- --=============================================================================================
- -- do_valid_o and di_req_o strobe output logic
- -- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a
- -- fixed-length delayed pulse for the output flags, at the parallel clock domain
- out_transfer_proc : process ( pclk_i, do_transfer_reg, di_req_reg,
- do_valid_A, do_valid_B, do_valid_D,
- di_req_o_A, di_req_o_B, di_req_o_D ) is
- begin
- if pclk_i'event and pclk_i = '1' then -- clock at parallel port clock
- -- do_transfer_reg -> do_valid_o_reg
- do_valid_A <= do_transfer_reg; -- the input signal must be at least 2 clocks long
- do_valid_B <= do_valid_A; -- feed it to a ripple chain of FFDs
- do_valid_C <= do_valid_B;
- do_valid_D <= do_valid_C;
- do_valid_o_reg <= do_valid_next; -- registered output pulse
- --------------------------------
- -- di_req_reg -> di_req_o_reg
- di_req_o_A <= di_req_reg; -- the input signal must be at least 2 clocks long
- di_req_o_B <= di_req_o_A; -- feed it to a ripple chain of FFDs
- di_req_o_C <= di_req_o_B;
- di_req_o_D <= di_req_o_C;
- di_req_o_reg <= di_req_o_next; -- registered output pulse
- end if;
- -- generate a 2-clocks pulse at the 3rd clock cycle
- do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
- di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
- end process out_transfer_proc;
- -- parallel load input registers: data register and write enable
- in_transfer_proc: process ( pclk_i, wren_i, wr_ack_reg ) is
- begin
- -- registered data input, input register with clock enable
- if pclk_i'event and pclk_i = '1' then
- if wren_i = '1' then
- di_reg <= di_i; -- parallel data input buffer register
- end if;
- end if;
- -- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
- if pclk_i'event and pclk_i = '1' then
- if wren_i = '1' then -- wren_i is the sync preset for wren
- wren <= '1';
- elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren
- wren <= '0';
- end if;
- end if;
- end process in_transfer_proc;
-
- --=============================================================================================
- -- REGISTER TRANSFER PROCESSES
- --=============================================================================================
- -- fsm state and data registers: synchronous to the spi base reference clock
- core_reg_proc : process (sclk_i) is
- begin
- -- FF registers clocked on rising edge and cleared on sync rst_i
- if sclk_i'event and sclk_i = '1' then
- if rst_i = '1' then -- sync reset
- state_reg <= 0; -- only provide local reset for the state machine
- elsif fsm_ce = '1' then -- fsm_ce is clock enable for the fsm
- state_reg <= state_next; -- state register
- end if;
- end if;
- -- FF registers clocked synchronous to the fsm state
- if sclk_i'event and sclk_i = '1' then
- if fsm_ce = '1' then
- sh_reg <= sh_next; -- shift register
- ssel_ena_reg <= ssel_ena_next; -- spi select enable
- do_buffer_reg <= do_buffer_next; -- registered output data buffer
- do_transfer_reg <= do_transfer_next; -- output data transferred to buffer
- di_req_reg <= di_req_next; -- input data request
- wr_ack_reg <= wr_ack_next; -- write acknowledge for data load synchronization
- end if;
- end if;
- -- FF registers clocked one-half cycle earlier than the fsm state
- if sclk_i'event and sclk_i = '1' then
- if sck_ena_ce = '1' then
- sck_ena_reg <= sck_ena_next; -- spi clock enable: look ahead logic
- end if;
- end if;
- end process core_reg_proc;
-
- --=============================================================================================
- -- COMBINATORIAL LOGIC PROCESSES
- --=============================================================================================
- -- state and datapath combinatorial logic
- core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
- do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren ) is
- begin
- sh_next <= sh_reg; -- all output signals are assigned to (avoid latches)
- ssel_ena_next <= ssel_ena_reg; -- controls the slave select line
- sck_ena_next <= sck_ena_reg; -- controls the clock enable of spi sck line
- do_buffer_next <= do_buffer_reg; -- output data buffer
- do_transfer_next <= do_transfer_reg; -- output data flag
- wr_ack_next <= wr_ack_reg; -- write acknowledge
- di_req_next <= di_req_reg; -- prefetch data request
- spi_mosi_o <= sh_reg(N-1); -- default to avoid latch inference
- state_next <= state_reg; -- next state
- case state_reg is
-
- when (N+1) => -- this state is to enable SSEL before SCK
- spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
- ssel_ena_next <= '1'; -- tx in progress: will assert SSEL
- sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle)
- di_req_next <= '0'; -- prefetch data request: deassert when shifting data
- wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
- state_next <= state_reg - 1; -- update next state at each sck pulse
-
- when (N) => -- deassert 'di_rdy' and stretch do_valid
- spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
- di_req_next <= '0'; -- prefetch data request: deassert when shifting data
- sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
- sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
- wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
- state_next <= state_reg - 1; -- update next state at each sck pulse
-
- when (N-1) downto (PREFETCH+3) => -- remove 'do_transfer' and shift bits
- spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
- di_req_next <= '0'; -- prefetch data request: deassert when shifting data
- do_transfer_next <= '0'; -- reset 'do_valid' transfer signal
- sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
- sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
- wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
- state_next <= state_reg - 1; -- update next state at each sck pulse
-
- when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o' signal
- spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
- di_req_next <= '1'; -- request data in advance to allow for pipeline delays
- sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
- sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
- wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
- state_next <= state_reg - 1; -- update next state at each sck pulse
-
- when 1 => -- transfer rx data to do_buffer and restart if new data is written
- spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
- di_req_next <= '1'; -- request data in advance to allow for pipeline delays
- do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer
- do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer
- do_transfer_next <= '1'; -- signal transfer to do_buffer
- if wren = '1' then -- load tx register if valid data present at di_i
- state_next <= N; -- next state is top bit of new data
- sh_next <= di_reg; -- load parallel data from di_reg into shifter
- sck_ena_next <= '1'; -- SCK enabled
- wr_ack_next <= '1'; -- acknowledge data in transfer
- else
- sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
- wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
- state_next <= state_reg - 1; -- update next state at each sck pulse
- end if;
-
- when 0 => -- idle state: start and end of transmission
- di_req_next <= '1'; -- will request data if shifter empty
- sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
- if wren = '1' then -- load tx register if valid data present at di_i
- spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
- ssel_ena_next <= '1'; -- enable interface SSEL
- state_next <= N+1; -- start from idle: let one cycle for SSEL settling
- sh_next <= di_reg; -- load bits from di_reg into shifter
- wr_ack_next <= '1'; -- acknowledge data in transfer
- else
- spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
- ssel_ena_next <= '0'; -- deassert SSEL: interface is idle
- wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
- state_next <= 0; -- when idle, keep this state
- end if;
-
- when others =>
- state_next <= 0; -- state 0 is safe state
- end case;
- end process core_combi_proc;
-
- --=============================================================================================
- -- OUTPUT LOGIC PROCESSES
- --=============================================================================================
- -- data output processes
- spi_ssel_o_proc: spi_ssel_o <= not ssel_ena_reg; -- active-low slave select line
- do_o_proc: do_o <= do_buffer_reg; -- parallel data out
- do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- data out valid
- di_req_o_proc: di_req_o <= di_req_o_reg; -- input data request for next cycle
- wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- write acknowledge
- -----------------------------------------------------------------------------------------------
- -- SCK out logic: pipeline phase compensation for the SCK line
- -----------------------------------------------------------------------------------------------
- -- This is a MUX with an output register.
- -- The register gives us a pipeline delay for the SCK line, pairing with the state machine moore
- -- output pipeline delay for the MOSI line, and thus enabling higher SCK frequency.
- spi_sck_o_gen_proc : process (sclk_i, sck_ena_reg, spi_clk, spi_clk_reg) is
- begin
- if sclk_i'event and sclk_i = '1' then
- if sck_ena_reg = '1' then
- spi_clk_reg <= spi_clk; -- copy the selected clock polarity
- else
- spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity
- end if;
- end if;
- spi_sck_o <= spi_clk_reg; -- connect register to output
- end process spi_sck_o_gen_proc;
-
- --=============================================================================================
- -- DEBUG LOGIC PROCESSES
- --=============================================================================================
- -- these signals are useful for verification, and can be deleted after debug.
- do_transfer_proc: do_transfer_o <= do_transfer_reg;
- state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4));
- rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg;
- wren_o_proc: wren_o <= wren;
- sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg;
- core_clk_o_proc: core_clk_o <= core_clk;
- core_n_clk_o_proc: core_n_clk_o <= core_n_clk;
- core_ce_o_proc: core_ce_o <= core_ce;
- core_n_ce_o_proc: core_n_ce_o <= core_n_ce;
- sck_ena_o_proc: sck_ena_o <= sck_ena_reg;
- sck_ena_ce_o_proc: sck_ena_ce_o <= sck_ena_ce;
-
-end architecture rtl;
+-----------------------------------------------------------------------------------------------------------------------
+-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
+--
+-- Create Date: 12:18:12 04/25/2011
+-- Module Name: SPI_MASTER - RTL
+-- Project Name: SPI MASTER / SLAVE INTERFACE
+-- Target Devices: Spartan-6
+-- Tool versions: ISE 13.1
+-- Description:
+--
+-- This block is the SPI master interface, implemented in one single entity.
+-- All internal core operations are synchronous to the 'sclk_i', and a spi base clock is generated by dividing sclk_i downto
+-- a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
+-- All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
+-- 'sclk_i' clock.
+-- For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line.
+-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
+-- clock domains.
+-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
+-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), lookahead prefetch signaling
+-- ('PREFETCH'), and spi base clock division from sclk_i ('SPI_2X_CLK_DIV').
+--
+-- SPI CLOCK GENERATION
+-- ====================
+--
+-- The clock generation for the SPI SCK is derived from the high-speed 'sclk_i' clock. The core divides this reference
+-- clock to form the SPI base clock, by the 'SPI_2X_CLK_DIV' generic parameter. The user must set the divider value for the
+-- SPI_2X clock, which is 2x the desired SCK frequency.
+-- All registers in the core are clocked by the high-speed clocks, and clock enables are used to run the FSM and other logic
+-- at lower rates. This architecture preserves FPGA clock resources like global clock buffers, and avoids path delays caused
+-- by combinatorial clock dividers outputs.
+-- The core has async clock domain circuitry to handle asynchronous clocks for the SPI and parallel interfaces.
+--
+-- PARALLEL WRITE INTERFACE
+-- ========================
+-- The parallel interface has an input port 'di_i' and an output port 'do_o'.
+-- Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. 'di_req_o' is a look ahead data request line,
+-- that is set 'PREFETCH' clock cycles in advance to synchronize a pipelined memory or fifo to present the
+-- next input data at 'di_i' in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
+-- For a pipelined sync RAM, a PREFETCH of 2 cycles allows an address generator to present the new adress to the RAM in one
+-- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the shifter.
+-- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
+-- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last SPI clock cycle,
+-- if continuous transmission is intended. If 'wren_i' is not valid 2 SPI clock cycles after the last transmitted bit, the interface
+-- enters idle state and deasserts SSEL.
+-- When the interface is idle, 'wren_i' write strobe loads the data and starts transmission. 'di_req_o' will strobe when entering
+-- idle state, if a previously loaded data has already been transferred.
+--
+-- PARALLEL WRITE SEQUENCE
+-- =======================
+-- __ __ __ __ __ __ __
+-- pclk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- parallel interface clock
+-- ___________
+-- di_req_o ________/ \_____________________... -- 'di_req_o' asserted on rising edge of 'pclk_i'
+-- ______________ ___________________________...
+-- di_i __old_data____X______new_data_____________... -- user circuit loads data on 'di_i' at next 'pclk_i' rising edge
+-- _______
+-- wren_i __________________________/ \_______... -- user strobes 'wren_i' for one cycle of 'pclk_i'
+--
+--
+-- PARALLEL READ INTERFACE
+-- =======================
+-- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received,
+-- the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_clk'.
+-- The signal 'do_valid_o' is set one 'spi_clk' clock after, to directly drive a synchronous memory or fifo write enable.
+-- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'pclk_i'.
+-- When the interface is idle, data at the 'do_o' port holds the last word received.
+--
+-- PARALLEL READ SEQUENCE
+-- ======================
+-- ______ ______ ______ ______
+-- spi_clk bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- internal spi 2x base clock
+-- _ __ __ __ __ __ __ __ __
+-- pclk_i \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock (may be async to sclk_i)
+-- _____________ _____________________________________... -- 1) rx data is transferred to 'do_buffer_reg'
+-- do_o ___old_data__X__________new_data___________________... -- after last rx bit, at rising 'spi_clk'.
+-- ____________
+-- do_valid_o ____________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'pclk_i' cycles
+-- -- on the 3rd 'pclk_i' rising edge.
+--
+--
+-- The propagation delay of spi_sck_o and spi_mosi_o, referred to the internal clock, is balanced by similar path delays,
+-- but the sampling delay of spi_miso_i imposes a setup time referred to the sck signal that limits the high frequency
+-- of the interface, for full duplex operation.
+--
+-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
+-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
+--
+------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
+--
+-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
+--
+-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
+--
+-- Copyright (C) 2011 Jonny Doin
+-- -----------------------------
+--
+-- This source file may be used and distributed without restriction provided that this copyright statement is not
+-- removed from the file and that any derivative work contains the original copyright notice and the associated
+-- disclaimer.
+--
+-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
+-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
+-- (at your option) any later version.
+--
+-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
+-- it from http://www.gnu.org/licenses/lgpl.txt
+--
+-- Unlike FELIX, this file is not Licensed under the Apache License, but it is not included in the FELIX project anymore
+------------------------------ REVISION HISTORY -----------------------------------------------------------------------
+--
+-- 2011/04/28 v0.01.0010 [JD] shifter implemented as a sequential process. timing problems and async issues in synthesis.
+-- 2011/05/01 v0.01.0030 [JD] changed original shifter design to a fully pipelined RTL fsmd. solved all synthesis issues.
+-- 2011/05/05 v0.01.0034 [JD] added an internal buffer register for rx_data, to allow greater liberty in data load/store.
+-- 2011/05/08 v0.10.0038 [JD] increased one state to have SSEL start one cycle before SCK. Implemented full CPOL/CPHA
+-- logic, based on generics, and do_valid_o signal.
+-- 2011/05/13 v0.20.0045 [JD] streamlined signal names, added PREFETCH parameter, added assertions.
+-- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries.
+-- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core.
+-- 2011/06/05 v0.96.0053 [JD] changed async clear to sync resets.
+-- 2011/06/07 v0.97.0065 [JD] added cross-clock buffers, fixed fsm async glitches.
+-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
+-- synthesis LUT overhead in Spartan-6 architecture.
+-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
+-- 2011/06/12 v0.97.0079 [JD] streamlined wr_ack for all cases and eliminated unnecessary register resets.
+-- 2011/06/14 v0.97.0083 [JD] (bug CPHA effect) : redesigned SCK output circuit.
+-- (minor bug) : removed fsm registers from (not rst_i) chip enable.
+-- 2011/06/15 v0.97.0086 [JD] removed master MISO input register, to relax MISO data setup time (to get higher speed).
+-- 2011/07/09 v1.00.0095 [JD] changed all clocking scheme to use a single high-speed clock with clock enables to control lower
+-- frequency sequential circuits, to preserve clocking resources and avoid path delay glitches.
+-- 2011/07/10 v1.00.0098 [JD] implemented SCK clock divider circuit to generate spi clock directly from system clock.
+-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz,
+-- 7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
+-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
+-- 2011/07/17 v1.11.0080 [JD] BUG: CPOL='1', CPHA='1' @50MHz causes MOSI to be shifted one bit earlier.
+-- BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end.
+-- 2011/07/18 v1.12.0105 [JD] CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'.
+-- for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz.
+-- 2011/07/24 v1.13.0125 [JD] FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches.
+-- Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz.
+-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
+-- for each state, to avoid reported inference problems in some synthesis engines.
+-- Streamlined port names and indentation blocks.
+-- 2011/08/01 v1.15.0135 [JD] Fixed latch inference for spi_mosi_o driver at the fsm.
+-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
+-- 2011/08/04 v1.15.0136 [JD] Fixed assertions (PREFETCH >= 1) and minor comment bugs.
+--
+-----------------------------------------------------------------------------------------------------------------------
+-- TODO
+-- ====
+--
+-----------------------------------------------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+
+--================================================================================================================
+-- SYNTHESIS CONSIDERATIONS
+-- ========================
+-- There are several output ports that are used to simulate and verify the core operation.
+-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
+-- circuitry.
+-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
+-- synthesis tool will remove the receive logic from the generated circuitry.
+-- Alternatively, you can remove these ports and related circuitry once the core is verified and
+-- integrated to your circuit.
+--================================================================================================================
+
+entity spi_master is
+ Generic (
+ N : positive := 32; -- 32bit serial word length is default
+ CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
+ CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
+ PREFETCH : positive := 2; -- prefetch lookahead cycles
+ SPI_2X_CLK_DIV : positive := 5); -- for a 100MHz sclk_i, yields a 10MHz SCK
+ Port (
+ sclk_i : in std_logic := 'X'; -- high-speed serial interface system clock
+ pclk_i : in std_logic := 'X'; -- high-speed parallel interface system clock
+ rst_i : in std_logic := 'X'; -- reset core
+ ---- serial interface ----
+ spi_ssel_o : out std_logic; -- spi bus slave select line
+ spi_sck_o : out std_logic; -- spi bus sck
+ spi_mosi_o : out std_logic; -- spi bus mosi output
+ spi_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
+ ---- parallel interface ----
+ di_req_o : out std_logic; -- preload lookahead data request line
+ di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit)
+ wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle
+ wr_ack_o : out std_logic; -- write acknowledge
+ do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge.
+ do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked on rising spi_clk after last bit)
+ --- debug ports: can be removed or left unconnected for the application circuit ---
+ sck_ena_o : out std_logic; -- debug: internal sck enable signal
+ sck_ena_ce_o : out std_logic; -- debug: internal sck clock enable signal
+ do_transfer_o : out std_logic; -- debug: internal transfer driver
+ wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
+ rx_bit_reg_o : out std_logic; -- debug: internal rx bit
+ state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
+ core_clk_o : out std_logic;
+ core_n_clk_o : out std_logic;
+ core_ce_o : out std_logic;
+ core_n_ce_o : out std_logic;
+ sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
+ );
+end spi_master;
+
+--================================================================================================================
+-- this architecture is a pipelined register-transfer description.
+-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
+--================================================================================================================
+architecture rtl of spi_master is
+ -- core clocks, generated from 'sclk_i': initialized at GSR to differential values
+ signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
+ signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
+ signal core_ce : std_logic := '0'; -- core clock enable, positive logic
+ signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
+ -- spi bus clock, generated from the CPOL selected core clock polarity
+ signal spi_2x_ce : std_logic := '1'; -- spi_2x clock enable
+ signal spi_clk : std_logic := '0'; -- spi bus output clock
+ signal spi_clk_reg : std_logic; -- output pipeline delay for spi sck (do NOT global initialize)
+ -- core fsm clock enables
+ signal fsm_ce : std_logic := '1'; -- fsm clock enable
+ signal sck_ena_ce : std_logic := '1'; -- SCK clock enable
+ signal samp_ce : std_logic := '1'; -- data sampling clock enable
+ --
+ -- GLOBAL RESET:
+ -- all signals are initialized to zero at GSR (global set/reset) by giving explicit
+ -- initialization values at declaration. This is needed for all Xilinx FPGAs, and
+ -- especially for the Spartan-6 and newer CLB architectures, where a async reset can
+ -- reduce the usability of the slice registers, due to the need to share the control
+ -- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
+ -- By using GSR for the initialization, and reducing async RESET local init to the bare
+ -- essential, the model achieves better LUT/FF packing and CLB usability.
+ --
+ -- internal state signals for register and combinatorial stages
+ signal state_next : natural range N+1 downto 0 := 0;
+ signal state_reg : natural range N+1 downto 0 := 0;
+ -- shifter signals for register and combinatorial stages
+ signal sh_next : std_logic_vector (N-1 downto 0);
+ signal sh_reg : std_logic_vector (N-1 downto 0);
+ -- input bit sampled buffer
+ signal rx_bit_reg : std_logic := '0';
+ -- buffered di_i data signals for register and combinatorial stages
+ signal di_reg : std_logic_vector (N-1 downto 0);
+ -- internal wren_i stretcher for fsm combinatorial stage
+ signal wren : std_logic;
+ signal wr_ack_next : std_logic := '0';
+ signal wr_ack_reg : std_logic := '0';
+ -- internal SSEL enable control signals
+ signal ssel_ena_next : std_logic := '0';
+ signal ssel_ena_reg : std_logic := '0';
+ -- internal SCK enable control signals
+ signal sck_ena_next : std_logic;
+ signal sck_ena_reg : std_logic;
+ -- buffered do_o data signals for register and combinatorial stages
+ signal do_buffer_next : std_logic_vector (N-1 downto 0);
+ signal do_buffer_reg : std_logic_vector (N-1 downto 0);
+ -- internal signal to flag transfer to do_buffer_reg
+ signal do_transfer_next : std_logic := '0';
+ signal do_transfer_reg : std_logic := '0';
+ -- internal input data request signal
+ signal di_req_next : std_logic := '0';
+ signal di_req_reg : std_logic := '0';
+ -- cross-clock do_transfer_reg -> do_valid_o_reg pipeline
+ signal do_valid_A : std_logic := '0';
+ signal do_valid_B : std_logic := '0';
+ signal do_valid_C : std_logic := '0';
+ signal do_valid_D : std_logic := '0';
+ signal do_valid_next : std_logic := '0';
+ signal do_valid_o_reg : std_logic := '0';
+ -- cross-clock di_req_reg -> di_req_o_reg pipeline
+ signal di_req_o_A : std_logic := '0';
+ signal di_req_o_B : std_logic := '0';
+ signal di_req_o_C : std_logic := '0';
+ signal di_req_o_D : std_logic := '0';
+ signal di_req_o_next : std_logic := '1';
+ signal di_req_o_reg : std_logic := '1';
+begin
+ --=============================================================================================
+ -- GENERICS CONSTRAINTS CHECKING
+ --=============================================================================================
+ -- minimum word width is 8 bits
+ assert N >= 8
+ report "Generic parameter 'N' (shift register size) needs to be 8 bits minimum"
+ severity FAILURE;
+ -- minimum prefetch lookahead check
+ assert PREFETCH >= 1
+ report "Generic parameter 'PREFETCH' (lookahead count) needs to be 1 minimum"
+ severity FAILURE;
+ -- maximum prefetch lookahead check
+ assert PREFETCH <= N-5
+ report "Generic parameter 'PREFETCH' (lookahead count) out of range, needs to be N-5 maximum"
+ severity FAILURE;
+ -- SPI_2X_CLK_DIV clock divider value must not be zero
+ assert SPI_2X_CLK_DIV > 0
+ report "Generic parameter 'SPI_2X_CLK_DIV' must not be zero"
+ severity FAILURE;
+
+ --=============================================================================================
+ -- CLOCK GENERATION
+ --=============================================================================================
+ -- In order to preserve global clocking resources, the core clocking scheme is completely based
+ -- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
+ -- the spi clock generator and the input sampling clock.
+ -- The clock generation block derives 2 continuous antiphase signals from the 2x spi base clock
+ -- for the core clocking.
+ -- The 2 clock phases are generated by separate and synchronous FFs, and should have only
+ -- differential interconnect delay skew.
+ -- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock
+ -- enables are used to control clocking of all internal synchronous circuitry.
+ -- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
+ -- based on the configuration of CPOL and CPHA.
+ -- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
+ -- modes, by a single high-speed global clock, preserving clock resources and clock to data skew.
+ -----------------------------------------------------------------------------------------------
+ -- generate the 2x spi base clock enable from the serial high-speed input clock
+ spi_2x_ce_gen_proc: process (sclk_i) is
+ variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0 := 0;
+ begin
+ if sclk_i'event and sclk_i = '1' then
+ if clk_cnt = SPI_2X_CLK_DIV-1 then
+ spi_2x_ce <= '1';
+ clk_cnt := 0;
+ else
+ spi_2x_ce <= '0';
+ clk_cnt := clk_cnt + 1;
+ end if;
+ end if;
+ end process spi_2x_ce_gen_proc;
+ -----------------------------------------------------------------------------------------------
+ -- generate the core antiphase clocks and clock enables from the 2x base CE.
+ core_clock_gen_proc : process (sclk_i) is
+ begin
+ if sclk_i'event and sclk_i = '1' then
+ if spi_2x_ce = '1' then
+ -- generate the 2 antiphase core clocks
+ core_clk <= core_n_clk;
+ core_n_clk <= not core_n_clk;
+ -- generate the 2 phase core clock enables
+ core_ce <= core_n_clk;
+ core_n_ce <= not core_n_clk;
+ else
+ core_ce <= '0';
+ core_n_ce <= '0';
+ end if;
+ end if;
+ end process core_clock_gen_proc;
+
+ --=============================================================================================
+ -- GENERATE BLOCKS
+ --=============================================================================================
+ -- spi clk generator: generate spi_clk from core_clk depending on CPOL
+ spi_sck_cpol_0_proc: if CPOL = '0' generate
+ begin
+ spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW
+ end generate;
+
+ spi_sck_cpol_1_proc: if CPOL = '1' generate
+ begin
+ spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
+ end generate;
+ -----------------------------------------------------------------------------------------------
+ -- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
+ -- always sample data at the half-cycle of the fsm update cell
+ samp_ce_cpha_0_proc: if CPHA = '0' generate
+ begin
+ samp_ce <= core_ce;
+ end generate;
+
+ samp_ce_cpha_1_proc: if CPHA = '1' generate
+ begin
+ samp_ce <= core_n_ce;
+ end generate;
+ -----------------------------------------------------------------------------------------------
+ -- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
+ fsm_ce_cpha_0_proc: if CPHA = '0' generate
+ begin
+ fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable
+ end generate;
+
+ fsm_ce_cpha_1_proc: if CPHA = '1' generate
+ begin
+ fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
+ end generate;
+ -----------------------------------------------------------------------------------------------
+ -- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock
+ sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
+
+ --=============================================================================================
+ -- REGISTERED INPUTS
+ --=============================================================================================
+ -- rx bit flop: capture rx bit after SAMPLE edge of sck
+ rx_bit_proc : process (sclk_i, spi_miso_i) is
+ begin
+ if sclk_i'event and sclk_i = '1' then
+ if samp_ce = '1' then
+ rx_bit_reg <= spi_miso_i;
+ end if;
+ end if;
+ end process rx_bit_proc;
+
+ --=============================================================================================
+ -- CROSS-CLOCK PIPELINE TRANSFER LOGIC
+ --=============================================================================================
+ -- do_valid_o and di_req_o strobe output logic
+ -- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a
+ -- fixed-length delayed pulse for the output flags, at the parallel clock domain
+ out_transfer_proc : process ( pclk_i, do_transfer_reg, di_req_reg,
+ do_valid_A, do_valid_B, do_valid_D,
+ di_req_o_A, di_req_o_B, di_req_o_D ) is
+ begin
+ if pclk_i'event and pclk_i = '1' then -- clock at parallel port clock
+ -- do_transfer_reg -> do_valid_o_reg
+ do_valid_A <= do_transfer_reg; -- the input signal must be at least 2 clocks long
+ do_valid_B <= do_valid_A; -- feed it to a ripple chain of FFDs
+ do_valid_C <= do_valid_B;
+ do_valid_D <= do_valid_C;
+ do_valid_o_reg <= do_valid_next; -- registered output pulse
+ --------------------------------
+ -- di_req_reg -> di_req_o_reg
+ di_req_o_A <= di_req_reg; -- the input signal must be at least 2 clocks long
+ di_req_o_B <= di_req_o_A; -- feed it to a ripple chain of FFDs
+ di_req_o_C <= di_req_o_B;
+ di_req_o_D <= di_req_o_C;
+ di_req_o_reg <= di_req_o_next; -- registered output pulse
+ end if;
+ -- generate a 2-clocks pulse at the 3rd clock cycle
+ do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
+ di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
+ end process out_transfer_proc;
+ -- parallel load input registers: data register and write enable
+ in_transfer_proc: process ( pclk_i, wren_i, wr_ack_reg ) is
+ begin
+ -- registered data input, input register with clock enable
+ if pclk_i'event and pclk_i = '1' then
+ if wren_i = '1' then
+ di_reg <= di_i; -- parallel data input buffer register
+ end if;
+ end if;
+ -- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
+ if pclk_i'event and pclk_i = '1' then
+ if wren_i = '1' then -- wren_i is the sync preset for wren
+ wren <= '1';
+ elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren
+ wren <= '0';
+ end if;
+ end if;
+ end process in_transfer_proc;
+
+ --=============================================================================================
+ -- REGISTER TRANSFER PROCESSES
+ --=============================================================================================
+ -- fsm state and data registers: synchronous to the spi base reference clock
+ core_reg_proc : process (sclk_i) is
+ begin
+ -- FF registers clocked on rising edge and cleared on sync rst_i
+ if sclk_i'event and sclk_i = '1' then
+ if rst_i = '1' then -- sync reset
+ state_reg <= 0; -- only provide local reset for the state machine
+ elsif fsm_ce = '1' then -- fsm_ce is clock enable for the fsm
+ state_reg <= state_next; -- state register
+ end if;
+ end if;
+ -- FF registers clocked synchronous to the fsm state
+ if sclk_i'event and sclk_i = '1' then
+ if fsm_ce = '1' then
+ sh_reg <= sh_next; -- shift register
+ ssel_ena_reg <= ssel_ena_next; -- spi select enable
+ do_buffer_reg <= do_buffer_next; -- registered output data buffer
+ do_transfer_reg <= do_transfer_next; -- output data transferred to buffer
+ di_req_reg <= di_req_next; -- input data request
+ wr_ack_reg <= wr_ack_next; -- write acknowledge for data load synchronization
+ end if;
+ end if;
+ -- FF registers clocked one-half cycle earlier than the fsm state
+ if sclk_i'event and sclk_i = '1' then
+ if sck_ena_ce = '1' then
+ sck_ena_reg <= sck_ena_next; -- spi clock enable: look ahead logic
+ end if;
+ end if;
+ end process core_reg_proc;
+
+ --=============================================================================================
+ -- COMBINATORIAL LOGIC PROCESSES
+ --=============================================================================================
+ -- state and datapath combinatorial logic
+ core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
+ do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren ) is
+ begin
+ sh_next <= sh_reg; -- all output signals are assigned to (avoid latches)
+ ssel_ena_next <= ssel_ena_reg; -- controls the slave select line
+ sck_ena_next <= sck_ena_reg; -- controls the clock enable of spi sck line
+ do_buffer_next <= do_buffer_reg; -- output data buffer
+ do_transfer_next <= do_transfer_reg; -- output data flag
+ wr_ack_next <= wr_ack_reg; -- write acknowledge
+ di_req_next <= di_req_reg; -- prefetch data request
+ spi_mosi_o <= sh_reg(N-1); -- default to avoid latch inference
+ state_next <= state_reg; -- next state
+ case state_reg is
+
+ when (N+1) => -- this state is to enable SSEL before SCK
+ spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
+ ssel_ena_next <= '1'; -- tx in progress: will assert SSEL
+ sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle)
+ di_req_next <= '0'; -- prefetch data request: deassert when shifting data
+ wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
+ state_next <= state_reg - 1; -- update next state at each sck pulse
+
+ when (N) => -- deassert 'di_rdy' and stretch do_valid
+ spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
+ di_req_next <= '0'; -- prefetch data request: deassert when shifting data
+ sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
+ sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
+ wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
+ state_next <= state_reg - 1; -- update next state at each sck pulse
+
+ when (N-1) downto (PREFETCH+3) => -- remove 'do_transfer' and shift bits
+ spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
+ di_req_next <= '0'; -- prefetch data request: deassert when shifting data
+ do_transfer_next <= '0'; -- reset 'do_valid' transfer signal
+ sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
+ sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
+ wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
+ state_next <= state_reg - 1; -- update next state at each sck pulse
+
+ when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o' signal
+ spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
+ di_req_next <= '1'; -- request data in advance to allow for pipeline delays
+ sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
+ sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
+ wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
+ state_next <= state_reg - 1; -- update next state at each sck pulse
+
+ when 1 => -- transfer rx data to do_buffer and restart if new data is written
+ spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
+ di_req_next <= '1'; -- request data in advance to allow for pipeline delays
+ do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer
+ do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer
+ do_transfer_next <= '1'; -- signal transfer to do_buffer
+ if wren = '1' then -- load tx register if valid data present at di_i
+ state_next <= N; -- next state is top bit of new data
+ sh_next <= di_reg; -- load parallel data from di_reg into shifter
+ sck_ena_next <= '1'; -- SCK enabled
+ wr_ack_next <= '1'; -- acknowledge data in transfer
+ else
+ sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
+ wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
+ state_next <= state_reg - 1; -- update next state at each sck pulse
+ end if;
+
+ when 0 => -- idle state: start and end of transmission
+ di_req_next <= '1'; -- will request data if shifter empty
+ sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
+ if wren = '1' then -- load tx register if valid data present at di_i
+ spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
+ ssel_ena_next <= '1'; -- enable interface SSEL
+ state_next <= N+1; -- start from idle: let one cycle for SSEL settling
+ sh_next <= di_reg; -- load bits from di_reg into shifter
+ wr_ack_next <= '1'; -- acknowledge data in transfer
+ else
+ spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
+ ssel_ena_next <= '0'; -- deassert SSEL: interface is idle
+ wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
+ state_next <= 0; -- when idle, keep this state
+ end if;
+
+ when others =>
+ state_next <= 0; -- state 0 is safe state
+ end case;
+ end process core_combi_proc;
+
+ --=============================================================================================
+ -- OUTPUT LOGIC PROCESSES
+ --=============================================================================================
+ -- data output processes
+ spi_ssel_o_proc: spi_ssel_o <= not ssel_ena_reg; -- active-low slave select line
+ do_o_proc: do_o <= do_buffer_reg; -- parallel data out
+ do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- data out valid
+ di_req_o_proc: di_req_o <= di_req_o_reg; -- input data request for next cycle
+ wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- write acknowledge
+ -----------------------------------------------------------------------------------------------
+ -- SCK out logic: pipeline phase compensation for the SCK line
+ -----------------------------------------------------------------------------------------------
+ -- This is a MUX with an output register.
+ -- The register gives us a pipeline delay for the SCK line, pairing with the state machine moore
+ -- output pipeline delay for the MOSI line, and thus enabling higher SCK frequency.
+ spi_sck_o_gen_proc : process (sclk_i, sck_ena_reg, spi_clk, spi_clk_reg) is
+ begin
+ if sclk_i'event and sclk_i = '1' then
+ if sck_ena_reg = '1' then
+ spi_clk_reg <= spi_clk; -- copy the selected clock polarity
+ else
+ spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity
+ end if;
+ end if;
+ spi_sck_o <= spi_clk_reg; -- connect register to output
+ end process spi_sck_o_gen_proc;
+
+ --=============================================================================================
+ -- DEBUG LOGIC PROCESSES
+ --=============================================================================================
+ -- these signals are useful for verification, and can be deleted after debug.
+ do_transfer_proc: do_transfer_o <= do_transfer_reg;
+ state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4));
+ rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg;
+ wren_o_proc: wren_o <= wren;
+ sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg;
+ core_clk_o_proc: core_clk_o <= core_clk;
+ core_n_clk_o_proc: core_n_clk_o <= core_n_clk;
+ core_ce_o_proc: core_ce_o <= core_ce;
+ core_n_ce_o_proc: core_n_ce_o <= core_n_ce;
+ sck_ena_o_proc: sck_ena_o <= sck_ena_reg;
+ sck_ena_ce_o_proc: sck_ena_ce_o <= sck_ena_ce;
+
+end architecture rtl;
diff --git a/sources/ttc/ttc_busy/BusyVirtualElink.vhd b/sources/ttc/ttc_busy/BusyVirtualElink.vhd
index 2c8c392e3..f38b5f642 100644
--- a/sources/ttc/ttc_busy/BusyVirtualElink.vhd
+++ b/sources/ttc/ttc_busy/BusyVirtualElink.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
diff --git a/sources/ttc/ttc_busy/TTCToHostVirtualElink.vhd b/sources/ttc/ttc_busy/TTCToHostVirtualElink.vhd
index 28a5edf2e..30919cf56 100644
--- a/sources/ttc/ttc_busy/TTCToHostVirtualElink.vhd
+++ b/sources/ttc/ttc_busy/TTCToHostVirtualElink.vhd
@@ -1,3 +1,20 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
library ieee;
use ieee.std_logic_1164.all;
--
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