diff --git a/.gitignore b/.gitignore
index aecc6f43dfbc1cef30b707c7ced4a2f183a62808..d48ca2f74566bc9d4bf5aef62c990c1321349ac5 100644
--- a/.gitignore
+++ b/.gitignore
@@ -56,7 +56,6 @@ simulation/VUnit/*.mem
*.cf
**vivado_libs**
.*
-simulation/VUnit/**
*.qdb
*.qtl
diff --git a/scripts/filesets/felig_fileset.tcl b/scripts/filesets/felig_fileset.tcl
index 0f9157bea4c9efd9acae9050d082abb740e1e7a2..dc6c7763198e2b8a55785220950e5cdd7863447b 100644
--- a/scripts/filesets/felig_fileset.tcl
+++ b/scripts/filesets/felig_fileset.tcl
@@ -134,11 +134,21 @@ set XDC_FILES_BNL712 [concat $XDC_FILES_BNL712 \
# felig_top_BNL712_v2.0.xdc \
set SIM_FILES [concat $SIM_FILES \
- FELIG/felig_sim_top_bnl712.vhd \
- FELIG/felig_sim_64b66b_decoding.vhd]
+ FELIG/felig_sim_top_bnl712.vhd\
+ FELIG/felig_sim_64b66b_decoding.vhd\
+ FELIG/felig_lpgbt_sim.vhd\
+ UVVMtests/tb/FELIGemulator_tb.vhd\
+ UVVMtests/tb/FELIGlinkwrapperLPGBT_tb.vhd\
+ UVVMtests/tb/FELIGexternaltrigger_tb.vhd\
+]
set WCFG_FILES [concat $WCFG_FILES \
- FELIG/waveforms/FELIG_phase2_behav.wcfg]
+ FELIG/waveforms/FELIGemulator_tb_behav.wcfg\
+ FELIG/waveforms/FELIGexternaltrigger_tb_behav.wcfg\
+ FELIG/waveforms/FELIGlinkwrapperLPGBT_tb_behav.wcfg\
+ FELIG/waveforms/felig_lpgbt_sim.wcfg\
+ FELIG/waveforms/FELIG_phase2_behav.wcfg\
+ ]
diff --git a/simulation/FELIG/add_felig_sim_files.tcl b/simulation/FELIG/add_felig_sim_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5a75d248bbd23415cfd17cdc674c9a52aedd8e98
--- /dev/null
+++ b/simulation/FELIG/add_felig_sim_files.tcl
@@ -0,0 +1,20 @@
+#NEEDS TO BE RUN in scripts/FELIX_top/
+source ../helper/clear_filesets.tcl
+
+source ../filesets/felig_fileset.tcl
+
+#set VHDL_FILES [concat $VHDL_FILES $VHDL_FILES_KU]
+set SIM_FILES [concat $SIM_FILES $SIM_FILES_KU]
+
+set scriptdir [pwd]
+set firmware_dir $scriptdir/../../
+
+foreach SIM_FILE $SIM_FILES {
+ add_files -fileset sim_1 -force -norecurse ${firmware_dir}/simulation/$SIM_FILE
+ set_property library work [get_files ${firmware_dir}/simulation/$SIM_FILE]
+ set_property file_type {VHDL 2008} [get_files ${firmware_dir}/simulation/$SIM_FILE]
+}
+
+foreach WCFG_FILE $WCFG_FILES {
+ add_files -fileset sim_1 -force -norecurse ${firmware_dir}/simulation/$WCFG_FILE
+}
diff --git a/simulation/FELIG/add_lpgbt_files.tcl b/simulation/FELIG/add_lpgbt_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..94774a30cc3131db9dce809fac0b7a4a1d397e2d
--- /dev/null
+++ b/simulation/FELIG/add_lpgbt_files.tcl
@@ -0,0 +1,18 @@
+#NEEDS TO BE RUN in scripts/FELIX_top/
+source ../helper/clear_filesets.tcl
+
+source ../filesets/lpgbt_core_fileset.tcl
+
+set VHDL_FILES [concat $VHDL_FILES $VHDL_FILES_KU]
+
+set scriptdir [pwd]
+set firmware_dir $scriptdir/../../
+
+foreach VHDL_FILE $VHDL_FILES {
+ set file_path [file normalize ${firmware_dir}/sources/${VHDL_FILE}]
+
+ read_vhdl -library work $file_path
+ set_property FILE_TYPE {VHDL 2008} [get_files ${file_path}]
+ add_file $file_path
+}
+
diff --git a/simulation/FELIG/add_ttcemu_files.tcl b/simulation/FELIG/add_ttcemu_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..cdafae05c5a7286076d6a5340cc77eca645d08b3
--- /dev/null
+++ b/simulation/FELIG/add_ttcemu_files.tcl
@@ -0,0 +1,18 @@
+#NEEDS TO BE RUN in scripts/FELIX_top/
+source ../helper/clear_filesets.tcl
+
+source ../filesets/ttc_emulator_fileset.tcl
+
+set VHDL_FILES [concat $VHDL_FILES $VHDL_FILES_KU]
+
+set scriptdir [pwd]
+set firmware_dir $scriptdir/../../
+
+foreach VHDL_FILE $VHDL_FILES {
+ set file_path [file normalize ${firmware_dir}/sources/${VHDL_FILE}]
+
+ read_vhdl -library work $file_path
+ set_property FILE_TYPE {VHDL 2008} [get_files ${file_path}]
+ add_file $file_path
+}
+
diff --git a/simulation/FELIG/felig_lpgbt_sim.vhd b/simulation/FELIG/felig_lpgbt_sim.vhd
index 2239a7bc4919815e65a3a3bf3a9d850450718807..b177087690da18cef1aceda4b5ec08108dea23a3 100644
--- a/simulation/FELIG/felig_lpgbt_sim.vhd
+++ b/simulation/FELIG/felig_lpgbt_sim.vhd
@@ -1,3 +1,4 @@
+--ricardo luz, argonne
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -23,7 +24,7 @@ end felig_lpgbt_sim;
architecture Behavioral of felig_lpgbt_sim is
- component clk_wiz_40_0 -- @suppress "Component declaration is not equal to its matching entity"
+ component clk_wiz_40_0 -- @suppress "Component declaratiechoon is not equal to its matching entity"
port(
clk_in2 : in STD_LOGIC;
clk_in_sel : in STD_LOGIC;
@@ -151,7 +152,7 @@ begin
downlinkUserData_i => downlinkUserData_i, --in
downlinkEcData_i => downlinkEcData_i, --in
downlinkIcData_i => downlinkIcData_i, --in
- TXCLK40 => TXCLK40, --in
+ TXCLK40 => clk40, --in
TXCLK320 => GT_TX_WORD_CLK, --in
RXCLK320m => GT_RX_WORD_CLK, --in
uplinkSelectFEC_i => CTRL_FECMODE, --in
@@ -224,16 +225,12 @@ begin
Port map
(
clk40_in => rxrecclk40m,
- --TXCLK40 => txclk40m,--clk40_in, --in
- --RXCLK40 => rxrecclk40m, --in
TXCLK320 => GT_TX_WORD_CLK, --in
RXCLK320 => GT_RX_WORD_CLK, --in
rst_uplink_i => TX_RESET_i, --in
ctr_clkSlip_s => RxSlide_FE(i), --out
aligned => alignment_done_f_FE(i), --out
sta_headerFlag_o => sta_headerFlag_out_FE(i), --out
- sta_headerFlag_shift => open, --out
- clk_dataFlag_rxGb_s_o => open, --out
dat_upLinkWord_fromGb_s => TX_DATA_FE(i), --out
dat_downLinkWord_fromMgt_s16 => RX_DATA_16b, --in
rst_dnlink_i => rst_dnlink,--RL --in
@@ -294,9 +291,9 @@ begin
if timeout then
exit;
end if;
- data_to_back_end <= data_to_back_end + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
- data_to_front_end <= data_to_front_end + "00000000000000000000000000000001";
- wait for 3 us;
+ data_to_back_end <= data_to_back_end + x"1";
+ data_to_front_end <= data_to_front_end + x"1";
+ wait for 25 ns;
end loop;
wait for 1000 us;
end process;
diff --git a/simulation/FELIG/felig_sim_top_bnl712.vhd b/simulation/FELIG/felig_sim_top_bnl712.vhd
index f5100041e0f2a594037979d395666b5101cc5e0d..e8f20d1989686af1df9d0278021bf94fb16925c8 100644
--- a/simulation/FELIG/felig_sim_top_bnl712.vhd
+++ b/simulation/FELIG/felig_sim_top_bnl712.vhd
@@ -269,7 +269,7 @@ begin
lane_control(i).global.FEC <= '0';--register_map_control.LPGBT_FEC(0)
lane_control(i).global.DATARATE <= '1';-- not register_map_control.LPGBT_DATARATE(0)
lane_control(i).global.aligned <= linkValid_array(i);
- lane_control(i).fmemu_random.SELECT_RANDOM <= pcie0_register_map_40_control.FMEMU_RANDOM_CONTROL.SELECT_RANDOM;
+ --lane_control(i).fmemu_random.SELECT_RANDOM <= pcie0_register_map_40_control.FMEMU_RANDOM_CONTROL.SELECT_RANDOM;
lane_control(i).fmemu_random.FMEMU_RANDOM_RAM_ADDR <= pcie0_register_map_40_control.FMEMU_RANDOM_RAM_ADDR;
lane_control(i).fmemu_random.FMEMU_RANDOM_RAM <= pcie0_register_map_40_control.FMEMU_RANDOM_RAM;
lane_control(i).fmemu_random.FMEMU_RANDOM_CONTROL <= pcie0_register_map_40_control.FMEMU_RANDOM_CONTROL;
@@ -585,6 +585,8 @@ begin
link_tx_flag_in => link_tx_flag_i, --gbt_tx_flag_i,
link_rx_flag_in => link_rx_flag_i, -- gbt_rx_flag_i,
+ l1a_int_trigger_out => open, --sim
+
lane_control => lane_control,
lane_monitor => open --lane_monitor,
-- register_map_control_40xtal => pcie0_register_map_40_control,
diff --git a/simulation/FELIG/waveforms/FELIGemulator_tb_behav.wcfg b/simulation/FELIG/waveforms/FELIGemulator_tb_behav.wcfg
new file mode 100644
index 0000000000000000000000000000000000000000..b27d4e6d2e58a1f7cc634accedf3771966f0b148
--- /dev/null
+++ b/simulation/FELIG/waveforms/FELIGemulator_tb_behav.wcfg
@@ -0,0 +1,302 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+ <wave_state>
+ </wave_state>
+ <db_ref_list>
+ <db_ref path="FELIGemulator_tb_behav.wdb" id="1">
+ <top_modules>
+ <top_module name="FELIGemulator_tb" />
+ <top_module name="axi_stream_package" />
+ <top_module name="centralrouter_package" />
+ <top_module name="felix_package" />
+ <top_module name="glbl" />
+ <top_module name="ip_lib" />
+ <top_module name="pcie_package" />
+ <top_module name="type_lib" />
+ <top_module name="vcomponents" />
+ </top_modules>
+ </db_ref>
+ </db_ref_list>
+ <zoom_setting>
+ <ZoomStartTime time="0.000000 us"></ZoomStartTime>
+ <ZoomEndTime time="171.908068 us"></ZoomEndTime>
+ <Cursor1Time time="171.908067 us"></Cursor1Time>
+ </zoom_setting>
+ <column_width_setting>
+ <NameColumnWidth column_width="206"></NameColumnWidth>
+ <ValueColumnWidth column_width="150"></ValueColumnWidth>
+ </column_width_setting>
+ <WVObjectSize size="66" />
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/clk40">
+ <obj_property name="ElementShortName">clk40</obj_property>
+ <obj_property name="ObjectShortName">clk40</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/clk160">
+ <obj_property name="ElementShortName">clk160</obj_property>
+ <obj_property name="ObjectShortName">clk160</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/clk240">
+ <obj_property name="ElementShortName">clk240</obj_property>
+ <obj_property name="ObjectShortName">clk240</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/clk320">
+ <obj_property name="ElementShortName">clk320</obj_property>
+ <obj_property name="ObjectShortName">clk320</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/clkTX">
+ <obj_property name="ElementShortName">clkTX[0:0]</obj_property>
+ <obj_property name="ObjectShortName">clkTX[0:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/clkRX">
+ <obj_property name="ElementShortName">clkRX[0:0]</obj_property>
+ <obj_property name="ObjectShortName">clkRX[0:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/m_axis_aclk">
+ <obj_property name="ElementShortName">m_axis_aclk</obj_property>
+ <obj_property name="ObjectShortName">m_axis_aclk</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/clk_prcss">
+ <obj_property name="ElementShortName">clk_prcss</obj_property>
+ <obj_property name="ObjectShortName">clk_prcss</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/link_tx_flag">
+ <obj_property name="ElementShortName">link_tx_flag[0:0]</obj_property>
+ <obj_property name="ObjectShortName">link_tx_flag[0:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/reset">
+ <obj_property name="ElementShortName">reset</obj_property>
+ <obj_property name="ObjectShortName">reset</obj_property>
+ </wvobject>
+ <wvobject fp_name="divider667" type="divider">
+ <obj_property name="label">Emulator</obj_property>
+ <obj_property name="DisplayName">label</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(0)\/emu_0/l1a_trig">
+ <obj_property name="ElementShortName">l1a_trig</obj_property>
+ <obj_property name="ObjectShortName">l1a_trig</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(0)\/emu_0/l1a_id">
+ <obj_property name="ElementShortName">l1a_id[15:0]</obj_property>
+ <obj_property name="ObjectShortName">l1a_id[15:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/elink_data_in">
+ <obj_property name="ElementShortName">elink_data_in[0:111][9:0]</obj_property>
+ <obj_property name="ObjectShortName">elink_data_in[0:111][9:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(0)\/emu_0/def_data_gen/elinkdata_o">
+ <obj_property name="ElementShortName">elinkdata_o[17:0]</obj_property>
+ <obj_property name="ObjectShortName">elinkdata_o[17:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(1)\/emu_0/def_data_gen/elinkdata_o">
+ <obj_property name="ElementShortName">elinkdata_o[17:0]</obj_property>
+ <obj_property name="ObjectShortName">elinkdata_o[17:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(2)\/emu_0/def_data_gen/elinkdata_o">
+ <obj_property name="ElementShortName">elinkdata_o[17:0]</obj_property>
+ <obj_property name="ObjectShortName">elinkdata_o[17:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(3)\/emu_0/def_data_gen/elinkdata_o">
+ <obj_property name="ElementShortName">elinkdata_o[17:0]</obj_property>
+ <obj_property name="ObjectShortName">elinkdata_o[17:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(4)\/emu_0/def_data_gen/elinkdata_o">
+ <obj_property name="ElementShortName">elinkdata_o[17:0]</obj_property>
+ <obj_property name="ObjectShortName">elinkdata_o[17:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(5)\/emu_0/def_data_gen/elinkdata_o">
+ <obj_property name="ElementShortName">elinkdata_o[17:0]</obj_property>
+ <obj_property name="ObjectShortName">elinkdata_o[17:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(6)\/emu_0/def_data_gen/elinkdata_o">
+ <obj_property name="ElementShortName">elinkdata_o[17:0]</obj_property>
+ <obj_property name="ObjectShortName">elinkdata_o[17:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(0)\/emu_0/enc8b10bx/dataIN">
+ <obj_property name="ElementShortName">dataIN[7:0]</obj_property>
+ <obj_property name="ObjectShortName">dataIN[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(1)\/emu_0/enc8b10bx/dataIN">
+ <obj_property name="ElementShortName">dataIN[7:0]</obj_property>
+ <obj_property name="ObjectShortName">dataIN[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(2)\/emu_0/enc8b10bx/dataIN">
+ <obj_property name="ElementShortName">dataIN[7:0]</obj_property>
+ <obj_property name="ObjectShortName">dataIN[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(3)\/emu_0/enc8b10bx/dataIN">
+ <obj_property name="ElementShortName">dataIN[7:0]</obj_property>
+ <obj_property name="ObjectShortName">dataIN[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(4)\/emu_0/enc8b10bx/dataIN">
+ <obj_property name="ElementShortName">dataIN[7:0]</obj_property>
+ <obj_property name="ObjectShortName">dataIN[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(5)\/emu_0/enc8b10bx/dataIN">
+ <obj_property name="ElementShortName">dataIN[7:0]</obj_property>
+ <obj_property name="ObjectShortName">dataIN[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(6)\/emu_0/enc8b10bx/dataIN">
+ <obj_property name="ElementShortName">dataIN[7:0]</obj_property>
+ <obj_property name="ObjectShortName">dataIN[7:0]</obj_property>
+ </wvobject>
+ <wvobject fp_name="divider668" type="divider">
+ <obj_property name="label">GBT/LPGBT out</obj_property>
+ <obj_property name="DisplayName">label</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/link_tx_data">
+ <obj_property name="ElementShortName">link_tx_data[0:0][227:0]</obj_property>
+ <obj_property name="ObjectShortName">link_tx_data[0:0][227:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/link_tx_valid">
+ <obj_property name="ElementShortName">link_tx_valid[0:0]</obj_property>
+ <obj_property name="ObjectShortName">link_tx_valid[0:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/l1id">
+ <obj_property name="ElementShortName">l1id[15:0]</obj_property>
+ <obj_property name="ObjectShortName">l1id[15:0]</obj_property>
+ </wvobject>
+ <wvobject fp_name="divider859" type="divider">
+ <obj_property name="label">maxis</obj_property>
+ <obj_property name="DisplayName">label</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/m_axis">
+ <obj_property name="ElementShortName">m_axis[0:0,0:41]</obj_property>
+ <obj_property name="ObjectShortName">m_axis[0:0,0:41]</obj_property>
+ <obj_property name="isExpanded"></obj_property>
+ </wvobject>
+ <wvobject fp_name="divider859" type="divider">
+ <obj_property name="label">decoder out</obj_property>
+ <obj_property name="DisplayName">label</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/\g_checking_data(0)\/\g_Streams(24)\/data">
+ <obj_property name="ElementShortName">data[31:0]</obj_property>
+ <obj_property name="ObjectShortName">data[31:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/\g_checking_data(0)\/\g_Streams(24)\/data10b">
+ <obj_property name="ElementShortName">data10b[9:0]</obj_property>
+ <obj_property name="ObjectShortName">data10b[9:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/\g_checking_data(0)\/\g_Streams(24)\/count8b">
+ <obj_property name="ElementShortName">count8b[1:0]</obj_property>
+ <obj_property name="ObjectShortName">count8b[1:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/\g_checking_data(0)\/\g_Streams(24)\/count_chunks">
+ <obj_property name="ElementShortName">count_chunks[6:0]</obj_property>
+ <obj_property name="ObjectShortName">count_chunks[6:0]</obj_property>
+ <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/\g_checking_data(0)\/\g_Streams(24)\/checked">
+ <obj_property name="ElementShortName">checked</obj_property>
+ <obj_property name="ObjectShortName">checked</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/\g_checking_data(0)\/\g_Streams(24)\/check_words">
+ <obj_property name="ElementShortName">check_words</obj_property>
+ <obj_property name="ObjectShortName">check_words</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/\g_checking_data(0)\/\g_Streams(24)\/check_length">
+ <obj_property name="ElementShortName">check_length</obj_property>
+ <obj_property name="ObjectShortName">check_length</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/\g_checking_data(0)\/\g_Streams(24)\/last">
+ <obj_property name="ElementShortName">last</obj_property>
+ <obj_property name="ObjectShortName">last</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/\g_checking_data(0)\/\g_Streams(24)\/keep">
+ <obj_property name="ElementShortName">keep[3:0]</obj_property>
+ <obj_property name="ObjectShortName">keep[3:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/\g_checking_data(0)\/\g_Streams(24)\/exp_checks">
+ <obj_property name="ElementShortName">exp_checks[6:0]</obj_property>
+ <obj_property name="ObjectShortName">exp_checks[6:0]</obj_property>
+ <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/\g_checking_data(0)\/\g_Streams(24)\/reset_v_ch">
+ <obj_property name="ElementShortName">reset_v_ch</obj_property>
+ <obj_property name="ObjectShortName">reset_v_ch</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/\g_checking_data(0)\/\g_Streams(24)\/cnt_checks">
+ <obj_property name="ElementShortName">cnt_checks[6:0]</obj_property>
+ <obj_property name="ObjectShortName">cnt_checks[6:0]</obj_property>
+ <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/epath_aligned">
+ <obj_property name="ElementShortName">epath_aligned[0:0,39:0]</obj_property>
+ <obj_property name="ObjectShortName">epath_aligned[0:0,39:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/\g_checking_data(0)\/\g_Streams(24)\/good">
+ <obj_property name="ElementShortName">good</obj_property>
+ <obj_property name="ObjectShortName">good</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/l1a">
+ <obj_property name="ElementShortName">l1a</obj_property>
+ <obj_property name="ObjectShortName">l1a</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/data_good">
+ <obj_property name="ElementShortName">data_good[0:0,39:0]</obj_property>
+ <obj_property name="ObjectShortName">data_good[0:0,39:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/epath_enabled">
+ <obj_property name="ElementShortName">epath_enabled[0:0,39:0]</obj_property>
+ <obj_property name="ObjectShortName">epath_enabled[0:0,39:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/epath_aligned">
+ <obj_property name="ElementShortName">epath_aligned[0:0,39:0]</obj_property>
+ <obj_property name="ObjectShortName">epath_aligned[0:0,39:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/count_final">
+ <obj_property name="ElementShortName">count_final[4:0]</obj_property>
+ <obj_property name="ObjectShortName">count_final[4:0]</obj_property>
+ <obj_property name="Radix">HEXRADIX</obj_property>
+ <obj_property name="CustomSignalColor">#FAAFBE</obj_property>
+ <obj_property name="UseCustomSignalColor">true</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/FELIG_emu/\emulator_inst(0)\/gbt/\dgen_group(0)\/emu_0/l1a_id">
+ <obj_property name="ElementShortName">l1a_id[15:0]</obj_property>
+ <obj_property name="ObjectShortName">l1a_id[15:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/l1a">
+ <obj_property name="ElementShortName">l1a</obj_property>
+ <obj_property name="ObjectShortName">l1a</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/epath_enabled_slv">
+ <obj_property name="ElementShortName">epath_enabled_slv[39:0]</obj_property>
+ <obj_property name="ObjectShortName">epath_enabled_slv[39:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/epath_aligned_slv">
+ <obj_property name="ElementShortName">epath_aligned_slv[39:0]</obj_property>
+ <obj_property name="ObjectShortName">epath_aligned_slv[39:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/epath_aligned_d_slv">
+ <obj_property name="ElementShortName">epath_aligned_d_slv[39:0]</obj_property>
+ <obj_property name="ObjectShortName">epath_aligned_d_slv[39:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/epath_aligned_dd_slv">
+ <obj_property name="ElementShortName">epath_aligned_dd_slv[39:0]</obj_property>
+ <obj_property name="ObjectShortName">epath_aligned_dd_slv[39:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/data_good_slv">
+ <obj_property name="ElementShortName">data_good_slv[39:0]</obj_property>
+ <obj_property name="ObjectShortName">data_good_slv[39:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/reset">
+ <obj_property name="ElementShortName">reset</obj_property>
+ <obj_property name="ObjectShortName">reset</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/reset_d">
+ <obj_property name="ElementShortName">reset_d</obj_property>
+ <obj_property name="ObjectShortName">reset_d</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGemulator_tb/FELIG_emu/l1a_int_trigger">
+ <obj_property name="ElementShortName">l1a_int_trigger</obj_property>
+ <obj_property name="ObjectShortName">l1a_int_trigger</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/enabled_aligned">
+ <obj_property name="ElementShortName">enabled_aligned[15:0][1:0]</obj_property>
+ <obj_property name="ObjectShortName">enabled_aligned[15:0][1:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGemulator_tb/\g_checking_data(0)\/\g_Streams(24)\/exp_checks">
+ <obj_property name="ElementShortName">exp_checks[6:0]</obj_property>
+ <obj_property name="ObjectShortName">exp_checks[6:0]</obj_property>
+ <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+ </wvobject>
+</wave_config>
diff --git a/simulation/FELIG/waveforms/FELIGexternaltrigger_tb_behav.wcfg b/simulation/FELIG/waveforms/FELIGexternaltrigger_tb_behav.wcfg
new file mode 100644
index 0000000000000000000000000000000000000000..52cc8eb5e3c0925f0856052ba4d6e1fca9bcf1e7
--- /dev/null
+++ b/simulation/FELIG/waveforms/FELIGexternaltrigger_tb_behav.wcfg
@@ -0,0 +1,250 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+ <wave_state>
+ </wave_state>
+ <db_ref_list>
+ <db_ref path="FELIGexternaltrigger_tb_behav.wdb" id="1">
+ <top_modules>
+ <top_module name="FELIGexternaltrigger_tb" />
+ <top_module name="axi_stream_package" />
+ <top_module name="centralrouter_package" />
+ <top_module name="felix_package" />
+ <top_module name="glbl" />
+ <top_module name="ip_lib" />
+ <top_module name="pcie_package" />
+ <top_module name="type_lib" />
+ <top_module name="vcomponents" />
+ </top_modules>
+ </db_ref>
+ </db_ref_list>
+ <zoom_setting>
+ <ZoomStartTime time="0.000000 us"></ZoomStartTime>
+ <ZoomEndTime time="60.000001 us"></ZoomEndTime>
+ <Cursor1Time time="57.542518 us"></Cursor1Time>
+ </zoom_setting>
+ <column_width_setting>
+ <NameColumnWidth column_width="189"></NameColumnWidth>
+ <ValueColumnWidth column_width="66"></ValueColumnWidth>
+ </column_width_setting>
+ <WVObjectSize size="54" />
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/clk40">
+ <obj_property name="ElementShortName">clk40</obj_property>
+ <obj_property name="ObjectShortName">clk40</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/clk320">
+ <obj_property name="ElementShortName">clk320</obj_property>
+ <obj_property name="ObjectShortName">clk320</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/reset">
+ <obj_property name="ElementShortName">reset</obj_property>
+ <obj_property name="ObjectShortName">reset</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/L1A">
+ <obj_property name="ElementShortName">L1A</obj_property>
+ <obj_property name="ObjectShortName">L1A</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/L1A_count">
+ <obj_property name="ElementShortName">L1A_count[7:0]</obj_property>
+ <obj_property name="ObjectShortName">L1A_count[7:0]</obj_property>
+ <obj_property name="isExpanded"></obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/TTCEmu/TTCout">
+ <obj_property name="ElementShortName">TTCout[9:0]</obj_property>
+ <obj_property name="ObjectShortName">TTCout[9:0]</obj_property>
+ </wvobject>
+ <wvobject fp_name="divider20" type="divider">
+ <obj_property name="label">emul</obj_property>
+ <obj_property name="DisplayName">label</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/felig_emulator/TTC_out">
+ <obj_property name="ElementShortName">TTC_out[9:0]</obj_property>
+ <obj_property name="ObjectShortName">TTC_out[9:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/felig_emulator/ttc_fifo_din">
+ <obj_property name="ElementShortName">ttc_fifo_din[9:0]</obj_property>
+ <obj_property name="ObjectShortName">ttc_fifo_din[9:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/felig_emulator/ttc_fifo_dout">
+ <obj_property name="ElementShortName">ttc_fifo_dout[9:0]</obj_property>
+ <obj_property name="ObjectShortName">ttc_fifo_dout[9:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/felig_emulator/TTC_out_fifo">
+ <obj_property name="ElementShortName">TTC_out_fifo[9:0]</obj_property>
+ <obj_property name="ObjectShortName">TTC_out_fifo[9:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/felig_emulator/link_aligned">
+ <obj_property name="ElementShortName">link_aligned</obj_property>
+ <obj_property name="ObjectShortName">link_aligned</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/felig_emulator/ttc_fifo_rst">
+ <obj_property name="ElementShortName">ttc_fifo_rst</obj_property>
+ <obj_property name="ObjectShortName">ttc_fifo_rst</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/felig_emulator/lane_reset">
+ <obj_property name="ElementShortName">lane_reset</obj_property>
+ <obj_property name="ObjectShortName">lane_reset</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/felig_emulator/ext_l1a_trigger">
+ <obj_property name="ElementShortName">ext_l1a_trigger</obj_property>
+ <obj_property name="ObjectShortName">ext_l1a_trigger</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/felig_emulator/ext_l1a_id">
+ <obj_property name="ElementShortName">ext_l1a_id[15:0]</obj_property>
+ <obj_property name="ObjectShortName">ext_l1a_id[15:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/felig_emulator/l1a_trigger">
+ <obj_property name="ElementShortName">l1a_trigger</obj_property>
+ <obj_property name="ObjectShortName">l1a_trigger</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/felig_emulator/l1a_id">
+ <obj_property name="ElementShortName">l1a_id[15:0]</obj_property>
+ <obj_property name="ObjectShortName">l1a_id[15:0]</obj_property>
+ </wvobject>
+ <wvobject fp_name="divider109" type="divider">
+ <obj_property name="label">top</obj_property>
+ <obj_property name="DisplayName">label</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/emu_l1a_id">
+ <obj_property name="ElementShortName">emu_l1a_id[15:0]</obj_property>
+ <obj_property name="ObjectShortName">emu_l1a_id[15:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/emu_l1a">
+ <obj_property name="ElementShortName">emu_l1a</obj_property>
+ <obj_property name="ObjectShortName">emu_l1a</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/tx_data">
+ <obj_property name="ElementShortName">tx_data[227:0]</obj_property>
+ <obj_property name="ObjectShortName">tx_data[227:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/tx_eg_data">
+ <obj_property name="ElementShortName">tx_eg_data[6:0][31:0]</obj_property>
+ <obj_property name="ObjectShortName">tx_eg_data[6:0][31:0]</obj_property>
+ </wvobject>
+ <wvobject fp_name="divider1892" type="divider">
+ <obj_property name="label">data_valid</obj_property>
+ <obj_property name="DisplayName">label</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/aligned">
+ <obj_property name="ElementShortName">aligned</obj_property>
+ <obj_property name="ObjectShortName">aligned</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/data_to_be_checked">
+ <obj_property name="ElementShortName">data_to_be_checked[7:0]</obj_property>
+ <obj_property name="ObjectShortName">data_to_be_checked[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/felig_emulator/data_ready_tx_out">
+ <obj_property name="ElementShortName">data_ready_tx_out</obj_property>
+ <obj_property name="ObjectShortName">data_ready_tx_out</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/data_delay">
+ <obj_property name="ElementShortName">data_delay[7:0]</obj_property>
+ <obj_property name="ObjectShortName">data_delay[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/data_count">
+ <obj_property name="ElementShortName">data_count[31:0]</obj_property>
+ <obj_property name="ObjectShortName">data_count[31:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/valid_delay">
+ <obj_property name="ElementShortName">valid_delay</obj_property>
+ <obj_property name="ObjectShortName">valid_delay</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/data_size">
+ <obj_property name="ElementShortName">data_size[31:0]</obj_property>
+ <obj_property name="ObjectShortName">data_size[31:0]</obj_property>
+ <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+ </wvobject>
+ <wvobject fp_name="divider2164" type="divider">
+ <obj_property name="label">check word</obj_property>
+ <obj_property name="DisplayName">label</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/emu_l1a">
+ <obj_property name="ElementShortName">emu_l1a</obj_property>
+ <obj_property name="ObjectShortName">emu_l1a</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/exp_checks">
+ <obj_property name="ElementShortName">exp_checks[6:0]</obj_property>
+ <obj_property name="ObjectShortName">exp_checks[6:0]</obj_property>
+ <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/cnt_checks">
+ <obj_property name="ElementShortName">cnt_checks[6:0]</obj_property>
+ <obj_property name="ObjectShortName">cnt_checks[6:0]</obj_property>
+ <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/data_delay">
+ <obj_property name="ElementShortName">data_delay[7:0]</obj_property>
+ <obj_property name="ObjectShortName">data_delay[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/check_words">
+ <obj_property name="ElementShortName">check_words</obj_property>
+ <obj_property name="ObjectShortName">check_words</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/clk40">
+ <obj_property name="ElementShortName">clk40</obj_property>
+ <obj_property name="ObjectShortName">clk40</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/emu_l1a">
+ <obj_property name="ElementShortName">emu_l1a</obj_property>
+ <obj_property name="ObjectShortName">emu_l1a</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/emu_l1a_40">
+ <obj_property name="ElementShortName">emu_l1a_40</obj_property>
+ <obj_property name="ObjectShortName">emu_l1a_40</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/clk320">
+ <obj_property name="ElementShortName">clk320</obj_property>
+ <obj_property name="ObjectShortName">clk320</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/good">
+ <obj_property name="ElementShortName">good</obj_property>
+ <obj_property name="ObjectShortName">good</obj_property>
+ </wvobject>
+ <wvobject fp_name="divider2466" type="divider">
+ <obj_property name="label">triggers</obj_property>
+ <obj_property name="DisplayName">label</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/felig_emulator/ext_l1a_trigger">
+ <obj_property name="ElementShortName">ext_l1a_trigger</obj_property>
+ <obj_property name="ObjectShortName">ext_l1a_trigger</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/felig_emulator/ext_l1a_id">
+ <obj_property name="ElementShortName">ext_l1a_id[15:0]</obj_property>
+ <obj_property name="ObjectShortName">ext_l1a_id[15:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/single_ecr_long">
+ <obj_property name="ElementShortName">single_ecr_long</obj_property>
+ <obj_property name="ObjectShortName">single_ecr_long</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/felig_emulator/ECR">
+ <obj_property name="ElementShortName">ECR</obj_property>
+ <obj_property name="ObjectShortName">ECR</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/l1a_id_register_rst">
+ <obj_property name="ElementShortName">l1a_id_register_rst</obj_property>
+ <obj_property name="ObjectShortName">l1a_id_register_rst</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/next_l1a_id">
+ <obj_property name="ElementShortName">next_l1a_id[15:0]</obj_property>
+ <obj_property name="ObjectShortName">next_l1a_id[15:0]</obj_property>
+ </wvobject>
+ <wvobject fp_name="divider2779" type="divider">
+ <obj_property name="label">checks</obj_property>
+ <obj_property name="DisplayName">label</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/count_triggers">
+ <obj_property name="ElementShortName">count_triggers[7:0]</obj_property>
+ <obj_property name="ObjectShortName">count_triggers[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/count_good_ids">
+ <obj_property name="ElementShortName">count_good_ids[7:0]</obj_property>
+ <obj_property name="ObjectShortName">count_good_ids[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGexternaltrigger_tb/count_good_data">
+ <obj_property name="ElementShortName">count_good_data[7:0]</obj_property>
+ <obj_property name="ObjectShortName">count_good_data[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGexternaltrigger_tb/test">
+ <obj_property name="ElementShortName">test</obj_property>
+ <obj_property name="ObjectShortName">test</obj_property>
+ </wvobject>
+</wave_config>
diff --git a/simulation/FELIG/waveforms/FELIGlinkwrapperLPGBT_tb_behav.wcfg b/simulation/FELIG/waveforms/FELIGlinkwrapperLPGBT_tb_behav.wcfg
new file mode 100644
index 0000000000000000000000000000000000000000..564b986b2bfc4e217c8a1efc0950efe5d20e0dcf
--- /dev/null
+++ b/simulation/FELIG/waveforms/FELIGlinkwrapperLPGBT_tb_behav.wcfg
@@ -0,0 +1,82 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+ <wave_state>
+ </wave_state>
+ <db_ref_list>
+ <db_ref path="FELIGlinkwrapperLPGBT_tb_behav.wdb" id="1">
+ <top_modules>
+ <top_module name="FELIGlinkwrapperLPGBT_tb" />
+ <top_module name="axi_stream_package" />
+ <top_module name="centralrouter_package" />
+ <top_module name="felix_package" />
+ <top_module name="glbl" />
+ <top_module name="lpgbtfpga_package" />
+ <top_module name="pcie_package" />
+ <top_module name="type_lib" />
+ <top_module name="vcomponents" />
+ </top_modules>
+ </db_ref>
+ </db_ref_list>
+ <zoom_setting>
+ <ZoomStartTime time="16,107.414 ns"></ZoomStartTime>
+ <ZoomEndTime time="16,343.285 ns"></ZoomEndTime>
+ <Cursor1Time time="21,000.000 ns"></Cursor1Time>
+ </zoom_setting>
+ <column_width_setting>
+ <NameColumnWidth column_width="203"></NameColumnWidth>
+ <ValueColumnWidth column_width="152"></ValueColumnWidth>
+ </column_width_setting>
+ <WVObjectSize size="13" />
+ <wvobject type="logic" fp_name="/FELIGlinkwrapperLPGBT_tb/clk40">
+ <obj_property name="ElementShortName">clk40</obj_property>
+ <obj_property name="ObjectShortName">clk40</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGlinkwrapperLPGBT_tb/clk320">
+ <obj_property name="ElementShortName">clk320</obj_property>
+ <obj_property name="ObjectShortName">clk320</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGlinkwrapperLPGBT_tb/reset_clk40">
+ <obj_property name="ElementShortName">reset_clk40</obj_property>
+ <obj_property name="ObjectShortName">reset_clk40</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/FELIGlinkwrapperLPGBT_tb/reset_done_clk40">
+ <obj_property name="ElementShortName">reset_done_clk40</obj_property>
+ <obj_property name="ObjectShortName">reset_done_clk40</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGlinkwrapperLPGBT_tb/alignment_done_BE">
+ <obj_property name="ElementShortName">alignment_done_BE[0:0]</obj_property>
+ <obj_property name="ObjectShortName">alignment_done_BE[0:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGlinkwrapperLPGBT_tb/alignment_done_FE">
+ <obj_property name="ElementShortName">alignment_done_FE[0:0]</obj_property>
+ <obj_property name="ObjectShortName">alignment_done_FE[0:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGlinkwrapperLPGBT_tb/TX_DATA_BE">
+ <obj_property name="ElementShortName">TX_DATA_BE[0:0][15:0]</obj_property>
+ <obj_property name="ObjectShortName">TX_DATA_BE[0:0][15:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGlinkwrapperLPGBT_tb/TX_DATA_FE">
+ <obj_property name="ElementShortName">TX_DATA_FE[0:0][31:0]</obj_property>
+ <obj_property name="ObjectShortName">TX_DATA_FE[0:0][31:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGlinkwrapperLPGBT_tb/data_to_be_clk40">
+ <obj_property name="ElementShortName">data_to_be_clk40[223:0]</obj_property>
+ <obj_property name="ObjectShortName">data_to_be_clk40[223:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGlinkwrapperLPGBT_tb/uplinkData_i_BE">
+ <obj_property name="ElementShortName">uplinkData_i_BE[0:0][233:0]</obj_property>
+ <obj_property name="ObjectShortName">uplinkData_i_BE[0:0][233:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGlinkwrapperLPGBT_tb/data_to_fe_clk40">
+ <obj_property name="ElementShortName">data_to_fe_clk40[31:0]</obj_property>
+ <obj_property name="ObjectShortName">data_to_fe_clk40[31:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGlinkwrapperLPGBT_tb/downLinkData_i_FE">
+ <obj_property name="ElementShortName">downLinkData_i_FE[0:0][35:0]</obj_property>
+ <obj_property name="ObjectShortName">downLinkData_i_FE[0:0][35:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/FELIGlinkwrapperLPGBT_tb/data_rdy_BE">
+ <obj_property name="ElementShortName">data_rdy_BE[0:0]</obj_property>
+ <obj_property name="ObjectShortName">data_rdy_BE[0:0]</obj_property>
+ </wvobject>
+</wave_config>
diff --git a/simulation/FELIG/felig_lpgbt_sim.wcfg b/simulation/FELIG/waveforms/felig_lpgbt_sim.wcfg
similarity index 97%
rename from simulation/FELIG/felig_lpgbt_sim.wcfg
rename to simulation/FELIG/waveforms/felig_lpgbt_sim.wcfg
index 693d91c8c58801bb51520872a247e72fa229d779..f4a5c3fe33fff60a5ca8c0f0131159046da5febb 100644
--- a/simulation/FELIG/felig_lpgbt_sim.wcfg
+++ b/simulation/FELIG/waveforms/felig_lpgbt_sim.wcfg
@@ -16,13 +16,13 @@
</db_ref>
</db_ref_list>
<zoom_setting>
- <ZoomStartTime time="977.931 ns"></ZoomStartTime>
- <ZoomEndTime time="1,004.414 ns"></ZoomEndTime>
- <Cursor1Time time="1,000.000 ns"></Cursor1Time>
+ <ZoomStartTime time="0.000000 us"></ZoomStartTime>
+ <ZoomEndTime time="21.000001 us"></ZoomEndTime>
+ <Cursor1Time time="9.793750 us"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="203"></NameColumnWidth>
- <ValueColumnWidth column_width="160"></ValueColumnWidth>
+ <ValueColumnWidth column_width="156"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="56" />
<wvobject fp_name="divider1259" type="divider">
@@ -93,6 +93,7 @@
<wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/FE_UPLINK_USER_DATA">
<obj_property name="ElementShortName">FE_UPLINK_USER_DATA[223:0]</obj_property>
<obj_property name="ObjectShortName">FE_UPLINK_USER_DATA[223:0]</obj_property>
+ <obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/FE_UPLINK_IC_DATA">
<obj_property name="ElementShortName">FE_UPLINK_IC_DATA[1:0]</obj_property>
@@ -105,6 +106,7 @@
<wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_BE(0)\/uplinkDATA">
<obj_property name="ElementShortName">uplinkDATA[223:0]</obj_property>
<obj_property name="ObjectShortName">uplinkDATA[223:0]</obj_property>
+ <obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_BE(0)\/uplinkIC">
<obj_property name="ElementShortName">uplinkIC[1:0]</obj_property>
@@ -117,6 +119,8 @@
<wvobject type="array" fp_name="/felig_lpgbt_sim/uplinkData_i_BE">
<obj_property name="ElementShortName">uplinkData_i_BE[3:0][233:0]</obj_property>
<obj_property name="ObjectShortName">uplinkData_i_BE[3:0][233:0]</obj_property>
+ <obj_property name="Radix">HEXRADIX</obj_property>
+ <obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="logic" fp_name="/felig_lpgbt_sim/\limk_loop_BE(3)\/lpgbt_BE/lpgbtfpga_uplink_fec5_inst/rst_pattsearch_s">
<obj_property name="ElementShortName">rst_pattsearch_s</obj_property>
diff --git a/simulation/UVVMtests/tb/FELIGemulator_tb.vhd b/simulation/UVVMtests/tb/FELIGemulator_tb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d39becd89e2b902ef41be2ecc7de3bcd7611d95e
--- /dev/null
+++ b/simulation/UVVMtests/tb/FELIGemulator_tb.vhd
@@ -0,0 +1,701 @@
+--ricardo luz, argonne
+--based on simulation/FELIG/felig_sim_top_bnl712.vhd
+
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.numeric_std_unsigned.all;
+ use IEEE.std_logic_textio.all;
+
+ use std.env.all;
+ use std.textio.all;
+
+ use work.FELIX_package.all;
+ use work.pcie_package.all;
+ use work.axi_stream_package.all;
+ use work.centralRouter_package.all;
+ use work.type_lib.ALL;
+
+library xpm;
+ use xpm.vcomponents.all;
+
+library uvvm_util;
+ context uvvm_util.uvvm_util_context;
+
+entity FELIGemulator_tb is
+ generic(
+ use_vunit : boolean := false;
+ FIRMWARE_MODE : integer := 11 --6 GBT, 11 LPGBT
+ );
+ port(
+ uvvm_completed: out std_logic := '0'
+ );
+end FELIGemulator_tb;
+
+architecture tb of FELIGemulator_tb is
+ function FM_TO_STREAMS (FIRMWARE_MODE:integer)
+ return integer is
+ begin
+ if FIRMWARE_MODE = 11 then
+ return 30;
+ elsif FIRMWARE_MODE = 6 then
+ return 42;
+ else
+ return 0;
+ end if;
+ end function;
+
+ constant GBT_NUM : integer := 1;
+ constant NUMELINKmax : integer := 112; --name number of epahts per egroup (theoretically 2b epath * 112=224, but never happens)
+ constant NUMEGROUPmax : integer := 7; --name number of egroups
+ constant STREAMS_TOHOST : integer := FM_TO_STREAMS(FIRMWARE_MODE);
+
+ constant clk40_period : time := 25 ns;
+ signal clk_en : boolean := false;
+ signal clk40 : std_logic;
+ signal clk40_tmp : std_logic := '0';
+ signal clk240 : std_logic;
+ signal clk240_tmp : std_logic := '0';
+ signal clk160 : std_logic;
+ signal clk160_tmp : std_logic := '0';
+ signal clk320 : std_logic;
+ signal clk320_tmp : std_logic := '0';
+ signal clk_prcss : std_logic := '0';
+ signal clkTX : std_logic_vector(GBT_NUM-1 downto 0);
+ signal clkRX : std_logic_vector(GBT_NUM-1 downto 0);
+ signal cnt_div : std_logic_vector(1 downto 0) := (others => '0');
+ signal cnt_div_max : std_logic_vector(1 downto 0) := (others => '0');
+
+ signal reset : std_logic;
+ signal reset_d : std_logic;
+
+ signal lane_control : array_of_lane_control_type(GBT_NUM-1 downto 0);
+ signal lane_monitor : array_of_lane_monitor_type(GBT_NUM-1 downto 0);
+ signal select_random : std_logic_vector(0 downto 0) := "0";
+
+ signal link_tx_data : txrx228b_type(0 to GBT_NUM-1);
+ --signal link_rx_data : txrx120b_type(0 to GBT_NUM-1);
+ signal link_tx_valid : std_logic_vector(0 to GBT_NUM-1);
+ signal link_tx_flag : std_logic_vector(GBT_NUM-1 downto 0);
+ --signal link_rx_flag : std_logic_vector(GBT_NUM-1 downto 0);
+
+ signal l1id : std_logic_vector(15 downto 0) := (others => '0');
+ signal l1id_buf : std_logic_vector(15 downto 0) := (others => '0');
+ signal l1a, l1a_d : std_logic := '0';
+ signal l1a_int_trigger : std_logic := '0';
+ signal l1a_int_trigger_d : std_logic := '0';
+
+ signal m_axis : axis_32_2d_array_type(0 to GBT_NUM-1, 0 to STREAMS_TOHOST-1);
+ signal m_axis_aclk : std_logic;
+ type array_2d_8b is array (natural range <>, natural range <>) of std_logic_vector(7 downto 0);
+ type array_2d_3b is array (natural range <>, natural range <>) of std_logic_vector(2 downto 0);
+ type array_2d_1b is array (natural range <>, natural range <>) of std_logic;
+ signal epath_enabled : array_2d_1b(GBT_NUM-1 downto 0, STREAMS_TOHOST-3 downto 0);
+ signal epath_aligned : array_2d_1b(GBT_NUM-1 downto 0, STREAMS_TOHOST-3 downto 0);
+ signal epath_width : array_2d_3b(GBT_NUM-1 downto 0, STREAMS_TOHOST-3 downto 0);
+ signal data_good : array_2d_1b(GBT_NUM-1 downto 0, STREAMS_TOHOST-3 downto 0);
+
+ signal epath_enabled_slv : std_logic_vector((STREAMS_TOHOST-2)*GBT_NUM-1 downto 0);
+ signal epath_aligned_slv : std_logic_vector((STREAMS_TOHOST-2)*GBT_NUM-1 downto 0);
+ signal epath_aligned_d_slv : std_logic_vector((STREAMS_TOHOST-2)*GBT_NUM-1 downto 0) := (others => '0');
+ signal epath_aligned_dd_slv : std_logic_vector((STREAMS_TOHOST-2)*GBT_NUM-1 downto 0) := (others => '0');
+ signal data_good_slv : std_logic_vector((STREAMS_TOHOST-2)*GBT_NUM-1 downto 0) := (others => '0');
+ signal chunk_size : array_2d_8b(GBT_NUM-1 downto 0, STREAMS_TOHOST-3 downto 0);
+
+ signal count_final : std_logic_vector(4 downto 0) := (others => '0');
+ signal enabled_aligned : array_2b(15 downto 0) := (others => (others => '0'));
+ signal timeout : boolean := false;
+begin
+
+ --clocks
+
+ clk160_tmp <= not clk160_tmp after clk40_period/8; --160 MHZ
+ clk160 <= clk160_tmp when clk_en else '0';
+ clk240_tmp <= not clk240_tmp after clk40_period/12; --240 MHZ
+ clk240 <= clk240_tmp when clk_en else '0';
+ clk320_tmp <= not clk320_tmp after clk40_period/16; --320 MHZ
+ clk320 <= clk320_tmp when clk_en else '0';
+
+ cnt_div_max <= "11" when FIRMWARE_MODE = 11 else "10" when FIRMWARE_MODE = 6 else "00";
+ clk_prcss <= clk320 when FIRMWARE_MODE = 11 else clk240 when FIRMWARE_MODE = 6 else '0';
+ clk40 <= clk40_tmp;
+ process(clk_prcss) --clk40 needs to be in sync with clk240 for GBT and clk320 for LPGBT
+ begin
+ if rising_edge(clk_prcss) then
+ if cnt_div = cnt_div_max then
+ cnt_div <= "00";
+ clk40_tmp <= not clk40_tmp;
+ else
+ cnt_div <= cnt_div + "01";
+ end if;
+ end if;
+ end process;
+
+
+ --Link Configuration
+ g_lane_control : for link in 0 to GBT_NUM-1 generate
+ signal elink_output_width : array_of_slv_2_0(NUMELINKmax-1 downto 0) := (others => "111");
+ signal elink_enable : std_logic_vector(NUMELINKmax-1 downto 0) := (others => '1');
+ signal data_format : std_logic_vector(1 downto 0);
+ begin
+ lane_control(link).global.framegen_reset <= '0';
+ lane_control(link).global.elink_sync <= '0';
+ lane_control(link).global.framegen_data_select <= '0';
+ lane_control(link).global.emu_data_select <= '1';
+ lane_control(link).global.l1a_source <= '0';
+ lane_control(link).global.loopback_fifo_delay <= "00010";
+ lane_control(link).global.loopback_fifo_reset <= '0';
+ lane_control(link).global.a_ch_bit_sel <= "0000001";
+ lane_control(link).global.b_ch_bit_sel <= "0000010";
+ lane_control(link).global.MSB <= '1';
+ lane_control(link).global.FEC <= '0';
+ lane_control(link).global.DATARATE <= '1';
+ lane_control(link).global.aligned <= '1';
+ lane_control(link).global.l1a_max_count <= x"0000190";
+
+ lane_control(link).fmemu_random.FMEMU_RANDOM_CONTROL.SELECT_RANDOM <= select_random;
+ lane_control(link).fmemu_random.FMEMU_RANDOM_CONTROL.SEED <= "1000000000"; --0x200
+ lane_control(link).fmemu_random.FMEMU_RANDOM_CONTROL.POLYNOMIAL <= "1001000000"; --0x240
+ lane_control(link).fmemu_random.FMEMU_RANDOM_RAM_ADDR <= "0000000000";
+ lane_control(link).fmemu_random.FMEMU_RANDOM_RAM.WE <= "0";
+ lane_control(link).fmemu_random.FMEMU_RANDOM_RAM.CHANNEL_SELECT <= (others=>'0');
+ lane_control(link).fmemu_random.FMEMU_RANDOM_RAM.DATA <= (others=>'0');
+
+ lane_control(link).emulator(0).output_width <= "010" when FIRMWARE_MODE = 11 else "000" when FIRMWARE_MODE = 6 else "000";-- 8b 2b
+ lane_control(link).emulator(1).output_width <= "010" when FIRMWARE_MODE = 11 else "000" when FIRMWARE_MODE = 6 else "000";-- 8b 2b
+ lane_control(link).emulator(2).output_width <= "011" when FIRMWARE_MODE = 11 else "001" when FIRMWARE_MODE = 6 else "000";--16b 4b
+ lane_control(link).emulator(3).output_width <= "011" when FIRMWARE_MODE = 11 else "001" when FIRMWARE_MODE = 6 else "000";--16b 4b
+ lane_control(link).emulator(4).output_width <= "100" when FIRMWARE_MODE = 11 else "010" when FIRMWARE_MODE = 6 else "000";--32b 8b
+ lane_control(link).emulator(5).output_width <= "100";--32b
+ lane_control(link).emulator(6).output_width <= "100";--32b
+
+ data_format <= "01";
+
+ g_emu_control : for egroup in lane_control(link).emulator'range generate
+ lane_control(link).emulator(egroup).pattern_select <= "00";
+ lane_control(link).emulator(egroup).data_format <= data_format;
+ lane_control(link).emulator(egroup).sw_busy <= '0';
+ lane_control(link).emulator(egroup).reset <= '0';--emu_reset;
+ lane_control(link).emulator(egroup).chunk_length <= X"003C"; --60+8
+ lane_control(link).emulator(egroup).userdata <= X"ABCD";
+
+ less_that_five : if egroup<5 generate
+ elink_enable(egroup*16+7 downto egroup*16) <= X"FF" when (lane_control(link).emulator(egroup).output_width <= "000") else
+ X"55" when (lane_control(link).emulator(egroup).output_width <= "001") else
+ X"11" when (lane_control(link).emulator(egroup).output_width <= "010") else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "011") else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "100");
+ elink_enable(egroup*16+15 downto egroup*16+8) <= X"FF" when (lane_control(link).emulator(egroup).output_width <= "000" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"55" when (lane_control(link).emulator(egroup).output_width <= "001" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"11" when (lane_control(link).emulator(egroup).output_width <= "010" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "011" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"00";
+ end generate less_that_five;
+ five : if egroup=5 generate
+ elink_enable(egroup*16+7 downto egroup*16) <= X"FF" when (lane_control(link).emulator(egroup).output_width <= "000" and FIRMWARE_MODE = 11) else
+ X"55" when (lane_control(link).emulator(egroup).output_width <= "001" and FIRMWARE_MODE = 11) else
+ X"11" when (lane_control(link).emulator(egroup).output_width <= "010" and FIRMWARE_MODE = 11) else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "011" and FIRMWARE_MODE = 11) else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "100" and FIRMWARE_MODE = 11) else
+ X"00";
+ elink_enable(egroup*16+15 downto egroup*16+8) <= X"FF" when (lane_control(link).emulator(egroup).output_width <= "000" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"55" when (lane_control(link).emulator(egroup).output_width <= "001" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"11" when (lane_control(link).emulator(egroup).output_width <= "010" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "011" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"00";
+ end generate five;
+ six : if egroup=6 generate
+ elink_enable(egroup*16+7 downto egroup*16) <= X"FF" when (lane_control(link).emulator(egroup).output_width <= "000" and FIRMWARE_MODE = 11 and lane_control(link).global.FEC = '0') else
+ X"55" when (lane_control(link).emulator(egroup).output_width <= "001" and FIRMWARE_MODE = 11 and lane_control(link).global.FEC = '0') else
+ X"11" when (lane_control(link).emulator(egroup).output_width <= "010" and FIRMWARE_MODE = 11 and lane_control(link).global.FEC = '0') else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "011" and FIRMWARE_MODE = 11 and lane_control(link).global.FEC = '0') else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "100" and FIRMWARE_MODE = 11 and lane_control(link).global.FEC = '0') else
+ X"00";
+ elink_enable(egroup*16+15 downto egroup*16+8) <= X"FF" when (lane_control(link).emulator(egroup).output_width <= "000" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1' and lane_control(link).global.FEC = '0') else
+ X"55" when (lane_control(link).emulator(egroup).output_width <= "001" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1' and lane_control(link).global.FEC = '0') else
+ X"11" when (lane_control(link).emulator(egroup).output_width <= "010" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1' and lane_control(link).global.FEC = '0') else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "011" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1' and lane_control(link).global.FEC = '0') else
+ X"00";
+ end generate six;
+ width : for k in 0 to 7 generate
+ elink_output_width(egroup*16+k) <= lane_control(link).emulator(egroup).output_width;
+ elink_output_width(egroup*16+k+8) <= lane_control(link).emulator(egroup).output_width when (FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else "111";
+ end generate width;
+
+ end generate g_emu_control;
+
+ g_elink_control : for epath in lane_control(link).elink'range generate
+ lane_control(link).elink(epath).input_width <= '0' when data_format = "00" else '1';
+ lane_control(link).elink(epath).endian_mode <= '0';
+ lane_control(link).elink(epath).enable <= elink_enable(epath);
+ lane_control(link).elink(epath).output_width <= elink_output_width(epath);
+ end generate g_elink_control;
+
+ end generate g_lane_control;
+
+ --FELIG emulator wrapper
+
+ g_lw_signals : for i in 0 to GBT_NUM-1 generate
+ signal count_max : std_logic_vector(2 downto 0);
+ signal count : std_logic_vector(2 downto 0) := "000";
+ begin
+ clkTX(i) <= clk320 when FIRMWARE_MODE = 11 else clk240 when FIRMWARE_MODE = 6 else '0';
+ count_max <= "111" when FIRMWARE_MODE = 11 else "101" when FIRMWARE_MODE = 6 else "000";
+ process(clkTX(i))
+ begin
+ if rising_edge(clkTX(i)) then
+ if count = count_max then
+ count <= "000";
+ link_tx_flag(i) <= '1';
+ else
+ count <= count + "001";
+ link_tx_flag(i) <= '0';
+ end if;
+ end if;
+ end process;
+ end generate g_lw_signals;
+
+ clkRX <= clkTX;
+ --link_rx_flag <= link_tx_flag;
+
+ FELIG_emu : entity work.EmulatorWrapper
+ generic map(
+ GBT_NUM => GBT_NUM,
+ NUMELINKmax => NUMELINKmax,
+ NUMEGROUPmax => NUMEGROUPmax,
+ FIRMWARE_MODE => FIRMWARE_MODE)
+ port map (
+ clk40 => clk40,
+ gt_txusrclk_in => clkTX,
+ gt_rxusrclk_in => clkRX,
+ link_tx_data_228b_array_out => link_tx_data,
+ data_ready_tx_out => link_tx_valid,
+ link_rx_data_120b_array_in => (others => (others => '0')),
+ link_tx_flag_in => link_tx_flag,
+ link_rx_flag_in => (others => '0'),--link_rx_flag,
+ l1a_int_trigger_out => l1a_int_trigger,
+ lane_control => lane_control,
+ lane_monitor => lane_monitor
+ );
+
+ l1id <= lane_monitor(0).global.l1a_id(15 downto 0);
+ process(clk40)
+ begin
+ if rising_edge(clk40) then
+ l1id_buf <= l1id;
+ if l1id_buf /= l1id then
+ l1a <= '1';
+ else
+ l1a <= '0';
+ end if;
+ end if;
+ end process;
+
+ --decoding lpgbt
+ g_dec_LPGBT: if FIRMWARE_MODE = 11 generate
+ signal lpGBT_UPLINK_USER_DATA : txrx224b_type(0 to GBT_NUM-1);
+ signal AlignmentPulseAlign : std_logic;
+ signal AlignmentPulseDeAlign : std_logic;
+ begin
+ m_axis_aclk <= clk240;
+ pulsegen0: entity work.AlignmentPulseGen
+ generic map(
+ MAX_VAL_DEALIGN => 2048, --2048 bytes at 8b10b / 80 Mb/s elink.
+ MAX_VAL_ALIGN => 20 --2 bytes at 8b10b / 80 Mb/s elink.
+ )
+ port map(
+ clk40 => clk40,
+ AlignmentPulseAlign => AlignmentPulseAlign,
+ AlignmentPulseDeAlign => AlignmentPulseDeAlign
+ );
+ g_Links : for link in 0 to GBT_NUM-1 generate
+ begin
+ process(clk40)
+ begin
+ if rising_edge(clk40) then
+ lpGBT_UPLINK_USER_DATA(link) <= link_tx_data(link)(223 downto 0);
+ end if;
+ end process;
+ g_Egroups: for egroup in 0 to 6 generate
+ signal ElinkWidth : std_logic_vector(2 downto 0);
+ signal PathEnable : std_logic_vector(3 downto 0);
+ signal ElinkAligned : std_logic_vector(3 downto 0);
+ signal m_axis_s : axis_32_array_type(0 to 3);
+ begin
+ g_axisindex: for i in 0 to 3 generate
+ m_axis(link,egroup*4+i) <= m_axis_s(i);
+ end generate;
+ ElinkWidth <= lane_control(link).emulator(egroup).output_width;
+ PathEnable <= "1111" when ElinkWidth = "010" else
+ "0101" when ElinkWidth = "011" else
+ "0001" when ElinkWidth = "100" else
+ "0000";
+
+ g_epaths : for epath in 0 to 3 generate
+ epath_width(link,egroup*4+epath) <= lane_control(link).emulator(egroup).output_width;
+ epath_enabled(link,egroup*4+epath) <= PathEnable(epath);
+ epath_aligned(link,egroup*4+epath) <= ElinkAligned(epath);
+ end generate;
+ --! Instantiate one Egroup.
+ eGroup0: entity work.DecEgroup_8b10b
+ generic map(
+ BLOCKSIZE => 1024,
+ Support32bWidth => '1',
+ Support16bWidth => '1',
+ Support8bWidth => '1',
+ IncludeElinks => "1111",
+ VERSAL => false
+ )
+ port map(
+ clk40 => clk40,
+ daq_reset => reset,
+ daq_fifo_flush => '0',
+ DataIn => lpGBT_UPLINK_USER_DATA(link)(egroup*32+31 downto egroup*32),
+ EnableIn => PathEnable,
+ LinkAligned => lane_control(link).global.aligned,
+ ElinkWidth => ElinkWidth,
+ AlignmentPulseAlign => AlignmentPulseAlign,
+ AlignmentPulseDeAlign => AlignmentPulseDeAlign,
+ AutoRealign => '1',
+ RealignmentEvent => open,
+ PathEncoding => x"1111", --"0001" per epath. All 8b10b encoded
+ ElinkAligned => ElinkAligned,
+ DecodingErrors => open,
+ MsbFirst => '1',
+ ReverseInputBits => (others => '0'),
+ HGTD_ALTIROC_DECODING => '0',
+ FE_BUSY_out => open,
+ m_axis => m_axis_s,
+ m_axis_tready => (others => '1'),
+ m_axis_aclk => m_axis_aclk,
+ m_axis_prog_empty => open
+ );
+ end generate g_Egroups;
+ end generate g_Links;
+ end generate g_dec_LPGBT;
+
+ g_dec_GBT: if FIRMWARE_MODE = 6 generate
+ type txrx80b_type is array (natural range <>) of std_logic_vector(79 downto 0);
+ signal GBT_UPLINK_USER_DATA : txrx80b_type(0 to GBT_NUM-1);
+ signal AlignmentPulseAlign : std_logic;
+ signal AlignmentPulseDeAlign : std_logic;
+ begin
+ m_axis_aclk <= clk160;
+ pulsegen0: entity work.AlignmentPulseGen
+ generic map(
+ MAX_VAL_DEALIGN => 2048, --2048 bytes at 8b10b / 80 Mb/s elink.
+ MAX_VAL_ALIGN => 20 --2 bytes at 8b10b / 80 Mb/s elink.
+ )
+ port map(
+ clk40 => clk40,
+ AlignmentPulseAlign => AlignmentPulseAlign,
+ AlignmentPulseDeAlign => AlignmentPulseDeAlign
+ );
+ g_Links : for link in 0 to GBT_NUM-1 generate
+ begin
+ process(clk40)
+ begin
+ if rising_edge(clk40) then
+ GBT_UPLINK_USER_DATA(link) <= link_tx_data(link)(111 downto 32);
+ end if;
+ end process;
+ g_Egroups: for egroup in 0 to 4 generate
+ signal ReverseElinks : std_logic_vector(7 downto 0);
+ signal ElinkWidth : std_logic_vector(2 downto 0);
+ signal PathEnable : std_logic_vector(7 downto 0);
+ signal EnableEgroupTruncation : std_logic;
+ signal DecoderAligned : std_logic_vector(7 downto 0);
+ signal m_axis_s : axis_32_array_type(0 to 7);
+ begin
+ g_axisindex: for i in 0 to 7 generate
+ m_axis(link,egroup*8+i) <= m_axis_s(i);
+ end generate;
+
+ ReverseElinks <= (others => '0');
+ ElinkWidth <= lane_control(link).emulator(egroup).output_width;
+ PathEnable <= "11111111" when ElinkWidth = "000" else
+ "01010101" when ElinkWidth = "001" else
+ "00010001" when ElinkWidth = "010" else
+ "00000001" when ElinkWidth = "011" else
+ "00000000";
+ EnableEgroupTruncation <= '0'; --to_sl(register_map_control.DECODING_EGROUP_CTRL(link mod 12)(egroup).ENABLE_TRUNCATION);
+
+ g_epaths : for epath in 0 to 7 generate
+ epath_width(link,egroup*8+epath) <= lane_control(link).emulator(egroup).output_width;
+ epath_enabled(link,egroup*8+epath) <= PathEnable(epath);
+ epath_aligned(link,egroup*8+epath) <= DecoderAligned(epath);
+ end generate;
+
+ eGroup0: entity work.DecodingEgroupGBT
+ generic map(
+ INCLUDE_16b => '1',
+ INCLUDE_8b => '1',
+ INCLUDE_4b => '1',
+ INCLUDE_2b => '1',
+ INCLUDE_8b10b => '1',
+ INCLUDE_HDLC => '0',
+ INCLUDE_DIRECT => '0',
+ BLOCKSIZE => 1024,
+ USE_BUILT_IN_FIFO => x"AA",
+ GENERATE_FEI4B => false,
+ VERSAL => false
+ )
+ port map(
+ clk40 => clk40,
+ daq_reset => reset,
+ daq_fifo_flush => '0',
+ EpathEnable => PathEnable,
+ EpathEncoding => x"11111111", --"0001" per epath. All 8b10b encoded
+ ElinkWidth => ElinkWidth,
+ MsbFirst => '1',
+ ReverseInputBits => ReverseElinks,
+ EnableTruncation => EnableEgroupTruncation,
+ DecoderAligned => DecoderAligned,
+ EGroupData => GBT_UPLINK_USER_DATA(link)(egroup*16+15 downto egroup*16),
+ GBTAligned => lane_control(link).global.aligned,
+ FE_BUSY_out => open,
+ m_axis => m_axis_s,
+ m_axis_tready => (others => '1'),
+ m_axis_aclk => m_axis_aclk,
+ m_axis_prog_empty => open,
+ AlignmentPulseAlign => AlignmentPulseAlign,
+ AlignmentPulseDeAlign => AlignmentPulseDeAlign,
+ AutoRealign => '1',
+ RealignmentEvent => open
+ );
+
+ end generate g_Egroups;
+ end generate g_Links;
+ end generate g_dec_GBT;
+
+ --checking data
+ g_checking_data : for link in 0 to GBT_NUM-1 generate
+ g_Streams: for stream in 0 to STREAMS_TOHOST-3 generate
+ signal data : std_logic_vector(31 downto 0);
+ signal data10b : std_logic_vector(9 downto 0);
+ signal valid : std_logic;
+ signal last : std_logic;
+ signal keep : std_logic_vector(3 downto 0);
+ signal count8b : std_logic_vector(1 downto 0) := "00";
+ signal count_chunks : std_logic_vector(6 downto 0);
+ signal checked : std_logic := '0';
+ signal check_words : std_logic := '0';
+ signal check_length : std_logic := '0';
+ signal reset_v_ch : std_logic := '0';
+ signal width : std_logic_vector(7 downto 0);
+ signal exp_checks : std_logic_vector(6 downto 0) := (others => '0');
+ signal cnt_checks : std_logic_vector(6 downto 0) := (others => '0');
+ signal good : std_logic := '0';
+ begin
+ data <= m_axis(link,stream).tdata when epath_aligned(link,stream) = '1' and epath_enabled(link,stream) = '1' else (others => '0');
+ valid <= m_axis(link,stream).tvalid when epath_aligned(link,stream) = '1' and epath_enabled(link,stream) = '1' else '0';
+ last <= m_axis(link,stream).tlast when epath_aligned(link,stream) = '1' and epath_enabled(link,stream) = '1' else '0';
+ keep <= m_axis(link,stream).tkeep when epath_aligned(link,stream) = '1' and epath_enabled(link,stream) = '1' else (others => '0');
+ width <= "00000010" when epath_width(link,stream) = "000" else
+ "00000100" when epath_width(link,stream) = "001" else
+ "00001000" when epath_width(link,stream) = "010" else
+ "00010000" when epath_width(link,stream) = "011" else
+ "00100000" when epath_width(link,stream) = "100" else
+ "00000000";
+ --data_good(link,stream) <= '0' when stream = 24 else good;
+ data_good(link,stream) <= good;
+
+ process(m_axis_aclk)
+ begin
+ if rising_edge(m_axis_aclk) then
+ if count8b = "00" and valid = '0' then
+ count8b <= count8b;
+ elsif count8b = "11" then
+ count8b <= "00";
+ else
+ count8b <= count8b + "01";
+ end if;
+ end if;
+ end process;
+ data10b <= "11" & data( 7 downto 0) when count8b = "00" and valid = '1' and keep(0) = '1' and keep(3 downto 1) = "000" and last = '1' else
+ "01" & data( 7 downto 0) when count8b = "00" and valid = '1' and keep(0) = '1' else
+ "11" & data(15 downto 8) when count8b = "01" and keep(1) = '1' and keep(3 downto 2) = "00" and last = '1' else
+ "01" & data(15 downto 8) when count8b = "01" and keep(1) = '1' else
+ "11" & data(23 downto 16) when count8b = "01" and keep(2) = '1' and keep(3) = '0' and last = '1' else
+ "01" & data(23 downto 16) when count8b = "10" and keep(2) = '1'else
+ last & "1" & data(31 downto 24) when count8b = "11" and keep(3) = '1'else
+ (others=> '0');
+ process(m_axis_aclk)
+ variable v_chunks : integer := 0;
+ variable size : integer := 0;
+ variable next_w : integer := 0;
+ variable next_b : integer := 0;
+ begin
+ if rising_edge(m_axis_aclk) then
+ if data10b(9 downto 8) = "01" then
+ v_chunks := v_chunks + 1;
+ reset_v_ch <= '0';
+ --check_length <= '0';
+ elsif data10b(9 downto 8) = "11" then
+ v_chunks := v_chunks + 1;
+ reset_v_ch <= '1';
+ if v_chunks = size + 8 then --size + header
+ check_length <= '1';
+ --else
+ --check_length <= '0';
+ end if;
+ elsif data10b(9 downto 8) = "00" then
+ --check_length <= '0';
+ if reset_v_ch = '1' then
+ if v_chunks = 0 then
+ cnt_checks <= (others => '0');
+ reset_v_ch <= '0';
+ else
+ v_chunks := 0;
+ end if;
+ else
+ reset_v_ch <= '0';
+ end if;
+ end if;
+
+ count_chunks <= std_logic_vector(to_unsigned(v_chunks, count_chunks'length));
+ exp_checks <= std_logic_vector(to_unsigned(5 + size/2, exp_checks'length));
+
+ if v_chunks = 1 and data10b(7 downto 0) = x"aa" and data10b(8) = '1' then --checks first byte
+ check_words <= '1';
+ elsif v_chunks = 3 and data10b(8) = '1' then
+ size := to_integer(unsigned(data10b(7 downto 0)));
+ chunk_size(link,stream) <= data10b(7 downto 0);
+ elsif v_chunks = 5 and data10b(7 downto 0) = l1id(7 downto 0) and data10b(8) = '1' then
+ check_words <= '1';
+ next_w := 10;
+ next_b := size - 2;
+ elsif v_chunks = 6 and data10b(7 downto 0) = x"bb" and data10b(8) = '1'then
+ check_words <= '1';
+ elsif v_chunks = 7 and data10b(7 downto 0) = x"aa" and data10b(8) = '1'then
+ check_words <= '1';
+ elsif v_chunks = 8 and data10b(7 downto 0) = width and data10b(8) = '1' then
+ check_words <= '1';
+ elsif v_chunks = next_w and data10b(7 downto 0) = std_logic_vector(to_unsigned(next_b,8)) and data10b(8) = '1' then
+ check_words <= '1';
+ next_w := next_w + 2;
+ if next_b > 1 then
+ next_b := next_b - 2;
+ end if;
+ else
+ check_words <= '0';
+ end if;
+
+ if check_words = '1' then
+ cnt_checks <= cnt_checks + '1';
+ end if;
+
+ if cnt_checks = exp_checks and check_length = '1' then
+ check_length <= '0';
+ good <= '1';
+ end if;
+
+ if l1a = '1' then --new trigger
+ good <= '0';
+ end if;
+ end if;
+ end process;
+ end generate g_Streams;
+ end generate g_checking_data;
+
+ process(m_axis_aclk)
+ variable count_f : integer := 0;
+ begin
+ if rising_edge(m_axis_aclk) then
+ reset_d <= reset;
+ l1a_d <= l1a;
+ l1a_int_trigger_d <= l1a_int_trigger;
+ if l1a_int_trigger = '1' and l1a_int_trigger_d = '0' then
+ epath_aligned_d_slv <= epath_aligned_slv;
+ epath_aligned_dd_slv <= epath_aligned_d_slv; --delaying again because l1a_int_trigger comes before l1a so comparison wouldnt work
+ end if;
+ if l1a_d = '0' and l1a = '1'then
+ count_f := count_f + 1;
+ if data_good_slv = epath_aligned_dd_slv and count_f <= 16 then
+ count_final <= count_final + '1';
+ if epath_aligned_dd_slv = epath_enabled_slv then
+ enabled_aligned(count_f-1) <= "11";
+ else
+ enabled_aligned(count_f-1) <= "01";
+ end if;
+ end if;
+ elsif l1a_d = '1' and l1a = '0' then
+ log(ID_MONITOR,"enabled_aligned value is "&to_string(enabled_aligned(count_f-1),HEX)&". 0: data bad, 1: data good but not all decoders aligned, 3: data goot and aligned", C_SCOPE);
+ end if;
+ end if;
+ end process;
+
+ g_to_slv_link : for link in 0 to GBT_NUM-1 generate
+ g_to_slv_stream: for stream in 0 to STREAMS_TOHOST-3 generate
+ epath_enabled_slv(link*(STREAMS_TOHOST-2)+stream) <= epath_enabled(link,stream);
+ epath_aligned_slv(link*(STREAMS_TOHOST-2)+stream) <= epath_aligned(link,stream);
+ data_good_slv(link*(STREAMS_TOHOST-2)+stream) <= data_good(link,stream);
+ end generate g_to_slv_stream;
+ end generate g_to_slv_link;
+
+ --sim process
+ mainproc : process
+ variable vcnt : std_logic_vector(4 downto 0);
+ begin
+ assert false
+ report "START SIMULATION"
+ severity NOTE;
+ clk_en <= true;
+ reset <= '0';
+ select_random <= "0";
+ wait for 2 ns;
+ reset <= '1';
+ wait for 50 ns;
+ reset <= '0';
+ log(ID_MONITOR,"chunk size fixed to "&to_string(lane_control(0).emulator(0).chunk_length,DEC), C_SCOPE);
+ while true loop
+ wait until l1a = '1' or timeout;
+ if l1id /= "0000000000000000" then
+ log(ID_MONITOR,"TRIGGER NUMBER "&to_string(l1id,DEC), C_SCOPE);
+ for link in 0 to GBT_NUM-1 loop
+ for stream in 0 to STREAMS_TOHOST-3 loop
+ if epath_enabled(link,stream) = '1' then
+ log(ID_MONITOR,"LINK "&to_string(link)&
+ " EPATH "&to_string(stream)&
+ " ENABLED "&to_string(epath_enabled(link,stream))&
+ " ALIGNED "&to_string(epath_aligned(link,stream))&
+ " SIZE "&to_string(chunk_size(link,stream),DEC)&
+ " DATA GOOD "&to_string(data_good(link,stream))
+ , C_SCOPE);
+ end if;
+ end loop;
+ end loop;
+ end if;
+ wait for 1 ns;
+ if timeout or l1id = "0000000000010000" then
+ exit;
+ elsif l1id = "0000000000000111" then
+ select_random <= "1";
+ end if;
+ end loop;
+ wait for 1 us;
+
+ vcnt := count_final;
+ check_value(vcnt,l1id(4 downto 0), ERROR, "Verifying the number of triggers with good data",C_SCOPE);
+ check_value(timeout,false, ERROR, "Timeout check",C_SCOPE);
+ report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
+ log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
+
+ -- Finish the simulation
+ if use_vunit = false then
+ std.env.stop;
+ end if;
+ uvvm_completed <= '1';
+ wait; -- to stop completely
+ finish;
+ wait for 1000 us;
+ end process;
+
+ --timeout
+ timeoutproc : process
+ begin
+ wait for 1000 us;
+ timeout <= true;
+ end process;
+end tb;
+
diff --git a/simulation/UVVMtests/tb/FELIGexternaltrigger_tb.vhd b/simulation/UVVMtests/tb/FELIGexternaltrigger_tb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a385fad8daebfe226a2fc9b433bc1c7349324210
--- /dev/null
+++ b/simulation/UVVMtests/tb/FELIGexternaltrigger_tb.vhd
@@ -0,0 +1,512 @@
+--ricardo luz, argonne
+
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.numeric_std_unsigned.all;
+ use IEEE.std_logic_textio.all;
+
+ use std.env.all;
+ use std.textio.all;
+
+ use work.FELIX_package.all;
+ use work.pcie_package.all;
+ use work.axi_stream_package.all;
+ use work.centralRouter_package.all;
+ use work.type_lib.ALL;
+
+library xpm;
+ use xpm.vcomponents.all;
+
+library uvvm_util;
+ context uvvm_util.uvvm_util_context;
+
+entity FELIGexternaltrigger_tb is
+ generic(
+ use_vunit : boolean := false
+ );
+ port(
+ uvvm_completed: out std_logic := '0'
+ );
+end FELIGexternaltrigger_tb;
+
+architecture Behavioral of FELIGexternaltrigger_tb is
+ function FM_TO_PROTOCOL(FIRMWARE_MODE:integer)
+ return std_logic is
+ begin
+ if FIRMWARE_MODE = FIRMWARE_MODE_FELIG_GBT then
+ return '0';
+ elsif FIRMWARE_MODE = FIRMWARE_MODE_FELIG_LPGBT then
+ return '1';
+ else
+ return '0';
+ end if;
+ end function;
+ constant GBT_NUM : integer := 1;
+ constant FIRMWARE_MODE : integer := 11;
+ constant NUMELINKmax : integer := 112; --name number of epahts per egroup (theoretically 2b epath * 112=224, but never happens)
+ constant NUMEGROUPmax : integer := 7; --name number of egroups
+
+ constant clk40_period : time := 25 ns;
+ signal clk_en : boolean := false;
+ signal clk40 : std_logic;
+ signal clk40_tmp : std_logic := '0';
+ signal clk320 : std_logic;
+ signal clk320_tmp : std_logic := '0';
+ signal clk_prcss : std_logic := '0';
+ signal clkTX : std_logic_vector(GBT_NUM-1 downto 0);
+ signal clkRX : std_logic_vector(GBT_NUM-1 downto 0);
+ signal cnt_div : std_logic_vector(1 downto 0) := (others => '0');
+ signal cnt_div_max : std_logic_vector(1 downto 0) := (others => '0');
+
+ signal reset : std_logic;
+ signal reset_d : std_logic;
+
+ signal register_map_control : register_map_control_type;
+-- signal single_l1a_long : std_logic_vector(0 downto 0) := "0";
+-- signal single_ecr_long : std_logic_vector(0 downto 0) := "0";
+-- signal single_bcr_long : std_logic_vector(0 downto 0) := "0";
+ signal single_l1a_long : std_logic := '0';
+ signal single_ecr_long : std_logic := '0';
+ signal single_bcr_long : std_logic := '0';
+ signal enable_ttc : std_logic := '0';
+ signal TTCout : std_logic_vector(9 downto 0) := (others => '0');
+ signal TTCout320 : std_logic_vector(9 downto 0) := (others => '0');
+
+ signal lane_control : array_of_lane_control_type(GBT_NUM-1 downto 0);
+ signal lane_monitor : array_of_lane_monitor_type(GBT_NUM-1 downto 0);
+ signal aligned : std_logic := '0';
+
+ signal L1A : std_logic := '0';
+ signal L1A_count : std_logic_vector(7 downto 0) := (others => '0');
+ signal l1a_id_register_rst : std_logic := '0';
+ signal txrx_flag : std_logic := '0';
+ signal rx_data : std_logic_vector(119 downto 0) := (others => '0');
+ signal tx_data : std_logic_vector(227 downto 0) := (others => '0');
+ signal tx_eg_data : array_32b(NUMEGROUPmax-1 downto 0);
+ signal data_to_be_checked : std_logic_vector(7 downto 0) := (others => '0');
+ signal tx_rdy : std_logic := '0';
+ signal data_delay : std_logic_vector(7 downto 0) := (others => '0');
+ signal valid_delay : std_logic := '0';
+ signal data_count : std_logic_vector(31 downto 0) := (others => '0');
+ signal data_size : std_logic_vector(31 downto 0) := (others => '0');
+
+ signal emu_l1a_id : std_logic_vector(15 downto 0) := (others => '0');
+ signal emu_l1a_id_delay : std_logic_vector(15 downto 0) := (others => '0');
+ signal emu_l1a : std_logic := '0';
+ signal emu_l1a_40 : std_logic := '0';
+ signal next_l1a_id : std_logic_vector(15 downto 0) := x"0001";
+
+ signal check_words : std_logic := '0';
+ signal exp_checks : std_logic_vector(6 downto 0) := (others => '0');
+ signal cnt_checks : std_logic_vector(6 downto 0) := (others => '0');
+ signal good : std_logic := '0';
+
+ signal count_good_ids : std_logic_vector(7 downto 0) := (others => '0');
+ signal count_good_data : std_logic_vector(7 downto 0) := (others => '0');
+ signal count_triggers : std_logic_vector(7 downto 0) := (others => '0');
+
+ signal test : std_logic := '0';
+ signal timeout : boolean := false;
+begin
+
+ --clocks
+
+ clk320_tmp <= not clk320_tmp after clk40_period/16; --320 MHZ
+ clk320 <= clk320_tmp when clk_en else '0';
+
+ cnt_div_max <= "11";
+ clk_prcss <= clk320;
+ clk40 <= clk40_tmp;
+ process(clk_prcss)
+ begin
+ if rising_edge(clk_prcss) then
+ if cnt_div = cnt_div_max then
+ cnt_div <= "00";
+ clk40_tmp <= not clk40_tmp;
+ else
+ cnt_div <= cnt_div + "01";
+ end if;
+ end if;
+ end process;
+
+ --gen lane_control for FELIG
+
+ g_lane_control : for link in 0 to GBT_NUM-1 generate
+ signal elink_output_width : array_of_slv_2_0(NUMELINKmax-1 downto 0) := (others => "111");
+ signal elink_enable : std_logic_vector(NUMELINKmax-1 downto 0) := (others => '1');
+ signal data_format : std_logic_vector(1 downto 0);
+ begin
+ lane_control(link).global.framegen_reset <= '0';
+ lane_control(link).global.elink_sync <= '0';
+ lane_control(link).global.framegen_data_select <= '0';
+ lane_control(link).global.emu_data_select <= '1';
+ lane_control(link).global.l1a_source <= '1';--EXTERNAL TRIGGER
+ lane_control(link).global.loopback_fifo_delay <= "00010";
+ lane_control(link).global.loopback_fifo_reset <= '0';
+ lane_control(link).global.a_ch_bit_sel <= "0000000";
+ lane_control(link).global.b_ch_bit_sel <= "0000001";
+ lane_control(link).global.MSB <= '1';
+ lane_control(link).global.FEC <= '0';
+ lane_control(link).global.DATARATE <= '1';
+ lane_control(link).global.aligned <= aligned;
+ lane_control(link).global.l1a_max_count <= x"0000000";
+ lane_control(link).global.lane_reset <= '0';
+ lane_control(link).global.l1a_counter_reset <= l1a_id_register_rst;
+ lane_control(link).fmemu_random.FMEMU_RANDOM_CONTROL.SELECT_RANDOM <= "0";
+ lane_control(link).fmemu_random.FMEMU_RANDOM_CONTROL.SEED <= "1000000000"; --0x200
+ lane_control(link).fmemu_random.FMEMU_RANDOM_CONTROL.POLYNOMIAL <= "1001000000"; --0x240
+ lane_control(link).fmemu_random.FMEMU_RANDOM_RAM_ADDR <= "0000000000";
+ lane_control(link).fmemu_random.FMEMU_RANDOM_RAM.WE <= "0";
+ lane_control(link).fmemu_random.FMEMU_RANDOM_RAM.CHANNEL_SELECT <= (others=>'0');
+ lane_control(link).fmemu_random.FMEMU_RANDOM_RAM.DATA <= (others=>'0');
+
+ lane_control(link).emulator(0).output_width <= "010" when FIRMWARE_MODE = 11 else "000" when FIRMWARE_MODE = 6 else "000";-- 8b 2b
+ lane_control(link).emulator(1).output_width <= "010" when FIRMWARE_MODE = 11 else "000" when FIRMWARE_MODE = 6 else "000";-- 8b 2b
+ lane_control(link).emulator(2).output_width <= "011" when FIRMWARE_MODE = 11 else "001" when FIRMWARE_MODE = 6 else "000";--16b 4b
+ lane_control(link).emulator(3).output_width <= "011" when FIRMWARE_MODE = 11 else "001" when FIRMWARE_MODE = 6 else "000";--16b 4b
+ lane_control(link).emulator(4).output_width <= "100" when FIRMWARE_MODE = 11 else "010" when FIRMWARE_MODE = 6 else "000";--32b 8b
+ lane_control(link).emulator(5).output_width <= "100";--32b
+ lane_control(link).emulator(6).output_width <= "100";--32b
+
+ data_format <= "00";
+
+ g_emu_control : for egroup in lane_control(link).emulator'range generate
+ lane_control(link).emulator(egroup).pattern_select <= "00";
+ lane_control(link).emulator(egroup).data_format <= data_format;
+ lane_control(link).emulator(egroup).sw_busy <= '0';
+ lane_control(link).emulator(egroup).reset <= '0';--emu_reset;
+ lane_control(link).emulator(egroup).chunk_length <= X"003C"; --60+8
+ lane_control(link).emulator(egroup).userdata <= X"ABCD";
+
+ less_that_five : if egroup<5 generate
+ elink_enable(egroup*16+7 downto egroup*16) <= X"FF" when (lane_control(link).emulator(egroup).output_width <= "000") else
+ X"55" when (lane_control(link).emulator(egroup).output_width <= "001") else
+ X"11" when (lane_control(link).emulator(egroup).output_width <= "010") else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "011") else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "100");
+ elink_enable(egroup*16+15 downto egroup*16+8) <= X"FF" when (lane_control(link).emulator(egroup).output_width <= "000" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"55" when (lane_control(link).emulator(egroup).output_width <= "001" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"11" when (lane_control(link).emulator(egroup).output_width <= "010" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "011" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"00";
+ end generate less_that_five;
+ five : if egroup=5 generate
+ elink_enable(egroup*16+7 downto egroup*16) <= X"FF" when (lane_control(link).emulator(egroup).output_width <= "000" and FIRMWARE_MODE = 11) else
+ X"55" when (lane_control(link).emulator(egroup).output_width <= "001" and FIRMWARE_MODE = 11) else
+ X"11" when (lane_control(link).emulator(egroup).output_width <= "010" and FIRMWARE_MODE = 11) else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "011" and FIRMWARE_MODE = 11) else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "100" and FIRMWARE_MODE = 11) else
+ X"00";
+ elink_enable(egroup*16+15 downto egroup*16+8) <= X"FF" when (lane_control(link).emulator(egroup).output_width <= "000" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"55" when (lane_control(link).emulator(egroup).output_width <= "001" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"11" when (lane_control(link).emulator(egroup).output_width <= "010" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "011" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else
+ X"00";
+ end generate five;
+ six : if egroup=6 generate
+ elink_enable(egroup*16+7 downto egroup*16) <= X"FF" when (lane_control(link).emulator(egroup).output_width <= "000" and FIRMWARE_MODE = 11 and lane_control(link).global.FEC = '0') else
+ X"55" when (lane_control(link).emulator(egroup).output_width <= "001" and FIRMWARE_MODE = 11 and lane_control(link).global.FEC = '0') else
+ X"11" when (lane_control(link).emulator(egroup).output_width <= "010" and FIRMWARE_MODE = 11 and lane_control(link).global.FEC = '0') else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "011" and FIRMWARE_MODE = 11 and lane_control(link).global.FEC = '0') else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "100" and FIRMWARE_MODE = 11 and lane_control(link).global.FEC = '0') else
+ X"00";
+ elink_enable(egroup*16+15 downto egroup*16+8) <= X"FF" when (lane_control(link).emulator(egroup).output_width <= "000" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1' and lane_control(link).global.FEC = '0') else
+ X"55" when (lane_control(link).emulator(egroup).output_width <= "001" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1' and lane_control(link).global.FEC = '0') else
+ X"11" when (lane_control(link).emulator(egroup).output_width <= "010" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1' and lane_control(link).global.FEC = '0') else
+ X"01" when (lane_control(link).emulator(egroup).output_width <= "011" and FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1' and lane_control(link).global.FEC = '0') else
+ X"00";
+ end generate six;
+ width : for k in 0 to 7 generate
+ elink_output_width(egroup*16+k) <= lane_control(link).emulator(egroup).output_width;
+ elink_output_width(egroup*16+k+8) <= lane_control(link).emulator(egroup).output_width when (FIRMWARE_MODE = 11 and lane_control(link).global.DATARATE = '1') else "111";
+ end generate width;
+
+ end generate g_emu_control;
+
+ g_elink_control : for epath in lane_control(link).elink'range generate
+ lane_control(link).elink(epath).input_width <= '0' when data_format = "00" else '1';
+ lane_control(link).elink(epath).endian_mode <= '0';
+ lane_control(link).elink(epath).enable <= elink_enable(epath);
+ lane_control(link).elink(epath).output_width <= elink_output_width(epath);
+ end generate g_elink_control;
+
+ end generate g_lane_control;
+
+ --Generate FELIX TTC signals
+
+ process(clk40)
+ begin
+ if rising_edge(clk40) then
+ if L1A_count = x"8F" then
+ L1A_count <= x"00";
+ L1A <= '1';
+ count_triggers <= count_triggers + '1';
+ else
+ L1A_count <= L1A_count + x"01";
+ L1A <= '0';
+ if count_triggers = x"04" and L1A_count = x"08" then
+ single_ecr_long <= '1';
+ l1a_id_register_rst <= '0';
+ log(ID_MONITOR,"ECR issued", C_SCOPE);
+ elsif count_triggers = x"09" and L1A_count = x"1F" then
+ single_ecr_long <= '0';
+ l1a_id_register_rst <= '1';
+ log(ID_MONITOR,"L1A ID register reset used", C_SCOPE);
+ else
+ single_ecr_long <= '0';
+ l1a_id_register_rst <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ single_l1a_long <= L1A;
+ register_map_control.TTC_EMU.SEL(1) <= enable_ttc;
+ register_map_control.TTC_EMU.ENA(0) <= enable_ttc;
+ register_map_control.TTC_EMU_TP_DELAY <= x"00000040";
+ register_map_control.TTC_EMU_L1A_PERIOD <= x"00000000";
+ register_map_control.TTC_EMU_ECR_PERIOD <= x"00000000";
+ register_map_control.TTC_EMU_BCR_PERIOD <= x"00000dec";
+ register_map_control.TTC_EMU_LONG_CHANNEL_DATA <= x"00000000";
+ register_map_control.TTC_EMU_CONTROL.BROADCAST <= "000000";
+ register_map_control.TTC_EMU_RESET(64) <= reset;
+ register_map_control.TTC_EMU_CONTROL.L1A(24) <= single_l1a_long;
+ register_map_control.TTC_EMU_CONTROL.ECR(26) <= single_ecr_long;
+ register_map_control.TTC_EMU_CONTROL.BCR(25) <= single_bcr_long;
+ register_map_control.TTC_EMU_CONTROL.BUSY_IN_ENABLE <= "0";
+
+ TTCEmu: entity work.TTC_Emulator
+ port map(
+ Clock => clk40,
+ Reset => reset,
+ register_map_control => register_map_control,
+ add_s8 => open,
+ add_d8 => open,
+ add_strobe => open,
+ add_e => open,
+ TTCout => TTCout, -- : out std_logic_vector(9 downto 0)
+ BUSYIn => '0'
+ );
+
+
+ --cdr ttcout 40 to 320
+ process(clk320)
+ variable count : integer := 0;
+ begin
+ if rising_edge(clk320) then
+ TTCout320 <= TTCout;
+ if count = 7 then
+ count := 0;
+ txrx_flag <= '1';
+ else
+ count := count + 1;
+ txrx_flag <= '0';
+ end if;
+ end if;
+ end process;
+
+ --FELIG emulator
+
+ rx_data(1) <= TTCout320(1); --b channel
+ rx_data(0) <= TTCout320(0); --l1a
+
+ felig_emulator : entity work.emulator
+ generic map (
+ useGBTdataEmulator => false,
+ sim_emulator => false,
+ LANE_ID => 0,
+ PROTOCOL => FM_TO_PROTOCOL(FIRMWARE_MODE)
+ )
+ port map (
+ clk40 => clk40,
+ lane_rxclk => clk320,
+ lane_txclk => clk320,
+ l1a_int_trigger => '0',
+ l1a_int_int_id => (others => '0'),
+ l1a_trigger_out => emu_l1a,
+ gbt_tx_data_228b_out => tx_data,
+ data_ready_tx_out => tx_rdy,
+ gbt_rx_data_120b_in => rx_data,
+ gbt_tx_flag_in => txrx_flag,
+ gbt_rx_flag_in => txrx_flag,
+ lane_control => lane_control(0),
+ lane_monitor => lane_monitor(0)--,
+ );
+
+ emu_l1a_id <= lane_monitor(0).global.l1a_id(15 downto 0);
+
+ g_egroups : for eg in 0 to NUMEGROUPmax-1 generate --assuming LPGBT
+ tx_eg_data(eg) <= tx_data(32*(eg+1)-1 downto 32*eg);
+ end generate;
+
+ data_to_be_checked <= tx_data(7 downto 0); -- 1 epath of the 8b egroup
+
+ --gen data_valid
+
+ process(clk320)
+ variable count_l1a : integer := 0;
+ begin
+ if rising_edge(clk320) then
+ if aligned = '1' then
+ if tx_rdy = '1' then
+ data_delay <= data_to_be_checked;
+ if valid_delay = '1' then
+ data_count <= data_count + '1';
+ else
+ data_count <= (others => '0');
+ end if;
+
+ if data_count = x"00000002" then
+ data_size <= data_delay + x"00000008";
+ end if;
+
+ if data_count = data_size - x"00000001" and data_size /= x"00000000" then
+ valid_delay <= '0';
+ end if;
+ end if;
+ if data_to_be_checked /= data_delay then
+ valid_delay <= '1';
+ end if;
+ end if;
+ if emu_l1a = '1' then
+ count_l1a := count_l1a + 1;
+ emu_l1a_40 <= '1';
+ else
+ if count_l1a /= 0 then
+ if count_l1a = 8 then
+ count_l1a := 0;
+ emu_l1a_40 <= '0';
+ else
+ count_l1a := count_l1a + 1;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ --check_data (based on FELIGemulator_tb.vhd)
+
+ process(clk40)
+ variable v_chunks : integer := 0;
+ variable size : integer := 100;
+ variable next_w : integer := 100;
+ variable next_b : integer := 100;
+ variable flag_check : std_logic := '0';
+ begin
+ if rising_edge(clk40) then
+ if valid_delay = '1' then
+ v_chunks := v_chunks + 1;
+ else
+ v_chunks := 0;
+ end if;
+
+ if v_chunks = 1 and data_delay = x"aa" then --checks first byte
+ check_words <= '1';
+ flag_check := '1';
+ elsif v_chunks = 3 then
+ size := to_integer(unsigned(data_delay));
+ --chunk_size(link,stream) <= data_delay;
+ elsif v_chunks = 5 and data_delay = emu_l1a_id(7 downto 0) then
+ check_words <= '1';
+ next_w := 10;
+ next_b := size - 2;
+ elsif v_chunks = 6 and data_delay = x"bb" then
+ check_words <= '1';
+ elsif v_chunks = 7 and data_delay = x"aa" then
+ check_words <= '1';
+ elsif v_chunks = 8 and data_delay = x"8" then
+ check_words <= '1';
+ elsif v_chunks = next_w and data_delay = std_logic_vector(to_unsigned(next_b,8)) then
+ check_words <= '1';
+ next_w := next_w + 2;
+ if next_b > 1 then
+ next_b := next_b - 2;
+ end if;
+ else
+ check_words <= '0';
+ end if;
+
+ if check_words = '1' then
+ cnt_checks <= cnt_checks + '1';
+ end if;
+
+ exp_checks <= std_logic_vector(to_unsigned(5 + size/2, exp_checks'length));
+
+ if cnt_checks = exp_checks and aligned = '1' then
+ good <= '1';
+ end if;
+
+ if flag_check = '1' and emu_l1a_40 = '1' then
+ flag_check := '0';
+ cnt_checks <= (others => '0');
+ good <= '0';
+ if good = '1' then
+ count_good_data <= count_good_data + '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ --check l1a_id
+ process(clk40)
+ begin
+ if rising_edge(clk40) then
+ emu_l1a_id_delay <= emu_l1a_id;
+ if emu_l1a_id_delay /= emu_l1a_id then
+ if aligned = '1' then
+ log(ID_MONITOR,"L1A ID is " & to_string(emu_l1a_id,DEC), C_SCOPE);
+ end if;
+ if emu_l1a_id = next_l1a_id then
+ count_good_ids <= count_good_ids + '1';
+ next_l1a_id <= next_l1a_id + '1';
+ end if;
+ end if;
+ if single_ecr_long = '1' or l1a_id_register_rst = '1' then
+ next_l1a_id <= (others => '0');
+ end if;
+ end if;
+ end process;
+
+ --main process
+ mainproc : process
+ variable vcnt : std_logic_vector(4 downto 0);
+ begin
+ assert false
+ report "START SIMULATION"
+ severity NOTE;
+ clk_en <= true;
+ reset <= '0';
+ wait for 2 ns;
+ reset <= '1';
+ wait for 50 ns;
+ reset <= '0';
+ wait for 50 ns;
+ enable_ttc <= '1';
+ wait for 50 ns;
+ aligned <= '1';
+
+ wait until (count_triggers = x"0F" and L1A_count = x"4F") or timeout;
+ check_value(count_good_ids,count_triggers, ERROR, "Comparing count_good_ids with count_triggers",C_SCOPE);
+ check_value(count_good_data,count_triggers-'1', ERROR, "Comparing count_good_data with count_triggers",C_SCOPE);
+ check_value(timeout,false, ERROR, "Timeout check",C_SCOPE);
+ report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
+ log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
+
+ --Finish the simulation
+ if use_vunit = false then
+ std.env.stop;
+ end if;
+ uvvm_completed <= '1';
+ wait; -- to stop completely
+ finish;
+ wait for 1000 us;
+ end process;
+
+ --timeout
+ timeoutproc : process
+ begin
+ wait for 500 us;
+ timeout <= true;
+ end process;
+end Behavioral;
diff --git a/simulation/UVVMtests/tb/FELIGlinkwrapperLPGBT_tb.vhd b/simulation/UVVMtests/tb/FELIGlinkwrapperLPGBT_tb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a0d0c6ed63c9971bab5c8667034b1f3762bcf765
--- /dev/null
+++ b/simulation/UVVMtests/tb/FELIGlinkwrapperLPGBT_tb.vhd
@@ -0,0 +1,346 @@
+--ricardo luz, argonne
+--based on simulation/FELIG/felig_lpgbt_sim.vhd
+
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.numeric_std_unsigned.all;
+ use IEEE.std_logic_textio.all;
+
+ use std.env.all;
+ use std.textio.all;
+
+ use work.FELIX_package.all;
+ use work.pcie_package.all;
+ use work.axi_stream_package.all;
+ use work.centralRouter_package.all;
+ use work.type_lib.ALL;
+
+library xpm;
+ use xpm.vcomponents.all;
+
+library uvvm_util;
+ context uvvm_util.uvvm_util_context;
+
+entity FELIGlinkwrapperLPGBT_tb is
+ generic(
+ use_vunit : boolean := false
+ );
+ port(
+ uvvm_completed: out std_logic := '0'
+ );
+end FELIGlinkwrapperLPGBT_tb;
+
+architecture Behavioral of FELIGlinkwrapperLPGBT_tb is
+
+ constant GBT_NUM : integer := 1;
+
+ constant clk40_period : time := 25 ns;
+ signal clk_en : boolean := false;
+ signal clk40 : std_logic;
+ signal clk40_tmp : std_logic := '0';
+ signal clk320 : std_logic;
+ signal clk320_tmp : std_logic := '0';
+ signal clk_prcss : std_logic := '0';
+ signal cnt_div : std_logic_vector(1 downto 0) := (others => '0');
+ signal cnt_div_max : std_logic_vector(1 downto 0) := (others => '0');
+
+ signal reset : std_logic := '0';
+ signal reset_done : std_logic := '0';
+ signal reset_clk40 : std_logic := '0';
+ signal reset_done_clk40 : std_logic := '0';
+
+ type data16barray is array (0 to GBT_NUM-1) of std_logic_vector(15 downto 0);
+ type data32barray is array (0 to GBT_NUM-1) of std_logic_vector(31 downto 0);
+ type txrx234b_48ch_type is array (GBT_NUM-1 downto 0) of std_logic_vector(233 downto 0);
+ type txrx36b_48ch_type is array (GBT_NUM-1 downto 0) of std_logic_vector(35 downto 0);
+
+ --lpgbt BE
+ signal alignment_done_BE : std_logic_vector(GBT_NUM-1 downto 0);
+ signal data_rdy_BE : std_logic_vector(GBT_NUM-1 downto 0);
+ signal RxSlide_BE : std_logic_vector(GBT_NUM-1 downto 0);
+ signal TX_DATA_BE : data16barray := (others => ("0000000000000000"));
+ signal uplinkData_i_BE : txrx234b_48ch_type;
+ signal fec_error_i_BE : std_logic_vector(GBT_NUM-1 downto 0);
+ signal fec_err_cnt_i_BE : array_32b(0 to GBT_NUM-1);
+
+ --lpgbt FE
+ signal RxSlide_FE : std_logic_vector(GBT_NUM-1 downto 0);
+ signal alignment_done_FE : std_logic_vector(GBT_NUM-1 downto 0);
+ signal sta_headerFlag_out_FE : std_logic_vector(GBT_NUM-1 downto 0);
+ signal TX_DATA_FE : data32barray := (others => ("00000000000000000000000000000000"));
+ signal downLinkData_i_FE : txrx36b_48ch_type;
+ signal tx_flag_out_FE : std_logic_vector(GBT_NUM-1 downto 0);
+
+ --data
+ signal data_to_be : std_logic_vector(223 downto 0) := (others => '0');
+ signal data_to_fe : std_logic_vector(31 downto 0) := (others => '0');
+
+ --check
+ signal aligned : std_logic := '0';
+ signal good_FE : std_logic_vector(GBT_NUM-1 downto 0) := (others => '0');
+ signal good_BE : std_logic_vector(GBT_NUM-1 downto 0) := (others => '0');
+ constant GBT_one : std_logic_vector(GBT_NUM-1 downto 0) := (others => '1');
+
+ signal timeout : boolean := false;
+begin
+
+ --clocks
+
+ clk320_tmp <= not clk320_tmp after clk40_period/16; --320 MHZ
+ clk320 <= clk320_tmp when clk_en else '0';
+
+ cnt_div_max <= "11";
+ clk_prcss <= clk320;
+ clk40 <= clk40_tmp;
+
+ process(clk_prcss)
+ begin
+ if rising_edge(clk_prcss) then
+ if cnt_div = cnt_div_max then
+ cnt_div <= "00";
+ clk40_tmp <= not clk40_tmp;
+ else
+ cnt_div <= cnt_div + "01";
+ end if;
+ end if;
+ end process;
+
+ --reset
+
+ process(clk40)
+ begin
+ if clk40'event and clk40='1' then
+ reset_clk40 <= reset;
+ reset_done_clk40 <= reset_done;
+ data_to_be <= data_to_be + x"1";
+ data_to_fe <= data_to_fe + x"1";
+ end if;
+ end process;
+
+ -- lpgbt FELIX
+ link_loop_BE : for i in 0 to GBT_NUM-1 generate
+ signal downlinkUserData_i : std_logic_vector(31 downto 0);
+ signal downlinkEcData_i : std_logic_vector(1 downto 0);
+ signal downlinkIcData_i : std_logic_vector(1 downto 0);
+ signal GT_TX_WORD_CLK : std_logic;
+ signal GT_RX_WORD_CLK : std_logic;
+ signal uplinkDATA : std_logic_vector(223 downto 0);
+ signal uplinkEC : std_logic_vector(1 downto 0);
+ signal uplinkIC : std_logic_vector(1 downto 0);
+ begin
+ downlinkUserData_i <= data_to_fe;
+ downlinkIcData_i <= "00";
+ downlinkEcData_i <= "11";
+ GT_TX_WORD_CLK <= clk320;
+ GT_RX_WORD_CLK <= clk320;
+ lpgbt_BE: entity work.FLX_LpGBT_BE
+ Port map (
+ downlinkUserData_i => downlinkUserData_i,
+ downlinkEcData_i => downlinkEcData_i,
+ downlinkIcData_i => downlinkIcData_i,
+ TXCLK40 => clk40,
+ TXCLK320 => GT_TX_WORD_CLK,
+ RXCLK320m => GT_RX_WORD_CLK,
+ uplinkSelectFEC_i => '0', --FEC5
+ data_rdy => data_rdy_BE(i),
+ Tx_scrambler_bypass => '0',
+ Tx_Interleaver_bypass => '0',
+ Tx_FEC_bypass => '0',
+ TxData_Out => TX_DATA_BE(i),
+ rxdatain => TX_DATA_FE(i),
+ GBT_TX_RST => reset_clk40,
+ GBT_RX_RST => reset_clk40,
+ uplinkBypassInterleaver_i => '0',
+ uplinkBypassFECEncoder_i => '0',
+ uplinkBypassScrambler_i => '0',
+ uplinkMulticycleDelay_i => "011", --register_map_control.GBT_TX_TC_DLY_VALUE1(2 downto 0);
+ sta_headerFecLocked_o => alignment_done_BE(i),
+ ctr_clkSlip_o => RxSlide_BE(i),
+ uplinkReady_o => open,
+ uplinkUserData_o => uplinkData_i_BE(i)(229 downto 0),
+ uplinkEcData_o => uplinkData_i_BE(i)(231 downto 230),
+ uplinkIcData_o => uplinkData_i_BE(i)(233 downto 232),
+ fec_error_o => fec_error_i_BE(i),
+ fec_err_cnt_o => fec_err_cnt_i_BE(i)
+ );
+ uplinkDATA <= uplinkData_i_BE(i)(223 downto 0);
+ uplinkEC <= uplinkData_i_BE(i)(231 downto 230);
+ uplinkIC <= uplinkData_i_BE(i)(233 downto 232);
+ end generate;
+
+ -- lpgbt FELIG
+ link_loop_FE : for i in 0 to GBT_NUM-1 generate
+ signal GT_TX_WORD_CLK : std_logic;
+ signal GT_RX_WORD_CLK : std_logic;
+ signal FE_UPLINK_USER_DATA : std_logic_vector(223 downto 0);
+ signal FE_UPLINK_IC_DATA : std_logic_vector(1 downto 0);
+ signal FE_UPLINK_EC_DATA : std_logic_vector(1 downto 0);
+ signal downlinkDATA : std_logic_vector(31 downto 0);
+ signal downlinkEC : std_logic_vector(1 downto 0);
+ signal downlinkIC : std_logic_vector(1 downto 0);
+ signal count : std_logic_vector(2 downto 0) := "000";
+ signal data_en : std_logic;
+ begin
+ GT_TX_WORD_CLK <= clk320;
+ GT_RX_WORD_CLK <= clk320;
+ FE_UPLINK_USER_DATA <= data_to_be;
+ FE_UPLINK_IC_DATA <= "10";
+ FE_UPLINK_EC_DATA <= "01";
+ lpgbt_FE: entity work.FLX_LpGBT_FE
+ Port map
+ (
+ clk40_in => clk40,
+ TXCLK320 => GT_TX_WORD_CLK,
+ RXCLK320 => GT_RX_WORD_CLK,
+ rst_uplink_i => reset_clk40,
+ ctr_clkSlip_s => RxSlide_FE(i),
+ aligned => alignment_done_FE(i),
+ sta_headerFlag_o => sta_headerFlag_out_FE(i),
+ dat_upLinkWord_fromGb_s => TX_DATA_FE(i),
+ dat_downLinkWord_fromMgt_s16 => TX_DATA_BE(i),
+ rst_dnlink_i => reset_clk40,
+ sta_mgtRxRdy_s => reset_done_clk40,
+ downLinkBypassDeinterleaver => '0',
+ downLinkBypassFECDecoder => '0',
+ downLinkBypassDescsrambler => '0',
+ enableFECErrCounter => '0',
+ upLinkScramblerBypass => '0',
+ upLinkInterleaverBypass => '0',
+ fecMode => '0', --FEC5
+ txDataRate => '1', --10.24 Gb/s
+ phase_sel => "100",
+ upLinkData => FE_UPLINK_USER_DATA,
+ upLinkDataIC => FE_UPLINK_IC_DATA,
+ upLinkDataEC => FE_UPLINK_EC_DATA,
+ upLinkDataREADY => data_en,
+ downLinkData => downLinkData_i_FE(i)(31 downto 0),
+ downLinkDataIC => downLinkData_i_FE(i)(33 downto 32),
+ downLinkDataEC => downLinkData_i_FE(i)(35 downto 34),
+ tx_flag_out => tx_flag_out_FE(i)
+ );
+ downlinkDATA <= downLinkData_i_FE(i)(31 downto 0);
+ downlinkEC <= downLinkData_i_FE(i)(33 downto 32);
+ downlinkIC <= downLinkData_i_FE(i)(35 downto 34);
+ process(GT_TX_WORD_CLK)
+ begin
+ if GT_TX_WORD_CLK'event and GT_TX_WORD_CLK='1' then
+ count <= count + "001";
+ if count = "111" then
+ data_en <= '1';
+ else
+ data_en <= '0';
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ --check_data
+ process(clk320)
+ begin
+ if clk320'event and clk320='1' then
+ if alignment_done_FE = GBT_one and alignment_done_BE = GBT_one then
+ aligned <= '1';
+ else
+ aligned <= '0';
+ end if;
+ end if;
+ end process;
+
+ link_check : for i in 0 to GBT_NUM-1 generate
+ signal dif_FE : integer := 0;
+ signal dif_BE : integer := 0;
+
+ begin
+ process(clk320)
+ begin
+ if clk320'event and clk320='1' then
+ if cnt_div = "10" and clk40 = '1' and aligned = '1' then
+ if dif_FE = 0 and dif_BE = 0 then
+ dif_FE <= to_integer(unsigned(data_to_fe-downLinkData_i_FE(0)(31 downto 0)));
+ dif_BE <= to_integer(unsigned(data_to_be-uplinkData_i_BE(0)(223 downto 0)));
+ else
+ if data_to_fe > downLinkData_i_FE(0)(31 downto 0) then
+ if dif_FE = to_integer(unsigned(data_to_fe-downLinkData_i_FE(0)(31 downto 0))) then
+ good_FE(i) <= '1';
+ else
+ good_FE(i) <= '0';
+ end if;
+ else
+ good_FE(i) <= '0';
+ end if;
+ if data_to_be > uplinkData_i_BE(0)(223 downto 0) then
+ if dif_BE = to_integer(unsigned(data_to_be-uplinkData_i_BE(0)(223 downto 0))) then
+ good_BE(i) <= '1';
+ else
+ good_BE(i) <= '0';
+ end if;
+ else
+ good_BE(i) <= '0';
+ end if;
+ end if;
+ elsif aligned = '0' then
+ dif_FE <= 0;
+ dif_BE <= 0;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ --sim process
+ mainproc : process
+ variable var_FE : std_logic_vector(GBT_NUM-1 downto 0) := (others => '0');
+ variable var_BE : std_logic_vector(GBT_NUM-1 downto 0) := (others => '0');
+ variable var_br : integer := 0;
+ begin
+ assert false
+ report "START SIMULATION"
+ severity NOTE;
+ clk_en <= true;
+ wait for 2 us;
+ reset <= '1';
+ wait for 2 us;
+ reset <='0';
+ reset_done <= '1';
+ wait for 5 us;
+ var_br := 0;
+ wait until (aligned = '1' and good_FE = GBT_one and good_FE = GBT_one) or timeout;
+ var_FE := good_FE;
+ var_BE := good_BE;
+ while true loop
+ if timeout or data_to_fe > "00000000000000000001000000000000" then
+ exit;
+ end if;
+ if good_BE /= var_BE or var_FE /= good_FE then
+ var_br := 1;
+ log(ID_MONITOR,"Value changed. good_BE is "&to_string(good_BE)&" it was "&to_string(var_BE)&". good_FE is "&to_string(good_FE)&" it was "&to_string(var_FE), C_SCOPE);
+ wait for 25 ns;
+ var_BE := good_BE;
+ var_FE := good_FE;
+ else
+ wait for 25 ns;
+ end if;
+ end loop;
+
+ check_value(var_br, 0, ERROR, "Test if good_BE or good_FE ever changed value. If failed, check output.txt for more detail",C_SCOPE);
+ check_value(timeout,false, ERROR, "Timeout check",C_SCOPE);
+ report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
+ log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
+
+ -- Finish the simulation
+ if use_vunit = false then
+ std.env.stop;
+ end if;
+ uvvm_completed <= '1';
+ wait; -- to stop completely
+ finish;
+ wait for 1000 us;
+ end process;
+
+ timeoutproc : process
+ begin
+ wait for 1000 us;
+ timeout <= true;
+ end process;
+
+end Behavioral;
diff --git a/simulation/VUnit/tb/FELIGemulator_GBT_vunit_tb.vhd b/simulation/VUnit/tb/FELIGemulator_GBT_vunit_tb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9113d6890f1b34ebfc5fe4209fa58d7654f18cba
--- /dev/null
+++ b/simulation/VUnit/tb/FELIGemulator_GBT_vunit_tb.vhd
@@ -0,0 +1,81 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
+--========================================================================================================================
+-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
+-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
+-- contact Bitvis AS <support@bitvis.no>.
+--
+-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
+-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
+--========================================================================================================================
+
+------------------------------------------------------------------------------------------
+-- VUnit wrapper for FELIGemulator_tb GBT
+------------------------------------------------------------------------------------------
+
+
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+
+library lib;
+--
+
+library vunit_lib;
+ context vunit_lib.vunit_context;
+
+-- Test case entity
+entity FELIGemulator_GBT_vunit_tb is
+ generic (
+ runner_cfg : string
+ );
+end entity;
+
+architecture func of FELIGemulator_GBT_vunit_tb is
+ signal uvvm_completed : std_logic;
+ constant C_CLK_PERIOD_250 : time := 4 ns;
+begin
+
+ uut_tb: entity work.FELIGemulator_tb
+ generic map(
+ use_vunit => true,
+ FIRMWARE_MODE => 6
+ )
+ port map(
+ uvvm_completed => uvvm_completed
+ );
+
+
+ vunit_main : process is
+ begin
+ report "VUnit initializing";
+ test_runner_setup(runner, runner_cfg);
+ report "VUnit initialized";
+ while uvvm_completed /= '1' loop
+ wait for C_CLK_PERIOD_250;
+ end loop;
+ report "VUnit UVVM done, cleaning up";
+ test_runner_cleanup(runner);
+
+ end process vunit_main;
+
+end architecture;
+
+
diff --git a/simulation/VUnit/tb/FELIGemulator_LPGBT_vunit_tb.vhd b/simulation/VUnit/tb/FELIGemulator_LPGBT_vunit_tb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1c30330174c1211522c0412f7af33286f67cf6e5
--- /dev/null
+++ b/simulation/VUnit/tb/FELIGemulator_LPGBT_vunit_tb.vhd
@@ -0,0 +1,81 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
+--========================================================================================================================
+-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
+-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
+-- contact Bitvis AS <support@bitvis.no>.
+--
+-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
+-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
+--========================================================================================================================
+
+------------------------------------------------------------------------------------------
+-- VUnit wrapper for FELIGemulator_tb LPGBT
+------------------------------------------------------------------------------------------
+
+
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+
+library lib;
+--
+
+library vunit_lib;
+ context vunit_lib.vunit_context;
+
+-- Test case entity
+entity FELIGemulator_LPGBT_vunit_tb is
+ generic (
+ runner_cfg : string
+ );
+end entity;
+
+architecture func of FELIGemulator_LPGBT_vunit_tb is
+ signal uvvm_completed : std_logic;
+ constant C_CLK_PERIOD_250 : time := 4 ns;
+begin
+
+ uut_tb: entity work.FELIGemulator_tb
+ generic map(
+ use_vunit => true,
+ FIRMWARE_MODE => 11
+ )
+ port map(
+ uvvm_completed => uvvm_completed
+ );
+
+
+ vunit_main : process is
+ begin
+ report "VUnit initializing";
+ test_runner_setup(runner, runner_cfg);
+ report "VUnit initialized";
+ while uvvm_completed /= '1' loop
+ wait for C_CLK_PERIOD_250;
+ end loop;
+ report "VUnit UVVM done, cleaning up";
+ test_runner_cleanup(runner);
+
+ end process vunit_main;
+
+end architecture;
+
+
diff --git a/simulation/VUnit/tb/FELIGexternaltrigger_tb.vhd b/simulation/VUnit/tb/FELIGexternaltrigger_tb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9081640b0f61cee0b2ea695d70b749c2dc52c260
--- /dev/null
+++ b/simulation/VUnit/tb/FELIGexternaltrigger_tb.vhd
@@ -0,0 +1,80 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
+--========================================================================================================================
+-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
+-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
+-- contact Bitvis AS <support@bitvis.no>.
+--
+-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
+-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
+--========================================================================================================================
+
+------------------------------------------------------------------------------------------
+-- VUnit wrapper for FELIGexternaltrigger_tb
+------------------------------------------------------------------------------------------
+
+
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+
+library lib;
+--
+
+library vunit_lib;
+ context vunit_lib.vunit_context;
+
+-- Test case entity
+entity FELIGexternaltrigger_vunit_tb is
+ generic (
+ runner_cfg : string
+ );
+end entity;
+
+architecture func of FELIGexternaltrigger_vunit_tb is
+ signal uvvm_completed : std_logic;
+ constant C_CLK_PERIOD_250 : time := 4 ns;
+begin
+
+ uut_tb: entity work.FELIGexternaltrigger_tb
+ generic map(
+ use_vunit => true
+ )
+ port map(
+ uvvm_completed => uvvm_completed
+ );
+
+
+ vunit_main : process is
+ begin
+ report "VUnit initializing";
+ test_runner_setup(runner, runner_cfg);
+ report "VUnit initialized";
+ while uvvm_completed /= '1' loop
+ wait for C_CLK_PERIOD_250;
+ end loop;
+ report "VUnit UVVM done, cleaning up";
+ test_runner_cleanup(runner);
+
+ end process vunit_main;
+
+end architecture;
+
+
diff --git a/simulation/VUnit/tb/FELIGlinkwrapperLPGBT_tb.vhd b/simulation/VUnit/tb/FELIGlinkwrapperLPGBT_tb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6db3a59892967eef1a99674413d1e440b8f88fb0
--- /dev/null
+++ b/simulation/VUnit/tb/FELIGlinkwrapperLPGBT_tb.vhd
@@ -0,0 +1,80 @@
+--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+--! Authors:
+--! Frans Schreuder
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--! http://www.apache.org/licenses/LICENSE-2.0
+--!
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+
+--========================================================================================================================
+-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
+-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
+-- contact Bitvis AS <support@bitvis.no>.
+--
+-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
+-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
+--========================================================================================================================
+
+------------------------------------------------------------------------------------------
+-- VUnit wrapper for FELIGlinkwrapperLPGBT_tb
+------------------------------------------------------------------------------------------
+
+
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+
+library lib;
+--
+
+library vunit_lib;
+ context vunit_lib.vunit_context;
+
+-- Test case entity
+entity FELIGlinkwrapperLPGBT_vunit_tb is
+ generic (
+ runner_cfg : string
+ );
+end entity;
+
+architecture func of FELIGlinkwrapperLPGBT_vunit_tb is
+ signal uvvm_completed : std_logic;
+ constant C_CLK_PERIOD_250 : time := 4 ns;
+begin
+
+ uut_tb: entity work.FELIGlinkwrapperLPGBT_tb
+ generic map(
+ use_vunit => true
+ )
+ port map(
+ uvvm_completed => uvvm_completed
+ );
+
+
+ vunit_main : process is
+ begin
+ report "VUnit initializing";
+ test_runner_setup(runner, runner_cfg);
+ report "VUnit initialized";
+ while uvvm_completed /= '1' loop
+ wait for C_CLK_PERIOD_250;
+ end loop;
+ report "VUnit UVVM done, cleaning up";
+ test_runner_cleanup(runner);
+
+ end process vunit_main;
+
+end architecture;
+
+
diff --git a/sources/FELIG/data_generator/elink_data_emulator.vhd b/sources/FELIG/data_generator/elink_data_emulator.vhd
index e6722a4aae877e2a0a80ed739d950c296bcf0e81..0cb28007d48df7b48c17777f71a1756da1040888 100644
--- a/sources/FELIG/data_generator/elink_data_emulator.vhd
+++ b/sources/FELIG/data_generator/elink_data_emulator.vhd
@@ -328,7 +328,7 @@ begin
)
port map(
src_clk => '0',
- src_in => fmemu_random.SELECT_RANDOM(0),
+ src_in => fmemu_random.FMEMU_RANDOM_CONTROL.SELECT_RANDOM(fmemu_random.FMEMU_RANDOM_CONTROL.SELECT_RANDOM'low),
dest_clk => clk,
dest_out => select_random
);
diff --git a/sources/FELIG/data_generator/elink_printer_bit_feeder_v2.vhd b/sources/FELIG/data_generator/elink_printer_bit_feeder_v2.vhd
index 85514bcf2864e3df887bd85e1cfc9059a3f8daab..f56c05699432dc1c1fc40afa0174bc48eedfcdb3 100644
--- a/sources/FELIG/data_generator/elink_printer_bit_feeder_v2.vhd
+++ b/sources/FELIG/data_generator/elink_printer_bit_feeder_v2.vhd
@@ -198,7 +198,11 @@ begin
end if;
if wr_to_reg_final_d = '1' then
reg_160_8b10b((count+1)*10 - 1 downto count*10) <= word_test;
- reg_160_direc((count+1)*8 - 1 downto count*8 ) <= word_test(7 downto 0);
+ if MSBfirst = '0' then
+ reg_160_direc((count+1)*8 - 1 downto count*8 ) <= word_in_d(7 downto 0);
+ else
+ reg_160_direc((count+1)*8 - 1 downto count*8 ) <= word_in_d(9 downto 2);
+ end if;
if flag_count <= '0' then
if count = count_max then
count <= 0;
@@ -322,7 +326,11 @@ begin
end if;
if wr_to_reg_final_d = '1' then
reg_160_8b10b((count+1)*10 - 1 downto count*10) <= word_test;
- reg_160_direc((count+1)*8 - 1 downto count*8 ) <= word_test(7 downto 0);
+ if MSBfirst = '0' then
+ reg_160_direc((count+1)*8 - 1 downto count*8 ) <= word_in_d(7 downto 0);
+ else
+ reg_160_direc((count+1)*8 - 1 downto count*8 ) <= word_in_d(9 downto 2);
+ end if;
if flag_count <= '0' then
if count = count_max then
count <= 0;
diff --git a/sources/FELIG/data_generator/elink_printer_v2.vhd b/sources/FELIG/data_generator/elink_printer_v2.vhd
index 618cb8b96c9b5f4a4457f9f7fad700a20ab3d9e1..e6657c28cd4df670e1c9b42899a629b620eb0ac6 100644
--- a/sources/FELIG/data_generator/elink_printer_v2.vhd
+++ b/sources/FELIG/data_generator/elink_printer_v2.vhd
@@ -197,6 +197,9 @@ begin
--------
if (gbt_word_latch = '1') then
gbt_payload_i <= gbt_bit_stream;
+ data_ready <= '1';
+ else
+ data_ready <= '0';
end if;
--------
case gbt_shift_count is
diff --git a/sources/FELIG/emulator/Emulator.vhd b/sources/FELIG/emulator/Emulator.vhd
index 1cd9d00fad48d5b7505575ac6585bb4445c06656..37195b8a81fce5f0d301654e85abf7df1d9c6329 100644
--- a/sources/FELIG/emulator/Emulator.vhd
+++ b/sources/FELIG/emulator/Emulator.vhd
@@ -107,7 +107,7 @@ architecture Behavioral of Emulator is
signal l1id : std_logic_vector( 15 downto 0) := (others => '0');
signal l1a_ext_int_id : std_logic_vector( 15 downto 0) := (others => '0'); --MT
signal l1a_ext_int_id_extra : std_logic_vector( 31 downto 0) := (others => '0'); --MT
- signal l1a_int_int_id_tx_clk : std_logic_vector(15 downto 0);
+ signal l1a_int_int_id_tx_clk : std_logic_vector( 15 downto 0) := (others => '0');
signal elink_sync : std_logic := '0';
signal elink_sync_reg : std_logic;
signal emu_data_re : std_logic_vector(0 to NUMEGROUPmax-1); --(0 to 4);
@@ -150,6 +150,8 @@ architecture Behavioral of Emulator is
signal out_of_sync : std_logic_vector(NUMEGROUPmax-1 downto 0) := (others => '0');
signal or_out_of_sync : std_logic;
signal flag_sync : std_logic_vector(0 to NUMEGROUPmax-1);
+ signal start_dsp_flag : std_logic := '0'; -- so dsp works in sim
+ signal start_dsp : std_logic := '0'; -- so dsp works in sim
--RL to be implemented
--signal aurora_en : std_logic_vector(0 to NUMELINKmax-1);
@@ -443,17 +445,22 @@ begin
flag_ext_counter_reset <= '0';
end if;
end if;
- end if;
+ if start_dsp_flag = '0' then
+ start_dsp_flag <= '1';
+ start_dsp <= '1';
+ else
+ start_dsp <= '0';
+ end if; end if;
end process;
--l1a id counter
l1a_ext_int_id_counter : dsp_counter
PORT MAP (
CLK => lane_txclk,
- CE => ext_counter_l1a_trigger,
+ CE => ext_counter_l1a_trigger or start_dsp,
SCLR => '0',
UP => '1',
- LOAD => l1a_ext_counter_reset,
+ LOAD => l1a_ext_counter_reset or start_dsp,
L => X"000000000000",
Q(47 downto 16) => l1a_ext_int_id_extra,
Q(15 downto 0) => l1a_ext_int_id
diff --git a/sources/FELIG/emulator/EmulatorWrapper.vhd b/sources/FELIG/emulator/EmulatorWrapper.vhd
index e2da90097e575e98cb1c6442e2d76106d9c2066d..1e1f7fbfb488d2840d5ae7f72ac94d5968c3532d 100644
--- a/sources/FELIG/emulator/EmulatorWrapper.vhd
+++ b/sources/FELIG/emulator/EmulatorWrapper.vhd
@@ -59,7 +59,7 @@ entity EmulatorWrapper is
FIRMWARE_MODE : integer := 0
);
port(
- clk40 : in std_logic;
+ clk40 : in std_logic;
gt_txusrclk_in : in std_logic_vector(GBT_NUM-1 downto 0);
gt_rxusrclk_in : in std_logic_vector(GBT_NUM-1 downto 0);
link_tx_data_228b_array_out : out txrx228b_type(0 to GBT_NUM-1);
@@ -67,6 +67,7 @@ entity EmulatorWrapper is
link_rx_data_120b_array_in : in txrx120b_type(0 to GBT_NUM-1);
link_tx_flag_in : in std_logic_vector(GBT_NUM-1 downto 0);
link_rx_flag_in : in std_logic_vector(GBT_NUM-1 downto 0);
+ l1a_int_trigger_out : out std_logic;
lane_control : in array_of_lane_control_type(GBT_NUM-1 downto 0);
lane_monitor : out array_of_lane_monitor_type(GBT_NUM-1 downto 0)
);
@@ -86,29 +87,30 @@ architecture RTL of EmulatorWrapper is
return '0';
end if;
end function;
- signal l1a_int_trigger : std_logic;
- signal l1a_int_int_id : std_logic_vector(15 downto 0);
- signal l1a_int_int_id_extra : std_logic_vector(31 downto 0);
- signal l1a_int_count, l1a_int_max_count : std_logic_vector(31 downto 0);
+ signal l1a_int_trigger : std_logic := '0';
+ signal l1a_int_int_id : std_logic_vector(15 downto 0) := (others=>'0');
+ signal l1a_int_int_id_extra : std_logic_vector(31 downto 0) := (others=>'0');
+ signal l1a_int_count, l1a_int_max_count : std_logic_vector(31 downto 0) := (others=>'0');
signal l1a_int_max_count_extra : std_logic_vector(15 downto 0) := (others=>'0');
- signal l1a_int_count_load : std_logic;
- signal l1a_int_int_id_sclr : std_logic;
+ signal l1a_int_count_load : std_logic := '0';
+ signal l1a_int_int_id_sclr : std_logic := '0';
signal l1a_int_counter_reset : std_logic := '0';
signal flag_int_counter_reset : std_logic := '0';
- signal counter_reset : std_logic;
-
+ signal counter_reset : std_logic := '0';
+ signal start_dsp_flag : std_logic := '0'; -- so dsp works in sim
+ signal start_dsp : std_logic := '0'; -- so dsp works in sim
begin
l1a_int_max_count <= "0000" & lane_control(0).global.l1a_max_count;--"0000" & register_map_control_40xtal.FELIG_GLOBAL_CONTROL.FAKE_L1A_RATE;
counter_reset <= lane_control(0).global.l1a_counter_reset;
-
+ l1a_int_trigger_out <= l1a_int_trigger;
l1a_int_counter : dsp_counter
PORT MAP (
CLK => clk40,
CE => '1',
SCLR => '0',
UP => '0',
- LOAD => l1a_int_count_load,
+ LOAD => l1a_int_count_load or start_dsp,
L(47 downto 32) => X"0000",
L(31 downto 0) => l1a_int_max_count,
Q(47 downto 32) => l1a_int_max_count_extra, --MT SIMU+
@@ -118,10 +120,10 @@ begin
l1a_int_int_id_counter : dsp_counter
PORT MAP (
CLK => clk40,
- CE => l1a_int_trigger,
+ CE => l1a_int_trigger or start_dsp,
SCLR => l1a_int_int_id_sclr,
UP => '1',
- LOAD => l1a_int_counter_reset, --RL
+ LOAD => l1a_int_counter_reset or start_dsp, --RL
L => X"000000000000",
Q(47 downto 16) => l1a_int_int_id_extra, --MT SIMU+ open,
Q(15 downto 0) => l1a_int_int_id
@@ -144,13 +146,12 @@ begin
process(clk40)
begin
- if clk40'event and clk40='1' then
+ if clk40'event and clk40 = '1' then
if l1a_int_max_count = 0 then
l1a_int_trigger <= '0';
l1a_int_int_id_sclr <= '1';
l1a_int_count_load <= '1';
elsif l1a_int_count = 0 then
-
l1a_int_trigger <= '1';
l1a_int_int_id_sclr <= '0';
l1a_int_count_load <= '1';
@@ -159,11 +160,16 @@ begin
l1a_int_int_id_sclr <= '0';
l1a_int_count_load <= '0';
end if;
+ if start_dsp_flag = '0' then
+ start_dsp_flag <= '1';
+ start_dsp <= '1';
+ else
+ start_dsp <= '0';
+ end if;
end if;
end process;
emulator_inst : for link in GBT_NUM-1 downto 0 generate
-
gbt : entity work.emulator
generic map (
useGBTdataEmulator => false,
@@ -185,9 +191,7 @@ begin
gbt_rx_flag_in => link_rx_flag_in(link),
lane_control => lane_control(link),
lane_monitor => lane_monitor(link)--,
-
);
-
end generate;
end RTL;
diff --git a/sources/FELIG/packages/type_lib.vhd b/sources/FELIG/packages/type_lib.vhd
index 287d22b892d05318a58d283b8d97481520f5aeca..1cbf89c42730879b13412d63a4b762ab0f6dbdfe 100644
--- a/sources/FELIG/packages/type_lib.vhd
+++ b/sources/FELIG/packages/type_lib.vhd
@@ -166,7 +166,6 @@ package type_lib is
end record lane_global_control;
type lane_emu_random_control is record
- SELECT_RANDOM : std_logic_vector(0 downto 0);
FMEMU_RANDOM_RAM_ADDR : std_logic_vector(9 downto 0); -- Controls the address of the ramblock for the random number generator
FMEMU_RANDOM_RAM : bitfield_fmemu_random_ram_t_type;
FMEMU_RANDOM_CONTROL : bitfield_fmemu_random_control_w_type;
diff --git a/sources/FELIG/templates/LaneRegisterRemapper.vhd b/sources/FELIG/templates/LaneRegisterRemapper.vhd
index f53e89fe74c665454b1023b733366110e1e4acab..439c013c57e3c9fc64e2c96c65949e3b50f733dd 100644
--- a/sources/FELIG/templates/LaneRegisterRemapper.vhd
+++ b/sources/FELIG/templates/LaneRegisterRemapper.vhd
@@ -103,7 +103,6 @@ begin
lane_control(i).global.l1a_counter_reset <= register_map_control.FELIG_L1ID_RESET (register_map_control.FELIG_L1ID_RESET'low);
lane_control(i).global.MSB <= register_map_control.ENCODING_REVERSE_10B (register_map_control.ENCODING_REVERSE_10B'low);
lane_control(i).global.l1a_max_count <= register_map_control.FELIG_GLOBAL_CONTROL.FAKE_L1A_RATE;
- lane_control(i).fmemu_random.SELECT_RANDOM <= register_map_control.FMEMU_RANDOM_CONTROL.SELECT_RANDOM;
lane_control(i).fmemu_random.FMEMU_RANDOM_RAM_ADDR <= register_map_control.FMEMU_RANDOM_RAM_ADDR;
lane_control(i).fmemu_random.FMEMU_RANDOM_RAM <= register_map_control.FMEMU_RANDOM_RAM;
lane_control(i).fmemu_random.FMEMU_RANDOM_CONTROL <= register_map_control.FMEMU_RANDOM_CONTROL;
diff --git a/sources/FelixTop/felig_top_bnl712.vhd b/sources/FelixTop/felig_top_bnl712.vhd
index 20e80c9ca309b18e74c572e2778ca42d2d563937..65abc364500cb63c2612876310dcb64572fa3efa 100644
--- a/sources/FelixTop/felig_top_bnl712.vhd
+++ b/sources/FelixTop/felig_top_bnl712.vhd
@@ -396,6 +396,7 @@ begin
link_rx_data_120b_array_in => link_rx_data_120b_array_tmp,
link_tx_flag_in => link_tx_flag_i,
link_rx_flag_in => link_rx_flag_i,
+ l1a_int_trigger_out => open, --sim
lane_control => lane_control,
lane_monitor => lane_monitor
);
diff --git a/sources/ip_cores/sim/Distr_LUT_felig_sim_netlist.vhdl b/sources/ip_cores/sim/Distr_LUT_felig_sim_netlist.vhdl
index 7243ce09c45090948f4372f372cb5f6d3bc40a7f..34e1eb6ddbc8b9e66870d8ca7c9b46819a62e8a6 100644
--- a/sources/ip_cores/sim/Distr_LUT_felig_sim_netlist.vhdl
+++ b/sources/ip_cores/sim/Distr_LUT_felig_sim_netlist.vhdl
@@ -1,661 +1,667 @@
--- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018
--- Date : Tue Nov 12 18:15:58 2019
--- Host : felix02.hep.anl.gov running 64-bit Scientific Linux release 6.10 (Carbon)
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Wed Oct 23 09:28:28 2024
+-- Host : felix04.hep.anl.gov running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
--- /users/mtrovato/Phase1/felig/firmware/Projects/FLX712_FELIG/FLX712_FELIG.srcs/sources_1/ip/Distr_LUT_felig/Distr_LUT_felig_sim_netlist.vhdl
+-- /users/rluz/firmware_copies/241023_FELIG_FLX712_FLX-1507_UVVM_testbench/Projects/FLX712_FELIG/FLX712_FELIG.gen/sources_1/ip/Distr_LUT_felig/Distr_LUT_felig_sim_netlist.vhdl
-- Design : Distr_LUT_felig
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcku115-flvf1924-2-e
-- --------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity Distr_LUT_felig_blk_mem_gen_prim_wrapper_init is
- port (
- doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
- clka : in STD_LOGIC;
- clkb : in STD_LOGIC;
- wea : in STD_LOGIC_VECTOR ( 0 to 0 );
- enb : in STD_LOGIC;
- sleep : in STD_LOGIC;
- addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
- addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
- dina : in STD_LOGIC_VECTOR ( 15 downto 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of Distr_LUT_felig_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
-end Distr_LUT_felig_blk_mem_gen_prim_wrapper_init;
+`protect begin_protected
+`protect version = 1
+`protect encrypt_agent = "XILINX"
+`protect encrypt_agent_info = "Xilinx Encryption Tool 2024.1"
+`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
+`protect key_block
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-architecture STRUCTURE of Distr_LUT_felig_blk_mem_gen_prim_wrapper_init is
- signal \DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_70\ : STD_LOGIC;
- signal \DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_71\ : STD_LOGIC;
- signal \NLW_DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_CASDOUTA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
- signal \NLW_DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_CASDOUTB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
- signal \NLW_DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_CASDOUTPA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal \NLW_DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_CASDOUTPB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal \NLW_DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOUTADOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
- signal \NLW_DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOUTPADOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute box_type : string;
- attribute box_type of \DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
-begin
-\DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E2
- generic map(
- CASCADE_ORDER_A => "NONE",
- CASCADE_ORDER_B => "NONE",
- CLOCK_DOMAINS => "INDEPENDENT",
- DOA_REG => 1,
- DOB_REG => 1,
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- INIT_38 => X"0103010301030103010301030103010301030103010301030103010301030103",
- INIT_39 => X"0109010901090109010901090109010901090109010901090103010301030103",
- INIT_3A => X"0110011001100110011001100109010901090109010901090109010901090109",
- INIT_3B => X"0116011601160116011001100110011001100110011001100110011001100110",
- INIT_3C => X"011C011C011C011C011C01160116011601160116011601160116011601160116",
- INIT_3D => X"012201220122012201220122012201220122011C011C011C011C011C011C011C",
- INIT_3E => X"0136012F012F012F012F012F012F012901290129012901290129012901290122",
- INIT_3F => X"016F015D0155014F0149014901430143013D013D013D013D0136013601360136",
- INIT_A => B"00" & X"0000",
- INIT_B => B"00" & X"0000",
- INIT_FILE => "NONE",
- IS_CLKARDCLK_INVERTED => '0',
- IS_CLKBWRCLK_INVERTED => '0',
- IS_ENARDEN_INVERTED => '0',
- IS_ENBWREN_INVERTED => '0',
- IS_RSTRAMARSTRAM_INVERTED => '0',
- IS_RSTRAMB_INVERTED => '0',
- IS_RSTREGARSTREG_INVERTED => '0',
- IS_RSTREGB_INVERTED => '0',
- RDADDRCHANGEA => "FALSE",
- RDADDRCHANGEB => "FALSE",
- READ_WIDTH_A => 18,
- READ_WIDTH_B => 18,
- RSTREG_PRIORITY_A => "REGCE",
- RSTREG_PRIORITY_B => "REGCE",
- SIM_COLLISION_CHECK => "ALL",
- SLEEP_ASYNC => "FALSE",
- SRVAL_A => B"00" & X"0000",
- SRVAL_B => B"00" & X"0000",
- WRITE_MODE_A => "NO_CHANGE",
- WRITE_MODE_B => "NO_CHANGE",
- WRITE_WIDTH_A => 18,
- WRITE_WIDTH_B => 18
- )
- port map (
- ADDRARDADDR(13 downto 4) => addra(9 downto 0),
- ADDRARDADDR(3 downto 0) => B"0000",
- ADDRBWRADDR(13 downto 4) => addrb(9 downto 0),
- ADDRBWRADDR(3 downto 0) => B"0000",
- ADDRENA => '0',
- ADDRENB => '0',
- CASDIMUXA => '0',
- CASDIMUXB => '0',
- CASDINA(15 downto 0) => B"0000000000000000",
- CASDINB(15 downto 0) => B"0000000000000000",
- CASDINPA(1 downto 0) => B"00",
- CASDINPB(1 downto 0) => B"00",
- CASDOMUXA => '0',
- CASDOMUXB => '0',
- CASDOMUXEN_A => '0',
- CASDOMUXEN_B => '0',
- CASDOUTA(15 downto 0) => \NLW_DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_CASDOUTA_UNCONNECTED\(15 downto 0),
- CASDOUTB(15 downto 0) => \NLW_DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_CASDOUTB_UNCONNECTED\(15 downto 0),
- CASDOUTPA(1 downto 0) => \NLW_DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_CASDOUTPA_UNCONNECTED\(1 downto 0),
- CASDOUTPB(1 downto 0) => \NLW_DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_CASDOUTPB_UNCONNECTED\(1 downto 0),
- CASOREGIMUXA => '0',
- CASOREGIMUXB => '0',
- CASOREGIMUXEN_A => '0',
- CASOREGIMUXEN_B => '0',
- CLKARDCLK => clka,
- CLKBWRCLK => clkb,
- DINADIN(15 downto 0) => dina(15 downto 0),
- DINBDIN(15 downto 0) => B"0000000000000000",
- DINPADINP(1 downto 0) => B"00",
- DINPBDINP(1 downto 0) => B"00",
- DOUTADOUT(15 downto 0) => \NLW_DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOUTADOUT_UNCONNECTED\(15 downto 0),
- DOUTBDOUT(15 downto 0) => doutb(15 downto 0),
- DOUTPADOUTP(1 downto 0) => \NLW_DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOUTPADOUTP_UNCONNECTED\(1 downto 0),
- DOUTPBDOUTP(1) => \DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_70\,
- DOUTPBDOUTP(0) => \DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_71\,
- ENARDEN => wea(0),
- ENBWREN => enb,
- REGCEAREGCE => '0',
- REGCEB => enb,
- RSTRAMARSTRAM => '0',
- RSTRAMB => '0',
- RSTREGARSTREG => '0',
- RSTREGB => '0',
- SLEEP => sleep,
- WEA(1 downto 0) => B"11",
- WEBWE(3 downto 0) => B"0000"
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity Distr_LUT_felig_blk_mem_gen_prim_width is
- port (
- doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
- clka : in STD_LOGIC;
- clkb : in STD_LOGIC;
- wea : in STD_LOGIC_VECTOR ( 0 to 0 );
- enb : in STD_LOGIC;
- sleep : in STD_LOGIC;
- addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
- addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
- dina : in STD_LOGIC_VECTOR ( 15 downto 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of Distr_LUT_felig_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
-end Distr_LUT_felig_blk_mem_gen_prim_width;
+`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
+VRSQ05ZaB6bIhFIQ823mTvlJaG9+5iW5C3+KxGjq0sq9ziCshKOLpOGPDMmOWDqA4uBaxC5IKISr
+w8+A8mqbYjXo5m1g8sGjNaETS0HKJsK+l5Y++tN4IEUs+DwxgrPR/+LWtChuOzVkfC7BG3LVUEMj
+zM3GAyGcXGJ3sdBItZAfsevyiy7kr4Fw+nk2hWytGteu1NZk3VzPE7KQHLkOlHBPXf6P0j8LpKcr
+2oNDgQ/WaEmg6OOvFeJuaWDaee8Sn6wKP/caMyoGdSeczsPtRrJeoSRlbNHlxhCv7zg+Cn2AgwrR
+PTqGsMrkhv9U0sq+waS0CmwChsk4WB7RspGYUg==
-architecture STRUCTURE of Distr_LUT_felig_blk_mem_gen_prim_width is
-begin
-\prim_init.ram\: entity work.Distr_LUT_felig_blk_mem_gen_prim_wrapper_init
- port map (
- addra(9 downto 0) => addra(9 downto 0),
- addrb(9 downto 0) => addrb(9 downto 0),
- clka => clka,
- clkb => clkb,
- dina(15 downto 0) => dina(15 downto 0),
- doutb(15 downto 0) => doutb(15 downto 0),
- enb => enb,
- sleep => sleep,
- wea(0) => wea(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity Distr_LUT_felig_blk_mem_gen_generic_cstr is
- port (
- doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
- clka : in STD_LOGIC;
- clkb : in STD_LOGIC;
- wea : in STD_LOGIC_VECTOR ( 0 to 0 );
- enb : in STD_LOGIC;
- sleep : in STD_LOGIC;
- addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
- addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
- dina : in STD_LOGIC_VECTOR ( 15 downto 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of Distr_LUT_felig_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
-end Distr_LUT_felig_blk_mem_gen_generic_cstr;
+`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
+`protect key_block
+tNziOjCznlvIl4dadmB9r23Duf+HQHWOuHmupEU3PJxrazHVtZdNKspG9sRXhF9mjbpnSiKYCdFK
+Jr9W/dxUid36faFIPKQazVTuOiE0hkzVQAGpYxXjT/ITB/9EFBvgvP5L3EAhHv32x6MA1vkFSI7x
+HrZ09YNFEF6T7DPTZE4=
-architecture STRUCTURE of Distr_LUT_felig_blk_mem_gen_generic_cstr is
-begin
-\ramloop[0].ram.r\: entity work.Distr_LUT_felig_blk_mem_gen_prim_width
- port map (
- addra(9 downto 0) => addra(9 downto 0),
- addrb(9 downto 0) => addrb(9 downto 0),
- clka => clka,
- clkb => clkb,
- dina(15 downto 0) => dina(15 downto 0),
- doutb(15 downto 0) => doutb(15 downto 0),
- enb => enb,
- sleep => sleep,
- wea(0) => wea(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity Distr_LUT_felig_blk_mem_gen_top is
- port (
- doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
- clka : in STD_LOGIC;
- clkb : in STD_LOGIC;
- wea : in STD_LOGIC_VECTOR ( 0 to 0 );
- enb : in STD_LOGIC;
- sleep : in STD_LOGIC;
- addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
- addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
- dina : in STD_LOGIC_VECTOR ( 15 downto 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of Distr_LUT_felig_blk_mem_gen_top : entity is "blk_mem_gen_top";
-end Distr_LUT_felig_blk_mem_gen_top;
+`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
+QCYfxgkUHlX1cre1q9aS3sVDIOX36YBK4ZwJXAVUwA6f1OQ77XibjpWJHt5FK9F0PcYp/j21pqzO
+BRdkDcFLVAjxER4J5t5iMVhoeMk+3fpiKfYrm4WFl1ygsJsfFJP0jqO1OkjC8iFBtm3n6b7CTl1o
+cjBbcBp8UgW6E8rf5inXA0dRqybnyxKJSnMFYLinvpVU6QEc4OKO7mi/i/s9p/efiP+CdQf0yDRU
+Fw7o7x0D7tjBv943g5L+4wGZ2JYU+ISqn4Ajxy/bWTTJDe6T/15evhngS61MC8Xjamzc4YLZBP8o
+ShfSLoeZeO+Hk5n3xzJRghM0DQ6Sj7NqXFY68w==
-architecture STRUCTURE of Distr_LUT_felig_blk_mem_gen_top is
-begin
-\valid.cstr\: entity work.Distr_LUT_felig_blk_mem_gen_generic_cstr
- port map (
- addra(9 downto 0) => addra(9 downto 0),
- addrb(9 downto 0) => addrb(9 downto 0),
- clka => clka,
- clkb => clkb,
- dina(15 downto 0) => dina(15 downto 0),
- doutb(15 downto 0) => doutb(15 downto 0),
- enb => enb,
- sleep => sleep,
- wea(0) => wea(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity Distr_LUT_felig_blk_mem_gen_v8_4_1_synth is
- port (
- doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
- clka : in STD_LOGIC;
- clkb : in STD_LOGIC;
- wea : in STD_LOGIC_VECTOR ( 0 to 0 );
- enb : in STD_LOGIC;
- sleep : in STD_LOGIC;
- addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
- addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
- dina : in STD_LOGIC_VECTOR ( 15 downto 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of Distr_LUT_felig_blk_mem_gen_v8_4_1_synth : entity is "blk_mem_gen_v8_4_1_synth";
-end Distr_LUT_felig_blk_mem_gen_v8_4_1_synth;
+`protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
+Uy8FDDy3dZQGAnMQV0HBesEs+/oZdaq35Kj1PGhy9J/+EBZm0nhhQgYtku8tWABW2jKAC1GtNTvo
+uReQyr1hteMxTbD5OIuqv86eb1hXZVENlZ7ichG8auUjkeHAkaSYNbHOuDLIhSqHEL67XbcZ9zPG
+1JOY3+VONSww0KYPcQbGSo/2DaC5C0Y+mZODRfJ4+b0WXjce6UaJetilBc3VtqqmodIM2d3HDawF
+R0xVJfHj86rXmUkY+SNUw60zsV6raCY6G3k/rXpei1d6zn8tCThkKG5fwiWY8zA7kRdTFIlVKP9h
+fb6kfzRBRT/BgVQ8d4RgEcEVV8m3u/Mf4KIlTw==
-architecture STRUCTURE of Distr_LUT_felig_blk_mem_gen_v8_4_1_synth is
-begin
-\gnbram.gnativebmg.native_blk_mem_gen\: entity work.Distr_LUT_felig_blk_mem_gen_top
- port map (
- addra(9 downto 0) => addra(9 downto 0),
- addrb(9 downto 0) => addrb(9 downto 0),
- clka => clka,
- clkb => clkb,
- dina(15 downto 0) => dina(15 downto 0),
- doutb(15 downto 0) => doutb(15 downto 0),
- enb => enb,
- sleep => sleep,
- wea(0) => wea(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity Distr_LUT_felig_blk_mem_gen_v8_4_1 is
- port (
- clka : in STD_LOGIC;
- rsta : in STD_LOGIC;
- ena : in STD_LOGIC;
- regcea : in STD_LOGIC;
- wea : in STD_LOGIC_VECTOR ( 0 to 0 );
- addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
- dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
- douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
- clkb : in STD_LOGIC;
- rstb : in STD_LOGIC;
- enb : in STD_LOGIC;
- regceb : in STD_LOGIC;
- web : in STD_LOGIC_VECTOR ( 0 to 0 );
- addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
- dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
- doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
- injectsbiterr : in STD_LOGIC;
- injectdbiterr : in STD_LOGIC;
- eccpipece : in STD_LOGIC;
- sbiterr : out STD_LOGIC;
- dbiterr : out STD_LOGIC;
- rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
- sleep : in STD_LOGIC;
- deepsleep : in STD_LOGIC;
- shutdown : in STD_LOGIC;
- rsta_busy : out STD_LOGIC;
- rstb_busy : out STD_LOGIC;
- s_aclk : in STD_LOGIC;
- s_aresetn : in STD_LOGIC;
- s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
- s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_awvalid : in STD_LOGIC;
- s_axi_awready : out STD_LOGIC;
- s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
- s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
- s_axi_wlast : in STD_LOGIC;
- s_axi_wvalid : in STD_LOGIC;
- s_axi_wready : out STD_LOGIC;
- s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_bvalid : out STD_LOGIC;
- s_axi_bready : in STD_LOGIC;
- s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
- s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_arvalid : in STD_LOGIC;
- s_axi_arready : out STD_LOGIC;
- s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_rdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
- s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_rlast : out STD_LOGIC;
- s_axi_rvalid : out STD_LOGIC;
- s_axi_rready : in STD_LOGIC;
- s_axi_injectsbiterr : in STD_LOGIC;
- s_axi_injectdbiterr : in STD_LOGIC;
- s_axi_sbiterr : out STD_LOGIC;
- s_axi_dbiterr : out STD_LOGIC;
- s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
- );
- attribute C_ADDRA_WIDTH : integer;
- attribute C_ADDRA_WIDTH of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 10;
- attribute C_ADDRB_WIDTH : integer;
- attribute C_ADDRB_WIDTH of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 10;
- attribute C_ALGORITHM : integer;
- attribute C_ALGORITHM of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 1;
- attribute C_AXI_ID_WIDTH : integer;
- attribute C_AXI_ID_WIDTH of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 4;
- attribute C_AXI_SLAVE_TYPE : integer;
- attribute C_AXI_SLAVE_TYPE of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_AXI_TYPE : integer;
- attribute C_AXI_TYPE of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 1;
- attribute C_BYTE_SIZE : integer;
- attribute C_BYTE_SIZE of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 9;
- attribute C_COMMON_CLK : integer;
- attribute C_COMMON_CLK of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_COUNT_18K_BRAM : string;
- attribute C_COUNT_18K_BRAM of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "1";
- attribute C_COUNT_36K_BRAM : string;
- attribute C_COUNT_36K_BRAM of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "0";
- attribute C_CTRL_ECC_ALGO : string;
- attribute C_CTRL_ECC_ALGO of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "NONE";
- attribute C_DEFAULT_DATA : string;
- attribute C_DEFAULT_DATA of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "0";
- attribute C_DISABLE_WARN_BHV_COLL : integer;
- attribute C_DISABLE_WARN_BHV_COLL of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_DISABLE_WARN_BHV_RANGE : integer;
- attribute C_DISABLE_WARN_BHV_RANGE of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_ELABORATION_DIR : string;
- attribute C_ELABORATION_DIR of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "./";
- attribute C_ENABLE_32BIT_ADDRESS : integer;
- attribute C_ENABLE_32BIT_ADDRESS of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_EN_DEEPSLEEP_PIN : integer;
- attribute C_EN_DEEPSLEEP_PIN of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_EN_ECC_PIPE : integer;
- attribute C_EN_ECC_PIPE of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_EN_RDADDRA_CHG : integer;
- attribute C_EN_RDADDRA_CHG of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_EN_RDADDRB_CHG : integer;
- attribute C_EN_RDADDRB_CHG of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_EN_SAFETY_CKT : integer;
- attribute C_EN_SAFETY_CKT of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_EN_SHUTDOWN_PIN : integer;
- attribute C_EN_SHUTDOWN_PIN of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_EN_SLEEP_PIN : integer;
- attribute C_EN_SLEEP_PIN of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_EST_POWER_SUMMARY : string;
- attribute C_EST_POWER_SUMMARY of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "Estimated Power for IP : 2.810143 mW";
- attribute C_FAMILY : string;
- attribute C_FAMILY of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "kintexu";
- attribute C_HAS_AXI_ID : integer;
- attribute C_HAS_AXI_ID of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_HAS_ENA : integer;
- attribute C_HAS_ENA of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_HAS_ENB : integer;
- attribute C_HAS_ENB of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 1;
- attribute C_HAS_INJECTERR : integer;
- attribute C_HAS_INJECTERR of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
- attribute C_HAS_MEM_OUTPUT_REGS_A of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
- attribute C_HAS_MEM_OUTPUT_REGS_B of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 1;
- attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
- attribute C_HAS_MUX_OUTPUT_REGS_A of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
- attribute C_HAS_MUX_OUTPUT_REGS_B of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_HAS_REGCEA : integer;
- attribute C_HAS_REGCEA of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_HAS_REGCEB : integer;
- attribute C_HAS_REGCEB of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_HAS_RSTA : integer;
- attribute C_HAS_RSTA of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_HAS_RSTB : integer;
- attribute C_HAS_RSTB of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
- attribute C_HAS_SOFTECC_INPUT_REGS_A of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
- attribute C_HAS_SOFTECC_OUTPUT_REGS_B of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_INITA_VAL : string;
- attribute C_INITA_VAL of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "0";
- attribute C_INITB_VAL : string;
- attribute C_INITB_VAL of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "0";
- attribute C_INIT_FILE : string;
- attribute C_INIT_FILE of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "Distr_LUT_felig.mem";
- attribute C_INIT_FILE_NAME : string;
- attribute C_INIT_FILE_NAME of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "Distr_LUT_felig.mif";
- attribute C_INTERFACE_TYPE : integer;
- attribute C_INTERFACE_TYPE of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_LOAD_INIT_FILE : integer;
- attribute C_LOAD_INIT_FILE of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 1;
- attribute C_MEM_TYPE : integer;
- attribute C_MEM_TYPE of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 1;
- attribute C_MUX_PIPELINE_STAGES : integer;
- attribute C_MUX_PIPELINE_STAGES of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_PRIM_TYPE : integer;
- attribute C_PRIM_TYPE of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 1;
- attribute C_READ_DEPTH_A : integer;
- attribute C_READ_DEPTH_A of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 1024;
- attribute C_READ_DEPTH_B : integer;
- attribute C_READ_DEPTH_B of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 1024;
- attribute C_READ_WIDTH_A : integer;
- attribute C_READ_WIDTH_A of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 16;
- attribute C_READ_WIDTH_B : integer;
- attribute C_READ_WIDTH_B of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 16;
- attribute C_RSTRAM_A : integer;
- attribute C_RSTRAM_A of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_RSTRAM_B : integer;
- attribute C_RSTRAM_B of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_RST_PRIORITY_A : string;
- attribute C_RST_PRIORITY_A of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "CE";
- attribute C_RST_PRIORITY_B : string;
- attribute C_RST_PRIORITY_B of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "CE";
- attribute C_SIM_COLLISION_CHECK : string;
- attribute C_SIM_COLLISION_CHECK of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "ALL";
- attribute C_USE_BRAM_BLOCK : integer;
- attribute C_USE_BRAM_BLOCK of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_USE_BYTE_WEA : integer;
- attribute C_USE_BYTE_WEA of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_USE_BYTE_WEB : integer;
- attribute C_USE_BYTE_WEB of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_USE_DEFAULT_DATA : integer;
- attribute C_USE_DEFAULT_DATA of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_USE_ECC : integer;
- attribute C_USE_ECC of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_USE_SOFTECC : integer;
- attribute C_USE_SOFTECC of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_USE_URAM : integer;
- attribute C_USE_URAM of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 0;
- attribute C_WEA_WIDTH : integer;
- attribute C_WEA_WIDTH of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 1;
- attribute C_WEB_WIDTH : integer;
- attribute C_WEB_WIDTH of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 1;
- attribute C_WRITE_DEPTH_A : integer;
- attribute C_WRITE_DEPTH_A of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 1024;
- attribute C_WRITE_DEPTH_B : integer;
- attribute C_WRITE_DEPTH_B of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 1024;
- attribute C_WRITE_MODE_A : string;
- attribute C_WRITE_MODE_A of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "NO_CHANGE";
- attribute C_WRITE_MODE_B : string;
- attribute C_WRITE_MODE_B of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "WRITE_FIRST";
- attribute C_WRITE_WIDTH_A : integer;
- attribute C_WRITE_WIDTH_A of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 16;
- attribute C_WRITE_WIDTH_B : integer;
- attribute C_WRITE_WIDTH_B of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is 16;
- attribute C_XDEVICEFAMILY : string;
- attribute C_XDEVICEFAMILY of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "kintexu";
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "blk_mem_gen_v8_4_1";
- attribute downgradeipidentifiedwarnings : string;
- attribute downgradeipidentifiedwarnings of Distr_LUT_felig_blk_mem_gen_v8_4_1 : entity is "yes";
-end Distr_LUT_felig_blk_mem_gen_v8_4_1;
+`protect key_keyowner="Xilinx", key_keyname="xilinxt_2023_11", key_method="rsa"
+`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
+`protect key_block
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-architecture STRUCTURE of Distr_LUT_felig_blk_mem_gen_v8_4_1 is
- signal \<const0>\ : STD_LOGIC;
-begin
- dbiterr <= \<const0>\;
- douta(15) <= \<const0>\;
- douta(14) <= \<const0>\;
- douta(13) <= \<const0>\;
- douta(12) <= \<const0>\;
- douta(11) <= \<const0>\;
- douta(10) <= \<const0>\;
- douta(9) <= \<const0>\;
- douta(8) <= \<const0>\;
- douta(7) <= \<const0>\;
- douta(6) <= \<const0>\;
- douta(5) <= \<const0>\;
- douta(4) <= \<const0>\;
- douta(3) <= \<const0>\;
- douta(2) <= \<const0>\;
- douta(1) <= \<const0>\;
- douta(0) <= \<const0>\;
- rdaddrecc(9) <= \<const0>\;
- rdaddrecc(8) <= \<const0>\;
- rdaddrecc(7) <= \<const0>\;
- rdaddrecc(6) <= \<const0>\;
- rdaddrecc(5) <= \<const0>\;
- rdaddrecc(4) <= \<const0>\;
- rdaddrecc(3) <= \<const0>\;
- rdaddrecc(2) <= \<const0>\;
- rdaddrecc(1) <= \<const0>\;
- rdaddrecc(0) <= \<const0>\;
- rsta_busy <= \<const0>\;
- rstb_busy <= \<const0>\;
- s_axi_arready <= \<const0>\;
- s_axi_awready <= \<const0>\;
- s_axi_bid(3) <= \<const0>\;
- s_axi_bid(2) <= \<const0>\;
- s_axi_bid(1) <= \<const0>\;
- s_axi_bid(0) <= \<const0>\;
- s_axi_bresp(1) <= \<const0>\;
- s_axi_bresp(0) <= \<const0>\;
- s_axi_bvalid <= \<const0>\;
- s_axi_dbiterr <= \<const0>\;
- s_axi_rdaddrecc(9) <= \<const0>\;
- s_axi_rdaddrecc(8) <= \<const0>\;
- s_axi_rdaddrecc(7) <= \<const0>\;
- s_axi_rdaddrecc(6) <= \<const0>\;
- s_axi_rdaddrecc(5) <= \<const0>\;
- s_axi_rdaddrecc(4) <= \<const0>\;
- s_axi_rdaddrecc(3) <= \<const0>\;
- s_axi_rdaddrecc(2) <= \<const0>\;
- s_axi_rdaddrecc(1) <= \<const0>\;
- s_axi_rdaddrecc(0) <= \<const0>\;
- s_axi_rdata(15) <= \<const0>\;
- s_axi_rdata(14) <= \<const0>\;
- s_axi_rdata(13) <= \<const0>\;
- s_axi_rdata(12) <= \<const0>\;
- s_axi_rdata(11) <= \<const0>\;
- s_axi_rdata(10) <= \<const0>\;
- s_axi_rdata(9) <= \<const0>\;
- s_axi_rdata(8) <= \<const0>\;
- s_axi_rdata(7) <= \<const0>\;
- s_axi_rdata(6) <= \<const0>\;
- s_axi_rdata(5) <= \<const0>\;
- s_axi_rdata(4) <= \<const0>\;
- s_axi_rdata(3) <= \<const0>\;
- s_axi_rdata(2) <= \<const0>\;
- s_axi_rdata(1) <= \<const0>\;
- s_axi_rdata(0) <= \<const0>\;
- s_axi_rid(3) <= \<const0>\;
- s_axi_rid(2) <= \<const0>\;
- s_axi_rid(1) <= \<const0>\;
- s_axi_rid(0) <= \<const0>\;
- s_axi_rlast <= \<const0>\;
- s_axi_rresp(1) <= \<const0>\;
- s_axi_rresp(0) <= \<const0>\;
- s_axi_rvalid <= \<const0>\;
- s_axi_sbiterr <= \<const0>\;
- s_axi_wready <= \<const0>\;
- sbiterr <= \<const0>\;
-GND: unisim.vcomponents.GND
- port map (
- G => \<const0>\
- );
-inst_blk_mem_gen: entity work.Distr_LUT_felig_blk_mem_gen_v8_4_1_synth
- port map (
- addra(9 downto 0) => addra(9 downto 0),
- addrb(9 downto 0) => addrb(9 downto 0),
- clka => clka,
- clkb => clkb,
- dina(15 downto 0) => dina(15 downto 0),
- doutb(15 downto 0) => doutb(15 downto 0),
- enb => enb,
- sleep => sleep,
- wea(0) => wea(0)
- );
-end STRUCTURE;
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+`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
@@ -674,11 +680,11 @@ entity Distr_LUT_felig is
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of Distr_LUT_felig : entity is true;
attribute CHECK_LICENSE_TYPE : string;
- attribute CHECK_LICENSE_TYPE of Distr_LUT_felig : entity is "Distr_LUT_felig,blk_mem_gen_v8_4_1,{}";
+ attribute CHECK_LICENSE_TYPE of Distr_LUT_felig : entity is "Distr_LUT_felig,blk_mem_gen_v8_4_8,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of Distr_LUT_felig : entity is "yes";
attribute x_core_info : string;
- attribute x_core_info of Distr_LUT_felig : entity is "blk_mem_gen_v8_4_1,Vivado 2018.1";
+ attribute x_core_info of Distr_LUT_felig : entity is "blk_mem_gen_v8_4_8,Vivado 2024.1";
end Distr_LUT_felig;
architecture STRUCTURE of Distr_LUT_felig is
@@ -802,6 +808,10 @@ architecture STRUCTURE of Distr_LUT_felig is
attribute C_READ_DEPTH_A of U0 : label is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 1024;
+ attribute C_READ_LATENCY_A : integer;
+ attribute C_READ_LATENCY_A of U0 : label is 1;
+ attribute C_READ_LATENCY_B : integer;
+ attribute C_READ_LATENCY_B of U0 : label is 1;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 16;
attribute C_READ_WIDTH_B : integer;
@@ -849,12 +859,14 @@ architecture STRUCTURE of Distr_LUT_felig is
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
+ attribute is_du_within_envelope : string;
+ attribute is_du_within_envelope of U0 : label is "true";
attribute x_interface_info : string;
attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
attribute x_interface_parameter : string;
- attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER";
+ attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
- attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER";
+ attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
@@ -862,7 +874,7 @@ architecture STRUCTURE of Distr_LUT_felig is
attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
begin
-U0: entity work.Distr_LUT_felig_blk_mem_gen_v8_4_1
+U0: entity work.Distr_LUT_felig_blk_mem_gen_v8_4_8
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9 downto 0) => addrb(9 downto 0),
@@ -880,8 +892,8 @@ U0: entity work.Distr_LUT_felig_blk_mem_gen_v8_4_1
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
- regcea => '0',
- regceb => '0',
+ regcea => '1',
+ regceb => '1',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',