diff --git a/sources/LpGBT/LpGBT_FELIX/lpgbtemul_top.vhd b/sources/LpGBT/LpGBT_FELIX/lpgbtemul_top.vhd
index 41162920e946061d4a85a93097e396e3412e8cc9..7afabec7a3381311e8788402b8b8218a418c07ac 100644
--- a/sources/LpGBT/LpGBT_FELIX/lpgbtemul_top.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/lpgbtemul_top.vhd
@@ -1,7 +1,7 @@
-- IEEE VHDL standard library:
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
--use work.lpgbtfpga_package.all;
--=================================================================================================--
@@ -11,20 +11,20 @@ use ieee.numeric_std.all;
entity lpgbtemul_top is
generic(
-- MGT-specific parameters
- -- Read your MGT user guide before connecting them
+ -- Read your MGT user guide before connecting them
rxslide_pulse_duration : integer:= 2; -- Duration of GT_RXSLIDE_OUT pulse
rxslide_pulse_delay : integer:= 128 -- Minimum time between two GT_RXSLIDE_OUT pulses
);
- port(
+ port(
-- DownLink
- downlinkClkEn_o : out std_logic;
+ downlinkClkEn_o : out std_logic;
downLinkDataGroup0 : out std_logic_vector(15 downto 0);
downLinkDataGroup1 : out std_logic_vector(15 downto 0);
downLinkDataEc : out std_logic_vector(1 downto 0);
downLinkDataIc : out std_logic_vector(1 downto 0);
downlinkRdy_o : out std_logic;
-
- -- Uplink
+
+ -- Uplink
uplinkClkEn_i : in std_logic;
upLinkData0 : in std_logic_vector(31 downto 0);
upLinkData1 : in std_logic_vector(31 downto 0);
@@ -36,30 +36,30 @@ entity lpgbtemul_top is
upLinkDataIC : in std_logic_vector(1 downto 0);
upLinkDataEC : in std_logic_vector(1 downto 0);
uplinkRdy_o : out std_logic;
-
- -- Uplink mode
+
+ -- Uplink mode
fecMode : in std_logic; -- 0=FEC5, 1=FEC12
txDataRate : in std_logic; -- 1=5G , 2=10G
- -- Transceiver
+ -- Transceiver
GT_RXUSRCLK_IN : in std_logic;
GT_TXUSRCLK_IN : in std_logic;
- GT_RXSLIDE_OUT : out std_logic;
+ GT_RXSLIDE_OUT : out std_logic;
GT_TXREADY_IN : in std_logic;
GT_RXREADY_IN : in std_logic;
GT_TXDATA_OUT : out std_logic_vector(31 downto 0);
GT_RXDATA_IN : in std_logic_vector(31 downto 0)
- );
+ );
end lpgbtemul_top;
--=================================================================================================--
---#################################### Architecture ###########################################--
+--#################################### Architecture ###########################################--
--=================================================================================================--
architecture behavioral of lpgbtemul_top is
- -- Downlink
+ -- Downlink
signal dat_downLinkWord_fromMgt_s : std_logic_vector(31 downto 0);
signal sta_mgtRxRdy_s : std_logic;
signal rst_pattsearch_s : std_logic;
@@ -106,59 +106,59 @@ architecture behavioral of lpgbtemul_top is
signal upLinkDataIC_s : std_logic_vector(1 downto 0);
signal upLinkDataEC_s : std_logic_vector(1 downto 0);
- component upLinkTxDataPath
- port (
- clk : in std_logic;
- dataEnable : in std_logic;
- txDataGroup0 : in std_logic_vector(31 downto 0);
- txDataGroup1 : in std_logic_vector(31 downto 0);
- txDataGroup2 : in std_logic_vector(31 downto 0);
- txDataGroup3 : in std_logic_vector(31 downto 0);
- txDataGroup4 : in std_logic_vector(31 downto 0);
- txDataGroup5 : in std_logic_vector(31 downto 0);
- txDataGroup6 : in std_logic_vector(31 downto 0);
-
- txIC : in std_logic_vector( 1 downto 0);
- txEC : in std_logic_vector( 1 downto 0);
- txDummyFec5 : in std_logic_vector( 5 downto 0);
- txDummyFec12 : in std_logic_vector( 9 downto 0);
- scramblerBypass : in std_logic;
- interleaverBypass : in std_logic;
- fecMode : in std_logic;
- txDataRate : in std_logic;
- fecDisable : in std_logic;
- scramblerReset : in std_logic;
- upLinkFrame : out std_logic_vector(255 downto 0)
- );
+ component upLinkTxDataPath
+ port (
+ clk : in std_logic;
+ dataEnable : in std_logic;
+ txDataGroup0 : in std_logic_vector(31 downto 0);
+ txDataGroup1 : in std_logic_vector(31 downto 0);
+ txDataGroup2 : in std_logic_vector(31 downto 0);
+ txDataGroup3 : in std_logic_vector(31 downto 0);
+ txDataGroup4 : in std_logic_vector(31 downto 0);
+ txDataGroup5 : in std_logic_vector(31 downto 0);
+ txDataGroup6 : in std_logic_vector(31 downto 0);
+
+ txIC : in std_logic_vector( 1 downto 0);
+ txEC : in std_logic_vector( 1 downto 0);
+ txDummyFec5 : in std_logic_vector( 5 downto 0);
+ txDummyFec12 : in std_logic_vector( 9 downto 0);
+ scramblerBypass : in std_logic;
+ interleaverBypass : in std_logic;
+ fecMode : in std_logic;
+ txDataRate : in std_logic;
+ fecDisable : in std_logic;
+ scramblerReset : in std_logic;
+ upLinkFrame : out std_logic_vector(255 downto 0)
+ );
end component;
-
- component downLinkRxDataPath
- port (
- clk : in std_logic;
- downLinkFrame : in std_logic_vector( 63 downto 0);
- dataStrobe : out std_logic;
- dataOut : out std_logic_vector( 31 downto 0);
- dataEC : out std_logic_vector( 1 downto 0);
- dataIC : out std_logic_vector( 1 downto 0);
- header : out std_logic_vector( 3 downto 0);
- dataEnable : in std_logic;
- bypassDeinterleaver : in std_logic;
- bypassFECDecoder : in std_logic;
- bypassDescrambler : in std_logic;
- fecCorrectionCount : out std_logic_vector( 15 downto 0)
+
+ component downLinkRxDataPath
+ port (
+ clk : in std_logic;
+ downLinkFrame : in std_logic_vector( 63 downto 0);
+ dataStrobe : out std_logic;
+ dataOut : out std_logic_vector( 31 downto 0);
+ dataEC : out std_logic_vector( 1 downto 0);
+ dataIC : out std_logic_vector( 1 downto 0);
+ header : out std_logic_vector( 3 downto 0);
+ dataEnable : in std_logic;
+ bypassDeinterleaver : in std_logic;
+ bypassFECDecoder : in std_logic;
+ bypassDescrambler : in std_logic;
+ fecCorrectionCount : out std_logic_vector( 15 downto 0)
);
end component;
-
-begin --========#### Architecture Body ####========--
+
+begin --========#### Architecture Body ####========--
---------------------------- Downlink ----------------------------
sta_mgtRxRdy_s <= GT_RXREADY_IN ;
rst_pattsearch_s <= not(sta_mgtRxRdy_s) ;
rst_datapath_s <= not(sta_headeLocked_s);
- clk_mgtRxUsrclk_s <= GT_RXUSRCLK_IN ;
- GT_RXSLIDE_OUT <= ctr_clkSlip_s ;
+ clk_mgtRxUsrclk_s <= GT_RXUSRCLK_IN ;
+ GT_RXSLIDE_OUT <= ctr_clkSlip_s ;
dat_downLinkWord_fromMgt_s <= GT_RXDATA_IN ;
@@ -175,19 +175,19 @@ begin --========#### Architecture Body ####========--
downlinkRdy_s1 <= downlinkRdy_s0;
downlinkRdy_o <= downlinkRdy_s1;
end if;
- end if;
+ end if;
end process;
--! Multicycle path configuration (downlink)
syncShiftRegDown_proc: process(sta_rxgbxRdy_s, clk_mgtRxUsrclk_s)
variable cnter : integer range 0 to 7;
begin
-
+
if sta_rxgbxRdy_s = '0' then
- cnter := 0;
- RX_CLKEn_s <= '0';
- rst_downlinkInitDone_s <= '0';
-
+ cnter := 0;
+ RX_CLKEn_s <= '0';
+ rst_downlinkInitDone_s <= '0';
+
elsif rising_edge(clk_mgtRxUsrclk_s) then
if clk_dataFlag_rxGb_s = '1' then
cnter := 0;
@@ -198,10 +198,10 @@ begin --========#### Architecture Body ####========--
RX_CLKEn_s <= '0';
if cnter = 4 then
RX_CLKEn_s <= rst_downlinkInitDone_s;
- end if;
+ end if;
end if;
end process;
-
+
-- Pattern aligner
mgt_framealigner_inst: entity work.mgt_framealigner
GENERIC map (
@@ -215,27 +215,27 @@ begin --========#### Architecture Body ####========--
c_bitslip_waitdly => rxslide_pulse_delay
)
- PORT map (
+ PORT map (
-- Clock(s)
clk_pcsRx_i => clk_mgtRxUsrclk_s,
-
+
-- Reset(s)
rst_pattsearch_i => rst_pattsearch_s,
-
+
-- Control
cmd_bitslipCtrl_o => ctr_clkSlip_s,
-
+
-- Status
sta_headerLocked_o => sta_headeLocked_s,
sta_headerFlag_o => sta_headerFlag_s,
sta_bitSlipEven_o => open,
-- Data
dat_word_i => dat_downLinkWord_toPattSrch_s
- );
+ );
- dat_downLinkWord_toPattSrch_s <= dat_downLinkWord_fromMgt_s(24) & dat_downLinkWord_fromMgt_s(25) & dat_downLinkWord_fromMgt_s(26) & dat_downLinkWord_fromMgt_s(27) &
- dat_downLinkWord_fromMgt_s(16) & dat_downLinkWord_fromMgt_s(17) & dat_downLinkWord_fromMgt_s(18) & dat_downLinkWord_fromMgt_s(19) &
- dat_downLinkWord_fromMgt_s(8) & dat_downLinkWord_fromMgt_s(9) & dat_downLinkWord_fromMgt_s(10) & dat_downLinkWord_fromMgt_s(11) &
+ dat_downLinkWord_toPattSrch_s <= dat_downLinkWord_fromMgt_s(24) & dat_downLinkWord_fromMgt_s(25) & dat_downLinkWord_fromMgt_s(26) & dat_downLinkWord_fromMgt_s(27) &
+ dat_downLinkWord_fromMgt_s(16) & dat_downLinkWord_fromMgt_s(17) & dat_downLinkWord_fromMgt_s(18) & dat_downLinkWord_fromMgt_s(19) &
+ dat_downLinkWord_fromMgt_s(8) & dat_downLinkWord_fromMgt_s(9) & dat_downLinkWord_fromMgt_s(10) & dat_downLinkWord_fromMgt_s(11) &
dat_downLinkWord_fromMgt_s(3) & dat_downLinkWord_fromMgt_s(2) & dat_downLinkWord_fromMgt_s(1) & dat_downLinkWord_fromMgt_s(0);
-- Downlink gearbox
@@ -257,7 +257,7 @@ begin --========#### Architecture Body ####========--
-- Data
dat_inFrame_i => dat_downLinkWord_fromMgt_s,
dat_outFrame_o => dat_downLinkWord_fromGb_s,
-
+
-- Status
sta_gbRdy_o => sta_rxgbxRdy_s
);
@@ -266,7 +266,7 @@ begin --========#### Architecture Body ####========--
port map (
clk => clk_mgtRxUsrclk_s,
downLinkFrame => dat_downLinkWord_fromGb_s(63 downto 0),
- dataStrobe => open,
+ dataStrobe => open,
dataOut(15 downto 0) => downLinkDataGroup0_s,
dataOut(31 downto 16) => downLinkDataGroup1_s,
dataEC => downLinkDataEc_s,
@@ -279,15 +279,15 @@ begin --========#### Architecture Body ####========--
fecCorrectionCount => open
);
- downlinkClkEn_o <= RX_CLKEn_s;
+ downlinkClkEn_o <= RX_CLKEn_s;
downLinkDataGroup0 <= downLinkDataGroup0_s;
downLinkDataGroup1 <= downLinkDataGroup1_s;
downLinkDataEc <= downLinkDataEc_s;
downLinkDataIc <= downLinkDataIc_s;
-------------------------------------------------------------------
- ---------------------------- Uplink -------------------------------
- sta_mgtTxRdy_s <= GT_TXREADY_IN;
+ ---------------------------- Uplink -------------------------------
+ sta_mgtTxRdy_s <= GT_TXREADY_IN;
rst_uplinkGb_s <= not(sta_mgtTxRdy_s);
uplinkRdy_o <= sta_txGbRdy_s;
clk_mgtTxUsrclk_s <= GT_TXUSRCLK_IN;
@@ -297,19 +297,19 @@ begin --========#### Architecture Body ####========--
variable cnter : integer range 0 to 7;
begin
if rst_uplinkGb_s = '1' then
- cnter := 0;
- uplinkClkEn_shgb_s <= '0';
- rst_uplinkGb_synch_s <= '1';
- rst_uplinkInitDone_s <= '0';
- upLinkData0_s <= (others => '0');
- upLinkData1_s <= (others => '0');
- upLinkData2_s <= (others => '0');
- upLinkData3_s <= (others => '0');
- upLinkData4_s <= (others => '0');
- upLinkData5_s <= (others => '0');
- upLinkData6_s <= (others => '0');
- upLinkDataIC_s <= (others => '0');
- upLinkDataEC_s <= (others => '0');
+ cnter := 0;
+ uplinkClkEn_shgb_s <= '0';
+ rst_uplinkGb_synch_s <= '1';
+ rst_uplinkInitDone_s <= '0';
+ upLinkData0_s <= (others => '0');
+ upLinkData1_s <= (others => '0');
+ upLinkData2_s <= (others => '0');
+ upLinkData3_s <= (others => '0');
+ upLinkData4_s <= (others => '0');
+ upLinkData5_s <= (others => '0');
+ upLinkData6_s <= (others => '0');
+ upLinkDataIC_s <= (others => '0');
+ upLinkDataEC_s <= (others => '0');
elsif rising_edge(clk_mgtTxUsrclk_s) then
if uplinkClkEn_i = '1' then
cnter := 0;
@@ -330,14 +330,14 @@ begin --========#### Architecture Body ####========--
if cnter = 4 then
uplinkClkEn_shgb_s <= '1';
rst_uplinkGb_synch_s <= rst_uplinkGb_s or not(rst_uplinkInitDone_s);
- end if;
+ end if;
end if;
end process;
txdatapath_inst : upLinkTxDataPath
port map (
clk => clk_mgtTxUsrclk_s,
- dataEnable => uplinkClkEn_i,
+ dataEnable => uplinkClkEn_i,
txDataGroup0 => upLinkData0_s,
txDataGroup1 => upLinkData1_s,
txDataGroup2 => upLinkData2_s,
@@ -359,33 +359,33 @@ begin --========#### Architecture Body ####========--
);
upLinkPipelineBeforeOversampling_proc: process(rst_uplinkGb_s, clk_mgtTxUsrclk_s)
- begin
+ begin
if rst_uplinkGb_s = '1' then
dat_upLinkWord_fromLpGBT_pipeline_s <= (others => '0');
elsif rising_edge(clk_mgtTxUsrclk_s) then
if uplinkClkEn_i='1' then
- dat_upLinkWord_fromLpGBT_pipeline_s <= dat_upLinkWord_fromLpGBT_s;
+ dat_upLinkWord_fromLpGBT_pipeline_s <= dat_upLinkWord_fromLpGBT_s;
end if;
- end if;
- end process;
+ end if;
+ end process;
oversampler_gen: for i in 0 to 127 generate
oversampler_ph_gen: for j in 0 to 1 generate
dat_upLinkWord_toGb_s((i*2)+j) <= dat_upLinkWord_fromLpGBT_pipeline_s(i) when txDataRate = '0' else
dat_upLinkWord_fromLpGBT_pipeline_s((i*2)+j);
end generate;
- end generate;
+ end generate;
upLinkPipelineAfterOversampling_proc: process(rst_uplinkGb_s, clk_mgtTxUsrclk_s)
- begin
+ begin
if rst_uplinkGb_s = '1' then
dat_upLinkWord_toGb_pipeline_s <= (others => '0');
elsif rising_edge(clk_mgtTxUsrclk_s) then
if uplinkClkEn_shgb_s = '1' then
- dat_upLinkWord_toGb_pipeline_s <= dat_upLinkWord_toGb_s;
+ dat_upLinkWord_toGb_pipeline_s <= dat_upLinkWord_toGb_s;
end if;
- end if;
- end process;
+ end if;
+ end process;
txGearbox_inst: entity work.txGearbox
generic map (
@@ -395,7 +395,7 @@ begin --========#### Architecture Body ####========--
)
port map (
-- Clock and reset
- clk_inClk_i => clk_mgtTxUsrclk_s ,
+ clk_inClk_i => clk_mgtTxUsrclk_s ,
clk_clkEn_i => uplinkClkEn_shgb_s ,
clk_outClk_i => clk_mgtTxUsrclk_s ,
rst_gearbox_i => rst_uplinkGb_synch_s ,
@@ -405,7 +405,7 @@ begin --========#### Architecture Body ####========--
);
GT_TXDATA_OUT <= dat_upLinkWord_fromGb_s;
- -------------------------------------------------------------------
+-------------------------------------------------------------------
end behavioral;
--=================================================================================================--