diff --git a/scripts/FELIX_top/do_implementation_BNL712_FULL_24ch.tcl b/scripts/FELIX_top/do_implementation_BNL712_FULL_24ch.tcl
index 1fb88a579f15fa53f0c0a7fde07b5128d937b917..ce62173baf8f2e6460b493404dd18b9187727ffc 100644
--- a/scripts/FELIX_top/do_implementation_BNL712_FULL_24ch.tcl
+++ b/scripts/FELIX_top/do_implementation_BNL712_FULL_24ch.tcl
@@ -47,5 +47,7 @@ set FIRMWARE_MODE $FIRMWARE_MODE_FULL
#uncomment to build the FIRMWARE with LTI_TTC system
#set TTC_SYS_SEL $LTITTC
+#Set to false to set BUILD_TIME to the clock, true for GIT_COMMIT_TIME. With false, the build is reproducible.
+set DETERMINISTIC_BUILD_TIME false
source ../helper/do_implementation_post.tcl
diff --git a/scripts/FELIX_top/do_implementation_BNL712_LPGBT_20ch.tcl b/scripts/FELIX_top/do_implementation_BNL712_LPGBT_20ch.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..94dfcdb9ae1bae6cfa9c93c7e0bd3921d4fbf233
--- /dev/null
+++ b/scripts/FELIX_top/do_implementation_BNL712_LPGBT_20ch.tcl
@@ -0,0 +1,63 @@
+
+# This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+# Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+# Authors:
+# Kai Chen
+# Weihao Wu
+# Andrea Borga
+# Enrico Gamberini
+# William Wulff
+# Frans Schreuder
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+source ../helper/do_implementation_pre.tcl
+
+#set STOP_TO_ADD_ILA to 1 in order to stop after synthesis phase and add an ILA
+set STOP_TO_ADD_ILA 0
+
+set GBT_NUM 20
+set OPTO_TRX 4
+set CARD_TYPE 712
+set app_clk_freq 200
+set ENDPOINTS 2
+set GTREFCLKS 5
+
+set PLL_SEL $CPLL
+
+set IncludeDecodingEpath2_HDLC 7'b0000000
+set IncludeDecodingEpath2_8b10b 7'b0000000
+set IncludeDecodingEpath4_8b10b 7'b0000000
+set IncludeDecodingEpath8_8b10b 7'b1111111
+set IncludeDecodingEpath16_8b10b 7'b1111111
+set IncludeDecodingEpath32_8b10b 7'b1111111
+
+set IncludeEncodingEpath2_HDLC 5'b00000
+set IncludeEncodingEpath2_8b10b 5'b01111
+set IncludeEncodingEpath4_8b10b 5'b01111
+set IncludeEncodingEpath8_8b10b 5'b01111
+set INCLUDE_DIRECT 5'b01111
+set INCLUDE_TTC 5'b01111
+set INCLUDE_RD53 5'b00000
+
+#determine the FIRMWARE_MODE register value
+# 0: GBT mode
+# 1: FULL mode
+# 2: LTDB mode (GBT mode with only IC and TTC links)
+# 3: FE-I4B mode
+set FIRMWARE_MODE $FIRMWARE_MODE_LPGBT
+
+#Set to false to set BUILD_TIME to the clock, true for GIT_COMMIT_TIME. With false, the build is reproducible.
+set DETERMINISTIC_BUILD_TIME false
+
+source ../helper/do_implementation_post.tcl
diff --git a/scripts/FELIX_top/do_implementation_BNL712_LPGBT_24ch.tcl b/scripts/FELIX_top/do_implementation_BNL712_LPGBT_24ch.tcl
index 9d16d30f0b29d40cfedb51e4d05999e2f721ddd5..6b171d1f320752398c819e528574f4f8b0e2f451 100644
--- a/scripts/FELIX_top/do_implementation_BNL712_LPGBT_24ch.tcl
+++ b/scripts/FELIX_top/do_implementation_BNL712_LPGBT_24ch.tcl
@@ -33,11 +33,11 @@ set app_clk_freq 200
set ENDPOINTS 2
set GTREFCLKS 5
-set PLL_SEL $QPLL
+set PLL_SEL $CPLL
-set IncludeDecodingEpath2_HDLC 7'b1111111
-set IncludeDecodingEpath2_8b10b 7'b1111111
-set IncludeDecodingEpath4_8b10b 7'b1111111
+set IncludeDecodingEpath2_HDLC 7'b0000000
+set IncludeDecodingEpath2_8b10b 7'b0000000
+set IncludeDecodingEpath4_8b10b 7'b0000000
set IncludeDecodingEpath8_8b10b 7'b1111111
set IncludeDecodingEpath16_8b10b 7'b1111111
set IncludeDecodingEpath32_8b10b 7'b1111111
@@ -57,4 +57,7 @@ set INCLUDE_RD53 5'b00000
# 3: FE-I4B mode
set FIRMWARE_MODE $FIRMWARE_MODE_LPGBT
+#Set to false to set BUILD_TIME to the clock, true for GIT_COMMIT_TIME. With false, the build is reproducible.
+set DETERMINISTIC_BUILD_TIME false
+
source ../helper/do_implementation_post.tcl
diff --git a/scripts/FELIX_top/do_implementation_BNL712_LPGBT_4ch.tcl b/scripts/FELIX_top/do_implementation_BNL712_LPGBT_4ch.tcl
index 569fd8dec2760662e2e59dcc31b194e25899d0e8..438813c709c7adf3bcd704757bd7f683b4ddb0a2 100644
--- a/scripts/FELIX_top/do_implementation_BNL712_LPGBT_4ch.tcl
+++ b/scripts/FELIX_top/do_implementation_BNL712_LPGBT_4ch.tcl
@@ -2,10 +2,11 @@
# This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
# Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
# Authors:
-# Andrea Borga
-# Israel Grayzman
# Kai Chen
-# RHabraken
+# Weihao Wu
+# Andrea Borga
+# Enrico Gamberini
+# William Wulff
# Frans Schreuder
#
# Licensed under the Apache License, Version 2.0 (the "License");
@@ -32,7 +33,7 @@ set app_clk_freq 200
set ENDPOINTS 2
set GTREFCLKS 5
-set PLL_SEL $QPLL
+set PLL_SEL $CPLL
set IncludeDecodingEpath2_HDLC 7'b0000000
set IncludeDecodingEpath2_8b10b 7'b0000000
@@ -45,13 +46,10 @@ set IncludeEncodingEpath2_HDLC 5'b00000
set IncludeEncodingEpath2_8b10b 5'b01111
set IncludeEncodingEpath4_8b10b 5'b01111
set IncludeEncodingEpath8_8b10b 5'b01111
-set INCLUDE_DIRECT 5'b00000
+set INCLUDE_DIRECT 5'b01111
set INCLUDE_TTC 5'b01111
set INCLUDE_RD53 5'b00000
-#Use clock to set timestamp, so every build is different and might meet timing...
-set DETERMINISTIC_BUILD_TIME false
-
#determine the FIRMWARE_MODE register value
# 0: GBT mode
# 1: FULL mode
@@ -59,4 +57,7 @@ set DETERMINISTIC_BUILD_TIME false
# 3: FE-I4B mode
set FIRMWARE_MODE $FIRMWARE_MODE_LPGBT
+#Set to false to set BUILD_TIME to the clock, true for GIT_COMMIT_TIME. With false, the build is reproducible.
+set DETERMINISTIC_BUILD_TIME false
+
source ../helper/do_implementation_post.tcl
diff --git a/scripts/FELIX_top/do_implementation_BNL712_LPGBT_8ch.tcl b/scripts/FELIX_top/do_implementation_BNL712_LPGBT_8ch.tcl
index f51c0a9f3896f7a7e55dd51ac66efff288d3a05e..6c4635bca96a19c7879ace42f6f26ba43bfa3424 100644
--- a/scripts/FELIX_top/do_implementation_BNL712_LPGBT_8ch.tcl
+++ b/scripts/FELIX_top/do_implementation_BNL712_LPGBT_8ch.tcl
@@ -2,10 +2,11 @@
# This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
# Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
# Authors:
-# Andrea Borga
-# Israel Grayzman
# Kai Chen
-# RHabraken
+# Weihao Wu
+# Andrea Borga
+# Enrico Gamberini
+# William Wulff
# Frans Schreuder
#
# Licensed under the Apache License, Version 2.0 (the "License");
@@ -32,7 +33,7 @@ set app_clk_freq 200
set ENDPOINTS 2
set GTREFCLKS 5
-set PLL_SEL $QPLL
+set PLL_SEL $CPLL
set IncludeDecodingEpath2_HDLC 7'b0000000
set IncludeDecodingEpath2_8b10b 7'b0000000
@@ -45,7 +46,7 @@ set IncludeEncodingEpath2_HDLC 5'b00000
set IncludeEncodingEpath2_8b10b 5'b01111
set IncludeEncodingEpath4_8b10b 5'b01111
set IncludeEncodingEpath8_8b10b 5'b01111
-set INCLUDE_DIRECT 5'b00000
+set INCLUDE_DIRECT 5'b01111
set INCLUDE_TTC 5'b01111
set INCLUDE_RD53 5'b00000
@@ -56,4 +57,7 @@ set INCLUDE_RD53 5'b00000
# 3: FE-I4B mode
set FIRMWARE_MODE $FIRMWARE_MODE_LPGBT
+#Set to false to set BUILD_TIME to the clock, true for GIT_COMMIT_TIME. With false, the build is reproducible.
+set DETERMINISTIC_BUILD_TIME false
+
source ../helper/do_implementation_post.tcl
diff --git a/scripts/FELIX_top/do_implementation_BNL712_pixel_24ch.tcl b/scripts/FELIX_top/do_implementation_BNL712_pixel_24ch.tcl
index 7f6056ddcecaeba33d93cea3d3a0910d970c4fce..86b628b3156012c2916851faa7fc205d694ab46d 100644
--- a/scripts/FELIX_top/do_implementation_BNL712_pixel_24ch.tcl
+++ b/scripts/FELIX_top/do_implementation_BNL712_pixel_24ch.tcl
@@ -58,4 +58,7 @@ set ISTESTBEAM false
# 9: LPGBT mode
set FIRMWARE_MODE $FIRMWARE_MODE_PIXEL
+#Set to false to set BUILD_TIME to the clock, true for GIT_COMMIT_TIME. With false, the build is reproducible.
+set DETERMINISTIC_BUILD_TIME false
+
source ../helper/do_implementation_post.tcl
diff --git a/scripts/FELIX_top/do_implementation_BNL712_strips_24ch.tcl b/scripts/FELIX_top/do_implementation_BNL712_strips_24ch.tcl
index 2c1f6efda6242a722d5d27f767664be993155efa..610d585aea1126ac5f9d2fd05dcc68a4bc8f1bf2 100644
--- a/scripts/FELIX_top/do_implementation_BNL712_strips_24ch.tcl
+++ b/scripts/FELIX_top/do_implementation_BNL712_strips_24ch.tcl
@@ -28,6 +28,8 @@ set app_clk_freq 200
set ENDPOINTS 2
set GTREFCLKS 5
+set PLL_SEL $CPLL
+
set FIRMWARE_MODE $FIRMWARE_MODE_STRIP
#Tell elinkconfig that only 4 and 8-bit decoding is allowed
diff --git a/sources/ip_cores/kintexUltrascale/KCU_NORXBUF_PCS_CPLL_1CH.xci b/sources/ip_cores/kintexUltrascale/KCU_NORXBUF_PCS_CPLL_1CH.xci
index 9dcb79c18d8f9c12d175e163b9d63a5df8c9f4b7..4e6c4e8bb552803801f1e92795e79810332658c7 100644
--- a/sources/ip_cores/kintexUltrascale/KCU_NORXBUF_PCS_CPLL_1CH.xci
+++ b/sources/ip_cores/kintexUltrascale/KCU_NORXBUF_PCS_CPLL_1CH.xci
@@ -908,4 +908,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/KCU_PMA_QPLL_4CH_LPGBT.xci b/sources/ip_cores/kintexUltrascale/KCU_PMA_QPLL_4CH_LPGBT.xci
index 079b1969aa98001a7dfe951265497743b6456daa..4462dd5f2cce15ff8adbf21a3102bc03c17020f3 100644
--- a/sources/ip_cores/kintexUltrascale/KCU_PMA_QPLL_4CH_LPGBT.xci
+++ b/sources/ip_cores/kintexUltrascale/KCU_PMA_QPLL_4CH_LPGBT.xci
@@ -903,4 +903,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH.xci b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH.xci
index 0d6352e788c8c84e226618df8097128daf43056d..3c6184d7757ae3cf6ca6e6a0e65461a461b01340 100644
--- a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH.xci
+++ b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH.xci
@@ -904,4 +904,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH_LPGBT.xci b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH_LPGBT.xci
index c99fdec1b860985a984bb52c7af9bc8d7a5b08aa..000c02616feac40baffe283e91ee7ce3200da5ae 100644
--- a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH_LPGBT.xci
+++ b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_CPLL_1CH_LPGBT.xci
@@ -893,4 +893,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_4CH.xci b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_4CH.xci
index bdfe8daefad4de04ef47d11194aa197bb964a080..eeaa8251d8c76b5244013af8f1715dafe7eaba10 100644
--- a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_4CH.xci
+++ b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_4CH.xci
@@ -896,4 +896,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT.xci b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT.xci
index 63953fc1354b996965911171238d501c3bb0c53e..80dd401b027ec8b95fbf97e8fba2eac29f7992d3 100644
--- a/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT.xci
+++ b/sources/ip_cores/kintexUltrascale/KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT.xci
@@ -899,4 +899,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/axi8_fifo_bif.xci b/sources/ip_cores/kintexUltrascale/axi8_fifo_bif.xci
index 02093e9b90a5b34faedc6aff7bf4ab7e438d2f25..778506dc7652bb559e586df2897e942216716cc1 100644
--- a/sources/ip_cores/kintexUltrascale/axi8_fifo_bif.xci
+++ b/sources/ip_cores/kintexUltrascale/axi8_fifo_bif.xci
@@ -526,4 +526,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/axi8_fifo_bram.xci b/sources/ip_cores/kintexUltrascale/axi8_fifo_bram.xci
index eab33267641a38083faa537fd51607268d195a42..0ab2fd5369f34107f16b4e632ec53fe27195d981 100644
--- a/sources/ip_cores/kintexUltrascale/axi8_fifo_bram.xci
+++ b/sources/ip_cores/kintexUltrascale/axi8_fifo_bram.xci
@@ -526,4 +526,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/axis32_fifo_bif.xci b/sources/ip_cores/kintexUltrascale/axis32_fifo_bif.xci
index e9b202d07a51c0af37f49828a173549b0355540e..87b60adb22fdc9d13f4b282daad3062c6e04665f 100644
--- a/sources/ip_cores/kintexUltrascale/axis32_fifo_bif.xci
+++ b/sources/ip_cores/kintexUltrascale/axis32_fifo_bif.xci
@@ -528,4 +528,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/clk_wiz_100_0.xci b/sources/ip_cores/kintexUltrascale/clk_wiz_100_0.xci
index 7aa7ef583f9998d9d714726782ed94ecde8a4a5f..bf5e6c72cf026bbcd2a0bfac92a39f1db4a29956 100644
--- a/sources/ip_cores/kintexUltrascale/clk_wiz_100_0.xci
+++ b/sources/ip_cores/kintexUltrascale/clk_wiz_100_0.xci
@@ -683,4 +683,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/clk_wiz_156_0.xci b/sources/ip_cores/kintexUltrascale/clk_wiz_156_0.xci
index c9d62523a05553672f4a0626f888422793679d5f..34cdc88a80e972bbf4ea2a387cf59bd503fac78f 100644
--- a/sources/ip_cores/kintexUltrascale/clk_wiz_156_0.xci
+++ b/sources/ip_cores/kintexUltrascale/clk_wiz_156_0.xci
@@ -683,4 +683,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/clk_wiz_200_0.xci b/sources/ip_cores/kintexUltrascale/clk_wiz_200_0.xci
index 585391458db2513f1548be769f2fd6a94ddef06c..e6dd6c28fdd54bac9c48c95d24d2f95d3d92c48b 100644
--- a/sources/ip_cores/kintexUltrascale/clk_wiz_200_0.xci
+++ b/sources/ip_cores/kintexUltrascale/clk_wiz_200_0.xci
@@ -683,4 +683,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/clk_wiz_250.xci b/sources/ip_cores/kintexUltrascale/clk_wiz_250.xci
index 5c500027a927ed19920de3cc2e7adfea193538e6..2f66e0e5ca229613a0fbc230a9c6a282e6d583c8 100644
--- a/sources/ip_cores/kintexUltrascale/clk_wiz_250.xci
+++ b/sources/ip_cores/kintexUltrascale/clk_wiz_250.xci
@@ -708,4 +708,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/clk_wiz_40_0.xci b/sources/ip_cores/kintexUltrascale/clk_wiz_40_0.xci
index f151891b3dfa411dc2fb988e23c7e21a4793f771..c526fc430f3a469bc43ee3c11da13ea310452d3f 100644
--- a/sources/ip_cores/kintexUltrascale/clk_wiz_40_0.xci
+++ b/sources/ip_cores/kintexUltrascale/clk_wiz_40_0.xci
@@ -784,4 +784,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/clk_wiz_regmap.xci b/sources/ip_cores/kintexUltrascale/clk_wiz_regmap.xci
index cae85df1a9b37a59b2a71b2074bc9a3999d5fd93..4daa385f25b7312fec5bec5f2d277fac5e84714b 100644
--- a/sources/ip_cores/kintexUltrascale/clk_wiz_regmap.xci
+++ b/sources/ip_cores/kintexUltrascale/clk_wiz_regmap.xci
@@ -668,4 +668,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/debug_bridge_0.xci b/sources/ip_cores/kintexUltrascale/debug_bridge_0.xci
index a277ba4206451fe8138a20644bbac4b1d5c81087..11bd7293555c2719383de18677f7c04adfd79e4c 100644
--- a/sources/ip_cores/kintexUltrascale/debug_bridge_0.xci
+++ b/sources/ip_cores/kintexUltrascale/debug_bridge_0.xci
@@ -136,4 +136,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/dsp_counter.xci b/sources/ip_cores/kintexUltrascale/dsp_counter.xci
index 3ebb024d162acbdd3e8a2a44d41f2bfcd680bc7e..1fb588ec221cfe59c3d56be89525e8ea383cec75 100644
--- a/sources/ip_cores/kintexUltrascale/dsp_counter.xci
+++ b/sources/ip_cores/kintexUltrascale/dsp_counter.xci
@@ -204,4 +204,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_48g_ku.xci b/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_48g_ku.xci
index a840b69edf34f95cac944558c9efaa968f71d660..cca853f5b7f60068de1b2437e3ece2cfdfae091e 100644
--- a/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_48g_ku.xci
+++ b/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_48g_ku.xci
@@ -901,4 +901,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_ku.xci b/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_ku.xci
index 38f6f60e8f4539dfdf6279988cc1c4a9c4cdfb78..210893240758bf0e69fd7a83a1613147b59e5c71 100644
--- a/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_ku.xci
+++ b/sources/ip_cores/kintexUltrascale/gtwizard_fullmode_cpll_ku.xci
@@ -905,4 +905,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/gtwizard_ttc_rxcpll.xci b/sources/ip_cores/kintexUltrascale/gtwizard_ttc_rxcpll.xci
index 0e77140ecb7994fccb5e2a302ad018d9025591c3..048a41f0b80ddaf889897d5b1418be4bcef0a91d 100644
--- a/sources/ip_cores/kintexUltrascale/gtwizard_ttc_rxcpll.xci
+++ b/sources/ip_cores/kintexUltrascale/gtwizard_ttc_rxcpll.xci
@@ -919,4 +919,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7038.xci b/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7038.xci
index c375cfdcdeddc9a3dec5061182d5bd4ec92647f4..e8afa50d8c37bf1e54738f9f55829a6eb07d56a4 100644
--- a/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7038.xci
+++ b/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7038.xci
@@ -1298,4 +1298,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7039.xci b/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7039.xci
index 501619fae2922abf37933ede019ac7342230e049..4a83604b3a3625f9888cb8253c3196cc9039d425 100644
--- a/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7039.xci
+++ b/sources/ip_cores/kintexUltrascale/pcie3_ultrascale_7039.xci
@@ -1275,4 +1275,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/system_management_wiz_0.xci b/sources/ip_cores/kintexUltrascale/system_management_wiz_0.xci
index b5cddb8efb881ffcaead9c6275d7b0c4bdbce1a3..a685046bcfb50f6e4208d62ca03ada79fae080c0 100644
--- a/sources/ip_cores/kintexUltrascale/system_management_wiz_0.xci
+++ b/sources/ip_cores/kintexUltrascale/system_management_wiz_0.xci
@@ -948,4 +948,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/sources/ip_cores/kintexUltrascale/wavegen_dsp_counter.xci b/sources/ip_cores/kintexUltrascale/wavegen_dsp_counter.xci
index 5b8a9be6899dede54403c62f97408f560a320990..2f8db16f41e46ec462edf1f769beba62a323a23c 100644
--- a/sources/ip_cores/kintexUltrascale/wavegen_dsp_counter.xci
+++ b/sources/ip_cores/kintexUltrascale/wavegen_dsp_counter.xci
@@ -192,4 +192,4 @@
}
}
}
-}
+}
\ No newline at end of file