diff --git a/sources/FullModeEmulator/FMEmu_FSM_mealy.vhd b/sources/FullModeEmulator/FMEmu_FSM_mealy.vhd
index 44d4e6a63101d5e31cc36d8b4614533a52c05e0c..b28cadd2c934ae7faf3e28d22f2d163e8b33db5a 100755
--- a/sources/FullModeEmulator/FMEmu_FSM_mealy.vhd
+++ b/sources/FullModeEmulator/FMEmu_FSM_mealy.vhd
@@ -94,14 +94,14 @@ architecture fsm of FMEmu_FSM is
signal sL1A_CNT_RM : unsigned(15 downto 0) := (OTHERS => '0');
signal sBUSY_ENA_RM : std_logic := '0';
signal sL1A_CNT_RM_d : unsigned(15 downto 0) := (OTHERS => '0');
- signal sDATA_SRC_SEL_RM : std_logic_vector(0 downto 0) := (OTHERS => '0');
+ signal sCONSTANT_CHUNK_LENGTH_RM : std_logic_vector(0 downto 0) := (OTHERS => '0');
signal sL1A_Decr : std_logic := '0';
signal sL1A_Incr_r, sL1A_Incr_r1 : std_logic := '0';
signal sXoff_nXon : std_logic_vector(0 downto 0) := (OTHERS => '0');
--signal sXon_TTC_r : std_logic_vector(0 downto 0) := (OTHERS => '0');
--signal sXon_TTC_pulse : std_logic_vector(0 downto 0) := (OTHERS => '0');
- signal FFU_FM_EMU_T, FFU_FM_EMU_T_d, FFU_FM_EMU_T_pulse, FFU_FM_EMU_T_pulse_d : std_logic_vector(0 downto 0) := (OTHERS => '0');
+ signal FFU_FM_EMU_T, FFU_FM_EMU_T_d : std_logic_vector(0 downto 0) := (OTHERS => '0');
type state_type is (SETUP_EMU, PAUSE_EMU, INIT_RAM, SEND_SOP,SEND_L1ID, SEND_BCID, SEND_DATA,SEND_CRC, SEND_EOP) ;
signal fmemu_state : state_type := SETUP_EMU;
@@ -118,9 +118,9 @@ architecture fsm of FMEmu_FSM is
signal rBUSY_TH_LOW : std_logic_vector(7 downto 0) := (others => '0');
signal rBUSY_ENA : std_logic := '0';
signal rL1A_CNT : std_logic_vector(15 downto 0) := (others => '0');
- signal rDATA_SRC_SEL : std_logic_vector(0 downto 0) := (others => '0');
+ signal rCONSTANT_CHUNK_LENGTH : std_logic_vector(0 downto 0) := (others => '0');
signal rIDLE_CNT : std_logic_vector(15 downto 0) := (others => '0');
- signal rL1ID : std_logic_vector(31 downto 0) := (others => '0');
+ --signal rL1ID : std_logic_vector(31 downto 0) := (others => '0');
signal rBCID : std_logic_vector(31 downto 0) := (others => '0');
signal rWORD_CNT : std_logic_vector(15 downto 0) := (others => '0'); -- @suppress "signal rWORD_CNT is never read"
@@ -135,25 +135,11 @@ architecture fsm of FMEmu_FSM is
signal BUSY_ON_d : std_logic:='0';
signal Xoff_nXon_RM : std_logic_vector(0 downto 0) := (others => '0');
signal RST_RAM_FSM : std_logic:='0';
- signal rd_valid : std_logic;
- signal L1A_Incr_fifo : std_logic_vector(7 downto 0);
+ signal L1A_Incr_fifo : std_logic_vector(0 downto 0);
signal L1A_Incr_d : std_logic:= '0';
- signal L1A_Incr_din : std_logic_vector(7 downto 0);
- signal wr_en : std_logic := '1';
+ signal L1A_Incr_din : std_logic_vector(0 downto 0);
+ signal wr_en, rd_en, full, empty : std_logic;
- COMPONENT fifo_L1A_Incr
- PORT (
- wr_clk : IN STD_LOGIC;
- rd_clk : IN STD_LOGIC;
- din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- wr_en : IN STD_LOGIC;
- rd_en : IN STD_LOGIC;
- dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
- full : OUT STD_LOGIC;
- empty : OUT STD_LOGIC;
- valid : OUT STD_LOGIC
- );
- END COMPONENT;
begin
-- register used in FMEmu
rBCR <= register_map_control.FMEMU_CONTROL.BCR;
@@ -165,7 +151,7 @@ rINLC_CRC32 <= register_map_control.FMEMU_CONTROL.INLC_CRC32;
rBUSY_TH_HIGH <= register_map_control.FMEMU_COUNTERS.BUSY_TH_HIGH;
rBUSY_TH_LOW <= register_map_control.FMEMU_COUNTERS.BUSY_TH_LOW;
rL1A_CNT <= register_map_control.FMEMU_COUNTERS.L1A_CNT; -- 0xFFFF send data continuously
-rDATA_SRC_SEL <= register_map_control.FMEMU_CONTROL.DATA_SRC_SEL; -- default '0' --> data from emu ram
+rCONSTANT_CHUNK_LENGTH <= register_map_control.FMEMU_CONTROL.CONSTANT_CHUNK_LENGTH; -- default '0' --> data from emu ram
rIDLE_CNT <= register_map_control.FMEMU_COUNTERS.IDLE_CNT;
rBUSY_ENA <= register_map_control.FMEMU_CONTROL.FE_BUSY_ENABLE(31);
FFU_FM_EMU_T(0 downto 0) <= register_map_control.FMEMU_CONTROL.FFU_FM_EMU_T(16 downto 16);
@@ -191,11 +177,10 @@ cdc_bcid0 : xpm_cdc_gray
WIDTH => 32
)
port map (
- dest_out_bin => sBCID_240,
- dest_clk => CLK240,
src_clk => REC_CLK40,
- src_in_bin => std_logic_vector(sBCID)
-
+ src_in_bin => std_logic_vector(sBCID),
+ dest_clk => CLK240,
+ dest_out_bin => sBCID_240
);
cdc_Xoff_nXon : xpm_cdc_single
@@ -206,10 +191,10 @@ cdc_Xoff_nXon : xpm_cdc_single
SRC_INPUT_REG => 1
)
port map (
- dest_out => Xoff_nXon_240,
- dest_clk => CLK240,
src_clk => REC_CLK40,
- src_in => Xoff_nXon(0)
+ src_in => Xoff_nXon(0),
+ dest_clk => CLK240,
+ dest_out => Xoff_nXon_240
);
@@ -227,30 +212,57 @@ RST_RAM <= RST or RST_RAM_FSM;
rg_enb => rg_enb,
rg_doutb => rg_doutb);
-
---ila_fsm_comp: entity work.ila_fsm
--- PORT map(
--- clk => CLK240,
--- probe0 => (others => vL1A_CntUP),
--- probe1 => (others => vL1A_CntDN),
--- probe2 => (others => L1A_Incr)
----- probe3 => sL1A_CNT
--- );
-
- fifo_inst0: fifo_L1A_Incr
- PORT MAP(
--- rd_rst => RST,
--- wr_rst => RST,
- wr_clk => REC_CLK40,
- rd_clk => CLK240,
- din => L1A_Incr_din,
- wr_en => wr_en,
- rd_en => rd_valid,
- dout => L1A_Incr_fifo,
- full => open,
- empty => open,
- valid => rd_valid
- );
+xpm_fifo_async_inst : xpm_fifo_async
+ generic map (
+ CDC_SYNC_STAGES => 2, -- DECIMAL
+ DOUT_RESET_VALUE => "0", -- String
+ ECC_MODE => "no_ecc", -- String
+ FIFO_MEMORY_TYPE => "auto", -- String
+ FIFO_READ_LATENCY => 1, -- DECIMAL
+ FIFO_WRITE_DEPTH => 16, -- DECIMAL
+ FULL_RESET_VALUE => 0, -- DECIMAL
+ PROG_EMPTY_THRESH => 8, -- DECIMAL
+ PROG_FULL_THRESH => 8, -- DECIMAL
+ RD_DATA_COUNT_WIDTH => 4, -- DECIMAL
+ READ_DATA_WIDTH => 1, -- DECIMAL
+ READ_MODE => "fwft", -- String
+ RELATED_CLOCKS => 0, -- DECIMAL
+ SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+ USE_ADV_FEATURES => "0000", -- String
+ WAKEUP_TIME => 0, -- DECIMAL
+ WRITE_DATA_WIDTH => 1, -- DECIMAL
+ WR_DATA_COUNT_WIDTH => 4 -- DECIMAL
+ )
+ port map (
+ sleep => '0',
+ rst => RST,
+ wr_clk => REC_CLK40,
+ wr_en => wr_en,
+ din => L1A_Incr_din,
+ full => full,
+ prog_full => open,
+ wr_data_count => open,
+ overflow => open,
+ wr_rst_busy => open,
+ almost_full => open,
+ wr_ack => open,
+ rd_clk => CLK240,
+ rd_en => rd_en,
+ dout => L1A_Incr_fifo,
+ empty => empty,
+ prog_empty => open,
+ rd_data_count => open,
+ underflow => open,
+ rd_rst_busy => open,
+ almost_empty => open,
+ data_valid => open,
+ injectsbiterr => '0',
+ injectdbiterr => '0',
+ sbiterr => open,
+ dbiterr => open
+ );
+ wr_en <= not full;
+ rd_en <= not empty;
L1A_Incr_d <= L1A_Incr_fifo(0);
L1A_Incr_din <= (others => L1A_Incr);
@@ -340,8 +352,6 @@ sL1A_CNT_debug <= std_logic_vector(sL1A_CNT);
BUSY_ON_t <= sBUSY_ENA_RM;
elsif (sL1A_CNT <= sBUSY_TH_LOW_RM) then
BUSY_ON_t <= '0';
- else
- BUSY_ON_t <= BUSY_ON_t;
end if;
else
BUSY_ON_t <= '0';
@@ -440,7 +450,7 @@ begin
sBUSY_TH_HIGH_RM <= x"FF" & unsigned(rBUSY_TH_HIGH);
sBUSY_TH_LOW_RM <= x"00" & unsigned(rBUSY_TH_LOW);
sTTC_MODE_RM <= rTTC_MODE; -- default '0' --> regmap mode
- sDATA_SRC_SEL_RM <= rDATA_SRC_SEL; -- default '0' --> data from emu ram
+ sCONSTANT_CHUNK_LENGTH_RM <= rCONSTANT_CHUNK_LENGTH; -- default '0' --> data from emu ram
sL1A_CNT_RM <= unsigned(rL1A_CNT); -- 0xFFFF send data continuously
Xoff_nXon_RM(0) <= Xoff_nXon_240;
CRC_EN <= rINLC_CRC32(0);
@@ -453,12 +463,12 @@ process (CLK240)
begin
if (rising_edge(CLK240)) then
FFU_FM_EMU_T_d <= FFU_FM_EMU_T;
- FFU_FM_EMU_T_pulse_d <= FFU_FM_EMU_T_pulse;
- if(FFU_FM_EMU_T_d = "0" and FFU_FM_EMU_T="1") then
- FFU_FM_EMU_T_pulse <= "1";
- elsif(fmemu_state = SEND_EOP ) then
- FFU_FM_EMU_T_pulse <= "0";
- end if;
+ --FFU_FM_EMU_T_pulse_d <= FFU_FM_EMU_T_pulse;
+ --if(FFU_FM_EMU_T_d = "0" and FFU_FM_EMU_T="1") then
+ --FFU_FM_EMU_T_pulse <= "1";
+ --elsif(fmemu_state = SEND_EOP ) then
+ --FFU_FM_EMU_T_pulse <= "0";
+ --end if;
end if;
end process;
@@ -481,10 +491,10 @@ begin
L1ID_cnten <= '0';
RST_RAM_FSM <= '0';
else
- if(BUSY_ON_d = '0' and BUSY_ON_t = '1') then
- EMUout_dtype <="100"; -- default send idle
- elsif(BUSY_ON_d = '1' and BUSY_ON_t = '0') then
- EMUout_dtype <="101"; -- default send idle
+ if(BUSY_ON_d = '0' and BUSY_ON_t = '1' and sBUSY_ENA_RM = '1') then
+ EMUout_dtype <="100"; -- Busy on (SOB)
+ elsif(BUSY_ON_d = '1' and BUSY_ON_t = '0' and sBUSY_ENA_RM = '1') then
+ EMUout_dtype <="101"; -- Busy off (EOB)
elsif(sXoff_nXon = "0") then
EMUout_dtype <="011"; -- default send idle
EMUout <= x"FFFF0000";
@@ -563,7 +573,7 @@ begin
DataToCRC <= std_logic_vector(sL1ID_low(7 downto 0) & sL1ID_low(15 downto 8) & sL1ID_low(23 downto 16) & sL1ID_high);
CALC_CRC <= '1';
L1ID_cnten <= '1';
- if(sDATA_SRC_SEL_RM = "0") then
+ if(sCONSTANT_CHUNK_LENGTH_RM = "0") then
sWORD_CNT <= unsigned(rg_doutb); --(rWORD_CNT);
else
sWORD_CNT <= unsigned(rWORD_CNT);
diff --git a/sources/FullModeEmulator/FMEmu_top_bnl711.vhd b/sources/FullModeEmulator/FMEmu_top_bnl711.vhd
index 7e17065fc87966927dc68fa5fc7516496041907a..7ffdd7a59a026c57ea5968ea1af1ed9191c1fd33 100755
--- a/sources/FullModeEmulator/FMEmu_top_bnl711.vhd
+++ b/sources/FullModeEmulator/FMEmu_top_bnl711.vhd
@@ -627,21 +627,31 @@ register_map_generators.FMEMU_EVENT_INFO.L1ID <= FMEMU_EVENT_INFO_L1ID(0);
register_map_generators.FMEMU_EVENT_INFO.BCID <= FMEMU_EVENT_INFO_BCID(0);
FSM_COMP: for i in 0 to GBT_NUM-1 generate
+ signal XoffElink : std_logic_vector(1 downto 0);
+ signal XoffIndex : integer range 0 to 118;
+ signal TTCin : std_logic_vector(2 downto 0); --TTC option 1, 2 or 3 for L1A, BCR and ECR
+ signal TTCIndex : integer range 0 to 118;
+begin
+ process(RXOUTCLK_40)
begin
-
+ if rising_edge(RXOUTCLK_40) then
+ XoffIndex <= to_integer(unsigned(pcie0_register_map_control_appreg_clk.FMEMU_CONTROL.XONXOFF_BITNR(55 downto 49)&'0'));
+ TTCIndex <= to_integer(unsigned(pcie0_register_map_control_appreg_clk.FMEMU_CONTROL.L1A_BITNR(63 downto 58)&'0'&'0'));
+ end if;
+
+ end process;
+
+ XoffElink <= RX_120b(i)(1+XoffIndex downto XoffIndex);
+ TTCin <= RX_120b(i)(2+TTCIndex downto TTCIndex);
Xoff_decoder_top_inst: entity work.Xoff_decoder_top
generic map (
- do_generate => true,
- DinWidth => 2, --maximum width of the elink
- includeDirectMode => true
+ DinWidth => 2 --maximum width of the elink
)
Port map(
- DIN => RX_120b(i)(33 downto 32),
+ DIN => XoffElink,--RX_120b(i)(33 downto 32),
Clk => RXOUTCLK_40,
Reset => reset,
- InputWidth => 2,
- MODE8b => '0',
DATA_OUT => open, --DATA_OUT_DEC,
DATA_RDY => open, --DATA_RDY_DEC,
Xoff_nXon => Xoff_nXon(i)
@@ -656,9 +666,9 @@ Xoff_decoder_top_inst: entity work.Xoff_decoder_top
FMEMU_EVENT_INFO_BCID => FMEMU_EVENT_INFO_BCID(i), --pcie0_register_map_monitor,
Xoff_nXon(0) => Xoff_nXon(i), --"0", -- : in std_logic_vector(0 downto 0);
--Xoff_nXon_en => pcie0_register_map_40_control.XOFF_ENABLE(i downto i),
- L1A_Incr => RX_120b(i)(64), -- : in std_logic; -- signal coming from ttc decoders
- BCR_in => '0', --RX_120b(0)(65), -- : in std_logic; -- signal coming from ttc decoders
- ECR_in => '0', --RX_120b(0)(66), -- : in std_logic; -- signal coming from ttc decoders
+ L1A_Incr => TTCin(0),--RX_120b(i)(64), -- : in std_logic; -- signal coming from ttc decoders
+ BCR_in => TTCin(1),--'0', --RX_120b(0)(65), -- : in std_logic; -- signal coming from ttc decoders
+ ECR_in => TTCin(2), --RX_120b(0)(66), -- : in std_logic; -- signal coming from ttc decoders
RST => reset, -- : in std_logic;
CRC => CRC(i), -- : in std_logic_vector(31 downto 0);
RST_RAM => RST_RAM(i),
diff --git a/sources/FullModeTransmitter/FMchannelTXctrl_emu.vhd b/sources/FullModeTransmitter/FMchannelTXctrl_emu.vhd
index 62088771b19010bd962cd36ba2b5c264d751b463..b0e2936ea0a4a589efdca70488ce21e35efa2c69 100644
--- a/sources/FullModeTransmitter/FMchannelTXctrl_emu.vhd
+++ b/sources/FullModeTransmitter/FMchannelTXctrl_emu.vhd
@@ -7,10 +7,10 @@
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
-library work, ieee;
+library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
-use ieee.std_logic_unsigned.all;
+use ieee.std_logic_unsigned.all; -- @suppress "Deprecated package"
--use work.centralRouter_package.all;
--! Full Mode channel transmitter controller
@@ -46,25 +46,25 @@ signal crc_din, crc_din_r1: std_logic_vector(31 downto 0);
signal crc_kin, crc_kin_r1 : std_logic_vector(3 downto 0);
signal crc_out : std_logic_vector(19 downto 0);
signal tx_state : integer :=0;
-signal fifo_dout_r1 : std_logic_vector(31 downto 0);
+--signal fifo_dout_r1 : std_logic_vector(31 downto 0);
-signal fifo_dtype_r1 : std_logic_vector(2 downto 0);
+--signal fifo_dtype_r1 : std_logic_vector(2 downto 0);
-signal err_detect_r1 : std_logic;
-signal eop_detect_r1 : std_logic;
-signal eop_detect_r2 : std_logic;
+--signal err_detect_r1 : std_logic;
+--signal eop_detect_r1 : std_logic;
+--signal eop_detect_r2 : std_logic;
-signal sop_detect_r1 : std_logic;
-signal sop_detect_r2 : std_logic;
+--signal sop_detect_r1 : std_logic;
+--signal sop_detect_r2 : std_logic;
-signal sob_detect_r1 : std_logic;
-signal eob_detect_r1 : std_logic;
-signal sob_detect_r2 : std_logic;
-signal eob_detect_r2 : std_logic;
+--signal sob_detect_r1 : std_logic;
+--signal eob_detect_r1 : std_logic;
+--signal sob_detect_r2 : std_logic;
+--signal eob_detect_r2 : std_logic;
-signal dout_r1 : std_logic_vector(31 downto 0);
-signal kout_r1 : std_logic_vector(3 downto 0);
+--signal dout_r1 : std_logic_vector(31 downto 0);
+--signal kout_r1 : std_logic_vector(3 downto 0);
begin
@@ -81,34 +81,34 @@ eob_detect <= '1' when (fifo_dtype = "101") else '0'; -- end-of-busy
-- reading from user's fifo
---------------------------------------------------------------------------------------
-tx_state_output: process(clk240, rst)
-begin
- if (rst = '1') then
- fifo_dout_r1 <= (others => '0');
- fifo_dtype_r1 <= (others => '0');
- err_detect_r1 <= '0';
- eop_detect_r1 <= '0';
- sop_detect_r1 <= '0';
- eop_detect_r2 <= '0';
- sop_detect_r2 <= '0';
- sob_detect_r1 <= '0';
- eob_detect_r1 <= '0';
- sob_detect_r2 <= '0';
- eob_detect_r2 <= '0';
- elsif rising_edge(clk240) then
- fifo_dout_r1 <= fifo_dout;
- fifo_dtype_r1 <= fifo_dtype;
- err_detect_r1 <= err_detect;
- eop_detect_r1 <= eop_detect;
- sop_detect_r1 <= sop_detect;
- eop_detect_r2 <= eop_detect_r1;
- sop_detect_r2 <= sop_detect_r1;
- sob_detect_r1 <= sob_detect;
- eob_detect_r1 <= eob_detect;
- sob_detect_r2 <= sob_detect_r1;
- eob_detect_r2 <= eob_detect_r1;
- end if;
-end process;
+--tx_state_output: process(clk240, rst)
+--begin
+ --if (rst = '1') then
+ --fifo_dout_r1 <= (others => '0');
+ --fifo_dtype_r1 <= (others => '0');
+ --err_detect_r1 <= '0';
+ --eop_detect_r1 <= '0';
+ --sop_detect_r1 <= '0';
+ --eop_detect_r2 <= '0';
+ --sop_detect_r2 <= '0';
+ --sob_detect_r1 <= '0';
+ --eob_detect_r1 <= '0';
+ --sob_detect_r2 <= '0';
+ --eob_detect_r2 <= '0';
+ --elsif rising_edge(clk240) then
+ --fifo_dout_r1 <= fifo_dout;
+ --fifo_dtype_r1 <= fifo_dtype;
+ --err_detect_r1 <= err_detect;
+ --eop_detect_r1 <= eop_detect;
+ --sop_detect_r1 <= sop_detect;
+ --eop_detect_r2 <= eop_detect_r1;
+ --sop_detect_r2 <= sop_detect_r1;
+ --sob_detect_r1 <= sob_detect;
+ --eob_detect_r1 <= eob_detect;
+ --sob_detect_r2 <= sob_detect_r1;
+ --eob_detect_r2 <= eob_detect_r1;
+ --end if;
+--end process;
tx_detect_output: process(clk240, rst)
begin
diff --git a/sources/Xoff_decoder/8b10_dec_wrap.vhd b/sources/Xoff_decoder/8b10_dec_wrap.vhd
index aba87e0f7c507a34480302dbe0eb7e75eb30c9d8..0ec3bd0285797a6aaa3f63646d5e716aaf3e72e7 100644
--- a/sources/Xoff_decoder/8b10_dec_wrap.vhd
+++ b/sources/Xoff_decoder/8b10_dec_wrap.vhd
@@ -104,7 +104,7 @@ GBT_mode: if (GENERATE_FEI4B = false) generate
---
end generate GBT_mode;
-FEI4B: if (GENERATE_FEI4B = true) generate
+FEI4B: if (GENERATE_FEI4B) generate
ISK_comma <= '1' when (ABCDEIFGHJ_IN = FEI4B_COMMAp or ABCDEIFGHJ_IN = FEI4B_COMMAn) else '0';
ISK_soc <= '1' when (ABCDEIFGHJ_IN = FEI4B_SOCp or ABCDEIFGHJ_IN = FEI4B_SOCn) else '0';
ISK_eoc <= '1' when (ABCDEIFGHJ_IN = FEI4B_EOCp or ABCDEIFGHJ_IN = FEI4B_EOCn) else '0';
diff --git a/sources/Xoff_decoder/Xoff_decoder_top.vhd b/sources/Xoff_decoder/Xoff_decoder_top.vhd
index 32ceddf4304a0006e7ac941f785142491a817728..09fc170cad96788bdd6d36405693633245d1c089 100644
--- a/sources/Xoff_decoder/Xoff_decoder_top.vhd
+++ b/sources/Xoff_decoder/Xoff_decoder_top.vhd
@@ -26,16 +26,14 @@ use IEEE.NUMERIC_STD.ALL;
entity Xoff_decoder_top is
generic (
- do_generate : boolean := true;
- DinWidth : integer range 0 to 16 := 16; --maximum width of the elink
- includeDirectMode : boolean := true
+ DinWidth : integer range 0 to 16 := 16 --maximum width of the elink
);
Port (
DIN : in std_logic_vector(DinWidth-1 downto 0);
Clk : in std_logic;
Reset: in std_logic;
- InputWidth: in integer range 0 to 16;
- MODE8b : in std_logic; --for direct mode set to '1', for 8b10b mode set to '0'
+ --InputWidth: in integer range 0 to 16;
+ --MODE8b : in std_logic; --for direct mode set to '1', for 8b10b mode set to '0'
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
Xoff_nXon : out std_logic
@@ -57,22 +55,22 @@ DIN_s <= DIN(1 downto 0);
InputShifterNb_inst : entity work.InputShifterNb
port map (
- Clk => Clk,
- Reset => Reset,
- DIN => DIN_s,
- DOUT => DOUT,
- DValid => DValid
+ DIN => DIN_s,
+ DOUT => DOUT,
+ DValid => DValid,
+ Clk => Clk,
+ Reset => Reset
);
-process(clk)
+process(Clk)
begin
- if rising_edge(clk) then
+ if rising_edge(Clk) then
DATA_RDY <= DValid;
end if;
end process;
-process(clk, Reset)
+process(Clk)
begin
- if rising_edge(clk) then
+ if rising_edge(Clk) then
if(Reset = '1') then
Xoff_nXon <= '0';
count <= (others => '0');
@@ -88,6 +86,9 @@ begin
end process;
dec_8b10: entity work.dec_8b10_wrap
+ generic map(
+ GENERATE_FEI4B => false
+ )
port map(
RESET => Reset,
RBYTECLK => Clk,
@@ -97,8 +98,4 @@ end process;
BUSY => Xoff_nXon_t
);
-
-
-
-
end Behavioral;
diff --git a/sources/felixUserSupport/fullmodetransceiver_gth_gth/FM_transceiver_BNL711_GBTin_FMout.vhd b/sources/felixUserSupport/fullmodetransceiver_gth_gth/FM_transceiver_BNL711_GBTin_FMout.vhd
index ebbf4abf0eea75b846edac2981c979b0b6e3cb4c..161b2b29fe8b348f9ed89cf4f6c904fbfbccae49 100644
--- a/sources/felixUserSupport/fullmodetransceiver_gth_gth/FM_transceiver_BNL711_GBTin_FMout.vhd
+++ b/sources/felixUserSupport/fullmodetransceiver_gth_gth/FM_transceiver_BNL711_GBTin_FMout.vhd
@@ -318,7 +318,7 @@ architecture RTL of FullModeTransceiver is
--signal TX_N_i : std_logic_vector(47 downto 0):=x"000000000000";
--signal TX_P_i : std_logic_vector(47 downto 0):=x"000000000000";
- signal drpclk : std_logic_vector(0 downto 0);
+ --signal drpclk : std_logic_vector(0 downto 0);
--signal userclk_tx_active_out : std_logic_vector(GBT_NUM-1 downto 0);
--signal userclk_rx_active_out : std_logic_vector(GBT_NUM-1 downto 0);
signal userclk_rx_active_out_p: std_logic_vector(GBT_NUM-1 downto 0);
@@ -660,7 +660,7 @@ begin
end generate;
- drpclk(0) <= drpclk_in;
+ --drpclk(0) <= drpclk_in;
process(drpclk_in)
begin
diff --git a/sources/shared/xadc_drp.vhd b/sources/shared/xadc_drp.vhd
index fc8ce2ee65e1752c8a7906edddefee1d83369e75..33be835fcdecf6a9f5482175f57e013485d8db42 100644
--- a/sources/shared/xadc_drp.vhd
+++ b/sources/shared/xadc_drp.vhd
@@ -177,4 +177,4 @@ vccint <= vccint_s;
vccaux <= vccaux_s;
vccbram <= vccbram_s;
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/sources/templates/dma_control.vhd b/sources/templates/dma_control.vhd
index 436c0a82aa6894d8f56b7bf8aa3acdb04139d7ac..b72bd5f6a78c48fb2ebd75299ffef56cb732c182 100644
--- a/sources/templates/dma_control.vhd
+++ b/sources/templates/dma_control.vhd
@@ -9213,9 +9213,9 @@ end process;
register_map_control_s.FMEMU_CONTROL.ECR <= REG_FMEMU_CONTROL_ECR_C; -- Reset L1ID to 0
end if;
if EMU_GENERATE_REGS then
- register_map_control_s.FMEMU_CONTROL.DATA_SRC_SEL <= REG_FMEMU_CONTROL_DATA_SRC_SEL_C; -- Data source select
- -- 0: Data input comes from EMURAM
- -- 1: Data input comes from PCIe
+ register_map_control_s.FMEMU_CONTROL.CONSTANT_CHUNK_LENGTH <= REG_FMEMU_CONTROL_CONSTANT_CHUNK_LENGTH_C; -- Data source select
+ -- 0: Random chunk length
+ -- 1: Constant chunk length
end if;
if EMU_GENERATE_REGS then
@@ -11452,22 +11452,22 @@ end process;
if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then
register_map_control_s.R3L1_CTRL (3)(3).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_03_R3L1_3_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_CTRL.OPTIONS <= REG_MROD_CTRL_OPTIONS_C; -- Extra options for MROD
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_CTRL.ENASPARE1 <= REG_MROD_CTRL_ENASPARE1_C; -- Enable spare1
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_CTRL.ENAMANSLIDE <= REG_MROD_CTRL_ENAMANSLIDE_C; -- Enable Manual Slide in Rx Locking
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_CTRL.ENAPASSALL <= REG_MROD_CTRL_ENAPASSALL_C; -- Enable PassAll in EmptySuppress
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_CTRL.ENATXCOUNT <= REG_MROD_CTRL_ENATXCOUNT_C; -- Enable SimpleCount in TxDriver for locking
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_CTRL.GOLTESTMODE <= REG_MROD_CTRL_GOLTESTMODE_C; -- GOL Test Mode (emulate CSM):
-- 0: Run Data Emulator when 1; 0: stop, load emulator fifo
-- 1: Enable Circulate when 1; 0: send fifo data only once
@@ -11475,67 +11475,67 @@ end process;
-- 3: Enable pattern generator
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_TCVRCTRL.SLIDEMAX <= REG_MROD_TCVRCTRL_SLIDEMAX_C; -- Maximum RXSLIDES before fire a TCVR reset
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_TCVRCTRL.SLIDEWAIT <= REG_MROD_TCVRCTRL_SLIDEWAIT_C; -- RXclk delay in TCVR for next RX_SLIDE operation
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_TCVRCTRL.FRAMESIZE <= REG_MROD_TCVRCTRL_FRAMESIZE_C; -- Number of 32 data words in 1 frame
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_CSMENABLE <= REG_MROD_EP0_CSMENABLE_C; -- EP0 CSM Data Enable channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_EMPTYSUPPR <= REG_MROD_EP0_EMPTYSUPPR_C; -- EP0 Set Empty Suppression channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_HPTDCMODE <= REG_MROD_EP0_HPTDCMODE_C; -- EP0 Set HPTDC Mode channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_CLRFIFOS <= REG_MROD_EP0_CLRFIFOS_C; -- EP0 Clear FIFOs channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_EMULOADENA <= REG_MROD_EP0_EMULOADENA_C; -- EP0 Emulator Load Enable channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_TRXLOOPBACK <= REG_MROD_EP0_TRXLOOPBACK_C; -- EP0 Transceiver Loopback Enable channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_TXCVRRESET <= REG_MROD_EP0_TXCVRRESET_C; -- EP0 Transceiver Reset all channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_RXRESET <= REG_MROD_EP0_RXRESET_C; -- EP0 Receiver Reset channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_TXRESET <= REG_MROD_EP0_TXRESET_C; -- EP0 Transmitter Reset channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_CSMENABLE <= REG_MROD_EP1_CSMENABLE_C; -- EP1 CSM Data Enable channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_EMPTYSUPPR <= REG_MROD_EP1_EMPTYSUPPR_C; -- EP1 Set Empty Suppression channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_HPTDCMODE <= REG_MROD_EP1_HPTDCMODE_C; -- EP1 Set HPTDC Mode channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_CLRFIFOS <= REG_MROD_EP1_CLRFIFOS_C; -- EP1 Clear FIFOs channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_EMULOADENA <= REG_MROD_EP1_EMULOADENA_C; -- EP1 Emulator Load Enable channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_TRXLOOPBACK <= REG_MROD_EP1_TRXLOOPBACK_C; -- EP1 Transceiver Loopback Enable channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_TXCVRRESET <= REG_MROD_EP1_TXCVRRESET_C; -- EP1 Transceiver Reset all channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_RXRESET <= REG_MROD_EP1_RXRESET_C; -- EP1 Receiver Reset channel 23-0
end if;
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_TXRESET <= REG_MROD_EP1_TXRESET_C; -- EP1 Transmitter Reset channel 23-0
end if;
-----------------------------------
@@ -17263,9 +17263,9 @@ end process;
register_read_data_25_s(43 downto 43) <= register_map_control_s.FMEMU_CONTROL.BCR; -- Reset BCID to 0
register_read_data_25_s(42 downto 42) <= register_map_control_s.FMEMU_CONTROL.ECR; -- Reset L1ID to 0
- register_read_data_25_s(41 downto 41) <= register_map_control_s.FMEMU_CONTROL.DATA_SRC_SEL; -- Data source select
- -- 0: Data input comes from EMURAM
- -- 1: Data input comes from PCIe
+ register_read_data_25_s(41 downto 41) <= register_map_control_s.FMEMU_CONTROL.CONSTANT_CHUNK_LENGTH; -- Data source select
+ -- 0: Random chunk length
+ -- 1: Constant chunk length
register_read_data_25_s(40 downto 32) <= register_map_monitor_s.register_map_generators.FMEMU_CONTROL.INT_STATUS_EMU; -- Read internal status emulator
register_read_data_25_s(31 downto 31) <= register_map_control_s.FMEMU_CONTROL.FE_BUSY_ENABLE; -- Enable the BUSY mechanism if L1A counter passes threshold
@@ -18946,7 +18946,7 @@ end process;
when REG_STRIPS_L1_TRIGGER => register_read_data_25_s(64 downto 64) <= register_map_control_s.STRIPS_L1_TRIGGER; -- (for tests only) simulate L1 trigger (issues 4-5 sequential triggers)
when REG_STRIPS_R3L1_TRIGGER => register_read_data_25_s(64 downto 64) <= register_map_control_s.STRIPS_R3L1_TRIGGER; -- (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)
when REG_MROD_CTRL =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(15 downto 8) <= register_map_control_s.MROD_CTRL.OPTIONS; -- Extra options for MROD
register_read_data_25_s(7 downto 7) <= register_map_control_s.MROD_CTRL.ENASPARE1; -- Enable spare1
register_read_data_25_s(6 downto 6) <= register_map_control_s.MROD_CTRL.ENAMANSLIDE; -- Enable Manual Slide in Rx Locking
@@ -18960,81 +18960,81 @@ end process;
end if;
when REG_MROD_TCVRCTRL =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 16) <= register_map_control_s.MROD_TCVRCTRL.SLIDEMAX; -- Maximum RXSLIDES before fire a TCVR reset
register_read_data_25_s(15 downto 8) <= register_map_control_s.MROD_TCVRCTRL.SLIDEWAIT; -- RXclk delay in TCVR for next RX_SLIDE operation
register_read_data_25_s(7 downto 0) <= register_map_control_s.MROD_TCVRCTRL.FRAMESIZE; -- Number of 32 data words in 1 frame
end if;
when REG_MROD_EP0_CSMENABLE =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_CSMENABLE; -- EP0 CSM Data Enable channel 23-0
end if;
when REG_MROD_EP0_EMPTYSUPPR =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_EMPTYSUPPR; -- EP0 Set Empty Suppression channel 23-0
end if;
when REG_MROD_EP0_HPTDCMODE =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_HPTDCMODE; -- EP0 Set HPTDC Mode channel 23-0
end if;
when REG_MROD_EP0_CLRFIFOS =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_CLRFIFOS; -- EP0 Clear FIFOs channel 23-0
end if;
when REG_MROD_EP0_EMULOADENA =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_EMULOADENA; -- EP0 Emulator Load Enable channel 23-0
end if;
when REG_MROD_EP0_TRXLOOPBACK =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_TRXLOOPBACK; -- EP0 Transceiver Loopback Enable channel 23-0
end if;
when REG_MROD_EP0_TXCVRRESET =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_TXCVRRESET; -- EP0 Transceiver Reset all channel 23-0
end if;
when REG_MROD_EP0_RXRESET =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_RXRESET; -- EP0 Receiver Reset channel 23-0
end if;
when REG_MROD_EP0_TXRESET =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_TXRESET; -- EP0 Transmitter Reset channel 23-0
end if;
when REG_MROD_EP1_CSMENABLE =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_CSMENABLE; -- EP1 CSM Data Enable channel 23-0
end if;
when REG_MROD_EP1_EMPTYSUPPR =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_EMPTYSUPPR; -- EP1 Set Empty Suppression channel 23-0
end if;
when REG_MROD_EP1_HPTDCMODE =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_HPTDCMODE; -- EP1 Set HPTDC Mode channel 23-0
end if;
when REG_MROD_EP1_CLRFIFOS =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_CLRFIFOS; -- EP1 Clear FIFOs channel 23-0
end if;
when REG_MROD_EP1_EMULOADENA =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_EMULOADENA; -- EP1 Emulator Load Enable channel 23-0
end if;
when REG_MROD_EP1_TRXLOOPBACK =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_TRXLOOPBACK; -- EP1 Transceiver Loopback Enable channel 23-0
end if;
when REG_MROD_EP1_TXCVRRESET =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_TXCVRRESET; -- EP1 Transceiver Reset all channel 23-0
end if;
when REG_MROD_EP1_RXRESET =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_RXRESET; -- EP1 Receiver Reset channel 23-0
end if;
when REG_MROD_EP1_TXRESET =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_TXRESET; -- EP1 Transmitter Reset channel 23-0
end if;
@@ -20779,51 +20779,51 @@ end process;
-- MRODmonitors
when REG_MROD_EP0_CSMH_EMPTY =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_CSMH_EMPTY; -- EP0 CSM Handler FIFO Empty 23-0
end if;
when REG_MROD_EP0_CSMH_FULL =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_CSMH_FULL; -- EP0 CSM Handler FIFO Full 23-0
end if;
when REG_MROD_EP0_RXALIGNBSY =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_RXALIGNBSY; -- EP0 Receiver Aligned monitor 23-0
end if;
when REG_MROD_EP0_RXRECDATA =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_RXRECDATA; -- EP0 Receiver Data monitor 23-0
end if;
when REG_MROD_EP0_RXRECIDLES =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_RXRECIDLES; -- EP0 Receiver Idle monitor 23-0
end if;
when REG_MROD_EP0_TXLOCKED =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_TXLOCKED; -- EP0 Transmitter Locked monitor 23-0
end if;
when REG_MROD_EP1_CSMH_EMPTY =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_CSMH_EMPTY; -- EP1 CSM Handler FIFO Empty 23-0
end if;
when REG_MROD_EP1_CSMH_FULL =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_CSMH_FULL; -- EP1 CSM Handler FIFO Full 23-0
end if;
when REG_MROD_EP1_RXALIGNBSY =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_RXALIGNBSY; -- EP1 Receiver Aligned monitor 23-0
end if;
when REG_MROD_EP1_RXRECDATA =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_RXRECDATA; -- EP1 Receiver Data monitor 23-0
end if;
when REG_MROD_EP1_RXRECIDLES =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_RXRECIDLES; -- EP1 Receiver Idle monitor 23-0
end if;
when REG_MROD_EP1_TXLOCKED =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_TXLOCKED; -- EP1 Transmitter Locked monitor 23-0
end if;
-----------------------------------
@@ -26362,9 +26362,9 @@ end process;
register_map_control_s.FMEMU_CONTROL.BCR <= register_write_data_25_v(43 downto 43); -- Reset BCID to 0
register_map_control_s.FMEMU_CONTROL.ECR <= register_write_data_25_v(42 downto 42); -- Reset L1ID to 0
- register_map_control_s.FMEMU_CONTROL.DATA_SRC_SEL <= register_write_data_25_v(41 downto 41); -- Data source select
- -- 0: Data input comes from EMURAM
- -- 1: Data input comes from PCIe
+ register_map_control_s.FMEMU_CONTROL.CONSTANT_CHUNK_LENGTH <= register_write_data_25_v(41 downto 41); -- Data source select
+ -- 0: Random chunk length
+ -- 1: Constant chunk length
register_map_control_s.FMEMU_CONTROL.FE_BUSY_ENABLE <= register_write_data_25_v(31 downto 31); -- Enable the BUSY mechanism if L1A counter passes threshold
register_map_control_s.FMEMU_CONTROL.FFU_FM_EMU_T <= register_write_data_25_v(30 downto 16); -- For Future Use (trigger registers)
@@ -28041,7 +28041,7 @@ end process;
when REG_STRIPS_L1_TRIGGER => register_map_control_s.STRIPS_L1_TRIGGER <= "1"; -- (for tests only) simulate L1 trigger (issues 4-5 sequential triggers)
when REG_STRIPS_R3L1_TRIGGER => register_map_control_s.STRIPS_R3L1_TRIGGER <= "1"; -- (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)
when REG_MROD_CTRL =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_CTRL.OPTIONS <= register_write_data_25_v(15 downto 8); -- Extra options for MROD
register_map_control_s.MROD_CTRL.ENASPARE1 <= register_write_data_25_v(7 downto 7); -- Enable spare1
register_map_control_s.MROD_CTRL.ENAMANSLIDE <= register_write_data_25_v(6 downto 6); -- Enable Manual Slide in Rx Locking
@@ -28055,81 +28055,81 @@ end process;
end if;
when REG_MROD_TCVRCTRL =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_TCVRCTRL.SLIDEMAX <= register_write_data_25_v(23 downto 16); -- Maximum RXSLIDES before fire a TCVR reset
register_map_control_s.MROD_TCVRCTRL.SLIDEWAIT <= register_write_data_25_v(15 downto 8); -- RXclk delay in TCVR for next RX_SLIDE operation
register_map_control_s.MROD_TCVRCTRL.FRAMESIZE <= register_write_data_25_v(7 downto 0); -- Number of 32 data words in 1 frame
end if;
when REG_MROD_EP0_CSMENABLE =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_CSMENABLE <= register_write_data_25_v(23 downto 0); -- EP0 CSM Data Enable channel 23-0
end if;
when REG_MROD_EP0_EMPTYSUPPR =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_EMPTYSUPPR <= register_write_data_25_v(23 downto 0); -- EP0 Set Empty Suppression channel 23-0
end if;
when REG_MROD_EP0_HPTDCMODE =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_HPTDCMODE <= register_write_data_25_v(23 downto 0); -- EP0 Set HPTDC Mode channel 23-0
end if;
when REG_MROD_EP0_CLRFIFOS =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_CLRFIFOS <= register_write_data_25_v(23 downto 0); -- EP0 Clear FIFOs channel 23-0
end if;
when REG_MROD_EP0_EMULOADENA =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_EMULOADENA <= register_write_data_25_v(23 downto 0); -- EP0 Emulator Load Enable channel 23-0
end if;
when REG_MROD_EP0_TRXLOOPBACK =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_TRXLOOPBACK <= register_write_data_25_v(23 downto 0); -- EP0 Transceiver Loopback Enable channel 23-0
end if;
when REG_MROD_EP0_TXCVRRESET =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_TXCVRRESET <= register_write_data_25_v(23 downto 0); -- EP0 Transceiver Reset all channel 23-0
end if;
when REG_MROD_EP0_RXRESET =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_RXRESET <= register_write_data_25_v(23 downto 0); -- EP0 Receiver Reset channel 23-0
end if;
when REG_MROD_EP0_TXRESET =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP0_TXRESET <= register_write_data_25_v(23 downto 0); -- EP0 Transmitter Reset channel 23-0
end if;
when REG_MROD_EP1_CSMENABLE =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_CSMENABLE <= register_write_data_25_v(23 downto 0); -- EP1 CSM Data Enable channel 23-0
end if;
when REG_MROD_EP1_EMPTYSUPPR =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_EMPTYSUPPR <= register_write_data_25_v(23 downto 0); -- EP1 Set Empty Suppression channel 23-0
end if;
when REG_MROD_EP1_HPTDCMODE =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_HPTDCMODE <= register_write_data_25_v(23 downto 0); -- EP1 Set HPTDC Mode channel 23-0
end if;
when REG_MROD_EP1_CLRFIFOS =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_CLRFIFOS <= register_write_data_25_v(23 downto 0); -- EP1 Clear FIFOs channel 23-0
end if;
when REG_MROD_EP1_EMULOADENA =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_EMULOADENA <= register_write_data_25_v(23 downto 0); -- EP1 Emulator Load Enable channel 23-0
end if;
when REG_MROD_EP1_TRXLOOPBACK =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_TRXLOOPBACK <= register_write_data_25_v(23 downto 0); -- EP1 Transceiver Loopback Enable channel 23-0
end if;
when REG_MROD_EP1_TXCVRRESET =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_TXCVRRESET <= register_write_data_25_v(23 downto 0); -- EP1 Transceiver Reset all channel 23-0
end if;
when REG_MROD_EP1_RXRESET =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_RXRESET <= register_write_data_25_v(23 downto 0); -- EP1 Receiver Reset channel 23-0
end if;
when REG_MROD_EP1_TXRESET =>
- if MROD_GENERATE_REGS = true then
+ if MROD_GENERATE_REGS then
register_map_control_s.MROD_EP1_TXRESET <= register_write_data_25_v(23 downto 0); -- EP1 Transmitter Reset channel 23-0
end if;
-----------------------------------
diff --git a/sources/templates/pcie_package.vhd b/sources/templates/pcie_package.vhd
index 010a81cb4a96ced0bd584a0e8e66c17c3f0f46a7..c126bec314fdb9d81363b48b7d5e8dafccfd696e 100644
--- a/sources/templates/pcie_package.vhd
+++ b/sources/templates/pcie_package.vhd
@@ -2011,9 +2011,9 @@ package pcie_package is
BCR : std_logic_vector(43 downto 43); -- Reset BCID to 0
ECR : std_logic_vector(42 downto 42); -- Reset L1ID to 0
- DATA_SRC_SEL : std_logic_vector(41 downto 41); -- Data source select
- -- 0: Data input comes from EMURAM
- -- 1: Data input comes from PCIe
+ CONSTANT_CHUNK_LENGTH : std_logic_vector(41 downto 41); -- Data source select
+ -- 0: Random chunk length
+ -- 1: Constant chunk length
FE_BUSY_ENABLE : std_logic_vector(31 downto 31); -- Enable the BUSY mechanism if L1A counter passes threshold
FFU_FM_EMU_T : std_logic_vector(30 downto 16); -- For Future Use (trigger registers)
@@ -6214,7 +6214,7 @@ package pcie_package is
constant REG_FMEMU_COUNTERS_L1A_CNT_C : std_logic_vector(31 downto 16) := x"0100"; -- Number of chunks to send if not in TTC mode
constant REG_FMEMU_COUNTERS_BUSY_TH_HIGH_C : std_logic_vector(15 downto 8) := x"14"; -- Assert BUSY-ON above this threshold
constant REG_FMEMU_COUNTERS_BUSY_TH_LOW_C : std_logic_vector(7 downto 0) := x"0f"; -- De-assert BUSY-ON below this threshold
- constant REG_FMEMU_CONTROL_L1A_BITNR_C : std_logic_vector(63 downto 56) := x"20"; -- Bitfield for L1A in TTC frame
+ constant REG_FMEMU_CONTROL_L1A_BITNR_C : std_logic_vector(63 downto 56) := x"30"; -- Bitfield for L1A in TTC frame
constant REG_FMEMU_CONTROL_XONXOFF_BITNR_C : std_logic_vector(55 downto 48) := x"20"; -- Bitfield for Xon/Xoff in TTC frame
constant REG_FMEMU_CONTROL_EMU_START_C : std_logic_vector(47 downto 47) := "0"; -- Start emulator functionality
constant REG_FMEMU_CONTROL_TTC_MODE_C : std_logic_vector(46 downto 46) := "0"; -- Control the emulator by TTC input or by RegMap (1/0)
@@ -6224,9 +6224,9 @@ package pcie_package is
constant REG_FMEMU_CONTROL_BCR_C : std_logic_vector(43 downto 43) := "0"; -- Reset BCID to 0
constant REG_FMEMU_CONTROL_ECR_C : std_logic_vector(42 downto 42) := "0"; -- Reset L1ID to 0
- constant REG_FMEMU_CONTROL_DATA_SRC_SEL_C : std_logic_vector(41 downto 41) := "0"; -- Data source select
- -- 0: Data input comes from EMURAM
- -- 1: Data input comes from PCIe
+ constant REG_FMEMU_CONTROL_CONSTANT_CHUNK_LENGTH_C: std_logic_vector(41 downto 41) := "0"; -- Data source select
+ -- 0: Random chunk length
+ -- 1: Constant chunk length
constant REG_FMEMU_CONTROL_FE_BUSY_ENABLE_C : std_logic_vector(31 downto 31) := "0"; -- Enable the BUSY mechanism if L1A counter passes threshold
constant REG_FMEMU_CONTROL_FFU_FM_EMU_T_C : std_logic_vector(30 downto 16) := "000000000000000"; -- For Future Use (trigger registers)
diff --git a/sources/templates/registermap.tex b/sources/templates/registermap.tex
index 589acf47340adc2aca77bedd6df1d51871e2bc40..2f0c05186fd8a0d61a367664829c1f2bf023f530 100644
--- a/sources/templates/registermap.tex
+++ b/sources/templates/registermap.tex
@@ -1264,7 +1264,7 @@ any & T & Any write to this register clears the FELIG L1ID \\
& & INLC\_CRC32 & 44:44 & W & 0: No checksum\newline 1: Append the data with a CRC32\newline \\
& & BCR & 43:43 & W & Reset BCID to 0 \\
& & ECR & 42:42 & W & Reset L1ID to 0 \\
- & & DATA\_SRC\_SEL & 41:41 & W & Data source select\newline 0: Data input comes from EMURAM\newline 1: Data input comes from PCIe\newline \\
+ & & CONSTANT\_CHUNK\_LENGTH & 41:41 & W & Data source select\newline 0: Random chunk length\newline 1: Constant chunk length\newline \\
& & INT\_STATUS\_EMU & 40:32 & R & Read internal status emulator \\
& & FE\_BUSY\_ENABLE & 31 & W & Enable the BUSY mechanism if L1A counter passes threshold \\
& & FFU\_FM\_EMU\_T & 30:16 & W & For Future Use (trigger registers) \\
diff --git a/sources/templates/registers-4.10.html b/sources/templates/registers-4.10.html
index 7121de630fce048a5ad84a6ba4eb437d6582d2ac..d14e86f4fa5c220f6e2ef42c4b58f691d9e2c99b 100644
--- a/sources/templates/registers-4.10.html
+++ b/sources/templates/registers-4.10.html
@@ -4102,10 +4102,10 @@ th {
<td class="desc">Reset L1ID to 0</td>
</tr>
<tr>
- <td class="name">DATA_SRC_SEL</td>
+ <td class="name">CONSTANT_CHUNK_LENGTH</td>
<td class="range">41..41</td>
<td class="type">W</td>
- <td class="desc">Data source select<br/>0: Data input comes from EMURAM<br/>1: Data input comes from PCIe<br/></td>
+ <td class="desc">Data source select<br/>0: Random chunk length<br/>1: Constant chunk length<br/></td>
</tr>
<tr>
<td class="name">INT_STATUS_EMU</td>
diff --git a/sources/templates/registers-4.10.yaml b/sources/templates/registers-4.10.yaml
index 527f9461db73713a1497718d6ee1475dc394ec05..38298415bdd64636c945dec90e1c69bd84c66fea 100755
--- a/sources/templates/registers-4.10.yaml
+++ b/sources/templates/registers-4.10.yaml
@@ -2779,7 +2779,7 @@ Generators:
- range: 63..56
type: W
name: L1A_BITNR
- default: 32
+ default: 48
desc: Bitfield for L1A in TTC frame
- range: 55..48
type: W
@@ -2820,12 +2820,12 @@ Generators:
desc: Reset L1ID to 0
- range: 41..41
type: W
- name: DATA_SRC_SEL
+ name: CONSTANT_CHUNK_LENGTH
default: 0
desc: |
Data source select
- 0: Data input comes from EMURAM
- 1: Data input comes from PCIe
+ 0: Random chunk length
+ 1: Constant chunk length
- range: 40..32
type: R
name: INT_STATUS_EMU
@@ -3257,7 +3257,7 @@ MRODregisters:
group: MROD_CONTROL
desc: Specific registers for MROD
endpoints: 0
- generate: MROD_GENERATE_REGS = true
+ generate: MROD_GENERATE_REGS
entries:
- name: MROD_CTRL
type: W
@@ -3419,7 +3419,7 @@ MRODmonitors:
group: MROD_MONITOR
desc: Specific registers for MROD
endpoints: 0
- generate: MROD_GENERATE_REGS = true
+ generate: MROD_GENERATE_REGS
entries:
- name: MROD_EP0_CSMH_EMPTY
type: R
diff --git a/sources/templates/registers-diff-4.9-4.10.html b/sources/templates/registers-diff-4.9-4.10.html
index 408b086a8aadb9cfdb7476a80a1c94646e7d4b2b..8b3301dcb11ee9b82ad93e5fb78d75c846a5633e 100644
--- a/sources/templates/registers-diff-4.9-4.10.html
+++ b/sources/templates/registers-diff-4.9-4.10.html
@@ -3891,7 +3891,7 @@ th {
<td class="value changedNone">None</td>
</tr>
<tr>
- <td class="state changed"></td>
+ <td class="state changedRemoved">Removed</td>
<td class="field changedNone">DATA_SRC_SEL</td>
<td class="range changedNone">41..41</td>
<td class="type changedNone">W</td>
@@ -3997,11 +3997,11 @@ th {
<td class="value changedFalse">None</td>
</tr>
<tr>
- <td class="state changed"></td>
- <td class="field changedNone">DATA_SRC_SEL</td>
- <td class="range changedFalse">41..41</td>
+ <td class="state changedAdded">Added</td>
+ <td class="field changedTrue">CONSTANT_CHUNK_LENGTH</td>
+ <td class="range changedTrue">41..41</td>
<td class="type changedFalse">W</td>
- <td class="desc changedFalse">Data source select<br/>0: Data input comes from EMURAM<br/>1: Data input comes from PCIe<br/></td>
+ <td class="desc changedFalse">Data source select<br/>0: Random chunk length<br/>1: Constant chunk length<br/></td>
<td class="value changedFalse">None</td>
</tr>
<tr>
diff --git a/sources/templates/registers.pdf b/sources/templates/registers.pdf
index 2f7017f280079acc172b664dea568b9bebb2dc95..3a096f79b0107747ea18576b4b2fc10411dc55a1 100644
Binary files a/sources/templates/registers.pdf and b/sources/templates/registers.pdf differ