diff --git a/sources/FelixMROD/Busy_TTC.vhd b/sources/FelixMROD/Busy_TTC.vhd
index 92f7c40a7388fd9199bffb8c0ba1354051e0b311..2bfc95e5523ed5bb20b734a700cbda55e7729dd0 100644
--- a/sources/FelixMROD/Busy_TTC.vhd
+++ b/sources/FelixMROD/Busy_TTC.vhd
@@ -14,7 +14,7 @@
--!-----------------------------------------------------------------------------
--! @object Entity design.Busy_TTC
--! =project FELIX_MROD
---! @modified Mon Nov 11 13:46:31 2019
+--! @modified Thu Mar 26 17:13:28 2020
--!-----------------------------------------------------------------------------
library ieee, work;
@@ -33,7 +33,6 @@ entity Busy_TTC is
generateTTCemu : boolean := false);
port (
BUSY_INTERRUPT : out std_logic;
- BUSY_OUT : out std_logic;
CDRlocked : out std_logic;
CLK_TTC_N : in std_logic;
CLK_TTC_P : in std_logic;
@@ -45,6 +44,7 @@ entity Busy_TTC is
DATA_TTC_P : in std_logic;
LOL_ADN : in std_logic;
LOS_ADN : in std_logic;
+ MasterBusy : out std_logic;
TTC_ToHost_Data : out TTC_ToHost_data_type;
TTCout : out std_logic_vector(9 downto 0);
clk40 : in std_logic;
@@ -60,7 +60,7 @@ end entity Busy_TTC;
--!-----------------------------------------------------------------------------
--! @object Architecture design.Busy_TTC.a0
--! =project FELIX_MROD
---! @modified Mon Nov 11 13:46:31 2019
+--! @modified Thu Mar 26 17:13:28 2020
--!-----------------------------------------------------------------------------
@@ -147,7 +147,7 @@ begin
ttc_TTC_BUSY_mon_array(i) <= TTC_BUSY_mon_array(i);
end generate g3;
- BUSY_OUT <= BUSY_OUT_s; -- any busy request from entity TTC_BUSY
+ MasterBusy <= BUSY_OUT_s; -- any busy request from entity MasterBusy
u1: TTCdataSwitch
generic map(
diff --git a/sources/FelixMROD/CRFM_felixmrod.vhd b/sources/FelixMROD/CRFM_felixmrod.vhd
index 7fc9d2c16fa501d00bfbe5e19aadfcaa1967a489..49365a24452bb1b5cf25c66e8656741beebe9f26 100644
--- a/sources/FelixMROD/CRFM_felixmrod.vhd
+++ b/sources/FelixMROD/CRFM_felixmrod.vhd
@@ -11,7 +11,7 @@
--! @version FELIX_MROD: Interface to GOL links coming from the MDT Chambers.
--! This code replaces the "CRFM" entity, adding special code
--! to adapt to the readout of the MDT chambers (uses no GBT links to frontend).
---! @modified Mon Feb 03 10:20:00 2020
+--! @modified Thu Apr 02 10:20:00 2020
--!-----------------------------------------------------------------------------
--! Use standard library
@@ -52,12 +52,16 @@ generic (
EnableFrHo_Egroup4Eproc8_8b10b : boolean := true;
wideMode : boolean := false; -- [set in top module]
STATIC_CENTRALROUTER : boolean := false; -- removes update process from central router register map, only initial constant values are used
+ FIRMWARE_MODE : integer := 1;
--
FMCH_NUM : integer := 1;
toHostTimeoutBitn : integer := 8;
GENERATE_XOFF : boolean := true;
CARD_TYPE : integer := 712;
- CREnableFromHost : boolean := true
+ CREnableFromHost : boolean := true;
+ SUPER_CHUNK_FACTOR : integer := 1;
+ BLOCKSIZE : integer := 1024;
+ CHUNK_TRAILER_32B : boolean := false
);
port (
clk40 : in std_logic;
@@ -132,7 +136,8 @@ signal fhMUXdout_valid, thMUXdin_rdy, thMUXdin_rdy_s : std_logic := '0';
type gbtFHconfig_array_type is array (0 to (GBT_NUM-1)) of crUpstreamConfig_type;
signal gbtFHconfig_array : gbtFHconfig_array_type;
-signal THtransferENA, crOUTfifo_pfull, croutfifo_full, DownFifoPEmpty_s, croutfifo_empty : std_logic;
+signal THtransferENA, DownFifoPEmpty_s : std_logic;
+signal crOUTfifo_pfull, croutfifo_full, croutfifo_empty : std_logic;
signal fmch_monitor_array : fmch_monitor_array_type(0 to FMCH_NUM-1);
----
signal busyOut_array : busyOut_array_type (0 to (FMCH_NUM-1));
@@ -155,6 +160,7 @@ signal register_queue_array : register_queue_array_type;
signal fhFifoDout_rdy : std_logic := '0';
signal fhFifoDout : std_logic_vector (255 downto 0);
signal thFMbusyOut_s : std_logic_vector ((FMCH_NUM-1) downto 0);
+signal thFMXoff_s : std_logic;
signal UpFifoFull_mon_array : UpFifoFull_mon_array_type(0 to 23);
@@ -163,8 +169,6 @@ signal TTC_DELAY_array : TTC_DELAY_array_type;
signal auxUpstreamConfig : std_logic_vector (0 downto 0);
-signal thFMXoff_s : std_logic;
-
signal upfifoDoutClk : std_logic;
constant FMCH_NUM_ZEROS: std_logic_vector(FMCH_NUM-1 downto 0) := (others => '0');
@@ -181,22 +185,16 @@ end function;
signal ExtendedTestPulse : std_logic; -- NSW required a 32x 40MHz clock pulse,
signal TestPulseCounter : integer range 0 to 31; -- 32 states counter
-constant felix_mrod : boolean := true;
-
------------------------------------------------------------------------------------------
begin
-do_g0: if (felix_mrod = true) generate
+do_g0: if (FIRMWARE_MODE = 8) generate -- firmware for FelixMROD
-- Assign clock (FromHost direction)
upfifoDoutClk <= clk80;
- -- cr_monitor unused
- -- register_map_cr_monitor.IC_FROMHOST_FIFO <= (others => (others => '0'));
- -- register_map_cr_monitor.IC_TOHOST_FIFO <= (others => (others => '0'));
-
end generate do_g0;
-do_g1: if (felix_mrod = false) generate
+do_g1: if (FIRMWARE_MODE /= 8) generate -- not for FelixMROD
--Assign multiplexer clock according to the number of channels (FromHost direction), we need at least 12.5MHz per GBT_NUM
g_upfifoclk_40M: if GBT_NUM <= 3 generate
upfifoDoutClk <= clk40;
@@ -232,7 +230,7 @@ port map(
--
-do_g2: if (felix_mrod = false) generate
+do_g2: if (FIRMWARE_MODE /= 8) generate -- not for FelixMROD
------------------------------------------------------------------------------------------
-- CRFM monitor register connection module
@@ -433,7 +431,7 @@ port map(
);
--
end generate crFH;
-
+--
------------------------------------------------------------
-- from Host input fifo
------------------------------------------------------------
@@ -442,20 +440,22 @@ end generate crFH;
UpFifoPfull_or <= '0' when (UpFifoPfull_array = zerosGBT_NUMarray) else '1'; -- can't write to at least one GBT wm fifo -> stop reading from crINfifo
crINfifo_re <= (not crINfifo_empty) and (not UpFifoPfull_or) and (not cr_rst);
--
-
fhFifoDout<= fromHostFifo_dout;
fromHostFifo_rd_en <= crINfifo_re;
crINfifo_empty <= fromHostFifo_empty;
fromHostFifo_rd_clk <= upfifoDoutClk;
fromHostFifo_rst <= cr_fifo_flush;
-
+--
+fhXoff <= '0' when (fhXoff_array = zerosGBT_NUMarray) else '1';
+--
end generate g_enableFromHost;
-do_g3: if (CREnableFromHost = false and felix_mrod = true) generate
+do_g3: if (CREnableFromHost = false and FIRMWARE_MODE = 8) generate -- for FelixMROD
+fhXoff_array <= (others => '0'); -- no fhXoff_array output from GBTdmUpstream
+UpFifoPfull_or <= '0'; -- no UpFifoPfull_array output from GBTdmUpstream
+crINfifo_re <= '1' when ((crINfifo_empty = '0') and (UpFifoPfull_or = '0') and (cr_rst = '0')) else '0';
-- if I can't write (UpFifoPfull/=0) to at least one GBT wm fifo, then stop reading from crINfifo
-crINfifo_re <= '1' when ((crINfifo_empty = '0') and (cr_rst = '0')) else '0'; -- no UpFifoPfull_array
-fhXoff_array <= (others => '0'); -- no fhXoff_array and UpFifoPfull_array output from GBTdmUpstream
fhFifoDout<= fromHostFifo_dout;
fromHostFifo_rd_en <= crINfifo_re;
@@ -463,15 +463,14 @@ crINfifo_empty <= fromHostFifo_empty;
fromHostFifo_rd_clk <= upfifoDoutClk;
fromHostFifo_rst <= cr_fifo_flush;
-end generate do_g3;
+fhXoff <= '0' when (fhXoff_array = zerosGBT_NUMarray) else '1';
+end generate do_g3;
--
--fhFifoPfull <= fhFifoPfull_s; -- goes to wupper
--
-fhXoff <= '0' when (fhXoff_array = zerosGBT_NUMarray) else '1';
--
-
process(upfifoDoutClk) -- 1-clock pipeline
begin
if rising_edge(upfifoDoutClk) then
@@ -500,13 +499,17 @@ begin
thFMdmN: entity work.thFMdm
generic map(
FMCHid => I,
+ FIRMWARE_MODE => FIRMWARE_MODE,
STATIC_CENTRALROUTER => STATIC_CENTRALROUTER,
- toHostTimeoutBitn => toHostTimeoutBitn
+ toHostTimeoutBitn => toHostTimeoutBitn,
+ SUPER_CHUNK_FACTOR => SUPER_CHUNK_FACTOR,
+ BLOCKSIZE => BLOCKSIZE,
+ CHUNK_TRAILER_32B => CHUNK_TRAILER_32B
)
port map(
clk40 => clk40,
clk250 => clk250,
- clk_wrth => clk80, --
+ clk_wrth => clk80, -- clock for write to host
rst => cr_rst,
register_map_control => register_map_control,
register_map_control_appreg_clk => register_map_control_appreg_clk, --register_map_control,
@@ -523,7 +526,7 @@ port map(
fmchFifo_dvalid => fmchFifo_dvalid_array(I),
fmchFifo_hasBlock => fmchFifo_hasBlock_array(I), -- out, 'block_ready' flag
fmchXoffout => fmchXoff_array(I), -- out test purposes only, flag to a data source to stop transmitting
- fmchHighThreshCrossed => register_map_xoff_monitor.XOFF_FM_HIGH_THRESH.CROSS_LATCHED(I+24), -- max. 24
+ fmchHighThreshCrossed => register_map_xoff_monitor.XOFF_FM_HIGH_THRESH.CROSS_LATCHED(I+24),
fmchHighThreshCrossedLatch => register_map_xoff_monitor.XOFF_FM_HIGH_THRESH.CROSSED(I),
fmchLowThreshCrossed => register_map_xoff_monitor.XOFF_FM_LOW_THRESH_CROSSED(I),
--fmchXoffin => croutfifo_full, -- in, crOUTfifo is pfull 4060/3830 (out of 4096), stop writing flag
@@ -558,7 +561,7 @@ port map(
-----
TTC_ToHost_emu_ena => register_map_control.CR_TTC_TOHOST.EMU_ENABLE(2), -- IG: enabling the emulator
TTC_ToHost_Fake_ena => register_map_control.CR_TTC_TOHOST.EMU_FAKE_READY_ENABLE(63), -- IG: enable the fake ready signals from the emulator
- TTC_ToHost_Fake_Val => register_map_control.CR_TTC_TOHOST.EMU_FAKE_READY_VALUE(60 downto 48), -- IG: set the value of the fake ready signals counter (vector is one bit bigger then the TTC_ToHost_TO_max)
+ TTC_ToHost_Fake_Val => register_map_control.CR_TTC_TOHOST.EMU_FAKE_READY_VALUE(60 downto 48), -- IG: set the value of the fake ready signals counter (vector is one bit bigger then the TTC_ToHost_TO_max)
-----
FIFOdout => fmchFifo_dout_array(FMCH_NUM),
FIFOhasBlock => fmchFifo_hasBlock_array(FMCH_NUM),
@@ -574,11 +577,12 @@ port map(
------------------------------------------------------------
THPCIeM: entity work.thfmPCIeManager
generic map(
- FMCH_NUM => FMCH_NUM+1
+ FMCH_NUM => FMCH_NUM+1,
+ BLOCKSIZE => BLOCKSIZE
)
port map(
clk => clk250,
- rst => cr_rst, -- reset is deasserted after fifo flush!
+ rst => cr_rst, -- reset is deasserted after fifo flush!
thch_rdy_array => fmchFifo_hasBlock_array, -- in, 'block_ready' flags from GBTdms
PCIe_ena => THtransferENA, -- in, '1' when crOUTfifo is ready to accept 1 block (not fifo pfull)
thch_sel => thch_sel, -- out, data mux select
@@ -611,12 +615,12 @@ dataMUXn: entity work.MUXn_d256b (Behavioral)
sel_bitn => 5 -- max. 24
)
port map(
- clk => clk250,
- data => fmchFifo_dout_array,
- data_rdy => thMUXdin_rdy,
- sel => thMUXsel,
- data_out => fhMUXdout,
- data_out_rdy => fhMUXdout_valid
+ clk => clk250,
+ data => fmchFifo_dout_array,
+ data_rdy => thMUXdin_rdy,
+ sel => thMUXsel,
+ data_out => fhMUXdout,
+ data_out_rdy => fhMUXdout_valid
);
--
------------------------------------------------------------
@@ -668,10 +672,10 @@ begin
elsif rising_edge(clk40) then
for i in 0 to FMCH_NUM-1 loop
if(thFMbusyOut_s(i) = '1') then
- register_map_xoff_monitor.FM_BUSY_CHANNEL_STATUS.BUSY_LATCHED(i+24) <= '1'; -- max. 24
+ register_map_xoff_monitor.FM_BUSY_CHANNEL_STATUS.BUSY_LATCHED(i+24) <= '1';
end if;
if(register_map_control.FM_BUSY_CHANNEL_STATUS.CLEAR_LATCH="1") then
- register_map_xoff_monitor.FM_BUSY_CHANNEL_STATUS.BUSY_LATCHED(i+24) <= '0'; -- max. 24
+ register_map_xoff_monitor.FM_BUSY_CHANNEL_STATUS.BUSY_LATCHED(i+24) <= '0';
end if;
register_map_xoff_monitor.FM_BUSY_CHANNEL_STATUS.BUSY(i) <= thFMbusyOut_s(i);
end loop;
@@ -705,5 +709,49 @@ begin
end process;
+do_g10: if (FIRMWARE_MODE = 8) generate -- firmware for FelixMROD
+ -- drive unused data from host to gbt
+ do_g11: for i in 0 to (GBT_NUM-1) generate
+ fhOutData_array(i) <= (others => '0');
+ end generate do_g11;
+ --
+ -- drive unused registers xoff_monitor.dma...
+ register_map_xoff_monitor.DMA_BUSY_STATUS.FROMHOST_BUSY <= (others => '0');
+ register_map_xoff_monitor.DMA_BUSY_STATUS.TOHOST_BUSY <= (others => '0');
+ register_map_xoff_monitor.DMA_BUSY_STATUS.FROMHOST_BUSY_LATCHED <= (others => '0');
+ register_map_xoff_monitor.DMA_BUSY_STATUS.TOHOST_BUSY_LATCHED <= (others => '0');
+ register_map_cr_monitor.MAX_TIMEOUT <= (others => '0');
+ --
+ -- drive unused registers cr_monitor.ic...
+ do_g12: for i in 0 to (GBT_NUM-1) generate
+ register_map_cr_monitor.IC_FROMHOST_FIFO(i).FULL <= (others => '0');
+ register_map_cr_monitor.IC_TOHOST_FIFO(i).EMPTY <= (others => '0');
+ register_map_cr_monitor.IC_TOHOST_FIFO(i).DATAOUT <= (others => '0');
+ end generate do_g12;
+ -- drive unused registers cr_monitor.cr_tohost_gbt_mon...
+ do_g13: for i in 0 to (GBT_NUM-1) generate
+ register_map_cr_monitor.CR_TOHOST_GBT_MON(i).CROUTFIFO_PROG_FULL <= (others => '0');
+ register_map_cr_monitor.CR_TOHOST_GBT_MON(i).WMFIFO_FULL <= (others => '0');
+ register_map_cr_monitor.CR_TOHOST_GBT_MON(i).MINI_EGROUP_ALMOST_FULL <= (others => '0');
+ register_map_cr_monitor.CR_TOHOST_GBT_MON(i).EPATH0_ALMOST_FULL <= (others => '0');
+ register_map_cr_monitor.CR_TOHOST_GBT_MON(i).EPATH1_ALMOST_FULL <= (others => '0');
+ register_map_cr_monitor.CR_TOHOST_GBT_MON(i).EPATH2_ALMOST_FULL <= (others => '0');
+ register_map_cr_monitor.CR_TOHOST_GBT_MON(i).EPATH3_ALMOST_FULL <= (others => '0');
+ register_map_cr_monitor.CR_TOHOST_GBT_MON(i).EPATH4_ALMOST_FULL <= (others => '0');
+ register_map_cr_monitor.CR_TOHOST_GBT_MON(i).EPATH5_ALMOST_FULL <= (others => '0');
+ register_map_cr_monitor.CR_TOHOST_GBT_MON(i).EPATH6_ALMOST_FULL <= (others => '0');
+ end generate do_g13;
+ -- drive unused registers cr_monitor.cr_fromhost_gbt_mon...
+ do_g14: for i in 0 to (GBT_NUM-1) generate
+ -- register_map_cr_monitor.CR_FROMHOST_GBT_MON(i).xxx <= (others => '0');
+ register_map_cr_monitor.CR_FROMHOST_GBT_MON(i).MINI_EGROUP_ALMOST_FULL <= (others => '0');
+ register_map_cr_monitor.CR_FROMHOST_GBT_MON(i).EPATH0_ALMOST_FULL <= (others => '0');
+ register_map_cr_monitor.CR_FROMHOST_GBT_MON(i).EPATH1_ALMOST_FULL <= (others => '0');
+ register_map_cr_monitor.CR_FROMHOST_GBT_MON(i).EPATH2_ALMOST_FULL <= (others => '0');
+ register_map_cr_monitor.CR_FROMHOST_GBT_MON(i).EPATH3_ALMOST_FULL <= (others => '0');
+ register_map_cr_monitor.CR_FROMHOST_GBT_MON(i).EPATH4_ALMOST_FULL <= (others => '0');
+ end generate do_g14;
+end generate do_g10;
+
end Behavioral;
diff --git a/sources/FelixMROD/CR_Wupper.vhd b/sources/FelixMROD/CR_Wupper.vhd
index f0fba404b9e8cbb6f36932e6bdacc20c4b0cd54d..ed1903d35defa3a4c31adcbe374f10303b3bd671 100644
--- a/sources/FelixMROD/CR_Wupper.vhd
+++ b/sources/FelixMROD/CR_Wupper.vhd
@@ -14,7 +14,7 @@
--!-----------------------------------------------------------------------------
--! @object Entity design.CR_Wupper
--! =project FELIX_MROD
---! @modified Wed Jan 29 12:04:03 2020
+--! @modified Fri Apr 03 20:45:11 2020
--!-----------------------------------------------------------------------------
library ieee, work;
@@ -43,7 +43,11 @@ entity CR_Wupper is
STATIC_CENTRALROUTER : boolean := true;
CREnableFromHost : boolean := true;
toHostTimeoutBitn : integer := 10;
+ BLOCKSIZE : integer := 1024;
+ CHUNK_TRAILER_32B : boolean := false;
+ SUPER_CHUNK_FACTOR : integer := 1;
wideMode : boolean := false;
+ FIRMWARE_MODE : integer := 1;
BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE";
GIT_HASH : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000";
GIT_TAG : std_logic_vector(127 downto 0) := x"00000000000000000000000000000000";
@@ -74,11 +78,16 @@ entity CR_Wupper is
BUSY_INTERRUPT : in std_logic;
CRBusyOut : out std_logic_vector(NUMCH-1 downto 0);
CR_FIFO_Busy : out std_logic;
+ CSM0Monitor : in regs_csm_monitor;
+ CSM1Monitor : in regs_csm_monitor;
ChBusy : out std_logic_vector(NUMCH-1 downto 0);
ChData : in slv33_array(0 to NUMCH-1);
ChValid : in std_logic_vector(NUMCH-1 downto 0);
+ MasterBusy : in std_logic;
TTC_ToHost_Data : in TTC_ToHost_data_type;
TTCout : in std_logic_vector(9 downto 0);
+ Trx0Monitor : in regs_trx_monitor;
+ Trx1Monitor : in regs_trx_monitor;
clk160 : in std_logic;
clk250 : in std_logic;
clk40 : in std_logic;
@@ -99,8 +108,6 @@ entity CR_Wupper is
prmap_app_control : out register_map_control_type;
prmap_board_info : in register_map_gen_board_info_type;
prmap_hk_monitor : in register_map_hk_monitor_type;
- prmap_mrodEP0_mon : in regmap_mrodEP0_monitor_type;
- prmap_mrodEP1_mon : in regmap_mrodEP1_monitor_type;
prmap_ttc_monitor : in register_map_ttc_monitor_type;
rst_hw : in std_logic;
rst_soft_40 : out std_logic;
@@ -112,7 +119,7 @@ end entity CR_Wupper;
--!-----------------------------------------------------------------------------
--! @object Architecture design.CR_Wupper.a0
--! =project FELIX_MROD
---! @modified Wed Jan 29 12:04:03 2020
+--! @modified Fri Apr 03 20:45:11 2020
--!-----------------------------------------------------------------------------
@@ -129,6 +136,10 @@ architecture a0 of CR_Wupper is
GENERATE_XOFF : boolean := true;
CARD_TYPE : integer := 712;
CREnableFromHost : boolean := true;
+ BLOCKSIZE : integer := 1024;
+ CHUNK_TRAILER_32B : boolean := false;
+ SUPER_CHUNK_FACTOR : integer := 1;
+ FIRMWARE_MODE : integer := 1;
EnableFrHo_Egroup0Eproc2_HDLC : boolean := false;
EnableFrHo_Egroup0Eproc2_8b10b : boolean := false;
EnableFrHo_Egroup0Eproc4_8b10b : boolean := false;
@@ -199,13 +210,13 @@ architecture a0 of CR_Wupper is
register_map_gen_board_info : in register_map_gen_board_info_type;
register_map_hk_monitor : in register_map_hk_monitor_type;
register_map_monitor : out register_map_monitor_type;
- register_mrodEP0_mon : in regmap_mrodEP0_monitor_type;
- register_mrodEP1_mon : in regmap_mrodEP1_monitor_type;
+ register_mrod_monitor : in regmap_mrod_monitor_type;
register_map_ttc_monitor : in register_map_ttc_monitor_type;
register_map_xoff_monitor : in register_map_xoff_monitor_type;
rst_hw : in std_logic;
rst_soft_40 : out std_logic;
- rst_soft_appregclk : in std_logic);
+ rst_soft_appregclk : in std_logic;
+ master_busy_in : in std_logic);
end component register_map_sync;
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
@@ -310,8 +321,7 @@ architecture a0 of CR_Wupper is
signal register_map_cr_monitor : register_map_cr_monitor_type;
signal register_map_gbt_monitor : register_map_gbt_monitor_type;
signal register_map_gen_board_info : register_map_gen_board_info_type;
- signal register_mrodEP0_mon : regmap_mrodEP0_monitor_type;
- signal register_mrodEP1_mon : regmap_mrodEP1_monitor_type;
+ signal register_mrod_monitor : regmap_mrod_monitor_type;
signal register_map_ttc_monitor : register_map_ttc_monitor_type;
signal cr_register_map_xoff_monitor : register_map_xoff_monitor_type;
signal interrupt_call : std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4);
@@ -363,28 +373,29 @@ begin
thFMlinkValid_array <= ChValid; -- input valid
ChBusy <= thFMbusy_array; -- FMCR busy
- CRBusyOut(NUMCH-1 downto 0) <= thFMbusy_array(FMCH_NUM-1 downto 0); --@@GBT_NUM/2-1
+ CRBusyOut(NUMCH-1 downto 0) <= thFMbusy_array(FMCH_NUM-1 downto 0);
rst_soft_40 <= rst_soft_40_0; -- reset output
pcie_DMA_Busy <= pcie_tohost_busy_out;
pcie_soft_reset <= reset_soft_pcie;
pcie_appreg_clk <= appreg_clk; --appreg_clk output from pcie
- prmap_app_control <= pcie_register_map_control_appreg_clk; -- registers on appreg_clk
- prmap_40_control <= pcie_register_map_40_control; -- registers on clk40
+ prmap_app_control <= pcie_register_map_control_appreg_clk; -- registers on appreg_clk
+ prmap_40_control <= pcie_register_map_40_control; -- registers on clk40
register_map_hk_monitor <= prmap_hk_monitor;
register_map_gen_board_info <= prmap_board_info;
register_map_ttc_monitor <= prmap_ttc_monitor;
- register_mrodEP0_mon <= prmap_mrodEP0_mon;
- register_mrodEP1_mon <= prmap_mrodEP1_mon;
- -- gbt monitor registers unused
- --register_map_gbt_monitor <= prmap_gbt_mon;
+ register_mrod_monitor.MROD_EP0_RXLOCKED(NUMCH-1 downto 0) <= Trx0Monitor.RXLOCKED(NUMCH-1 downto 0);
+ register_mrod_monitor.MROD_EP0_TXLOCKED(NUMCH-1 downto 0) <= Trx0Monitor.RXLOCKED(NUMCH-1 downto 0);
+ register_mrod_monitor.MROD_EP0_CSMH_EMPTY(NUMCH-1 downto 0) <= CSM0Monitor.CSMH_EMPTY(NUMCH-1 downto 0);
+ register_mrod_monitor.MROD_EP0_CSMH_FULL(NUMCH-1 downto 0) <= CSM0Monitor.CSMH_FULL(NUMCH-1 downto 0);
- -- gbt emulator unused
- register_map_emu_monitor.GBT_EMU_CONFIG.RDDATA <= (others => '0');
- register_map_emu_monitor.GBT_FM_EMU_READ <= (others => '0');
+ register_mrod_monitor.MROD_EP1_RXLOCKED(NUMCH-1 downto 0) <= Trx1Monitor.RXLOCKED(NUMCH-1 downto 0);
+ register_mrod_monitor.MROD_EP1_TXLOCKED(NUMCH-1 downto 0) <= Trx1Monitor.RXLOCKED(NUMCH-1 downto 0);
+ register_mrod_monitor.MROD_EP1_CSMH_EMPTY(NUMCH-1 downto 0) <= CSM1Monitor.CSMH_EMPTY(NUMCH-1 downto 0);
+ register_mrod_monitor.MROD_EP1_CSMH_FULL(NUMCH-1 downto 0) <= CSM1Monitor.CSMH_FULL(NUMCH-1 downto 0);
interrupt_call_i <= interrupt_call(7) & BUSY_INTERRUPT & interrupt_call(5 downto 4);
@@ -428,6 +439,10 @@ begin
GENERATE_XOFF => GENERATE_XOFF,
CARD_TYPE => CARD_TYPE,
CREnableFromHost => CREnableFromHost,
+ BLOCKSIZE => BLOCKSIZE,
+ CHUNK_TRAILER_32B => CHUNK_TRAILER_32B,
+ SUPER_CHUNK_FACTOR => SUPER_CHUNK_FACTOR,
+ FIRMWARE_MODE => FIRMWARE_MODE,
EnableFrHo_Egroup0Eproc2_HDLC => EnableFrHo_Egroup0Eproc2_HDLC,
EnableFrHo_Egroup0Eproc2_8b10b => EnableFrHo_Egroup0Eproc2_8b10b,
EnableFrHo_Egroup0Eproc4_8b10b => EnableFrHo_Egroup0Eproc4_8b10b,
@@ -498,13 +513,13 @@ begin
register_map_gen_board_info => register_map_gen_board_info,
register_map_hk_monitor => register_map_hk_monitor,
register_map_monitor => pcie_register_map_monitor,
- register_mrodEP0_mon => register_mrodEP0_mon,
- register_mrodEP1_mon => register_mrodEP1_mon,
+ register_mrod_monitor => register_mrod_monitor,
register_map_ttc_monitor => register_map_ttc_monitor,
register_map_xoff_monitor => cr_register_map_xoff_monitor,
rst_hw => rst_hw,
rst_soft_40 => rst_soft_40_0,
- rst_soft_appregclk => reset_soft_pcie
+ rst_soft_appregclk => reset_soft_pcie,
+ master_busy_in => MasterBusy
);
u3: fifo_16KB_256to32 -- small fromHost fifo (512x256 to 4096x32)
@@ -593,5 +608,40 @@ begin
tohost_busy_out => pcie_tohost_busy_out
);
+ ---------------------------------------------
+
+ -- drive unused registers emu_monitor...
+ register_map_emu_monitor.GBT_EMU_CONFIG.RDDATA <= (others => '0');
+ register_map_emu_monitor.GBT_FM_EMU_READ <= (others => '0');
+
+ -- drive unused registers gbt_monitor...
+ register_map_gbt_monitor.GBT_VERSION.DATE <= (others => '0');
+ register_map_gbt_monitor.GBT_VERSION.GBT_VERSION <= (others => '0');
+ register_map_gbt_monitor.GBT_VERSION.GTH_IP_VERSION <= (others => '0');
+ register_map_gbt_monitor.GBT_VERSION.RESERVED <= (others => '0');
+ register_map_gbt_monitor.GBT_VERSION.GTHREFCLK_SEL <= (others => '0');
+ register_map_gbt_monitor.GBT_VERSION.RX_CLK_SEL <= (others => '0');
+ register_map_gbt_monitor.GBT_VERSION.PLL_SEL <= (others => '0');
+ register_map_gbt_monitor.GBT_TXRESET_DONE <= (others => '0');
+ register_map_gbt_monitor.GBT_RXRESET_DONE <= (others => '0');
+ register_map_gbt_monitor.GBT_TXFSMRESET_DONE <= (others => '0');
+ register_map_gbt_monitor.GBT_RXFSMRESET_DONE <= (others => '0');
+ register_map_gbt_monitor.GBT_CPLL_FBCLK_LOST <= (others => '0');
+ register_map_gbt_monitor.GBT_PLL_LOCK.QPLL_LOCK <= (others => '0');
+ register_map_gbt_monitor.GBT_PLL_LOCK.CPLL_LOCK <= (others => '0');
+ register_map_gbt_monitor.GBT_RXCDR_LOCK <= (others => '0');
+ register_map_gbt_monitor.GBT_CLK_SAMPLED <= (others => '0');
+ register_map_gbt_monitor.GBT_RX_IS_HEADER <= (others => '0');
+ register_map_gbt_monitor.GBT_RX_IS_DATA <= (others => '0');
+ register_map_gbt_monitor.GBT_RX_HEADER_FOUND <= (others => '0');
+ register_map_gbt_monitor.GBT_ALIGNMENT_DONE <= (others => '0');
+ register_map_gbt_monitor.GBT_OUT_MUX_STATUS <= (others => '0');
+ register_map_gbt_monitor.GBT_ERROR <= (others => '0');
+ register_map_gbt_monitor.GBT_GBT_TOPBOT_C <= (others => '0');
+ register_map_gbt_monitor.GBT_FM_RX_DISP_ERROR1 <= (others => '0');
+ register_map_gbt_monitor.GBT_FM_RX_DISP_ERROR2 <= (others => '0');
+ register_map_gbt_monitor.GBT_FM_RX_NOTINTABLE1 <= (others => '0');
+ register_map_gbt_monitor.GBT_FM_RX_NOTINTABLE2 <= (others => '0');
+
end architecture a0 ; -- of CR_Wupper
diff --git a/sources/FelixMROD/CSMHandler.vhd b/sources/FelixMROD/CSMHandler.vhd
index a2c0230174eec5e2c7873a66de1b08410616f842..b9ae506574e251277c371df2dac2849869c3c0cf 100644
--- a/sources/FelixMROD/CSMHandler.vhd
+++ b/sources/FelixMROD/CSMHandler.vhd
@@ -14,7 +14,7 @@
--!-----------------------------------------------------------------------------
--! @object Entity design.CSMHandler
--! =project FELIX_MROD
---! @modified Wed Nov 27 14:27:03 2019
+--! @modified Wed Apr 01 23:09:11 2020
--!-----------------------------------------------------------------------------
library ieee, work;
@@ -31,6 +31,7 @@ entity CSMHandler is
NUMCH : integer := 2;
W_ENDPOINT : integer := 0); -- select Wupper_Endpoint partition
port (
+ CSMMonitor : out regs_csm_monitor;
ChBusy : in std_logic_vector(NUMCH-1 downto 0);
ChData : out slv33_array(0 to NUMCH-1);
ChValid : out std_logic_vector(NUMCH-1 downto 0);
@@ -50,15 +51,13 @@ entity CSMHandler is
fhFifoRE : out std_logic;
fhFifoValid : in std_logic;
prmap_app_control : in register_map_control_type;
- prmap_mrodEP0_mon : out regmap_mrodEP0_monitor_type;
- prmap_mrodEP1_mon : out regmap_mrodEP1_monitor_type;
sys_reset_n : in std_logic);
end entity CSMHandler;
--!-----------------------------------------------------------------------------
--! @object Architecture design.CSMHandler.a0
--! =project FELIX_MROD
---! @modified Wed Nov 27 14:27:03 2019
+--! @modified Wed Apr 01 23:09:11 2020
--!-----------------------------------------------------------------------------
architecture a0 of CSMHandler is
@@ -158,6 +157,7 @@ begin
NUMCH => NUMCH,
W_ENDPOINT => W_ENDPOINT)
port map(
+ CSMMonitor => CSMMonitor,
ClearCh => ClearCh,
Empty => Empty,
EmptySupp => EmptySupp,
@@ -173,8 +173,6 @@ begin
clk50 => clk50,
clk80 => clk80,
prmap_app_control => prmap_app_control,
- prmap_mrodEP0_mon => prmap_mrodEP0_mon,
- prmap_mrodEP1_mon => prmap_mrodEP1_mon,
sys_reset_n => sys_reset_n);
end architecture a0 ; -- of CSMHandler
diff --git a/sources/FelixMROD/CareTaker.vhd b/sources/FelixMROD/CareTaker.vhd
index 1005fc30a6788cf20d485bc5476c80279c726904..820d5bb08845fa8076e3e401ae25ff664b82be44 100644
--- a/sources/FelixMROD/CareTaker.vhd
+++ b/sources/FelixMROD/CareTaker.vhd
@@ -14,7 +14,7 @@
--!-----------------------------------------------------------------------------
--! @object Entity design.CareTaker
--! =project FELIX_MROD
---! @modified Mon Feb 03 10:21:29 2020
+--! @modified Sun Mar 29 15:07:09 2020
--!-----------------------------------------------------------------------------
library ieee, work;
@@ -47,7 +47,6 @@ entity CareTaker is
USE_Si5324_RefCLK : boolean := false;
generateTTCemu : boolean := false;
generate_IC_EC_TTC_only : boolean := false;
- GENERATE_FEI4B : boolean := false;
GENERATE_TRUNCATION_MECHANISM : boolean := false;
wideMode : boolean := false;
EnableFrHo_Egroup0Eproc2_HDLC : boolean := false;
@@ -94,7 +93,10 @@ entity CareTaker is
EnableToHo_Egroup4Eproc2_8b10b : boolean := false;
EnableToHo_Egroup4Eproc4_8b10b : boolean := false;
EnableToHo_Egroup4Eproc8_8b10b : boolean := false;
- EnableToHo_Egroup4Eproc16_8b10b : boolean := false);
+ EnableToHo_Egroup4Eproc16_8b10b : boolean := false;
+ GENERATE_FEI4B : boolean := false;
+ BLOCKSIZE : integer := 1024;
+ CHUNK_TRAILER_32B : boolean := false);
port (
I2C_SMB : out std_logic;
I2C_SMBUS_CFG_nEN : out std_logic;
@@ -159,7 +161,7 @@ end entity CareTaker;
--!-----------------------------------------------------------------------------
--! @object Architecture design.CareTaker.a0
--! =project FELIX_MROD
---! @modified Mon Feb 03 10:21:29 2020
+--! @modified Sun Mar 29 15:07:09 2020
--!-----------------------------------------------------------------------------
@@ -231,7 +233,9 @@ architecture a0 of CareTaker is
EnableFrHo_Egroup4Eproc2_8b10b : boolean := false;
EnableFrHo_Egroup4Eproc4_8b10b : boolean := false;
EnableFrHo_Egroup4Eproc8_8b10b : boolean := false;
- GENERATE_FEI4B : boolean := false);
+ GENERATE_FEI4B : boolean := false;
+ BLOCKSIZE : integer := 1024;
+ CHUNK_TRAILER_32B : boolean := false);
port (
LMK_locked : in std_logic_vector(0 downto 0);
MMCM_Locked_in : in std_logic;
@@ -340,7 +344,6 @@ begin
includeDirectMode => includeDirectMode,
CREnableFromHost => CREnableFromHost,
GENERATE_XOFF => GENERATE_XOFF,
- GENERATE_FEI4B => GENERATE_FEI4B,
EnableToHo_Egroup0Eproc2_HDLC => EnableToHo_Egroup0Eproc2_HDLC,
EnableToHo_Egroup0Eproc2_8b10b => EnableToHo_Egroup0Eproc2_8b10b,
EnableToHo_Egroup0Eproc4_8b10b => EnableToHo_Egroup0Eproc4_8b10b,
@@ -385,7 +388,10 @@ begin
EnableFrHo_Egroup4Eproc2_HDLC => EnableFrHo_Egroup4Eproc2_HDLC,
EnableFrHo_Egroup4Eproc2_8b10b => EnableFrHo_Egroup4Eproc2_8b10b,
EnableFrHo_Egroup4Eproc4_8b10b => EnableFrHo_Egroup4Eproc4_8b10b,
- EnableFrHo_Egroup4Eproc8_8b10b => EnableFrHo_Egroup4Eproc8_8b10b)
+ EnableFrHo_Egroup4Eproc8_8b10b => EnableFrHo_Egroup4Eproc8_8b10b,
+ GENERATE_FEI4B => GENERATE_FEI4B,
+ BLOCKSIZE => BLOCKSIZE,
+ CHUNK_TRAILER_32B => CHUNK_TRAILER_32B)
port map(
LMK_locked => slv_LMK_locked,
MMCM_Locked_in => MMCM_Locked,
diff --git a/sources/FelixMROD/EvtMux.vhd b/sources/FelixMROD/EvtMux.vhd
index f47753d8c334f3e9c62098abdcd995fff1a7f147..309fb18a5f168e39bb765fbde68981f3ac6d55f5 100644
--- a/sources/FelixMROD/EvtMux.vhd
+++ b/sources/FelixMROD/EvtMux.vhd
@@ -14,7 +14,7 @@
--!-----------------------------------------------------------------------------
--! @object Entity design.EvtMux
--! =project FELIX_MROD
---! @modified Mon Oct 14 18:30:25 2019
+--! @modified Sat Mar 14 11:26:45 2020
--!-----------------------------------------------------------------------------
library ieee, work;
@@ -49,7 +49,7 @@ end entity EvtMux;
--!-----------------------------------------------------------------------------
--! @object Architecture design.EvtMux.a0
--! =project FELIX_MROD
---! @modified Mon Oct 14 18:30:25 2019
+--! @modified Sat Mar 14 11:26:45 2020
--!-----------------------------------------------------------------------------
@@ -76,6 +76,9 @@ architecture a0 of EvtMux is
--GTMode(1) : 1/0 : circulate fifo / fill fifo from HOST SHARC (replace BOT+EOT)
--GTMode(2) : 1/0 : triggered / untriggered test mode
+ -- BOT: 31-29="101", 28-24="TDCnr", 23-12=ECnt, 11-00=BCnt
+ -- EOT: 31-28="1100", 27-24="00x0" , 23-12=ECnt, 11-00=wcnt
+
begin
EnaRun <= GTMode(0); -- GTMode(0)='1': run the emulator; when '0': load data into fifo
@@ -95,9 +98,13 @@ begin
-- Select ECnt to overwrite parts of the BOT and EOT words in the data.
-- Force bit 26 to zero before calculating the (horizontal) parity (odd parity goes to bit 26)
- Fdata <= DF(31 downto 27) & '0' & DF(25) & DF(24) & ECnt & DF(11 downto 0) -- insert new ECnt
- when ((GTMode(1) = '1') and (BOTEvt = '1' or EOTEvt = '1')) -- when BOT or EOT
- else DF(31 downto 27) & '0' & DF(25 downto 0); -- any other data unchanged
+ Fdata(31 downto 12) <= DF(31 downto 27) & '0' & DF(25) & DF(24) & ECnt -- insert new ECnt
+ when ((GTMode(1) = '1') and (BOTEvt = '1' or EOTEvt = '1')) -- when BOT or EOT
+ else DF(31 downto 27) & '0' & DF(25 downto 12); -- any other data unchanged
+
+ Fdata(11 downto 0) <= x"BC" & ECnt(3 downto 0) -- insert new BCnt: x"BC" & ECnt(3-0)
+ when ((GTMode(1) = '1') and (BOTEvt = '1')) -- when BOT
+ else DF(11 downto 0); -- any other data unchanged
-- read FifoBuffer when (not EmptyBuffer and not FullSender and not ForceIdle)
diff --git a/sources/FelixMROD/GetControls.vhd b/sources/FelixMROD/GetControls.vhd
index d33228ef86a10ade349e2411318a8a3707d7540d..c901f6c01162e3899ca427c384bcbd519507646c 100644
--- a/sources/FelixMROD/GetControls.vhd
+++ b/sources/FelixMROD/GetControls.vhd
@@ -14,7 +14,7 @@
--!-----------------------------------------------------------------------------
--! @object Entity design.GetControls
--! =project FELIX_MROD
---! @modified Wed Nov 27 15:06:33 2019
+--! @modified Fri Apr 03 20:44:55 2020
--!-----------------------------------------------------------------------------
library ieee, work;
@@ -31,6 +31,7 @@ entity GetControls is
NUMCH : integer := 2;
W_ENDPOINT : integer := 0);
port (
+ CSMMonitor : out regs_csm_monitor;
ClearCh : out std_logic_vector(NUMCH-1 downto 0);
Empty : in std_logic_vector(NUMCH-1 downto 0);
EmptySupp : out std_logic_vector(NUMCH-1 downto 0);
@@ -46,15 +47,13 @@ entity GetControls is
clk50 : in std_logic;
clk80 : in std_logic;
prmap_app_control : in register_map_control_type;
- prmap_mrodEP0_mon : out regmap_mrodEP0_monitor_type;
- prmap_mrodEP1_mon : out regmap_mrodEP1_monitor_type;
sys_reset_n : in std_logic);
end entity GetControls;
--!-----------------------------------------------------------------------------
--! @object Architecture design.GetControls.a0
--! =project FELIX_MROD
---! @modified Wed Nov 27 15:06:33 2019
+--! @modified Fri Apr 03 20:44:55 2020
--!-----------------------------------------------------------------------------
@@ -93,9 +92,6 @@ begin
end if;
end loop;
EnaReadHost <= check; -- enable when one or more bits are set
- --
- prmap_mrodEP0_mon.MROD_EP0_CSMH_EMPTY(NUMCH-1 downto 0) <= Empty(NUMCH-1 downto 0);
- prmap_mrodEP0_mon.MROD_EP0_CSMH_FULL(NUMCH-1 downto 0) <= Full(NUMCH-1 downto 0);
end if;
end process;
@@ -156,9 +152,6 @@ begin
end if;
end loop;
EnaReadHost <= check; -- enable when one or more bits are set
- --
- prmap_mrodEP1_mon.MROD_EP1_CSMH_EMPTY(NUMCH-1 downto 0) <= Empty(NUMCH-1 downto 0);
- prmap_mrodEP1_mon.MROD_EP1_CSMH_FULL(NUMCH-1 downto 0) <= Full(NUMCH-1 downto 0);
end if;
end process;
@@ -195,5 +188,20 @@ begin
end generate gen1;
+ -- synchronize monitor registers into clk80 domain (centralrouter)
+
+ pr20:
+ process (clk80, sys_reset_n)
+ variable check : std_logic;
+ begin
+ if (sys_reset_n = '0') then
+ CSMMonitor.CSMH_EMPTY(NUMCH-1 downto 0) <= (others => '0');
+ CSMMonitor.CSMH_FULL(NUMCH-1 downto 0) <= (others => '0');
+ elsif (rising_edge(clk80)) then
+ CSMMonitor.CSMH_EMPTY(NUMCH-1 downto 0) <= Empty(NUMCH-1 downto 0);
+ CSMMonitor.CSMH_FULL(NUMCH-1 downto 0) <= Full(NUMCH-1 downto 0);
+ end if;
+ end process;
+
end architecture a0 ; -- of GetControls
diff --git a/sources/FelixMROD/GetTRXControl.vhd b/sources/FelixMROD/GetTRXControl.vhd
index 22c03805a2143cfbc96ce0b9a778a4b48281bfad..67461c331dca07bfca1084da09ef28349d9aa452 100644
--- a/sources/FelixMROD/GetTRXControl.vhd
+++ b/sources/FelixMROD/GetTRXControl.vhd
@@ -14,7 +14,7 @@
--!-----------------------------------------------------------------------------
--! @object Entity design.GetTRXControl
--! =project FELIX_MROD
---! @modified Tue Jan 21 22:22:08 2020
+--! @modified Fri Apr 03 20:51:07 2020
--!-----------------------------------------------------------------------------
library ieee, work;
@@ -40,18 +40,17 @@ entity GetTRXControl is
TXCVR_ResetAll : out std_logic_vector(NUMCH-1 downto 0);
TX_CHxLocked : in std_logic_vector(NUMCH-1 downto 0);
TX_CHxReset : out std_logic_vector(NUMCH-1 downto 0);
+ TrxMonitor : out regs_trx_monitor;
clk40 : in std_logic;
clk50 : in std_logic;
prmap_app_control : in register_map_control_type;
- prmap_mrodEP0_mon : out regmap_mrodEP0_monitor_type;
- prmap_mrodEP1_mon : out regmap_mrodEP1_monitor_type;
sys_reset_n : in std_logic);
end entity GetTRXControl;
--!-----------------------------------------------------------------------------
--! @object Architecture design.GetTRXControl.a0
--! =project FELIX_MROD
---! @modified Tue Jan 21 22:22:08 2020
+--! @modified Fri Apr 03 20:51:07 2020
--!-----------------------------------------------------------------------------
@@ -79,8 +78,6 @@ begin
TX_CHxReset(NUMCH-1 downto 0) <= prmap_app_control.MROD_EP0_TXRESET(NUMCH-1 downto 0);
TXCVR_ResetAll(NUMCH-1 downto 0) <= prmap_app_control.MROD_EP0_TXCVRRESET(NUMCH-1 downto 0);
EnManSlide <= prmap_app_control.MROD_CTRL.OPTIONS(12);
- prmap_mrodEP0_mon.MROD_EP0_RXLOCKED(NUMCH-1 downto 0) <= RX_CHxLocked(NUMCH-1 downto 0);
- prmap_mrodEP0_mon.MROD_EP0_TXLOCKED(NUMCH-1 downto 0) <= TX_CHxLocked(NUMCH-1 downto 0);
end if;
end process;
@@ -128,8 +125,6 @@ begin
TX_CHxReset(NUMCH-1 downto 0) <= prmap_app_control.MROD_EP1_TXRESET(NUMCH-1 downto 0);
TXCVR_ResetAll(NUMCH-1 downto 0) <= prmap_app_control.MROD_EP1_TXCVRRESET(NUMCH-1 downto 0);
EnManSlide <= prmap_app_control.MROD_CTRL.OPTIONS(12);
- prmap_mrodEP1_mon.MROD_EP1_RXLOCKED(NUMCH-1 downto 0) <= RX_CHxLocked(NUMCH-1 downto 0);
- prmap_mrodEP1_mon.MROD_EP1_TXLOCKED(NUMCH-1 downto 0) <= TX_CHxLocked(NUMCH-1 downto 0);
end if;
end process;
@@ -158,5 +153,19 @@ begin
end generate gen1;
+ -- synchronize monitor registers into the clk40 domain (centralrouter)
+
+ pr20:
+ process (clk40, sys_reset_n)
+ begin
+ if (sys_reset_n = '0') then
+ TrxMonitor.RXLOCKED(NUMCH-1 downto 0) <= (others => '0');
+ TrxMonitor.TXLOCKED(NUMCH-1 downto 0) <= (others => '0');
+ elsif (rising_edge(clk40)) then
+ TrxMonitor.RXLOCKED(NUMCH-1 downto 0) <= RX_CHxLocked(NUMCH-1 downto 0);
+ TrxMonitor.TXLOCKED(NUMCH-1 downto 0) <= TX_CHxLocked(NUMCH-1 downto 0);
+ end if;
+ end process;
+
end architecture a0 ; -- of GetTRXControl
diff --git a/sources/FelixMROD/Transceiver-dum.vhd b/sources/FelixMROD/Transceiver-dum.vhd
deleted file mode 100644
index de36f1164cc8515450c5ed5604b4b2f8b3d8dc08..0000000000000000000000000000000000000000
--- a/sources/FelixMROD/Transceiver-dum.vhd
+++ /dev/null
@@ -1,103 +0,0 @@
---!-----------------------------------------------------------------------------
---! @authors R. Habraken, T. Wijnen
---! @company Radboud University Nijmegen
---! @startdate 01-Feb-2019
---! @version 1.0
---! @project FELIX_MROD: MROD functionality implemented on a FELIX board.
---!-----------------------------------------------------------------------------
---! @brief
---! Use a FELIX board to interface to GOL links coming from the MDT Chambers.
---! Provides a new type of interface to possibly replace the MROD system.
---!
---!-----------------------------------------------------------------------------
-
---!-----------------------------------------------------------------------------
---! @object Entity design.Transceiver
---! =project FELIX_MROD
---! @modified Tue Jan 21 22:44:46 2020
---!-----------------------------------------------------------------------------
-
-library ieee, work;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-use work.felix_mrod_package.all;
-use work.centralRouter_package.all;
-use work.FELIX_gbt_package.all;
-use work.pcie_package.all;
-
-entity Transceiver is
- generic(
- GBT_NUM : integer := 4;
- NUMCH : integer := 4;
- W_ENDPOINT : integer := 0);
- port (
- EnChan : in std_logic_vector(NUMCH-1 downto 0);
- EnManSlide : in std_logic;
- MReset : in std_logic;
- QX_GTREFCLK_N : in std_logic_vector(4 downto 0);
- QX_GTREFCLK_P : in std_logic_vector(4 downto 0);
- RX_CHxLocked : out std_logic_vector(NUMCH-1 downto 0);
- RX_CHxReset : in std_logic_vector(NUMCH-1 downto 0);
- RxClk : out std_logic_vector(NUMCH-1 downto 0);
- RxData : out slv32_array(0 to NUMCH-1);
- RxValid : out std_logic_vector(NUMCH-1 downto 0);
- TRXloopback : in std_logic_vector(NUMCH-1 downto 0);
- TXCVR_ResetAll : in std_logic_vector(NUMCH-1 downto 0);
- TX_CHxLocked : out std_logic_vector(NUMCH-1 downto 0);
- TX_CHxReset : in std_logic_vector(NUMCH-1 downto 0);
- TxClk : out std_logic_vector(NUMCH-1 downto 0);
- TxData : in slv33_array(0 to NUMCH-1);
- TxValid : in std_logic_vector(NUMCH-1 downto 0);
- clk50 : in std_logic;
- gtrxn_in : in std_logic_vector(NUMCH-1 downto 0);
- gtrxp_in : in std_logic_vector(NUMCH-1 downto 0);
- gttxn_out : out std_logic_vector(NUMCH-1 downto 0);
- gttxp_out : out std_logic_vector(NUMCH-1 downto 0);
- prmap_app_control : in register_map_control_type;
- sysclk_in : in std_logic);
-end entity Transceiver;
-
---!-----------------------------------------------------------------------------
---! @object Architecture design.Transceiver.a0
---! =project FELIX_MROD
---! @modified Tue Jan 21 22:44:46 2020
---!-----------------------------------------------------------------------------
-
-
-architecture a0 of Transceiver is
-
--- signal loopback_s : std_logic_vector(2 downto 0); -- "000" = no loopback
--- loopback_s <= prmap_app_control.GTH_LOOPBACK_CONTROL;
-
- signal loopback : std_logic_vector(23 downto 0);
- signal txDvalid : std_logic_vector(NUMCH-1 downto 0);
-
-begin
-
- RxClk <= (others => clk50);
- TxClk <= (others => clk50);
-
- g0: if (W_ENDPOINT = 0) generate --
- loopback <= prmap_app_control.MROD_EP0_TRXLOOPBACK;
- end generate g0;
-
- g1: if (W_ENDPOINT = 1) generate --
- loopback <= prmap_app_control.MROD_EP1_TRXLOOPBACK;
- end generate g1;
-
- g2: for i in NUMCH-1 downto 0 generate
- begin
- txDvalid(i) <= '1' when (TxValid(i) = '1' and TxData(i)(32) = '0') else '0';
- RxValid(i) <= txDvalid(i) when (loopback(i) = '1') else '0';
- RxData(i) <= TxData(i)(31 downto 0) when (txDvalid(i) = '1') else x"04000000";
- end generate g2;
-
- g3: for i in NUMCH-1 downto 0 generate
- begin
- gttxn_out(i) <= '1';
- gttxp_out(i) <= '0';
- end generate g3;
-
-end architecture a0 ; -- of Transceiver
-
diff --git a/sources/FelixMROD/Transceiver.vhd b/sources/FelixMROD/Transceiver.vhd
index 906092934bc1bddb2ee34a3f8b0f51486f732b97..5cbbae4d6a00b1c2b758b2d4e0e343da828693f8 100644
--- a/sources/FelixMROD/Transceiver.vhd
+++ b/sources/FelixMROD/Transceiver.vhd
@@ -13,8 +13,8 @@
--!-----------------------------------------------------------------------------
--! @object Entity design.Transceiver
---! project FELIX_MROD
---! modified Tue Jun 04 12:14:23 2019
+--! =project FELIX_MROD
+--! @modified Mon Mar 30 10:32:32 2020
--!-----------------------------------------------------------------------------
library ieee, work;
@@ -23,599 +23,83 @@ use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.felix_mrod_package.all;
use work.centralRouter_package.all;
---use work.FELIX_gbt_package.all;
+use work.FELIX_gbt_package.all;
use work.pcie_package.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
entity Transceiver is
generic(
- W_ENDPOINT : integer := 0;
- NUMCH : integer := 2;
- GBT_NUM : integer := 4);
+ GBT_NUM : integer := 4;
+ NUMCH : integer := 4;
+ W_ENDPOINT : integer := 0);
port (
- EnChan : in std_logic_vector(NUMCH-1 downto 0);
- MReset : in std_logic;
- QX_GTREFCLK_N : in std_logic_vector(4 downto 0);
- QX_GTREFCLK_P : in std_logic_vector(4 downto 0);
- RX_CHxLocked : out std_logic_vector(NUMCH-1 downto 0);
- RX_CHxReset : in std_logic_vector(NUMCH-1 downto 0);
- --RX_FSM_RESET_DONE : out std_logic_vector(NUMCH/4-1 downto 0);
- ------------------ Receive Ports - FPGA RX interface Ports -----------------
- RxClk : out std_logic_vector(NUMCH-1 downto 0);
- RxData : out slv32_array(0 to NUMCH-1);
- RxValid : out std_logic_vector(NUMCH-1 downto 0);
- ------------------ Transmit Ports - TX Data Path interface -----------------
- TRXloopback : in std_logic_vector(NUMCH-1 downto 0);
- TX_CHxLocked : in std_logic_vector(NUMCH-1 downto 0);
- TX_CHxReset : in std_logic_vector(NUMCH-1 downto 0);
- TxClk : out std_logic_vector(NUMCH-1 downto 0);
- TxData : in slv33_array(0 to NUMCH-1);
- TxValid : in std_logic_vector(NUMCH-1 downto 0);
- ------------------ Transmit Ports - pattern Generator Ports ----------------
- --Txprbssel_in : in std_logic_vector(2 downto 0);
- clk50 : in std_logic;
- gtrxn_in : in std_logic_vector(NUMCH-1 downto 0);
- gtrxp_in : in std_logic_vector(NUMCH-1 downto 0);
- gttxn_out : out std_logic_vector(NUMCH-1 downto 0);
- gttxp_out : out std_logic_vector(NUMCH-1 downto 0);
- ------------------ 40 MHz system (DRP) clk
- prmap_app_control : in register_map_control_type;
- --register_map_control : in register_map_control_type;
- sysclk_in : in std_logic
- );
-
+ EnChan : in std_logic_vector(NUMCH-1 downto 0);
+ EnManSlide : in std_logic;
+ MReset : in std_logic;
+ QX_GTREFCLK_N : in std_logic_vector(4 downto 0);
+ QX_GTREFCLK_P : in std_logic_vector(4 downto 0);
+ RX_CHxLocked : out std_logic_vector(NUMCH-1 downto 0);
+ RX_CHxReset : in std_logic_vector(NUMCH-1 downto 0);
+ RxClk : out std_logic_vector(NUMCH-1 downto 0);
+ RxData : out slv32_array(0 to NUMCH-1);
+ RxValid : out std_logic_vector(NUMCH-1 downto 0);
+ TRXloopback : in std_logic_vector(NUMCH-1 downto 0);
+ TXCVR_ResetAll : in std_logic_vector(NUMCH-1 downto 0);
+ TX_CHxLocked : out std_logic_vector(NUMCH-1 downto 0);
+ TX_CHxReset : in std_logic_vector(NUMCH-1 downto 0);
+ TxClk : out std_logic_vector(NUMCH-1 downto 0);
+ TxData : in slv33_array(0 to NUMCH-1);
+ TxValid : in std_logic_vector(NUMCH-1 downto 0);
+ clk50 : in std_logic;
+ gtrxn_in : in std_logic_vector(NUMCH-1 downto 0);
+ gtrxp_in : in std_logic_vector(NUMCH-1 downto 0);
+ gttxn_out : out std_logic_vector(NUMCH-1 downto 0);
+ gttxp_out : out std_logic_vector(NUMCH-1 downto 0);
+ prmap_app_control : in register_map_control_type;
+ sysclk_in : in std_logic);
end entity Transceiver;
--!-----------------------------------------------------------------------------
--! @object Architecture design.Transceiver.a0
---! project FELIX_MROD
---! modified Tue Jun 04 12:14:23 2019
+--! =project FELIX_MROD
+--! @modified Mon Mar 30 10:32:32 2020
--!-----------------------------------------------------------------------------
-architecture a0 of Transceiver is
-
---COMPONENT MRODtransceiver_core
--- PORT (
--- gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
--- gtwiz_userclk_tx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
--- gtwiz_userclk_tx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
--- gtwiz_userclk_tx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
--- gtwiz_userclk_tx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
--- gtwiz_userclk_rx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
--- gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
--- gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
--- gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
--- gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
--- gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
--- gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
--- gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
--- gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
--- gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
--- gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
--- gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
--- gtrefclk01_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
--- qpll1outclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
--- qpll1outrefclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
--- drpclk_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
--- gthrxn_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
--- gthrxp_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
--- gtrefclk0_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
--- loopback_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
--- rx8b10ben_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
--- rxusrclk_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
--- rxusrclk2_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
--- tx8b10ben_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
--- txctrl0_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
--- txctrl1_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
--- txctrl2_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
--- gthtxn_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
--- gthtxp_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
--- gtpowergood_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
--- rxcdrlock_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
--- rxctrl0_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
--- rxctrl1_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
--- rxctrl2_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--- rxctrl3_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--- rxoutclk_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
--- rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
--- txpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
--- txprgdivresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
--- );
---END COMPONENT;
-
-COMPONENT MRODtransceiver_core
- PORT (
- gtwiz_userclk_tx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userclk_rx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
- gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
- gtrefclk01_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- qpll1outclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- qpll1outrefclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- drpclk_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- gthrxn_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- gthrxp_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- gtrefclk0_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- loopback_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
- rx8b10ben_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- rxusrclk_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- rxusrclk2_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- tx8b10ben_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- txctrl0_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
- txctrl1_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
- txctrl2_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- txusrclk_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- txusrclk2_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- gthtxn_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- gthtxp_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- gtpowergood_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- rxcdrlock_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- rxctrl0_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
- rxctrl1_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
- rxctrl2_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- rxctrl3_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- rxoutclk_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- txoutclk_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- txpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- txprgdivresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
- );
-END COMPONENT;
-
-
-COMPONENT vio_0_quad
- PORT (
- clk : IN STD_LOGIC;
- probe_in0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- probe_in1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- probe_in2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- probe_in3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe_in4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe_in5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe_out3 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
- );
-END COMPONENT;
-
-COMPONENT ila_gth_quad
-
-PORT (
- clk : IN STD_LOGIC;
- probe0 : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
- probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- probe2 : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
- probe3 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
- probe4 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
- probe5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- probe6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
-);
-END COMPONENT ;
-signal RESETslv: std_logic_vector (0 downto 0);
-signal RX_FSM_RESET_DONE_sA,RX_FSM_RESET_DONE_sB: std_logic_vector(NUMCH/4-1 downto 0);
---signal RXSLIDE_S: std_logic_vector(NUMCH - 1 downto 0);
-signal gtrefclk0_i, gtrefclk1_i, gtrefclk2_i : std_logic;
-signal loopback_in_s : std_logic_vector(2 downto 0);
-signal rxusrclk_sA, rxusrclk_sB : std_logic_vector(NUMCH-1 downto 0);
-signal rxoutclk_sA, rxoutclk_sB : std_logic_vector(NUMCH-1 downto 0);
-signal txusrclk_sA, txusrclk_sB : std_logic_vector(NUMCH-1 downto 0);
-signal txoutclk_sA, txoutclk_sB : std_logic_vector(NUMCH-1 downto 0);
-signal rxdata_out_sA, rxdata_out_sB : std_logic_vector((NUMCH*32)-1 downto 0);
-signal txdata_in_sA, txdata_in_sB : std_logic_vector((NUMCH*32)-1 downto 0);
-signal gtrxp_in_sA, gtrxn_in_sA, gttxp_out_sA, gttxn_out_sA : std_logic_vector(NUMCH-1 downto 0);
-signal gtrxp_in_sB, gtrxn_in_sB, gttxp_out_sB, gttxn_out_sB : std_logic_vector(NUMCH-1 downto 0);
-signal txctrl2_in_sA, txctrl2_in_sB : std_logic_vector((NUMCH*8)-1 downto 0);
-signal rxctrl0_out_sA, rxctrl0_out_sB : std_logic_vector((NUMCH*16)-1 downto 0);
-signal rxctrl1_out_sA, rxctrl1_out_sB : std_logic_vector((NUMCH*16)-1 downto 0);
-signal rxctrl2_out_sA, rxctrl2_out_sB : std_logic_vector((NUMCH*8)-1 downto 0);
-signal rxctrl3_out_sA, rxctrl3_out_sB : std_logic_vector((NUMCH*8)-1 downto 0);
-
-signal rxcdrlock_out_sA, rxcdrlock_out_sB : std_logic_vector(NUMCH-1 downto 0);
-
---Monitor signals (connect to VIO)
-signal rxpmaresetdone_out_sA, rxpmaresetdone_out_sB : std_logic_vector(NUMCH-1 downto 0);
-signal txpmaresetdone_out_sA, txpmaresetdone_out_sB : std_logic_vector(NUMCH-1 downto 0);
-signal gtpowergood_out_sA, gtpowergood_out_sB : std_logic_vector(NUMCH-1 downto 0);
-signal gtwiz_reset_rx_done_out_sA : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_rx_done_out_sB : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_tx_done_out_sA : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_tx_done_out_sB : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_rx_cdr_stable_out_sA : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_rx_cdr_stable_out_sB : std_logic_vector(NUMCH/4-1 downto 0);
-
---Resets, connected to VIO
---signal gtwiz_reset_rx_datapath_in : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_rx_datapath_in_sA : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_rx_datapath_in_sB : std_logic_vector(NUMCH/4-1 downto 0);
---signal gtwiz_reset_rx_pll_and_datapath_in : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_rx_pll_and_datapath_in_sA : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_rx_pll_and_datapath_in_sB : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_all_in : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_all_in_sA : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_all_in_sB : std_logic_vector(NUMCH/4-1 downto 0);
---signal gtwiz_reset_tx_pll_and_datapath_in : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_tx_pll_and_datapath_in_sA : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_tx_pll_and_datapath_in_sB : std_logic_vector(NUMCH/4-1 downto 0);
---signal gtwiz_reset_tx_datapath_in : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_tx_datapath_in_sA : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_reset_tx_datapath_in_sB : std_logic_vector(NUMCH/4-1 downto 0);
---signal gtwiz_userclk_tx_reset_in : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_userclk_tx_reset_in_sA : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_userclk_tx_reset_in_sB : std_logic_vector(NUMCH/4-1 downto 0);
---signal gtwiz_userclk_rx_active_in : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_userclk_rx_active_in_sA : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_userclk_rx_active_in_sB : std_logic_vector(NUMCH/4-1 downto 0);
---signal gtwiz_userclk_tx_active_out : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_userclk_tx_active_out_sA : std_logic_vector(NUMCH/4-1 downto 0);
-signal gtwiz_userclk_tx_active_out_sB : std_logic_vector(NUMCH/4-1 downto 0);
+architecture a0 of Transceiver is
-type drpclk_in_type is array (NUMCH/4-1 downto 0) of std_logic_vector(3 downto 0);
-signal drpclk_in, gtrefclk0_in_sA, gtrefclk0_in_sB : drpclk_in_type;
-signal cesyncRX_s, clrsyncRX_s : std_logic_vector(NUMCH-1 downto 0);
-signal cesyncTX_s, clrsyncTX_s : std_logic_vector(NUMCH-1 downto 0);
+ --signal loopback_s : std_logic_vector(2 downto 0); -- "000" = no loopback
+ --loopback_s <= prmap_app_control.GTH_LOOPBACK_CONTROL;
---signal rxdata_out : slv32_array(0 to NUMCH-1);
-signal rxcharisk_out : slv04_array(0 to NUMCH -1);
-signal txdata_in_bufA, txdata_in_bufB : slv32_array(0 to NUMCH-1);
-signal txcharisk_in : slv04_array(0 to NUMCH-1);
-signal RXUSRCLK_OUT : std_logic_vector(NUMCH-1 downto 0);
-signal TXUSRCLK_OUT : std_logic_vector(NUMCH-1 downto 0);
+ signal loopback : std_logic_vector(23 downto 0);
+ signal txDvalid : std_logic_vector(NUMCH-1 downto 0);
begin
- loopback_in_s <= prmap_app_control.GTH_LOOPBACK_CONTROL;
- RESETslv <= (others => MReset);
-
--- generate once per PCIE end point
- genEP_0: if (W_ENDPOINT = 0) generate
-
--- generate once per channel
- g_CHx_A: for i in 0 to (NUMCH - 1) generate
- RX_CHxLocked(i) <= rxcdrlock_out_sA(i); --'1';
-
- gttxp_out(i) <= gttxp_out_sA(i);
- gttxn_out(i) <= gttxn_out_sA(i);
- gtrxp_in_sA(i) <= gtrxp_in(i);
- gtrxn_in_sA(i) <= gtrxn_in(i);
-
- --RX data, ctrl and clk
- RxData(i) <= rxdata_out_sA(i*32+31 downto i*32);
- rxcharisk_out(i) <= rxctrl0_out_sA(i*16+3 downto i*16);
- RxValid(i) <= '1' when (rxcharisk_out(i) = "0000") else '0';
- RxClk(i) <= rxusrclk_sA(i);
-
- -- EP 0: TRX data, ctrl and clk
- txdata_in_bufA(i) <= TxData(31 downto 0)(i);
- txdata_in_sA(i*32+31 downto i*32) <= txdata_in_bufA(i);
- txcharisk_in(i) <= (others => TxData(i)(32) );
- txctrl2_in_sA(i*8+3 downto i*8) <= txcharisk_in(i);
- TxClk(i) <= txusrclk_sA(i);
-
- -- Rx and Tx clk buffers
- BUFG_GT_RXinst: BUFG_GT port map(
- O => rxusrclk_sA(i),
- CE => cesyncRX_s(i),
- CEMASK => '1',
- CLR => clrsyncRX_s(i),
- CLRMASK => '1',
- DIV => "000",
- I => rxoutclk_sA(i)
- );
-
- BUFG_GT_SYNC_RXinst: BUFG_GT_SYNC port map(
- CESYNC => cesyncRX_s(i),
- CLRSYNC => clrsyncRX_s(i),
- CLK => rxoutclk_sA(i),
- CE => '1',
- CLR => '0'
- );
-
- BUFG_GT_TXinst: BUFG_GT port map(
- O => txusrclk_sA(i),
- CE => cesyncTX_s(i),
- CEMASK => '1',
- CLR => clrsyncTX_s(i),
- CLRMASK => '1',
- DIV => "000",
- I => txoutclk_sA(i)
- );
-
- BUFG_GT_SYNC_TXinst: BUFG_GT_SYNC port map(
- CESYNC => cesyncTX_s(i),
- CLRSYNC => clrsyncTX_s(i),
- CLK => txoutclk_sA(i),
- CE => '1',
- CLR => '0'
- );
- end generate g_CHx_A;
-
---gen XCVR CoreA: if (W_ENDPOINT = 0) generate
-g_quadsA: for i in 0 to (NUMCH/4-1) generate -- channel A LOWER SLR generate in multiples of 4 channels
-
- -- RefClk
- IBUFDS_GTE3_inst0 : IBUFDS_GTE3
- generic map (
- REFCLK_EN_TX_PATH => '0', -- Refer to Transceiver User Guide
- REFCLK_HROW_CK_SEL => "00", -- Refer to Transceiver User Guide
- REFCLK_ICNTL_RX => "00" -- Refer to Transceiver User Guide
- )
- port map (
- O => gtrefclk0_i, -- 1-bit output: Refer to Transceiver User Guide
- ODIV2 => open, -- 1-bit output: Refer to Transceiver User Guide
- CEB => '0', -- 1-bit input: Refer to Transceiver User Guide
- I => Qx_GTREFCLK_P(0), -- 1-bit input: Refer to Transceiver User Guide
- IB => Qx_GTREFCLK_N(0) -- 1-bit input: Refer to Transceiver User Guide
- );
-
- drpclk_in(i) <= (others => sysclk_in);
- gtrefclk0_in_sA(i) <= (others => gtrefclk0_i);
- --RX_FSM_RESET_DONE(i) <= RX_FSM_RESET_DONE_sA(i);
-
- u0 : MRODtransceiver_core
- PORT MAP (
- gtwiz_userclk_tx_active_in => (others => '1'),
- gtwiz_userclk_rx_active_in => gtwiz_userclk_rx_active_in_sA(i downto i),
- gtwiz_reset_clk_freerun_in(0) => sysclk_in,
- gtwiz_reset_all_in => gtwiz_reset_all_in_sA(i downto i),
- gtwiz_reset_tx_pll_and_datapath_in => gtwiz_reset_tx_pll_and_datapath_in_sA(i downto i) or RESETslv,
- gtwiz_reset_tx_datapath_in => gtwiz_reset_tx_datapath_in_sA(i downto i),
- gtwiz_reset_rx_pll_and_datapath_in => gtwiz_reset_rx_pll_and_datapath_in_sA(i downto i),
- gtwiz_reset_rx_datapath_in => gtwiz_reset_rx_datapath_in_sA(i downto i),
- gtwiz_reset_rx_cdr_stable_out => gtwiz_reset_rx_cdr_stable_out_sA(i downto i),
- gtwiz_reset_tx_done_out => gtwiz_reset_tx_done_out_sA(i downto i),
- gtwiz_reset_rx_done_out => RX_FSM_RESET_DONE_sA(i downto i),
- gtwiz_userdata_tx_in => txdata_in_sA((128*(i+1))-1 downto (128 * (i))),
- gtwiz_userdata_rx_out => rxdata_out_sA((128*(i+1))-1 downto (128 * (i))),
- gtrefclk01_in(0) => gtrefclk0_i,
- qpll1outclk_out => open,
- qpll1outrefclk_out => open,
- drpclk_in => drpclk_in(i),
- gthrxn_in => gtrxn_in_sA,
- gthrxp_in => gtrxp_in_sA,
- gtrefclk0_in => gtrefclk0_in_sA(i),
- loopback_in => (loopback_in_s & loopback_in_s & loopback_in_s & loopback_in_s),-- "1111",
- rx8b10ben_in => (others => '1'),
- rxusrclk_in => rxusrclk_sA(i*4+3 downto i*4),
- rxusrclk2_in => rxusrclk_sA(i*4+3 downto i*4),
- tx8b10ben_in => (others => '1'),
- txctrl0_in => (others => '0'),
- txctrl1_in => (others => '0'),
- txctrl2_in => txctrl2_in_sA((32*(i+1))-1 downto 32*(i)),
- txusrclk_in => txusrclk_sA(i*4+3 downto i*4),
- txusrclk2_in => txusrclk_sA(i*4+3 downto i*4),
- gthtxn_out => gttxn_out_sA,
- gthtxp_out => gttxp_out_sA,
- gtpowergood_out => gtpowergood_out_sA,
- rxcdrlock_out => rxcdrlock_out_sA((4*(i+1))-1 downto 4*(i)),
- rxctrl0_out => rxctrl0_out_sA,
- rxctrl1_out => rxctrl1_out_sA,
- rxctrl2_out => rxctrl2_out_sA,
- rxctrl3_out => rxctrl3_out_sA,
- rxoutclk_out => rxoutclk_sA(i*4+3 downto i*4),
- rxpmaresetdone_out => rxpmaresetdone_out_sA((4*(i+1))-1 downto 4*(i)),
- txoutclk_out => txoutclk_sA(i*4+3 downto i*4),
- txpmaresetdone_out => txpmaresetdone_out_sA((4*(i+1))-1 downto 4*(i)),
- txprgdivresetdone_out => open
- );
-
- transceiver_vioA: vio_0_quad
- PORT MAP (
- clk => sysclk_in,
- probe_in0 => rxpmaresetdone_out_sA,--4
- probe_in1 => txpmaresetdone_out_sA,--4
- probe_in2 => gtpowergood_out_sA, --4
- probe_in3 => RX_FSM_RESET_DONE_sA, --1
- probe_in4 => gtwiz_reset_tx_done_out_sA, --1
- probe_in5 => gtwiz_reset_rx_cdr_stable_out_sA,--1
- probe_out0 => gtwiz_reset_rx_datapath_in_sA,--1
- probe_out1 => gtwiz_reset_rx_pll_and_datapath_in_sA,--1
- probe_out2 => gtwiz_reset_all_in_sA,--1
- probe_out3 => gtwiz_reset_tx_pll_and_datapath_in_sA,--1
- probe_out4 => gtwiz_reset_tx_datapath_in_sA,--1
- probe_out5 => gtwiz_userclk_tx_reset_in_sA,--1
- probe_out6 => gtwiz_userclk_rx_active_in_sA--1 Set to 1 in VIO.
- );
-
- transceiver_ilaA : ila_gth_quad
- PORT MAP (
- clk => rxusrclk_sA(0),
- probe0 => txdata_in_sA,
- probe1 => txctrl2_in_sA,
- probe2 => rxdata_out_sA,
- probe3 => rxctrl0_out_sA,
- probe4 => rxctrl1_out_sA,
- probe5 => rxctrl2_out_sA,
- probe6 => rxctrl3_out_sA
- );
-
- end generate g_quadsA; --A channel
- end generate genEP_0;
-
-
- genEP_1: if (W_ENDPOINT = 1) generate
-
--- generate once per channel
- g_CHx_B: for i in 0 to (NUMCH - 1) generate
- RX_CHxLocked(i) <= rxcdrlock_out_sB(i); --'1';
-
- gttxp_out(i) <= gttxp_out_sB(i);
- gttxn_out(i) <= gttxn_out_sB(i);
- gtrxp_in_sB(i) <= gtrxp_in(i);
- gtrxn_in_sB(i) <= gtrxn_in(i);
-
- --RX data, ctrl and clk
- RxData(i) <= rxdata_out_sB(i*32+31 downto i*32);
- rxcharisk_out(i) <= rxctrl0_out_sB(i*16+3 downto i*16);
- RxValid(i) <= '1' when (rxcharisk_out(i) = "0000") else '0';
-
- RxClk(i) <= rxusrclk_sB(i);
-
- --EP 1: TRX data, ctrl and clk
- txdata_in_bufB(i) <= TxData(31 downto 0)(i);
- txdata_in_sB(i*32+31 downto i*32) <= txdata_in_bufB(i);
- txcharisk_in(i) <= (others => TxData(i)(32) );
- txctrl2_in_sB(i*8+3 downto i*8) <= txcharisk_in(i);
- TxClk(i) <= txusrclk_sB(i);
-
- -- Rx and Tx clk buffers
- BUFG_GT_RXinst: BUFG_GT port map(
- O => rxusrclk_sB(i),
- CE => cesyncRX_s(i),
- CEMASK => '1',
- CLR => clrsyncRX_s(i),
- CLRMASK => '1',
- DIV => "000",
- I => rxoutclk_sB(i)
- );
-
- BUFG_GT_SYNC_RXinst: BUFG_GT_SYNC port map(
- CESYNC => cesyncRX_s(i),
- CLRSYNC => clrsyncRX_s(i),
- CLK => rxoutclk_sB(i),
- CE => '1',
- CLR => '0'
- );
-
- BUFG_GT_TXinst: BUFG_GT port map(
- O => txusrclk_sB(i),
- CE => cesyncTX_s(i),
- CEMASK => '1',
- CLR => clrsyncTX_s(i),
- CLRMASK => '1',
- DIV => "000",
- I => txoutclk_sB(i)
- );
-
- BUFG_GT_SYNC_TXinst: BUFG_GT_SYNC port map(
- CESYNC => cesyncTX_s(i),
- CLRSYNC => clrsyncTX_s(i),
- CLK => txoutclk_sB(i),
- CE => '1',
- CLR => '0'
- );
- end generate g_CHx_B;
-
-
---gen XCVR_CoreB: if (W_ENDPOINT = 1) generate
-g_quadsB: for i in 0 to (NUMCH/4-1) generate -- channel B UPPER SLR: generate in multiples of 4 channels
-
- IBUFDS_GTE3_inst1 : IBUFDS_GTE3
- generic map (
- REFCLK_EN_TX_PATH => '0', -- Refer to Transceiver User Guide
- REFCLK_HROW_CK_SEL => "00", -- Refer to Transceiver User Guide
- REFCLK_ICNTL_RX => "00" -- Refer to Transceiver User Guide
- )
- port map (
- O => gtrefclk1_i, -- 1-bit output: Refer to Transceiver User Guide
- ODIV2 => open, -- 1-bit output: Refer to Transceiver User Guide
- CEB => '0', -- 1-bit input: Refer to Transceiver User Guide
- I => Qx_GTREFCLK_P(1), -- 1-bit input: Refer to Transceiver User Guide
- IB => Qx_GTREFCLK_N(1) -- 1-bit input: Refer to Transceiver User Guide
- );
-
- drpclk_in(i) <= (others => sysclk_in);
- gtrefclk0_in_sB(i) <= (others => gtrefclk1_i);
- --RX_FSM_RESET_DONE(i) <= RX_FSM_RESET_DONE_sB(i);
-
- u0 : MRODtransceiver_core
- PORT MAP (
- --gtwiz_userclk_tx_reset_in => gtwiz_userclk_tx_reset_in_sB(i downto i),
- --gtwiz_userclk_tx_srcclk_out => open,
- --gtwiz_userclk_tx_usrclk_out => txusrclk_sB(i*4+3 downto i*4),
- --gtwiz_userclk_tx_usrclk2_out => open,
- --gtwiz_userclk_tx_active_out => gtwiz_userclk_tx_active_out_sB(i downto i),
- gtwiz_userclk_tx_active_in => (others => '1'),
- gtwiz_userclk_rx_active_in => gtwiz_userclk_rx_active_in_sB(i downto i),
- gtwiz_reset_clk_freerun_in(0) => sysclk_in,
- gtwiz_reset_all_in => gtwiz_reset_all_in_sB(i downto i),
- gtwiz_reset_tx_pll_and_datapath_in => gtwiz_reset_tx_pll_and_datapath_in_sB(i downto i) or RESETslv,
- gtwiz_reset_tx_datapath_in => gtwiz_reset_tx_datapath_in_sB(i downto i),
- gtwiz_reset_rx_pll_and_datapath_in => gtwiz_reset_rx_pll_and_datapath_in_sB(i downto i),
- gtwiz_reset_rx_datapath_in => gtwiz_reset_rx_datapath_in_sB(i downto i),
- gtwiz_reset_rx_cdr_stable_out => gtwiz_reset_rx_cdr_stable_out_sB(i downto i),
- gtwiz_reset_tx_done_out => gtwiz_reset_tx_done_out_sB(i downto i),
- gtwiz_reset_rx_done_out => RX_FSM_RESET_DONE_sB(i downto i),
- gtwiz_userdata_tx_in => txdata_in_sB((128*(i+1))-1 downto (128 * (i))),
- gtwiz_userdata_rx_out => rxdata_out_sB((128*(i+1))-1 downto (128 * (i))),
- gtrefclk01_in(0) => gtrefclk1_i,
- qpll1outclk_out => open,
- qpll1outrefclk_out => open,
- drpclk_in => drpclk_in(i),
- gthrxn_in => gtrxn_in_sB,
- gthrxp_in => gtrxp_in_sB,
- gtrefclk0_in => gtrefclk0_in_sB(i),
- loopback_in => (loopback_in_s & loopback_in_s & loopback_in_s & loopback_in_s),-- "010010010010",
- rx8b10ben_in => (others => '1'),
- rxusrclk_in => rxusrclk_sB(i*4+3 downto i*4),
- rxusrclk2_in => rxusrclk_sB(i*4+3 downto i*4),
- tx8b10ben_in => (others => '1'),
- txctrl0_in => (others => '0'),
- txctrl1_in => (others => '0'),
- txctrl2_in => txctrl2_in_sB((32*(i+1))-1 downto 32*(i)),
- txusrclk_in => txusrclk_sB(i*4+3 downto i*4),
- txusrclk2_in => txusrclk_sB(i*4+3 downto i*4),
- gthtxn_out => gttxn_out_sB,
- gthtxp_out => gttxp_out_sB,
- gtpowergood_out => gtpowergood_out_sB,
- rxcdrlock_out => rxcdrlock_out_sB((4*(i+1))-1 downto 4*(i)),
- rxctrl0_out => rxctrl0_out_sB,
- rxctrl1_out => rxctrl1_out_sB,
- rxctrl2_out => rxctrl2_out_sB,
- rxctrl3_out => rxctrl3_out_sB,
- rxoutclk_out => rxoutclk_sB(i*4+3 downto i*4),
- rxpmaresetdone_out => rxpmaresetdone_out_sB((4*(i+1))-1 downto 4*(i)),
- txoutclk_out => txoutclk_sB(i*4+3 downto i*4),
- txpmaresetdone_out => txpmaresetdone_out_sB((4*(i+1))-1 downto 4*(i)),
- txprgdivresetdone_out => open
- );
-
- transceiver_vioB: vio_0_quad
- PORT MAP (
- clk => sysclk_in,
- probe_in0 => rxpmaresetdone_out_sB,--4
- probe_in1 => txpmaresetdone_out_sB,--4
- probe_in2 => gtpowergood_out_sB, --4
- probe_in3 => RX_FSM_RESET_DONE_sB, --1
- probe_in4 => gtwiz_reset_tx_done_out_sB, --1
- probe_in5 => gtwiz_reset_rx_cdr_stable_out_sB,--1
- probe_out0 => gtwiz_reset_rx_datapath_in_sB,--1
- probe_out1 => gtwiz_reset_rx_pll_and_datapath_in_sB,--1
- probe_out2 => gtwiz_reset_all_in_sB,--1
- probe_out3 => gtwiz_reset_tx_pll_and_datapath_in_sB,--1
- probe_out4 => gtwiz_reset_tx_datapath_in_sB,--1
- probe_out5 => gtwiz_userclk_tx_reset_in_sB,--1
- probe_out6 => gtwiz_userclk_rx_active_in_sB--1
- );
-
- transceiver_ilaB : ila_gth_quad
- PORT MAP (
- clk => rxusrclk_sB(0),
- probe0 => txdata_in_sB,
- probe1 => txctrl2_in_sB,
- probe2 => rxdata_out_sB,
- probe3 => rxctrl0_out_sB,
- probe4 => rxctrl1_out_sB,
- probe5 => rxctrl2_out_sB,
- probe6 => rxctrl3_out_sB
- );
-
- end generate g_quadsB; -- B-CHANNEL
- end generate genEP_1;
+ RxClk <= (others => clk50);
+ TxClk <= (others => clk50);
+
+ g0: if (W_ENDPOINT = 0) generate --
+ loopback <= prmap_app_control.MROD_EP0_TRXLOOPBACK;
+ end generate g0;
+
+ g1: if (W_ENDPOINT = 1) generate --
+ loopback <= prmap_app_control.MROD_EP1_TRXLOOPBACK;
+ end generate g1;
+
+ g2: for i in NUMCH-1 downto 0 generate
+ begin
+ txDvalid(i) <= '1' when (TxValid(i) = '1' and TxData(i)(32) = '0') else '0';
+ RxValid(i) <= txDvalid(i) when (loopback(i) = '1') else '0';
+ RxData(i) <= TxData(i)(31 downto 0) when (txDvalid(i) = '1') else x"04000000";
+ end generate g2;
+
+ g3: for i in NUMCH-1 downto 0 generate
+ begin
+ gttxn_out(i) <= '1';
+ gttxp_out(i) <= '0';
+ RX_CHxLocked(i) <= '1';
+ TX_CHxLocked(i) <= '1';
+ end generate g3;
end architecture a0 ; -- of Transceiver
diff --git a/sources/FelixMROD/Transceiver_Quad.vhd b/sources/FelixMROD/Transceiver_Quad.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..906092934bc1bddb2ee34a3f8b0f51486f732b97
--- /dev/null
+++ b/sources/FelixMROD/Transceiver_Quad.vhd
@@ -0,0 +1,621 @@
+--!-----------------------------------------------------------------------------
+--! @authors R. Habraken, T. Wijnen
+--! @company Radboud University Nijmegen
+--! @startdate 01-Feb-2019
+--! @version 1.0
+--! @project FELIX_MROD: MROD functionality implemented on a FELIX board.
+--!-----------------------------------------------------------------------------
+--! @brief
+--! Use a FELIX board to interface to GOL links coming from the MDT Chambers.
+--! Provides a new type of interface to possibly replace the MROD system.
+--!
+--!-----------------------------------------------------------------------------
+
+--!-----------------------------------------------------------------------------
+--! @object Entity design.Transceiver
+--! project FELIX_MROD
+--! modified Tue Jun 04 12:14:23 2019
+--!-----------------------------------------------------------------------------
+
+library ieee, work;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use work.felix_mrod_package.all;
+use work.centralRouter_package.all;
+--use work.FELIX_gbt_package.all;
+use work.pcie_package.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity Transceiver is
+ generic(
+ W_ENDPOINT : integer := 0;
+ NUMCH : integer := 2;
+ GBT_NUM : integer := 4);
+ port (
+ EnChan : in std_logic_vector(NUMCH-1 downto 0);
+ MReset : in std_logic;
+ QX_GTREFCLK_N : in std_logic_vector(4 downto 0);
+ QX_GTREFCLK_P : in std_logic_vector(4 downto 0);
+ RX_CHxLocked : out std_logic_vector(NUMCH-1 downto 0);
+ RX_CHxReset : in std_logic_vector(NUMCH-1 downto 0);
+ --RX_FSM_RESET_DONE : out std_logic_vector(NUMCH/4-1 downto 0);
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ RxClk : out std_logic_vector(NUMCH-1 downto 0);
+ RxData : out slv32_array(0 to NUMCH-1);
+ RxValid : out std_logic_vector(NUMCH-1 downto 0);
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ TRXloopback : in std_logic_vector(NUMCH-1 downto 0);
+ TX_CHxLocked : in std_logic_vector(NUMCH-1 downto 0);
+ TX_CHxReset : in std_logic_vector(NUMCH-1 downto 0);
+ TxClk : out std_logic_vector(NUMCH-1 downto 0);
+ TxData : in slv33_array(0 to NUMCH-1);
+ TxValid : in std_logic_vector(NUMCH-1 downto 0);
+ ------------------ Transmit Ports - pattern Generator Ports ----------------
+ --Txprbssel_in : in std_logic_vector(2 downto 0);
+ clk50 : in std_logic;
+ gtrxn_in : in std_logic_vector(NUMCH-1 downto 0);
+ gtrxp_in : in std_logic_vector(NUMCH-1 downto 0);
+ gttxn_out : out std_logic_vector(NUMCH-1 downto 0);
+ gttxp_out : out std_logic_vector(NUMCH-1 downto 0);
+ ------------------ 40 MHz system (DRP) clk
+ prmap_app_control : in register_map_control_type;
+ --register_map_control : in register_map_control_type;
+ sysclk_in : in std_logic
+ );
+
+end entity Transceiver;
+
+--!-----------------------------------------------------------------------------
+--! @object Architecture design.Transceiver.a0
+--! project FELIX_MROD
+--! modified Tue Jun 04 12:14:23 2019
+--!-----------------------------------------------------------------------------
+
+architecture a0 of Transceiver is
+
+--COMPONENT MRODtransceiver_core
+-- PORT (
+-- gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- gtwiz_userclk_tx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- gtwiz_userclk_tx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- gtwiz_userclk_tx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- gtwiz_userclk_tx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- gtwiz_userclk_rx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+-- gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
+-- gtrefclk01_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- qpll1outclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- qpll1outrefclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+-- drpclk_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- gthrxn_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- gthrxp_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- gtrefclk0_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- loopback_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+-- rx8b10ben_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- rxusrclk_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- rxusrclk2_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- tx8b10ben_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- txctrl0_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+-- txctrl1_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+-- txctrl2_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+-- gthtxn_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- gthtxp_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- gtpowergood_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- rxcdrlock_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- rxctrl0_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
+-- rxctrl1_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
+-- rxctrl2_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+-- rxctrl3_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+-- rxoutclk_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- txpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-- txprgdivresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+-- );
+--END COMPONENT;
+
+COMPONENT MRODtransceiver_core
+ PORT (
+ gtwiz_userclk_tx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_rx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+ gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
+ gtrefclk01_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ qpll1outclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ qpll1outrefclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ drpclk_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ gthrxn_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ gthrxp_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ gtrefclk0_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ loopback_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+ rx8b10ben_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ rxusrclk_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ rxusrclk2_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ tx8b10ben_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ txctrl0_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+ txctrl1_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+ txctrl2_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ txusrclk_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ txusrclk2_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ gthtxn_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+ gthtxp_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+ gtpowergood_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+ rxcdrlock_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+ rxctrl0_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
+ rxctrl1_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
+ rxctrl2_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ rxctrl3_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ rxoutclk_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+ rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+ txoutclk_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+ txpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+ txprgdivresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+ );
+END COMPONENT;
+
+
+COMPONENT vio_0_quad
+ PORT (
+ clk : IN STD_LOGIC;
+ probe_in0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ probe_in1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ probe_in2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ probe_in3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe_in4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe_in5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe_out3 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+ );
+END COMPONENT;
+
+COMPONENT ila_gth_quad
+
+PORT (
+ clk : IN STD_LOGIC;
+ probe0 : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+ probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ probe2 : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+ probe3 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+ probe4 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+ probe5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ probe6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
+);
+END COMPONENT ;
+
+signal RESETslv: std_logic_vector (0 downto 0);
+signal RX_FSM_RESET_DONE_sA,RX_FSM_RESET_DONE_sB: std_logic_vector(NUMCH/4-1 downto 0);
+--signal RXSLIDE_S: std_logic_vector(NUMCH - 1 downto 0);
+signal gtrefclk0_i, gtrefclk1_i, gtrefclk2_i : std_logic;
+signal loopback_in_s : std_logic_vector(2 downto 0);
+signal rxusrclk_sA, rxusrclk_sB : std_logic_vector(NUMCH-1 downto 0);
+signal rxoutclk_sA, rxoutclk_sB : std_logic_vector(NUMCH-1 downto 0);
+signal txusrclk_sA, txusrclk_sB : std_logic_vector(NUMCH-1 downto 0);
+signal txoutclk_sA, txoutclk_sB : std_logic_vector(NUMCH-1 downto 0);
+signal rxdata_out_sA, rxdata_out_sB : std_logic_vector((NUMCH*32)-1 downto 0);
+signal txdata_in_sA, txdata_in_sB : std_logic_vector((NUMCH*32)-1 downto 0);
+signal gtrxp_in_sA, gtrxn_in_sA, gttxp_out_sA, gttxn_out_sA : std_logic_vector(NUMCH-1 downto 0);
+signal gtrxp_in_sB, gtrxn_in_sB, gttxp_out_sB, gttxn_out_sB : std_logic_vector(NUMCH-1 downto 0);
+signal txctrl2_in_sA, txctrl2_in_sB : std_logic_vector((NUMCH*8)-1 downto 0);
+signal rxctrl0_out_sA, rxctrl0_out_sB : std_logic_vector((NUMCH*16)-1 downto 0);
+signal rxctrl1_out_sA, rxctrl1_out_sB : std_logic_vector((NUMCH*16)-1 downto 0);
+signal rxctrl2_out_sA, rxctrl2_out_sB : std_logic_vector((NUMCH*8)-1 downto 0);
+signal rxctrl3_out_sA, rxctrl3_out_sB : std_logic_vector((NUMCH*8)-1 downto 0);
+
+signal rxcdrlock_out_sA, rxcdrlock_out_sB : std_logic_vector(NUMCH-1 downto 0);
+
+--Monitor signals (connect to VIO)
+signal rxpmaresetdone_out_sA, rxpmaresetdone_out_sB : std_logic_vector(NUMCH-1 downto 0);
+signal txpmaresetdone_out_sA, txpmaresetdone_out_sB : std_logic_vector(NUMCH-1 downto 0);
+signal gtpowergood_out_sA, gtpowergood_out_sB : std_logic_vector(NUMCH-1 downto 0);
+signal gtwiz_reset_rx_done_out_sA : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_rx_done_out_sB : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_tx_done_out_sA : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_tx_done_out_sB : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_rx_cdr_stable_out_sA : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_rx_cdr_stable_out_sB : std_logic_vector(NUMCH/4-1 downto 0);
+
+--Resets, connected to VIO
+--signal gtwiz_reset_rx_datapath_in : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_rx_datapath_in_sA : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_rx_datapath_in_sB : std_logic_vector(NUMCH/4-1 downto 0);
+--signal gtwiz_reset_rx_pll_and_datapath_in : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_rx_pll_and_datapath_in_sA : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_rx_pll_and_datapath_in_sB : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_all_in : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_all_in_sA : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_all_in_sB : std_logic_vector(NUMCH/4-1 downto 0);
+--signal gtwiz_reset_tx_pll_and_datapath_in : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_tx_pll_and_datapath_in_sA : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_tx_pll_and_datapath_in_sB : std_logic_vector(NUMCH/4-1 downto 0);
+--signal gtwiz_reset_tx_datapath_in : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_tx_datapath_in_sA : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_reset_tx_datapath_in_sB : std_logic_vector(NUMCH/4-1 downto 0);
+--signal gtwiz_userclk_tx_reset_in : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_userclk_tx_reset_in_sA : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_userclk_tx_reset_in_sB : std_logic_vector(NUMCH/4-1 downto 0);
+--signal gtwiz_userclk_rx_active_in : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_userclk_rx_active_in_sA : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_userclk_rx_active_in_sB : std_logic_vector(NUMCH/4-1 downto 0);
+--signal gtwiz_userclk_tx_active_out : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_userclk_tx_active_out_sA : std_logic_vector(NUMCH/4-1 downto 0);
+signal gtwiz_userclk_tx_active_out_sB : std_logic_vector(NUMCH/4-1 downto 0);
+
+type drpclk_in_type is array (NUMCH/4-1 downto 0) of std_logic_vector(3 downto 0);
+signal drpclk_in, gtrefclk0_in_sA, gtrefclk0_in_sB : drpclk_in_type;
+signal cesyncRX_s, clrsyncRX_s : std_logic_vector(NUMCH-1 downto 0);
+signal cesyncTX_s, clrsyncTX_s : std_logic_vector(NUMCH-1 downto 0);
+
+--signal rxdata_out : slv32_array(0 to NUMCH-1);
+signal rxcharisk_out : slv04_array(0 to NUMCH -1);
+signal txdata_in_bufA, txdata_in_bufB : slv32_array(0 to NUMCH-1);
+signal txcharisk_in : slv04_array(0 to NUMCH-1);
+signal RXUSRCLK_OUT : std_logic_vector(NUMCH-1 downto 0);
+signal TXUSRCLK_OUT : std_logic_vector(NUMCH-1 downto 0);
+
+begin
+
+ loopback_in_s <= prmap_app_control.GTH_LOOPBACK_CONTROL;
+ RESETslv <= (others => MReset);
+
+-- generate once per PCIE end point
+ genEP_0: if (W_ENDPOINT = 0) generate
+
+-- generate once per channel
+ g_CHx_A: for i in 0 to (NUMCH - 1) generate
+ RX_CHxLocked(i) <= rxcdrlock_out_sA(i); --'1';
+
+ gttxp_out(i) <= gttxp_out_sA(i);
+ gttxn_out(i) <= gttxn_out_sA(i);
+ gtrxp_in_sA(i) <= gtrxp_in(i);
+ gtrxn_in_sA(i) <= gtrxn_in(i);
+
+ --RX data, ctrl and clk
+ RxData(i) <= rxdata_out_sA(i*32+31 downto i*32);
+ rxcharisk_out(i) <= rxctrl0_out_sA(i*16+3 downto i*16);
+ RxValid(i) <= '1' when (rxcharisk_out(i) = "0000") else '0';
+ RxClk(i) <= rxusrclk_sA(i);
+
+ -- EP 0: TRX data, ctrl and clk
+ txdata_in_bufA(i) <= TxData(31 downto 0)(i);
+ txdata_in_sA(i*32+31 downto i*32) <= txdata_in_bufA(i);
+ txcharisk_in(i) <= (others => TxData(i)(32) );
+ txctrl2_in_sA(i*8+3 downto i*8) <= txcharisk_in(i);
+ TxClk(i) <= txusrclk_sA(i);
+
+ -- Rx and Tx clk buffers
+ BUFG_GT_RXinst: BUFG_GT port map(
+ O => rxusrclk_sA(i),
+ CE => cesyncRX_s(i),
+ CEMASK => '1',
+ CLR => clrsyncRX_s(i),
+ CLRMASK => '1',
+ DIV => "000",
+ I => rxoutclk_sA(i)
+ );
+
+ BUFG_GT_SYNC_RXinst: BUFG_GT_SYNC port map(
+ CESYNC => cesyncRX_s(i),
+ CLRSYNC => clrsyncRX_s(i),
+ CLK => rxoutclk_sA(i),
+ CE => '1',
+ CLR => '0'
+ );
+
+ BUFG_GT_TXinst: BUFG_GT port map(
+ O => txusrclk_sA(i),
+ CE => cesyncTX_s(i),
+ CEMASK => '1',
+ CLR => clrsyncTX_s(i),
+ CLRMASK => '1',
+ DIV => "000",
+ I => txoutclk_sA(i)
+ );
+
+ BUFG_GT_SYNC_TXinst: BUFG_GT_SYNC port map(
+ CESYNC => cesyncTX_s(i),
+ CLRSYNC => clrsyncTX_s(i),
+ CLK => txoutclk_sA(i),
+ CE => '1',
+ CLR => '0'
+ );
+ end generate g_CHx_A;
+
+--gen XCVR CoreA: if (W_ENDPOINT = 0) generate
+g_quadsA: for i in 0 to (NUMCH/4-1) generate -- channel A LOWER SLR generate in multiples of 4 channels
+
+ -- RefClk
+ IBUFDS_GTE3_inst0 : IBUFDS_GTE3
+ generic map (
+ REFCLK_EN_TX_PATH => '0', -- Refer to Transceiver User Guide
+ REFCLK_HROW_CK_SEL => "00", -- Refer to Transceiver User Guide
+ REFCLK_ICNTL_RX => "00" -- Refer to Transceiver User Guide
+ )
+ port map (
+ O => gtrefclk0_i, -- 1-bit output: Refer to Transceiver User Guide
+ ODIV2 => open, -- 1-bit output: Refer to Transceiver User Guide
+ CEB => '0', -- 1-bit input: Refer to Transceiver User Guide
+ I => Qx_GTREFCLK_P(0), -- 1-bit input: Refer to Transceiver User Guide
+ IB => Qx_GTREFCLK_N(0) -- 1-bit input: Refer to Transceiver User Guide
+ );
+
+ drpclk_in(i) <= (others => sysclk_in);
+ gtrefclk0_in_sA(i) <= (others => gtrefclk0_i);
+ --RX_FSM_RESET_DONE(i) <= RX_FSM_RESET_DONE_sA(i);
+
+ u0 : MRODtransceiver_core
+ PORT MAP (
+ gtwiz_userclk_tx_active_in => (others => '1'),
+ gtwiz_userclk_rx_active_in => gtwiz_userclk_rx_active_in_sA(i downto i),
+ gtwiz_reset_clk_freerun_in(0) => sysclk_in,
+ gtwiz_reset_all_in => gtwiz_reset_all_in_sA(i downto i),
+ gtwiz_reset_tx_pll_and_datapath_in => gtwiz_reset_tx_pll_and_datapath_in_sA(i downto i) or RESETslv,
+ gtwiz_reset_tx_datapath_in => gtwiz_reset_tx_datapath_in_sA(i downto i),
+ gtwiz_reset_rx_pll_and_datapath_in => gtwiz_reset_rx_pll_and_datapath_in_sA(i downto i),
+ gtwiz_reset_rx_datapath_in => gtwiz_reset_rx_datapath_in_sA(i downto i),
+ gtwiz_reset_rx_cdr_stable_out => gtwiz_reset_rx_cdr_stable_out_sA(i downto i),
+ gtwiz_reset_tx_done_out => gtwiz_reset_tx_done_out_sA(i downto i),
+ gtwiz_reset_rx_done_out => RX_FSM_RESET_DONE_sA(i downto i),
+ gtwiz_userdata_tx_in => txdata_in_sA((128*(i+1))-1 downto (128 * (i))),
+ gtwiz_userdata_rx_out => rxdata_out_sA((128*(i+1))-1 downto (128 * (i))),
+ gtrefclk01_in(0) => gtrefclk0_i,
+ qpll1outclk_out => open,
+ qpll1outrefclk_out => open,
+ drpclk_in => drpclk_in(i),
+ gthrxn_in => gtrxn_in_sA,
+ gthrxp_in => gtrxp_in_sA,
+ gtrefclk0_in => gtrefclk0_in_sA(i),
+ loopback_in => (loopback_in_s & loopback_in_s & loopback_in_s & loopback_in_s),-- "1111",
+ rx8b10ben_in => (others => '1'),
+ rxusrclk_in => rxusrclk_sA(i*4+3 downto i*4),
+ rxusrclk2_in => rxusrclk_sA(i*4+3 downto i*4),
+ tx8b10ben_in => (others => '1'),
+ txctrl0_in => (others => '0'),
+ txctrl1_in => (others => '0'),
+ txctrl2_in => txctrl2_in_sA((32*(i+1))-1 downto 32*(i)),
+ txusrclk_in => txusrclk_sA(i*4+3 downto i*4),
+ txusrclk2_in => txusrclk_sA(i*4+3 downto i*4),
+ gthtxn_out => gttxn_out_sA,
+ gthtxp_out => gttxp_out_sA,
+ gtpowergood_out => gtpowergood_out_sA,
+ rxcdrlock_out => rxcdrlock_out_sA((4*(i+1))-1 downto 4*(i)),
+ rxctrl0_out => rxctrl0_out_sA,
+ rxctrl1_out => rxctrl1_out_sA,
+ rxctrl2_out => rxctrl2_out_sA,
+ rxctrl3_out => rxctrl3_out_sA,
+ rxoutclk_out => rxoutclk_sA(i*4+3 downto i*4),
+ rxpmaresetdone_out => rxpmaresetdone_out_sA((4*(i+1))-1 downto 4*(i)),
+ txoutclk_out => txoutclk_sA(i*4+3 downto i*4),
+ txpmaresetdone_out => txpmaresetdone_out_sA((4*(i+1))-1 downto 4*(i)),
+ txprgdivresetdone_out => open
+ );
+
+ transceiver_vioA: vio_0_quad
+ PORT MAP (
+ clk => sysclk_in,
+ probe_in0 => rxpmaresetdone_out_sA,--4
+ probe_in1 => txpmaresetdone_out_sA,--4
+ probe_in2 => gtpowergood_out_sA, --4
+ probe_in3 => RX_FSM_RESET_DONE_sA, --1
+ probe_in4 => gtwiz_reset_tx_done_out_sA, --1
+ probe_in5 => gtwiz_reset_rx_cdr_stable_out_sA,--1
+ probe_out0 => gtwiz_reset_rx_datapath_in_sA,--1
+ probe_out1 => gtwiz_reset_rx_pll_and_datapath_in_sA,--1
+ probe_out2 => gtwiz_reset_all_in_sA,--1
+ probe_out3 => gtwiz_reset_tx_pll_and_datapath_in_sA,--1
+ probe_out4 => gtwiz_reset_tx_datapath_in_sA,--1
+ probe_out5 => gtwiz_userclk_tx_reset_in_sA,--1
+ probe_out6 => gtwiz_userclk_rx_active_in_sA--1 Set to 1 in VIO.
+ );
+
+ transceiver_ilaA : ila_gth_quad
+ PORT MAP (
+ clk => rxusrclk_sA(0),
+ probe0 => txdata_in_sA,
+ probe1 => txctrl2_in_sA,
+ probe2 => rxdata_out_sA,
+ probe3 => rxctrl0_out_sA,
+ probe4 => rxctrl1_out_sA,
+ probe5 => rxctrl2_out_sA,
+ probe6 => rxctrl3_out_sA
+ );
+
+ end generate g_quadsA; --A channel
+ end generate genEP_0;
+
+
+ genEP_1: if (W_ENDPOINT = 1) generate
+
+-- generate once per channel
+ g_CHx_B: for i in 0 to (NUMCH - 1) generate
+ RX_CHxLocked(i) <= rxcdrlock_out_sB(i); --'1';
+
+ gttxp_out(i) <= gttxp_out_sB(i);
+ gttxn_out(i) <= gttxn_out_sB(i);
+ gtrxp_in_sB(i) <= gtrxp_in(i);
+ gtrxn_in_sB(i) <= gtrxn_in(i);
+
+ --RX data, ctrl and clk
+ RxData(i) <= rxdata_out_sB(i*32+31 downto i*32);
+ rxcharisk_out(i) <= rxctrl0_out_sB(i*16+3 downto i*16);
+ RxValid(i) <= '1' when (rxcharisk_out(i) = "0000") else '0';
+
+ RxClk(i) <= rxusrclk_sB(i);
+
+ --EP 1: TRX data, ctrl and clk
+ txdata_in_bufB(i) <= TxData(31 downto 0)(i);
+ txdata_in_sB(i*32+31 downto i*32) <= txdata_in_bufB(i);
+ txcharisk_in(i) <= (others => TxData(i)(32) );
+ txctrl2_in_sB(i*8+3 downto i*8) <= txcharisk_in(i);
+ TxClk(i) <= txusrclk_sB(i);
+
+ -- Rx and Tx clk buffers
+ BUFG_GT_RXinst: BUFG_GT port map(
+ O => rxusrclk_sB(i),
+ CE => cesyncRX_s(i),
+ CEMASK => '1',
+ CLR => clrsyncRX_s(i),
+ CLRMASK => '1',
+ DIV => "000",
+ I => rxoutclk_sB(i)
+ );
+
+ BUFG_GT_SYNC_RXinst: BUFG_GT_SYNC port map(
+ CESYNC => cesyncRX_s(i),
+ CLRSYNC => clrsyncRX_s(i),
+ CLK => rxoutclk_sB(i),
+ CE => '1',
+ CLR => '0'
+ );
+
+ BUFG_GT_TXinst: BUFG_GT port map(
+ O => txusrclk_sB(i),
+ CE => cesyncTX_s(i),
+ CEMASK => '1',
+ CLR => clrsyncTX_s(i),
+ CLRMASK => '1',
+ DIV => "000",
+ I => txoutclk_sB(i)
+ );
+
+ BUFG_GT_SYNC_TXinst: BUFG_GT_SYNC port map(
+ CESYNC => cesyncTX_s(i),
+ CLRSYNC => clrsyncTX_s(i),
+ CLK => txoutclk_sB(i),
+ CE => '1',
+ CLR => '0'
+ );
+ end generate g_CHx_B;
+
+
+--gen XCVR_CoreB: if (W_ENDPOINT = 1) generate
+g_quadsB: for i in 0 to (NUMCH/4-1) generate -- channel B UPPER SLR: generate in multiples of 4 channels
+
+ IBUFDS_GTE3_inst1 : IBUFDS_GTE3
+ generic map (
+ REFCLK_EN_TX_PATH => '0', -- Refer to Transceiver User Guide
+ REFCLK_HROW_CK_SEL => "00", -- Refer to Transceiver User Guide
+ REFCLK_ICNTL_RX => "00" -- Refer to Transceiver User Guide
+ )
+ port map (
+ O => gtrefclk1_i, -- 1-bit output: Refer to Transceiver User Guide
+ ODIV2 => open, -- 1-bit output: Refer to Transceiver User Guide
+ CEB => '0', -- 1-bit input: Refer to Transceiver User Guide
+ I => Qx_GTREFCLK_P(1), -- 1-bit input: Refer to Transceiver User Guide
+ IB => Qx_GTREFCLK_N(1) -- 1-bit input: Refer to Transceiver User Guide
+ );
+
+ drpclk_in(i) <= (others => sysclk_in);
+ gtrefclk0_in_sB(i) <= (others => gtrefclk1_i);
+ --RX_FSM_RESET_DONE(i) <= RX_FSM_RESET_DONE_sB(i);
+
+ u0 : MRODtransceiver_core
+ PORT MAP (
+ --gtwiz_userclk_tx_reset_in => gtwiz_userclk_tx_reset_in_sB(i downto i),
+ --gtwiz_userclk_tx_srcclk_out => open,
+ --gtwiz_userclk_tx_usrclk_out => txusrclk_sB(i*4+3 downto i*4),
+ --gtwiz_userclk_tx_usrclk2_out => open,
+ --gtwiz_userclk_tx_active_out => gtwiz_userclk_tx_active_out_sB(i downto i),
+ gtwiz_userclk_tx_active_in => (others => '1'),
+ gtwiz_userclk_rx_active_in => gtwiz_userclk_rx_active_in_sB(i downto i),
+ gtwiz_reset_clk_freerun_in(0) => sysclk_in,
+ gtwiz_reset_all_in => gtwiz_reset_all_in_sB(i downto i),
+ gtwiz_reset_tx_pll_and_datapath_in => gtwiz_reset_tx_pll_and_datapath_in_sB(i downto i) or RESETslv,
+ gtwiz_reset_tx_datapath_in => gtwiz_reset_tx_datapath_in_sB(i downto i),
+ gtwiz_reset_rx_pll_and_datapath_in => gtwiz_reset_rx_pll_and_datapath_in_sB(i downto i),
+ gtwiz_reset_rx_datapath_in => gtwiz_reset_rx_datapath_in_sB(i downto i),
+ gtwiz_reset_rx_cdr_stable_out => gtwiz_reset_rx_cdr_stable_out_sB(i downto i),
+ gtwiz_reset_tx_done_out => gtwiz_reset_tx_done_out_sB(i downto i),
+ gtwiz_reset_rx_done_out => RX_FSM_RESET_DONE_sB(i downto i),
+ gtwiz_userdata_tx_in => txdata_in_sB((128*(i+1))-1 downto (128 * (i))),
+ gtwiz_userdata_rx_out => rxdata_out_sB((128*(i+1))-1 downto (128 * (i))),
+ gtrefclk01_in(0) => gtrefclk1_i,
+ qpll1outclk_out => open,
+ qpll1outrefclk_out => open,
+ drpclk_in => drpclk_in(i),
+ gthrxn_in => gtrxn_in_sB,
+ gthrxp_in => gtrxp_in_sB,
+ gtrefclk0_in => gtrefclk0_in_sB(i),
+ loopback_in => (loopback_in_s & loopback_in_s & loopback_in_s & loopback_in_s),-- "010010010010",
+ rx8b10ben_in => (others => '1'),
+ rxusrclk_in => rxusrclk_sB(i*4+3 downto i*4),
+ rxusrclk2_in => rxusrclk_sB(i*4+3 downto i*4),
+ tx8b10ben_in => (others => '1'),
+ txctrl0_in => (others => '0'),
+ txctrl1_in => (others => '0'),
+ txctrl2_in => txctrl2_in_sB((32*(i+1))-1 downto 32*(i)),
+ txusrclk_in => txusrclk_sB(i*4+3 downto i*4),
+ txusrclk2_in => txusrclk_sB(i*4+3 downto i*4),
+ gthtxn_out => gttxn_out_sB,
+ gthtxp_out => gttxp_out_sB,
+ gtpowergood_out => gtpowergood_out_sB,
+ rxcdrlock_out => rxcdrlock_out_sB((4*(i+1))-1 downto 4*(i)),
+ rxctrl0_out => rxctrl0_out_sB,
+ rxctrl1_out => rxctrl1_out_sB,
+ rxctrl2_out => rxctrl2_out_sB,
+ rxctrl3_out => rxctrl3_out_sB,
+ rxoutclk_out => rxoutclk_sB(i*4+3 downto i*4),
+ rxpmaresetdone_out => rxpmaresetdone_out_sB((4*(i+1))-1 downto 4*(i)),
+ txoutclk_out => txoutclk_sB(i*4+3 downto i*4),
+ txpmaresetdone_out => txpmaresetdone_out_sB((4*(i+1))-1 downto 4*(i)),
+ txprgdivresetdone_out => open
+ );
+
+ transceiver_vioB: vio_0_quad
+ PORT MAP (
+ clk => sysclk_in,
+ probe_in0 => rxpmaresetdone_out_sB,--4
+ probe_in1 => txpmaresetdone_out_sB,--4
+ probe_in2 => gtpowergood_out_sB, --4
+ probe_in3 => RX_FSM_RESET_DONE_sB, --1
+ probe_in4 => gtwiz_reset_tx_done_out_sB, --1
+ probe_in5 => gtwiz_reset_rx_cdr_stable_out_sB,--1
+ probe_out0 => gtwiz_reset_rx_datapath_in_sB,--1
+ probe_out1 => gtwiz_reset_rx_pll_and_datapath_in_sB,--1
+ probe_out2 => gtwiz_reset_all_in_sB,--1
+ probe_out3 => gtwiz_reset_tx_pll_and_datapath_in_sB,--1
+ probe_out4 => gtwiz_reset_tx_datapath_in_sB,--1
+ probe_out5 => gtwiz_userclk_tx_reset_in_sB,--1
+ probe_out6 => gtwiz_userclk_rx_active_in_sB--1
+ );
+
+ transceiver_ilaB : ila_gth_quad
+ PORT MAP (
+ clk => rxusrclk_sB(0),
+ probe0 => txdata_in_sB,
+ probe1 => txctrl2_in_sB,
+ probe2 => rxdata_out_sB,
+ probe3 => rxctrl0_out_sB,
+ probe4 => rxctrl1_out_sB,
+ probe5 => rxctrl2_out_sB,
+ probe6 => rxctrl3_out_sB
+ );
+
+ end generate g_quadsB; -- B-CHANNEL
+ end generate genEP_1;
+
+end architecture a0 ; -- of Transceiver
+
diff --git a/sources/FelixMROD/TrxBuffer.vhd b/sources/FelixMROD/TrxBuffer.vhd
index fa2bb0f977e05f62ffc3befea3466718a4573205..54c8128cdc6aa86a60d6b23cca63159d05e6f8dc 100644
--- a/sources/FelixMROD/TrxBuffer.vhd
+++ b/sources/FelixMROD/TrxBuffer.vhd
@@ -14,7 +14,7 @@
--!-----------------------------------------------------------------------------
--! @object Entity design.TrxBuffer
--! =project FELIX_MROD
---! @modified Tue Jan 21 22:44:30 2020
+--! @modified Wed Apr 01 23:14:18 2020
--!-----------------------------------------------------------------------------
library ieee, work;
@@ -41,21 +41,20 @@ entity TrxBuffer is
RxValid : out std_logic_vector(NUMCH-1 downto 0);
TXfrGTH_N : out std_logic_vector(NUMCH-1 downto 0);
TXfrGTH_P : out std_logic_vector(NUMCH-1 downto 0);
+ TrxMonitor : out regs_trx_monitor;
TxClk : out std_logic_vector(NUMCH-1 downto 0);
TxData : in slv33_array(0 to NUMCH-1);
TxValid : in std_logic_vector(NUMCH-1 downto 0);
clk40 : in std_logic;
clk50 : in std_logic;
prmap_app_control : in register_map_control_type;
- prmap_mrodEP0_mon : out regmap_mrodEP0_monitor_type;
- prmap_mrodEP1_mon : out regmap_mrodEP1_monitor_type;
sys_reset_n : in std_logic);
end entity TrxBuffer;
--!-----------------------------------------------------------------------------
--! @object Architecture design.TrxBuffer.a0
--! =project FELIX_MROD
---! @modified Tue Jan 21 22:44:30 2020
+--! @modified Wed Apr 01 23:14:18 2020
--!-----------------------------------------------------------------------------
architecture a0 of TrxBuffer is
@@ -86,14 +85,13 @@ begin
TXCVR_ResetAll => TXCVR_ResetAll,
TX_CHxLocked => TX_CHxLocked,
TX_CHxReset => TX_CHxReset,
+ TrxMonitor => TrxMonitor,
clk40 => clk40,
clk50 => clk50,
prmap_app_control => prmap_app_control,
- prmap_mrodEP0_mon => prmap_mrodEP0_mon,
- prmap_mrodEP1_mon => prmap_mrodEP1_mon,
sys_reset_n => sys_reset_n);
- u1: entity work.TransceiverGen1CH(a0)
+ u1: entity work.Transceiver(a0)
generic map(
GBT_NUM => GBT_NUM,
NUMCH => NUMCH,
diff --git a/sources/FelixMROD/TrxBuffer-dum.vhd b/sources/FelixMROD/TrxBuffer_1CH.vhd
similarity index 92%
rename from sources/FelixMROD/TrxBuffer-dum.vhd
rename to sources/FelixMROD/TrxBuffer_1CH.vhd
index ca3bfddf41426952b5f9d17e11e8d795bb14f4d7..513685beb96d64c9955d4e2d194fb22cb79d3e3e 100644
--- a/sources/FelixMROD/TrxBuffer-dum.vhd
+++ b/sources/FelixMROD/TrxBuffer_1CH.vhd
@@ -12,7 +12,7 @@
--!-----------------------------------------------------------------------------
--!-----------------------------------------------------------------------------
---! @object Entity design.TrxBuffer
+--! @object Entity design.TrxBuffer_1CH
--! =project FELIX_MROD
--! @modified Tue Jan 21 22:44:30 2020
--!-----------------------------------------------------------------------------
@@ -26,7 +26,7 @@ use work.centralRouter_package.all;
use work.FELIX_gbt_package.all;
use work.pcie_package.all;
-entity TrxBuffer is
+entity TrxBuffer_1CH is
generic(
GBT_NUM : integer := 4;
NUMCH : integer := 4;
@@ -50,15 +50,15 @@ entity TrxBuffer is
prmap_mrodEP0_mon : out regmap_mrodEP0_monitor_type;
prmap_mrodEP1_mon : out regmap_mrodEP1_monitor_type;
sys_reset_n : in std_logic);
-end entity TrxBuffer;
+end entity TrxBuffer_1CH;
--!-----------------------------------------------------------------------------
---! @object Architecture design.TrxBuffer.a0
+--! @object Architecture design.TrxBuffer_1CH.a0
--! =project FELIX_MROD
--! @modified Tue Jan 21 22:44:30 2020
--!-----------------------------------------------------------------------------
-architecture a0 of TrxBuffer is
+architecture a0 of TrxBuffer_1CH is
signal MReset : std_logic;
signal RX_CHxReset : std_logic_vector(NUMCH-1 downto 0);
@@ -93,7 +93,7 @@ begin
prmap_mrodEP1_mon => prmap_mrodEP1_mon,
sys_reset_n => sys_reset_n);
- u1: entity work.Transceiver(a0)
+ u1: entity work.TransceiverGen1CH(a0)
generic map(
GBT_NUM => GBT_NUM,
NUMCH => NUMCH,
@@ -124,5 +124,5 @@ begin
prmap_app_control => prmap_app_control,
sysclk_in => clk50);
-end architecture a0 ; -- of TrxBuffer
+end architecture a0 ; -- of TrxBuffer_1CH
diff --git a/sources/FelixMROD/TxDriver.vhd b/sources/FelixMROD/TxDriver.vhd
index 3d452dd051d2ea40c03e3b4eb9c22e1ef9732fa8..cd2d70a4a6923b30db9c5bf456a7cf31a787ead5 100644
--- a/sources/FelixMROD/TxDriver.vhd
+++ b/sources/FelixMROD/TxDriver.vhd
@@ -14,7 +14,7 @@
--!-----------------------------------------------------------------------------
--! @object Entity design.TxDriver
--! =project FELIX_MROD
---! @modified Tue Jan 21 17:41:18 2020
+--! @modified Fri Mar 13 16:10:27 2020
--!-----------------------------------------------------------------------------
library ieee, work;
@@ -45,7 +45,7 @@ end entity TxDriver;
--!-----------------------------------------------------------------------------
--! @object Architecture design.TxDriver.a0
--! =project FELIX_MROD
---! @modified Tue Jan 21 17:41:18 2020
+--! @modified Fri Mar 13 16:10:27 2020
--!-----------------------------------------------------------------------------
@@ -123,8 +123,12 @@ begin
dcnt <= dcnt + "00001"; -- count words
elsif (EnaTxSimpleCnt = '1') then
QValid <= '1'; -- word valid, set pattern
- data <= '0' & idcode & "000" & std_logic_vector(dcnt)
- & std_logic_vector(ccnt) & std_logic_vector(ccnt) & "000" & std_logic_vector(dcnt);
+ if (idcode = x"D0") then
+ data <= '0' & idcode & x"000000";
+ else
+ data <= '0' & idcode & "000" & std_logic_vector(dcnt)
+ & std_logic_vector(ccnt) & std_logic_vector(ccnt) & "000" & std_logic_vector(dcnt);
+ end if;
dcnt <= dcnt + "00001"; -- count words
idcode <= x"04"; -- next idcode
else
diff --git a/sources/FelixMROD/felix_mrod_package.vhd b/sources/FelixMROD/felix_mrod_package.vhd
index babf103e68695ee036c9f7f18019493c0f45dd30..c547671b75e43ad01f2b72d9e6a4d5432098e60d 100644
--- a/sources/FelixMROD/felix_mrod_package.vhd
+++ b/sources/FelixMROD/felix_mrod_package.vhd
@@ -25,6 +25,15 @@ package felix_mrod_package is
type slv33_array is array (natural range <>) of std_logic_vector(32 downto 0);
type slv36_array is array (natural range <>) of std_logic_vector(35 downto 0);
+ type regs_csm_monitor is record
+ CSMH_EMPTY : std_logic_vector(23 downto 0); -- CSM Handler FIFO Empty 23-0
+ CSMH_FULL : std_logic_vector(23 downto 0); -- CSM Handler FIFO Full 23-0
+ end record;
+ type regs_trx_monitor is record
+ RXLOCKED : std_logic_vector(23 downto 0); -- Receiver Locked monitor 23-0
+ TXLOCKED : std_logic_vector(23 downto 0); -- Transmitter Locked monitor 23-0
+ end record;
+
constant SLV32ZERO : std_logic_vector(31 downto 0) := x"00000000";
constant SLV36ZERO : std_logic_vector(35 downto 0) := x"000000000";
constant SLV33ZERO : std_logic_vector(32 downto 0) := '0' & x"00000000";
diff --git a/sources/FelixMROD/felix_mrod_top.vhd b/sources/FelixMROD/felix_mrod_top.vhd
index 437c84ad2baf31a67f8a5bb1102f8b7eaaa12c36..1f45d49cf4e8b060e4b932579c6471aae1495158 100644
--- a/sources/FelixMROD/felix_mrod_top.vhd
+++ b/sources/FelixMROD/felix_mrod_top.vhd
@@ -14,7 +14,7 @@
--!-----------------------------------------------------------------------------
--! @object Entity design.felix_mrod_top
--! =project FELIX_MROD
---! @modified Fri Jan 31 16:10:06 2020
+--! @modified Wed Apr 01 23:19:08 2020
--!-----------------------------------------------------------------------------
library ieee, work;
@@ -29,7 +29,7 @@ use work.pcie_package.all;
entity felix_mrod_top is
generic(
NUMBER_OF_INTERRUPTS : integer := 8;
- NUMBER_OF_DESCRIPTORS : integer := 8;
+ NUMBER_OF_DESCRIPTORS : integer := 2;
OPTO_TRX : integer := 4;
APP_CLK_FREQ : integer := 200;
GBT_NUM : integer := 4; -- number of GBT channels
@@ -52,7 +52,7 @@ entity felix_mrod_top is
useToFrontendGBTdataEmulator : boolean := false;
useToHostGBTdataEmulator : boolean := false;
TTC_test_mode : boolean := false;
- CREnableFromHost : boolean := false;
+ CREnableFromHost : boolean := true;
ENDPOINTS : integer := 2;
FIRMWARE_MODE : integer := 1;
BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE";
@@ -68,6 +68,9 @@ entity felix_mrod_top is
GENERATE_FEI4B : boolean := false;
GENERATE_TRUNCATION_MECHANISM : boolean := false;
GENERATE_FM_WRAP : boolean := false;
+ BLOCKSIZE : integer := 1024;
+ CHUNK_TRAILER_32B : boolean := false;
+ SUPER_CHUNK_FACTOR : integer := 1;
wideMode : boolean := false;
EnableFrHo_Egroup0Eproc2_HDLC : boolean := false;
EnableFrHo_Egroup0Eproc2_8b10b : boolean := false;
@@ -209,7 +212,7 @@ end entity felix_mrod_top;
--!-----------------------------------------------------------------------------
--! @object Architecture design.felix_mrod_top.a0
--! =project FELIX_MROD
---! @modified Fri Jan 31 16:10:06 2020
+--! @modified Wed Apr 01 23:19:08 2020
--!-----------------------------------------------------------------------------
architecture a0 of felix_mrod_top is
@@ -288,12 +291,16 @@ architecture a0 of felix_mrod_top is
signal u21_TxClk : std_logic_vector(NUMCH-1 downto 0);
signal u11_TxClk : std_logic_vector(NUMCH-1 downto 0);
signal BUSY_INTERRUPT : std_logic;
- signal prmap_mrodEP0_mon : regmap_mrodEP0_monitor_type;
- signal prmap_mrodEP1_mon : regmap_mrodEP1_monitor_type;
signal u11_RxClk : std_logic_vector(NUMCH-1 downto 0);
signal u21_RxClk : std_logic_vector(NUMCH-1 downto 0);
+ signal MasterBusy : std_logic;
+ signal Trx0Monitor : regs_trx_monitor;
+ signal Trx1Monitor : regs_trx_monitor;
+ signal CSM0Monitor : regs_csm_monitor;
+ signal CSM1Monitor : regs_csm_monitor;
begin
+ BUSY_OUT <= MasterBusy;
u11: entity work.TrxBuffer(a0)
generic map(
@@ -310,14 +317,13 @@ begin
RxValid => u11_RxValid,
TXfrGTH_N => u11_TX_N,
TXfrGTH_P => u11_TX_P,
+ TrxMonitor => Trx0Monitor,
TxClk => u11_TxClk,
TxData => u12_TxData,
TxValid => u12_TxValid,
clk40 => clk40,
clk50 => clk50,
prmap_app_control => prmap_app_control,
- prmap_mrodEP0_mon => prmap_mrodEP0_mon,
- prmap_mrodEP1_mon => open,
sys_reset_n => sys_reset_n);
u21: entity work.TrxBuffer(a0)
@@ -335,14 +341,13 @@ begin
RxValid => u21_RxValid,
TXfrGTH_N => u21_TX_N,
TXfrGTH_P => u21_TX_P,
+ TrxMonitor => Trx1Monitor,
TxClk => u21_TxClk,
TxData => u22_TxData,
TxValid => u22_TxValid,
clk40 => clk40,
clk50 => clk50,
prmap_app_control => prmap_app_control,
- prmap_mrodEP0_mon => open,
- prmap_mrodEP1_mon => prmap_mrodEP1_mon,
sys_reset_n => sys_reset_n);
u12: entity work.CSMHandler(a0)
@@ -350,6 +355,7 @@ begin
NUMCH => NUMCH,
W_ENDPOINT => 0)
port map(
+ CSMMonitor => CSM0Monitor,
ChBusy => u13_ChBusy,
ChData => u12_ChData,
ChValid => u12_ChValid,
@@ -369,8 +375,6 @@ begin
fhFifoRE => u12_fhFifoRE,
fhFifoValid => u13_fhFifoValid,
prmap_app_control => prmap_app_control,
- prmap_mrodEP0_mon => prmap_mrodEP0_mon,
- prmap_mrodEP1_mon => open,
sys_reset_n => sys_reset_n);
u22: entity work.CSMHandler(a0)
@@ -378,6 +382,7 @@ begin
NUMCH => NUMCH,
W_ENDPOINT => 1)
port map(
+ CSMMonitor => CSM1Monitor,
ChBusy => u23_ChBusy,
ChData => u22_ChData,
ChValid => u22_ChValid,
@@ -397,8 +402,6 @@ begin
fhFifoRE => u22_fhFifoRE,
fhFifoValid => u23_fhFifoValid,
prmap_app_control => prmap_app_control,
- prmap_mrodEP0_mon => open,
- prmap_mrodEP1_mon => prmap_mrodEP1_mon,
sys_reset_n => sys_reset_n);
u31: entity work.Busy_TTC(a0)
@@ -408,7 +411,6 @@ begin
generateTTCemu => generateTTCemu)
port map(
BUSY_INTERRUPT => BUSY_INTERRUPT,
- BUSY_OUT => BUSY_OUT,
CDRlocked => CDRlocked,
CLK_TTC_N => CLK_TTC_N,
CLK_TTC_P => CLK_TTC_P,
@@ -420,6 +422,7 @@ begin
DATA_TTC_P => DATA_TTC_P,
LOL_ADN => LOL_ADN,
LOS_ADN => LOS_ADN,
+ MasterBusy => MasterBusy,
TTC_ToHost_Data => TTC_ToHost_Data,
TTCout => TTCout,
clk40 => clk40,
@@ -491,7 +494,6 @@ begin
USE_Si5324_RefCLK => USE_Si5324_RefCLK,
generateTTCemu => generateTTCemu,
generate_IC_EC_TTC_only => generate_IC_EC_TTC_only,
- GENERATE_FEI4B => GENERATE_FEI4B,
GENERATE_TRUNCATION_MECHANISM => GENERATE_TRUNCATION_MECHANISM,
wideMode => wideMode,
EnableFrHo_Egroup0Eproc2_HDLC => EnableFrHo_Egroup0Eproc2_HDLC,
@@ -538,7 +540,10 @@ begin
EnableToHo_Egroup4Eproc2_8b10b => EnableToHo_Egroup4Eproc2_8b10b,
EnableToHo_Egroup4Eproc4_8b10b => EnableToHo_Egroup4Eproc4_8b10b,
EnableToHo_Egroup4Eproc8_8b10b => EnableToHo_Egroup4Eproc8_8b10b,
- EnableToHo_Egroup4Eproc16_8b10b => EnableToHo_Egroup3Eproc16_8b10b)
+ EnableToHo_Egroup4Eproc16_8b10b => EnableToHo_Egroup3Eproc16_8b10b,
+ GENERATE_FEI4B => GENERATE_FEI4B,
+ BLOCKSIZE => BLOCKSIZE,
+ CHUNK_TRAILER_32B => CHUNK_TRAILER_32B)
port map(
I2C_SMB => I2C_SMB,
I2C_SMBUS_CFG_nEN => I2C_SMBUS_CFG_nEN,
@@ -657,7 +662,11 @@ begin
STATIC_CENTRALROUTER => STATIC_CENTRALROUTER,
CREnableFromHost => CREnableFromHost,
toHostTimeoutBitn => toHostTimeoutBitn,
+ BLOCKSIZE => BLOCKSIZE,
+ CHUNK_TRAILER_32B => CHUNK_TRAILER_32B,
+ SUPER_CHUNK_FACTOR => SUPER_CHUNK_FACTOR,
wideMode => wideMode,
+ FIRMWARE_MODE => FIRMWARE_MODE,
BUILD_DATETIME => BUILD_DATETIME,
GIT_HASH => GIT_HASH,
GIT_TAG => GIT_TAG,
@@ -688,11 +697,16 @@ begin
BUSY_INTERRUPT => BUSY_INTERRUPT,
CRBusyOut => CR0BusyOut,
CR_FIFO_Busy => CR0_FIFO_Busy,
+ CSM0Monitor => CSM0Monitor,
+ CSM1Monitor => CSM1Monitor,
ChBusy => u13_ChBusy,
ChData => u12_ChData,
ChValid => u12_ChValid,
+ MasterBusy => MasterBusy,
TTC_ToHost_Data => TTC_ToHost_Data,
TTCout => TTCout,
+ Trx0Monitor => Trx0Monitor,
+ Trx1Monitor => Trx1Monitor,
clk160 => clk160,
clk250 => clk250,
clk40 => clk40,
@@ -713,8 +727,6 @@ begin
prmap_app_control => prmap_app_control,
prmap_board_info => prmap_board_info,
prmap_hk_monitor => prmap_hk_monitor,
- prmap_mrodEP0_mon => prmap_mrodEP0_mon,
- prmap_mrodEP1_mon => prmap_mrodEP1_mon,
prmap_ttc_monitor => prmap_ttc_monitor,
rst_hw => rst_hw,
rst_soft_40 => rst0_soft_40,
@@ -739,7 +751,11 @@ begin
STATIC_CENTRALROUTER => STATIC_CENTRALROUTER,
CREnableFromHost => CREnableFromHost,
toHostTimeoutBitn => toHostTimeoutBitn,
+ BLOCKSIZE => BLOCKSIZE,
+ CHUNK_TRAILER_32B => CHUNK_TRAILER_32B,
+ SUPER_CHUNK_FACTOR => SUPER_CHUNK_FACTOR,
wideMode => wideMode,
+ FIRMWARE_MODE => FIRMWARE_MODE,
BUILD_DATETIME => BUILD_DATETIME,
GIT_HASH => GIT_HASH,
GIT_TAG => GIT_TAG,
@@ -770,11 +786,16 @@ begin
BUSY_INTERRUPT => BUSY_INTERRUPT,
CRBusyOut => CR1BusyOut,
CR_FIFO_Busy => CR1_FIFO_Busy,
+ CSM0Monitor => CSM0Monitor,
+ CSM1Monitor => CSM1Monitor,
ChBusy => u23_ChBusy,
ChData => u22_ChData,
ChValid => u22_ChValid,
+ MasterBusy => MasterBusy,
TTC_ToHost_Data => TTC_ToHost_Data,
TTCout => TTCout,
+ Trx0Monitor => Trx0Monitor,
+ Trx1Monitor => Trx1Monitor,
clk160 => clk160,
clk250 => clk250,
clk40 => clk40,
@@ -795,8 +816,6 @@ begin
prmap_app_control => open,
prmap_board_info => prmap_board_info,
prmap_hk_monitor => prmap_hk_monitor,
- prmap_mrodEP0_mon => prmap_mrodEP0_mon,
- prmap_mrodEP1_mon => prmap_mrodEP1_mon,
prmap_ttc_monitor => prmap_ttc_monitor,
rst_hw => rst_hw,
rst_soft_40 => open,
diff --git a/sources/FelixMROD/housekeeping_module_mrod.vhd b/sources/FelixMROD/housekeeping_module_mrod.vhd
index 7f52b25100681390d675aaf7b9a1bdb5fe481c84..d4700bc2c6b6af7bb68ce88bedc7c6b72ea9d4f4 100644
--- a/sources/FelixMROD/housekeeping_module_mrod.vhd
+++ b/sources/FelixMROD/housekeeping_module_mrod.vhd
@@ -1,3 +1,7 @@
+--!------------------------------------------------------------------------------
+--! NIKHEF - National Institute for Subatomic Physics
+--! Electronics Department
+--!------------------------------------------------------------------------------
@@ -75,7 +79,10 @@ entity housekeeping_module is
EnableFrHo_Egroup4Eproc2_HDLC : boolean := true;
EnableFrHo_Egroup4Eproc4_8b10b : boolean := true;
EnableFrHo_Egroup4Eproc8_8b10b : boolean := true;
- GENERATE_FEI4B : boolean := false);
+ GENERATE_FEI4B : boolean := false;
+ --SUPER_CHUNK_FACTOR : integer := 12;
+ BLOCKSIZE : integer := 1024;
+ CHUNK_TRAILER_32B : boolean := false);
port (
LMK_locked : in std_logic_vector(0 downto 0);
MMCM_Locked_in : in std_logic;
@@ -228,7 +235,9 @@ architecture structure of housekeeping_module is
EnableFrHo_Egroup4Eproc2_HDLC : boolean := true;
EnableFrHo_Egroup4Eproc4_8b10b : boolean := true;
EnableFrHo_Egroup4Eproc8_8b10b : boolean := true;
- GENERATE_FEI4B : boolean := false);
+ GENERATE_FEI4B : boolean := false;
+ BLOCKSIZE : integer := 1024;
+ CHUNK_TRAILER_32B : boolean := false);
port (
AUTOMATIC_CLOCK_SWITCH_ENABLED : out std_logic_vector(0 downto 0);
register_map_gen_board_info : out register_map_gen_board_info_type);
@@ -393,7 +402,9 @@ begin
EnableFrHo_Egroup4Eproc2_HDLC => EnableFrHo_Egroup4Eproc2_HDLC,
EnableFrHo_Egroup4Eproc4_8b10b => EnableFrHo_Egroup4Eproc4_8b10b,
EnableFrHo_Egroup4Eproc8_8b10b => EnableFrHo_Egroup4Eproc8_8b10b,
- GENERATE_FEI4B => GENERATE_FEI4B)
+ GENERATE_FEI4B => GENERATE_FEI4B,
+ BLOCKSIZE => BLOCKSIZE,
+ CHUNK_TRAILER_32B => CHUNK_TRAILER_32B)
port map(
AUTOMATIC_CLOCK_SWITCH_ENABLED => AUTOMATIC_CLOCK_SWITCH_ENABLED,
register_map_gen_board_info => register_map_gen_board_info);
@@ -454,7 +465,7 @@ begin
g_WITH_INTERNAL_TIMEBASE => true, --: boolean := true;
g_CLK_SYS_FREQ => 25000000, --: integer;
g_COUNTER_BITS => 32, --: integer := 32;
- g_CHANNELS => GBT_NUM) --: integer := 1)
+ g_CHANNELS => GBT_NUM) --: integer := 1)
port map(
clk_sys_i => appreg_clk,--: in std_logic;
clk_in_i => RXUSRCLK_IN,--: in std_logic_vector(g_CHANNELS -1 downto 0);
diff --git a/sources/FelixMROD/register_map_sync.vhd b/sources/FelixMROD/register_map_sync.vhd
index a94a42e553adc79e2173a6dabe57e16d5b9e5400..3f86beddfb78376fd240ec86e7c192083bc2eaba 100644
--- a/sources/FelixMROD/register_map_sync.vhd
+++ b/sources/FelixMROD/register_map_sync.vhd
@@ -1,3 +1,8 @@
+--!------------------------------------------------------------------------------
+--! NIKHEF - National Institute for Subatomic Physics
+--! Electronics Department
+--!------------------------------------------------------------------------------
+--! 01-mar-2020, RH,TW: added FELIX_MROD monitor registers
@@ -25,13 +30,13 @@ entity register_map_sync is
register_map_gen_board_info : in register_map_gen_board_info_type;
register_map_hk_monitor : in register_map_hk_monitor_type;
register_map_monitor : out register_map_monitor_type;
- register_mrodEP0_mon : in regmap_mrodEP0_monitor_type;
- register_mrodEP1_mon : in regmap_mrodEP1_monitor_type;
+ register_mrod_monitor : in regmap_mrod_monitor_type;
register_map_ttc_monitor : in register_map_ttc_monitor_type;
register_map_xoff_monitor : in register_map_xoff_monitor_type;
rst_hw : in std_logic;
rst_soft_40 : out std_logic;
- rst_soft_appregclk : in std_logic);
+ rst_soft_appregclk : in std_logic;
+ master_busy_in : in std_logic);
end entity register_map_sync;
@@ -46,8 +51,7 @@ architecture rtl of register_map_sync is
signal register_map_cr_monitor_p1 : register_map_cr_monitor_type;
signal register_map_gbt_monitor_p1 : register_map_gbt_monitor_type;
signal register_map_emu_monitor_p1 : register_map_gbtemu_monitor_type;
- signal register_map_mrodEP0_monitor_p1 : regmap_mrodEP0_monitor_type;
- signal register_map_mrodEP1_monitor_p1 : regmap_mrodEP1_monitor_type;
+ signal register_map_mrod_monitor_p1 : regmap_mrod_monitor_type;
signal register_map_ttc_monitor_p1 : register_map_ttc_monitor_type;
signal register_map_xoff_monitor_p1 : register_map_xoff_monitor_type;
@@ -61,7 +65,6 @@ architecture rtl of register_map_sync is
signal rst_soft_p1 : std_logic;
--attribute ASYNC_REG of register_map_control_p1 : signal is "TRUE";
--attribute ASYNC_REG of rst_soft_p1 : signal is "TRUE";
-
begin
@@ -77,9 +80,21 @@ begin
end process;
appreg_sync: process(appreg_clk)
+ variable master_busy_p1, master_busy_p2: std_logic;
begin
if(rising_edge(appreg_clk)) then
- interrupt_call <= interrupt_call_p1;
+ if master_busy_p1 /= master_busy_p2 then
+ interrupt_call(6) <= '1';
+ else
+ interrupt_call(6) <= '0';
+ end if;
+
+ master_busy_p2 := master_busy_p1;
+ master_busy_p1 := master_busy_in;
+
+ interrupt_call(7) <= interrupt_call_p1(7);
+ interrupt_call(5) <= interrupt_call_p1(5);
+ interrupt_call(4) <= interrupt_call_p1(4);
interrupt_call_p1 <= interrupt_call_cr;
register_map_monitor.register_map_gen_board_info <= register_map_gen_board_info; --does not need synchronization as it contains only constants
register_map_monitor.register_map_hk_monitor <= register_map_hk_monitor_p1;
@@ -90,10 +105,8 @@ begin
register_map_gbt_monitor_p1 <= register_map_gbt_monitor;
register_map_monitor.register_map_gbtemu_monitor <= register_map_emu_monitor_p1;
register_map_emu_monitor_p1 <= register_map_emu_monitor;
- register_map_monitor.regmap_mrodEP0_monitor <= register_map_mrodEP0_monitor_p1;
- register_map_mrodEP0_monitor_p1 <= register_mrodEP0_mon;
- register_map_monitor.regmap_mrodEP1_monitor <= register_map_mrodEP1_monitor_p1;
- register_map_mrodEP1_monitor_p1 <= register_mrodEP1_mon;
+ register_map_monitor.regmap_mrod_monitor <= register_map_mrod_monitor_p1;
+ register_map_mrod_monitor_p1 <= register_mrod_monitor;
register_map_monitor.register_map_ttc_monitor <= register_map_ttc_monitor_p1;
register_map_ttc_monitor_p1 <= register_map_ttc_monitor;
register_map_monitor.register_map_xoff_monitor <= register_map_xoff_monitor_p1;
@@ -101,5 +114,39 @@ begin
end if;
end process;
-end architecture rtl ; -- of register_map_sync
+ -- drive unused registers felig_mon_ttc...
+ do_g0: for i in 0 to 23 generate
+ register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).L1ID <= (others => '0');
+ register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).XL1ID <= (others => '0');
+ register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).BCID <= (others => '0');
+ register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).RESERVED0 <= (others => '0');
+ register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).LEN <= (others => '0');
+ register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).FMT <= (others => '0');
+ register_map_monitor.register_map_generators.FELIG_MON_TTC_1(i).RESERVED1 <= (others => '0');
+ register_map_monitor.register_map_generators.FELIG_MON_TTC_1(i).TRIGGER_TYPE <= (others => '0');
+ register_map_monitor.register_map_generators.FELIG_MON_TTC_1(i).ORBIT <= (others => '0');
+ -- drive unused registers felig_mon_xxx...
+ register_map_monitor.register_map_generators.FELIG_MON_COUNTERS(i).SLIDE_COUNT <= (others => '0');
+ register_map_monitor.register_map_generators.FELIG_MON_COUNTERS(i).FC_ERROR_COUNT <= (others => '0');
+ register_map_monitor.register_map_generators.FELIG_MON_FREQ(i).TX <= (others => '0');
+ register_map_monitor.register_map_generators.FELIG_MON_FREQ(i).RX <= (others => '0');
+ register_map_monitor.register_map_generators.FELIG_MON_L1A_ID(i) <= (others => '0');
+ register_map_monitor.register_map_generators.FELIG_MON_PICXO(i).VLOT <= (others => '0');
+ register_map_monitor.register_map_generators.FELIG_MON_PICXO(i).ERROR <= (others => '0');
+ register_map_monitor.register_map_generators.FELIG_MON_ITK_STRIPS(i) <= (others => '0');
+ end generate do_g0;
+
+ -- drive unused registers fmemu_control...
+ register_map_monitor.register_map_generators.FMEMU_CONTROL.INT_STATUS_EMU <= (others => '0');
+ -- drive unused registers wishbone_monitor...
+ register_map_monitor.wishbone_monitor.WISHBONE_WRITE.FULL <= (others => '0');
+ register_map_monitor.wishbone_monitor.WISHBONE_READ.EMPTY <= (others => '0');
+ register_map_monitor.wishbone_monitor.WISHBONE_READ.DATA <= (others => '0');
+ register_map_monitor.wishbone_monitor.WISHBONE_STATUS.INT <= (others => '0');
+ register_map_monitor.wishbone_monitor.WISHBONE_STATUS.RETRY <= (others => '0');
+ register_map_monitor.wishbone_monitor.WISHBONE_STATUS.STALL <= (others => '0');
+ register_map_monitor.wishbone_monitor.WISHBONE_STATUS.ACKNOWLEDGE <= (others => '0');
+ register_map_monitor.wishbone_monitor.WISHBONE_STATUS.ERROR <= (others => '0');
+end architecture rtl ; -- of register_map_sync
+
diff --git a/sources/FelixMROD/thFMch_fifo_driver_mrod.vhd b/sources/FelixMROD/thFMch_fifo_driver_mrod.vhd
index cbea8de67191c32366675609fc38dd5f19846582..ecdd41eab10ea39d51d220aa239d2b758b83fdbc 100644
--- a/sources/FelixMROD/thFMch_fifo_driver_mrod.vhd
+++ b/sources/FelixMROD/thFMch_fifo_driver_mrod.vhd
@@ -6,14 +6,6 @@
--! Module Name: thFMch_fifo_driver
--! Project Name: FELIX
----------------------------------------------------------------------------------
---!-----------------------------------------------------------------------------
---! @authors R. Habraken, T. Wijnen (Radboud University Nijmegen)
---! @version FELIX_MROD: Interface to GOL links coming from the MDT Chambers.
---! This code replaces the "thFMch_fifo_driver" entity, adding special code
---! to adapt to the readout of the MDT chambers (uses no GBT links to frontend).
---! @modified Thu Oct 31 12:40:40 2019
---!-----------------------------------------------------------------------------
-
--! Use standard library
library ieee;
use ieee.std_logic_1164.all;
@@ -26,7 +18,11 @@ use work.centralRouter_package.all;
entity thFMch_fifo_driver is
generic (
FMCHid : integer := 0;
- toHostTimeoutBitn : integer := 8
+ FIRMWARE_MODE : integer := 1;
+ toHostTimeoutBitn : integer := 8;
+ SUPER_CHUNK_FACTOR : integer := 6;
+ BLOCKSIZE : integer := 1024;
+ CHUNK_TRAILER_32B : boolean := false
);
port (
clk40 : in std_logic;
@@ -36,7 +32,7 @@ port (
--re_o : out std_logic;
--empty_i : in std_logic;
din_rdy : in std_logic;
- din : in std_logic_vector (35 downto 0);
+ din : in std_logic_vector (32 downto 0);
----------
--timeOutCnt_i : in std_logic_vector ((toHostTimeoutBitn-1) downto 0); -- @ clk40 domain
timeOutEna_i : in std_logic;
@@ -57,7 +53,7 @@ signal is_comma,is_soc,is_eoc,is_sob,is_eob : std_logic;
--
signal BLOCK_HEADER : std_logic_vector (31 downto 0);
-signal din_r0, din_r1: std_logic_vector(35 downto 0);
+signal din_r0, din_r1: std_logic_vector(32 downto 0);
signal din_r : std_logic_vector (31 downto 0) := (others => '0');
signal din_code_r : std_logic_vector (1 downto 0) := (others => '0');
signal din_rdy_r0, din_rdy_r1, din_rdy_r : std_logic := '0';
@@ -81,10 +77,6 @@ signal crc_out : std_logic_vector(19 downto 0);
signal timeOutCnt : std_logic_vector ((toHostTimeoutBitn-1) downto 0); -- @ clk240 domain
signal trunc_s : std_logic; --signal copy of the truncation variable (in toBlock).
-
-constant felix_mrod : boolean := true;
-
-------------------------------------------------------------------------------------------
begin
@@ -163,7 +155,7 @@ begin
end if;
end process;
-do_crc: if (felix_mrod = false) generate
+do_crc: if (FIRMWARE_MODE /= 8) generate -- not for FelixMROD
begin
-- CRC module takes 2 clock cycles to calculate CRC
crc20_0: entity work.CRC
@@ -181,7 +173,7 @@ crc20_0: entity work.CRC
Reset => crc_start);
end generate do_crc;
-no_crc: if (felix_mrod = true) generate -- do not use crc (forces trailer CRC error to '0')
+no_crc: if (FIRMWARE_MODE = 8) generate -- for FelixMROD: do not use crc (forces trailer CRC error to '0')
begin
crc_out <= din_r(27 downto 8);
end generate no_crc;
diff --git a/sources/FelixMROD/thFMdm_mrod.vhd b/sources/FelixMROD/thFMdm_mrod.vhd
index 2fe7288780988afd88c7057471f9aa25f81362a1..7e1f4295e7d6891c954b3eed029fc44b87b31361 100644
--- a/sources/FelixMROD/thFMdm_mrod.vhd
+++ b/sources/FelixMROD/thFMdm_mrod.vhd
@@ -6,21 +6,13 @@
--! Module Name: thFMdm
--! Project Name: FELIX
----------------------------------------------------------------------------------
---!-----------------------------------------------------------------------------
---! @authors R. Habraken, T. Wijnen (Radboud University Nijmegen)
---! @version FELIX_MROD: Interface to GOL links coming from the MDT Chambers.
---! This code replaces the "thFMdm" entity, adding special code
---! to adapt to the readout of the MDT chambers (uses no GBT links to frontend).
---! @modified Tue Dec 03 13:00:00 2019
---!-----------------------------------------------------------------------------
-
--! Use standard library
library IEEE, work;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
-use work.centralRouter_package.all;
use work.pcie_package.all;
+use work.centralRouter_package.all;
use work.all;
--! to-Host centralRouter logic
@@ -28,8 +20,12 @@ use work.all;
entity thFMdm is
generic (
FMCHid : integer := 0;
+ FIRMWARE_MODE : integer := 1;
STATIC_CENTRALROUTER : boolean := false; -- removes update process from central router register map, only initial constant values are used
- toHostTimeoutBitn : integer := 8
+ toHostTimeoutBitn : integer := 8;
+ SUPER_CHUNK_FACTOR : integer := 1;
+ BLOCKSIZE : integer := 1024;
+ CHUNK_TRAILER_32B : boolean := false
);
port (
clk40 : in std_logic;
@@ -98,7 +94,7 @@ signal chFIFO_empty, chFIFO_pempty : std_logic;
signal chFIFO_din32_rdy, ch_xoff : std_logic;
signal chFIFO_din32 : std_logic_vector(31 downto 0);
signal chFIFO_dout_s : std_logic_vector(255 downto 0);
-signal chfifo_driver_din : std_logic_vector(35 downto 0);
+signal chfifo_driver_din : std_logic_vector(32 downto 0);
--
signal wr_data_count : std_logic_vector(3 downto 0);
signal xoff_fm_ch_fifo_thresh_low : std_logic_vector(3 downto 0);
@@ -182,12 +178,16 @@ fmch_ena <= '1' when (fmch_config_reg(0) = '1' and FMCHlink_valid = '1') else '0
------------------------------------------------------------
-- full mode channel FIFO driver
------------------------------------------------------------
-chfifo_driver_din <= "000" & FMCHdtype & FMCHdin;
+chfifo_driver_din <= FMCHdtype & FMCHdin;
chFIFOdriver: entity work.thFMch_fifo_driver
generic map(
FMCHid => FMCHid,
- toHostTimeoutBitn => toHostTimeoutBitn
+ FIRMWARE_MODE => FIRMWARE_MODE,
+ toHostTimeoutBitn => toHostTimeoutBitn,
+ SUPER_CHUNK_FACTOR => SUPER_CHUNK_FACTOR,
+ BLOCKSIZE => BLOCKSIZE,
+ CHUNK_TRAILER_32B => CHUNK_TRAILER_32B
)
port map (
clk40 => clk40,
@@ -238,8 +238,8 @@ port map (
prog_full => chFIFO_pfull, -- '1' when a space for only one block is left (threshold 3580/3581)
prog_empty => chFIFO_pempty, -- '1' when less then one block is written (threshold 31/32)
wr_data_count => wr_data_count,
- prog_full_thresh => std_logic_vector(to_unsigned(3581, 12)),
- prog_empty_thresh => std_logic_vector(to_unsigned(31, 9))
+ prog_full_thresh => std_logic_vector(to_unsigned(4093-(BLOCKSIZE/2), 12)),
+ prog_empty_thresh => std_logic_vector(to_unsigned((BLOCKSIZE/32)-1, 9))
);
pr2: process(clk_wrth) -- fifo write clock
diff --git a/sources/FelixMROD/thfmPCIeManager_mrod.vhd b/sources/FelixMROD/thfmPCIeManager_mrod.vhd
index 4fc9ea07bb4a7928994e164cb85a4382750efe63..71423033cacafeed84a7eed18717fff829643bec 100644
--- a/sources/FelixMROD/thfmPCIeManager_mrod.vhd
+++ b/sources/FelixMROD/thfmPCIeManager_mrod.vhd
@@ -6,7 +6,6 @@
--! Module Name: thfmPCIeManager
--! Project Name: FELIX
----------------------------------------------------------------------------------
-
--! Use standard library
library ieee,work;
use ieee.std_logic_1164.all;
@@ -18,7 +17,8 @@ use work.all;
--! reading from Downstream thchs order
entity thfmPCIeManager is
Generic (
- FMCH_NUM : integer := 1
+ FMCH_NUM : integer := 1;
+ BLOCKSIZE : integer := 1024
);
Port (
clk : in std_logic;
@@ -35,7 +35,9 @@ end thfmPCIeManager;
architecture Behavioral of thfmPCIeManager is
signal FMCHcount : std_logic_vector(5 downto 0) := (others => '0'); -- counts to maximum possible channel number (0 to 31) (double clocks)
-signal BLOCKcount : std_logic_vector(5 downto 0) := (others => '0'); -- counts 256-bit words in block (0 to 31)
+
+constant NUMBER_OF_256_PER_BLOCK : integer := BLOCKSIZE / 32;
+signal BLOCKcount : integer range 0 to (NUMBER_OF_256_PER_BLOCK*2)-1 := 0; -- counts 256-bit words in block (0 to 31)
signal thch_rdy_array_full : std_logic_vector(FMCH_NUM-1 downto 0) := (others => '0');
signal thch_reN_array : std_logic_vector(FMCH_NUM-1 downto 0);
@@ -95,7 +97,7 @@ thch_rdy_pulse: entity work.pulse_pdxx_pwxx
pulseout => thch_rdy_1clk
);
--
-block_done <= '1' when (BLOCKcount = "100000") else '0'; -- 1KByte = 256 x 32
+block_done <= '1' when (BLOCKcount = NUMBER_OF_256_PER_BLOCK) else '0'; -- 1KByte = 256 x 32
--
reN: entity work.ReMuxN
generic map(N => FMCH_NUM)
@@ -120,16 +122,16 @@ thch_re_array <= thch_reN_array((FMCH_NUM-1) downto 0);
BLOCKcounter : process(rst_state, clk)
begin
if rst_state = '1' then
- BLOCKcount <= "000001"; --(others => '0');
+ BLOCKcount <= 1;
elsif clk'event and clk = '1' then
if re_s = '1' then
if block_done = '1' then
- BLOCKcount <= "000001"; --(others => '0');
+ BLOCKcount <= 1;
else
BLOCKcount <= BLOCKcount + 1;
end if;
else
- BLOCKcount <= "000001"; --(others => '0');
+ BLOCKcount <= 1;
end if;
end if;
end process;
diff --git a/sources/centralRouter/CRFM.vhd b/sources/centralRouter/CRFM.vhd
index 96ccc13203f817df4a1657b0caea5f79c4050baf..a3c6925493361421a134c92814686429728e0c86 100644
--- a/sources/centralRouter/CRFM.vhd
+++ b/sources/centralRouter/CRFM.vhd
@@ -6,7 +6,6 @@
--! Module Name: CRFM
--! Project Name: FELIX
----------------------------------------------------------------------------------
-
--! Use standard library
library work, ieee, unisim;
use ieee.std_logic_1164.all;
@@ -50,7 +49,10 @@ generic (
toHostTimeoutBitn : integer := 8;
GENERATE_XOFF : boolean := true;
CARD_TYPE : integer;
- CREnableFromHost : boolean := true
+ CREnableFromHost : boolean := true;
+ SUPER_CHUNK_FACTOR : integer := 1;
+ BLOCKSIZE : integer := 1024;
+ CHUNK_TRAILER_32B : boolean := false
);
port (
clk40 : in std_logic;
@@ -479,7 +481,10 @@ thFMdmN: entity work.thFMdm
generic map(
FMCHid => I,
STATIC_CENTRALROUTER => STATIC_CENTRALROUTER,
- toHostTimeoutBitn => toHostTimeoutBitn
+ toHostTimeoutBitn => toHostTimeoutBitn,
+ SUPER_CHUNK_FACTOR => SUPER_CHUNK_FACTOR,
+ BLOCKSIZE => BLOCKSIZE,
+ CHUNK_TRAILER_32B => CHUNK_TRAILER_32B
)
port map(
clk40 => clk40,
@@ -551,7 +556,10 @@ port map(
-- writing to the cr OUT FIFO / reading from channel fifos
------------------------------------------------------------
THPCIeM: entity work.thfmPCIeManager
-generic map(FMCH_NUM => FMCH_NUM+1)
+generic map(
+ FMCH_NUM => FMCH_NUM+1,
+ BLOCKSIZE => BLOCKSIZE
+ )
port map(
clk => clk250,
rst => cr_rst, -- reset is deasserted after fifo flush!
diff --git a/sources/centralRouter/thFMch_fifo_driver.vhd b/sources/centralRouter/thFMch_fifo_driver.vhd
index 41e276182bc37996295548e9208fa9de9b06c34e..8cd6456274ac4c781e6b8ff96a0ff40d0d07cc97 100644
--- a/sources/centralRouter/thFMch_fifo_driver.vhd
+++ b/sources/centralRouter/thFMch_fifo_driver.vhd
@@ -18,7 +18,10 @@ use work.centralRouter_package.all;
entity thFMch_fifo_driver is
generic (
FMCHid : integer := 0;
- toHostTimeoutBitn : integer := 8
+ toHostTimeoutBitn : integer := 8;
+ SUPER_CHUNK_FACTOR : integer := 6;
+ BLOCKSIZE : integer := 1024;
+ CHUNK_TRAILER_32B : boolean := false
);
port (
clk40 : in std_logic;
@@ -28,7 +31,7 @@ port (
--re_o : out std_logic;
--empty_i : in std_logic;
din_rdy : in std_logic;
- din : in std_logic_vector (35 downto 0);
+ din : in std_logic_vector (32 downto 0);
----------
--timeOutCnt_i : in std_logic_vector ((toHostTimeoutBitn-1) downto 0); -- @ clk40 domain
timeOutEna_i : in std_logic;
@@ -45,11 +48,15 @@ architecture Behavioral of thFMch_fifo_driver is
--
--signal din_rdy,re_o_s : std_logic := '0';
signal busy_o_r : std_logic := '0';
-signal is_comma,is_soc,is_eoc,is_sob,is_eob : std_logic;
+signal is_comma,is_soc,is_eoc,is_sob,is_eob, is_eoc_intermediate, intermediate_crc_check: std_logic;
+constant NUMBER_OF_WORDS_PER_BLOCK: integer := BLOCKSIZE/4;
+--eg180620 count chunks and enable soc/eoc
+signal chunk_enable : std_logic := '1';
+--constant SUPER_CHUNK : integer := 12;
--
signal BLOCK_HEADER : std_logic_vector (31 downto 0);
-signal din_r0, din_r1: std_logic_vector(35 downto 0);
+signal din_r0, din_r1: std_logic_vector(32 downto 0);
signal din_r : std_logic_vector (31 downto 0) := (others => '0');
signal din_code_r : std_logic_vector (1 downto 0) := (others => '0');
signal din_rdy_r0, din_rdy_r1, din_rdy_r : std_logic := '0';
@@ -68,7 +75,7 @@ constant STORED_DATA_DEPTH : integer := 4;
signal sop_detected: std_logic;
signal reset_state, rst_p1, rst_p2 : std_logic;
-signal crc_calc, crc_start : std_logic;
+signal crc_calc, crc_start, chunk_start : std_logic;
signal crc_out : std_logic_vector(19 downto 0);
signal timeOutCnt : std_logic_vector ((toHostTimeoutBitn-1) downto 0); -- @ clk240 domain
@@ -96,6 +103,11 @@ crc_control: process(clk240)
begin
if rising_edge(clk240) then
crc_calc <= (not din(32)) and din_rdy;
+ if (din(32)='1' and din(7 downto 0)=Kchar_sop and chunk_enable='1') then --same as is_soc, but one clk earlier
+ chunk_start <= '1';
+ else
+ chunk_start <= '0';
+ end if;
if (din(32)='1' and din(7 downto 0)=Kchar_sop) then --same as is_soc, but one clk earlier
crc_start <= '1';
else
@@ -114,6 +126,29 @@ begin
end if;
end process;
+chunk_counting: process(clk240)
+ variable chunk_count : integer range 0 to SUPER_CHUNK_FACTOR := SUPER_CHUNK_FACTOR;
+ variable chunk_count_incr : std_logic := '0';
+begin
+ if rising_edge(clk240) then
+ if(reset_state = '1') then
+ chunk_enable <= '0';
+ chunk_count := SUPER_CHUNK_FACTOR;
+ chunk_count_incr := '0';
+ elsif (din_rdy='1' and din(32)='1' and din(7 downto 0)=Kchar_sop and chunk_count_incr='0') then
+ chunk_count := chunk_count - 1;
+ chunk_count_incr:='1';
+ if (chunk_count = 0) then
+ chunk_enable <= '1';
+ chunk_count := SUPER_CHUNK_FACTOR;
+ else
+ chunk_enable <= '0';
+ end if;
+ else
+ chunk_count_incr := '0';
+ end if;
+ end if;
+end process;
------------------------------------------------------------
-- input data type
@@ -126,17 +161,22 @@ begin
else
is_comma <= '0';
end if;
- is_soc <= crc_start; --CRC start is the same as is_soc, but one clock earlier.
+ is_soc <= chunk_start; --CRC start is the same as is_soc, but one clock earlier.
--if (din_r0(32)='1' and din_r0(7 downto 0)=Kchar_sop) then
-- is_soc <= '1';
--else
-- is_soc <= '0';
--end if;
- if (din_r0(32)='1' and din_r0(7 downto 0)=Kchar_eop)then
+ if (din_r0(32)='1' and din_r0(7 downto 0)=Kchar_eop and chunk_enable='1')then
is_eoc <= '1';
else
is_eoc <= '0';
end if;
+ if (din_r0(32)='1' and din_r0(7 downto 0)=Kchar_eop)then
+ is_eoc_intermediate <= '1';
+ else
+ is_eoc_intermediate <= '0';
+ end if;
if (din_r0(32)='1' and din_r0(7 downto 0)=Kchar_sob)then
is_sob <= '1';
else
@@ -233,7 +273,8 @@ begin
sop_detected <= '0';
next_din_code_r := "00";
elsif rising_edge (clk240) then
-
+ intermediate_crc_check <= '0';
+
if din_rdy_r1 = '1' then
if din_r1(32)='1' then -- byte(0) is a K-character
if is_soc = '1' then
@@ -252,6 +293,9 @@ begin
din_rdy_r <= '0';
busy_o_r <= '0'; -- end-of-busy
else --comma
+ if is_eoc_intermediate = '1' then
+ intermediate_crc_check <= '1';
+ end if;
din_rdy_r <= '0';
NULL;
end if;
@@ -274,9 +318,9 @@ busy_o <= busy_o_r;
toblock: process(clk240)
variable wordOUT_v : std_logic_vector(31 downto 0) := x"0000_0000";
variable wordOUT_rdy_v : std_logic;
- variable blockCounter : integer range 0 to 255; --counts the number of 32 bit words that form a block.
+ variable blockCounter : integer range 0 to NUMBER_OF_WORDS_PER_BLOCK-1; --counts the number of 32 bit words that form a block.
variable blockSequence : std_logic_vector(4 downto 0); --counts the block sequence in the block header
- variable chunkCounter : std_logic_vector (11 downto 0); --counts the length in the chunk, both for trailer generation and truncation
+ variable chunkCounter : std_logic_vector (15 downto 0); --counts the length in the chunk, both for trailer generation and truncation
variable stored_data_code : std_logic_vector(1 downto 0);
variable create_trailer, create_zero_trailer, create_timeout_trailer : std_logic;
variable trunc : std_logic;
@@ -295,7 +339,7 @@ begin
if(reset_state = '1') then
blockCounter := 0;
blockSequence := "00000";
- chunkCounter := x"000";
+ chunkCounter := x"0000";
create_trailer := '0';
create_zero_trailer := '0';
create_timeout_trailer := '0';
@@ -338,6 +382,12 @@ begin
when others =>
NULL;
end case;
+ else
+ if intermediate_crc_check = '1' then
+ if ( crc_out /= din_r(27 downto 8) ) then
+ CRC_error := '1';
+ end if;
+ end if;
end if;
if(EOC_error = '1' or SOC_error = '1') then
@@ -368,7 +418,7 @@ begin
end if;
- if(blockCounter = 255 and create_timeout_trailer = '0') then --end of block, always create trailer.
+ if(blockCounter = (NUMBER_OF_WORDS_PER_BLOCK-1) and create_timeout_trailer = '0') then --end of block, always create trailer.
create_trailer := '1';
end if;
@@ -449,15 +499,19 @@ begin
first_subchunk;
-
- wordOUT_v := x"0000" & trailerType & trunc & error_v & CRC_error & chunkCounter(9 downto 0);
- if(busy_o_r = '1') then --Send out Out of band trailer with SOB k-char (K28.2) when in busy state.
- wordOUT_v(31 downto 16) := x"E0" & Kchar_sob;
+ if CHUNK_TRAILER_32B then
+ wordOUT_v := trailerType & trunc & error_v & CRC_error & busy_o_r & "0" & x"00" & chunkCounter(15 downto 0);
+ else
+ wordOUT_v := x"0000" & trailerType & trunc & error_v & CRC_error & chunkCounter(9 downto 0);
+ if(busy_o_r = '1') then --Send out Out of band trailer with SOB k-char (K28.2) when in busy state.
+ wordOUT_v(31 downto 16) := x"E0" & Kchar_sob;
+ end if;
end if;
+
if(xoff = '0') then
error_v := '0';
CRC_error := '0';
- chunkCounter := x"000";
+ chunkCounter := x"0000";
wordOUT_rdy_v := '1';
end if;
@@ -466,7 +520,7 @@ begin
wordOUT_v := x"0000" & zero_data_trailer;
end if;
- if(blockCounter = 254 and xoff='0') then --trailer created one word before last, add zero trailer.
+ if(blockCounter = (NUMBER_OF_WORDS_PER_BLOCK-2) and xoff='0') then --trailer created one word before last, add zero trailer.
create_zero_trailer := '1'; --will be pipelined, zero trailer comes next clock cycle
end if;
@@ -481,18 +535,29 @@ begin
CRC_error := '0';
create_trailer := '0';
last_subchunk := '0';
- if(blockCounter = 255) then --end of block, we need to stop sending 0 trailers and add the 0xA0XX timeout trailer, then go back to idle
+ if(blockCounter = (NUMBER_OF_WORDS_PER_BLOCK-1)) then --end of block, we need to stop sending 0 trailers and add the 0xA0XX timeout trailer, then go back to idle
if (xoff='0') then
- wordOUT_v := x"0000" & timeout_trailer(15 downto 10) & chunkCounter(9 downto 0);
+ if CHUNK_TRAILER_32B then
+ wordOUT_v := timeout_trailer(15 downto 10) & "00" & x"00" & chunkCounter(15 downto 0);
+ else
+ wordOUT_v := x"0000" & timeout_trailer(15 downto 10) & chunkCounter(9 downto 0);
+ end if;
+
wordOUT_rdy_v := '1'; --If xoff (fifo full) we don't push out data.
- chunkCounter := x"000"; --chunk counter is reset here
+ chunkCounter := x"0000"; --chunk counter is reset here
create_timeout_trailer := '0'; --back to idle operation
end if;
elsif(din_rdy_r = '1') then
if (xoff='0') then
- wordOUT_v := x"0000" & timeout_trailer(15 downto 10) & chunkCounter(9 downto 0); --same operation, but in the middle of a block when new data arrives.
+
+ if CHUNK_TRAILER_32B then
+ wordOUT_v := timeout_trailer(15 downto 10) & "00" & x"00" & chunkCounter(15 downto 0); --same operation, but in the middle of a block when new data arrives.
+ else
+ wordOUT_v := x"0000" & timeout_trailer(15 downto 10) & chunkCounter(9 downto 0); --same operation, but in the middle of a block when new data arrives.
+ end if;
+
wordOUT_rdy_v := '1'; --fifo full? don't push out data.
- chunkCounter := x"000";
+ chunkCounter := x"0000";
create_timeout_trailer := '0'; --back to idle
stored_data(data_stored) := din_code_r & din_r; --meanwhile record data
data_stored := data_stored+1;
@@ -511,7 +576,7 @@ begin
if(wordOUT_rdy_v = '1') then
- if(blockCounter = 255) then
+ if(blockCounter = (NUMBER_OF_WORDS_PER_BLOCK-1)) then
blockCounter := 0;
else
blockCounter := blockCounter + 1; --increment blockCounter as we are pushing into the fifo.
diff --git a/sources/centralRouter/thFMdm.vhd b/sources/centralRouter/thFMdm.vhd
index 441512276a35132bc7efb3c273e67736195ca5c9..8cd7b80866157317a45295c5bff6cb6778107572 100644
--- a/sources/centralRouter/thFMdm.vhd
+++ b/sources/centralRouter/thFMdm.vhd
@@ -20,7 +20,10 @@ entity thFMdm is
generic (
FMCHid : integer := 0;
STATIC_CENTRALROUTER : boolean := false; -- removes update process from central router register map, only initial constant values are used
- toHostTimeoutBitn : integer := 8
+ toHostTimeoutBitn : integer := 8;
+ SUPER_CHUNK_FACTOR : integer := 1;
+ BLOCKSIZE : integer := 1024;
+ CHUNK_TRAILER_32B : boolean := false
);
port (
clk40 : in std_logic;
@@ -90,7 +93,7 @@ signal chFIFO_dout_s : std_logic_vector(255 downto 0);
signal wr_data_count : std_logic_vector(3 downto 0);
signal xoff_fm_ch_fifo_thresh_low: std_logic_vector(3 downto 0);
signal xoff_fm_ch_fifo_thresh_high: std_logic_vector(3 downto 0);
-signal chfifo_driver_din: std_logic_vector(35 downto 0);
+signal chfifo_driver_din: std_logic_vector(32 downto 0);
begin
------------------------------------------------------------
-- configuration registers map
@@ -153,11 +156,14 @@ fmch_ena <= fmch_config_reg(0) and FMCHlink_valid;
------------------------------------------------------------
-- full mode channel FIFO driver
------------------------------------------------------------
-chfifo_driver_din <= "000" & FMCHdtype & FMCHdin;
+chfifo_driver_din <= FMCHdtype & FMCHdin;
chFIFOdriver: entity work.thFMch_fifo_driver
generic map(
FMCHid => FMCHid,
- toHostTimeoutBitn => toHostTimeoutBitn
+ toHostTimeoutBitn => toHostTimeoutBitn,
+ SUPER_CHUNK_FACTOR => SUPER_CHUNK_FACTOR,
+ BLOCKSIZE => BLOCKSIZE,
+ CHUNK_TRAILER_32B => CHUNK_TRAILER_32B
)
port map (
clk40 => clk40,
@@ -207,8 +213,10 @@ port map (
prog_full => chFIFO_pfull, -- '1' when a space for only one block is left (threshold 3580/3581)
prog_empty => chFIFO_pempty, -- '1' when less then one block is written (threshold 31/32)
wr_data_count => wr_data_count,
- prog_full_thresh => std_logic_vector(to_unsigned(3581, 12)),
- prog_empty_thresh => std_logic_vector(to_unsigned(31, 9))
+ --prog_full_thresh => std_logic_vector(to_unsigned(4093-(NUMBER_OF_WORDS_PER_BLOCK*2), 12)),
+ --prog_empty_thresh => std_logic_vector(to_unsigned((NUMBER_OF_WORDS_PER_BLOCK/8)-1, 9))
+ prog_full_thresh => std_logic_vector(to_unsigned(4093-(BLOCKSIZE/2), 12)),
+ prog_empty_thresh => std_logic_vector(to_unsigned((BLOCKSIZE/32)-1, 9))
);
diff --git a/sources/centralRouter/thfmPCIeManager.vhd b/sources/centralRouter/thfmPCIeManager.vhd
index 015a9c7e37a7464cbcb500b1d6193a91db2eb32a..2dd168f77c0e17453d806a590c4c5f34b9bef6fa 100644
--- a/sources/centralRouter/thfmPCIeManager.vhd
+++ b/sources/centralRouter/thfmPCIeManager.vhd
@@ -17,7 +17,8 @@ use work.centralRouter_package.all;
--! reading from Downstream thchs order
entity thfmPCIeManager is
Generic (
- FMCH_NUM : integer := 1
+ FMCH_NUM : integer := 1;
+ BLOCKSIZE : integer := 1024
);
Port (
clk : in std_logic;
@@ -33,8 +34,10 @@ end thfmPCIeManager;
architecture Behavioral of thfmPCIeManager is
+constant NUMBER_OF_256_PER_BLOCK : integer := BLOCKSIZE / 32;
+
signal FMCHcount : std_logic_vector(4 downto 0) := (others => '0'); -- counts to maximum possible channel number (0 to 15) (double clocks)
-signal BLOCKcount : std_logic_vector(5 downto 0) := (others => '0'); -- counts 256-bit words in block (0 to 31)
+signal BLOCKcount : integer range 0 to (NUMBER_OF_256_PER_BLOCK*2)-1:=0; -- std_logic_vector(5 downto 0) := (others => '0'); -- counts 256-bit words in block (0 to 31)
signal thch_rdy_array_full : std_logic_vector(FMCH_NUM-1 downto 0) := (others => '0');
signal thch_reN_array : std_logic_vector(FMCH_NUM-1 downto 0);
@@ -85,7 +88,7 @@ thch_rdy <= thch_rdy_array_full(to_integer(unsigned(FMCHcount(4 downto 1))));
thch_rdy_s <= thch_rdy and (not FMCHcount(0)) and (not rst_state) and PCIe_ena;
thch_rdy_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk, thch_rdy_s, thch_rdy_1clk);
--
-block_done <= '1' when (BLOCKcount = "100000") else '0'; -- 1KByte = 256 x 32
+block_done <= '1' when (BLOCKcount = NUMBER_OF_256_PER_BLOCK) else '0'; -- 1KByte = 256 x 32
--
reN: entity work.ReMuxN
generic map( N => FMCH_NUM)
@@ -110,16 +113,16 @@ thch_re_array <= thch_reN_array((FMCH_NUM-1) downto 0);
BLOCKcounter : process(rst_state, clk)
begin
if rst_state = '1' then
- BLOCKcount <= "000001"; --(others => '0');
+ BLOCKcount <= 1; --(others => '0');
elsif clk'event and clk = '1' then
if re_s = '1' then
if block_done = '1' then
- BLOCKcount <= "000001"; --(others => '0');
+ BLOCKcount <= 1; --(others => '0');
else
BLOCKcount <= BLOCKcount + 1;
end if;
else
- BLOCKcount <= "000001"; --(others => '0');
+ BLOCKcount <= 1; --(others => '0');
end if;
end if;
end process;
diff --git a/sources/housekeeping/GenericConstantsToRegs.vhd b/sources/housekeeping/GenericConstantsToRegs.vhd
index 8495455e47a67864124501f7e9e19417f289112d..3b5316d49c4d1384a8b312855a5cca0509f84b26 100644
--- a/sources/housekeeping/GenericConstantsToRegs.vhd
+++ b/sources/housekeeping/GenericConstantsToRegs.vhd
@@ -75,7 +75,9 @@ entity GenericConstantsToRegs is
EnableFrHo_Egroup4Eproc2_HDLC : boolean := true;
EnableFrHo_Egroup4Eproc4_8b10b : boolean := true;
EnableFrHo_Egroup4Eproc8_8b10b : boolean := true;
- GENERATE_FEI4B : boolean := false);
+ GENERATE_FEI4B : boolean := false;
+ BLOCKSIZE : integer := 1024;
+ CHUNK_TRAILER_32B : boolean := false);
port (
AUTOMATIC_CLOCK_SWITCH_ENABLED : out std_logic_vector(0 downto 0);
register_map_gen_board_info : out register_map_gen_board_info_type);
@@ -95,25 +97,18 @@ architecture rtl of GenericConstantsToRegs is
begin
+ register_map_gen_board_info.TTC_EMU_CONST_GENERATE_TTC_EMU <= CONV(generateTTCemu);
+ --register_map_gen_board_info.TTC_EMU_CONST.TTC_TEST_MODE <= CONV(TTC_test_mode);
+ register_map_gen_board_info.GENERATE_GBT <= CONV(GENERATE_GBT); -- 1 when the GBT is included in the design
+ --register_map_gen_board_info.GBT_MAPPING <= std_logic_vector(to_unsigned(GBT_MAPPING,8)); -- CXP-to-GBT mapping:
+ -- 0: NORMAL CXP1 1-12 CXP2 13-24
+ -- 1: ALTERNATE CXP1 1-4,9-12,17-20
+ register_map_gen_board_info.OPTO_TRX_NUM <= std_logic_vector(to_unsigned(OPTO_TRX,8)); -- Number of optical transceivers in the design
+ register_map_gen_board_info.NUM_OF_CHANNELS <= std_logic_vector(to_unsigned(GBT_NUM,8)); -- Number of GBT Channels
+ register_map_gen_board_info.BLOCKSIZE <= std_logic_vector(to_unsigned(BLOCKSIZE, 16));
+ register_map_gen_board_info.CHUNK_TRAILER_32B <= CONV(CHUNK_TRAILER_32B);
+ register_map_gen_board_info.PCIE_ENDPOINTS <= std_logic_vector(to_unsigned(ENDPOINTS, 2));
- register_map_gen_board_info.TTC_EMU_CONST_GENERATE_TTC_EMU <= CONV(generateTTCemu);
- --register_map_gen_board_info.TTC_EMU_CONST.TTC_TEST_MODE <= CONV(TTC_test_mode);
- register_map_gen_board_info.GENERATE_GBT <= CONV(GENERATE_GBT); -- 1 when the GBT is included in the design
- --register_map_gen_board_info.GBT_MAPPING <= std_logic_vector(to_unsigned(GBT_MAPPING,8)); -- CXP-to-GBT mapping:
- -- 0: NORMAL CXP1 1-12 CXP2 13-24
- -- 1: ALTERNATE CXP1 1-4,9-12,17-20
- register_map_gen_board_info.OPTO_TRX_NUM <= std_logic_vector(to_unsigned(OPTO_TRX,8)); -- Number of optical transceivers in the design
- register_map_gen_board_info.NUM_OF_CHANNELS <= std_logic_vector(to_unsigned(GBT_NUM,8)); -- Number of GBT Channels
- register_map_gen_board_info.BLOCKSIZE <= "00000"& BLOCK_WORDn & '0'; -- Number of bytes in a block
- --register_map_gen_board_info.INCLUDE_EPROC16 <= CONV(includeEproc16); -- EPROC16 is included in Central Router
- --register_map_gen_board_info.INCLUDE_EPROC16.FRHOEPROC2 <= CONV(includeFrHoEproc2s); --EPROC is included in Central Router
- --register_map_gen_board_info.INCLUDE_EPROC16.FRHOEPROC4 <= CONV(includeFrHoEproc4s); --EPROC is included in Central Router
- --register_map_gen_board_info.INCLUDE_EPROC16.FRHOEPROC8 <= CONV(includeFrHoEproc8s); --EPROC is included in Central Router
- --register_map_gen_board_info.INCLUDE_EPROC16.FRHOEPROC16 <= CONV(false); --EPROC is included in Central Router
- --register_map_gen_board_info.INCLUDE_EPROC16.TOHOEPROC2 <= CONV(includeToHoEproc2s); --EPROC is included in Central Router
- --register_map_gen_board_info.INCLUDE_EPROC16.TOHOEPROC4 <= CONV(includeToHoEproc4s); --EPROC is included in Central Router
- --register_map_gen_board_info.INCLUDE_EPROC16.TOHOEPROC8 <= CONV(includeToHoEproc8s); --EPROC is included in Central Router
- --register_map_gen_board_info.INCLUDE_EPROC16.TOHOEPROC16 <= CONV(includeToHoEproc16); --EPROC is included in Central Router
register_map_gen_board_info.INCLUDE_EGROUP(0).TOHOST_HDLC <= CONV(EnableToHo_Egroup0Eproc2_HDLC );
register_map_gen_board_info.INCLUDE_EGROUP(0).TOHOST_02 <= CONV(EnableToHo_Egroup0Eproc2_8b10b);
register_map_gen_board_info.INCLUDE_EGROUP(0).TOHOST_04 <= CONV(EnableToHo_Egroup0Eproc4_8b10b);
@@ -159,8 +154,38 @@ begin
register_map_gen_board_info.INCLUDE_EGROUP(4).FROMHOST_02 <= CONV(EnableFrHo_Egroup4Eproc2_HDLC );
register_map_gen_board_info.INCLUDE_EGROUP(4).FROMHOST_04 <= CONV(EnableFrHo_Egroup4Eproc4_8b10b);
register_map_gen_board_info.INCLUDE_EGROUP(4).FROMHOST_08 <= CONV(EnableFrHo_Egroup4Eproc8_8b10b);
- register_map_gen_board_info.PCIE_ENDPOINTS <= std_logic_vector(to_unsigned(ENDPOINTS, 2));
-
+
+ register_map_gen_board_info.INCLUDE_EGROUP(5).FROMHOST_HDLC <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(5).FROMHOST_02 <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(5).FROMHOST_04 <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(5).FROMHOST_08 <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(6).FROMHOST_HDLC <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(6).FROMHOST_02 <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(6).FROMHOST_04 <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(6).FROMHOST_08 <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(5).TOHOST_HDLC <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(5).TOHOST_02 <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(5).TOHOST_04 <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(5).TOHOST_08 <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(5).TOHOST_16 <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(6).TOHOST_HDLC <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(6).TOHOST_02 <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(6).TOHOST_04 <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(6).TOHOST_08 <= (others => '0');
+ register_map_gen_board_info.INCLUDE_EGROUP(6).TOHOST_16 <= (others => '0');
+
+ -- these registers are loaded inside dma_control.vhd:
+ --register_map_gen_board_info.REG_MAP_VERSION
+ --register_map_gen_board_info.BOARD_ID_TIMESTAMP
+ --register_map_gen_board_info.GIT_COMMIT_TIME
+ --register_map_gen_board_info.GIT_TAG
+ --register_map_gen_board_info.GIT_COMMIT_NUMBER
+ --register_map_gen_board_info.GIT_HASH
+ --register_map_gen_board_info.GENERIC_CONSTANTS.INTERRUPTS
+ --register_map_gen_board_info.GENERIC_CONSTANTS.DESCRIPTORS
+ --register_map_gen_board_info.CARD_TYPE
+ --register_map_gen_board_info.PCIE_ENDPOINT
+
register_map_gen_board_info.FIRMWARE_MODE <= "0001" when (FIRMWARE_MODE = 1) else --FULL mode
"0010" when (generate_IC_EC_TTC_only = true) else --LTDB mode
"0011" when (GENERATE_FEI4B = true) else --FEI4 mode
@@ -169,13 +194,14 @@ begin
"0101" when (FIRMWARE_MODE = 5) else -- ITK Strip
"0110" when (FIRMWARE_MODE = 6) else -- FELIG
"0111" when (FIRMWARE_MODE = 7) else -- Full mode emulator
- "1000" when (FIRMWARE_MODE = 8); -- MROD mode
+ "1000" when (FIRMWARE_MODE = 8); -- FELIX_MROD
+
- --register_map_gen_board_info.CR_INTERNAL_LOOPBACK_MODE <= CONV(crInternalLoopbackMode); -- 1 when Central Router internal loopback mode is enabled
- register_map_gen_board_info.WIDE_MODE <= CONV(wideMode); -- GBT is configured in Wide mode
- --register_map_gen_board_info.DEBUG_MODE <= CONV(DEBUG_MODE); -- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
- -- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
- AUTOMATIC_CLOCK_SWITCH_ENABLED <= CONV(AUTOMATIC_CLOCK_SWITCH); -- 1 when the automatic clock switch is enabled in the design
+ --register_map_gen_board_info.CR_INTERNAL_LOOPBACK_MODE <= CONV(crInternalLoopbackMode); -- 1 when Central Router internal loopback mode is enabled
+ register_map_gen_board_info.WIDE_MODE <= CONV(wideMode); -- GBT is configured in Wide mode
+ --register_map_gen_board_info.DEBUG_MODE <= CONV(DEBUG_MODE); -- 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
+ -- 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
+ AUTOMATIC_CLOCK_SWITCH_ENABLED <= CONV(AUTOMATIC_CLOCK_SWITCH); -- 1 when the automatic clock switch is enabled in the design
register_map_gen_board_info.CR_GENERICS.FROM_HOST_INCLUDED <= CONV(CREnableFromHost);
register_map_gen_board_info.CR_GENERICS.DIRECT_MODE_INCLUDED <= CONV(includeDirectMode);
diff --git a/sources/pcie/register_map_sync.vhd b/sources/pcie/register_map_sync.vhd
index 6803f6f794ff2b76117c35a22b4006456e6fcc92..522b536141c3f3243a0bb4d28064c4f16ef4f37a 100644
--- a/sources/pcie/register_map_sync.vhd
+++ b/sources/pcie/register_map_sync.vhd
@@ -29,7 +29,8 @@ entity register_map_sync is
register_map_xoff_monitor : in register_map_xoff_monitor_type;
rst_hw : in std_logic;
rst_soft_40 : out std_logic;
- rst_soft_appregclk : in std_logic);
+ rst_soft_appregclk : in std_logic;
+ master_busy_in : in std_logic);
end entity register_map_sync;
@@ -73,9 +74,22 @@ begin
end process;
appreg_sync: process(appreg_clk)
+ variable master_busy_p1, master_busy_p2: std_logic;
begin
if(rising_edge(appreg_clk)) then
- interrupt_call <= interrupt_call_p1;
+ if master_busy_p1 /= master_busy_p2 then
+ interrupt_call(6) <= '1';
+ else
+ interrupt_call(6) <= '0';
+ end if;
+
+ master_busy_p2 := master_busy_p1;
+ master_busy_p1 := master_busy_in;
+
+
+ interrupt_call(7) <= interrupt_call_p1(7);
+ interrupt_call(5) <= interrupt_call_p1(5);
+ interrupt_call(4) <= interrupt_call_p1(4);
interrupt_call_p1 <= interrupt_call_cr;
register_map_monitor.register_map_gen_board_info <= register_map_gen_board_info; --does not need synchronization as it contains only constants
register_map_monitor.register_map_hk_monitor <= register_map_hk_monitor_p1;
diff --git a/sources/pcie/wupper.vhd b/sources/pcie/wupper.vhd
index a7f05a1296e7566d575b319809b196beace69997..39a8d56aa8f4de863ff849a40eddf4b9dfa92dab 100644
--- a/sources/pcie/wupper.vhd
+++ b/sources/pcie/wupper.vhd
@@ -1,4 +1,3 @@
-
--!------------------------------------------------------------------------------
--!
--! NIKHEF - National Institute for Subatomic Physics
@@ -71,7 +70,8 @@ entity wupper is
GBT_GENERATE_ALL_REGS : boolean := false;
EMU_GENERATE_REGS : boolean := false;
MROD_GENERATE_REGS : boolean := false;
- PCIE_ENDPOINT : integer := 0);
+ PCIE_ENDPOINT : integer := 0;
+ BLOCKSIZE : integer := 1024);
port (
appreg_clk : out std_logic;
flush_fifo : out std_logic;
@@ -159,7 +159,7 @@ begin
register_map_control <= register_map_control_s;
- u1: entity work.pcie_ep_wrap
+ ep0: entity work.pcie_ep_wrap
generic map(
CARD_TYPE => CARD_TYPE,
DEVID => DEVID)
@@ -216,7 +216,9 @@ begin
GIT_COMMIT_NUMBER => GIT_COMMIT_NUMBER,
GBT_GENERATE_ALL_REGS => GBT_GENERATE_ALL_REGS,
EMU_GENERATE_REGS => EMU_GENERATE_REGS,
- PCIE_ENDPOINT => PCIE_ENDPOINT)
+ MROD_GENERATE_REGS => MROD_GENERATE_REGS,
+ PCIE_ENDPOINT => PCIE_ENDPOINT,
+ BLOCKSIZE => BLOCKSIZE)
port map(
bar0 => bar0,
bar1 => bar1,
@@ -254,7 +256,7 @@ begin
tohost_pfull_threshold_negate => toHostFifo_pfull_threshold_negate,
user_lnk_up => lnk_up_net);
- u2: entity work.intr_ctrl
+ irq0: entity work.intr_ctrl
generic map(
NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS)
port map(
@@ -277,7 +279,7 @@ begin
s_axis_rq => m_axis_rq,
int_test => register_map_control_s.INT_TEST);
- u0: entity work.pcie_init
+ init0: entity work.pcie_init
port map(
bar0 => bar0,
bar1 => bar1,
@@ -299,12 +301,13 @@ begin
clk => clk,
reset => reset);
- u3: entity work.pcie_slow_clock
+ clk0: entity work.pcie_slow_clock
port map(
clk => clk,
regmap_clk => regmap_clk,
pll_locked => pll_locked,
reset_n => sys_rst_n,
reset_out => reset_hard);
+
end architecture structure ; -- of wupper
diff --git a/sources/pcie/wupper_core.vhd b/sources/pcie/wupper_core.vhd
index 972d3763151b1221b620126ce8dd49daf341f969..2152b3474a306ad2c503d8bafec7c6317b08a78c 100644
--- a/sources/pcie/wupper_core.vhd
+++ b/sources/pcie/wupper_core.vhd
@@ -67,10 +67,11 @@ entity wupper_core is
COMMIT_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE";
GIT_TAG : std_logic_vector(127 downto 0) := x"00000000000000000000000000000000";
GIT_COMMIT_NUMBER : integer := 0;
- GBT_GENERATE_ALL_REGS : boolean :=false;
+ GBT_GENERATE_ALL_REGS : boolean := false;
EMU_GENERATE_REGS : boolean := false;
- MROD_GENERATE_REGS : boolean := true;
- PCIE_ENDPOINT : integer := 0);
+ MROD_GENERATE_REGS : boolean := false;
+ PCIE_ENDPOINT : integer := 0;
+ BLOCKSIZE : integer := 1024);
port (
bar0 : in std_logic_vector(31 downto 0);
bar1 : in std_logic_vector(31 downto 0);
@@ -116,76 +117,9 @@ architecture structure of wupper_core is
signal u1_dma_descriptors : dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
signal dma_soft_reset : std_logic;
- component dma_read_write
- generic(
- NUMBER_OF_DESCRIPTORS : integer := 8);
- port (
- clk : in std_logic;
- dma_descriptors : in dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
- dma_soft_reset : in std_logic;
- dma_status : out dma_statuses_type(0 to (NUMBER_OF_DESCRIPTORS-1));
- fromHostFifo_din : out std_logic_vector(255 downto 0);
- fromHostFifo_prog_full : in std_logic;
- fromHostFifo_we : out std_logic;
- m_axis_r_rq : in axis_r_type;
- m_axis_rq : out axis_type;
- reset : in std_logic;
- s_axis_r_rc : out axis_r_type;
- s_axis_rc : in axis_type;
- toHostFifo_dout : in std_logic_vector(255 downto 0);
- toHostFifo_empty_thresh : out std_logic_vector(11 downto 0);
- toHostFifo_prog_empty : in std_logic;
- toHostFifo_re : out std_logic);
- end component dma_read_write;
-
- component dma_control
- generic(
- NUMBER_OF_DESCRIPTORS : integer := 8;
- NUMBER_OF_INTERRUPTS : integer := 8;
- SVN_VERSION : integer := 0;
- BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE";
- CARD_TYPE : integer := 710;
- GIT_HASH : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000";
- COMMIT_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE";
- GIT_TAG : std_logic_vector(127 downto 0) := x"00000000000000000000000000000000";
- GIT_COMMIT_NUMBER : integer := 0;
- GBT_GENERATE_ALL_REGS : boolean :=false;
- EMU_GENERATE_REGS : boolean := false;
- PCIE_ENDPOINT : integer := 0);
- port (
- bar0 : in std_logic_vector(31 downto 0);
- bar1 : in std_logic_vector(31 downto 0);
- bar2 : in std_logic_vector(31 downto 0);
- clk : in std_logic;
- regmap_clk : in std_logic;
- dma_descriptors : out dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
- dma_soft_reset : out std_logic;
- dma_status : in dma_statuses_type;
- flush_fifo : out std_logic;
- interrupt_vector : out interrupt_vectors_type(0 to (NUMBER_OF_INTERRUPTS-1));
- m_axis_cc : out axis_type;
- m_axis_r_cc : in axis_r_type;
- reset : in std_logic;
- reset_global_soft : out std_logic;
- s_axis_cq : in axis_type;
- s_axis_r_cq : out axis_r_type;
- register_map_monitor : in register_map_monitor_type;
- register_map_control : out register_map_control_type;
- interrupt_table_en : out std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 0);
- dma_interrupt_call : out std_logic_vector(3 downto 0);
- fifo_empty : in std_logic;
- fifo_full : in std_logic;
- fromhost_pfull_threshold_assert : out std_logic_vector(8 downto 0);
- fromhost_pfull_threshold_negate : out std_logic_vector(8 downto 0);
- tohost_pfull_threshold_assert : out std_logic_vector(11 downto 0);
- tohost_pfull_threshold_negate : out std_logic_vector(11 downto 0);
- tohost_busy_out : out std_logic;
- fromhost_busy_out : out std_logic);
- end component dma_control;
-
begin
- u0: dma_read_write
+ u0: entity work.dma_read_write
generic map(
NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS)
port map(
@@ -206,7 +140,7 @@ begin
toHostFifo_prog_empty => toHostFifo_prog_empty,
toHostFifo_re => toHostFifo_re);
- u1: dma_control
+ u1: entity work.dma_control
generic map(
NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS,
NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS,
@@ -219,7 +153,9 @@ begin
GIT_COMMIT_NUMBER => GIT_COMMIT_NUMBER,
GBT_GENERATE_ALL_REGS => GBT_GENERATE_ALL_REGS,
EMU_GENERATE_REGS => EMU_GENERATE_REGS,
- PCIE_ENDPOINT => PCIE_ENDPOINT)
+ MROD_GENERATE_REGS => MROD_GENERATE_REGS,
+ PCIE_ENDPOINT => PCIE_ENDPOINT,
+ BLOCKSIZE => BLOCKSIZE)
port map(
bar0 => bar0,
bar1 => bar1,
@@ -249,5 +185,6 @@ begin
tohost_pfull_threshold_negate => tohost_pfull_threshold_negate,
tohost_busy_out => tohost_busy_out,
fromhost_busy_out => fromhost_busy_out);
+
end architecture structure ; -- of wupper_core
diff --git a/sources/templates/build-doc.sh b/sources/templates/build-doc.sh
old mode 100644
new mode 100755
index bec61ba7094ab5ed455398f50c1c47b246661077..910e449b8cc3505134ad3d28cce04e5deee8f0cc
--- a/sources/templates/build-doc.sh
+++ b/sources/templates/build-doc.sh
@@ -1,15 +1,14 @@
#!/bin/sh -e
+# build the documentation from the registermap.tex file
-wuppercodegen=../../../software/wuppercodegen/wuppercodegen/cli.py
-registers=registers-4.10.yaml
-$wuppercodegen --version
-$wuppercodegen $registers registermap.tex.template registermap.tex
latex registers.tex
latex registers.tex
dvipdf registers.dvi
+
regdoc=../../../documents/regmap
-cp registers.pdf $regdoc
-cp registers.tex $regdoc
-cp registermap.tex $regdoc
+cp -p registers.pdf $regdoc
+cp -p registers.tex $regdoc
+cp -p registermap.tex $regdoc
+
+#cp -p *.html $regdoc
-cp *.html $regdoc
diff --git a/sources/templates/build-html.sh b/sources/templates/build-html.sh
index 9f0df8955b6fba4be3cf479f639370935dd53e28..02bef2171e9a4a16a99f2292d65bf2137b432996 100755
--- a/sources/templates/build-html.sh
+++ b/sources/templates/build-html.sh
@@ -22,5 +22,6 @@ $wuppercodegen --version
echo "Generating html documentation for current version..."
$wuppercodegen $current_registers $wuppercodegen_dir/input/registers.html.template registers-$1.html
-
+#regdoc=../../../documents/regmap
+#cp -p *.html $regdoc
diff --git a/sources/templates/build.sh b/sources/templates/build.sh
index 14438eead002f32e53b425cf3c977c623842eeb5..e1f9100de382d08d0b53287f81fc01d275453101 100755
--- a/sources/templates/build.sh
+++ b/sources/templates/build.sh
@@ -31,5 +31,10 @@ echo "Generating pcie_package.vhd and dma_control.vhd for current version..."
$wuppercodegen $current_registers $template_dir/pcie_package.vhd.template $template_dir/pcie_package.vhd
$wuppercodegen $current_registers $template_dir/dma_control.vhd.template $template_dir/dma_control.vhd
+# build the registermap.tex documentation file
+wuppercodegen=../../../software/wuppercodegen/wuppercodegen/cli.py
+registers=registers-${current_version}.yaml
+$wuppercodegen --version
+$wuppercodegen $registers registermap.tex.template registermap.tex
-
+#
diff --git a/sources/templates/dma_control.vhd b/sources/templates/dma_control.vhd
index 25fb5897c9743fa22370b19ec7c2662ad86a4d0d..21a2d73403df28851eec8af9071053479e3591e7 100644
--- a/sources/templates/dma_control.vhd
+++ b/sources/templates/dma_control.vhd
@@ -89,10 +89,11 @@ entity dma_control is
GIT_TAG : std_logic_vector(127 downto 0) := x"00000000000000000000000000000000";
GIT_COMMIT_NUMBER : integer := 0;
COMMIT_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE";
- GBT_GENERATE_ALL_REGS : boolean :=false;
+ GBT_GENERATE_ALL_REGS : boolean := false;
EMU_GENERATE_REGS : boolean := false;
- MROD_GENERATE_REGS : boolean := true;
- PCIE_ENDPOINT : integer := 0);
+ MROD_GENERATE_REGS : boolean := false;
+ PCIE_ENDPOINT : integer := 0;
+ BLOCKSIZE : integer := 1024);
port (
bar0 : in std_logic_vector(31 downto 0);
bar1 : in std_logic_vector(31 downto 0);
@@ -139,6 +140,8 @@ architecture rtl of dma_control is
constant WRITE_REGISTER_MODIFYWRITE_SLV : std_logic_vector(2 downto 0) := "100";
constant WAIT_RW_DONE_SLV : std_logic_vector(2 downto 0) := "101";
constant SEND_UNKNOWN_REQUEST_SLV : std_logic_vector(2 downto 0) := "111";
+
+ constant NUMBER_OF_WORDS_PER_BLOCK: integer := BLOCKSIZE/4;
signal dma_descriptors_s : dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
signal dma_descriptors_25_r_s : dma_descriptors_type(0 to 7);
@@ -771,8 +774,8 @@ end process;
fromhost_pfull_threshold_assert_s <= std_logic_vector(to_unsigned(10, 9));
fromhost_pfull_threshold_negate_s <= std_logic_vector(to_unsigned(6, 9));
- tohost_pfull_threshold_assert_s <= std_logic_vector(to_unsigned(4050, 12));
- tohost_pfull_threshold_negate_s <= std_logic_vector(to_unsigned(3744, 12));
+ tohost_pfull_threshold_assert_s <= std_logic_vector(to_unsigned(4095-(NUMBER_OF_WORDS_PER_BLOCK/8)*2, 12));
+ tohost_pfull_threshold_negate_s <= std_logic_vector(to_unsigned(4095-(NUMBER_OF_WORDS_PER_BLOCK/8)*3, 12));
busy_threshold_assert <= REG_BUSY_THRESH_ASSERT_C;
busy_threshold_negate <= REG_BUSY_THRESH_NEGATE_C;
@@ -7437,18 +7440,14 @@ end process;
register_map_control_s.TTC_BUSY_TIMING_CTRL.PRESCALE <= REG_TTC_BUSY_TIMING_CTRL_PRESCALE_C; -- Prescales the 40MHz clock to create an internal slow clock
register_map_control_s.TTC_BUSY_TIMING_CTRL.BUSY_WIDTH <= REG_TTC_BUSY_TIMING_CTRL_BUSY_WIDTH_C; -- Minimum number of 40MHz clocks that the busy is asserted
register_map_control_s.TTC_BUSY_TIMING_CTRL.LIMIT_TIME <= REG_TTC_BUSY_TIMING_CTRL_LIMIT_TIME_C; -- Number of prescaled clocks a given busy must be asserted before it is recognized
- register_map_control_s.TTC_EMU_CONTROL.LAST_LINE <= REG_TTC_EMU_CONTROL_LAST_LINE_C; -- Last line of the sequence
- register_map_control_s.TTC_EMU_CONTROL.REPEAT <= REG_TTC_EMU_CONTROL_REPEAT_C; -- Repeat the sequence
- register_map_control_s.TTC_EMU_CONTROL.BROADCAST5 <= REG_TTC_EMU_CONTROL_BROADCAST5_C; -- Broadcast 5
- register_map_control_s.TTC_EMU_CONTROL.BROADCAST4 <= REG_TTC_EMU_CONTROL_BROADCAST4_C; -- Broadcast 4
- register_map_control_s.TTC_EMU_CONTROL.BROADCAST3 <= REG_TTC_EMU_CONTROL_BROADCAST3_C; -- Broadcast 3
- register_map_control_s.TTC_EMU_CONTROL.BROADCAST2 <= REG_TTC_EMU_CONTROL_BROADCAST2_C; -- Broadcast 2
- register_map_control_s.TTC_EMU_CONTROL.BROADCAST1 <= REG_TTC_EMU_CONTROL_BROADCAST1_C; -- Broadcast 1
- register_map_control_s.TTC_EMU_CONTROL.BROADCAST0 <= REG_TTC_EMU_CONTROL_BROADCAST0_C; -- Broadcast 0
+ register_map_control_s.TTC_EMU_CONTROL.BROADCAST <= REG_TTC_EMU_CONTROL_BROADCAST_C; -- Broadcast data
register_map_control_s.TTC_EMU_CONTROL.ECR <= REG_TTC_EMU_CONTROL_ECR_C; -- Event counter reset
register_map_control_s.TTC_EMU_CONTROL.BCR <= REG_TTC_EMU_CONTROL_BCR_C; -- Bunch counter reset
register_map_control_s.TTC_EMU_CONTROL.L1A <= REG_TTC_EMU_CONTROL_L1A_C; -- Level 1 Accept
- register_map_control_s.TTC_EMU_CONTROL.STEP_COUNTER <= REG_TTC_EMU_CONTROL_STEP_COUNTER_C; -- Step counter value
+ register_map_control_s.TTC_EMU_L1A_PERIOD <= REG_TTC_EMU_L1A_PERIOD_C; -- L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
+ register_map_control_s.TTC_EMU_ECR_PERIOD <= REG_TTC_EMU_ECR_PERIOD_C; -- ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
+ register_map_control_s.TTC_EMU_BCR_PERIOD <= REG_TTC_EMU_BCR_PERIOD_C; -- BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
+ register_map_control_s.TTC_EMU_LONG_CHANNEL_DATA <= REG_TTC_EMU_LONG_CHANNEL_DATA_C; -- Long channel data for the TTC emulator
register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW <= REG_XOFF_FM_CH_FIFO_THRESH_LOW_C; -- Controls the low threshold of the channel fifo in FULL mode on which
-- an Xon will be asserted, bitfields control 4 MSB
@@ -9564,7 +9563,7 @@ end process;
register_map_control_s.IC_TOHOST_FIFO(23).RE <= REG_IC_TOHOST_FIFO_23_RE_C; -- Any write to this register will trigger a read enable from the fifo
end if;
register_map_control_s.TTC_BUSY_CLEAR <= REG_TTC_BUSY_CLEAR_C; -- clears the latching busy bits in TTC_BUSY_ACCEPTED
- register_map_control_s.TTC_EMU_CONTROL.WE <= REG_TTC_EMU_CONTROL_WE_C; -- Any write to this register executes a write enable
+ register_map_control_s.TTC_EMU_RESET <= REG_TTC_EMU_RESET_C; -- Any write to this register resets the TTC Emulator to the default state.
register_map_control_s.XOFF_FM_HIGH_THRESH.CLEAR_LATCH <= REG_XOFF_FM_HIGH_THRESH_CLEAR_LATCH_C; -- Writing this register will clear all CROSS_LATCHED bits
register_map_control_s.DMA_BUSY_STATUS.CLEAR_LATCH <= REG_DMA_BUSY_STATUS_CLEAR_LATCH_C; -- Any write to this register clears TOHOST_BUSY_LATCHED
register_map_control_s.FM_BUSY_CHANNEL_STATUS.CLEAR_LATCH <= REG_FM_BUSY_CHANNEL_STATUS_CLEAR_LATCH_C; -- Any write to this register will clear the BUSY_LATCHED bits
@@ -14328,19 +14327,15 @@ end process;
register_read_data_25_s(31 downto 16) <= register_map_control_s.TTC_BUSY_TIMING_CTRL.BUSY_WIDTH; -- Minimum number of 40MHz clocks that the busy is asserted
register_read_data_25_s(15 downto 0) <= register_map_control_s.TTC_BUSY_TIMING_CTRL.LIMIT_TIME; -- Number of prescaled clocks a given busy must be asserted before it is recognized
when REG_TTC_BUSY_CLEAR => register_read_data_25_s(64 downto 64) <= register_map_control_s.TTC_BUSY_CLEAR; -- clears the latching busy bits in TTC_BUSY_ACCEPTED
- when REG_TTC_EMU_CONTROL => register_read_data_25_s(64 downto 64) <= register_map_control_s.TTC_EMU_CONTROL.WE; -- Any write to this register executes a write enable
- register_read_data_25_s(35 downto 35) <= register_map_control_s.TTC_EMU_CONTROL.LAST_LINE; -- Last line of the sequence
- register_read_data_25_s(34 downto 34) <= register_map_control_s.TTC_EMU_CONTROL.REPEAT; -- Repeat the sequence
- register_read_data_25_s(32 downto 32) <= register_map_control_s.TTC_EMU_CONTROL.BROADCAST5; -- Broadcast 5
- register_read_data_25_s(31 downto 31) <= register_map_control_s.TTC_EMU_CONTROL.BROADCAST4; -- Broadcast 4
- register_read_data_25_s(30 downto 30) <= register_map_control_s.TTC_EMU_CONTROL.BROADCAST3; -- Broadcast 3
- register_read_data_25_s(29 downto 29) <= register_map_control_s.TTC_EMU_CONTROL.BROADCAST2; -- Broadcast 2
- register_read_data_25_s(28 downto 28) <= register_map_control_s.TTC_EMU_CONTROL.BROADCAST1; -- Broadcast 1
- register_read_data_25_s(27 downto 27) <= register_map_control_s.TTC_EMU_CONTROL.BROADCAST0; -- Broadcast 0
+ when REG_TTC_EMU_CONTROL => register_read_data_25_s(32 downto 27) <= register_map_control_s.TTC_EMU_CONTROL.BROADCAST; -- Broadcast data
register_read_data_25_s(26 downto 26) <= register_map_control_s.TTC_EMU_CONTROL.ECR; -- Event counter reset
register_read_data_25_s(25 downto 25) <= register_map_control_s.TTC_EMU_CONTROL.BCR; -- Bunch counter reset
register_read_data_25_s(24 downto 24) <= register_map_control_s.TTC_EMU_CONTROL.L1A; -- Level 1 Accept
- register_read_data_25_s(21 downto 0) <= register_map_control_s.TTC_EMU_CONTROL.STEP_COUNTER; -- Step counter value
+ when REG_TTC_EMU_L1A_PERIOD => register_read_data_25_s(31 downto 0) <= register_map_control_s.TTC_EMU_L1A_PERIOD; -- L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
+ when REG_TTC_EMU_ECR_PERIOD => register_read_data_25_s(31 downto 0) <= register_map_control_s.TTC_EMU_ECR_PERIOD; -- ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
+ when REG_TTC_EMU_BCR_PERIOD => register_read_data_25_s(31 downto 0) <= register_map_control_s.TTC_EMU_BCR_PERIOD; -- BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
+ when REG_TTC_EMU_LONG_CHANNEL_DATA => register_read_data_25_s(31 downto 0) <= register_map_control_s.TTC_EMU_LONG_CHANNEL_DATA; -- Long channel data for the TTC emulator
+ when REG_TTC_EMU_RESET => register_read_data_25_s(64 downto 64) <= register_map_control_s.TTC_EMU_RESET; -- Any write to this register resets the TTC Emulator to the default state.
when REG_XOFF_FM_CH_FIFO_THRESH_LOW => register_read_data_25_s(3 downto 0) <= register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW; -- Controls the low threshold of the channel fifo in FULL mode on which
-- an Xon will be asserted, bitfields control 4 MSB
@@ -17190,40 +17185,38 @@ end process;
register_read_data_25_s(1 downto 1) <= register_map_monitor_s.wishbone_monitor.WISHBONE_STATUS.ACKNOWLEDGE; -- Indicates the termination of a normal bus cycle
register_read_data_25_s(0 downto 0) <= register_map_monitor_s.wishbone_monitor.WISHBONE_STATUS.ERROR; -- Address not mapped by the crossbar
--- MROD_EP0monitors
+-- MRODmonitors
when REG_MROD_EP0_CSMH_EMPTY =>
if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrodEP0_monitor.MROD_EP0_CSMH_EMPTY; -- CSM Handler FIFO Empty 23-0
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_CSMH_EMPTY; -- CSM Handler FIFO Empty 23-0
end if;
when REG_MROD_EP0_CSMH_FULL =>
if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrodEP0_monitor.MROD_EP0_CSMH_FULL; -- CSM Handler FIFO Full 23-0
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_CSMH_FULL; -- CSM Handler FIFO Full 23-0
end if;
when REG_MROD_EP0_RXLOCKED =>
if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrodEP0_monitor.MROD_EP0_RXLOCKED; -- EP0 Receiver Locked monitor 23-0
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_RXLOCKED; -- EP0 Receiver Locked monitor 23-0
end if;
when REG_MROD_EP0_TXLOCKED =>
if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrodEP0_monitor.MROD_EP0_TXLOCKED; -- EP0 Transmitter Locked monitor 23-0
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_TXLOCKED; -- EP0 Transmitter Locked monitor 23-0
end if;
-
--- MROD_EP1monitors
when REG_MROD_EP1_CSMH_EMPTY =>
if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrodEP1_monitor.MROD_EP1_CSMH_EMPTY; -- CSM Handler FIFO Empty 23-0
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_CSMH_EMPTY; -- CSM Handler FIFO Empty 23-0
end if;
when REG_MROD_EP1_CSMH_FULL =>
if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrodEP1_monitor.MROD_EP1_CSMH_FULL; -- CSM Handler FIFO Full 23-0
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_CSMH_FULL; -- CSM Handler FIFO Full 23-0
end if;
when REG_MROD_EP1_RXLOCKED =>
if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrodEP1_monitor.MROD_EP1_RXLOCKED; -- EP1 Receiver Locked monitor 23-0
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_RXLOCKED; -- EP1 Receiver Locked monitor 23-0
end if;
when REG_MROD_EP1_TXLOCKED =>
if MROD_GENERATE_REGS = true then
- register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrodEP1_monitor.MROD_EP1_TXLOCKED; -- EP1 Transmitter Locked monitor 23-0
+ register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_TXLOCKED; -- EP1 Transmitter Locked monitor 23-0
end if;
-----------------------------------
---- GENERATED code END #3 ## ----
@@ -21911,19 +21904,15 @@ end process;
register_map_control_s.TTC_BUSY_TIMING_CTRL.BUSY_WIDTH <= register_write_data_25_v(31 downto 16); -- Minimum number of 40MHz clocks that the busy is asserted
register_map_control_s.TTC_BUSY_TIMING_CTRL.LIMIT_TIME <= register_write_data_25_v(15 downto 0); -- Number of prescaled clocks a given busy must be asserted before it is recognized
when REG_TTC_BUSY_CLEAR => register_map_control_s.TTC_BUSY_CLEAR <= "1"; -- clears the latching busy bits in TTC_BUSY_ACCEPTED
- when REG_TTC_EMU_CONTROL => register_map_control_s.TTC_EMU_CONTROL.WE <= "1"; -- Any write to this register executes a write enable
- register_map_control_s.TTC_EMU_CONTROL.LAST_LINE <= register_write_data_25_v(35 downto 35); -- Last line of the sequence
- register_map_control_s.TTC_EMU_CONTROL.REPEAT <= register_write_data_25_v(34 downto 34); -- Repeat the sequence
- register_map_control_s.TTC_EMU_CONTROL.BROADCAST5 <= register_write_data_25_v(32 downto 32); -- Broadcast 5
- register_map_control_s.TTC_EMU_CONTROL.BROADCAST4 <= register_write_data_25_v(31 downto 31); -- Broadcast 4
- register_map_control_s.TTC_EMU_CONTROL.BROADCAST3 <= register_write_data_25_v(30 downto 30); -- Broadcast 3
- register_map_control_s.TTC_EMU_CONTROL.BROADCAST2 <= register_write_data_25_v(29 downto 29); -- Broadcast 2
- register_map_control_s.TTC_EMU_CONTROL.BROADCAST1 <= register_write_data_25_v(28 downto 28); -- Broadcast 1
- register_map_control_s.TTC_EMU_CONTROL.BROADCAST0 <= register_write_data_25_v(27 downto 27); -- Broadcast 0
+ when REG_TTC_EMU_CONTROL => register_map_control_s.TTC_EMU_CONTROL.BROADCAST <= register_write_data_25_v(32 downto 27); -- Broadcast data
register_map_control_s.TTC_EMU_CONTROL.ECR <= register_write_data_25_v(26 downto 26); -- Event counter reset
register_map_control_s.TTC_EMU_CONTROL.BCR <= register_write_data_25_v(25 downto 25); -- Bunch counter reset
register_map_control_s.TTC_EMU_CONTROL.L1A <= register_write_data_25_v(24 downto 24); -- Level 1 Accept
- register_map_control_s.TTC_EMU_CONTROL.STEP_COUNTER <= register_write_data_25_v(21 downto 0); -- Step counter value
+ when REG_TTC_EMU_L1A_PERIOD => register_map_control_s.TTC_EMU_L1A_PERIOD <= register_write_data_25_v(31 downto 0); -- L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
+ when REG_TTC_EMU_ECR_PERIOD => register_map_control_s.TTC_EMU_ECR_PERIOD <= register_write_data_25_v(31 downto 0); -- ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
+ when REG_TTC_EMU_BCR_PERIOD => register_map_control_s.TTC_EMU_BCR_PERIOD <= register_write_data_25_v(31 downto 0); -- BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
+ when REG_TTC_EMU_LONG_CHANNEL_DATA => register_map_control_s.TTC_EMU_LONG_CHANNEL_DATA <= register_write_data_25_v(31 downto 0); -- Long channel data for the TTC emulator
+ when REG_TTC_EMU_RESET => register_map_control_s.TTC_EMU_RESET <= "1"; -- Any write to this register resets the TTC Emulator to the default state.
when REG_XOFF_FM_CH_FIFO_THRESH_LOW => register_map_control_s.XOFF_FM_CH_FIFO_THRESH_LOW <= register_write_data_25_v(3 downto 0); -- Controls the low threshold of the channel fifo in FULL mode on which
-- an Xon will be asserted, bitfields control 4 MSB
diff --git a/sources/templates/dma_control.vhd.template b/sources/templates/dma_control.vhd.template
index 9b4b383387bac0f6d295a3f881c30cb1fdb2658d..6dcbce8c3a11965197ecd6859eb7d1235a4c7570 100644
--- a/sources/templates/dma_control.vhd.template
+++ b/sources/templates/dma_control.vhd.template
@@ -68,10 +68,11 @@ entity dma_control is
GIT_TAG : std_logic_vector(127 downto 0) := x"00000000000000000000000000000000";
GIT_COMMIT_NUMBER : integer := 0;
COMMIT_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE";
- GBT_GENERATE_ALL_REGS : boolean :=false;
+ GBT_GENERATE_ALL_REGS : boolean := false;
EMU_GENERATE_REGS : boolean := false;
- MROD_GENERATE_REGS : boolean := true;
- PCIE_ENDPOINT : integer := 0);
+ MROD_GENERATE_REGS : boolean := false;
+ PCIE_ENDPOINT : integer := 0;
+ BLOCKSIZE : integer := 1024);
port (
bar0 : in std_logic_vector(31 downto 0);
bar1 : in std_logic_vector(31 downto 0);
@@ -118,6 +119,8 @@ architecture rtl of dma_control is
constant WRITE_REGISTER_MODIFYWRITE_SLV : std_logic_vector(2 downto 0) := "100";
constant WAIT_RW_DONE_SLV : std_logic_vector(2 downto 0) := "101";
constant SEND_UNKNOWN_REQUEST_SLV : std_logic_vector(2 downto 0) := "111";
+
+ constant NUMBER_OF_WORDS_PER_BLOCK: integer := BLOCKSIZE/4;
signal dma_descriptors_s : dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
signal dma_descriptors_25_r_s : dma_descriptors_type(0 to 7);
@@ -750,8 +753,8 @@ end process;
fromhost_pfull_threshold_assert_s <= std_logic_vector(to_unsigned(10, 9));
fromhost_pfull_threshold_negate_s <= std_logic_vector(to_unsigned(6, 9));
- tohost_pfull_threshold_assert_s <= std_logic_vector(to_unsigned(4050, 12));
- tohost_pfull_threshold_negate_s <= std_logic_vector(to_unsigned(3744, 12));
+ tohost_pfull_threshold_assert_s <= std_logic_vector(to_unsigned(4095-(NUMBER_OF_WORDS_PER_BLOCK/8)*2, 12));
+ tohost_pfull_threshold_negate_s <= std_logic_vector(to_unsigned(4095-(NUMBER_OF_WORDS_PER_BLOCK/8)*3, 12));
busy_threshold_assert <= REG_BUSY_THRESH_ASSERT_C;
busy_threshold_negate <= REG_BUSY_THRESH_NEGATE_C;
diff --git a/sources/templates/pcie_package.vhd b/sources/templates/pcie_package.vhd
index 4c622fcb93a2baba48e538e84b3ca90600fe7cf8..fb1a9dfc5ea7cbb8a93ef42311efbcc51726da5f 100644
--- a/sources/templates/pcie_package.vhd
+++ b/sources/templates/pcie_package.vhd
@@ -985,6 +985,11 @@ package pcie_package is
constant REG_TTC_BUSY_TIMING_CTRL : std_logic_vector(19 downto 0) := x"084b0";
constant REG_TTC_BUSY_CLEAR : std_logic_vector(19 downto 0) := x"084c0";
constant REG_TTC_EMU_CONTROL : std_logic_vector(19 downto 0) := x"084d0";
+ constant REG_TTC_EMU_L1A_PERIOD : std_logic_vector(19 downto 0) := x"084e0";
+ constant REG_TTC_EMU_ECR_PERIOD : std_logic_vector(19 downto 0) := x"084f0";
+ constant REG_TTC_EMU_BCR_PERIOD : std_logic_vector(19 downto 0) := x"08500";
+ constant REG_TTC_EMU_LONG_CHANNEL_DATA : std_logic_vector(19 downto 0) := x"08510";
+ constant REG_TTC_EMU_RESET : std_logic_vector(19 downto 0) := x"08520";
--** XOFF_BUSYControlsAndMonitors
constant REG_XOFF_FM_CH_FIFO_THRESH_LOW : std_logic_vector(19 downto 0) := x"08800";
@@ -1395,17 +1400,15 @@ package pcie_package is
constant REG_MROD_EP1_RXRESET : std_logic_vector(19 downto 0) := x"0d110";
constant REG_MROD_EP1_TXRESET : std_logic_vector(19 downto 0) := x"0d120";
- --** MROD_EP0monitors
- constant REG_MROD_EP0_CSMH_EMPTY : std_logic_vector(19 downto 0) := x"0e000";
- constant REG_MROD_EP0_CSMH_FULL : std_logic_vector(19 downto 0) := x"0e010";
- constant REG_MROD_EP0_RXLOCKED : std_logic_vector(19 downto 0) := x"0e020";
- constant REG_MROD_EP0_TXLOCKED : std_logic_vector(19 downto 0) := x"0e030";
-
- --** MROD_EP1monitors
- constant REG_MROD_EP1_CSMH_EMPTY : std_logic_vector(19 downto 0) := x"0e700";
- constant REG_MROD_EP1_CSMH_FULL : std_logic_vector(19 downto 0) := x"0e710";
- constant REG_MROD_EP1_RXLOCKED : std_logic_vector(19 downto 0) := x"0e720";
- constant REG_MROD_EP1_TXLOCKED : std_logic_vector(19 downto 0) := x"0e730";
+ --** MRODmonitors
+ constant REG_MROD_EP0_CSMH_EMPTY : std_logic_vector(19 downto 0) := x"0d800";
+ constant REG_MROD_EP0_CSMH_FULL : std_logic_vector(19 downto 0) := x"0d810";
+ constant REG_MROD_EP0_RXLOCKED : std_logic_vector(19 downto 0) := x"0d820";
+ constant REG_MROD_EP0_TXLOCKED : std_logic_vector(19 downto 0) := x"0d830";
+ constant REG_MROD_EP1_CSMH_EMPTY : std_logic_vector(19 downto 0) := x"0d840";
+ constant REG_MROD_EP1_CSMH_FULL : std_logic_vector(19 downto 0) := x"0d850";
+ constant REG_MROD_EP1_RXLOCKED : std_logic_vector(19 downto 0) := x"0d860";
+ constant REG_MROD_EP1_TXLOCKED : std_logic_vector(19 downto 0) := x"0d870";
-----------------------------------
---- GENERATED code END #1 ## ----
-----------------------------------
@@ -1624,20 +1627,11 @@ package pcie_package is
LIMIT_TIME : std_logic_vector(15 downto 0); -- Number of prescaled clocks a given busy must be asserted before it is recognized
end record;
- type bitfield_ttc_emu_control_t_type is record
- WE : std_logic_vector(64 downto 64); -- Any write to this register executes a write enable
- LAST_LINE : std_logic_vector(35 downto 35); -- Last line of the sequence
- REPEAT : std_logic_vector(34 downto 34); -- Repeat the sequence
- BROADCAST5 : std_logic_vector(32 downto 32); -- Broadcast 5
- BROADCAST4 : std_logic_vector(31 downto 31); -- Broadcast 4
- BROADCAST3 : std_logic_vector(30 downto 30); -- Broadcast 3
- BROADCAST2 : std_logic_vector(29 downto 29); -- Broadcast 2
- BROADCAST1 : std_logic_vector(28 downto 28); -- Broadcast 1
- BROADCAST0 : std_logic_vector(27 downto 27); -- Broadcast 0
+ type bitfield_ttc_emu_control_w_type is record
+ BROADCAST : std_logic_vector(32 downto 27); -- Broadcast data
ECR : std_logic_vector(26 downto 26); -- Event counter reset
BCR : std_logic_vector(25 downto 25); -- Bunch counter reset
L1A : std_logic_vector(24 downto 24); -- Level 1 Accept
- STEP_COUNTER : std_logic_vector(21 downto 0); -- Step counter value
end record;
type bitfield_xoff_fm_high_thresh_t_type is record
@@ -1942,7 +1936,12 @@ package pcie_package is
TTC_DELAY : bitfield_ttc_delay_w_array_type; -- Controls the TTC Fanout delay values
TTC_BUSY_TIMING_CTRL : bitfield_ttc_busy_timing_ctrl_w_type; -- TTC and BUSY Controls and Monitors
TTC_BUSY_CLEAR : std_logic_vector(64 downto 64); -- clears the latching busy bits in TTC_BUSY_ACCEPTED
- TTC_EMU_CONTROL : bitfield_ttc_emu_control_t_type; -- TTC and BUSY Controls and Monitors
+ TTC_EMU_CONTROL : bitfield_ttc_emu_control_w_type; -- TTC and BUSY Controls and Monitors
+ TTC_EMU_L1A_PERIOD : std_logic_vector(31 downto 0); -- L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
+ TTC_EMU_ECR_PERIOD : std_logic_vector(31 downto 0); -- ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
+ TTC_EMU_BCR_PERIOD : std_logic_vector(31 downto 0); -- BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
+ TTC_EMU_LONG_CHANNEL_DATA : std_logic_vector(31 downto 0); -- Long channel data for the TTC emulator
+ TTC_EMU_RESET : std_logic_vector(64 downto 64); -- Any write to this register resets the TTC Emulator to the default state.
XOFF_FM_CH_FIFO_THRESH_LOW : std_logic_vector(3 downto 0); -- Controls the low threshold of the channel fifo in FULL mode on which
-- an Xon will be asserted, bitfields control 4 MSB
@@ -4912,35 +4911,35 @@ package pcie_package is
constant REG_CR_REVERSE_10B_TOHOST_C : std_logic_vector(0 downto 0) := "1"; -- 1: Receive 10-bit word in ToHost EPROCS, MSB first
-- 0: Receive 10-bit word in ToHost EPROCS, LSB first
- constant REG_CR_LTDB_TTC_DELAY_EGROUP4_EPATH6_C : std_logic_vector(7 downto 7) := "0"; -- Egroup 4, Epath 6
+ constant REG_CR_LTDB_TTC_DELAY_EGROUP4_EPATH6_C : std_logic_vector(7 downto 7) := "1"; -- Egroup 4, Epath 6
-- 1: Half a clock delay
-- 0: no delay
- constant REG_CR_LTDB_TTC_DELAY_EGROUP4_EPATH5_C : std_logic_vector(6 downto 6) := "0"; -- Egroup 4, Epath 5
+ constant REG_CR_LTDB_TTC_DELAY_EGROUP4_EPATH5_C : std_logic_vector(6 downto 6) := "1"; -- Egroup 4, Epath 5
-- 1: Half a clock delay
-- 0: no delay
- constant REG_CR_LTDB_TTC_DELAY_EGROUP4_EPATH4_C : std_logic_vector(5 downto 5) := "0"; -- Egroup 4, Epath 4
+ constant REG_CR_LTDB_TTC_DELAY_EGROUP4_EPATH4_C : std_logic_vector(5 downto 5) := "1"; -- Egroup 4, Epath 4
-- 1: Half a clock delay
-- 0: no delay
- constant REG_CR_LTDB_TTC_DELAY_EGROUP4_EPATH3_C : std_logic_vector(4 downto 4) := "0"; -- Egroup 4, Epath 3
+ constant REG_CR_LTDB_TTC_DELAY_EGROUP4_EPATH3_C : std_logic_vector(4 downto 4) := "1"; -- Egroup 4, Epath 3
-- 1: Half a clock delay
-- 0: no delay
- constant REG_CR_LTDB_TTC_DELAY_EGROUP4_EPATH0_C : std_logic_vector(3 downto 3) := "0"; -- Egroup 4, Epath 0
+ constant REG_CR_LTDB_TTC_DELAY_EGROUP4_EPATH0_C : std_logic_vector(3 downto 3) := "1"; -- Egroup 4, Epath 0
-- 1: Half a clock delay
-- 0: no delay
- constant REG_CR_LTDB_TTC_DELAY_EGROUP3_C : std_logic_vector(2 downto 2) := "0"; -- Egroup 3, Epath 0
+ constant REG_CR_LTDB_TTC_DELAY_EGROUP3_C : std_logic_vector(2 downto 2) := "1"; -- Egroup 3, Epath 0
-- 1: Half a clock delay
-- 0: no delay
- constant REG_CR_LTDB_TTC_DELAY_EGROUP2_C : std_logic_vector(1 downto 1) := "0"; -- Egroup 2, Epath 0
+ constant REG_CR_LTDB_TTC_DELAY_EGROUP2_C : std_logic_vector(1 downto 1) := "1"; -- Egroup 2, Epath 0
-- 1: Half a clock delay
-- 0: no delay
- constant REG_CR_LTDB_TTC_DELAY_EGROUP1_C : std_logic_vector(0 downto 0) := "0"; -- Egroup 1, Epath 0
+ constant REG_CR_LTDB_TTC_DELAY_EGROUP1_C : std_logic_vector(0 downto 0) := "1"; -- Egroup 1, Epath 0
-- 1: Half a clock delay
-- 0: no delay
@@ -5243,19 +5242,15 @@ package pcie_package is
constant REG_TTC_BUSY_TIMING_CTRL_BUSY_WIDTH_C : std_logic_vector(31 downto 16) := x"000f"; -- Minimum number of 40MHz clocks that the busy is asserted
constant REG_TTC_BUSY_TIMING_CTRL_LIMIT_TIME_C : std_logic_vector(15 downto 0) := x"000f"; -- Number of prescaled clocks a given busy must be asserted before it is recognized
constant REG_TTC_BUSY_CLEAR_C : std_logic_vector(64 downto 64) := "0"; -- clears the latching busy bits in TTC_BUSY_ACCEPTED
- constant REG_TTC_EMU_CONTROL_WE_C : std_logic_vector(64 downto 64) := "0"; -- Any write to this register executes a write enable
- constant REG_TTC_EMU_CONTROL_LAST_LINE_C : std_logic_vector(35 downto 35) := "0"; -- Last line of the sequence
- constant REG_TTC_EMU_CONTROL_REPEAT_C : std_logic_vector(34 downto 34) := "0"; -- Repeat the sequence
- constant REG_TTC_EMU_CONTROL_BROADCAST5_C : std_logic_vector(32 downto 32) := "0"; -- Broadcast 5
- constant REG_TTC_EMU_CONTROL_BROADCAST4_C : std_logic_vector(31 downto 31) := "0"; -- Broadcast 4
- constant REG_TTC_EMU_CONTROL_BROADCAST3_C : std_logic_vector(30 downto 30) := "0"; -- Broadcast 3
- constant REG_TTC_EMU_CONTROL_BROADCAST2_C : std_logic_vector(29 downto 29) := "0"; -- Broadcast 2
- constant REG_TTC_EMU_CONTROL_BROADCAST1_C : std_logic_vector(28 downto 28) := "0"; -- Broadcast 1
- constant REG_TTC_EMU_CONTROL_BROADCAST0_C : std_logic_vector(27 downto 27) := "0"; -- Broadcast 0
+ constant REG_TTC_EMU_CONTROL_BROADCAST_C : std_logic_vector(32 downto 27) := "000000"; -- Broadcast data
constant REG_TTC_EMU_CONTROL_ECR_C : std_logic_vector(26 downto 26) := "0"; -- Event counter reset
constant REG_TTC_EMU_CONTROL_BCR_C : std_logic_vector(25 downto 25) := "0"; -- Bunch counter reset
constant REG_TTC_EMU_CONTROL_L1A_C : std_logic_vector(24 downto 24) := "0"; -- Level 1 Accept
- constant REG_TTC_EMU_CONTROL_STEP_COUNTER_C : std_logic_vector(21 downto 0) := "0000000000000000000000"; -- Step counter value
+ constant REG_TTC_EMU_L1A_PERIOD_C : std_logic_vector(31 downto 0) := x"00000000"; -- L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
+ constant REG_TTC_EMU_ECR_PERIOD_C : std_logic_vector(31 downto 0) := x"00000000"; -- ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
+ constant REG_TTC_EMU_BCR_PERIOD_C : std_logic_vector(31 downto 0) := x"00000dec"; -- BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
+ constant REG_TTC_EMU_LONG_CHANNEL_DATA_C : std_logic_vector(31 downto 0) := x"00000000"; -- Long channel data for the TTC emulator
+ constant REG_TTC_EMU_RESET_C : std_logic_vector(64 downto 64) := "0"; -- Any write to this register resets the TTC Emulator to the default state.
constant REG_XOFF_FM_CH_FIFO_THRESH_LOW_C : std_logic_vector(3 downto 0) := x"b"; -- Controls the low threshold of the channel fifo in FULL mode on which
-- an Xon will be asserted, bitfields control 4 MSB
@@ -6350,22 +6345,15 @@ end record;
WISHBONE_STATUS : bitfield_wishbone_status_r_type;
end record;
--
--- MROD_EP0monitors
+-- MRODmonitors
--
- -- MROD_EP0monitors
- type regmap_mrodEP0_monitor_type is record
+ -- MRODmonitors
+ type regmap_mrod_monitor_type is record
MROD_EP0_CSMH_EMPTY : std_logic_vector(23 downto 0); -- CSM Handler FIFO Empty 23-0
MROD_EP0_CSMH_FULL : std_logic_vector(23 downto 0); -- CSM Handler FIFO Full 23-0
MROD_EP0_RXLOCKED : std_logic_vector(23 downto 0); -- EP0 Receiver Locked monitor 23-0
MROD_EP0_TXLOCKED : std_logic_vector(23 downto 0); -- EP0 Transmitter Locked monitor 23-0
-end record;
---
--- MROD_EP1monitors
---
-
- -- MROD_EP1monitors
- type regmap_mrodEP1_monitor_type is record
MROD_EP1_CSMH_EMPTY : std_logic_vector(23 downto 0); -- CSM Handler FIFO Empty 23-0
MROD_EP1_CSMH_FULL : std_logic_vector(23 downto 0); -- CSM Handler FIFO Full 23-0
MROD_EP1_RXLOCKED : std_logic_vector(23 downto 0); -- EP1 Receiver Locked monitor 23-0
@@ -6384,8 +6372,7 @@ end record;
register_map_hk_monitor : register_map_hk_monitor_type;
register_map_generators : register_map_generators_type;
wishbone_monitor : wishbone_monitor_type;
- regmap_mrodEP0_monitor : regmap_mrodEP0_monitor_type;
- regmap_mrodEP1_monitor : regmap_mrodEP1_monitor_type;
+ regmap_mrod_monitor : regmap_mrod_monitor_type;
end record;
-----------------------------------
---- GENERATED code END #4 ## ----
@@ -6398,4 +6385,4 @@ package body pcie_package is
begin
return A(A'low);
end function to_sl;
-end pcie_package;
\ No newline at end of file
+end pcie_package;
diff --git a/sources/templates/pcie_package.vhd.template b/sources/templates/pcie_package.vhd.template
index 5d2a76452eecba5d3d2bf451a51315b7c53b51d2..5983ff4f8be48debe7be5eb5281d27b43a175217 100644
--- a/sources/templates/pcie_package.vhd.template
+++ b/sources/templates/pcie_package.vhd.template
@@ -392,3 +392,4 @@ package body pcie_package is
return A(A'low);
end function to_sl;
end pcie_package;
+
diff --git a/sources/templates/registermap.tex b/sources/templates/registermap.tex
index de659f2ac6fa956ac73bb26fe43e9aca387644ff..3da93f9d3ab5ed01fe7cee6a9de4ad30c00f5bef 100644
--- a/sources/templates/registermap.tex
+++ b/sources/templates/registermap.tex
@@ -6,11 +6,11 @@
% DO NOT EDIT THIS FILE
%
% This file was generated from template 'registermap.tex.template'
-% and register map registers-4.9.yaml, version 4.9
+% and register map registers-4.10.yaml, version 4.10
% by the script 'wuppercodegen', version: 0.8.0,
% using the following commandline:
%
-% ../../../software/wuppercodegen/wuppercodegen/cli.py registers-4.9.yaml registermap.tex.template registermap.tex
+% ../../../software/wuppercodegen/wuppercodegen/cli.py registers-4.10.yaml registermap.tex.template registermap.tex
%
% Please do NOT edit this file, but edit the source file at 'registermap.tex.template'
%
@@ -20,7 +20,7 @@
% ***************************************************************************
% ***************************************************************************
-\section{FELIX register map, version 4.9}
+\section{FELIX register map, version 4.10}
Starting from the offset address of BAR0, BAR1 and BAR2, the register map for BAR0 expands from 0x0000 to 0x0430 for the PCIe control registers. BAR0 only contains registers associated with DMA. The offset for BAR0 is usually 0xFBB00000.
@@ -176,7 +176,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
\multicolumn{7}{|c|}{Generic Board Information} \\
\hline
0x0000 & 0,1 & \multicolumn{2}{l|}{REG\_MAP\_VERSION} &
-15:0 & R & Register Map Version, 4.9 formatted as 0x0409 \\
+15:0 & R & Register Map Version, 4.10 formatted as 0x0410 \\
\hline
0x0010 & 0,1 & \multicolumn{2}{l|}{BOARD\_ID\_TIMESTAMP} &
39:0 & R & Board ID Date / Time in BCD format YYMMDDhhmm \\
@@ -213,7 +213,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
0x00D0 & 0,1 & \multicolumn{2}{l|}{OPTO\_TRX\_NUM} &
7:0 & R & Number of optical transceivers in the design \\
\hline
-0x00E0 & 0,1 & \multicolumn{2}{l|}{TTC\_EMU\_CONST} &
+0x00E0 & 0,1 & \multicolumn{2}{l|}{TTC\_EMU\_CONST\_GENERATE\_TTC\_EMU} &
1 & R & 1 when TTC emulator is generated \\
\hline
\multicolumn{7}{|c|}{INCLUDE\_EGROUPS} \\
@@ -248,7 +248,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
0 & R & GBT is configured in Wide mode \\
\hline
0x0190 & 0,1 & \multicolumn{2}{l|}{FIRMWARE\_MODE} &
-3:0 & R & 0: GBT mode\newline 1: FULL mode\newline 2: LTDB mode (GBT mode with only IC and TTC links)\newline 3: FEI4 mode\newline 4: ITK Pixel\newline 5: ITK Strip\newline 6: FELIG\newline 7: FULL mode emulator\newline \newline \\
+3:0 & R & 0: GBT mode\newline 1: FULL mode\newline 2: LTDB mode (GBT mode with only IC and TTC links)\newline 3: FEI4 mode\newline 4: ITK Pixel\newline 5: ITK Strip\newline 6: FELIG\newline 7: FULL mode emulator\newline 8: FELIX\_MROD mode\newline \newline \\
\hline
0x01A0 & 0,1 & \multicolumn{2}{l|}{GTREFCLK\_SOURCE} &
1:0 & R & 0: Transceiver reference Clock source from Si5345\newline 1: Transceiver reference Clock source from Si5324\newline 2: Transceiver reference Clock from internal BUFG (GREFCLK)\newline \\
@@ -536,7 +536,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
35:0 & R & read emu ram data \\
\hline
0x5070 & 0, 1 & \multicolumn{2}{l|}{CR\_FM\_PATH\_ENA} &
-11:0 & W & FULL mode CR enable array, every bit is one path \\
+23:0 & W & FULL mode CR enable array, every bit is one path \\
\hline
\multicolumn{7}{|c|}{PATH\_HAS\_STREAM\_ID} \\
\hline
@@ -807,51 +807,33 @@ any & T & clears the latching busy bits in TTC\_BUSY\_ACCEPTED \\
\hline
0x84D0 & 0 & \multicolumn{5}{l|}{TTC\_EMU\_CONTROL} \\
\cline{3-7}
- & & & WE & any & T & Any write to this register executes a write enable \\
- & & & LAST\_LINE & 35 & W & Last line of the sequence \\
- & & & REPEAT & 34 & W & Repeat the sequence \\
- & & & BROADCAST5 & 32 & W & Broadcast 5 \\
- & & & BROADCAST4 & 31 & W & Broadcast 4 \\
- & & & BROADCAST3 & 30 & W & Broadcast 3 \\
- & & & BROADCAST2 & 29 & W & Broadcast 2 \\
- & & & BROADCAST1 & 28 & W & Broadcast 1 \\
- & & & BROADCAST0 & 27 & W & Broadcast 0 \\
+ & & & BROADCAST & 32:27 & W & Broadcast data \\
& & & ECR & 26 & W & Event counter reset \\
& & & BCR & 25 & W & Bunch counter reset \\
& & & L1A & 24 & W & Level 1 Accept \\
- & & & STEP\_COUNTER & 21:0 & W & Step counter value \\
+\hline
+0x84E0 & 0 & \multicolumn{2}{l|}{TTC\_EMU\_L1A\_PERIOD} &
+31:0 & W & L1A period in BC. 0 means manual L1A with TTC\_EMU\_CONTROL.L1A \\
+\hline
+0x84F0 & 0 & \multicolumn{2}{l|}{TTC\_EMU\_ECR\_PERIOD} &
+31:0 & W & ECR period in BC. 0 means manual ECR with TTC\_EMU\_CONTROL.ECR \\
+\hline
+0x8500 & 0 & \multicolumn{2}{l|}{TTC\_EMU\_BCR\_PERIOD} &
+31:0 & W & BCR period in BC. 0 means manual BCR with TTC\_EMU\_CONTROL.BCR \\
+\hline
+0x8510 & 0 & \multicolumn{2}{l|}{TTC\_EMU\_LONG\_CHANNEL\_DATA} &
+31:0 & W & Long channel data for the TTC emulator \\
+\hline
+0x8520 & 0 & \multicolumn{2}{l|}{TTC\_EMU\_RESET} &
+any & T & Any write to this register resets the TTC Emulator to the default state. \\
\hline
\multicolumn{7}{|c|}{XOFF\_BUSY Controls And Monitors} \\
\hline
-0x8800 & 0, 1 & \multicolumn{5}{l|}{XOFF\_FM\_CH\_FIFO\_THRESH\_LOW} \\
-\cline{3-7}
- & & & CH11 & 47:44 & W & Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB \\
- & & & CH10 & 43:40 & W & Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB \\
- & & & CH09 & 39:36 & W & Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB \\
- & & & CH08 & 35:32 & W & Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB \\
- & & & CH07 & 31:28 & W & Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB \\
- & & & CH06 & 27:24 & W & Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB \\
- & & & CH05 & 23:20 & W & Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB \\
- & & & CH04 & 19:16 & W & Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB \\
- & & & CH03 & 15:12 & W & Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB \\
- & & & CH02 & 11:8 & W & Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB \\
- & & & CH01 & 7:4 & W & Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB \\
- & & & CH00 & 3:0 & W & Controls the low theshold of the channel fifo in FULL mode on which an Xon will be asserted, bitfields control 4 MSB \\
-\hline
-0x8810 & 0, 1 & \multicolumn{5}{l|}{XOFF\_FM\_CH\_FIFO\_THRESH\_HIGH} \\
-\cline{3-7}
- & & & CH11 & 47:44 & W & Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB \\
- & & & CH10 & 43:40 & W & Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB \\
- & & & CH09 & 39:36 & W & Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB \\
- & & & CH08 & 35:32 & W & Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB \\
- & & & CH07 & 31:28 & W & Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB \\
- & & & CH06 & 27:24 & W & Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB \\
- & & & CH05 & 23:20 & W & Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB \\
- & & & CH04 & 19:16 & W & Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB \\
- & & & CH03 & 15:12 & W & Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB \\
- & & & CH02 & 11:8 & W & Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB \\
- & & & CH01 & 7:4 & W & Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB \\
- & & & CH00 & 3:0 & W & Controls the high theshold of the channel fifo in FULL mode on which an Xoff will be asserted, bitfields control 4 MSB \\
+0x8800 & 0, 1 & \multicolumn{2}{l|}{XOFF\_FM\_CH\_FIFO\_THRESH\_LOW} &
+3:0 & W & Controls the low threshold of the channel fifo in FULL mode on which\newline an Xon will be asserted, bitfields control 4 MSB\newline \\
+\hline
+0x8810 & 0, 1 & \multicolumn{2}{l|}{XOFF\_FM\_CH\_FIFO\_THRESH\_HIGH} &
+3:0 & W & Controls the high threshold of the channel fifo in FULL mode on which\newline an Xoff will be asserted, bitfields control 4 MSB\newline \\
\hline
0x8820 & 0, 1 & \multicolumn{2}{l|}{XOFF\_FM\_LOW\_THRESH\_CROSSED} &
23:0 & R & FIFO filled beyond the low threshold, 1 bit per channel \\
@@ -1305,6 +1287,93 @@ any & T & clears the latching busy bits in TTC\_BUSY\_ACCEPTED \\
& & & ACKNOWLEDGE & 1 & R & Indicates the termination of a normal bus cycle \\
& & & ERROR & 0 & R & Address not mapped by the crossbar \\
\hline
+\multicolumn{7}{|c|}{MRO Dregisters} \\
+\hline
+0xD000 & 0 & \multicolumn{5}{l|}{MROD\_CTRL} \\
+\cline{3-7}
+ & & & OPTIONS & 15:4 & W & Extra options for MROD \\
+ & & & GOLTESTMODE & 3:0 & W & GOL Test Mode (emulate CSM):\newline 0: Run Data Emulator when 1; 0: stop, load emulator fifo\newline 1: Enable Circulate when 1; 0: send fifo data only once\newline 2: Enable Triggered Mode when 1; 0: run continueously (no TTC)\newline 3: Enable pattern generator when 1; 0: off\newline \\
+\hline
+0xD010 & 0 & \multicolumn{2}{l|}{MROD\_EP0\_CSMENABLE} &
+23:0 & W & EP0 CSM Data Enable channel 23-0 \\
+\hline
+0xD020 & 0 & \multicolumn{2}{l|}{MROD\_EP0\_EMPTYSUPPR} &
+23:0 & W & EP0 Set Empty Suppression channel 23-0 \\
+\hline
+0xD030 & 0 & \multicolumn{2}{l|}{MROD\_EP0\_HPTDCMODE} &
+23:0 & W & EP0 Set HPTDC Mode channel 23-0 \\
+\hline
+0xD040 & 0 & \multicolumn{2}{l|}{MROD\_EP0\_CLRFIFOS} &
+23:0 & W & EP0 Clear FIFOs channel 23-0 \\
+\hline
+0xD050 & 0 & \multicolumn{2}{l|}{MROD\_EP0\_EMULOADENA} &
+23:0 & W & EP0 Emulator Load Enable channel 23-0 \\
+\hline
+0xD060 & 0 & \multicolumn{2}{l|}{MROD\_EP0\_TRXLOOPBACK} &
+23:0 & W & EP0 Transceiver Loopback Enable channel 23-0 \\
+\hline
+0xD070 & 0 & \multicolumn{2}{l|}{MROD\_EP0\_TXCVRRESET} &
+23:0 & W & EP0 Transceiver Reset all channel 23-0 \\
+\hline
+0xD080 & 0 & \multicolumn{2}{l|}{MROD\_EP0\_RXRESET} &
+23:0 & W & EP0 Receiver Reset channel 23-0 \\
+\hline
+0xD090 & 0 & \multicolumn{2}{l|}{MROD\_EP0\_TXRESET} &
+23:0 & W & EP0 Transmitter Reset channel 23-0 \\
+\hline
+0xD0A0 & 0 & \multicolumn{2}{l|}{MROD\_EP1\_CSMENABLE} &
+23:0 & W & EP1 CSM Data Enable channel 23-0 \\
+\hline
+0xD0B0 & 0 & \multicolumn{2}{l|}{MROD\_EP1\_EMPTYSUPPR} &
+23:0 & W & EP1 Set Empty Suppression channel 23-0 \\
+\hline
+0xD0C0 & 0 & \multicolumn{2}{l|}{MROD\_EP1\_HPTDCMODE} &
+23:0 & W & EP1 Set HPTDC Mode channel 23-0 \\
+\hline
+0xD0D0 & 0 & \multicolumn{2}{l|}{MROD\_EP1\_CLRFIFOS} &
+23:0 & W & EP1 Clear FIFOs channel 23-0 \\
+\hline
+0xD0E0 & 0 & \multicolumn{2}{l|}{MROD\_EP1\_EMULOADENA} &
+23:0 & W & EP1 Emulator Load Enable channel 23-0 \\
+\hline
+0xD0F0 & 0 & \multicolumn{2}{l|}{MROD\_EP1\_TRXLOOPBACK} &
+23:0 & W & EP1 Transceiver Loopback Enable channel 23-0 \\
+\hline
+0xD100 & 0 & \multicolumn{2}{l|}{MROD\_EP1\_TXCVRRESET} &
+23:0 & W & EP1 Transceiver Reset all channel 23-0 \\
+\hline
+0xD110 & 0 & \multicolumn{2}{l|}{MROD\_EP1\_RXRESET} &
+23:0 & W & EP1 Receiver Reset channel 23-0 \\
+\hline
+0xD120 & 0 & \multicolumn{2}{l|}{MROD\_EP1\_TXRESET} &
+23:0 & W & EP1 Transmitter Reset channel 23-0 \\
+\hline
+\multicolumn{7}{|c|}{MRO Dmonitors} \\
+\hline
+0xD800 & 0 & \multicolumn{2}{l|}{MROD\_EP0\_CSMH\_EMPTY} &
+23:0 & R & CSM Handler FIFO Empty 23-0 \\
+\hline
+0xD810 & 0 & \multicolumn{2}{l|}{MROD\_EP0\_CSMH\_FULL} &
+23:0 & R & CSM Handler FIFO Full 23-0 \\
+\hline
+0xD820 & 0 & \multicolumn{2}{l|}{MROD\_EP0\_RXLOCKED} &
+23:0 & R & EP0 Receiver Locked monitor 23-0 \\
+\hline
+0xD830 & 0 & \multicolumn{2}{l|}{MROD\_EP0\_TXLOCKED} &
+23:0 & R & EP0 Transmitter Locked monitor 23-0 \\
+\hline
+0xD840 & 0 & \multicolumn{2}{l|}{MROD\_EP1\_CSMH\_EMPTY} &
+23:0 & R & CSM Handler FIFO Empty 23-0 \\
+\hline
+0xD850 & 0 & \multicolumn{2}{l|}{MROD\_EP1\_CSMH\_FULL} &
+23:0 & R & CSM Handler FIFO Full 23-0 \\
+\hline
+0xD860 & 0 & \multicolumn{2}{l|}{MROD\_EP1\_RXLOCKED} &
+23:0 & R & EP1 Receiver Locked monitor 23-0 \\
+\hline
+0xD870 & 0 & \multicolumn{2}{l|}{MROD\_EP1\_TXLOCKED} &
+23:0 & R & EP1 Transmitter Locked monitor 23-0 \\
+\hline
\caption{FELIX register map BAR2}\label{tab:dma_register_map_bar2} \\
\end{longtabu}
%\end{landscape}
diff --git a/sources/templates/registers-4.10.yaml b/sources/templates/registers-4.10.yaml
index d9cb90f12570a141961d7fe08ffb79284050d30c..81db7581f64dc70130e974c2b78bcf7f24d5332b 100644
--- a/sources/templates/registers-4.10.yaml
+++ b/sources/templates/registers-4.10.yaml
@@ -85,14 +85,9 @@ Monitorsections:
bitfield:
- range: 0..0
type: R
- - name: MROD_EP0monitors
- record_name: regmap_mrodEP0_monitor
- bitfield:
- - range: 0..0
- type: R
- - name: MROD_EP1monitors
- record_name: regmap_mrodEP1_monitor
- bitfield:
+ - name: MRODmonitors
+ record_name: regmap_mrod_monitor
+ bitfield:
- range: 0..0
type: R
@@ -298,11 +293,9 @@ Bar2:
- ref: Wishbone
offset: 0xC000
- ref: MRODregisters
- offset: 0xD000
- - ref: MROD_EP0monitors
- offset: 0xE000
- - ref: MROD_EP1monitors
- offset: 0xE700
+ offset: 0xD000
+ - ref: MRODmonitors
+ offset: 0xD800
GenericBoardInformation:
group: GEN
@@ -631,56 +624,56 @@ CentralRouterControlsAndMonitors:
bitfield:
- range: 7
name: EGROUP4_EPATH6
- default: 0
+ default: 1
desc: |
Egroup 4, Epath 6
1: Half a clock delay
0: no delay
- range: 6
name: EGROUP4_EPATH5
- default: 0
+ default: 1
desc: |
Egroup 4, Epath 5
1: Half a clock delay
0: no delay
- range: 5
name: EGROUP4_EPATH4
- default: 0
+ default: 1
desc: |
Egroup 4, Epath 4
1: Half a clock delay
0: no delay
- range: 4
name: EGROUP4_EPATH3
- default: 0
+ default: 1
desc: |
Egroup 4, Epath 3
1: Half a clock delay
0: no delay
- range: 3
name: EGROUP4_EPATH0
- default: 0
+ default: 1
desc: |
Egroup 4, Epath 0
1: Half a clock delay
0: no delay
- range: 2
name: EGROUP3
- default: 0
+ default: 1
desc: |
Egroup 3, Epath 0
1: Half a clock delay
0: no delay
- range: 1
name: EGROUP2
- default: 0
+ default: 1
desc: |
Egroup 2, Epath 0
1: Half a clock delay
0: no delay
- range: 0
name: EGROUP1
- default: 0
+ default: 1
desc: |
Egroup 1, Epath 0
1: Half a clock delay
@@ -1551,35 +1544,9 @@ TTCBUSYControlsAndMonitors:
- name: TTC_EMU_CONTROL
type: W
bitfield:
- - range: any
- name: WE
- type: T
- desc: Any write to this register executes a write enable
- value: 1
- - range: 35
- name: LAST_LINE
- desc: Last line of the sequence
- - range: 34
- name: REPEAT
- desc: Repeat the sequence
- - range: 32
- name: BROADCAST5
- desc: Broadcast 5
- - range: 31
- name: BROADCAST4
- desc: Broadcast 4
- - range: 30
- name: BROADCAST3
- desc: Broadcast 3
- - range: 29
- name: BROADCAST2
- desc: Broadcast 2
- - range: 28
- name: BROADCAST1
- desc: Broadcast 1
- - range: 27
- name: BROADCAST0
- desc: Broadcast 0
+ - range: 32..27
+ name: BROADCAST
+ desc: Broadcast data
- range: 26
name: ECR
desc: Event counter reset
@@ -1589,9 +1556,41 @@ TTCBUSYControlsAndMonitors:
- range: 24
name: L1A
desc: Level 1 Accept
- - range: 21..0
- name: STEP_COUNTER
- desc: Step counter value
+
+ - name: TTC_EMU_L1A_PERIOD
+ type: W
+ desc: L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
+ bitfield:
+ - range: 31..0
+
+ - name: TTC_EMU_ECR_PERIOD
+ type: W
+ desc: ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
+ bitfield:
+ - range: 31..0
+
+ - name: TTC_EMU_BCR_PERIOD
+ type: W
+ desc: BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
+ bitfield:
+ - range: 31..0
+ default: 3564
+
+ - name: TTC_EMU_LONG_CHANNEL_DATA
+ type: W
+ desc: Long channel data for the TTC emulator
+ bitfield:
+ - range: 31..0
+
+ - name: TTC_EMU_RESET
+ desc: Any write to this register resets the TTC Emulator to the default state.
+ type: W
+ bitfield:
+ - range: any
+ value: 1
+ type: T
+
+
TTC_DEC_CTRLMON:
group: TDCM
@@ -2918,7 +2917,7 @@ MRODregisters:
desc: EP1 Transmitter Reset channel 23-0
default: 0
-MROD_EP0monitors:
+MRODmonitors:
group: MROD
desc: Specific registers for MROD
endpoints: 0
@@ -2944,13 +2943,6 @@ MROD_EP0monitors:
bitfield:
- range: 23..0
desc: EP0 Transmitter Locked monitor 23-0
-
-MROD_EP1monitors:
- group: MROD
- desc: Specific registers for MROD
- endpoints: 0
- generate: MROD_GENERATE_REGS = true
- entries:
- name: MROD_EP1_CSMH_EMPTY
type: R
bitfield:
@@ -2971,3 +2963,5 @@ MROD_EP1monitors:
bitfield:
- range: 23..0
desc: EP1 Transmitter Locked monitor 23-0
+
+#
diff --git a/sources/templates/registers-5.0.yaml b/sources/templates/registers-5.0.yaml
old mode 100755
new mode 100644
diff --git a/sources/templates/registers.pdf b/sources/templates/registers.pdf
index 14a503da52ce18282e754c586092f61f92002284..c8a42605b797e41e5cb7398c55c60561f2ca03b1 100644
Binary files a/sources/templates/registers.pdf and b/sources/templates/registers.pdf differ
diff --git a/sources/templates/registers.tex b/sources/templates/registers.tex
index de1f646abe20e804569b3fd15155ab525e391ff3..755b04264e73dc6ad1d6bdd4224c756067e33b67 100644
--- a/sources/templates/registers.tex
+++ b/sources/templates/registers.tex
@@ -2,8 +2,8 @@
\author{FELIX Team}
\input{et_template/template.tex}
\date{\SetDocumentDate}
-\def\DocVer{Rev 4.0}
-\def\SetDocumentDate{19-12-2017}
+\def\DocVer{Rev 4.10}
+\def\SetDocumentDate{03-04-2020}
\begin{document}
\chapter{\input{registermap.tex}}
\end{document}