diff --git a/sources/templates/registermap.tex b/sources/templates/registermap.tex
index 642d4dc0894acd8f7449c4338f149e9f853c60b9..ba25ed67c821d8a2fa44507b47259bc783703fec 100644
--- a/sources/templates/registermap.tex
+++ b/sources/templates/registermap.tex
@@ -6,11 +6,11 @@
 % DO NOT EDIT THIS FILE
 % 
 % This file was generated from template 'registermap.tex.template'
-% and register map registers-4.7.yaml, version 4.7
+% and register map registers-4.8.yaml, version 4.8
 % by the script 'wuppercodegen', version: 0.8.0,
 % using the following commandline:
 % 
-% ../../../software/wuppercodegen/wuppercodegen/cli.py registers-4.7.yaml registermap.tex.template registermap.tex
+% ../../../software/wuppercodegen/wuppercodegen/cli.py registers-4.8.yaml registermap.tex.template registermap.tex
 % 
 % Please do NOT edit this file, but edit the source file at 'registermap.tex.template'
 % 
@@ -20,7 +20,7 @@
 % ***************************************************************************
 % ***************************************************************************
 
-\section{FELIX register map, version 4.7}
+\section{FELIX register map, version 4.8}
 
 Starting from the offset address of BAR0, BAR1 and BAR2, the register map for BAR0 expands from 0x0000 to 0x0430 for the PCIe control registers. BAR0 only contains registers associated with DMA. The offset for BAR0 is usually 0xFBB00000.
 
@@ -179,7 +179,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
 \multicolumn{7}{|c|}{Generic Board Information} \\
 \hline
 0x0000 & 0,1 & \multicolumn{2}{l|}{REG\_MAP\_VERSION} &
-15:0 & R & Register Map Version, 4.7 formatted as 0x0407 \\
+15:0 & R & Register Map Version, 4.8 formatted as 0x0408 \\
 \hline
 0x0010 & 0,1 & \multicolumn{2}{l|}{BOARD\_ID\_TIMESTAMP} &
 39:0 & R & Board ID Date / Time in BCD format YYMMDDhhmm \\
@@ -230,7 +230,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
 0x00F0 & 0,1 & \multicolumn{2}{l|}{CR\_INTERNAL\_LOOPBACK\_MODE} &
 0 & R & 1 when Central Router internal loopback mode is enabled \\
 \hline
-\multicolumn{7}{|c|}{INCLUDE\_EGROUP} \\
+\multicolumn{7}{|c|}{INCLUDE\_EGROUPS} \\
 \hline
 0x0100 & 0,1 & \multicolumn{5}{l|}{INCLUDE\_EGROUP\_0} \\
 \cline{3-7}
@@ -298,6 +298,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
 \hline
 0x1100 & 0,1 & \multicolumn{5}{l|}{CR\_TOHOST\_GBT00\_EGROUP0\_CTRL} \\
 \cline{3-7}
+ & & & HAS\_STREAM\_ID & 59 & W & link is associated with a stream ID \\
  & & & INSTANT\_TIMEOUT\_ENA & 58:51 & W & instantly initiate a timeout for the given epath \\
  & & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
  & & & MAX\_CHUNK\_LEN & 42:31 & W & set the maximum length of a chunk, 0 disables truncation \\
@@ -308,6 +309,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
 \hline
 0x1160 & 0,1 & \multicolumn{5}{l|}{CR\_TOHOST\_GBT00\_EGROUP6\_CTRL} \\
 \cline{3-7}
+ & & & HAS\_STREAM\_ID & 59 & W & link is associated with a stream ID \\
  & & & INSTANT\_TIMEOUT\_ENA & 58:51 & W & instantly initiate a timeout for the given epath \\
  & & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
  & & & MAX\_CHUNK\_LEN & 42:31 & W & set the maximum length of a chunk, 0 disables truncation \\
@@ -336,6 +338,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
 \hline
 0x2240 & 0,1 & \multicolumn{5}{l|}{CR\_TOHOST\_GBT23\_EGROUP0\_CTRL} \\
 \cline{3-7}
+ & & & HAS\_STREAM\_ID & 59 & W & link is associated with a stream ID \\
  & & & INSTANT\_TIMEOUT\_ENA & 58:51 & W & instantly initiate a timeout for the given epath \\
  & & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
  & & & MAX\_CHUNK\_LEN & 42:31 & W & set the maximum length of a chunk, 0 disables truncation \\
@@ -346,6 +349,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
 \hline
 0x22A0 & 0,1 & \multicolumn{5}{l|}{CR\_TOHOST\_GBT23\_EGROUP6\_CTRL} \\
 \cline{3-7}
+ & & & HAS\_STREAM\_ID & 59 & W & link is associated with a stream ID \\
  & & & INSTANT\_TIMEOUT\_ENA & 58:51 & W & instantly initiate a timeout for the given epath \\
  & & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
  & & & MAX\_CHUNK\_LEN & 42:31 & W & set the maximum length of a chunk, 0 disables truncation \\
@@ -519,7 +523,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
 0x4300 & 0,1 & \multicolumn{2}{l|}{CR\_STATIC\_CONFIGURATION} &
 0 & R & Central Router Controls and Monitors \\
 \hline
-\multicolumn{7}{|c|}{CR\_DEFAULT\_EPROC\_ENA} \\
+\multicolumn{7}{|c|}{CR\_DEFAULT\_EPROC\_ENA\_G} \\
 \hline
 0x4310 & 0,1 & \multicolumn{2}{l|}{CR\_DEFAULT\_EPROC\_ENA0} &
 14:0 & R & Static CR default enable bits \\
@@ -529,7 +533,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
 0x4380 & 0,1 & \multicolumn{2}{l|}{CR\_DEFAULT\_EPROC\_ENA7} &
 14:0 & R & Static CR default enable bits \\
 \hline
-\multicolumn{7}{|c|}{CR\_DEFAULT\_EPROC\_ENCODING} \\
+\multicolumn{7}{|c|}{CR\_DEFAULT\_EPROC\_ENCODING\_G} \\
 \hline
 0x4390 & 0,1 & \multicolumn{2}{l|}{CR\_DEFAULT\_EPROC\_ENCODING0} &
 15:0 & R & Static CR default encoding bits \\
@@ -542,20 +546,6 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
 0x4410 & 0,1 & \multicolumn{2}{l|}{MAX\_TIMEOUT} &
 31:0 & R & Maximum allowed timeout value \\
 \hline
-\multicolumn{7}{|c|}{CR\_BLOCK\_COUNTERS} \\
-\hline
-0x4420 & 0,1 & \multicolumn{5}{l|}{CR\_BLOCK\_COUNT\_GBT00} \\
-\cline{3-7}
- & & & RESET & any & T & Any write clears the counter value \\
- & & & VAL & 31:0 & R & Counts the number of blocks that were transferred ToHost in the specified GBT \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-0x4590 & 0,1 & \multicolumn{5}{l|}{CR\_BLOCK\_COUNT\_GBT23} \\
-\cline{3-7}
- & & & RESET & any & T & Any write clears the counter value \\
- & & & VAL & 31:0 & R & Counts the number of blocks that were transferred ToHost in the specified GBT \\
-\hline
 \multicolumn{7}{|c|}{GBT Emulator Controls And Monitors} \\
 \hline
 0x5000 & 0 & \multicolumn{5}{l|}{GBT\_EMU\_ENA} \\
@@ -589,6 +579,9 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
 0x5070 & 0 & \multicolumn{2}{l|}{CR\_FM\_PATH\_ENA} &
 11:0 & W & FULL mode CR enable array, every bit is one path \\
 \hline
+0x5080 & 0 & \multicolumn{2}{l|}{CR\_FM\_PATH\_HAS\_STREAM\_ID} &
+11:0 & W & FULL mode link is associated with a stream ID \\
+\hline
 \multicolumn{7}{|c|}{GBT Wrapper Controls} \\
 \hline
 0x6400 & 0 & \multicolumn{2}{l|}{GBT\_CHANNEL\_DISABLE} &
@@ -797,7 +790,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
  & & & TH\_FF\_EMPTY & 3 & R & ToHostData Fifo status 1:empty 0:not empty \\
  & & & TTC\_BIT\_ERR & 2:0 & R & double bit, single bit and comm error in TTC data \\
 \hline
-\multicolumn{7}{|c|}{TTC\_BUSY\_ACCEPTED} \\
+\multicolumn{7}{|c|}{TTC\_BUSY\_ACCEPTED\_G} \\
 \hline
 0x8020 & 0,1 & \multicolumn{2}{l|}{TTC\_BUSY\_ACCEPTED00} &
 56:0 & R & busy has been asserted by the given ELINK. Reset by writing to TTC\_BUSY\_CLEAR \\
@@ -1291,6 +1284,33 @@ any & T & Fire a test MSIx interrupt \#4 \\
  & & & SEED & 19:10 & W & Seed for the random number generator, should not be 0 \\
  & & & POLYNOMIAL & 9:0 & W & POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1 \\
 \hline
+\multicolumn{7}{|c|}{Wishbone} \\
+\hline
+0xC000 & 0 & \multicolumn{5}{l|}{WISHBONE\_CONTROL} \\
+\cline{3-7}
+ & & & WRITE\_NOT\_READ & 32 & W & wishbone write command wishbone read command \\
+ & & & ADDRESS & 31:0 & W & Slave address for Wishbone bus \\
+\hline
+0xC010 & 0 & \multicolumn{5}{l|}{WISHBONE\_WRITE} \\
+\cline{3-7}
+ & & & WRITE\_ENABLE & any & T & Any write to this register triggers a write to the Wupper to Wishbone fifo \\
+ & & & FULL & 32 & R & Wishbone \\
+ & & & DATA & 31:0 & W & Wishbone \\
+\hline
+0xC020 & 0 & \multicolumn{5}{l|}{WISHBONE\_READ} \\
+\cline{3-7}
+ & & & READ\_ENABLE & any & T & Any write to this register triggers a read from the Wishbone to Wupper fifo \\
+ & & & EMPTY & 32 & R & Indicates that the Wishbone to Wupper fifo is empty \\
+ & & & DATA & 31:0 & R & Wishbone read data \\
+\hline
+0xC030 & 0 & \multicolumn{5}{l|}{WISHBONE\_STATUS} \\
+\cline{3-7}
+ & & & INT & 4 & R & interrupt \\
+ & & & RETRY & 3 & R & Interface is not ready to accept data cycle should be retried \\
+ & & & STALL & 2 & R & When pipelined mode slave can't accept additional transactions in its queue \\
+ & & & ACKNOWLEDGE & 1 & R & Indicates the termination of a normal bus cycle \\
+ & & & ERROR & 0 & R & Address not mapped by the crossbar \\
+\hline
 \caption{FELIX register map BAR2}\label{tab:dma_register_map_bar2} \\
 \end{longtabu}
 %\end{landscape}
diff --git a/sources/templates/registers.pdf b/sources/templates/registers.pdf
index 55edfea6510cf3ba8ee3804db493411615b44a78..461d72cab48300fc97c35b0268fca311ae2303a9 100644
Binary files a/sources/templates/registers.pdf and b/sources/templates/registers.pdf differ