diff --git a/sources/encoding/encoding.vhd b/sources/encoding/encoding.vhd
index 1278a0da810204ba45a4c273f8bad0d95aea56f5..16f0daea3ac011be1c4f88c37c4514e1c7c81d65 100644
--- a/sources/encoding/encoding.vhd
+++ b/sources/encoding/encoding.vhd
@@ -536,9 +536,12 @@ begin
strips_links: for i in 0 to 3 generate
signal strips_epath_almost_full : std_logic_vector(4 downto 0);
signal strips_rst : std_logic_vector(4 downto 0);
+ signal LCB_DOWNLINK_DATA, R3L1_DOWNLINK_DATA: std_logic_vector(3 downto 0);
+ signal LCB_R3L1_ELINK_SWAP: std_logic;
begin
register_map_encoding_monitor.ENCODING_EGROUP_CTRL(link)(i).EPATH_ALMOST_FULL <= "000" & strips_epath_almost_full;
strips_rst <= not register_map_control.ENCODING_EGROUP_CTRL(link)(i).EPATH_ENA(4 downto 0);
+ LCB_R3L1_ELINK_SWAP <= register_map_control.ITKSTRIP_LCB_R3L1_ELINK_SWAP(4*link+i);
strips_lcb_encoder: entity work.lcb_axi_encoder --@suppress
generic map (
@@ -574,9 +577,14 @@ begin
frame_start_pulse_o => open,
regmap_o => open,
-- output signals
- EdataOUT => lpGBT_DOWNLINK_USER_DATA_s(link)(i*8 + 3 downto i*8)
+ EdataOUT => LCB_DOWNLINK_DATA
);
+ --
+ lpGBT_DOWNLINK_USER_DATA_s(link)(i*8 + 7 downto i*8) <=
+ R3L1_DOWNLINK_DATA & LCB_DOWNLINK_DATA when LCB_R3L1_ELINK_SWAP = '0' else
+ LCB_DOWNLINK_DATA & R3L1_DOWNLINK_DATA;
+
-- Strips R3L1 encoders
strips_r3l1_encoder: entity work.r3l1_axi_encoder--@suppress
generic map (
@@ -609,7 +617,7 @@ begin
-- configuration from global register map
config => strips_config,
-- output signals
- EdataOUT => lpGBT_DOWNLINK_USER_DATA_s(link)(i*8 + 7 downto i*8 + 4)
+ EdataOUT => R3L1_DOWNLINK_DATA
);
end generate strips_links;
end generate g_links;
diff --git a/sources/templates/docs/html/registers-5.0.html b/sources/templates/docs/html/registers-5.0.html
index d5249212f5654c122668c9c34f728994aa897a5d..5e043fcc00c544bf268fbb57a41d755a2075d681 100644
--- a/sources/templates/docs/html/registers-5.0.html
+++ b/sources/templates/docs/html/registers-5.0.html
@@ -2697,6 +2697,15 @@ th {
<td class="type">W</td>
<td class="desc">Number of BC clocks between CAL and TRIGGER command if USE_CAL is set to 1</td>
</tr>
+ <tr>
+ <td rowspan="1">0x3AD0</td>
+ <td rowspan="1">0,1</td>
+ <td rowspan="1">ITKSTRIP_LCB_R3L1_ELINK_SWAP</td>
+ <td class="name"></td>
+ <td class="range">47..0</td>
+ <td class="type">W</td>
+ <td class="desc">Setting a bit, moves the LCB E-Link to the odd E-Link position and R3L1 to the even one on the lpGBT downlink. 4 bits per lpGBT link</td>
+ </tr>
<tr>
<td colspan="7" class="group">Frontend Emulator Controls And Monitors</td>
</tr>
diff --git a/sources/templates/generated/dma_control.vhd b/sources/templates/generated/dma_control.vhd
index c906c1bbe48ed208403c9600c0d8eca91f26051b..a83c90e062e4e3c4626c87e6f684ba28ff04c2a0 100644
--- a/sources/templates/generated/dma_control.vhd
+++ b/sources/templates/generated/dma_control.vhd
@@ -8511,6 +8511,7 @@ end process;
register_map_control_s.HGTD_ALTIROC_FASTCMD.SYNCLUMI <= REG_HGTD_ALTIROC_FASTCMD_SYNCLUMI_C; -- Set to 1 to trigger a SYNCLUMI command, rising edge of this bit. Clear in software
register_map_control_s.HGTD_ALTIROC_FASTCMD.GBRST <= REG_HGTD_ALTIROC_FASTCMD_GBRST_C; -- Set to 1 to trigger a GBRST command, rising edge of this bit. Clear in software
register_map_control_s.HGTD_ALTIROC_FASTCMD.TRIG_DELAY <= REG_HGTD_ALTIROC_FASTCMD_TRIG_DELAY_C; -- Number of BC clocks between CAL and TRIGGER command if USE_CAL is set to 1
+ register_map_control_s.ITKSTRIP_LCB_R3L1_ELINK_SWAP <= REG_ITKSTRIP_LCB_R3L1_ELINK_SWAP_C; -- Setting a bit, moves the LCB E-Link to the odd E-Link position and R3L1 to the even one on the lpGBT downlink. 4 bits per lpGBT link
register_map_control_s.FE_EMU_ENA.EMU_TOFRONTEND <= REG_FE_EMU_ENA_EMU_TOFRONTEND_C; -- Enable GBT dummy emulator ToFrontEnd
register_map_control_s.FE_EMU_ENA.EMU_TOHOST <= REG_FE_EMU_ENA_EMU_TOHOST_C; -- Enable GBT dummy emulator ToHost
register_map_control_s.FE_EMU_CONFIG.WE <= REG_FE_EMU_CONFIG_WE_C; -- write enable array, every bit is one emulator RAM block
@@ -15368,6 +15369,7 @@ end process;
register_read_data_25_s(12 downto 12) <= register_map_control_s.HGTD_ALTIROC_FASTCMD.SYNCLUMI; -- Set to 1 to trigger a SYNCLUMI command, rising edge of this bit. Clear in software
register_read_data_25_s(11 downto 11) <= register_map_control_s.HGTD_ALTIROC_FASTCMD.GBRST; -- Set to 1 to trigger a GBRST command, rising edge of this bit. Clear in software
register_read_data_25_s(10 downto 0) <= register_map_control_s.HGTD_ALTIROC_FASTCMD.TRIG_DELAY; -- Number of BC clocks between CAL and TRIGGER command if USE_CAL is set to 1
+ when REG_ITKSTRIP_LCB_R3L1_ELINK_SWAP => register_read_data_25_s(47 downto 0) <= register_map_control_s.ITKSTRIP_LCB_R3L1_ELINK_SWAP; -- Setting a bit, moves the LCB E-Link to the odd E-Link position and R3L1 to the even one on the lpGBT downlink. 4 bits per lpGBT link
when REG_FE_EMU_ENA => register_read_data_25_s(1 downto 1) <= register_map_control_s.FE_EMU_ENA.EMU_TOFRONTEND; -- Enable GBT dummy emulator ToFrontEnd
register_read_data_25_s(0 downto 0) <= register_map_control_s.FE_EMU_ENA.EMU_TOHOST; -- Enable GBT dummy emulator ToHost
when REG_FE_EMU_CONFIG => register_read_data_25_s(54 downto 47) <= register_map_control_s.FE_EMU_CONFIG.WE; -- write enable array, every bit is one emulator RAM block
@@ -23074,6 +23076,7 @@ end process;
register_map_control_s.HGTD_ALTIROC_FASTCMD.SYNCLUMI <= register_write_data_25_v(12 downto 12); -- Set to 1 to trigger a SYNCLUMI command, rising edge of this bit. Clear in software
register_map_control_s.HGTD_ALTIROC_FASTCMD.GBRST <= register_write_data_25_v(11 downto 11); -- Set to 1 to trigger a GBRST command, rising edge of this bit. Clear in software
register_map_control_s.HGTD_ALTIROC_FASTCMD.TRIG_DELAY <= register_write_data_25_v(10 downto 0); -- Number of BC clocks between CAL and TRIGGER command if USE_CAL is set to 1
+ when REG_ITKSTRIP_LCB_R3L1_ELINK_SWAP => register_map_control_s.ITKSTRIP_LCB_R3L1_ELINK_SWAP <= register_write_data_25_v(47 downto 0); -- Setting a bit, moves the LCB E-Link to the odd E-Link position and R3L1 to the even one on the lpGBT downlink. 4 bits per lpGBT link
when REG_FE_EMU_ENA => register_map_control_s.FE_EMU_ENA.EMU_TOFRONTEND <= register_write_data_25_v(1 downto 1); -- Enable GBT dummy emulator ToFrontEnd
register_map_control_s.FE_EMU_ENA.EMU_TOHOST <= register_write_data_25_v(0 downto 0); -- Enable GBT dummy emulator ToHost
when REG_FE_EMU_CONFIG => register_map_control_s.FE_EMU_CONFIG.WE <= register_write_data_25_v(54 downto 47); -- write enable array, every bit is one emulator RAM block
diff --git a/sources/templates/generated/dma_control_5.vhd b/sources/templates/generated/dma_control_5.vhd
index 713932c4e20f40b6720932e12c134fd08db6b9dd..a3c1174a5325e2e3291f495c709010ea9f97f119 100644
--- a/sources/templates/generated/dma_control_5.vhd
+++ b/sources/templates/generated/dma_control_5.vhd
@@ -6992,6 +6992,7 @@ end process;
register_map_control_s.YARR_FROMHOST_CALTRIGSEQ_WE <= REG_YARR_FROMHOST_CALTRIGSEQ_WE_C; -- enable to store CalPulse+Trigger Sequence into memory
register_map_control_s.YARR_FROMHOST_CALTRIGSEQ_WRDATA <= REG_YARR_FROMHOST_CALTRIGSEQ_WRDATA_C; -- CalPulse+Trigger Sequence to be stored in memory
register_map_control_s.YARR_FROMHOST_CALTRIGSEQ_WRADDR <= REG_YARR_FROMHOST_CALTRIGSEQ_WRADDR_C; -- memory address to store CalPulse+Trigger Sequence
+ register_map_control_s.ITKSTRIP_LCB_R3L1_ELINK_SWAP <= REG_ITKSTRIP_LCB_R3L1_ELINK_SWAP_C; -- Setting a bit, moves the LCB E-Link to the odd E-Link position and R3L1 to the even one on the lpGBT downlink. 4 bits per lpGBT link
register_map_control_s.FE_EMU_ENA.EMU_TOFRONTEND <= REG_FE_EMU_ENA_EMU_TOFRONTEND_C; -- Enable GBT dummy emulator ToFrontEnd
register_map_control_s.FE_EMU_ENA.EMU_TOHOST <= REG_FE_EMU_ENA_EMU_TOHOST_C; -- Enable GBT dummy emulator ToHost
register_map_control_s.FE_EMU_CONFIG.WE <= REG_FE_EMU_CONFIG_WE_C; -- write enable array, every bit is one emulator RAM block
@@ -12079,6 +12080,7 @@ end process;
when REG_YARR_FROMHOST_CALTRIGSEQ_WE => register_read_data_25_s(0 downto 0) <= register_map_control_s.YARR_FROMHOST_CALTRIGSEQ_WE; -- enable to store CalPulse+Trigger Sequence into memory
when REG_YARR_FROMHOST_CALTRIGSEQ_WRDATA => register_read_data_25_s(15 downto 0) <= register_map_control_s.YARR_FROMHOST_CALTRIGSEQ_WRDATA; -- CalPulse+Trigger Sequence to be stored in memory
when REG_YARR_FROMHOST_CALTRIGSEQ_WRADDR => register_read_data_25_s(4 downto 0) <= register_map_control_s.YARR_FROMHOST_CALTRIGSEQ_WRADDR; -- memory address to store CalPulse+Trigger Sequence
+ when REG_ITKSTRIP_LCB_R3L1_ELINK_SWAP => register_read_data_25_s(47 downto 0) <= register_map_control_s.ITKSTRIP_LCB_R3L1_ELINK_SWAP; -- Setting a bit, moves the LCB E-Link to the odd E-Link position and R3L1 to the even one on the lpGBT downlink. 4 bits per lpGBT link
when REG_FE_EMU_ENA => register_read_data_25_s(1 downto 1) <= register_map_control_s.FE_EMU_ENA.EMU_TOFRONTEND; -- Enable GBT dummy emulator ToFrontEnd
register_read_data_25_s(0 downto 0) <= register_map_control_s.FE_EMU_ENA.EMU_TOHOST; -- Enable GBT dummy emulator ToHost
when REG_FE_EMU_CONFIG => register_read_data_25_s(54 downto 47) <= register_map_control_s.FE_EMU_CONFIG.WE; -- write enable array, every bit is one emulator RAM block
@@ -17559,6 +17561,7 @@ end process;
when REG_YARR_FROMHOST_CALTRIGSEQ_WE => register_map_control_s.YARR_FROMHOST_CALTRIGSEQ_WE <= register_write_data_25_v(0 downto 0); -- enable to store CalPulse+Trigger Sequence into memory
when REG_YARR_FROMHOST_CALTRIGSEQ_WRDATA => register_map_control_s.YARR_FROMHOST_CALTRIGSEQ_WRDATA <= register_write_data_25_v(15 downto 0); -- CalPulse+Trigger Sequence to be stored in memory
when REG_YARR_FROMHOST_CALTRIGSEQ_WRADDR => register_map_control_s.YARR_FROMHOST_CALTRIGSEQ_WRADDR <= register_write_data_25_v(4 downto 0); -- memory address to store CalPulse+Trigger Sequence
+ when REG_ITKSTRIP_LCB_R3L1_ELINK_SWAP => register_map_control_s.ITKSTRIP_LCB_R3L1_ELINK_SWAP <= register_write_data_25_v(47 downto 0); -- Setting a bit, moves the LCB E-Link to the odd E-Link position and R3L1 to the even one on the lpGBT downlink. 4 bits per lpGBT link
when REG_FE_EMU_ENA => register_map_control_s.FE_EMU_ENA.EMU_TOFRONTEND <= register_write_data_25_v(1 downto 1); -- Enable GBT dummy emulator ToFrontEnd
register_map_control_s.FE_EMU_ENA.EMU_TOHOST <= register_write_data_25_v(0 downto 0); -- Enable GBT dummy emulator ToHost
when REG_FE_EMU_CONFIG => register_map_control_s.FE_EMU_CONFIG.WE <= register_write_data_25_v(54 downto 47); -- write enable array, every bit is one emulator RAM block
diff --git a/sources/templates/generated/pcie_package.vhd b/sources/templates/generated/pcie_package.vhd
index b7224f9439d90987ba013f9f6e47e71067625d2d..2e6dbc43c8fda03cdb4a278609b88ecf7e791867 100644
--- a/sources/templates/generated/pcie_package.vhd
+++ b/sources/templates/generated/pcie_package.vhd
@@ -928,6 +928,7 @@ package pcie_package is
constant REG_YARR_FROMHOST_CALTRIGSEQ_WRDATA : std_logic_vector(19 downto 0) := x"03aa0";
constant REG_YARR_FROMHOST_CALTRIGSEQ_WRADDR : std_logic_vector(19 downto 0) := x"03ab0";
constant REG_HGTD_ALTIROC_FASTCMD : std_logic_vector(19 downto 0) := x"03ac0";
+ constant REG_ITKSTRIP_LCB_R3L1_ELINK_SWAP : std_logic_vector(19 downto 0) := x"03ad0";
--** FrontendEmulatorControlsAndMonitors
constant REG_FE_EMU_ENA : std_logic_vector(19 downto 0) := x"04000";
@@ -2509,6 +2510,7 @@ package pcie_package is
YARR_FROMHOST_CALTRIGSEQ_WRDATA : std_logic_vector(15 downto 0); -- CalPulse+Trigger Sequence to be stored in memory
YARR_FROMHOST_CALTRIGSEQ_WRADDR : std_logic_vector(4 downto 0); -- memory address to store CalPulse+Trigger Sequence
HGTD_ALTIROC_FASTCMD : bitfield_hgtd_altiroc_fastcmd_w_type; -- Controls the HGTD Altiroc FASTCMD TTC encoder functionality (TTC option 8).
+ ITKSTRIP_LCB_R3L1_ELINK_SWAP : std_logic_vector(47 downto 0); -- Setting a bit, moves the LCB E-Link to the odd E-Link position and R3L1 to the even one on the lpGBT downlink. 4 bits per lpGBT link
FE_EMU_ENA : bitfield_fe_emu_ena_w_type; -- Frontend Emulator Controls and Monitors
FE_EMU_CONFIG : bitfield_fe_emu_config_w_type; -- Frontend Emulator Controls and Monitors
FE_EMU_READ : bitfield_fe_emu_read_w_type; -- Frontend Emulator Controls and Monitors
@@ -6386,6 +6388,7 @@ package pcie_package is
constant REG_HGTD_ALTIROC_FASTCMD_SYNCLUMI_C : std_logic_vector(12 downto 12) := "0"; -- Set to 1 to trigger a SYNCLUMI command, rising edge of this bit. Clear in software
constant REG_HGTD_ALTIROC_FASTCMD_GBRST_C : std_logic_vector(11 downto 11) := "0"; -- Set to 1 to trigger a GBRST command, rising edge of this bit. Clear in software
constant REG_HGTD_ALTIROC_FASTCMD_TRIG_DELAY_C : std_logic_vector(10 downto 0) := "00000000101"; -- Number of BC clocks between CAL and TRIGGER command if USE_CAL is set to 1
+ constant REG_ITKSTRIP_LCB_R3L1_ELINK_SWAP_C : std_logic_vector(47 downto 0) := x"000000000000"; -- Setting a bit, moves the LCB E-Link to the odd E-Link position and R3L1 to the even one on the lpGBT downlink. 4 bits per lpGBT link
constant REG_FE_EMU_ENA_EMU_TOFRONTEND_C : std_logic_vector(1 downto 1) := "0"; -- Enable GBT dummy emulator ToFrontEnd
constant REG_FE_EMU_ENA_EMU_TOHOST_C : std_logic_vector(0 downto 0) := "0"; -- Enable GBT dummy emulator ToHost
constant REG_FE_EMU_CONFIG_WE_C : std_logic_vector(54 downto 47) := x"00"; -- write enable array, every bit is one emulator RAM block
diff --git a/sources/templates/yaml/registers-5.0.yaml b/sources/templates/yaml/registers-5.0.yaml
index ebc6b8456c1c8df42dfc3f54b27ab23f436db948..80a0e501f8ce5d3298eac51ecc9f6fda76b5008e 100644
--- a/sources/templates/yaml/registers-5.0.yaml
+++ b/sources/templates/yaml/registers-5.0.yaml
@@ -1321,6 +1321,12 @@ EncodingControlsAndMonitors:
name: TRIG_DELAY
desc: Number of BC clocks between CAL and TRIGGER command if USE_CAL is set to 1
default: 5
+ - name: ITKSTRIP_LCB_R3L1_ELINK_SWAP
+ fw_modes: 5
+ desc: Setting a bit, moves the LCB E-Link to the odd E-Link position and R3L1 to the even one on the lpGBT downlink. 4 bits per lpGBT link
+ type: W
+ bitfield:
+ - range: 47..0