diff --git a/sources/templates/build-doc.sh b/sources/templates/build-doc.sh
index d4936aa65e8c229eefc5d728edc6e44ecda2e29f..22339b554213b20afa88ac4819db57790f294283 100755
--- a/sources/templates/build-doc.sh
+++ b/sources/templates/build-doc.sh
@@ -2,6 +2,7 @@
# build the documentation from the registermap.tex file
firmware_dir=../..
wuppercodegen_dir=$firmware_dir/WupperCodeGen
+wuppercodegen=$wuppercodegen_dir/wuppercodegen/cli.py
registers=registers-5.0.yaml
$wuppercodegen --version
$wuppercodegen $registers registermap.tex.template registermap-5.0.tex
diff --git a/sources/templates/registermap-5.0.tex b/sources/templates/registermap-5.0.tex
index 377e945e3dcba3de8a12e86769ae01d85d6f52d3..a02d9261c7193b016fe724d4f71c623aeaa990ab 100644
--- a/sources/templates/registermap-5.0.tex
+++ b/sources/templates/registermap-5.0.tex
@@ -10,7 +10,7 @@
% by the script 'wuppercodegen', version: 0.8.4,
% using the following commandline:
%
-% ../../../software/wuppercodegen/wuppercodegen/cli.py registers-5.0.yaml registermap.tex.template registermap-5.0.tex
+% ../../WupperCodeGen/wuppercodegen/cli.py registers-5.0.yaml registermap.tex.template registermap-5.0.tex
%
% Please do NOT edit this file, but edit the source file at 'registermap.tex.template'
%
@@ -229,28 +229,30 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
\hline
0x0100 & 0,1 & \multicolumn{4}{c|}{\small INCLUDE\_EGROUP\_0} \\
\cline{3-6}
- & & FROMHOST\_02 & 8 & R & FromHost EPROC02 is included in this EGROUP \\
- & & FROMHOST\_04 & 7 & R & FromHost EPROC04 is included in this EGROUP \\
- & & FROMHOST\_08 & 6 & R & FromHost EPROC8 is included in this EGROUP \\
+ & & TOHOST\_32 & 9 & R & ToHost EPATH32 is included in this EGROUP \\
+ & & FROMHOST\_02 & 8 & R & FromHost EPATH02 is included in this EGROUP \\
+ & & FROMHOST\_04 & 7 & R & FromHost EPATH04 is included in this EGROUP \\
+ & & FROMHOST\_08 & 6 & R & FromHost EPATH8 is included in this EGROUP \\
& & FROMHOST\_HDLC & 5 & R & FromHost HDLC is included in this EGROUP \\
- & & TOHOST\_02 & 4 & R & ToHost EPROC02 is included in this EGROUP \\
- & & TOHOST\_04 & 3 & R & ToHost EPROC04 is included in this EGROUP \\
- & & TOHOST\_08 & 2 & R & ToHost EPROC08 is included in this EGROUP \\
- & & TOHOST\_16 & 1 & R & ToHost EPROC16 is included in this EGROUP \\
+ & & TOHOST\_02 & 4 & R & ToHost EPATH02 is included in this EGROUP \\
+ & & TOHOST\_04 & 3 & R & ToHost EPATH04 is included in this EGROUP \\
+ & & TOHOST\_08 & 2 & R & ToHost EPATH08 is included in this EGROUP \\
+ & & TOHOST\_16 & 1 & R & ToHost EPATH16 is included in this EGROUP \\
& & TOHOST\_HDLC & 0 & R & ToHost HDLC is included in this EGROUP \\
\hline
\multicolumn{6}{|c|}{\ldots} \\
\hline
0x0160 & 0,1 & \multicolumn{4}{c|}{\small INCLUDE\_EGROUP\_6} \\
\cline{3-6}
- & & FROMHOST\_02 & 8 & R & FromHost EPROC02 is included in this EGROUP \\
- & & FROMHOST\_04 & 7 & R & FromHost EPROC04 is included in this EGROUP \\
- & & FROMHOST\_08 & 6 & R & FromHost EPROC8 is included in this EGROUP \\
+ & & TOHOST\_32 & 9 & R & ToHost EPATH32 is included in this EGROUP \\
+ & & FROMHOST\_02 & 8 & R & FromHost EPATH02 is included in this EGROUP \\
+ & & FROMHOST\_04 & 7 & R & FromHost EPATH04 is included in this EGROUP \\
+ & & FROMHOST\_08 & 6 & R & FromHost EPATH8 is included in this EGROUP \\
& & FROMHOST\_HDLC & 5 & R & FromHost HDLC is included in this EGROUP \\
- & & TOHOST\_02 & 4 & R & ToHost EPROC02 is included in this EGROUP \\
- & & TOHOST\_04 & 3 & R & ToHost EPROC04 is included in this EGROUP \\
- & & TOHOST\_08 & 2 & R & ToHost EPROC08 is included in this EGROUP \\
- & & TOHOST\_16 & 1 & R & ToHost EPROC16 is included in this EGROUP \\
+ & & TOHOST\_02 & 4 & R & ToHost EPATH02 is included in this EGROUP \\
+ & & TOHOST\_04 & 3 & R & ToHost EPATH04 is included in this EGROUP \\
+ & & TOHOST\_08 & 2 & R & ToHost EPATH08 is included in this EGROUP \\
+ & & TOHOST\_16 & 1 & R & ToHost EPATH16 is included in this EGROUP \\
& & TOHOST\_HDLC & 0 & R & ToHost HDLC is included in this EGROUP \\
\hline
0x0170 & 0,1 & WIDE\_MODE &
@@ -377,21 +379,23 @@ any & T & Central Router FromHost Controls and Monitors \\
\hline
0x2300 & 0,1 & \multicolumn{4}{c|}{\small DECODING\_LINK00\_EGROUP0\_CTRL} \\
\cline{3-6}
+ & & ENABLE\_TRUNCATION & 59 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
& & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
& & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
& & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
& & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
- & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\
+ & & EPATH\_ENA & 7:0 & W & Enable bits per EPATH \\
\hline
\multicolumn{6}{|c|}{\ldots} \\
\hline
0x2360 & 0,1 & \multicolumn{4}{c|}{\small DECODING\_LINK00\_EGROUP6\_CTRL} \\
\cline{3-6}
+ & & ENABLE\_TRUNCATION & 59 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
& & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
& & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
& & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
& & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
- & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\
+ & & EPATH\_ENA & 7:0 & W & Enable bits per EPATH \\
\hline
\multicolumn{6}{|c|}{\ldots} \\
\hline
@@ -399,26 +403,31 @@ any & T & Central Router FromHost Controls and Monitors \\
\hline
0x27D0 & 0,1 & \multicolumn{4}{c|}{\small DECODING\_LINK11\_EGROUP0\_CTRL} \\
\cline{3-6}
+ & & ENABLE\_TRUNCATION & 59 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
& & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
& & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
& & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
& & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
- & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\
+ & & EPATH\_ENA & 7:0 & W & Enable bits per EPATH \\
\hline
\multicolumn{6}{|c|}{\ldots} \\
\hline
0x2830 & 0,1 & \multicolumn{4}{c|}{\small DECODING\_LINK11\_EGROUP6\_CTRL} \\
\cline{3-6}
+ & & ENABLE\_TRUNCATION & 59 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
& & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
& & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
& & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
& & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
- & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\
+ & & EPATH\_ENA & 7:0 & W & Enable bits per EPATH \\
\hline
\multicolumn{6}{|c|}{MINI\_EGROUP\_TOHOST\_GEN} \\
\hline
0x2840 & 0,1 & \multicolumn{4}{c|}{\small MINI\_EGROUP\_TOHOST\_00} \\
\cline{3-6}
+ & & ENABLE\_AUX\_TRUNCATION & 15 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
+ & & ENABLE\_IC\_TRUNCATION & 14 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
+ & & ENABLE\_EC\_TRUNCATION & 13 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
& & AUX\_ALMOST\_FULL & 12 & R & Indicator that the AUX path FIFO is almost full \\
& & AUX\_BIT\_SWAPPING & 11 & W & 0: two input bits of IC e-link are as documented, 1: two input bits are swapped \\
& & AUX\_ENABLE & 10 & W & Enables the AUX channel \\
@@ -434,6 +443,9 @@ any & T & Central Router FromHost Controls and Monitors \\
\hline
0x29B0 & 0,1 & \multicolumn{4}{c|}{\small MINI\_EGROUP\_TOHOST\_23} \\
\cline{3-6}
+ & & ENABLE\_AUX\_TRUNCATION & 15 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
+ & & ENABLE\_IC\_TRUNCATION & 14 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
+ & & ENABLE\_EC\_TRUNCATION & 13 & W & Enable truncation mechanism in HDLC decoder for chunks > 12 bytes \\
& & AUX\_ALMOST\_FULL & 12 & R & Indicator that the AUX path FIFO is almost full \\
& & AUX\_BIT\_SWAPPING & 11 & W & 0: two input bits of IC e-link are as documented, 1: two input bits are swapped \\
& & AUX\_ENABLE & 10 & W & Enables the AUX channel \\
@@ -451,31 +463,19 @@ any & T & Central Router FromHost Controls and Monitors \\
0x29D0 & 0,1 & DECODING\_REVERSE\_10B &
0 & W & Reverse 10-bit word of elink data for 8b10b E-links\newline 1: Receive 10-bit word in ToHost E-Paths, MSB first\newline 0: Receive 10-bit word in ToHost E-Paths, LSB first\newline \\
\hline
-\multicolumn{6}{|c|}{YARR\_DEBUG} \\
+\multicolumn{6}{|c|}{YARR\_DEBUG\_ALLEGROUP\_TOHOST\_GEN} \\
\hline
-0x29E0 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_FROMHOST\_00} \\
+0x29E0 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_ALLEGROUP\_TOHOST\_00} \\
\cline{3-6}
- & & RD53A\_AZ\_EN & 56 & W & Auto zeroing module enable \\
- & & CNT\_TRIG\_CMD & 55:24 & R & Number of issued triggers via cmd \\
- & & CNT\_GENCALTRIG\_DLY & 23:16 & R & Measured distance between GenCal and first issued trigger via cmd \\
- & & ERR\_GENCALTRIG\_DLY & 15:8 & R & Number of mismatches between CNT\_GENCALTRIG\_DLY and REF\_DLY\_GENCALTRIG \\
- & & REF\_DLY\_GENCALTRIG & 7:0 & W & Reference distance between GenCal and First Trigger \\
-\hline
-0x29F0 & 0,1 & CNT\_RX\_64B66BHDR\_LANE0\_00 &
-31:0 & R & RD53A HDR from 64b66b module. LANE0 only \\
+ & & REF\_PACKET & 63:32 & W & Reference packet to be matched \\
+ & & CNT\_RX\_PACKET & 31:0 & R & Count packets of a given value \\
\hline
\multicolumn{6}{|c|}{\ldots} \\
\hline
-0x2B40 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_FROMHOST\_11} \\
+0x2A90 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_ALLEGROUP\_TOHOST\_11} \\
\cline{3-6}
- & & RD53A\_AZ\_EN & 56 & W & Auto zeroing module enable \\
- & & CNT\_TRIG\_CMD & 55:24 & R & Number of issued triggers via cmd \\
- & & CNT\_GENCALTRIG\_DLY & 23:16 & R & Measured distance between GenCal and first issued trigger via cmd \\
- & & ERR\_GENCALTRIG\_DLY & 15:8 & R & Number of mismatches between CNT\_GENCALTRIG\_DLY and REF\_DLY\_GENCALTRIG \\
- & & REF\_DLY\_GENCALTRIG & 7:0 & W & Reference distance between GenCal and First Trigger \\
-\hline
-0x2B50 & 0,1 & CNT\_RX\_64B66BHDR\_LANE0\_11 &
-31:0 & R & RD53A HDR from 64b66b module. LANE0 only \\
+ & & REF\_PACKET & 63:32 & W & Reference packet to be matched \\
+ & & CNT\_RX\_PACKET & 31:0 & R & Count packets of a given value \\
\hline
\multicolumn{6}{|c|}{SUPER\_CHUNK\_FACTOR\_GEN} \\
\hline
@@ -646,6 +646,43 @@ any & T & Central Router FromHost Controls and Monitors \\
& & AUTOMATIC\_MERGE\_DISABLE0 & 1 & W & Disable automatic merging \\
& & TTC\_SELECT0 & 0 & W & TTC/FromHost select (if automatic merging is disabled) \\
\hline
+\multicolumn{6}{|c|}{YARR\_DEBUG\_ALLEGROUP\_FROMHOST\_GEN} \\
+\hline
+0x3910 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_ALLEGROUP\_FROMHOST1\_00} \\
+\cline{3-6}
+ & & RD53A\_AZ\_EN & 48 & W & Auto zeroing module enable \\
+ & & CNT\_TRIG\_CMD & 47:16 & R & Number of issued triggers via cmd \\
+ & & ERR\_GENCALTRIG\_DLY & 15:8 & R & Number of mismatches between CNT\_GENCALTRIG\_DLY and REF\_DLY\_GENCALTRIG \\
+ & & REF\_DLY\_GENCALTRIG & 7:0 & W & Reference distance between GenCal and First Trigger \\
+\hline
+0x3920 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_ALLEGROUP\_FROMHOST2\_00} \\
+\cline{3-6}
+ & & CNT\_CMD & 47:16 & R & Number of issued commands \\
+ & & REF\_CMD & 15:0 & W & Cmd type to be counted. See RD53 Manual for list of allowed commands \\
+\hline
+\multicolumn{6}{|c|}{\ldots} \\
+\hline
+0x3A70 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_ALLEGROUP\_FROMHOST1\_11} \\
+\cline{3-6}
+ & & RD53A\_AZ\_EN & 48 & W & Auto zeroing module enable \\
+ & & CNT\_TRIG\_CMD & 47:16 & R & Number of issued triggers via cmd \\
+ & & ERR\_GENCALTRIG\_DLY & 15:8 & R & Number of mismatches between CNT\_GENCALTRIG\_DLY and REF\_DLY\_GENCALTRIG \\
+ & & REF\_DLY\_GENCALTRIG & 7:0 & W & Reference distance between GenCal and First Trigger \\
+\hline
+0x3A80 & 0,1 & \multicolumn{4}{c|}{\small YARR\_DEBUG\_ALLEGROUP\_FROMHOST2\_11} \\
+\cline{3-6}
+ & & CNT\_CMD & 47:16 & R & Number of issued commands \\
+ & & REF\_CMD & 15:0 & W & Cmd type to be counted. See RD53 Manual for list of allowed commands \\
+\hline
+0x3A90 & 0,1 & YARR\_FROMHOST\_CALTRIGSEQ\_WE &
+0 & W & enable to store CalPulse+Trigger Sequence into memory \\
+\hline
+0x3AA0 & 0,1 & YARR\_FROMHOST\_CALTRIGSEQ\_WRDATA &
+15:0 & W & CalPulse+Trigger Sequence to be stored in memory \\
+\hline
+0x3AB0 & 0,1 & YARR\_FROMHOST\_CALTRIGSEQ\_WRADDR &
+4:0 & W & memory address to store CalPulse+Trigger Sequence \\
+\hline
\multicolumn{6}{|c|}{Frontend Emulator Controls And Monitors} \\
\hline
0x4000 & 0, 1 & \multicolumn{4}{c|}{\small FE\_EMU\_ENA} \\
@@ -778,6 +815,11 @@ any & T & Central Router FromHost Controls and Monitors \\
& & LOCK & 48 & W & Locks this particular register. If set prevents software from touching it. \\
& & SEL & 47:0 & W & ToFrontEnd FanOut/Selector. Every bitfield is a channel:\newline 1 : GBT\_EMU, select GBT Emulator for a specific GBT link\newline 0 : TTC\_DEC, select CentralRouter data (including TTC) for a specific GBT link\newline \newline \\
\hline
+0x5720 & 0 & \multicolumn{4}{c|}{\small FULLMODE\_AUTO\_RX\_RESET} \\
+\cline{3-6}
+ & & ENABLE & 32 & W & Enable the Automatic RX Reset mechanism \\
+ & & TIMEOUT & 31:0 & W & Number of 40 MHz clock cycles until an unaligned link results in a reset pulse \\
+\hline
\multicolumn{6}{|c|}{Link Wrapper Monitors} \\
\hline
0x6600 & 0 & \multicolumn{4}{c|}{\small GBT\_VERSION} \\
@@ -948,7 +990,7 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
3:0 & W & Controls the low threshold of the channel fifo in FULL mode on which\newline an Xon will be asserted, bitfields control 4 MSB\newline \\
\hline
0x8010 & 0, 1 & XOFF\_FM\_CH\_FIFO\_THRESH\_HIGH &
-3:0 & W & Controls the high threshold of the channel fifo in FULL mode on which\newline an Xoff will be asserted, bitfields control 4 MSB - name: XOFF\_FM\_LOW\_THRESH\_CROSSED\newline \\
+3:0 & W & Controls the high threshold of the channel fifo in FULL mode on which\newline an Xoff will be asserted, bitfields control 4 MSB\newline \\
\hline
0x8020 & 0, 1 & XOFF\_FM\_LOW\_THRESH\_CROSSED &
23:0 & R & FIFO filled beyond the low threshold, 1 bit per channel \\
@@ -1360,8 +1402,8 @@ any & T & Any write to this register clears the FELIG L1ID \\
\hline
0xB800 & 0 & \multicolumn{4}{c|}{\small FMEMU\_EVENT\_INFO} \\
\cline{3-6}
- & & L1ID & 63:32 & W & 32b field to show L1ID \\
- & & BCID & 31:0 & W & 32b field to show BCID \\
+ & & L1ID & 63:32 & R & 32b field to show L1ID \\
+ & & BCID & 31:0 & R & 32b field to show BCID \\
\hline
0xB810 & 0 & \multicolumn{4}{c|}{\small FMEMU\_COUNTERS} \\
\cline{3-6}
@@ -1377,14 +1419,14 @@ any & T & Any write to this register clears the FELIG L1ID \\
& & XONXOFF\_BITNR & 55:48 & W & Bitfield for Xon/Xoff in TTC frame \\
& & EMU\_START & 47:47 & W & Start emulator functionality \\
& & TTC\_MODE & 46:46 & W & Control the emulator by TTC input or by RegMap (1/0) \\
- & & XONXOFF & 45:45 & W & Debug Xon/Xoff functionality (1/0) \\
+ & & XONXOFF & 45:45 & W & Enable Xon/Xoff functionality (1/0) \\
& & INLC\_CRC32 & 44:44 & W & 0: No checksum\newline 1: Append the data with a CRC32\newline \\
& & BCR & 43:43 & W & Reset BCID to 0 \\
& & ECR & 42:42 & W & Reset L1ID to 0 \\
- & & DATA\_SRC\_SEL & 41:41 & W & Data source select\newline 0: Data input comes from EMURAM\newline 1: Data input comes from PCIe\newline \\
+ & & CONSTANT\_CHUNK\_LENGTH & 41:41 & W & Data source select\newline 0: Random chunk length\newline 1: Constant chunk length\newline \\
& & INT\_STATUS\_EMU & 40:32 & R & Read internal status emulator \\
- & & FFU\_FM\_EMU\_T & 31:16 & W & For Future Use (trigger registers) \\
- & & FFU\_FM\_EMU\_W & 15:0 & W & For Future Use (write registers) \\
+ & & FFU\_FM\_EMU\_T & 16 & W & For Future Use (trigger registers) \\
+ & & FE\_BUSY\_ENABLE & 0 & W & Enable the BUSY mechanism if L1A counter passes threshold \\
\hline
0xB830 & 0 & FMEMU\_RANDOM\_RAM\_ADDR &
9:0 & W & Controls the address of the ramblock for the random number generator \\
@@ -1553,7 +1595,7 @@ any & T & (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 s
0xF130 & 0 & MROD\_EP1\_TXRESET &
23:0 & W & EP1 Transmitter Reset channel 23-0 \\
\hline
-\multicolumn{6}{|c|}{MROD Monitors} \\
+\multicolumn{6}{|c|}{MRO Dmonitors} \\
\hline
0xF800 & 0 & MROD\_EP0\_CSMH\_EMPTY &
23:0 & R & EP0 CSM Handler FIFO Empty 23-0 \\
diff --git a/sources/templates/registermap.tex b/sources/templates/registermap.tex
index 88e8c3c65ea4ba598b0a83ab4f3c68a8fe33d85c..a1ce159190e27b8e621dc5a24bd4fed9820ea928 100644
--- a/sources/templates/registermap.tex
+++ b/sources/templates/registermap.tex
@@ -6,16 +6,11 @@
% DO NOT EDIT THIS FILE
%
% This file was generated from template 'registermap.tex.template'
-<<<<<<< HEAD
-% and register map registers-5.0.yaml, version 5.0
-% by the script 'wuppercodegen', version: 0.8.0,
-=======
% and register map registers-4.10.yaml, version 4.10
% by the script 'wuppercodegen', version: 0.8.4,
->>>>>>> master
% using the following commandline:
%
-% ../../../software/wuppercodegen/wuppercodegen/cli.py registers-5.0.yaml registermap.tex.template registermap.tex
+% ../../../software/wuppercodegen/wuppercodegen/cli.py registers-4.10.yaml registermap.tex.template registermap.tex
%
% Please do NOT edit this file, but edit the source file at 'registermap.tex.template'
%
@@ -25,7 +20,7 @@
% ***************************************************************************
% ***************************************************************************
-\section{FELIX register map, version 5.0}
+\section{FELIX register map, version 4.10}
Starting from the offset address of BAR0, BAR1 and BAR2. BAR0 only contains registers associated with DMA.
\keepXColumns
@@ -189,13 +184,8 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
\hline
\multicolumn{6}{|c|}{Generic Board Information} \\
\hline
-<<<<<<< HEAD
-0x0000 & 0,1 & \multicolumn{2}{l|}{REG\_MAP\_VERSION} &
-15:0 & R & Register Map Version, 5.0 formatted as 0x0500 \\
-=======
0x0000 & 0,1 & REG\_MAP\_VERSION &
15:0 & R & Register Map Version, 4.10 formatted as 0x040A \\
->>>>>>> master
\hline
0x0010 & 0,1 & BOARD\_ID\_TIMESTAMP &
39:0 & R & Board ID Date / Time in BCD format YYMMDDhhmm \\
@@ -232,11 +222,7 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
0x00D0 & 0,1 & OPTO\_TRX\_NUM &
7:0 & R & Number of optical transceivers in the design \\
\hline
-<<<<<<< HEAD
-0x00E0 & 0,1 & \multicolumn{2}{l|}{GENERATE\_TTC\_EMU} &
-=======
0x00E0 & 0,1 & TTC\_EMU\_CONST\_GENERATE\_TTC\_EMU &
->>>>>>> master
1 & R & 1 when TTC emulator is generated \\
\hline
\multicolumn{6}{|c|}{INCLUDE\_EGROUPS} \\
@@ -270,13 +256,8 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
0x0170 & 0,1 & WIDE\_MODE &
0 & R & GBT is configured in Wide mode \\
\hline
-<<<<<<< HEAD
-0x0190 & 0,1 & \multicolumn{2}{l|}{FIRMWARE\_MODE} &
-3:0 & R & 0: GBT mode\newline 1: FULL mode\newline 2: LTDB mode (GBT mode with only IC and TTC links)\newline 3: FEI4 mode\newline 4: ITK Pixel\newline 5: ITK Strip\newline 6: FELIG\newline 7: FULL mode emulator\newline 8: FELIX\_MROD mode\newline 9: lpGBT mode\newline \newline \\
-=======
0x0190 & 0,1 & FIRMWARE\_MODE &
3:0 & R & 0: GBT mode\newline 1: FULL mode\newline 2: LTDB mode (GBT mode with only IC and TTC links)\newline 3: FEI4 mode\newline 4: ITK Pixel\newline 5: ITK Strip\newline 6: FELIG\newline 7: FULL mode emulator\newline 8: FELIX\_MROD mode\newline \newline \\
->>>>>>> master
\hline
0x01A0 & 0,1 & GTREFCLK\_SOURCE &
1:0 & R & 0: Transceiver reference Clock source from Si5345\newline 1: Transceiver reference Clock source from Si5324\newline 2: Transceiver reference Clock from internal BUFG (GREFCLK)\newline \\
@@ -299,548 +280,6 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
0x01F0 & 0,1 & NUMBER\_OF\_PCIE\_ENDPOINTS &
1:0 & R & Number of PCIe endpoints on the card. The BNL71x cards have 2 endpoints \\
\hline
-<<<<<<< HEAD
-0x0200 & 0,1 & \multicolumn{2}{l|}{SUPER\_CHUNK\_FACTOR} &
-7:0 & R & Number of full mode chunks glued together as one chunk \\
-\hline
-\multicolumn{7}{|c|}{CR To Host Controls And Monitors} \\
-\hline
-0x0800 & 0,1 & \multicolumn{5}{l|}{TIMEOUT\_CTRL} \\
-\cline{3-7}
- & & & ENABLE & 32 & W & 1 enables the timout trailer generation for ToHost mode \\
- & & & TIMEOUT & 31:0 & W & Number of 40 MHz clock cycles after which a timeout occurs. \\
-\hline
-0x0810 & 0,1 & \multicolumn{2}{l|}{MAX\_TIMEOUT} &
-31:0 & R & Maximum allowed timeout value \\
-\hline
-0x0820 & 0,1 & \multicolumn{5}{l|}{CRTOHOST\_FIFO\_STATUS} \\
-\cline{3-7}
- & & & CLEAR & any & T & Any write to this register clears the latched FULL flags \\
- & & & FULL & 47:24 & R & Every bit represents the full flag of a channel FIFO \\
- & & & FULL\_LATCHED & 23:0 & R & like FULL but a latched state, clear by writing to this register \\
-\hline
-\multicolumn{7}{|c|}{CR From Host Controls And Monitors} \\
-\hline
-0x1000 & 0,1 & \multicolumn{5}{l|}{CRFROMHOST\_FIFO\_STATUS} \\
-\cline{3-7}
- & & & CLEAR & any & T & Any write to this register clears the latched FULL flags \\
- & & & FULL & 47:24 & R & Every bit represents the full flag of a channel FIFO \\
- & & & FULL\_LATCHED & 23:0 & R & like FULL but a latched state, clear by writing to this register \\
-\hline
-\multicolumn{7}{|c|}{BROADCAST\_ENABLE\_GEN} \\
-\hline
-0x1010 & 0,1 & \multicolumn{2}{l|}{BROADCAST\_ENABLE\_00} &
-41:0 & W & Enable path to be included in a broadcast message. \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-0x1180 & 0,1 & \multicolumn{2}{l|}{BROADCAST\_ENABLE\_23} &
-41:0 & W & Enable path to be included in a broadcast message. \\
-\hline
-\multicolumn{7}{|c|}{Decoding Controls And Monitors} \\
-\hline
-\multicolumn{7}{|c|}{PATH\_HAS\_STREAM\_ID} \\
-\hline
-0x2000 & 0,1 & \multicolumn{5}{l|}{LINK\_00\_HAS\_STREAM\_ID} \\
-\cline{3-7}
- & & & EGROUP6 & 55:48 & W & EPATH (Wide mode or lpGBT) is associated with a STREAM ID \\
- & & & EGROUP5 & 47:40 & W & EPATH (Wide mode or lpGBT) is associated with a STREAM ID \\
- & & & EGROUP4 & 39:32 & W & EPATH is associated with a STREAM ID \\
- & & & EGROUP3 & 31:24 & W & EPATH is associated with a STREAM ID \\
- & & & EGROUP2 & 23:16 & W & EPATH is associated with a STREAM ID \\
- & & & EGROUP1 & 15:8 & W & EPATH is associated with a STREAM ID \\
- & & & EGROUP0 & 7:0 & W & EPATH is associated with a STREAM ID, use only bit0 for FULL mode. \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-0x2170 & 0,1 & \multicolumn{5}{l|}{LINK\_23\_HAS\_STREAM\_ID} \\
-\cline{3-7}
- & & & EGROUP6 & 55:48 & W & EPATH (Wide mode or lpGBT) is associated with a STREAM ID \\
- & & & EGROUP5 & 47:40 & W & EPATH (Wide mode or lpGBT) is associated with a STREAM ID \\
- & & & EGROUP4 & 39:32 & W & EPATH is associated with a STREAM ID \\
- & & & EGROUP3 & 31:24 & W & EPATH is associated with a STREAM ID \\
- & & & EGROUP2 & 23:16 & W & EPATH is associated with a STREAM ID \\
- & & & EGROUP1 & 15:8 & W & EPATH is associated with a STREAM ID \\
- & & & EGROUP0 & 7:0 & W & EPATH is associated with a STREAM ID, use only bit0 for FULL mode. \\
-\hline
-\multicolumn{7}{|c|}{DECODING\_LINK\_STATUS\_ARR} \\
-\hline
-0x2180 & 0,1 & \multicolumn{2}{l|}{DECODING\_LINK\_ALIGNED\_00} &
-57:0 & R & Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-0x22F0 & 0,1 & \multicolumn{2}{l|}{DECODING\_LINK\_ALIGNED\_23} &
-57:0 & R & Every bit corresponds to an E-link on one (lp)GBT or FULL-mode frame. For FULL mode only bit 0 is used \\
-\hline
-\multicolumn{7}{|c|}{DECODING\_EGROUP\_CTRL\_GEN} \\
-\hline
-\multicolumn{7}{|c|}{DECODING\_EGROUP} \\
-\hline
-0x2300 & 0,1 & \multicolumn{5}{l|}{DECODING\_LINK00\_EGROUP0\_CTRL} \\
-\cline{3-7}
- & & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
- & & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
- & & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
- & & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
- & & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-0x2360 & 0,1 & \multicolumn{5}{l|}{DECODING\_LINK00\_EGROUP6\_CTRL} \\
-\cline{3-7}
- & & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
- & & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
- & & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
- & & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
- & & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-\multicolumn{7}{|c|}{DECODING\_EGROUP} \\
-\hline
-0x27D0 & 0,1 & \multicolumn{5}{l|}{DECODING\_LINK11\_EGROUP0\_CTRL} \\
-\cline{3-7}
- & & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
- & & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
- & & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
- & & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
- & & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-0x2830 & 0,1 & \multicolumn{5}{l|}{DECODING\_LINK11\_EGROUP6\_CTRL} \\
-\cline{3-7}
- & & & EPATH\_ALMOST\_FULL & 58:51 & R & FIFO full indication \\
- & & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
- & & & PATH\_ENCODING & 42:11 & W & Encoding for every EPATH, 4 bits per E-path\newline 0: direct mode\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: TTC\newline 4: ITk Strips 8b10b\newline 5: ITk Pixel\newline 6: Endeavour\newline 7-15: reserved\newline \\
- & & & EPATH\_WIDTH & 10:8 & W & Width in bits of all EPATHS in an EGROUP 0:2, 1:4, 2:8, 3:16, 4:32 \\
- & & & EPATH\_ENA & 7:0 & W & Enable bits per EPROC \\
-\hline
-\multicolumn{7}{|c|}{MINI\_EGROUP\_TOHOST\_GEN} \\
-\hline
-0x2840 & 0,1 & \multicolumn{5}{l|}{MINI\_EGROUP\_TOHOST\_00} \\
-\cline{3-7}
- & & & AUX\_ALMOST\_FULL & 12 & R & Indicator that the AUX path FIFO is almost full \\
- & & & AUX\_BIT\_SWAPPING & 11 & W & 0: two input bits of IC e-link are as documented, 1: two input bits are swapped \\
- & & & AUX\_ENABLE & 10 & W & Enables the AUX channel \\
- & & & IC\_ALMOST\_FULL & 9 & R & Indicator that the IC path FIFO is almost full \\
- & & & IC\_BIT\_SWAPPING & 8 & W & 0: two input bits of IC e-link are as documented, 1: two input bits are swapped \\
- & & & IC\_ENABLE & 7 & W & Enables the IC channel \\
- & & & EC\_ALMOST\_FULL & 6 & R & Indicator that the EC path FIFO is almost full \\
- & & & EC\_BIT\_SWAPPING & 5 & W & 0: two input bits of EC e-link are as documented, 1: two input bits are swapped \\
- & & & EC\_ENCODING & 4:1 & W & Configures encoding of the EC channel \\
- & & & EC\_ENABLE & 0 & W & Enables the EC channel \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-0x29B0 & 0,1 & \multicolumn{5}{l|}{MINI\_EGROUP\_TOHOST\_23} \\
-\cline{3-7}
- & & & AUX\_ALMOST\_FULL & 12 & R & Indicator that the AUX path FIFO is almost full \\
- & & & AUX\_BIT\_SWAPPING & 11 & W & 0: two input bits of IC e-link are as documented, 1: two input bits are swapped \\
- & & & AUX\_ENABLE & 10 & W & Enables the AUX channel \\
- & & & IC\_ALMOST\_FULL & 9 & R & Indicator that the IC path FIFO is almost full \\
- & & & IC\_BIT\_SWAPPING & 8 & W & 0: two input bits of IC e-link are as documented, 1: two input bits are swapped \\
- & & & IC\_ENABLE & 7 & W & Enables the IC channel \\
- & & & EC\_ALMOST\_FULL & 6 & R & Indicator that the EC path FIFO is almost full \\
- & & & EC\_BIT\_SWAPPING & 5 & W & 0: two input bits of EC e-link are as documented, 1: two input bits are swapped \\
- & & & EC\_ENCODING & 4:1 & W & Configures encoding of the EC channel \\
- & & & EC\_ENABLE & 0 & W & Enables the EC channel \\
-\hline
-0x29C0 & 0,1 & \multicolumn{2}{l|}{TTC\_TOHOST\_ENABLE} &
-0 & W & Enables the ToHost Mini Egroup in TTC mode \\
-\hline
-0x29D0 & 0,1 & \multicolumn{2}{l|}{DECODING\_REVERSE\_10B} &
-0 & W & Reverse 10-bit word of elink data for 8b10b E-links\newline 1: Receive 10-bit word in ToHost E-Paths, MSB first\newline 0: Receive 10-bit word in ToHost E-Paths, LSB first\newline \\
-\hline
-\multicolumn{7}{|c|}{RD53 B\_PROCESSOR\_GEN} \\
-\hline
-0x29E0 & 0,1 & \multicolumn{5}{l|}{RD53B\_PROCESSOR\_00} \\
-\cline{3-7}
- & & & ENABLE\_MULTICHIP & 3 & R & Decoding block \\
- & & & ENABLE\_BINARYTREE & 2 & R & Decoding block \\
- & & & ENABLE\_TOT & 1 & R & Decoding block \\
- & & & DROP\_TOT & 0 & R & Decoding block \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-0x2DD0 & 0,1 & \multicolumn{5}{l|}{RD53B\_PROCESSOR\_63} \\
-\cline{3-7}
- & & & ENABLE\_MULTICHIP & 3 & R & Decoding block \\
- & & & ENABLE\_BINARYTREE & 2 & R & Decoding block \\
- & & & ENABLE\_TOT & 1 & R & Decoding block \\
- & & & DROP\_TOT & 0 & R & Decoding block \\
-\hline
-\multicolumn{7}{|c|}{Encoding Controls And Monitors} \\
-\hline
-0x3000 & 0,1 & \multicolumn{2}{l|}{ENCODING\_REVERSE\_10B} &
-0 & W & Reverse 10-bit word of elink data for 8b10b E-links. 1 MSB first, 0 LSB first \\
-\hline
-\multicolumn{7}{|c|}{ENCODING\_EGROUP\_CTRL\_GEN} \\
-\hline
-\multicolumn{7}{|c|}{ENCODING\_EGROUP} \\
-\hline
-0x3010 & 0,1 & \multicolumn{5}{l|}{ENCODING\_LINK00\_EGROUP0\_CTRL} \\
-\cline{3-7}
- & & & TTC\_OPTION & 62:59 & W & Selects TTC bits sent to the E-link \\
- & & & EPATH\_ALMOST\_FULL & 58:51 & R & Indiator that the EPATH FIFO is almost full \\
- & & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
- & & & EPATH\_WIDTH & 42:40 & W & Width of the Elinks in the egroup\newline 0: 2 bit 80 Mb/s\newline 1: 4 bit 160 Mb/s\newline 2: 8 bit 320 Mb/s\newline \\
- & & & PATH\_ENCODING & 39:8 & W & Encoding for every EPATH, 4 bits per E-Path\newline 0: No encoding\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: ITk Strip LCB\newline 4: ITk Pixel\newline 5: Endeavour\newline 6: reserved\newline 7: reserved\newline greater than 7: TTC mode, see firmware Phase 2 specification doc\newline \\
- & & & EPATH\_ENA & 7:0 & W & Enable bits per E-PATH \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-0x3050 & 0,1 & \multicolumn{5}{l|}{ENCODING\_LINK00\_EGROUP4\_CTRL} \\
-\cline{3-7}
- & & & TTC\_OPTION & 62:59 & W & Selects TTC bits sent to the E-link \\
- & & & EPATH\_ALMOST\_FULL & 58:51 & R & Indiator that the EPATH FIFO is almost full \\
- & & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
- & & & EPATH\_WIDTH & 42:40 & W & Width of the Elinks in the egroup\newline 0: 2 bit 80 Mb/s\newline 1: 4 bit 160 Mb/s\newline 2: 8 bit 320 Mb/s\newline \\
- & & & PATH\_ENCODING & 39:8 & W & Encoding for every EPATH, 4 bits per E-Path\newline 0: No encoding\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: ITk Strip LCB\newline 4: ITk Pixel\newline 5: Endeavour\newline 6: reserved\newline 7: reserved\newline greater than 7: TTC mode, see firmware Phase 2 specification doc\newline \\
- & & & EPATH\_ENA & 7:0 & W & Enable bits per E-PATH \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-\multicolumn{7}{|c|}{ENCODING\_EGROUP} \\
-\hline
-0x3380 & 0,1 & \multicolumn{5}{l|}{ENCODING\_LINK11\_EGROUP0\_CTRL} \\
-\cline{3-7}
- & & & TTC\_OPTION & 62:59 & W & Selects TTC bits sent to the E-link \\
- & & & EPATH\_ALMOST\_FULL & 58:51 & R & Indiator that the EPATH FIFO is almost full \\
- & & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
- & & & EPATH\_WIDTH & 42:40 & W & Width of the Elinks in the egroup\newline 0: 2 bit 80 Mb/s\newline 1: 4 bit 160 Mb/s\newline 2: 8 bit 320 Mb/s\newline \\
- & & & PATH\_ENCODING & 39:8 & W & Encoding for every EPATH, 4 bits per E-Path\newline 0: No encoding\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: ITk Strip LCB\newline 4: ITk Pixel\newline 5: Endeavour\newline 6: reserved\newline 7: reserved\newline greater than 7: TTC mode, see firmware Phase 2 specification doc\newline \\
- & & & EPATH\_ENA & 7:0 & W & Enable bits per E-PATH \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-0x33C0 & 0,1 & \multicolumn{5}{l|}{ENCODING\_LINK11\_EGROUP4\_CTRL} \\
-\cline{3-7}
- & & & TTC\_OPTION & 62:59 & W & Selects TTC bits sent to the E-link \\
- & & & EPATH\_ALMOST\_FULL & 58:51 & R & Indiator that the EPATH FIFO is almost full \\
- & & & REVERSE\_ELINKS & 50:43 & W & enables bit reversing for the elink in the given epath \\
- & & & EPATH\_WIDTH & 42:40 & W & Width of the Elinks in the egroup\newline 0: 2 bit 80 Mb/s\newline 1: 4 bit 160 Mb/s\newline 2: 8 bit 320 Mb/s\newline \\
- & & & PATH\_ENCODING & 39:8 & W & Encoding for every EPATH, 4 bits per E-Path\newline 0: No encoding\newline 1: 8b10b mode\newline 2: HDLC mode\newline 3: ITk Strip LCB\newline 4: ITk Pixel\newline 5: Endeavour\newline 6: reserved\newline 7: reserved\newline greater than 7: TTC mode, see firmware Phase 2 specification doc\newline \\
- & & & EPATH\_ENA & 7:0 & W & Enable bits per E-PATH \\
-\hline
-\multicolumn{7}{|c|}{MINI\_EGROUP\_FROMHOST\_GEN} \\
-\hline
-0x33D0 & 0,1 & \multicolumn{5}{l|}{MINI\_EGROUP\_FROMHOST\_00} \\
-\cline{3-7}
- & & & AUX\_ALMOST\_FULL & 12 & R & Indicator that the AUX Path FIFO is almost full \\
- & & & AUX\_BIT\_SWAPPING & 11 & W & 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped \\
- & & & AUX\_ENABLE & 10 & W & Enables the AUX channel \\
- & & & IC\_ALMOST\_FULL & 9 & R & Indicator that the IC Path FIFO is almost full \\
- & & & IC\_BIT\_SWAPPING & 8 & W & 0: two input bits of IC e-link are as documented, 1: two input bits are swapped \\
- & & & IC\_ENABLE & 7 & W & Enables the IC channel \\
- & & & EC\_ALMOST\_FULL & 6 & R & Indicator that the EC Path FIFO is almost full \\
- & & & EC\_BIT\_SWAPPING & 5 & W & 0: two output bits of EC e-link are as documented, 1: two output bits are swapped \\
- & & & EC\_ENCODING & 4:1 & W & Configures encoding of the EC channel \\
- & & & EC\_ENABLE & 0 & W & Configures the FromHost Mini egroup \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-0x3540 & 0,1 & \multicolumn{5}{l|}{MINI\_EGROUP\_FROMHOST\_23} \\
-\cline{3-7}
- & & & AUX\_ALMOST\_FULL & 12 & R & Indicator that the AUX Path FIFO is almost full \\
- & & & AUX\_BIT\_SWAPPING & 11 & W & 0: two input bits of AUX e-link are as documented, 1: two input bits are swapped \\
- & & & AUX\_ENABLE & 10 & W & Enables the AUX channel \\
- & & & IC\_ALMOST\_FULL & 9 & R & Indicator that the IC Path FIFO is almost full \\
- & & & IC\_BIT\_SWAPPING & 8 & W & 0: two input bits of IC e-link are as documented, 1: two input bits are swapped \\
- & & & IC\_ENABLE & 7 & W & Enables the IC channel \\
- & & & EC\_ALMOST\_FULL & 6 & R & Indicator that the EC Path FIFO is almost full \\
- & & & EC\_BIT\_SWAPPING & 5 & W & 0: two output bits of EC e-link are as documented, 1: two output bits are swapped \\
- & & & EC\_ENCODING & 4:1 & W & Configures encoding of the EC channel \\
- & & & EC\_ENABLE & 0 & W & Configures the FromHost Mini egroup \\
-\hline
-\multicolumn{7}{|c|}{ENCODING\_EGROUP\_CTRL\_FEI4\_GEN} \\
-\hline
-\multicolumn{7}{|c|}{ENCODING\_EGROUP\_FEI4} \\
-\hline
-0x3550 & 0,1 & \multicolumn{5}{l|}{ENCODING\_LINK00\_EGROUP0\_FEI4\_CTRL} \\
-\cline{3-7}
- & & & PHASE\_DELAY1 & 11:9 & W & phase delay of output data, with 320 Bb/s e-link 8 phases per BC \\
- & & & MANCHESTER\_ENABLE1 & 8 & W & enable manchester encoding \\
- & & & AUTOMATIC\_MERGE\_DISABLE1 & 7 & W & Disable automatic merging \\
- & & & TTC\_SELECT1 & 6 & W & TTC/FromHost select (if automatic merging is disabled) \\
- & & & PHASE\_DELAY0 & 5:3 & W & phase delay of output data, with 320 Bb/s e-link 8 phases per BC \\
- & & & MANCHESTER\_ENABLE0 & 2 & W & enable manchester encoding \\
- & & & AUTOMATIC\_MERGE\_DISABLE0 & 1 & W & Disable automatic merging \\
- & & & TTC\_SELECT0 & 0 & W & TTC/FromHost select (if automatic merging is disabled) \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-0x3590 & 0,1 & \multicolumn{5}{l|}{ENCODING\_LINK00\_EGROUP4\_FEI4\_CTRL} \\
-\cline{3-7}
- & & & PHASE\_DELAY1 & 11:9 & W & phase delay of output data, with 320 Bb/s e-link 8 phases per BC \\
- & & & MANCHESTER\_ENABLE1 & 8 & W & enable manchester encoding \\
- & & & AUTOMATIC\_MERGE\_DISABLE1 & 7 & W & Disable automatic merging \\
- & & & TTC\_SELECT1 & 6 & W & TTC/FromHost select (if automatic merging is disabled) \\
- & & & PHASE\_DELAY0 & 5:3 & W & phase delay of output data, with 320 Bb/s e-link 8 phases per BC \\
- & & & MANCHESTER\_ENABLE0 & 2 & W & enable manchester encoding \\
- & & & AUTOMATIC\_MERGE\_DISABLE0 & 1 & W & Disable automatic merging \\
- & & & TTC\_SELECT0 & 0 & W & TTC/FromHost select (if automatic merging is disabled) \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-\multicolumn{7}{|c|}{ENCODING\_EGROUP\_FEI4} \\
-\hline
-0x38C0 & 0,1 & \multicolumn{5}{l|}{ENCODING\_LINK11\_EGROUP0\_FEI4\_CTRL} \\
-\cline{3-7}
- & & & PHASE\_DELAY1 & 11:9 & W & phase delay of output data, with 320 Bb/s e-link 8 phases per BC \\
- & & & MANCHESTER\_ENABLE1 & 8 & W & enable manchester encoding \\
- & & & AUTOMATIC\_MERGE\_DISABLE1 & 7 & W & Disable automatic merging \\
- & & & TTC\_SELECT1 & 6 & W & TTC/FromHost select (if automatic merging is disabled) \\
- & & & PHASE\_DELAY0 & 5:3 & W & phase delay of output data, with 320 Bb/s e-link 8 phases per BC \\
- & & & MANCHESTER\_ENABLE0 & 2 & W & enable manchester encoding \\
- & & & AUTOMATIC\_MERGE\_DISABLE0 & 1 & W & Disable automatic merging \\
- & & & TTC\_SELECT0 & 0 & W & TTC/FromHost select (if automatic merging is disabled) \\
-\hline
-\multicolumn{7}{|c|}{\ldots} \\
-\hline
-0x3900 & 0,1 & \multicolumn{5}{l|}{ENCODING\_LINK11\_EGROUP4\_FEI4\_CTRL} \\
-\cline{3-7}
- & & & PHASE\_DELAY1 & 11:9 & W & phase delay of output data, with 320 Bb/s e-link 8 phases per BC \\
- & & & MANCHESTER\_ENABLE1 & 8 & W & enable manchester encoding \\
- & & & AUTOMATIC\_MERGE\_DISABLE1 & 7 & W & Disable automatic merging \\
- & & & TTC\_SELECT1 & 6 & W & TTC/FromHost select (if automatic merging is disabled) \\
- & & & PHASE\_DELAY0 & 5:3 & W & phase delay of output data, with 320 Bb/s e-link 8 phases per BC \\
- & & & MANCHESTER\_ENABLE0 & 2 & W & enable manchester encoding \\
- & & & AUTOMATIC\_MERGE\_DISABLE0 & 1 & W & Disable automatic merging \\
- & & & TTC\_SELECT0 & 0 & W & TTC/FromHost select (if automatic merging is disabled) \\
-\hline
-\multicolumn{7}{|c|}{Frontend Emulator Controls And Monitors} \\
-\hline
-0x4000 & 0, 1 & \multicolumn{5}{l|}{FE\_EMU\_ENA} \\
-\cline{3-7}
- & & & EMU\_TOFRONTEND & 1 & W & Enable GBT dummy emulator ToFrontEnd \\
- & & & EMU\_TOHOST & 0 & W & Enable GBT dummy emulator ToHost \\
-\hline
-0x4010 & 0, 1 & \multicolumn{5}{l|}{FE\_EMU\_CONFIG} \\
-\cline{3-7}
- & & & WE & 54:47 & W & write enable array, every bit is one emulator RAM block \\
- & & & WRADDR & 46:33 & W & write address bus \\
- & & & WRDATA & 32:0 & W & write data bus \\
-\hline
-0x4020 & 0, 1 & \multicolumn{5}{l|}{FE\_EMU\_READ} \\
-\cline{3-7}
- & & & SEL & 35:33 & W & Select ramblock to read back \\
- & & & DATA & 32:0 & R & Read back ramblock at FE\_EMU\_CONFIG.WRADDR \\
-\hline
-\multicolumn{7}{|c|}{Link Wrapper Controls} \\
-\hline
-0x5400 & 0 & \multicolumn{2}{l|}{GBT\_CHANNEL\_DISABLE} &
-47:0 & W & Disable selected lpGBT, GBT or FULL mode channel \\
-\hline
-0x5410 & 0 & \multicolumn{2}{l|}{GBT\_GENERAL\_CTRL} &
-63:0 & W & Alignment chk reset (not self clearing) \\
-\hline
-0x5420 & 0 & \multicolumn{5}{l|}{GBT\_MODE\_CTRL} \\
-\cline{3-7}
- & & & RX\_ALIGN\_TB\_SW & 2 & W & RX\_ALIGN\_TB\_SW \\
- & & & RX\_ALIGN\_SW & 1 & W & RX\_ALIGN\_SW \\
- & & & DESMUX\_USE\_SW & 0 & W & DESMUX\_USE\_SW \\
-\hline
-0x5480 & 0 & \multicolumn{2}{l|}{GBT\_RXSLIDE\_SELECT} &
-47:0 & W & RxSlide select [47:0] \\
-\hline
-0x5490 & 0 & \multicolumn{2}{l|}{GBT\_RXSLIDE\_MANUAL} &
-47:0 & W & RxSlide select [47:0] \\
-\hline
-0x54A0 & 0 & \multicolumn{2}{l|}{GBT\_TXUSRRDY} &
-47:0 & W & TxUsrRdy [47:0] \\
-\hline
-0x54B0 & 0 & \multicolumn{2}{l|}{GBT\_RXUSRRDY} &
-47:0 & W & RxUsrRdy [47:0] \\
-\hline
-0x54C0 & 0 & \multicolumn{2}{l|}{GBT\_SOFT\_RESET} &
-47:0 & W & SOFT\_RESET [47:0] \\
-\hline
-0x54D0 & 0 & \multicolumn{2}{l|}{GBT\_GTTX\_RESET} &
-47:0 & W & GTTX\_RESET [47:0] \\
-\hline
-0x54E0 & 0 & \multicolumn{2}{l|}{GBT\_GTRX\_RESET} &
-47:0 & W & GTRX\_RESET [47:0] \\
-\hline
-0x54F0 & 0 & \multicolumn{5}{l|}{GBT\_PLL\_RESET} \\
-\cline{3-7}
- & & & QPLL\_RESET & 59:48 & W & QPLL\_RESET [11:0] \\
- & & & CPLL\_RESET & 47:0 & W & CPLL\_RESET [47:0] \\
-\hline
-0x5500 & 0 & \multicolumn{5}{l|}{GBT\_SOFT\_TX\_RESET} \\
-\cline{3-7}
- & & & RESET\_ALL & 59:48 & W & SOFT\_TX\_RESET\_ALL [11:0] \\
- & & & RESET\_GT & 47:0 & W & SOFT\_TX\_RESET\_GT [47:0] \\
-\hline
-0x5510 & 0 & \multicolumn{5}{l|}{GBT\_SOFT\_RX\_RESET} \\
-\cline{3-7}
- & & & RESET\_ALL & 59:48 & W & SOFT\_TX\_RESET\_ALL [11:0] \\
- & & & RESET\_GT & 47:0 & W & SOFT\_TX\_RESET\_GT [47:0] \\
-\hline
-0x5520 & 0 & \multicolumn{2}{l|}{GBT\_ODD\_EVEN} &
-47:0 & W & OddEven [47:0] \\
-\hline
-0x5530 & 0 & \multicolumn{2}{l|}{GBT\_TOPBOT} &
-47:0 & W & TopBot [47:0] \\
-\hline
-0x5540 & 0 & \multicolumn{2}{l|}{GBT\_TX\_TC\_DLY\_VALUE1} &
-47:0 & W & TX\_TC\_DLY\_VALUE [47:0] \\
-\hline
-0x5550 & 0 & \multicolumn{2}{l|}{GBT\_TX\_TC\_DLY\_VALUE2} &
-47:0 & W & TX\_TC\_DLY\_VALUE [95:48] \\
-\hline
-0x5560 & 0 & \multicolumn{2}{l|}{GBT\_TX\_TC\_DLY\_VALUE3} &
-47:0 & W & TX\_TC\_DLY\_VALUE [143:96] \\
-\hline
-0x5570 & 0 & \multicolumn{2}{l|}{GBT\_TX\_TC\_DLY\_VALUE4} &
-47:0 & W & TX\_TC\_DLY\_VALUE [191:144] \\
-\hline
-0x5580 & 0 & \multicolumn{2}{l|}{GBT\_DATA\_TXFORMAT1} &
-47:0 & W & DATA\_TXFORMAT [47:0] \\
-\hline
-0x5590 & 0 & \multicolumn{2}{l|}{GBT\_DATA\_TXFORMAT2} &
-47:0 & W & DATA\_TXFORMAT [95:48] \\
-\hline
-0x55A0 & 0 & \multicolumn{2}{l|}{GBT\_DATA\_RXFORMAT1} &
-47:0 & W & DATA\_RXFORMAT [47:0] \\
-\hline
-0x55B0 & 0 & \multicolumn{2}{l|}{GBT\_DATA\_RXFORMAT2} &
-47:0 & W & DATA\_RXFORMAT [95:0] \\
-\hline
-0x55C0 & 0 & \multicolumn{2}{l|}{GBT\_TX\_RESET} &
-47:0 & W & TX Logic reset [47:0] \\
-\hline
-0x55D0 & 0 & \multicolumn{2}{l|}{GBT\_RX\_RESET} &
-47:0 & W & RX Logic reset [47:0] \\
-\hline
-0x55E0 & 0 & \multicolumn{2}{l|}{GBT\_TX\_TC\_METHOD} &
-47:0 & W & TX time domain crossing method [47:0] \\
-\hline
-0x55F0 & 0 & \multicolumn{2}{l|}{GBT\_OUTMUX\_SEL} &
-47:0 & W & Descrambler output MUX selection [47:0] \\
-\hline
-0x5600 & 0 & \multicolumn{2}{l|}{GBT\_TC\_EDGE} &
-47:0 & W & Sampling edge selection for TX domain crossing [47:0] \\
-\hline
-0x5610 & 0 & \multicolumn{2}{l|}{GBT\_TXPOLARITY} &
-47:0 & W & 0: default polarity\newline 1: reversed polarity for transmitter of GTH channels\newline \\
-\hline
-0x5620 & 0 & \multicolumn{2}{l|}{GBT\_RXPOLARITY} &
-47:0 & W & 0: default polarity\newline 1: reversed polarity for the receiver of the GTH channels\newline \\
-\hline
-0x5630 & 0 & \multicolumn{2}{l|}{GTH\_LOOPBACK\_CONTROL} &
-2:0 & W & Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.\newline 000: Normal operation\newline 001: Near-End PCS Loopback\newline 010: Near-End PMA Loopback\newline 011: Reserved\newline 100: Far-End PMA Loopback\newline 101: Reserved\newline 110: Far-End PCS Loopback \newline \\
-\hline
-0x5700 & 0 & \multicolumn{5}{l|}{GBT\_TOHOST\_FANOUT} \\
-\cline{3-7}
- & & & LOCK & 48 & W & Locks this particular register. If set prevents software from touching it. \\
- & & & SEL & 47:0 & W & ToHost FanOut/Selector. Every bitfield is a channel:\newline 1 : GBT\_EMU, select GBT Emulator for a specific CentralRouter channel\newline 0 : GBT\_WRAP, select real GBT link for a specific CentralRouter channel\newline \\
-\hline
-0x5710 & 0 & \multicolumn{5}{l|}{GBT\_TOFRONTEND\_FANOUT} \\
-\cline{3-7}
- & & & LOCK & 48 & W & Locks this particular register. If set prevents software from touching it. \\
- & & & SEL & 47:0 & W & ToFrontEnd FanOut/Selector. Every bitfield is a channel:\newline 1 : GBT\_EMU, select GBT Emulator for a specific GBT link\newline 0 : TTC\_DEC, select CentralRouter data (including TTC) for a specific GBT link\newline \newline \\
-\hline
-\multicolumn{7}{|c|}{Link Wrapper Monitors} \\
-\hline
-0x6600 & 0 & \multicolumn{5}{l|}{GBT\_VERSION} \\
-\cline{3-7}
- & & & DATE & 63:48 & R & Date \\
- & & & GBT\_VERSION & 47:32 & R & GBT Version \\
- & & & GTH\_IP\_VERSION & 31:16 & R & GTH IP Version \\
- & & & RESERVED & 15:3 & R & Reserved \\
- & & & GTHREFCLK\_SEL & 2 & R & GTHREFCLK SEL \\
- & & & RX\_CLK\_SEL & 1 & R & RX CLK SEL \\
- & & & PLL\_SEL & 0 & R & PLL SEL \\
-\hline
-0x6680 & 0 & \multicolumn{2}{l|}{GBT\_TXRESET\_DONE} &
-47:0 & R & TX Reset done [47:0] \\
-\hline
-0x6690 & 0 & \multicolumn{2}{l|}{GBT\_RXRESET\_DONE} &
-47:0 & R & RX Reset done [47:0] \\
-\hline
-0x66A0 & 0 & \multicolumn{2}{l|}{GBT\_TXFSMRESET\_DONE} &
-47:0 & R & TX FSM Reset done [47:0] \\
-\hline
-0x66B0 & 0 & \multicolumn{2}{l|}{GBT\_RXFSMRESET\_DONE} &
-47:0 & R & RX FSM Reset done [47:0] \\
-\hline
-0x66C0 & 0 & \multicolumn{2}{l|}{GBT\_CPLL\_FBCLK\_LOST} &
-47:0 & R & CPLL FBCLK LOST [47:0] \\
-\hline
-0x66D0 & 0 & \multicolumn{5}{l|}{GBT\_PLL\_LOCK} \\
-\cline{3-7}
- & & & QPLL\_LOCK & 59:48 & R & QPLL LOCK [11:0] \\
- & & & CPLL\_LOCK & 47:0 & R & CPLL LOCK [47:0] \\
-\hline
-0x66E0 & 0 & \multicolumn{2}{l|}{GBT\_RXCDR\_LOCK} &
-47:0 & R & RX CDR LOCK [47:0] \\
-\hline
-0x66F0 & 0 & \multicolumn{2}{l|}{GBT\_CLK\_SAMPLED} &
-47:0 & R & clk sampled [47:0] \\
-\hline
-0x6700 & 0 & \multicolumn{2}{l|}{GBT\_RX\_IS\_HEADER} &
-47:0 & R & RX IS HEADER [47:0] \\
-\hline
-0x6710 & 0 & \multicolumn{2}{l|}{GBT\_RX\_IS\_DATA} &
-47:0 & R & RX IS DATA [47:0] \\
-\hline
-0x6720 & 0 & \multicolumn{2}{l|}{GBT\_RX\_HEADER\_FOUND} &
-47:0 & R & RX HEADER FOUND [47:0] \\
-\hline
-0x6730 & 0 & \multicolumn{2}{l|}{GBT\_ALIGNMENT\_DONE} &
-47:0 & R & RX ALIGNMENT DONE [47:0] \\
-\hline
-0x6740 & 0 & \multicolumn{2}{l|}{GBT\_OUT\_MUX\_STATUS} &
-47:0 & R & GBT output mux status [47:0] \\
-\hline
-0x6750 & 0 & \multicolumn{2}{l|}{GBT\_ERROR} &
-47:0 & R & Error flags [47:0] \\
-\hline
-0x6760 & 0 & \multicolumn{2}{l|}{GBT\_GBT\_TOPBOT\_C} &
-47:0 & R & TopBot\_c [47:0] \\
-\hline
-0x6800 & 0 & \multicolumn{2}{l|}{GBT\_FM\_RX\_DISP\_ERROR1} &
-47:0 & R & Rx disparity error [47:0] \\
-\hline
-0x6810 & 0 & \multicolumn{2}{l|}{GBT\_FM\_RX\_DISP\_ERROR2} &
-47:0 & R & Rx disparity error [96:48] \\
-\hline
-0x6820 & 0 & \multicolumn{2}{l|}{GBT\_FM\_RX\_NOTINTABLE1} &
-47:0 & R & Rx not in table [47:0] \\
-\hline
-0x6830 & 0 & \multicolumn{2}{l|}{GBT\_FM\_RX\_NOTINTABLE2} &
-47:0 & R & Rx not in table [96:48] \\
-\hline
-\multicolumn{7}{|c|}{TTCBUSY Controls And Monitors} \\
-\hline
-\multicolumn{7}{|c|}{TTC\_DEC\_CTRLMON} \\
-\hline
-0x7000 & 0 & \multicolumn{5}{l|}{TTC\_DEC\_CTRL} \\
-\cline{3-7}
- & & & L1A\_DELAY & 30:27 & W & Number of BC to delay the L1A distribution to the frontends \\
- & & & BCID\_ONBCR & 26:15 & W & BCID is set to this value when BCR arrives \\
- & & & BUSY\_OUTPUT\_STATUS & 14 & R & Actual status of the BUSY LEMO output signal \\
- & & & ECR\_BCR\_SWAP & 13 & W & ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC) \\
- & & & BUSY\_OUTPUT\_INHIBIT & 12 & W & forces the Busy LEMO output to BUSY-OFF \\
- & & & TOHOST\_RST & 11 & W & reset toHost in ttc decoder \\
- & & & TT\_BCH\_EN & 10 & W & trigger type enable / disable for TTC-ToHost \\
- & & & XL1ID\_SW & 9:2 & W & set XL1ID value, the value to be set by XL1ID\_RST signal \\
- & & & XL1ID\_RST & 1 & W & giving a trigger signal to reset XL1ID value \\
- & & & MASTER\_BUSY & 0 & W & L1A trigger throttling \\
-\hline
-0x7010 & 0 & \multicolumn{5}{l|}{TTC\_DEC\_MON} \\
-\cline{3-7}
- & & & TH\_FF\_COUNT & 15:5 & R & ToHostData Fifo counts \\
- & & & TH\_FF\_FULL & 4 & R & ToHostData Fifo status 1:full 0:not full \\
- & & & TH\_FF\_EMPTY & 3 & R & ToHostData Fifo status 1:empty 0:not empty \\
- & & & TTC\_BIT\_ERR & 2:0 & R & double bit, single bit and comm error in TTC data \\
-\hline
-\multicolumn{7}{|c|}{TTC\_BUSY\_ACCEPTED\_G} \\
-\hline
-0x7020 & 0,1 & \multicolumn{2}{l|}{TTC\_BUSY\_ACCEPTED00} &
-=======
\multicolumn{6}{|c|}{Central Router Controls And Monitors} \\
\hline
0x1000 & 0,1 & IC\_FROMHOST\_PACKET\_RDY &
@@ -1336,21 +775,10 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
\multicolumn{6}{|c|}{TTC\_BUSY\_ACCEPTED\_G} \\
\hline
0x8020 & 0,1 & TTC\_BUSY\_ACCEPTED00 &
->>>>>>> master
56:0 & R & busy has been asserted by the given ELINK. Reset by writing to TTC\_BUSY\_CLEAR \\
\hline
\multicolumn{6}{|c|}{\ldots} \\
\hline
-<<<<<<< HEAD
-0x7190 & 0,1 & \multicolumn{2}{l|}{TTC\_BUSY\_ACCEPTED23} &
-56:0 & R & busy has been asserted by the given ELINK. Reset by writing to TTC\_BUSY\_CLEAR \\
-\hline
-0x71A0 & 0 & \multicolumn{5}{l|}{TTC\_EMU} \\
-\cline{3-7}
- & & & FULL & 2 & R & TTC Emulator memory full indication \\
- & & & SEL & 1 & W & Select TTC data source 1 TTC Emu | 0 TTC Decoder \\
- & & & ENA & 0 & W & Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence \\
-=======
0x8190 & 0,1 & TTC\_BUSY\_ACCEPTED23 &
56:0 & R & busy has been asserted by the given ELINK. Reset by writing to TTC\_BUSY\_CLEAR \\
\hline
@@ -1359,72 +787,14 @@ BAR2 stores registers for the control and monitor of HDL modules inside the FPGA
& & FULL & 2 & R & TTC Emulator memory full indication \\
& & SEL & 1 & W & Select TTC data source 1 TTC Emu | 0 TTC Decoder \\
& & ENA & 0 & W & Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence \\
->>>>>>> master
\hline
\multicolumn{6}{|c|}{TTC\_DELAY} \\
\hline
-<<<<<<< HEAD
-0x71B0 & 0 & \multicolumn{2}{l|}{TTC\_DELAY\_00} &
-=======
0x81B0 & 0 & TTC\_DELAY\_00 &
->>>>>>> master
3:0 & W & Controls the TTC Fanout delay values \\
\hline
\multicolumn{6}{|c|}{\ldots} \\
\hline
-<<<<<<< HEAD
-0x74A0 & 0 & \multicolumn{2}{l|}{TTC\_DELAY\_47} &
-3:0 & W & Controls the TTC Fanout delay values \\
-\hline
-0x74B0 & 0 & \multicolumn{5}{l|}{TTC\_BUSY\_TIMING\_CTRL} \\
-\cline{3-7}
- & & & PRESCALE & 51:32 & W & Prescales the 40MHz clock to create an internal slow clock \\
- & & & BUSY\_WIDTH & 31:16 & W & Minimum number of 40MHz clocks that the busy is asserted \\
- & & & LIMIT\_TIME & 15:0 & W & Number of prescaled clocks a given busy must be asserted before it is recognized \\
-\hline
-0x74C0 & 0 & \multicolumn{2}{l|}{TTC\_BUSY\_CLEAR} &
-any & T & clears the latching busy bits in TTC\_BUSY\_ACCEPTED \\
-\hline
-0x74D0 & 0 & \multicolumn{5}{l|}{TTC\_EMU\_CONTROL} \\
-\cline{3-7}
- & & & BROADCAST & 32:27 & W & Broadcast data \\
- & & & ECR & 26 & W & Event counter reset \\
- & & & BCR & 25 & W & Bunch counter reset \\
- & & & L1A & 24 & W & Level 1 Accept \\
-\hline
-0x74E0 & 0 & \multicolumn{2}{l|}{TTC\_EMU\_L1A\_PERIOD} &
-31:0 & W & L1A period in BC. 0 means manual L1A with TTC\_EMU\_CONTROL.L1A \\
-\hline
-0x74F0 & 0 & \multicolumn{2}{l|}{TTC\_EMU\_ECR\_PERIOD} &
-31:0 & W & ECR period in BC. 0 means manual ECR with TTC\_EMU\_CONTROL.ECR \\
-\hline
-0x7500 & 0 & \multicolumn{2}{l|}{TTC\_EMU\_BCR\_PERIOD} &
-31:0 & W & BCR period in BC. 0 means manual BCR with TTC\_EMU\_CONTROL.BCR \\
-\hline
-0x7510 & 0 & \multicolumn{2}{l|}{TTC\_EMU\_LONG\_CHANNEL\_DATA} &
-31:0 & W & Long channel data for the TTC emulator \\
-\hline
-0x7520 & 0 & \multicolumn{2}{l|}{TTC\_EMU\_RESET} &
-any & T & Any write to this register resets the TTC Emulator to the default state. \\
-\hline
-0x7530 & 0 & \multicolumn{2}{l|}{TTC\_L1ID\_MONITOR} &
-31:0 & R & Monitor L1ID and XL1ID. \\
-\hline
-0x7540 & 0 & \multicolumn{5}{l|}{TTC\_ECR\_MONITOR} \\
-\cline{3-7}
- & & & CLEAR & any & T & Counts the number of ECRs received from the TTC system, any write to this register clears the counter \\
- & & & VALUE & 31:0 & R & Counts the number of ECRs received from the TTC system, any write to this register clears the counter \\
-\hline
-0x7550 & 0 & \multicolumn{5}{l|}{TTC\_TTYPE\_MONITOR} \\
-\cline{3-7}
- & & & CLEAR & any & T & Counts the number of TType received from the TTC system, any write to this register clears the counter \\
- & & & VALUE & 31:0 & R & Counts the number of TType received from the TTC system, any write to this register clears the counter \\
-\hline
-0x7560 & 0 & \multicolumn{5}{l|}{TTC\_BCR\_PERIODICITY\_MONITOR} \\
-\cline{3-7}
- & & & CLEAR & any & T & Counts the number of times the BCR period does not match 3564, any write to this register clears the counter \\
- & & & VALUE & 31:0 & R & Counts the number of times the BCR period does not match 3564, any write to this register clears the counter \\
-=======
0x84A0 & 0 & TTC\_DELAY\_47 &
3:0 & W & Controls the TTC Fanout delay values \\
\hline
@@ -1477,7 +847,6 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
\cline{3-6}
& & CLEAR & any & T & Counts the number of times the BCR period does not match 3564, any write to this register clears the counter \\
& & VALUE & 31:0 & R & Counts the number of times the BCR period does not match 3564, any write to this register clears the counter \\
->>>>>>> master
\hline
0x8570 & 0 & \multicolumn{4}{c|}{\small TTC\_BCR\_COUNTER} \\
\cline{3-6}
@@ -1486,58 +855,6 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
\hline
\multicolumn{6}{|c|}{XOFF\_BUSY Controls And Monitors} \\
\hline
-<<<<<<< HEAD
-0x8000 & 0, 1 & \multicolumn{2}{l|}{XOFF\_FM\_CH\_FIFO\_THRESH\_LOW} &
-3:0 & W & Controls the low threshold of the channel fifo in FULL mode on which\newline an Xon will be asserted, bitfields control 4 MSB\newline \\
-\hline
-0x8010 & 0, 1 & \multicolumn{2}{l|}{XOFF\_FM\_CH\_FIFO\_THRESH\_HIGH} &
-3:0 & W & Controls the high threshold of the channel fifo in FULL mode on which\newline an Xoff will be asserted, bitfields control 4 MSB - name: XOFF\_FM\_LOW\_THRESH\_CROSSED\newline \\
-\hline
-0x8020 & 0, 1 & \multicolumn{2}{l|}{XOFF\_FM\_LOW\_THRESH\_CROSSED} &
-23:0 & R & FIFO filled beyond the low threshold, 1 bit per channel \\
-\hline
-0x8030 & 0, 1 & \multicolumn{5}{l|}{XOFF\_FM\_HIGH\_THRESH} \\
-\cline{3-7}
- & & & CLEAR\_LATCH & any & T & Writing this register will clear all CROSS\_LATCHED bits \\
- & & & CROSS\_LATCHED & 47:24 & R & FIFO filled beyond the high threshold, 1 latch bit per channel \\
- & & & CROSSED & 23:0 & R & FIFO filled beyond the high threshold, 1 bit per channel \\
-\hline
-0x8040 & 0, 1 & \multicolumn{2}{l|}{XOFF\_FM\_SOFT\_XOFF} &
-23:0 & W & Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON \\
-\hline
-0x8050 & 0, 1 & \multicolumn{2}{l|}{XOFF\_ENABLE} &
-23:0 & W & Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel \\
-\hline
-0x8060 & 0, 1 & \multicolumn{5}{l|}{DMA\_BUSY\_STATUS} \\
-\cline{3-7}
- & & & CLEAR\_LATCH & any & T & Any write to this register clears TOHOST\_BUSY\_LATCHED \\
- & & & ENABLE & 4 & W & Enable the DMA buffer on the server as a source of busy \\
- & & & TOHOST\_BUSY\_LATCHED & 3 & R & A tohost descriptor has passed BUSY\_THRESHOLD\_ASSERT in the past, busy flag was set \\
- & & & TOHOST\_BUSY & 0 & R & A tohost descriptor passed BUSY\_THRESHOLD\_ASSERT, busy flag set \\
-\hline
-0x8070 & 0, 1 & \multicolumn{5}{l|}{FM\_BUSY\_CHANNEL\_STATUS} \\
-\cline{3-7}
- & & & CLEAR\_LATCH & any & T & Any write to this register will clear the BUSY\_LATCHED bits \\
- & & & BUSY\_LATCHED & 47:24 & R & one Indicates that the given FULL mode channel has received BUSY-ON \\
- & & & BUSY & 23:0 & R & one Indicates that the given FULL mode channel is currently in BUSY state \\
-\hline
-0x8080 & 0, 1 & \multicolumn{5}{l|}{BUSY\_MAIN\_OUTPUT\_FIFO\_THRESH} \\
-\cline{3-7}
- & & & BUSY\_ENABLE & 24 & W & Enable busy generation if thresholds are crossed \\
- & & & LOW & 23:12 & W & Low, Negate threshold of busy generation from main output fifo \\
- & & & HIGH & 11:0 & W & High, Assert threshold of busy generation from main output fifo \\
-\hline
-0x8090 & 0, 1 & \multicolumn{5}{l|}{BUSY\_MAIN\_OUTPUT\_FIFO\_STATUS} \\
-\cline{3-7}
- & & & CLEAR\_LATCHED & any & T & Any write to this register will clear the \\
- & & & HIGH\_THRESH\_CROSSED\_LATCHED & 2 & R & Main output fifo has been full beyond HIGH THRESHOLD, write to clear \\
- & & & HIGH\_THRESH\_CROSSED & 1 & R & Main output fifo is full beyond HIGH THRESHOLD \\
- & & & LOW\_THRESH\_CROSSED & 0 & R & Main output fifo is full beyond LOW THRESHOLD \\
-\hline
-\multicolumn{7}{|c|}{ELINK\_BUSY\_ENABLE} \\
-\hline
-0x80A0 & 0 & \multicolumn{2}{l|}{ELINK\_BUSY\_ENABLE00} &
-=======
0x8800 & 0, 1 & XOFF\_FM\_CH\_FIFO\_THRESH\_LOW &
3:0 & W & Controls the low threshold of the channel fifo in FULL mode on which\newline an Xon will be asserted, bitfields control 4 MSB\newline \\
\hline
@@ -1588,29 +905,15 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
\multicolumn{6}{|c|}{ELINK\_BUSY\_ENABLE} \\
\hline
0x88A0 & 0 & ELINK\_BUSY\_ENABLE00 &
->>>>>>> master
56:0 & W & Per elink (and FULL mode link) enable of the busy signal towards the LEMO output \\
\hline
\multicolumn{6}{|c|}{\ldots} \\
\hline
-<<<<<<< HEAD
-0x8210 & 0 & \multicolumn{2}{l|}{ELINK\_BUSY\_ENABLE23} &
-=======
0x8A10 & 0 & ELINK\_BUSY\_ENABLE23 &
->>>>>>> master
56:0 & W & Per elink (and FULL mode link) enable of the busy signal towards the LEMO output \\
\hline
\multicolumn{6}{|c|}{XOFF\_STATISTICS} \\
\hline
-<<<<<<< HEAD
-0x8220 & 0,1 & \multicolumn{2}{l|}{XOFF\_PEAK\_DURATION00} &
-63:0 & R & Maximum occurred duration of XOFF on the given channel in 25ns bins since reset \\
-\hline
-0x8230 & 0,1 & \multicolumn{2}{l|}{XOFF\_TOTAL\_DURATION00} &
-63:0 & R & Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset \\
-\hline
-0x8240 & 0,1 & \multicolumn{2}{l|}{XOFF\_COUNT00} &
-=======
0x8A20 & 0,1 & XOFF\_PEAK\_DURATION00 &
63:0 & R & Maximum occurred duration of XOFF on the given channel in 25ns bins since reset \\
\hline
@@ -1618,20 +921,10 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
63:0 & R & Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset \\
\hline
0x8A40 & 0,1 & XOFF\_COUNT00 &
->>>>>>> master
63:0 & R & Total number of XOFF events per channel that occurred since a reset. \\
\hline
\multicolumn{6}{|c|}{\ldots} \\
\hline
-<<<<<<< HEAD
-0x8670 & 0,1 & \multicolumn{2}{l|}{XOFF\_PEAK\_DURATION23} &
-63:0 & R & Maximum occurred duration of XOFF on the given channel in 25ns bins since reset \\
-\hline
-0x8680 & 0,1 & \multicolumn{2}{l|}{XOFF\_TOTAL\_DURATION23} &
-63:0 & R & Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset \\
-\hline
-0x8690 & 0,1 & \multicolumn{2}{l|}{XOFF\_COUNT23} &
-=======
0x8E70 & 0,1 & XOFF\_PEAK\_DURATION23 &
63:0 & R & Maximum occurred duration of XOFF on the given channel in 25ns bins since reset \\
\hline
@@ -1639,7 +932,6 @@ any & T & Any write to this register resets the TTC Emulator to the default stat
63:0 & R & Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset \\
\hline
0x8E90 & 0,1 & XOFF\_COUNT23 &
->>>>>>> master
63:0 & R & Total number of XOFF events per channel that occurred since a reset. \\
\hline
\multicolumn{6}{|c|}{House Keeping Controls And Monitors} \\
@@ -2429,4 +1721,4 @@ any & T & (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 s
\caption{FELIX register map BAR2}\label{tab:dma_register_map_bar2}
\end{tabularx}
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+\newpage
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