diff --git a/sources/TTCdataEmulator/TTC_Emulator.vhd b/sources/TTCdataEmulator/TTC_Emulator.vhd
index 02d27dd5cf09661d917d16425e10074d55c7987d..bd88cd86f9a06772bb588bbea700651cc83c8c0e 100644
--- a/sources/TTCdataEmulator/TTC_Emulator.vhd
+++ b/sources/TTCdataEmulator/TTC_Emulator.vhd
@@ -74,7 +74,7 @@ architecture Behavioral of TTC_Emulator is
     signal      input_long_Bch      : std_logic_vector(31 downto 0);    -- default ...
     signal      input_broadcast     : std_logic_vector(5 downto 0);     
     signal      set_default         : std_logic;
-    signal      cycle_mode          : std_logic;
+   -- signal      cycle_mode          : std_logic;
 
     signal      single_l1a_long     : std_logic := '0';
     signal      single_l1a          : std_logic := '0';
@@ -202,22 +202,22 @@ begin
 ----- Cycle or non-cycle mode ------------------------------------------
 ------------------------------------------------------------------------
 
-    process(Clock)
-    begin
-        if rising_edge(Clock) then
-            if Reset = '1' or user_reset = '1' then
-                cycle_mode <= '0';
-            elsif en = '1' then
+--    process(Clock)
+--    begin
+--        if rising_edge(Clock) then
+--            if Reset = '1' or user_reset = '1' then
+--                cycle_mode <= '0';
+--            elsif en = '1' then
                 -- this need to be clarified.. would this be intuitive for the user?..
                 -- it could be disentagled in some ways...?
-                if input_l1a_period = x"0000_0000" and input_ecr_period = x"0000_0000" then
-                    cycle_mode <= '0';
-                else
-                    cycle_mode <= '1';
-                end if;
-            end if;
-        end if;
-    end process;
+--                if input_l1a_period = x"0000_0000" or input_ecr_period = x"0000_0000" or input_bcr_period = x"0000_0000" then --and
+--                    cycle_mode <= '0';
+--                else
+--                    cycle_mode <= '1';
+--                end if;
+--            end if;
+--        end if;
+--    end process;
 
 
 ------------------------------------------------------------------------
@@ -870,7 +870,7 @@ begin
 
     ecr_delay: entity work.signal_delay
     generic map (
-        width     => 4     -- number of clock cycles it shell be delayed- number of clock cycles it shell be delayed
+        width     => 4     -- number counter stages used to generate delay given in count_in 
     )
     port map (
         clk         => Clock,     -- clock
@@ -913,8 +913,8 @@ begin
 
     TTCout(0) <= l1_accept;
     TTCout(1) <= Serial_Bchannel;
-    TTCout(2) <= bcr or single_bcr;
-    TTCout(3) <= ecr or single_ecr;
+    TTCout(2) <= single_bcr when (input_bcr_period = X"0000_0000") else bcr or single_bcr;-- 
+    TTCout(3) <= single_ecr when (input_ecr_period = X"0000_0000") else ecr or single_ecr; --
     TTCout(4) <= ocr;      -- AS: use this output instead of broad(0); d(0)
     TTCout(5) <= broad(1); -- d(1)
     TTCout(6) <= broad(2); -- d(2)