From b151feb80a3fc048b7efafa482649dcb9dc13518 Mon Sep 17 00:00:00 2001
From: Frans Schreuder <f.schreuder@nikhef.nl>
Date: Wed, 2 Mar 2022 15:44:42 +0100
Subject: [PATCH] Pushed firmware version to rm-4.11
---
sources/templates/build-diff.sh | 4 +-
sources/templates/build-doc.sh | 2 +-
sources/templates/build-strips.sh | 4 +-
sources/templates/build.sh | 4 +-
sources/templates/dma_control.vhd | 6 +-
sources/templates/pcie_package.vhd | 6 +-
sources/templates/register_map_sync.vhd | 4 +-
sources/templates/registers-4.10.yaml | 0
sources/templates/registers-4.11.yaml | 3534 +++++++++++++++++
sources/templates/strips_config_package.vhd | 4 +-
.../strips_phase1_long_stave_mapping.vhd | 4 +-
.../strips_phase1_unknown_mapping.vhd | 4 +-
sources/templates/wupper.vhd | 4 +-
13 files changed, 3557 insertions(+), 23 deletions(-)
mode change 100755 => 100644 sources/templates/registers-4.10.yaml
create mode 100644 sources/templates/registers-4.11.yaml
diff --git a/sources/templates/build-diff.sh b/sources/templates/build-diff.sh
index 5a3da9e3f..66e7977c9 100755
--- a/sources/templates/build-diff.sh
+++ b/sources/templates/build-diff.sh
@@ -22,8 +22,8 @@
# Script to rebuild the derived files from templates
#
prev_version=4.10
-current_version=4.10
-next_version=4.10
+current_version=4.11
+next_version=4.11
# firmware directory:
firmware_dir=../..
diff --git a/sources/templates/build-doc.sh b/sources/templates/build-doc.sh
index 3f991af98..62228af1e 100755
--- a/sources/templates/build-doc.sh
+++ b/sources/templates/build-doc.sh
@@ -23,7 +23,7 @@
# build the documentation from the registermap.tex file
wuppercodegen=../../../software/wuppercodegen/wuppercodegen/cli.py
-registers=registers-4.10.yaml
+registers=registers-4.11.yaml
$wuppercodegen --version
$wuppercodegen $registers registermap.tex.template registermap.tex
latex registers.tex
diff --git a/sources/templates/build-strips.sh b/sources/templates/build-strips.sh
index 8503d8f98..76341922e 100755
--- a/sources/templates/build-strips.sh
+++ b/sources/templates/build-strips.sh
@@ -21,8 +21,8 @@
# Script to rebuild the derived files from templates
#
-prev_version=4.9
-current_version=4.10
+prev_version=4.10
+current_version=4.11
#
# firmware directory:
diff --git a/sources/templates/build.sh b/sources/templates/build.sh
index d5faea8c4..dc2c6ff9d 100755
--- a/sources/templates/build.sh
+++ b/sources/templates/build.sh
@@ -29,8 +29,8 @@
# Script to rebuild the derived files from templates
#
-prev_version=4.9
-current_version=4.10
+prev_version=4.10
+current_version=4.11
#next_version=4.9
diff --git a/sources/templates/dma_control.vhd b/sources/templates/dma_control.vhd
index d60fbf6bb..25e0cba05 100644
--- a/sources/templates/dma_control.vhd
+++ b/sources/templates/dma_control.vhd
@@ -40,11 +40,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../sources/templates/dma_control.vhd.template'
--- and register map ../../sources/templates/registers-4.10.yaml, version 4.10
+-- and register map ../../sources/templates/registers-4.11.yaml, version 4.11
-- by the script 'wuppercodegen', version: 0.8.4,
-- using the following commandline:
--
--- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.10.yaml ../../sources/templates/dma_control.vhd.template ../../sources/templates/dma_control.vhd
+-- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.11.yaml ../../sources/templates/dma_control.vhd.template ../../sources/templates/dma_control.vhd
--
-- Please do NOT edit this file, but edit the source file at '../../sources/templates/dma_control.vhd.template'
--
@@ -19096,7 +19096,7 @@ end process;
-- GenericBoardInformation
- when REG_REG_MAP_VERSION => register_read_data_25_s(15 downto 0) <= std_logic_vector(to_unsigned(1034,16)); -- Register Map Version, 4.10 formatted as 0x040A
+ when REG_REG_MAP_VERSION => register_read_data_25_s(15 downto 0) <= std_logic_vector(to_unsigned(1035,16)); -- Register Map Version, 4.11 formatted as 0x040B
when REG_BOARD_ID_TIMESTAMP => register_read_data_25_s(39 downto 0) <= BUILD_DATETIME; -- Board ID Date / Time in BCD format YYMMDDhhmm
when REG_GIT_COMMIT_TIME => register_read_data_25_s(39 downto 0) <= COMMIT_DATETIME; -- Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
when REG_GIT_TAG => register_read_data_25_s(63 downto 0) <= GIT_TAG(63 downto 0); -- String containing the current GIT TAG
diff --git a/sources/templates/pcie_package.vhd b/sources/templates/pcie_package.vhd
index 416f29fe2..005cfbfb6 100644
--- a/sources/templates/pcie_package.vhd
+++ b/sources/templates/pcie_package.vhd
@@ -39,11 +39,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../sources/templates/pcie_package.vhd.template'
--- and register map ../../sources/templates/registers-4.10.yaml, version 4.10
+-- and register map ../../sources/templates/registers-4.11.yaml, version 4.11
-- by the script 'wuppercodegen', version: 0.8.4,
-- using the following commandline:
--
--- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.10.yaml ../../sources/templates/pcie_package.vhd.template ../../sources/templates/pcie_package.vhd
+-- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.11.yaml ../../sources/templates/pcie_package.vhd.template ../../sources/templates/pcie_package.vhd
--
-- Please do NOT edit this file, but edit the source file at '../../sources/templates/pcie_package.vhd.template'
--
@@ -7644,7 +7644,7 @@ package pcie_package is
-- GenericBoardInformation
type register_map_gen_board_info_type is record
- REG_MAP_VERSION : std_logic_vector(15 downto 0); -- Register Map Version, 4.10 formatted as 0x040A
+ REG_MAP_VERSION : std_logic_vector(15 downto 0); -- Register Map Version, 4.11 formatted as 0x040B
BOARD_ID_TIMESTAMP : std_logic_vector(39 downto 0); -- Board ID Date / Time in BCD format YYMMDDhhmm
GIT_COMMIT_TIME : std_logic_vector(39 downto 0); -- Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
GIT_TAG : std_logic_vector(63 downto 0); -- String containing the current GIT TAG
diff --git a/sources/templates/register_map_sync.vhd b/sources/templates/register_map_sync.vhd
index 589928c54..6247a8060 100644
--- a/sources/templates/register_map_sync.vhd
+++ b/sources/templates/register_map_sync.vhd
@@ -23,11 +23,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../sources/templates/register_map_sync.vhd.template'
--- and register map ../../sources/templates/registers-4.10.yaml, version 4.10
+-- and register map ../../sources/templates/registers-4.11.yaml, version 4.11
-- by the script 'wuppercodegen', version: 0.8.4,
-- using the following commandline:
--
--- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.10.yaml ../../sources/templates/register_map_sync.vhd.template ../../sources/templates/register_map_sync.vhd
+-- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.11.yaml ../../sources/templates/register_map_sync.vhd.template ../../sources/templates/register_map_sync.vhd
--
-- Please do NOT edit this file, but edit the source file at '../../sources/templates/register_map_sync.vhd.template'
--
diff --git a/sources/templates/registers-4.10.yaml b/sources/templates/registers-4.10.yaml
old mode 100755
new mode 100644
diff --git a/sources/templates/registers-4.11.yaml b/sources/templates/registers-4.11.yaml
new file mode 100644
index 000000000..264907561
--- /dev/null
+++ b/sources/templates/registers-4.11.yaml
@@ -0,0 +1,3534 @@
+Registers:
+ version: '4.11'
+ warning: |
+ ***************************************************************************
+ ***************************************************************************
+ ***************************************************************************
+ ***************************************************************************
+ ***************************************************************************
+ DO NOT EDIT THIS FILE
+
+ This file was generated from template '{{ metadata.template }}'
+ and register map {{ metadata.config }}, version {{ tree.version }}
+ by the script '{{ metadata.name }}', version: {{ metadata.version }},
+ using the following commandline:
+
+ {{ metadata.cmdline }}
+
+ Please do NOT edit this file, but edit the source file at '{{ metadata.template }}'
+
+ ***************************************************************************
+ ***************************************************************************
+ ***************************************************************************
+ ***************************************************************************
+ ***************************************************************************
+
+ type: R
+ step: 0x010
+ default: 0
+ endpoints: 0,1
+ entries:
+ - ref: Bar0
+ offset: 0x0000
+ - ref: Bar1
+ offset: 0x0000
+ - ref: Bar2
+ offset: 0x0000
+ - ref: Monitorsections
+ offset: 0x0000
+
+Monitorsections:
+ endpoints: 0,1
+ entries:
+ - name: GenericBoardInformation
+ record_name: register_map_gen_board_info
+ bitfield:
+ - range: 0..0
+ type: R
+ - name: CentralRouterControlsAndMonitors
+ record_name: register_map_cr_monitor
+ bitfield:
+ - range: 0..0
+ type: R
+ - name: GBTEmulatorControlsAndMonitors
+ record_name: register_map_gbtemu_monitor
+ bitfield:
+ - range: 0..0
+ type: R
+ - name: GBTWrapperMonitors
+ record_name: register_map_gbt_monitor
+ bitfield:
+ - range: 0..0
+ type: R
+ - name: TTCBUSYControlsAndMonitors
+ record_name: register_map_ttc_monitor
+ bitfield:
+ - range: 0..0
+ type: R
+ - name: XOFF_BUSYControlsAndMonitors
+ record_name: register_map_xoff_monitor
+ bitfield:
+ - range: 0..0
+ type: R
+ - name: HouseKeepingControlsAndMonitors
+ record_name: register_map_hk_monitor
+ bitfield:
+ - range: 0..0
+ type: R
+ - name: Generators
+ record_name: register_map_generators
+ bitfield:
+ - range: 0..0
+ type: R
+ - name: Wishbone
+ record_name: wishbone_monitor
+ bitfield:
+ - range: 0..0
+ type: R
+ - name: MRODmonitors
+ record_name: regmap_mrod_monitor
+ bitfield:
+ - range: 0..0
+ type: R
+
+#Bar0 contains the registers dedicated to Wupper. Please only edit registers in Bar2
+#Registers in this group will not be generated with WupperCodeGen
+Bar0:
+ endpoints: 0,1
+ entries:
+ - ref: DMA_DESC
+ - ref: DMA_DESC_STATUS
+ offset: 0x0200
+ - name: BAR0_VALUE
+ offset: 0x0300
+ bitfield:
+ - range: 31..0
+ desc: Copy of BAR0 offset reg.
+ - name: BAR1_VALUE
+ bitfield:
+ - range: 31..0
+ desc: Copy of BAR1 offset reg.
+ - name: BAR2_VALUE
+ bitfield:
+ - range: 31..0
+ desc: Copy of BAR2 offset reg.
+ - name: DMA_DESC_ENABLE
+ offset: 0x0400
+ bitfield:
+ - range: 7..0
+ type: W
+ desc: Enable descriptors 7:0. One bit per descriptor. Cleared when Descriptor is handled.
+ #- name: DMA_FIFO_FLUSH
+ # type: T
+ # bitfield:
+ # - range: any
+ # desc: Flush (reset). Any write clears the DMA Main output FIFO
+ - name: DMA_RESET
+ offset: 0x420
+ type: T
+ bitfield:
+ - range: any
+ desc: Reset Wupper Core (DMA Controller FSMs)
+ - name: SOFT_RESET
+ type: T
+ bitfield:
+ - range: any
+ desc: Global Software Reset. Any write resets applications, e.g. the Central Router.
+ - name: REGISTER_RESET
+ type: T
+ bitfield:
+ - range: any
+ desc: Resets the register map to default values. Any write triggers this reset.
+ - name: FROMHOST_FULL_THRESH
+ type: W
+ bitfield:
+ - range: 22..16
+ name: THRESHOLD_ASSERT
+ desc: Assert value of the FromHost programmable full flag
+ - range: 6..0
+ name: THRESHOLD_NEGATE
+ desc: Negate value of the FromHost programmalbe full flag
+ - name: TOHOST_FULL_THRESH
+ type: W
+ bitfield:
+ - range: 27..16
+ name: THRESHOLD_ASSERT
+ desc: Assert value of the ToHost programmable full flag
+ - range: 11..0
+ name: THRESHOLD_NEGATE
+ desc: Negate value of the ToHost programmalbe full flag
+
+ - name: BUSY_THRESHOLD_ASSERT
+ type: W
+ desc: Tohost or Fromhost busy will be asserted in circular DMA mode when the server PC buffer gets full (space below ASSERT threshold)..
+ default: 0x6400000
+ bitfield:
+ - range: 63..0
+
+ - name: BUSY_THRESHOLD_NEGATE
+ type: W
+ desc: Tohost or Fromhost busy will be negated in circular DMA mode when the server PC buffer gets less full (space above NEGATE threshold).
+ default: 0x6E00000
+ bitfield:
+ - range: 63..0
+
+ - name: BUSY_STATUS
+ type: R
+ bitfield:
+ - range: 0
+ name: TOHOST_BUSY
+ desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
+
+ - name: PC_PTR_GAP
+ type: W
+ desc: This is the minimum value that the pc_pointer in a descriptor has to decrease in order to flip the evencycle_pc bit
+ default: 0x1000000
+ bitfield:
+ - range: 63..0
+
+DMA_DESC:
+ number: 8
+ type: W
+ entries:
+ - name: DMA_DESC_{index}
+ bitfield:
+ - range: 127..64
+ name: END_ADDRESS
+ desc: End Address
+ - range: 63..0
+ name: START_ADDRESS
+ desc: Start Address
+ - name: DMA_DESC_{index}a
+ bitfield:
+ - range: 127..64
+ name: SW_POINTER
+ desc: Pointer controlled by the software, indicating read or write status for circular DMA
+ - range: 12
+ name: WRAP_AROUND
+ desc: Wrap around
+ - range: 11
+ name: FROMHOST
+ desc: "1: fromHost/ 0: toHost"
+ - range: 10..0
+ name: NUM_WORDS
+ desc: Number of 32 bit words
+
+DMA_DESC_STATUS:
+ number: 8
+ entries:
+ - name: DMA_DESC_STATUS_{index}
+ bitfield:
+ - range: 66
+ name: EVEN_PC
+ desc: Even address cycle PC
+ - range: 65
+ name: EVEN_DMA
+ desc: Even address cycle DMA
+ - range: 64
+ name: DESC_DONE
+ desc: Descriptor Done
+ - range: 63..0
+ name: FW_POINTER
+ desc: Pointer controlled by the firmwarre, indicating where the DMA is busy reading or writing
+
+
+#Bar1 contains the registers dedicated to the Wupper interrupg controller.
+#Please only edit registers in Bar2.
+#Registers in this group will not be generated with WupperCodeGen
+Bar1:
+ endpoints: 0,1
+ type: W
+ entries:
+ - ref: INT_VEC
+ - name: INT_TAB_ENABLE
+ offset: 0x100
+ bitfield:
+ - range: 7..0
+ desc: |
+ Interrupt Table enable
+ Selectively enable Interrupts
+
+INT_VEC:
+ number: 16
+ type: W
+ entries:
+ - name: INT_VEC_{index}
+ bitfield:
+ - range: 127..96
+ name: INT_CTRL
+ desc: Interrupt Control
+ - range: 95..64
+ name: INT_DATA
+ desc: Interrupt Data
+ - range: 64..0
+ name: INT_ADDRESS
+ desc: Interrupt Address
+
+#Bar 2 contains application specific registers, used in the example application.
+#Registers in this group (and it's referenced subroups) will be generated with
+#WupperCodeGen for wupper Firmware, Software and Documentation
+Bar2:
+ entries:
+ - ref: GenericBoardInformation
+ offset: 0x0000
+ - ref: CentralRouterControlsAndMonitors
+ offset: 0x1000
+ - ref: GBTEmulatorControlsAndMonitors
+ offset: 0x5000
+ - ref: GBTWrapperControls
+ offset: 0x6000
+ - ref: GBTWrapperMonitors
+ offset: 0x7000
+ - ref: TTCBUSYControlsAndMonitors
+ offset: 0x8000
+ - ref: XOFF_BUSYControlsAndMonitors
+ offset: 0x8800
+ - ref: HouseKeepingControlsAndMonitors
+ offset: 0x9000
+ - ref: Generators
+ offset: 0xA000
+ - ref: Wishbone
+ offset: 0xC000
+ - ref: ITK_STRIPS_CTRL # ITk strips global controls
+ offset: 0xD000
+ - ref: MRODregisters
+ offset: 0xF000
+ - ref: MRODmonitors
+ offset: 0xF800
+
+GenericBoardInformation:
+ group: GEN
+ desc: Generic Board Information
+ endpoints: 0,1
+ entries:
+ - name: REG_MAP_VERSION
+ bitfield:
+ - range: 15..0
+ value: std_logic_vector(to_unsigned({{ tree.version|version }},16))
+ desc: Register Map Version, {{ tree.version }} formatted as {{ tree.version|version|xhex }}
+
+ - name: BOARD_ID_TIMESTAMP
+ bitfield:
+ - range: 39..0
+ value: BUILD_DATETIME
+ desc: Board ID Date / Time in BCD format YYMMDDhhmm
+
+ #- name: BOARD_ID_SVN
+ # bitfield:
+ # - range: 15..0
+ # value: std_logic_vector(to_unsigned(SVN_VERSION,16))
+ # desc: OBSOLETE Board ID SVN Revision
+
+ - name: GIT_COMMIT_TIME
+ offset: 0x30
+ bitfield:
+ - range: 39..0
+ value: COMMIT_DATETIME
+ desc: Board ID GIT Commit time of current revision, Date / Time in BCD format YYMMDDhhmm
+
+ - name: GIT_TAG
+ bitfield:
+ - range: 63..0
+ value: GIT_TAG(63 downto 0)
+ desc: String containing the current GIT TAG
+
+ - name: GIT_COMMIT_NUMBER
+ bitfield:
+ - range: 31..0
+ value: std_logic_vector(to_unsigned(GIT_COMMIT_NUMBER,32))
+ desc: Number of GIT commits after current GIT_TAG
+
+ - name: GIT_HASH
+ bitfield:
+ - range: 31..0
+ value: GIT_HASH(159 downto 128)
+ desc: Short GIT hash (32 bit)
+
+ - name: STATUS_LEDS
+ type: W
+ bitfield:
+ - range: 7..0
+ default: 0xAB
+ desc: Board GPIO Leds
+
+ - name: GENERIC_CONSTANTS
+ bitfield:
+ - range: 15..8
+ name: INTERRUPTS
+ value: std_logic_vector(to_unsigned(NUMBER_OF_INTERRUPTS,8))
+ desc: Number of Interrupts
+ - range: 7..0
+ name: DESCRIPTORS
+ value: std_logic_vector(to_unsigned(NUMBER_OF_DESCRIPTORS,8))
+ desc: Number of Descriptors
+
+ - name: NUM_OF_CHANNELS
+ bitfield:
+ - range: 7..0
+ desc: Number of GBT or FULL mode Channels
+
+ - name: CARD_TYPE
+ bitfield:
+ - range: 63..0
+ value: std_logic_vector(to_unsigned(CARD_TYPE,64))
+ desc: |
+ Card Type:
+ - 709 (0x2c5): FLX709, VC709
+ - 710 (0x2c6): FLX710, HTG710
+ - 711 (0x2c7): FLX711, BNL711
+ - 712 (0x2c8): FLX712, BNL712
+ - 128 (0x080): FLX128, VCU128
+
+ #- name: GBT_MAPPING
+ # bitfield:
+ # - range: 7..0
+ # desc: |
+ # OBSOLETE CXP-to-GBT mapping:
+ # 0: NORMAL CXP1 1-12 CXP2 13-24
+ # 1: ALTERNATE CXP1 1-4,9-12,17-20
+
+ - name: GENERATE_GBT
+ offset: 0xc0
+ bitfield:
+ - range: 0
+ desc: 1 when the GBT Wrapper is included in the design
+
+ - name: OPTO_TRX_NUM
+ bitfield:
+ - range: 7..0
+ desc: Number of optical transceivers in the design
+
+ - name: TTC_EMU_CONST_GENERATE_TTC_EMU
+ type: R
+ bitfield:
+ - range: 1
+ type: R
+ desc: 1 when TTC emulator is generated
+
+ #- range: 0
+ # type: R
+ # name: TTC_TEST_MODE
+ # desc: OBSOLETE 1 when TTC Test mode is anabled
+
+ #- name: CR_INTERNAL_LOOPBACK_MODE
+ # type: R
+ # bitfield:
+ # - range: 0
+ # desc: OBSOLETE 1 when Central Router internal loopback mode is enabled
+
+ - offset: 0x100
+ ref: INCLUDE_EGROUPS
+
+
+ - name: WIDE_MODE
+ type: R
+ bitfield:
+ - range: 0
+ desc: GBT is configured in Wide mode
+
+ #- name: DEBUG_MODE
+ # type: R
+ # bitfield:
+ # - range: 0
+ # desc: |
+ # OBSOLETE
+ # 0: SMA X3 is constant 0, SMA X4 is connected to clk40 (output).
+ # 1: Debug port module (SMA X3 and SMA X4) can be controlled using DEBUG_PORT_GBT and DEBUG_PORT_CLK
+
+ - name: FIRMWARE_MODE
+ type: R
+ offset: 0x190
+ bitfield:
+ - range: 3..0
+ desc: |
+ 0: GBT mode
+ 1: FULL mode
+ 2: LTDB mode (GBT mode with only IC and TTC links)
+ 3: FEI4 mode
+ 4: ITK Pixel
+ 5: ITK Strip
+ 6: FELIG
+ 7: FULL mode emulator
+ 8: FELIX_MROD mode
+
+ - name: GTREFCLK_SOURCE
+ type: R
+ bitfield:
+ - range: 1..0
+ desc: |
+ 0: Transceiver reference Clock source from Si5345
+ 1: Transceiver reference Clock source from Si5324
+ 2: Transceiver reference Clock from internal BUFG (GREFCLK)
+
+ - name: CR_GENERICS
+ type: R
+ bitfield:
+ - range: 2
+ name: XOFF_INCLUDED
+ desc: Xoff bits (usually full mode) can be generated by the FromHost Central Router
+ - range: 1
+ name: DIRECT_MODE_INCLUDED
+ desc: Indicates that the Direct mode functionality was built in the Central Router
+ - range: 0
+ name: FROM_HOST_INCLUDED
+ desc: Indicates that the From Host path of the Central router was included in the design
+
+ - name: BLOCKSIZE
+ type: R
+ desc: Number of bytes in a block
+ bitfield:
+ - range: 15..0
+
+ - name: PCIE_ENDPOINT
+ type: R
+ desc: Indicator of the PCIe endpoint on BNL71x cards with two endpoints. 0 or 1
+ bitfield:
+ - range: 0
+ value: std_logic_vector(to_unsigned(PCIE_ENDPOINT, 1))
+
+ - name: CHUNK_TRAILER_32B
+ type: R
+ desc: Indicator that the chunk trailer is in the new 32-bit format
+ bitfield:
+ - range: 0
+
+ - name: NUMBER_OF_PCIE_ENDPOINTS
+ type: R
+ desc: Number of PCIe endpoints on the card. The BNL71x cards have 2 endpoints
+ bitfield:
+ - range: 1..0
+
+INCLUDE_EGROUPS:
+ number: 7
+ entries:
+ - format_name: INCLUDE_EGROUP_{index}
+ name: INCLUDE_EGROUP
+ type_name: INCLUDE_EGROUP
+ type: R
+ bitfield:
+ - range: 8
+ name: FROMHOST_02
+ desc: FromHost EPROC02 is included in this EGROUP
+ - range: 7
+ name: FROMHOST_04
+ desc: FromHost EPROC04 is included in this EGROUP
+ - range: 6
+ name: FROMHOST_08
+ desc: FromHost EPROC8 is included in this EGROUP
+ - range: 5
+ name: FROMHOST_HDLC
+ desc: FromHost HDLC is included in this EGROUP
+ - range: 4
+ name: TOHOST_02
+ desc: ToHost EPROC02 is included in this EGROUP
+ - range: 3
+ name: TOHOST_04
+ desc: ToHost EPROC04 is included in this EGROUP
+ - range: 2
+ name: TOHOST_08
+ desc: ToHost EPROC08 is included in this EGROUP
+ - range: 1
+ name: TOHOST_16
+ desc: ToHost EPROC16 is included in this EGROUP
+ - range: 0
+ name: TOHOST_HDLC
+ desc: ToHost HDLC is included in this EGROUP
+
+
+CentralRouterControlsAndMonitors:
+ group: CRC
+ desc: Central Router Controls and Monitors
+ endpoints: 0,1
+ entries:
+ - name: IC_FROMHOST_PACKET_RDY
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: Rising edge indicates the complete packet can be read
+
+ - name: TIMEOUT_CTRL
+ type: W
+ descr: Controls the timout mechanism in the ToHost central router.
+ bitfield:
+ - range: 32
+ name: ENABLE
+ default: 1
+ desc: 1 enables the timout trailer generation for ToHost mode
+ - range: 31..0
+ name: TIMEOUT
+ default: 0xFFFFFFFF
+ desc: Number of 40 MHz clock cycles after which a timeout occurs.
+
+ - ref: CR_GBT_CTRL
+ desc: See Central Router Doc
+ offset: 0x0100
+
+ #- ref: IC_FIFOS
+ # desc: See Central Router Doc
+ # offset: 0x1400
+
+ - ref: MINI_EGROUP_CTRL
+ desc: Controls EC and TTC channels of Mini Egroups
+ offset: 0x1700
+
+ #- name: CR_FALLBACK_OPTIONS
+ # desc: OBSOLETE Julias personal register with Hello Kitty options
+ # type: W
+ # bitfield:
+ # - range: 63..0
+
+ - name: CR_TTC_TOHOST
+ desc: Enables the ToHost Mini Egroup in TTC mode
+ offset: 0x1a10
+ type: W
+ bitfield:
+ - range: 63
+ name: EMU_FAKE_READY_ENABLE
+ default: 0
+ - range: 60..48
+ name: EMU_FAKE_READY_VALUE
+ default: 0x1000
+ - range: 15..4
+ name: TIMEOUT_VALUE
+ default: 0xFFF
+ - range: 2
+ name: EMU_ENABLE
+ default: 0
+ - range: 1
+ name: TIMEOUT_ENABLE
+ default: 1
+ - range: 0
+ name: ENABLE
+ default: 1
+
+ - name: CR_REVERSE_10B
+ desc: Reverse 10-bit word of elink data
+ type: W
+ bitfield:
+ - range: 1
+ name: FROMHOST
+ default: 1
+ desc: |
+ 1: Serialize 10-bit word in FromHost EPROCS MSB first
+ 0: Serialize 10-bit word in FromHost EPROCS LSB first
+ - range: 0
+ name: TOHOST
+ default: 1
+ desc: |
+ 1: Receive 10-bit word in ToHost EPROCS, MSB first
+ 0: Receive 10-bit word in ToHost EPROCS, LSB first
+
+ - name: CR_LTDB_TTC_DELAY
+ desc: Controls TTC BCR delay in LTDB mode firmware
+ type: W
+ bitfield:
+ - range: 7
+ name: EGROUP4_EPATH6
+ default: 1
+ desc: |
+ Egroup 4, Epath 6
+ 1: Half a clock delay
+ 0: no delay
+ - range: 6
+ name: EGROUP4_EPATH5
+ default: 1
+ desc: |
+ Egroup 4, Epath 5
+ 1: Half a clock delay
+ 0: no delay
+ - range: 5
+ name: EGROUP4_EPATH4
+ default: 1
+ desc: |
+ Egroup 4, Epath 4
+ 1: Half a clock delay
+ 0: no delay
+ - range: 4
+ name: EGROUP4_EPATH3
+ default: 1
+ desc: |
+ Egroup 4, Epath 3
+ 1: Half a clock delay
+ 0: no delay
+ - range: 3
+ name: EGROUP4_EPATH0
+ default: 1
+ desc: |
+ Egroup 4, Epath 0
+ 1: Half a clock delay
+ 0: no delay
+ - range: 2
+ name: EGROUP3
+ default: 1
+ desc: |
+ Egroup 3, Epath 0
+ 1: Half a clock delay
+ 0: no delay
+ - range: 1
+ name: EGROUP2
+ default: 1
+ desc: |
+ Egroup 2, Epath 0
+ 1: Half a clock delay
+ 0: no delay
+ - range: 0
+ name: EGROUP1
+ default: 1
+ desc: |
+ Egroup 1, Epath 0
+ 1: Half a clock delay
+ 0: no delay
+# - ref: CR_XOFF_CTRL
+# offset: 0x2800
+# desc: Configure FromHost Xoff
+
+
+#Central Router monitors
+ - ref: CR_GBT_MON
+ offset: 0x3000
+ #- name: CR_STATIC_CONFIGURATION
+ # type: R
+ # bitfield:
+ # - range: 0
+ #- ref: CR_DEFAULT_EPROC_ENA_G
+ #- ref: CR_DEFAULT_EPROC_ENCODING_G
+ - name: MAX_TIMEOUT
+ type: R
+ desc: Maximum allowed timeout value
+ offset: 0x3410
+ bitfield:
+ - range: 31..0
+
+ - name: ELINK_REALIGNMENT
+ type: W
+ bitfield:
+ - range: any
+ name: CLEAR_REALIGNMENT_STATUS
+ type: T
+ value: 1
+ desc: Clears the ELINK Realignment event flags
+ - range: 0
+ name: ENABLE
+ default: 1
+ desc: Enable realignment mechanism in 8b10b E-Links after illegal character reception.
+
+ - ref: ELINK_REALIGNMENT_STATUS_GEN
+
+ - name: FULLMODE_32B_SOP
+ type: W
+ desc: When set to 1, use 32-bit 0x0000003C as start of chunk, otherwise only 8-bit 0x3C (FULL mode only)
+ bitfield:
+ - range: 0
+ default: 0
+
+ - name: FE_EMU_LOGIC
+ type: W
+ bitfield:
+ - range: 33
+ name: L1A_TRIGGERED
+ desc: 1 Send a chunk on every L1A, 0 use the IDLES to determine the rate
+ - range: 32
+ name: ENA
+ desc: Enable logic based FrontEnd emulator, instead of RAM based.
+ - range: 31..16
+ name: IDLES
+ desc: Number of IDLE bytes between chunks.
+ - range: 15..0
+ name: CHUNK_LENGTH
+ desc: Chunk length in bytes
+
+
+
+CR_GBT_CTRL:
+ number: 24
+ bitfield:
+ - range: 50..0
+ type: W
+ generate: GBT_NUM > {index:1}
+ entries:
+ - ref: EGROUP_TOHOST
+ - ref: EGROUP_FROMHOST
+
+EGROUP_TOHOST:
+ number: 7
+ format_name: GBT{index:02}
+ name: GBT
+ entries:
+ - name: TOHOST
+ format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
+ type_name: CR_TOHOST_EGROUP_CTRL
+ bitfield:
+ - range: 58..51
+ name: INSTANT_TIMEOUT_ENA
+ default: 0x0
+ desc: instantly initiate a timeout for the given epath
+ - range: 50..43
+ name: REVERSE_ELINKS
+ default: 0x0
+ desc: enables bit reversing for the elink in the given epath
+ - range: 42..31
+ name: MAX_CHUNK_LEN
+ default: MAX_CHUNK_LEN_array
+ desc: set the maximum length of a chunk, 0 disables truncation
+ - range: 30..15
+ name: PATH_ENCODING
+ desc: |
+ Encoding for every EPATH, 8 EPATHS per EGROUP
+ 0: direct mode
+ 1: 8b10b mode
+ 2: HDLC mode
+ default:
+ - PATH_ENCODING_array(0)
+ - PATH_ENCODING_array(1)
+ - PATH_ENCODING_array(2)
+ - PATH_ENCODING_array(3)
+ - PATH_ENCODING_array(4)
+ - PATH_ENCODING_array(5)
+ - PATH_ENCODING_array(6)
+
+ - range: 14..0
+ name: EPROC_ENA
+ desc: Enable bits per EPROC
+ default:
+ - EPROC_ENA_bits_array(0)
+ - EPROC_ENA_bits_array(1)
+ - EPROC_ENA_bits_array(2)
+ - EPROC_ENA_bits_array(3)
+ - EPROC_ENA_bits_array(4)
+ - EPROC_ENA_bits_array(5)
+ - EPROC_ENA_bits_array(6)
+
+EGROUP_FROMHOST:
+ number: 5
+ format_name: GBT{index:02}
+ entries:
+ - name: FROMHOST
+ desc: See Central Router Doc, indices [3,4] are optimized out in wideMode
+ format_name: CR_{name}_{parent}_EGROUP{index:1}_CTRL
+ type_name: CR_FROMHOST_EGROUP_CTRL
+ bitfield:
+ - range: 54..47
+ name: REVERSE_ELINKS
+ default: 0x0
+ desc: enables bit reversing for the elink in the given epath
+ - range: 46..15
+ name: PATH_ENCODING
+ desc: |
+ Encoding for every EPATH, 8 EPATHS per EGROUP
+ 0: direct mode
+ 1: 8b10b mode
+ 2: HDLC mode
+ greater than 3: TTC mode, see CentralRouter doc
+ default:
+ - FROMHOST_PATH_ENCODING_array(0)
+ - FROMHOST_PATH_ENCODING_array(1)
+ - FROMHOST_PATH_ENCODING_array(2)
+ - FROMHOST_PATH_ENCODING_array(3)
+ - FROMHOST_PATH_ENCODING_array(4)
+ - FROMHOST_PATH_ENCODING_array(5)
+ - FROMHOST_PATH_ENCODING_array(6)
+ - range: 14..0
+ desc: Enable bits per EPROC
+ name: EPROC_ENA
+
+# ----------------------- ITk strips link configuration start -----------------------
+
+ITK_STRIPS_CTRL:
+ entries:
+ - name: GLOBAL_STRIPS_CONFIG
+ desc: Synchronous trigger for all LCB links on device
+ type: W
+ bitfield:
+ - range: 15..11
+ type: W
+ name: TEST_MODULE_MASK
+ desc: (for tests only) contains R3 mask for the simulated trigger data
+ default: 0x0
+ - range: 10..4
+ type: W
+ name: TEST_R3L1_TAG
+ desc: (for tests only) contains R3 or L1 tag for the simulated trigger data
+ default: 0x0
+ - range: 1
+ type: W
+ name: TTC_GENERATE_GATING_ENABLE
+ desc: Global control for gating signal generation. Enables generating trickle gating signal in response to TTC BCR.
+ TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ (See also BC_START, and BC_STOP fields)
+ default: 0x0
+ - name: GLOBAL_TRICKLE_TRIGGER
+ type: T
+ bitfield:
+ - range: any
+ value: 1
+ desc: writing to this register issues a single trickle trigger for every LCB link connected to this FELIX device
+
+ - ref: ITK_STRIPS_GBT
+
+ - name: STRIPS_R3_TRIGGER
+ type: T
+ bitfield:
+ - range: any
+ value: 1
+ desc: (for tests only) simulate R3 trigger (issues 4-5 sequential triggers)
+ - name: STRIPS_L1_TRIGGER
+ type: T
+ bitfield:
+ - range: any
+ desc: (for tests only) simulate L1 trigger (issues 4-5 sequential triggers)
+ value: 1
+ - name: STRIPS_R3L1_TRIGGER
+ type: T
+ bitfield:
+ - range: any
+ desc: (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers)
+ value: 1
+
+ITK_STRIPS_GBT:
+ number: 4
+ format_name: STRIPS
+ generate: (GBT_NUM > {index:1} and FIRMWARE_MODE = 5)
+ entries:
+ - ref: ITK_STRIPS_LCB_LINKS
+ - ref: ITK_STRIPS_R3L1_LINKS
+
+ITK_STRIPS_LCB_LINKS:
+ number: 4
+ format_name: ITK_STRIPS_LCB_LINKS_{index:02}
+ type_name: ITK_LCB_LINK
+ entries:
+ - name: LCB
+ format_name: CR_{parent}_{name}_{index}
+ type_name: LCB_CTRL
+ desc: Determines LCB link configuration
+ type: W
+ bitfield:
+ - range: 49..38
+ type: W
+ name: L0A_BCR_DELAY
+ default: 0x0
+ desc: TTC BCR signal will be delayed by this many BCs
+ - range: 37..34
+ type: W
+ name: L0A_FRAME_DELAY
+ default: 0x0
+ desc: |
+ By how many BCs to delay an L0A frame. Updating this register may result in brief loss of LCB lock,
+ and some TTC L0A frames may be lost. Don't adjust this parameter while taking data.
+ - range: 33..32
+ type: W
+ name: FRAME_PHASE
+ default: 0x0
+ desc: phase of LCB frame with respect to TTC BCR signal
+ - range: 31..20
+ type: W
+ name: TRICKLE_BC_START
+ default: 0x0
+ desc: Determines the start of the allowed BC interval for low-priority LCB frames
+ - range: 19..8
+ type: W
+ name: TRICKLE_BC_STOP
+ default: 0x0
+ desc: Determines the end of the allowed BC interval for low-priority LCB frames
+ - range: 5..4
+ type: W
+ name: LCB_DESTINATION_MUX
+ default: 0x0
+ desc: |
+ Determines where the elink data is sent to:
+ 00: command decoder (use same command encoding format as trickle configuration)
+ 01: trickle memory (see phase2 documentation for command encoding format)
+ 10: directly to LCB link (expecting software-encoded HCC*/ABC* frames)
+ 11: (invalid, don't use)
+ - range: 3
+ type: W
+ name: TRICKLE_TRIG_RUN
+ default: 0x0
+ desc: |
+ if enabled, trickle configuration is sent out continuously to the front-end
+ (use together with TTC_GENERATE_GATING_EN for sending trickle configuration
+ continuously during a specified BC range. See also BC_START, and BC_STOP fields.)
+ - range: 2
+ type: W
+ name: TTC_L0A_ENABLE
+ default: 0x0
+ desc: enable generating L0A frames in response to TTC system signals
+ - range: 0
+ type: W
+ name: TTC_GENERATE_GATING_ENABLE
+ default: 0x0
+ desc: |
+ enables generating trickle gating signal in response to TTC BCR.
+ TRICKLE_TRIG_RUN must also be enabled for the trickle configuration to work.
+ (See also BC_START, and BC_STOP fields)
+ - name: TRICKLE_TRIGGER
+ format_name: CR_{parent}_{name}_{index}
+ type_name: TRICKLE_TRIGGER
+ type: T
+ bitfield:
+ - range: any
+ desc: writing to this register issues a single trickle trigger
+ value: 1
+ - name: TRICKLE_MEMORY_CONFIG
+ format_name: CR_{parent}_{name}_{index}
+ type_name: LCB_TRICKLE_CONFIG
+ desc: Trickle trigger configuration
+ type: W
+ bitfield:
+ - range: any
+ type: T
+ name: MOVE_WRITE_PTR
+ value: 1
+ desc: |
+ Writing to this register moves trickle configuration memory write pointer to WRITE_PTR address
+ - range: 47..32
+ type: W
+ name: WRITE_PTR
+ default: 0x0
+ desc: Trickle configuration memory write pointer
+ - range: 31..16
+ type: W
+ name: VALID_DATA_START
+ default: 0x0
+ desc: Start address of trickle configuration in trickle memory
+ - range: 15..0
+ type: W
+ name: VALID_DATA_END
+ default: 0x0
+ desc: Stop address of trickle configuration in trickle memory (last valid byte)
+ - name: MODULE_MASK_F_C
+ format_name: CR_{parent}_{name}_{index}
+ type_name: HCC_ABC_MASK_E_C
+ type: W
+ desc: |
+ Disables register commands addressed to masked HCC*/ABC* chips. Register commands for which
+ corresponding mask bit is set to '1' will be ignored by the command encoder.
+ This is useful to quickly disable trickle configuration for selected
+ modules without overwriting the entire trickle configuratrion memory.
+ bitfield:
+ - range: 63..48
+ type: W
+ name: HCC_MASK
+ default: 0x0
+ desc: |
+ HCC* module mask
+ - range: 47..32
+ type: W
+ name: ABC_MASK_HCC_E
+ default: 0x0
+ desc: |
+ Masks register commands with destination hcc_id = 0xE
+ mask(i) <=> (abc_id = i)
+ - range: 31..16
+ type: W
+ name: ABC_MASK_HCC_D
+ default: 0x0
+ desc: |
+ Masks register commands with destination hcc_id = 0xD
+ mask(i) <=> (abc_id = i)
+ - range: 15..0
+ type: W
+ name: ABC_MASK_HCC_C
+ default: 0x0
+ desc: |
+ Masks register commands with destination hcc_id = 0xC
+ mask(i) <=> (abc_id = i)
+ - name: ABC_MODULE_MASK_B_8
+ format_name: CR_{parent}_{name}_{index}
+ type_name: LCB_ABC_MASK_B_8
+ type: W
+ desc: |
+ Disables register commands addressed to masked ABC* chips. Register commands for which
+ corresponding mask bit is set to '1' will be ignored by the command encoder.
+ This is useful to quickly disable trickle configuration for selected
+ modules without overwriting the entire trickle configuratrion memory.
+ bitfield:
+ - range: 63..48
+ type: W
+ name: ABC_MASK_HCC_B
+ default: 0x0
+ desc: |
+ Masks register commands with destination hcc_id = 0xB
+ mask(i) <=> (abc_id = i)
+ - range: 47..32
+ type: W
+ name: ABC_MASK_HCC_A
+ default: 0x0
+ desc: |
+ Masks register commands with destination hcc_id = 0xA
+ mask(i) <=> (abc_id = i)
+ - range: 31..16
+ type: W
+ name: ABC_MASK_HCC_9
+ default: 0x0
+ desc: |
+ Masks register commands with destination hcc_id = 0x9
+ mask(i) <=> (abc_id = i)
+ - range: 15..0
+ type: W
+ name: ABC_MASK_HCC_8
+ default: 0x0
+ desc: |
+ Masks register commands with destination hcc_id = 0x8
+ mask(i) <=> (abc_id = i)
+ - name: ABC_MODULE_MASK_7_4
+ format_name: CR_{parent}_{name}_{index}
+ type_name: LCB_ABC_MASK_7_4
+ type: W
+ desc: |
+ Disables register commands addressed to masked ABC* chips. Register commands for which
+ corresponding mask bit is set to '1' will be ignored by the command encoder.
+ This is useful to quickly disable trickle configuration for selected
+ modules without overwriting the entire trickle configuratrion memory.
+ bitfield:
+ - range: 63..48
+ type: W
+ name: ABC_MASK_HCC_7
+ default: 0x0
+ desc: |
+ Masks register commands with destination hcc_id = 0x7
+ mask(i) <=> (abc_id = i)
+ - range: 47..32
+ type: W
+ name: ABC_MASK_HCC_6
+ default: 0x0
+ desc: |
+ Masks register commands with destination hcc_id = 0x6
+ mask(i) <=> (abc_id = i)
+ - range: 31..16
+ type: W
+ name: ABC_MASK_HCC_5
+ default: 0x0
+ desc: |
+ Masks register commands with destination hcc_id = 0x5
+ mask(i) <=> (abc_id = i)
+ - range: 15..0
+ type: W
+ name: ABC_MASK_HCC_4
+ default: 0x0
+ desc: |
+ Masks register commands with destination hcc_id = 0x4
+ mask(i) <=> (abc_id = i)
+ - name: ABC_MODULE_MASK_3_0
+ format_name: CR_{parent}_{name}_{index}
+ type_name: LCB_ABC_MASK_3_0
+ type: W
+ desc: |
+ Disables register commands addressed to masked ABC* chips. Register commands for which
+ corresponding mask bit is set to '1' will be ignored by the command encoder.
+ This is useful to quickly disable trickle configuration for selected
+ modules without overwriting the entire trickle configuratrion memory.
+ bitfield:
+ - range: 63..48
+ type: W
+ name: ABC_MASK_HCC_3
+ default: 0x0
+ desc: |
+ Masks register commands with destination hcc_id = 0x3
+ mask(i) <=> (abc_id = i)
+ - range: 47..32
+ type: W
+ name: ABC_MASK_HCC_2
+ default: 0x0
+ desc: |
+ Masks register commands with destination hcc_id = 0x2
+ mask(i) <=> (abc_id = i)
+ - range: 31..16
+ type: W
+ name: ABC_MASK_HCC_1
+ default: 0x0
+ desc: |
+ Masks register commands with destination hcc_id = 0x1
+ mask(i) <=> (abc_id = i)
+ - range: 15..0
+ type: W
+ name: ABC_MASK_HCC_0
+ default: 0x0
+ desc: |
+ Masks register commands with destination hcc_id = 0x0
+ mask(i) <=> (abc_id = i)
+
+
+ITK_STRIPS_R3L1_LINKS:
+ number: 4
+ format_name: ITK_R3L1_LINK_{index:02}
+ type_name: ITK_R3L1_LINK
+ entries:
+ - name: R3L1
+ format_name: CR_{parent}_{name}_{index:1}
+ type_name: R3L1_CTRL
+ desc: Determines R3L1 link configuration
+ type: W
+ bitfield:
+ - range: 3..2
+ type: W
+ name: FRAME_PHASE
+ default: 0x0
+ desc: phase of R3L1 frame with respect to TTC BCR signal
+ - range: 1
+ type: W
+ name: L1_ENABLE
+ default: 0x0
+ desc: enables sending TTC L1 signals to the front-end
+ - range: 0
+ type: W
+ name: R3_ENABLE
+ default: 0x0
+ desc: enables sending RoI R3 signals to the front-end
+
+
+# ----------------------- ITk strips link configuration end -----------------------
+
+#CR_XOFF_CTRL:
+# number: 24
+# type: W
+# bitfield:
+# - range: 39..0
+# entries:
+# - name: FROMHOST_XOFF_ENABLE
+# format_name: FROMHOST_XOFF_ENABLE_{index:02}
+# desc: When the corresponding ToHost (FULL Mode) channel reports full, this FromHost 2-bit elink will transmit Xoff
+# range: 39..0
+# default: 0
+# - name: FROMHOST_SOFT_XOFF
+# format_name: FROMHOST_SOFT_XOFF_{index:02}
+# desc: Transmit Xoff on corresponding 2-bit FromHost elink if configured in 8b10b mode. Transmit Xon when cleared
+# range: 39..0
+# default: 0
+
+
+#IC_FIFOS:
+# number: 24
+# format_name: IC_FROMHOST_TOHOST_FIFOS
+# entries:
+# - name: FROMHOST
+# format_name: IC_FROMHOST_FIFO_{index:02}
+# type_name: IC_FROMHOST_FIFO
+# type: W
+# generate: GBT_NUM > {index:1}
+# bitfield:
+# - range: any
+# type: T
+# value: not register_map_monitor_s.register_map_cr_monitor.IC_FROMHOST_FIFO({index}).FULL
+# name: WE
+# format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
+# desc: Any write to this register will trigger a write to the FIFO
+# - range: 8
+# type: R
+# name: FULL
+# format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
+# desc: Full flag of the fifo, do not write if 1
+# - range: 7..0
+# type: W
+# name: DATAIN
+# format_name: IC_FROMHOST_FIFO_{index:02}_{bitfield}
+# desc: Data input of fifo
+# - name: TOHOST
+# format_name: IC_TOHOST_FIFO_{index:02}
+# type_name: IC_TOHOST_FIFO
+# type: W
+# generate: GBT_NUM > {index:1}
+# bitfield:
+# - range: any
+# type: T
+# value: not register_map_monitor_s.register_map_cr_monitor.IC_TOHOST_FIFO({index}).EMPTY
+# name: RE
+# format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
+# desc: Any write to this register will trigger a read enable from the fifo
+# - range: 8
+# type: R
+# name: EMPTY
+# format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
+# desc: Empty flag of the fifo, do not read if 1
+# - range: 7..0
+# type: R
+# name: DATAOUT
+# format_name: IC_TOHOST_FIFO_{index:02}_{bitfield}
+# desc: Data output of fifo
+
+
+MINI_EGROUP_CTRL:
+ number: 24
+ format_name: MINI_EGROUP_CTRLS
+ entries:
+ - name: EC_TOHOST
+ format_name: EC_TOHOST_{index:02}
+ type_name: EC_TOHOST
+ desc: Configures the ToHost Mini egroup in EC mode
+ type: W
+ generate: GBT_NUM > {index:1}
+ bitfield:
+ - range: 7
+ name: SCA_AUX_BIT_SWAPPING
+ desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
+ default: 0
+ - range: 6
+ name: SCA_AUX_ENABLE
+ desc: Enables the SCA AUX channel
+ default: 1
+ - range: 5
+ name: IC_BIT_SWAPPING
+ desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
+ default: 1
+ - range: 4
+ name: IC_ENABLE
+ desc: Enables the IC channel
+ default: 1
+ - range: 3
+ name: BIT_SWAPPING
+ desc: "0: two input bits of EC e-link are as documented, 1: two input bits are swapped"
+ default: 0
+ - range: 2..1
+ name: ENCODING
+ desc: Configures encoding of the EC channel
+ default: 0x2
+ - range: 0
+ name: ENABLE
+ desc: Enables the EC channel
+ default: 1
+ - name: EC_FROMHOST
+ format_name: EC_FROMHOST_{index:02}
+ type_name: EC_FROMHOST
+ type: W
+ desc: Configures the FromHost Mini egroup in EC mode
+ generate: GBT_NUM > {index:1}
+ bitfield:
+ - range: 9
+ name: SCA_AUX_BIT_SWAPPING
+ desc: "0: two input bits of SCA AUX e-link are as documented, 1: two input bits are swapped"
+ default: 0
+ - range: 8
+ name: SCA_AUX_ENABLE
+ desc: Enables the SCA AUX channel
+ default: 1
+ - range: 7
+ name: IC_BIT_SWAPPING
+ desc: "0: two input bits of IC e-link are as documented, 1: two input bits are swapped"
+ default: 1
+ - range: 6
+ name: IC_ENABLE
+ desc: Enables the IC channel
+ default: 1
+ - range: 5
+ name: BIT_SWAPPING
+ desc: "0: two output bits of EC e-link are as documented, 1: two output bits are swapped"
+ default: 0
+ - range: 4..1
+ name: ENCODING
+ desc: Configures encoding of the EC channel
+ default: 0x2
+ - range: 0
+ name: ENABLE
+ default: 1
+
+
+CR_GBT_MON:
+ desc: See Central Router Doc
+ endpoints: 0
+ number: 24
+ entries:
+ - name: TOHOST
+ type_name: CR_TOHOST_GBT_MON
+ format_name: CR_{name}_GBT{index:02}_MON
+ generate: GBT_NUM > {index:1}
+ bitfield:
+ - range: 58
+ name: CROUTFIFO_PROG_FULL
+ - range: 57
+ name: WMFIFO_FULL
+ - range: 56
+ name: MINI_EGROUP_ALMOST_FULL
+ - range: 55..48
+ name: EPATH6_ALMOST_FULL
+ desc: Almost full bits of the EPATH fifos in EGROUP6
+ - range: 47..40
+ name: EPATH5_ALMOST_FULL
+ desc: Almost full bits of the EPATH fifos in EGROUP5
+ - range: 39..32
+ name: EPATH4_ALMOST_FULL
+ desc: Almost full bits of the EPATH fifos in EGROUP4
+ - range: 31..24
+ name: EPATH3_ALMOST_FULL
+ desc: Almost full bits of the EPATH fifos in EGROUP3
+ - range: 23..16
+ name: EPATH2_ALMOST_FULL
+ desc: Almost full bits of the EPATH fifos in EGROUP2
+ - range: 15..8
+ name: EPATH1_ALMOST_FULL
+ desc: Almost full bits of the EPATH fifos in EGROUP1
+ - range: 7..0
+ name: EPATH0_ALMOST_FULL
+ desc: Almost full bits of the EPATH fifos in EGROUP0
+ - name: FROMHOST
+ type_name: CR_FROMHOST_GBT_MON
+ format_name: CR_{name}_GBT{index:02}_MON
+ generate: GBT_NUM > {index:1}
+ bitfield:
+ - range: 40
+ name: MINI_EGROUP_ALMOST_FULL
+ - range: 39..32
+ name: EPATH4_ALMOST_FULL
+ desc: Almost full bits of the EPATH fifos in EGROUP4
+ - range: 31..24
+ name: EPATH3_ALMOST_FULL
+ desc: Almost full bits of the EPATH fifos in EGROUP3
+ - range: 23..16
+ name: EPATH2_ALMOST_FULL
+ desc: Almost full bits of the EPATH fifos in EGROUP2
+ - range: 15..8
+ name: EPATH1_ALMOST_FULL
+ desc: Almost full bits of the EPATH fifos in EGROUP1
+ - range: 7..0
+ name: EPATH0_ALMOST_FULL
+ desc: Almost full bits of the EPATH fifos in EGROUP0
+
+ELINK_REALIGNMENT_STATUS_GEN:
+ endpoints: 0, 1
+ number: 12
+ entries:
+ - name: ELINK_REALIGNMENT_STATUS
+ type_name: ELINK_REALIGNMENT_STATUS
+ format_name: ELINK_REALIGNMENT_STATUS_{index:02}
+ generate: GBT_NUM > {index:1}
+ desc: |
+ A realignment event due to an illegal 8b10b symbol has occurred.
+ 1 bit per Epath.
+ Clear status by writing to ELINK_REALIGNMENT.CLEAR_REALIGNMENT_STATUS
+ bitfield:
+ - range: 41..0
+
+
+
+GBTEmulatorControlsAndMonitors:
+ group: GEC
+ desc: GBT Emulator Controls and Monitors
+ endpoints: 0, 1
+ entries:
+ - name: GBT_EMU_ENA
+ type: W
+ bitfield:
+ - range: 1
+ name: TOFRONTEND
+ desc: Enable GBT dummy emulator ToFrontEnd
+ - range: 0
+ name: TOHOST
+ desc: Enable GBT dummy emulator ToHost
+
+ - name: GBT_EMU_CONFIG_WE_ARRAY
+ type: W
+ bitfield:
+ - range: 6..0
+ desc: write enable array, every bit is one emulator RAM block
+
+ - name: GBT_EMU_CONFIG
+ type: W
+ bitfield:
+ - range: 63..48
+ name: RDDATA
+ type: R
+ desc: read data bus
+ - range: 45..32
+ name: WRADDR
+ desc: write address bus
+ - range: 15..0
+ name: WRDATA
+ desc: write data bus
+
+ - name: GBT_FM_EMU_ENA_TOHOST
+ type: W
+ bitfield:
+ - range: 0
+ desc: Enable FULL mode dummy emulator ToHost
+
+ - name: GBT_FM_EMU_CONFIG_WE_ARRAY
+ type: W
+ bitfield:
+ - range: 0
+ desc: write enable for the full mode emulator ram block
+
+ - name: GBT_FM_EMU_CONFIG
+ type: W
+ bitfield:
+ - range: 53..40
+ name: WRADDR
+ desc: write address bus
+ - range: 35..0
+ name: WRDATA
+ desc: write data bus
+
+ - name: GBT_FM_EMU_READ
+ type: R
+ bitfield:
+ - range: 35..0
+ desc: read emu ram data
+
+
+ - name: CR_FM_PATH_ENA
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: FULL mode CR enable array, every bit is one path
+
+ - ref: PATH_HAS_STREAM_ID
+
+PATH_HAS_STREAM_ID:
+ number: 24
+ generate: GBT_NUM > {index:1}
+ entries:
+ - name: TOHOST
+ format_name: LINK_{index:02}_HAS_STREAM_ID
+ type_name: HAS_STREAM_ID
+ type: W
+ bitfield:
+ - range: 55..48
+ name: EGROUP6
+ default: 0x0
+ desc: EPATH (Wide mode) is associated with a STREAM ID
+ - range: 47..40
+ name: EGROUP5
+ default: 0x0
+ desc: EPATH (Wide mode) is associated with a STREAM ID
+ - range: 39..32
+ name: EGROUP4
+ default: 0x0
+ desc: EPATH is associated with a STREAM ID
+ - range: 31..24
+ name: EGROUP3
+ default: 0x0
+ desc: EPATH is associated with a STREAM ID
+ - range: 23..16
+ name: EGROUP2
+ default: 0x0
+ desc: EPATH is associated with a STREAM ID
+ - range: 15..8
+ name: EGROUP1
+ default: 0x0
+ desc: EPATH is associated with a STREAM ID
+ - range: 7..0
+ name: EGROUP0
+ default: 0x0
+ desc: EPATH is associated with a STREAM ID, use only bit0 for FULL mode.
+
+
+GBTWrapperControls:
+ group: GWC
+ desc: GBT Wrapper Controls
+ type: W
+ endpoints: 0
+ entries:
+ - name: GBT_CHANNEL_DISABLE
+ offset: 0x0400
+ bitfield:
+ - range: 47..0
+ desc: Disable selected GBT or FULL mode channel
+
+ - name: GBT_GENERAL_CTRL
+ bitfield:
+ - range: 63..0
+ desc: Alignment chk reset (not self clearing)
+
+ - name: GBT_MODE_CTRL
+ bitfield:
+ - range: 2
+ name: RX_ALIGN_TB_SW
+ desc: RX_ALIGN_TB_SW
+ - range: 1
+ name: RX_ALIGN_SW
+ desc: RX_ALIGN_SW
+ - range: 0
+ name: DESMUX_USE_SW
+ desc: DESMUX_USE_SW
+
+ - name: GBT_RXSLIDE_SELECT
+ offset: 0x0480
+ desc: RxSlide select [47:0]
+ generate: GBT_GENERATE_ALL_REGS
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_RXSLIDE_MANUAL
+ desc: RxSlide select [47:0]
+ generate: GBT_GENERATE_ALL_REGS
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_TXUSRRDY
+ desc: TxUsrRdy [47:0]
+ generate: GBT_GENERATE_ALL_REGS
+ bitfield:
+ - range: 47..0
+ default: 0xFFFFFFFFFFFF
+
+ - name: GBT_RXUSRRDY
+ desc: RxUsrRdy [47:0]
+ generate: GBT_GENERATE_ALL_REGS
+ bitfield:
+ - range: 47..0
+ default: 0xFFFFFFFFFFFF
+
+ - name: GBT_SOFT_RESET
+ desc: SOFT_RESET [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_GTTX_RESET
+ desc: GTTX_RESET [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_GTRX_RESET
+ desc: GTRX_RESET [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_PLL_RESET
+ bitfield:
+ - range: 59..48
+ name: QPLL_RESET
+ desc: QPLL_RESET [11:0]
+ - range: 47..0
+ name: CPLL_RESET
+ desc: CPLL_RESET [47:0]
+
+ - name: GBT_SOFT_TX_RESET
+ offset: 0x0500
+ generate: GBT_GENERATE_ALL_REGS
+ bitfield:
+ - range: 59..48
+ name: RESET_ALL
+ desc: SOFT_TX_RESET_ALL [11:0]
+ - range: 47..0
+ name: RESET_GT
+ desc: SOFT_TX_RESET_GT [47:0]
+
+ - name: GBT_SOFT_RX_RESET
+ generate: GBT_GENERATE_ALL_REGS
+ bitfield:
+ - range: 59..48
+ name: RESET_ALL
+ desc: SOFT_TX_RESET_ALL [11:0]
+ - range: 47..0
+ name: RESET_GT
+ desc: SOFT_TX_RESET_GT [47:0]
+
+ - name: GBT_ODD_EVEN
+ desc: OddEven [47:0]
+ generate: GBT_GENERATE_ALL_REGS
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_TOPBOT
+ desc: TopBot [47:0]
+ generate: GBT_GENERATE_ALL_REGS
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_TX_TC_DLY_VALUE1
+ bitfield:
+ - range: 47..0
+ default: 0x333333333333
+ desc: TX_TC_DLY_VALUE [47:0]
+
+ - name: GBT_TX_TC_DLY_VALUE2
+ bitfield:
+ - range: 47..0
+ default: 0x333333333333
+ desc: TX_TC_DLY_VALUE [95:48]
+
+ - name: GBT_TX_TC_DLY_VALUE3
+ bitfield:
+ - range: 47..0
+ default: 0x333333333333
+ desc: TX_TC_DLY_VALUE [143:96]
+
+ - name: GBT_TX_TC_DLY_VALUE4
+ bitfield:
+ - range: 47..0
+ default: 0x333333333333
+ desc: TX_TC_DLY_VALUE [191:144]
+
+ - name: GBT_DATA_TXFORMAT1
+ desc: DATA_TXFORMAT [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_DATA_TXFORMAT2
+ desc: DATA_TXFORMAT [95:48]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_DATA_RXFORMAT1
+ desc: DATA_RXFORMAT [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_DATA_RXFORMAT2
+ desc: DATA_RXFORMAT [95:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_TX_RESET
+ desc: TX Logic reset [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_RX_RESET
+ desc: RX Logic reset [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_TX_TC_METHOD
+ desc: TX time domain crossing method [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_OUTMUX_SEL
+ desc: Descrambler output MUX selection [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_TC_EDGE
+ desc: Sampling edge selection for TX domain crossing [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_TXPOLARITY
+ desc: |
+ 0: default polarity
+ 1: reversed polarity for transmitter of GTH channels
+ bitfield:
+ - range: 47..0
+ default: 0
+
+ - name: GBT_RXPOLARITY
+ desc: |
+ 0: default polarity
+ 1: reversed polarity for the receiver of the GTH channels
+ bitfield:
+ - range: 47..0
+ default: 0
+
+ - name: GTH_LOOPBACK_CONTROL
+ bitfield:
+ - range: 2..0
+ default: 0x0
+ desc: |
+ Controls loopback for loopback: read UG476 for the details. NOTE: the TXBUFFER is disabled, near end PCS loopback is not supported.
+ 000: Normal operation
+ 001: Near-End PCS Loopback
+ 010: Near-End PMA Loopback
+ 011: Reserved
+ 100: Far-End PMA Loopback
+ 101: Reserved
+ 110: Far-End PCS Loopback
+
+ - name: GBT_TOHOST_FANOUT
+ offset: 0x0700
+ bitfield:
+ - range: 48
+ name: LOCK
+ default: 0x0
+ desc: Locks this particular register. If set prevents software from touching it.
+ - range: 47..0
+ name: SEL
+ default: 0x0
+ desc: |
+ ToHost FanOut/Selector. Every bitfield is a channel:
+ 1 : GBT_EMU, select GBT Emulator for a specific CentralRouter channel
+ 0 : GBT_WRAP, select real GBT link for a specific CentralRouter channel
+
+ - name: GBT_TOFRONTEND_FANOUT
+ bitfield:
+ - range: 48
+ name: LOCK
+ default: 0x0
+ desc: Locks this particular register. If set prevents software from touching it.
+ - range: 47..0
+ name: SEL
+ default: 0x0
+ desc: |
+ ToFrontEnd FanOut/Selector. Every bitfield is a channel:
+ 1 : GBT_EMU, select GBT Emulator for a specific GBT link
+ 0 : TTC_DEC, select CentralRouter data (including TTC) for a specific GBT link
+
+ - name: FULLMODE_AUTO_RX_RESET
+ bitfield:
+ - range: 32
+ name: ENABLE
+ default: 1
+ desc: Enable the Automatic RX Reset mechanism
+ - range: 31..0
+ name: TIMEOUT
+ default: 0x00100000
+ desc: Number of 40 MHz clock cycles until an unaligned link results in a reset pulse
+
+
+GBTWrapperMonitors:
+ group: GWM
+ desc: GBT Wrapper Monitors
+ endpoints: 0
+ entries:
+ - name: GBT_VERSION
+ offset: 0x0600
+ bitfield:
+ - range: 63..48
+ name: DATE
+ desc: Date
+ - range: 47..32
+ name: GBT_VERSION
+ desc: GBT Version
+ - range: 31..16
+ name: GTH_IP_VERSION
+ desc: GTH IP Version
+ - range: 15..3
+ name: RESERVED
+ desc: Reserved
+ - range: 2
+ name: GTHREFCLK_SEL
+ desc: GTHREFCLK SEL
+ - range: 1
+ name: RX_CLK_SEL
+ desc: RX CLK SEL
+ - range: 0
+ name: PLL_SEL
+ desc: PLL SEL
+
+ - name: GBT_TXRESET_DONE
+ offset: 0x0680
+ desc: TX Reset done [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_RXRESET_DONE
+ desc: RX Reset done [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_TXFSMRESET_DONE
+ desc: TX FSM Reset done [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_RXFSMRESET_DONE
+ desc: RX FSM Reset done [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_CPLL_FBCLK_LOST
+ desc: CPLL FBCLK LOST [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_PLL_LOCK
+ bitfield:
+ - range: 59..48
+ name: QPLL_LOCK
+ desc: QPLL LOCK [11:0]
+ - range: 47..0
+ name: CPLL_LOCK
+ desc: CPLL LOCK [47:0]
+
+ - name: GBT_RXCDR_LOCK
+ desc: RX CDR LOCK [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_CLK_SAMPLED
+ desc: clk sampled [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_RX_IS_HEADER
+ desc: RX IS HEADER [47:0]
+ generate: GBT_GENERATE_ALL_REGS
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_RX_IS_DATA
+ desc: RX IS DATA [47:0]
+ generate: GBT_GENERATE_ALL_REGS
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_RX_HEADER_FOUND
+ desc: RX HEADER FOUND [47:0]
+ generate: GBT_GENERATE_ALL_REGS
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_ALIGNMENT_DONE
+ desc: RX ALIGNMENT DONE [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_OUT_MUX_STATUS
+ desc: GBT output mux status [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_ERROR
+ desc: Error flags [47:0]
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_GBT_TOPBOT_C
+ desc: TopBot_c [47:0]
+ generate: GBT_GENERATE_ALL_REGS
+ bitfield:
+ - range: 47..0
+
+ - name: GBT_FM_RX_DISP_ERROR1
+ offset: 0x0800
+ bitfield:
+ - range: 47..0
+ desc: Rx disparity error [47:0]
+
+ - name: GBT_FM_RX_DISP_ERROR2
+ bitfield:
+ - range: 47..0
+ desc: Rx disparity error [96:48]
+
+ - name: GBT_FM_RX_NOTINTABLE1
+ bitfield:
+ - range: 47..0
+ desc: Rx not in table [47:0]
+
+ - name: GBT_FM_RX_NOTINTABLE2
+ bitfield:
+ - range: 47..0
+ desc: Rx not in table [96:48]
+
+TTCBUSYControlsAndMonitors:
+ group: TTCBUSY
+ desc: TTC and BUSY Controls and Monitors
+ endpoints: 0
+ entries:
+
+ - ref: TTC_DEC_CTRLMON
+ desc: control and monitor bits for TTC decoder
+
+ - ref: TTC_BUSY_ACCEPTED_G
+
+ - name: TTC_EMU
+ type: W
+ bitfield:
+ - range: 2
+ name: FULL
+ type: R
+ desc: TTC Emulator memory full indication
+ - range: 1
+ name: SEL
+ desc: Select TTC data source 1 TTC Emu | 0 TTC Decoder
+ - range: 0
+ name: ENA
+ desc: Clear to load into the TTC emulator’s memory the required sequence, Set to run the TTC emulator sequence
+
+ - ref: TTC_DELAY
+
+ - name: TTC_BUSY_TIMING_CTRL
+ descr: Controls the BUSY Logic
+ type: W
+ bitfield:
+ - range: 51..32
+ name: PRESCALE
+ default: 0x0000F
+ desc: Prescales the 40MHz clock to create an internal slow clock
+ - range: 31..16
+ name: BUSY_WIDTH
+ default: 0x000F
+ desc: Minimum number of 40MHz clocks that the busy is asserted
+ - range: 15..0
+ name: LIMIT_TIME
+ default: 0x000F
+ desc: Number of prescaled clocks a given busy must be asserted before it is recognized
+
+ - name: TTC_BUSY_CLEAR
+ desc: clears the latching busy bits in TTC_BUSY_ACCEPTED
+ type: T
+ value: 1
+ bitfield:
+ - range: any
+
+ - name: TTC_EMU_CONTROL
+ type: W
+ bitfield:
+ - range: 33
+ name: BUSY_IN_ENABLE
+ desc: Enable internal BUSY input to stop L1A on BUSY
+ default: 1
+ - range: 32..27
+ name: BROADCAST
+ desc: Broadcast data
+ - range: 26
+ name: ECR
+ desc: Event counter reset
+ - range: 25
+ name: BCR
+ desc: Bunch counter reset
+ - range: 24
+ name: L1A
+ desc: Level 1 Accept
+
+ - name: TTC_EMU_L1A_PERIOD
+ type: W
+ desc: L1A period in BC. 0 means manual L1A with TTC_EMU_CONTROL.L1A
+ bitfield:
+ - range: 31..0
+
+ - name: TTC_EMU_ECR_PERIOD
+ type: W
+ desc: ECR period in BC. 0 means manual ECR with TTC_EMU_CONTROL.ECR
+ bitfield:
+ - range: 31..0
+
+ - name: TTC_EMU_BCR_PERIOD
+ type: W
+ desc: BCR period in BC. 0 means manual BCR with TTC_EMU_CONTROL.BCR
+ bitfield:
+ - range: 31..0
+ default: 3564
+
+ - name: TTC_EMU_LONG_CHANNEL_DATA
+ type: W
+ desc: Long channel data for the TTC emulator
+ bitfield:
+ - range: 31..0
+
+ - name: TTC_EMU_RESET
+ desc: Any write to this register resets the TTC Emulator to the default state.
+ type: W
+ bitfield:
+ - range: any
+ value: 1
+ type: T
+
+ - name: TTC_L1ID_MONITOR
+ desc: Monitor L1ID and XL1ID.
+ type: R
+ bitfield:
+ - range: 31..0
+
+ - name: TTC_ECR_MONITOR
+ desc: Counts the number of ECRs received from the TTC system, any write to this register clears the counter
+ type: W
+ bitfield:
+ - range: any
+ type: T
+ value: 1
+ name: CLEAR
+ - range: 31..0
+ type: R
+ name: VALUE
+
+ - name: TTC_TTYPE_MONITOR
+ desc: Counts the number of TType received from the TTC system, any write to this register clears the counter
+ type: W
+ bitfield:
+ - range: any
+ type: T
+ value: 1
+ name: CLEAR
+ - range: 31..0
+ type: R
+ name: VALUE
+
+ - name: TTC_BCR_PERIODICITY_MONITOR
+ desc: Counts the number of times the BCR period does not match 3564, any write to this register clears the counter
+ type: W
+ bitfield:
+ - range: any
+ type: T
+ value: 1
+ name: CLEAR
+ - range: 31..0
+ type: R
+ name: VALUE
+
+ - name: TTC_BCR_COUNTER
+ desc: Counts the number of times BCR is issued, any write to this register clears the counter
+ type: W
+ bitfield:
+ - range: any
+ type: T
+ value: 1
+ name: CLEAR
+ - range: 31..0
+ type: R
+ name: VALUE
+
+TTC_DEC_CTRLMON:
+ group: TDCM
+ format_name: TTC_DEC_CTRLMON
+ entries:
+ - name: TTC_DEC_CTRL
+ format_name: TTC_DEC_CTRL
+ type_name: TTC_DEC_CTRLS
+ type: W
+ bitfield:
+ - range: 30..27
+ name: B_CHAN_DELAY
+ type: W
+ desc: Number of BC to delay the L1A distribution to the frontends
+ - range: 26..15
+ name: BCID_ONBCR
+ type: W
+ desc: BCID is set to this value when BCR arrives
+ - range: 14
+ name: BUSY_OUTPUT_STATUS
+ type: R
+ desc: Actual status of the BUSY LEMO output signal
+ - range: 13
+ name: ECR_BCR_SWAP
+ default: 0
+ desc: ECR and BCR signals are swapped at the output of the TTC decoder (needed only for LAr TTC)
+ - range: 12
+ name: BUSY_OUTPUT_INHIBIT
+ default: 0
+ desc: forces the Busy LEMO output to BUSY-OFF
+ - range: 11
+ name: TOHOST_RST
+ desc: reset toHost in ttc decoder
+ default: 0
+ - range: 10
+ name: TT_BCH_EN
+ desc: trigger type enable / disable for TTC-ToHost
+ default: 1
+ - range: 9..2
+ name: XL1ID_SW
+ desc: set XL1ID value, the value to be set by XL1ID_RST signal
+ default: 0x00
+ - range: 1
+ name: XL1ID_RST
+ desc: giving a trigger signal to reset XL1ID value
+ default: 0
+ - range: 0
+ name: MASTER_BUSY
+ desc: L1A trigger throttling
+ default: 0
+ - name: TTC_DEC_MON
+ format_name: TTC_DEC_MON
+ type_name: TTC_DEC_MONS
+ type: R
+ bitfield:
+ - range: 15..5
+ name: TH_FF_COUNT
+ desc: ToHostData Fifo counts
+ - range: 4
+ name: TH_FF_FULL
+ desc: ToHostData Fifo status 1:full 0:not full
+ - range: 3
+ name: TH_FF_EMPTY
+ desc: ToHostData Fifo status 1:empty 0:not empty
+ - range: 2..0
+ name: TTC_BIT_ERR
+ desc: double bit, single bit and comm error in TTC data
+
+TTC_BUSY_ACCEPTED_G:
+ desc: busy has been asserted by the given ELINK. Reset by writing to TTC_BUSY_CLEAR
+ number: 24
+ endpoints: 0,1
+ type: R
+ entries:
+ - name: TTC_BUSY_ACCEPTED
+ format_name: TTC_BUSY_ACCEPTED{index:02}
+ type_name: TTC_BUSY_ACCEPTED
+ bitfield:
+ - range: 56..0
+
+
+
+TTC_DELAY:
+ number: 48
+ type: W
+ entries:
+ - name: TTC_DELAY
+ format_name: TTC_DELAY_{index:02}
+ type_name: TTC_DELAY
+ desc: Controls the TTC Fanout delay values
+ bitfield:
+ - range: 3..0
+ default: 0
+
+XOFF_BUSYControlsAndMonitors:
+ group: XOFF
+ desc: XOFF Controls and Monitors, see table 2 of Busy specs manual
+ endpoints: 0, 1
+ entries:
+ - name: XOFF_FM_CH_FIFO_THRESH_LOW
+ type: W
+ bitfield:
+ - range: 3..0
+ default: 0xB
+ desc: |
+ Controls the low threshold of the channel fifo in FULL mode on which
+ an Xon will be asserted, bitfields control 4 MSB
+ - name: XOFF_FM_CH_FIFO_THRESH_HIGH
+ type: W
+ bitfield:
+ - range: 3..0
+ default: 0xB
+ desc: |
+ Controls the high threshold of the channel fifo in FULL mode on which
+ an Xoff will be asserted, bitfields control 4 MSB
+ - name: XOFF_FM_LOW_THRESH_CROSSED
+ desc: FIFO filled beyond the low threshold, 1 bit per channel
+ type: R
+ bitfield:
+ - range: 23..0
+ - name: XOFF_FM_HIGH_THRESH
+ type: W
+ bitfield:
+ - range: any
+ name: CLEAR_LATCH
+ desc: Writing this register will clear all CROSS_LATCHED bits
+ type: T
+ value: 1
+ - range: 47..24
+ type: R
+ name: CROSS_LATCHED
+ desc: FIFO filled beyond the high threshold, 1 latch bit per channel
+ - range: 23..0
+ type: R
+ name: CROSSED
+ desc: FIFO filled beyond the high threshold, 1 bit per channel
+
+ - name: XOFF_FM_SOFT_XOFF
+ type: W
+ desc: Set any bit in this register to assert XOFF for the given channel, clearing bits will assert XON
+ bitfield:
+ - range: 23..0
+
+ - name: XOFF_ENABLE
+ type: W
+ desc: Enable XOFF assertion (To Frontend) in case the FULL mode CH FIFO gets beyond thresholds. One bit per channel
+ bitfield:
+ - range: 23..0
+
+ - name: DMA_BUSY_STATUS
+ type: W
+ bitfield:
+ - range: any
+ type: T
+ value: 1
+ name: CLEAR_LATCH
+ desc: Any write to this register clears TOHOST_BUSY_LATCHED
+ - range: 4
+ type: W
+ name: ENABLE
+ desc: Enable the DMA buffer on the server as a source of busy
+ default: 0
+ - range: 3
+ type: R
+ name: TOHOST_BUSY_LATCHED
+ desc: A tohost descriptor has passed BUSY_THRESHOLD_ASSERT in the past, busy flag was set
+ value: (others => tohost_busy_latched_40_s)
+ - range: 0
+ type: R
+ name: TOHOST_BUSY
+ desc: A tohost descriptor passed BUSY_THRESHOLD_ASSERT, busy flag set
+ value: (others => tohost_busy_40_s)
+
+ - name: FM_BUSY_CHANNEL_STATUS
+ type: W
+ bitfield:
+ - range: any
+ name: CLEAR_LATCH
+ type: T
+ value: 1
+ desc: Any write to this register will clear the BUSY_LATCHED bits
+ - range: 47..24
+ type: R
+ name: BUSY_LATCHED
+ desc: one Indicates that the given FULL mode channel has received BUSY-ON
+ - range: 23..0
+ type: R
+ name: BUSY
+ desc: one Indicates that the given FULL mode channel is currently in BUSY state
+
+ - name: BUSY_MAIN_OUTPUT_FIFO_THRESH
+ type: W
+ bitfield:
+ - range: 24
+ name: BUSY_ENABLE
+ desc: Enable busy generation if thresholds are crossed
+ default: 0
+ - range: 23..12
+ name: LOW
+ desc: Low, Negate threshold of busy generation from main output fifo
+ default: 0x3FF
+ - range: 11..0
+ name: HIGH
+ desc: High, Assert threshold of busy generation from main output fifo
+ default: 0x4FF
+
+ - name: BUSY_MAIN_OUTPUT_FIFO_STATUS
+ type: W
+ bitfield:
+ - range: any
+ name: CLEAR_LATCHED
+ value: 1
+ desc: Any write to this register will clear the
+ type: T
+ - range: 2
+ type: R
+ name: HIGH_THRESH_CROSSED_LATCHED
+ desc: Main output fifo has been full beyond HIGH THRESHOLD, write to clear
+ - range: 1
+ type: R
+ name: HIGH_THRESH_CROSSED
+ desc: Main output fifo is full beyond HIGH THRESHOLD
+ - range: 0
+ type: R
+ name: LOW_THRESH_CROSSED
+ desc: Main output fifo is full beyond LOW THRESHOLD
+ - ref: ELINK_BUSY_ENABLE
+ - ref: XOFF_STATISTICS
+
+
+ELINK_BUSY_ENABLE:
+ number: 24
+ endpoints: 0
+ type: W
+ entries:
+ - name: ELINK_BUSY_ENABLE
+ format_name: ELINK_BUSY_ENABLE{index:02}
+ type_name: ELINK_BUSY_ENABLE
+ desc: Per elink (and FULL mode link) enable of the busy signal towards the LEMO output
+ bitfield:
+ - range: 56..0
+ default: 0
+
+XOFF_STATISTICS:
+ number: 24
+ endpoints: 0,1
+ type: R
+ entries:
+ - name: XOFF_PEAK_DURATION
+ format_name: XOFF_PEAK_DURATION{index:02}
+ type_name: XOFF_PEAK_DURATION
+ desc: Maximum occurred duration of XOFF on the given channel in 25ns bins since reset
+ bitfield:
+ - range: 63..0
+ - name: XOFF_TOTAL_DURATION
+ format_name: XOFF_TOTAL_DURATION{index:02}
+ type_name: XOFF_TOTAL_DURATION
+ desc: Total occurred duration of XOFF on the given channel in 25ns bins, divide by number of Xoffs to calculate the average since reset
+ bitfield:
+ - range: 63..0
+ - name: XOFF_COUNT
+ format_name: XOFF_COUNT{index:02}
+ type_name: XOFF_COUNT
+ desc: Total number of XOFF events per channel that occurred since a reset.
+ bitfield:
+ - range: 63..0
+
+
+
+
+HouseKeepingControlsAndMonitors:
+ group: HKC
+ desc: House Keeping Controls and Monitors
+ endpoints: 0
+ entries:
+
+ - name: HK_CTRL_I2C
+ type: W
+ bitfield:
+ - range: 1
+ name: CONFIG_TRIG
+ desc: i2c_config_trig
+ - range: 0
+ name: CLKFREQ_SEL
+ desc: i2c_clkfreq_sel
+
+ - name: HK_CTRL_FMC
+ type: W
+ bitfield:
+ - range: 7
+ name: SI5345_LOL
+ type: R
+ desc: Loss of lock pin, only connected on FLX711
+ - range: 6..5
+ name: SI5345_INSEL
+ default: 0x0
+ desc: |
+ Selects the input clock source
+ 0 : FPGA (FMC LA01)
+ 1 : FMC OSC (40.079 MHz)
+ 2 : FPGA (FMC LA18)
+ - range: 4..3
+ name: SI5345_A
+ default: 0x0
+ desc: Si5345 I2C address select 2 LSB (0x0:default, dev id 0x68)
+ - range: 2
+ name: SI5345_OE
+ default: 0x1
+ desc: Si5345 active low output enable (0:enable)
+ - range: 1
+ name: SI5345_RSTN
+ default: 0x0
+ desc: Si5345 active low output enable (0:reset)
+ - range: 0
+ name: SI5345_SEL
+ default: 0x1
+ desc: |
+ Si5345 programming mode
+ 1 : I2C mode (default)
+ 0 : SPI mode
+
+ - name: HK_MON_FMC
+ type: W
+ bitfield:
+ - range: 1
+ name: SI5345_LOL
+ desc: Si5345 Loss Of Lock pin
+ - range: 0
+ name: SI5345_INTR
+ desc: Si5345 Interrupt flagging chip change of status
+
+ - name: MMCM_MAIN
+ type: W
+ offset: 0x0300
+ bitfield:
+ - range: 3
+ type: W
+ name: LCLK_SEL
+ default: 0x1
+ desc: |
+ 1: LCLK
+ 0: TTC
+ - range: 2..1
+ type: R
+ name: MAIN_INPUT
+ desc: |
+ Main MMCM Oscillator Input
+ 2: LCLK fixed
+ 1: TTC fixed
+ 0: selectable
+ - range: 0
+ type: R
+ name: PLL_LOCK
+ desc: Main MMCM PLL Lock Status
+
+ - name: LMK_LOCKED
+ type: R
+ bitfield:
+ - range: 0
+ desc: LMK Chip on BNL-711 locked
+
+ - name: FPGA_CORE_TEMP
+ type: R
+ bitfield:
+ - range: 11..0
+ desc: |
+ XADC temperature monitor for the FPGA CORE
+ for FLX709, FLX710
+ temp (C)= ((FPGA_CORE_TEMP* 503.975)/4096)-273.15
+ for FLX711
+ temp (C)= ((FPGA_CORE_TEMP* 502.9098)/4096)-273.8195
+ - name: FPGA_CORE_VCCINT
+ type: R
+ bitfield:
+ - range: 11..0
+ desc: XADC voltage measurement VCCINT = (FPGA_CORE_VCCINT *3.0)/4096
+ - name: FPGA_CORE_VCCAUX
+ type: R
+ bitfield:
+ - range: 11..0
+ desc: XADC voltage measurement VCCAUX = (FPGA_CORE_VCCAUX *3.0)/4096
+ - name: FPGA_CORE_VCCBRAM
+ type: R
+ bitfield:
+ - range: 11..0
+ desc: XADC voltage measurement VCCBRAM = (FPGA_CORE_VCCBRAM *3.0)/4096
+
+ - name: FPGA_DNA
+ type: R
+ bitfield:
+ - range: 63..0
+ desc: Unique identifier of the FPGA
+
+
+ #- name: SPI_WR
+ # type: W
+ # offset: 0x0400
+ # bitfield:
+ # - range: any
+ # type: T
+ # value: OBSOLETE not register_map_monitor_s.register_map_hk_monitor.SPI_WR.SPI_FULL
+ # name: SPI_WREN
+ # desc: Any write to this register triggers an SPI Write
+ # - range: 32
+ # type: R
+ # name: SPI_FULL
+ # desc: OBSOLETE SPI FIFO Full
+ # - range: 31..0
+ # type: W
+ # name: SPI_DIN
+ # desc: OBSOLETE SPI WRITE Data
+ #
+ #- name: SPI_RD
+ # type: T
+ # bitfield:
+ # - range: any
+ # type: T
+ # value: not register_map_monitor_s.register_map_hk_monitor.SPI_RD.SPI_EMPTY
+ # name: SPI_RDEN
+ # desc: OBSOLETE Any write to this register pops the last SPI data from the FIFO
+ # - range: 32
+ # type: R
+ # name: SPI_EMPTY
+ # desc: OBSOLETE SPI FIFO Empty
+ # - range: 31..0
+ # type: R
+ # name: SPI_DOUT
+ # desc: OBSOLETE SPI READ Data
+
+ - name: I2C_WR
+ type: W
+ offset: 0x420
+ bitfield:
+ - range: any
+ name: I2C_WREN
+ type: T
+ value: not register_map_monitor_s.register_map_hk_monitor.I2C_WR.I2C_FULL
+ desc: Any write to this register triggers an I2C read or write sequence
+ - range: 25
+ type: R
+ name: I2C_FULL
+ desc: I2C FIFO full
+ - range: 24
+ name: WRITE_2BYTES
+ type: W
+ desc: Write two bytes
+ - range: 23..16
+ name: DATA_BYTE2
+ type: W
+ desc: Data byte 2
+ - range: 15..8
+ name: DATA_BYTE1
+ type: W
+ desc: Data byte 1
+ - range: 7..1
+ name: SLAVE_ADDRESS
+ type: W
+ desc: Slave address
+ - range: 0
+ name: READ_NOT_WRITE
+ type: W
+ desc: READ/<o>WRITE</o>
+
+ - name: I2C_RD
+ type: T
+ bitfield:
+ - range: any
+ name: I2C_RDEN
+ type: T
+ value: not register_map_monitor_s.register_map_hk_monitor.I2C_RD.I2C_EMPTY
+ desc: Any write to this register pops the last I2C data from the FIFO
+ - range: 8
+ type: R
+ name: I2C_EMPTY
+ desc: I2C FIFO Empty
+ - range: 7..0
+ type: R
+ name: I2C_DOUT
+ desc: I2C READ Data
+
+
+ #- name: DEBUG_PORT_GBT
+ # offset: 0x0500
+ # type: W
+ # bitfield:
+ # - range: 6..0
+ # desc: OBSOLETE Debug GBT data bit N (119..0) on SMA HTGx#3
+
+ #- name: DEBUG_PORT_CLK
+ # type: W
+ # bitfield:
+ # - range: 3..0
+ # desc: OBSOLETE Debug clock and L1A port on SMA HTGx#4
+
+ - name: INT_TEST
+ offset: 0x0800
+ type: W
+ value: 1
+ bitfield:
+ - name: TRIGGER
+ type: T
+ range: any
+ desc: Fire a test MSIx interrupt set in IRQ
+ - name: IRQ
+ type: W
+ range: 3..0
+ desc: Set this field to a value equal to the MSIX interrupt to be fired. The write triggers the interrupt immediately.
+
+ - name: CONFIG_FLASH_WR
+ type: W
+ bitfield:
+ - range: 57
+ type: W
+ name: FAST_WRITE
+ desc: Write command only. Only used for fast programming.
+ - range: 56
+ type: W
+ name: FAST_READ
+ desc: Status reading without command writing. Only used for fast programming.
+ - range: 55
+ type: W
+ name: PAR_CTRL
+ desc: Choose use FW or uC to select the Flash partition. 1 FW | 0 uC.
+ - range: 54..53
+ type: W
+ name: PAR_WR
+ desc: Choose Flash partition. Valid when PAR_CTRL is 1.
+ - range: 52
+ type: W
+ name: FLASH_SEL
+ desc: 1 takes control over flash, 0 gives JTAG control over flash
+ - range: 51
+ type: W
+ name: DO_INIT
+ desc: Untested feature, don't use it yet.
+ - range: 50
+ type: W
+ name: DO_READSTATUS
+ desc: Reads status from flash
+ - range: 49
+ type: W
+ name: DO_CLEARSTATUS
+ desc: Clears status reading from flash, back to normal flash operation
+ - range: 48
+ type: W
+ name: DO_ERASEBLOCK
+ desc: Erased the current block of the flash, this register has to be cleared by software
+ - range: 47
+ name: DO_UNLOCK_BLOCK
+ type: W
+ desc: Unlock writes to the current block, this register has to be cleared by software
+ - range: 46
+ name: DO_READ
+ type: W
+ desc: Reads the 16 bits from current address, this register has to be cleared by software
+ - range: 45
+ name: DO_WRITE
+ type: W
+ desc: Writes the 16 bits to current address, this register has to be cleared by software
+ - range: 44
+ name: DO_READDEVICEID
+ type: W
+ desc: DIN should return 0x0089, this register has to be cleared by software
+ - range: 43
+ name: DO_RESET
+ type: W
+ desc: Can be used in the future, currently disconnected in firmware
+ - range: 42..16
+ name: ADDRESS
+ type: W
+ desc: Address for read and write operations (25 bits, upper 2 bits are controlled by uC)
+ - range: 15..0
+ name: WRITE_DATA
+ type: W
+ desc: Value of data to write towards flash
+ - name: CONFIG_FLASH_RD
+ type: R
+ bitfield:
+ - range: 19..18
+ name: PAR_RD
+ type: R
+ desc: Show which Flash partition is selected.
+ - range: 17
+ name: FLASH_REQ_DONE
+ type: R
+ desc: Request done
+ - range: 16
+ name: FLASH_BUSY
+ type: R
+ desc: Flash operation busy
+ - range: 15..0
+ name: READ_DATA
+ type: R
+ desc: Value of data read from flash
+ - name: SI5324_STATUS
+ type: R
+ bitfield:
+ - range: 15..8
+ name: LOL
+ desc: Loss of Lock Si5324
+ - range: 8..0
+ name: LOS
+ desc: Loss of Signal Si5324
+
+ - name: TACH_CNT
+ type: R
+ desc: Readout of the Fan tachometer speed of the BNL712 board
+ bitfield:
+ - range: 19..0
+
+ - name: RXUSRCLK_FREQ
+ type: W
+ bitfield:
+ - range: 38
+ name: VALID
+ type: R
+ desc: Indicates that the frequency measurement is valid
+ - range: 37..32
+ name: CHANNEL
+ type: W
+ desc: Select the Transceiver channel to measure the clock from.
+ - range: 31..0
+ name: VAL
+ type: R
+ desc: Frequency in Hz of the selected channel
+
+
+Generators:
+ group: GEN
+ desc: Specific registers for Hardware based Generators
+ endpoints: 0
+ generate: EMU_GENERATE_REGS
+ entries:
+ - name: FELIG_L1ID_RESET
+ type: W
+ desc: Any write to this register clears the FELIG L1ID
+ bitfield:
+ - range: any
+ type: T
+ value: 1
+ - ref: FELIG_DATA_GEN_CONFIG_ARR
+ offset: 0x20
+ - ref: FELIG_ELINK_CONFIG_ARR
+ - ref: FELIG_ELINK_ENABLE_ARR
+
+ - name: FELIG_GLOBAL_CONTROL
+ type: W
+ bitfield:
+ - range: 63..36
+ name: FAKE_L1A_RATE
+ default: 0
+ desc: Sets the internal fake L1 trigger rate. [25ns/LSB]
+ - range: 35..14
+ name: PICXO_OFFSET_PPM
+ default: 0
+ desc: When OFFSET_EN is 1, this directly sets the output frequency, within the given adjustment range.
+ - range: 12..12
+ name: TRACK_DATA
+ default: 0
+ desc: FELIG GT core control. Must be set to enable normal operation.
+ - range: 11..11
+ name: RXUSERRDY
+ default: 0
+ desc: FELIG GT core control. Must be set to enable normal operation.
+ - range: 10..10
+ name: TXUSERRDY
+ default: 0
+ desc: FELIG GT core control. Must be set to enable normal operation.
+ - range: 9..9
+ name: AUTO_RESET
+ default: 0
+ desc: FELIG GT core control. If set the GT core automatically resets on data error.
+ - range: 8..8
+ name: PICXO_RESET
+ default: 0
+ desc: FELIG GT core control. Manual PICXO reset.
+ - range: 7..7
+ name: GTTX_RESET
+ default: 0
+ desc: FELIG GT core control. Manual GT TX reset
+ - range: 6..6
+ name: CPLL_RESET
+ default: 0
+ desc: FELIG GT core control. Manual CPLL reset.
+ - range: 5..0
+ name: X3_X4_OUTPUT_SELECT
+ default: 0
+ desc: X3/X4 SMA output source select.
+
+ - ref: FELIG_LANE_CONFIG_ARR
+ - ref: FELIG_MON_TTC_0_ARR
+ - ref: FELIG_MON_TTC_1_ARR
+ - ref: FELIG_MON_COUNTERS_ARR
+ - ref: FELIG_MON_FREQ_ARR
+
+ - name: FELIG_MON_FREQ_GLOBAL
+ type: W
+ bitfield:
+ - range: 63..32
+ name: XTAL_100MHZ
+ default: 0
+ desc: FELIG local oscillator frequency[Hz].
+ - range: 31..0
+ name: CLK_41_667MHZ
+ desc: FELIG PCIE MGTREFCLK frequency[Hz].
+
+ - ref: FELIG_MON_L1A_ID_ARR
+ - ref: FELIG_MON_PICXO_ARR
+
+ - name: FELIG_RESET
+ type: W
+ bitfield:
+ - range: 63..48
+ name: LB_FIFO
+ default: 0
+ desc: One bit per lane. When set to 1, resets all loopback FIFOs.
+ - range: 47..24
+ name: FRAMEGEN
+ default: 0
+ desc: One bit per lane. When set to 1, resets all FELIG link checking logic.
+ - range: 23..0
+ name: LANE
+ default: 0
+ desc: One bit per lane. When set to 1, resets all FELIG lane logic.
+
+ - name: FELIG_RX_SLIDE_RESET
+ type: W
+ bitfield:
+ - range: 23..0
+ default: 0
+ desc: One bit per lane. When set to 1, resets the gbt rx slide counter.
+
+ - ref: FELIG_ITK_STRIPS_DATA_GEN_CONFIG_ARR
+ - ref: FELIG_MON_ITK_STRIPS_ARR
+
+ - name: FMEMU_EVENT_INFO
+ type: R
+ offset: 0x1800
+ bitfield:
+ - range: 63..32
+ name: L1ID
+ default: 0
+ desc: 32b field to show L1ID
+ - range: 31..0
+ name: BCID
+ default: 0
+ desc: 32b field to show BCID
+
+ - name: FMEMU_COUNTERS
+ type: W
+ bitfield:
+ - range: 63..48
+ name: WORD_CNT
+ default: 32
+ desc: Number of 32b words in one chunk
+ - range: 47..32
+ name: IDLE_CNT
+ default: 3
+ desc: Minimum number of idles between chunks
+ - range: 31..16
+ name: L1A_CNT
+ default: 256
+ desc: Number of chunks to send if not in TTC mode
+ - range: 15..8
+ name: BUSY_TH_HIGH
+ default: 20
+ desc: Assert BUSY-ON above this threshold
+ - range: 7..0
+ name: BUSY_TH_LOW
+ default: 15
+ desc: De-assert BUSY-ON below this threshold
+
+ - name: FMEMU_CONTROL
+ type: W
+ bitfield:
+ - range: 63..56
+ type: W
+ name: L1A_BITNR
+ default: 48
+ desc: Bitfield for L1A in TTC frame
+ - range: 55..48
+ type: W
+ name: XONXOFF_BITNR
+ default: 32
+ desc: Bitfield for Xon/Xoff in TTC frame
+ - range: 47..47
+ type: W
+ name: EMU_START
+ default: 0
+ desc: Start emulator functionality
+ - range: 46..46
+ type: W
+ name: TTC_MODE
+ default: 0
+ desc: Control the emulator by TTC input or by RegMap (1/0)
+ - range: 45..45
+ type: W
+ name: XONXOFF
+ default: 1
+ desc: Enable Xon/Xoff functionality (1/0)
+ - range: 44..44
+ type: W
+ name: INLC_CRC32
+ default: 0
+ desc: |
+ 0: No checksum
+ 1: Append the data with a CRC32
+ - range: 43..43
+ type: W
+ name: BCR
+ default: 0
+ desc: Reset BCID to 0
+ - range: 42..42
+ type: W
+ name: ECR
+ default: 0
+ desc: Reset L1ID to 0
+ - range: 41..41
+ type: W
+ name: CONSTANT_CHUNK_LENGTH
+ default: 0
+ desc: |
+ Data source select
+ 0: Random chunk length
+ 1: Constant chunk length
+ - range: 40..32
+ type: R
+ name: INT_STATUS_EMU
+ default: 0
+ desc: Read internal status emulator
+ - range: 16
+ type: W
+ name: FFU_FM_EMU_T
+ default: 0
+ desc: For Future Use (trigger registers)
+ - range: 0
+ type: W
+ name: FE_BUSY_ENABLE
+ default: 1
+ desc: Enable the BUSY mechanism if L1A counter passes threshold
+
+ - name: FMEMU_RANDOM_RAM_ADDR
+ type: W
+ desc: Controls the address of the ramblock for the random number generator
+ bitfield:
+ - range: 9..0
+ - name: FMEMU_RANDOM_RAM
+ type: W
+ bitfield:
+ - range: any
+ type: T
+ name: WE
+ value: 1
+ desc: Any write to this register (DATA) triggers a write to the ramblock
+ - range: 39..16
+ name: CHANNEL_SELECT
+ value: 0xFFFFFF
+ desc: Enable write enable only for the selected channel
+ - range: 15..0
+ name: DATA
+ type: W
+ desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
+ - name: FMEMU_RANDOM_CONTROL
+ type: W
+ desc: Controls the random chunk length generator
+ bitfield:
+ - name: SELECT_RANDOM
+ range: 20
+ desc: 1 enables the random chunk length, 0 uses a constant chunk length
+ default: 0
+ - name: SEED
+ range: 19..10
+ desc: Seed for the random number generator, should not be 0
+ default: 0x200
+ - name: POLYNOMIAL
+ range: 9..0
+ desc: POLYNOMIAL for the random number generator (10b LFSR) Bit9 should always be 1
+ default: 0x240
+
+ - name: FMEMU_CONFIG_WRADDR
+ type: W
+ bitfield:
+ - range: 9..0
+ value: 0
+ desc: write enable for the FMEmu ram block
+
+ - name: FMEMU_CONFIG
+ type: W
+ bitfield:
+ - range: any
+ type: T
+ name: WE
+ value: 1
+ desc: Any write to register WRDATA triggers a write to the ramblock
+ - range: 55..32
+ name: CHANNEL_SELECT
+ value: 0xFFFFFF
+ desc: Enable write enable only for the selected channel
+ - range: 31..0
+ name: WRDATA
+ type: W
+ desc: DATA field to be written to FMEMU_RANDOM_RAM_ADDR
+
+
+#Registers that are replicated 24 times under Generators:
+FELIG_DATA_GEN_CONFIG_ARR:
+ number: 24
+ type: W
+ entries:
+ - name: FELIG_DATA_GEN_CONFIG
+ format_name: FELIG_DATA_GEN_CONFIG_{index:02}
+ type_name: FELIG_DATA_GEN_CONFIG
+ desc: FELIG specific configuration test registers
+ bitfield:
+ - name: USERDATA
+ range: 63..48
+ default: 0
+ desc: Sets static payload word. When PATTERN_SEL=1.
+ - name: CHUNK_LENGTH
+ range: 47..32
+ default: 0
+ desc: FELIG data generator chunk-length in bytes.
+ - name: RESET
+ range: 19..15
+ default: 0
+ desc: FELIG data generator reset. One bit per group, 0:normal operation, 1:egroup emulation held in reset.
+ - name: SW_BUSY
+ range: 14..10
+ default: 0
+ desc: FELIG elink bus state. One bit per group, 0:normal operation, 1:elink enter busy state.
+ - name: DATA_FORMAT
+ range: 9..5
+ default: 0
+ desc: FELIG data generator format. 0:8b10b, 1:direct.
+ - name: PATTERN_SEL
+ range: 4..0
+ default: 0
+ desc: FELIG data payload type. One bit per group, 0:byte counter, 1:USERDATA
+
+FELIG_ELINK_CONFIG_ARR:
+ number: 24
+ type: W
+ entries:
+ - name: FELIG_ELINK_CONFIG
+ format_name: FELIG_ELINK_CONFIG_{index:02}
+ type_name: FELIG_ELINK_CONFIG
+ desc: FELIG specific configuration test registers
+ bitfield:
+ - name: ENDIAN_MOD
+ range: 39..35
+ default: 0
+ desc: FELIG elink data input endian control. One bit per egroup. 0:little-endian (8b10b), 1:big-endian.
+ - name: INPUT_WIDTH
+ range: 34..30
+ default: 0
+ desc: FELIG elink data input width. One bit per egroup. 0:8-bit (direct), 1:10-bit (8b10b).
+ - name: OUTPUT_WIDTH
+ range: 9..0
+ default: 0
+ desc: FELIG elink data output width.
+
+FELIG_ELINK_ENABLE_ARR:
+ number: 24
+ type: W
+ entries:
+ - name: FELIG_ELINK_ENABLE
+ format_name: FELIG_ELINK_ENABLE_{index:02}
+ type_name: FELIG_ELINK_ENABLE
+ desc: FELIG specific configuration registers
+ bitfield:
+ - range: 39..0
+ default: 0
+ desc: FELIG elink enable. One bit per elink. 0:disabled, 1:enabled.
+
+FELIG_LANE_CONFIG_ARR:
+ number: 24
+ type: W
+ entries:
+ - name: FELIG_LANE_CONFIG
+ format_name: FELIG_LANE_CONFIG_{index:02}
+ type_name: FELIG_LANE_CONFIG
+ desc: FELIG specific configuration registers
+ bitfield:
+ - name: B_CH_BIT_SEL
+ range: 63..42
+ default: 0
+ desc: When OFFSET_EN is 1. this directly sets the output frequency. within the given adjustment range.
+ - name: A_CH_BIT_SEL
+ range: 41..35
+ default: 0
+ desc: Selects the bit from the received FELIX data from which to extract the L1A.
+ - name: LB_FIFO_DELAY
+ range: 34..30
+ default: 0
+ desc: When the GTH or GTB loopback is enabled, this controls the loopback latency in clock cycles.
+ - name: ELINK_SYNC
+ range: 7..7
+ default: 0
+ desc: When set, synchronizes the elink word boundaries. Must be set back to 0 to resume normal operation.
+ - name: PICXO_OFFEST_EN
+ range: 6..6
+ default: 0
+ desc: FELIG TX frequency override. 0:frequency tracking enabled, 1:TX frequency set by PICXO_OFFSET_PPM.
+ - name: PI_HOLD
+ range: 5..5
+ default: 0
+ desc: FELIG phase-interpolator hold. 0:frequency tracking enabled, 1:freeze TX frequency.
+ - name: GBT_LB_ENABLE
+ range: 4..4
+ default: 0
+ desc: FELIG GBT direct loopback enable. 0:disabled, 1:enabled.
+ - name: GBH_LB_ENABLE
+ range: 3..3
+ default: 0
+ desc: FELIG GTH direct loopback enable. 0:disabled, 1:enabled.
+ - name: L1A_SOURCE
+ range: 2..2
+ default: 0
+ desc: FELIG L1A data source select. 0:from local counter, 1:from FELIX.
+ - name: GBT_EMU_SOURCE
+ range: 1..1
+ default: 0
+ desc: FELIG emulation data source select. 0:state-machine emulator, 1:ram-based emulator.
+ - name: FG_SOURCE
+ range: 0..0
+ default: 0
+ desc: FELIG link check data source selection control. 0:normal operation, 1:PRBS link checker (not elink emulation data)
+
+FELIG_MON_TTC_0_ARR:
+ number: 24
+ type: R
+ entries:
+ - name: FELIG_MON_TTC_0
+ format_name: FELIG_MON_TTC_0_{index:02}
+ type_name: FELIG_MON_TTC_0
+ desc: FELIG specific configuration registers
+ bitfield:
+ - name: L1ID
+ range: 63..40
+ default: 0
+ desc: Live TTC data monitor.
+ - name: XL1ID
+ range: 39..32
+ default: 0
+ desc: Live TTC data monitor.
+ - name: BCID
+ range: 31..20
+ default: 0
+ desc: Live TTC data monitor.
+ - name: RESERVED0
+ range: 19..16
+ default: 0
+ desc: Live TTC data monitor.
+ - name: LEN
+ range: 15..8
+ default: 0
+ desc: Live TTC data monitor.
+ - name: FMT
+ range: 7..0
+ default: 0
+ desc: Live TTC data monitor.
+
+FELIG_MON_TTC_1_ARR:
+ number: 24
+ type: R
+ entries:
+ - name: FELIG_MON_TTC_1
+ format_name: FELIG_MON_TTC_1_{index:02}
+ type_name: FELIG_MON_TTC_1
+ desc: FELIG specific configuration registers
+ bitfield:
+ - name: RESERVED1
+ range: 63..48
+ default: 0
+ desc: Live TTC data monitor.
+ - name: TRIGGER_TYPE
+ range: 47..32
+ default: 0
+ desc: Live TTC data monitor.
+ - name: ORBIT
+ range: 31..0
+ default: 0
+ desc: Live TTC data monitor.
+
+FELIG_MON_COUNTERS_ARR:
+ number: 24
+ type: R
+ entries:
+ - name: FELIG_MON_COUNTERS
+ format_name: FELIG_MON_COUNTERS_{index:02}
+ type_name: FELIG_MON_COUNTERS
+ desc: FELIG specific configuration registers
+ bitfield:
+ - name: SLIDE_COUNT
+ range: 63..32
+ default: 0
+ desc: Counts the number of rx slides commanded by the GBT logic. Should be static once a link is established.
+ - name: FC_ERROR_COUNT
+ range: 31..0
+ default:
+ desc: When FG_DATA_SELECT is 1, this counter reports the number of detected data errors.
+
+FELIG_MON_FREQ_ARR:
+ number: 24
+ type: R
+ entries:
+ - name: FELIG_MON_FREQ
+ format_name: FELIG_MON_FREQ_{index:02}
+ type_name: FELIG_MON_FREQ
+ desc: FELIG specific configuration registers
+ bitfield:
+ - name: TX
+ range: 63..32
+ default: 0
+ desc: FELIG regenerated TX clock frequency[Hz].
+ - name: RX
+ range: 31..0
+ default: 0
+ desc: FELIG recovered RX clock frequency[Hz].
+
+FELIG_MON_L1A_ID_ARR:
+ number: 24
+ type: R
+ entries:
+ - name: FELIG_MON_L1A_ID
+ format_name: FELIG_MON_L1A_ID_{index:02}
+ type_name: FELIG_MON_L1A_ID
+ desc: FELIG specific configuration registers
+ bitfield:
+ - range: 31..0
+ default: 0
+ desc: FELIG's last L1 ID.
+
+FELIG_MON_PICXO_ARR:
+ number: 24
+ type: R
+ entries:
+ - name: FELIG_MON_PICXO
+ format_name: FELIG_MON_PICXO_{index:02}
+ type_name: FELIG_MON_PICXO
+ desc: FELIG specific configuration registers
+ bitfield:
+ - name: VLOT
+ range: 53..32
+ default: 0
+ desc: Value indicates TX clock (recovered RX clock) to RX reference clock frequency offset.
+ - name: ERROR
+ range: 20..0
+ default: 0
+ desc: Value indicates RX to TX frequency tracking error.
+
+FELIG_ITK_STRIPS_DATA_GEN_CONFIG_ARR:
+ number: 24
+ type: W
+ entries:
+ - name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG
+ format_name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG_{index:02}
+ type_name: FELIG_ITK_STRIPS_DATA_GEN_CONFIG
+ desc: ITk Strips emulator specific configuration test registers
+ bitfield:
+ - name: ITKS_FIFO_CTL
+ range: 19..17
+ default: 0
+ desc: data fifo control 2:rst 1:rd 0:wr.
+ - name: ITKS_FIFO_DATA
+ range: 16..0
+ default: 0
+ desc: itks emu data 16:last word 15-0:data word
+
+FELIG_MON_ITK_STRIPS_ARR:
+ number: 24
+ type: R
+ entries:
+ - name: FELIG_MON_ITK_STRIPS
+ format_name: FELIG_MON_ITK_STRIPS_{index:02}
+ type_name: FELIG_MON_ITK_STRIPS
+ desc: ITk Strips emulator specific status registers
+ bitfield:
+ - name: ITKS_FIFO_STATUS
+ range: 2..0
+ default: 0
+ desc: data fifo status 2:write done 1:full 0:empty.
+
+
+
+Wishbone:
+ desc: Wishbone
+ endpoints: 0
+ entries:
+ - name: WISHBONE_CONTROL
+ type: W
+ bitfield:
+ - range: 32
+ name: WRITE_NOT_READ
+ desc: wishbone write command wishbone read command
+ - range: 31..0
+ name: ADDRESS
+ desc: Slave address for Wishbone bus
+ - name: WISHBONE_WRITE
+ type: T
+ bitfield:
+ - range: any
+ type: T
+ value: 1
+ name: WRITE_ENABLE
+ desc: Any write to this register triggers a write to the Wupper to Wishbone fifo
+ - range: 32
+ name: FULL
+ type: R
+ - range: 31..0
+ name: DATA
+ type: W
+ - name: WISHBONE_READ
+ type: T
+ bitfield:
+ - range: any
+ type: T
+ value: 1
+ name: READ_ENABLE
+ desc: Any write to this register triggers a read from the Wishbone to Wupper fifo
+ - range: 32
+ name: EMPTY
+ type: R
+ desc: Indicates that the Wishbone to Wupper fifo is empty
+ - range: 31..0
+ name: DATA
+ type: R
+ desc: Wishbone read data
+ - name: WISHBONE_STATUS
+ type: R
+ bitfield:
+ - range: 4
+ name: INT
+ desc: interrupt
+ - range: 3
+ name: RETRY
+ desc: Interface is not ready to accept data cycle should be retried
+ - range: 2
+ name: STALL
+ desc: When pipelined mode slave can't accept additional transactions in its queue
+ - range: 1
+ name: ACKNOWLEDGE
+ desc: Indicates the termination of a normal bus cycle
+ - range: 0
+ name: ERROR
+ desc: Address not mapped by the crossbar
+
+MRODregisters:
+ group: MROD_CONTROL
+ desc: Specific registers for MROD
+ endpoints: 0
+ generate: MROD_GENERATE_REGS
+ entries:
+ - name: MROD_CTRL
+ type: W
+ bitfield:
+ - range: 15..8
+ name: OPTIONS
+ default: 0
+ desc: Extra options for MROD
+ - range: 7..7
+ name: ENASPARE1
+ default: 0
+ desc: Enable spare1
+ - range: 6..6
+ name: ENAMANSLIDE
+ default: 0
+ desc: Enable Manual Slide in Rx Locking
+ - range: 5..5
+ name: ENAPASSALL
+ default: 0
+ desc: Enable PassAll in EmptySuppress
+ - range: 4..4
+ name: ENATXCOUNT
+ default: 0
+ desc: Enable SimpleCount in TxDriver for locking
+ - range: 3..0
+ name: GOLTESTMODE
+ default: 0
+ desc: |
+ GOL Test Mode (emulate CSM):
+ 0: Run Data Emulator when 1; 0: stop, load emulator fifo
+ 1: Enable Circulate when 1; 0: send fifo data only once
+ 2: Enable Triggered Mode when 1; 0: run continueously (no TTC)
+ 3: Enable pattern generator
+ - name: MROD_TCVRCTRL
+ type: W
+ bitfield:
+ - range: 23..16
+ name: SLIDEMAX
+ default: 0xFF
+ desc: Maximum RXSLIDES before fire a TCVR reset
+ - range: 15..8
+ name: SLIDEWAIT
+ default: 32
+ desc: RXclk delay in TCVR for next RX_SLIDE operation
+ - range: 7..0
+ name: FRAMESIZE
+ default: 20
+ desc: Number of 32 data words in 1 frame
+ - name: MROD_EP0_CSMENABLE
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP0 CSM Data Enable channel 23-0
+ default: 0
+ - name: MROD_EP0_EMPTYSUPPR
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP0 Set Empty Suppression channel 23-0
+ default: 0
+ - name: MROD_EP0_HPTDCMODE
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP0 Set HPTDC Mode channel 23-0
+ default: 0
+ - name: MROD_EP0_CLRFIFOS
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP0 Clear FIFOs channel 23-0
+ default: 0
+ - name: MROD_EP0_EMULOADENA
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP0 Emulator Load Enable channel 23-0
+ default: 0
+ - name: MROD_EP0_TRXLOOPBACK
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP0 Transceiver Loopback Enable channel 23-0
+ default: 0
+ - name: MROD_EP0_TXCVRRESET
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP0 Transceiver Reset all channel 23-0
+ default: 0
+ - name: MROD_EP0_RXRESET
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP0 Receiver Reset channel 23-0
+ default: 0
+ - name: MROD_EP0_TXRESET
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP0 Transmitter Reset channel 23-0
+ default: 0
+ - name: MROD_EP1_CSMENABLE
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP1 CSM Data Enable channel 23-0
+ default: 0
+ - name: MROD_EP1_EMPTYSUPPR
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP1 Set Empty Suppression channel 23-0
+ default: 0
+ - name: MROD_EP1_HPTDCMODE
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP1 Set HPTDC Mode channel 23-0
+ default: 0
+ - name: MROD_EP1_CLRFIFOS
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP1 Clear FIFOs channel 23-0
+ default: 0
+ - name: MROD_EP1_EMULOADENA
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP1 Emulator Load Enable channel 23-0
+ default: 0
+ - name: MROD_EP1_TRXLOOPBACK
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP1 Transceiver Loopback Enable channel 23-0
+ default: 0
+ - name: MROD_EP1_TXCVRRESET
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP1 Transceiver Reset all channel 23-0
+ default: 0
+ - name: MROD_EP1_RXRESET
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP1 Receiver Reset channel 23-0
+ default: 0
+ - name: MROD_EP1_TXRESET
+ type: W
+ bitfield:
+ - range: 23..0
+ desc: EP1 Transmitter Reset channel 23-0
+ default: 0
+
+MRODmonitors:
+ group: MROD_MONITOR
+ desc: Specific registers for MROD
+ endpoints: 0
+ generate: MROD_GENERATE_REGS
+ entries:
+ - name: MROD_EP0_CSMH_EMPTY
+ type: R
+ bitfield:
+ - range: 23..0
+ desc: EP0 CSM Handler FIFO Empty 23-0
+ - name: MROD_EP0_CSMH_FULL
+ type: R
+ bitfield:
+ - range: 23..0
+ desc: EP0 CSM Handler FIFO Full 23-0
+ - name: MROD_EP0_RXALIGNBSY
+ type: R
+ bitfield:
+ - range: 23..0
+ desc: EP0 Receiver Aligned monitor 23-0
+ - name: MROD_EP0_RXRECDATA
+ type: R
+ bitfield:
+ - range: 23..0
+ desc: EP0 Receiver Data monitor 23-0
+ - name: MROD_EP0_RXRECIDLES
+ type: R
+ bitfield:
+ - range: 23..0
+ desc: EP0 Receiver Idle monitor 23-0
+ - name: MROD_EP0_TXLOCKED
+ type: R
+ bitfield:
+ - range: 23..0
+ desc: EP0 Transmitter Locked monitor 23-0
+ - name: MROD_EP1_CSMH_EMPTY
+ type: R
+ bitfield:
+ - range: 23..0
+ desc: EP1 CSM Handler FIFO Empty 23-0
+ - name: MROD_EP1_CSMH_FULL
+ type: R
+ bitfield:
+ - range: 23..0
+ desc: EP1 CSM Handler FIFO Full 23-0
+ - name: MROD_EP1_RXALIGNBSY
+ type: R
+ bitfield:
+ - range: 23..0
+ desc: EP1 Receiver Aligned monitor 23-0
+ - name: MROD_EP1_RXRECDATA
+ type: R
+ bitfield:
+ - range: 23..0
+ desc: EP1 Receiver Data monitor 23-0
+ - name: MROD_EP1_RXRECIDLES
+ type: R
+ bitfield:
+ - range: 23..0
+ desc: EP1 Receiver Idle monitor 23-0
+ - name: MROD_EP1_TXLOCKED
+ type: R
+ bitfield:
+ - range: 23..0
+ desc: EP1 Transmitter Locked monitor 23-0
+
+#
diff --git a/sources/templates/strips_config_package.vhd b/sources/templates/strips_config_package.vhd
index b4c965a6b..9289f4126 100644
--- a/sources/templates/strips_config_package.vhd
+++ b/sources/templates/strips_config_package.vhd
@@ -27,11 +27,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../sources/templates/strips_config_package.vhd.template'
--- and register map ../../sources/templates/registers-4.10.yaml, version 4.10
+-- and register map ../../sources/templates/registers-4.11.yaml, version 4.11
-- by the script 'wuppercodegen', version: 0.8.4,
-- using the following commandline:
--
--- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.10.yaml ../../sources/templates/strips_config_package.vhd.template ../../sources/templates/strips_config_package.vhd
+-- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.11.yaml ../../sources/templates/strips_config_package.vhd.template ../../sources/templates/strips_config_package.vhd
--
-- Please do NOT edit this file, but edit the source file at '../../sources/templates/strips_config_package.vhd.template'
--
diff --git a/sources/templates/strips_phase1_long_stave_mapping.vhd b/sources/templates/strips_phase1_long_stave_mapping.vhd
index 790e41bca..65f7e976e 100644
--- a/sources/templates/strips_phase1_long_stave_mapping.vhd
+++ b/sources/templates/strips_phase1_long_stave_mapping.vhd
@@ -27,11 +27,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../sources/templates/strips_phase1_long_stave_mapping.vhd.template'
--- and register map ../../sources/templates/registers-4.10.yaml, version 4.10
+-- and register map ../../sources/templates/registers-4.11.yaml, version 4.11
-- by the script 'wuppercodegen', version: 0.8.4,
-- using the following commandline:
--
--- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.10.yaml ../../sources/templates/strips_phase1_long_stave_mapping.vhd.template ../../sources/templates/strips_phase1_long_stave_mapping.vhd
+-- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.11.yaml ../../sources/templates/strips_phase1_long_stave_mapping.vhd.template ../../sources/templates/strips_phase1_long_stave_mapping.vhd
--
-- Please do NOT edit this file, but edit the source file at '../../sources/templates/strips_phase1_long_stave_mapping.vhd.template'
--
diff --git a/sources/templates/strips_phase1_unknown_mapping.vhd b/sources/templates/strips_phase1_unknown_mapping.vhd
index abbd3f32c..20af3aa4f 100644
--- a/sources/templates/strips_phase1_unknown_mapping.vhd
+++ b/sources/templates/strips_phase1_unknown_mapping.vhd
@@ -27,11 +27,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../sources/templates/strips_phase1_unknown_mapping.vhd.template'
--- and register map ../../sources/templates/registers-4.10.yaml, version 4.10
+-- and register map ../../sources/templates/registers-4.11.yaml, version 4.11
-- by the script 'wuppercodegen', version: 0.8.4,
-- using the following commandline:
--
--- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.10.yaml ../../sources/templates/strips_phase1_unknown_mapping.vhd.template ../../sources/templates/strips_phase1_unknown_mapping.vhd
+-- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.11.yaml ../../sources/templates/strips_phase1_unknown_mapping.vhd.template ../../sources/templates/strips_phase1_unknown_mapping.vhd
--
-- Please do NOT edit this file, but edit the source file at '../../sources/templates/strips_phase1_unknown_mapping.vhd.template'
--
diff --git a/sources/templates/wupper.vhd b/sources/templates/wupper.vhd
index b414fb252..0e33e6c3a 100644
--- a/sources/templates/wupper.vhd
+++ b/sources/templates/wupper.vhd
@@ -30,11 +30,11 @@
-- DO NOT EDIT THIS FILE
--
-- This file was generated from template '../../sources/templates/wupper.vhd.template'
--- and register map ../../sources/templates/registers-4.10.yaml, version 4.10
+-- and register map ../../sources/templates/registers-4.11.yaml, version 4.11
-- by the script 'wuppercodegen', version: 0.8.4,
-- using the following commandline:
--
--- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.10.yaml ../../sources/templates/wupper.vhd.template ../../sources/templates/wupper.vhd
+-- ../../../software/wuppercodegen/wuppercodegen/cli.py ../../sources/templates/registers-4.11.yaml ../../sources/templates/wupper.vhd.template ../../sources/templates/wupper.vhd
--
-- Please do NOT edit this file, but edit the source file at '../../sources/templates/wupper.vhd.template'
--
--
GitLab