From c47a49e1e13a2edc3ba54835f95d62e8b306a2bc Mon Sep 17 00:00:00 2001
From: Ricardo Luz <ricardo.luz@cern.ch>
Date: Wed, 24 Jul 2024 10:42:35 -0500
Subject: [PATCH] FLXUSERS-594 added timing contraints to fix timing shift
---
constraints/pblocks_KCU_BNL711_v2.0_48ch.xdc | 89 +-
constraints/timing_constraints_ku.xdc | 2 +-
scripts/filesets/gbt_core_fileset.tcl | 1 +
.../GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd | 22 +-
sources/GBT/gbt_code/gbtTxRx_FELIX.vhd | 9 +-
sources/GBT/gbt_code/gbtTx_FELIX.vhd | 12 +-
.../GBT/gbt_code/gbt_tx_scrambler_FELIX.vhd | 267 +-
.../gbt_tx_timedomaincrossing_FELIX.vhd | 7 +-
.../ip_cores/kintexUltrascale/ila_LTDB.xci | 3252 +++++++++++++++++
9 files changed, 3498 insertions(+), 163 deletions(-)
create mode 100644 sources/ip_cores/kintexUltrascale/ila_LTDB.xci
diff --git a/constraints/pblocks_KCU_BNL711_v2.0_48ch.xdc b/constraints/pblocks_KCU_BNL711_v2.0_48ch.xdc
index 7371d9a9c..47e7bef53 100644
--- a/constraints/pblocks_KCU_BNL711_v2.0_48ch.xdc
+++ b/constraints/pblocks_KCU_BNL711_v2.0_48ch.xdc
@@ -12,29 +12,78 @@
#resize_pblock [get_pblocks pblock_0] -add {CLOCKREGION_X0Y0:CLOCKREGION_X5Y4}
-create_pblock pblock_1
-add_cells_to_pblock [get_pblocks pblock_1] [get_cells -quiet [list cr1 pcie1 fromHostFifo1 toHostFifo1]]
-add_cells_to_pblock pblock_1 [get_cells [list {g1.u2/CPLL_GEN.GTH_inst[24].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[25].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[26].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[27].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[28].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[29].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[30].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[31].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[32].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[33].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[34].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[35].GTH_TOP_INST}]]
-add_cells_to_pblock pblock_1 [get_cells [list {g1.u2/CPLL_GEN.GTH_inst[36].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[37].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[38].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[39].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[40].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[41].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[42].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[43].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[44].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[45].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[46].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[47].GTH_TOP_INST}]]
+#create_pblock pblock_1
+#add_cells_to_pblock [get_pblocks pblock_1] [get_cells -quiet [list cr1 pcie1 fromHostFifo1 toHostFifo1]]
+#add_cells_to_pblock pblock_1 [get_cells [list {g1.u2/CPLL_GEN.GTH_inst[24].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[25].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[26].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[27].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[28].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[29].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[30].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[31].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[32].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[33].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[34].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[35].GTH_TOP_INST}]]
+#add_cells_to_pblock pblock_1 [get_cells [list {g1.u2/CPLL_GEN.GTH_inst[36].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[37].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[38].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[39].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[40].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[41].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[42].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[43].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[44].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[45].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[46].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[47].GTH_TOP_INST}]]
-add_cells_to_pblock pblock_1 [get_cells [list {g1.u2/gbtRxTx[24].fifo_inst} {g1.u2/gbtRxTx[24].gbtTxRx_inst} {g1.u2/gbtRxTx[25].fifo_inst} {g1.u2/gbtRxTx[25].gbtTxRx_inst} {g1.u2/gbtRxTx[26].fifo_inst} {g1.u2/gbtRxTx[26].gbtTxRx_inst} {g1.u2/gbtRxTx[27].fifo_inst} {g1.u2/gbtRxTx[27].gbtTxRx_inst} {g1.u2/gbtRxTx[28].fifo_inst} {g1.u2/gbtRxTx[28].gbtTxRx_inst} {g1.u2/gbtRxTx[29].fifo_inst} {g1.u2/gbtRxTx[29].gbtTxRx_inst} {g1.u2/gbtRxTx[30].fifo_inst} {g1.u2/gbtRxTx[30].gbtTxRx_inst} {g1.u2/gbtRxTx[31].fifo_inst} {g1.u2/gbtRxTx[31].gbtTxRx_inst} {g1.u2/gbtRxTx[32].fifo_inst} {g1.u2/gbtRxTx[32].gbtTxRx_inst} {g1.u2/gbtRxTx[33].fifo_inst} {g1.u2/gbtRxTx[33].gbtTxRx_inst} {g1.u2/gbtRxTx[34].fifo_inst} {g1.u2/gbtRxTx[34].gbtTxRx_inst} {g1.u2/gbtRxTx[35].fifo_inst} {g1.u2/gbtRxTx[35].gbtTxRx_inst}]]
-add_cells_to_pblock pblock_1 [get_cells [list {g1.u2/gbtRxTx[36].fifo_inst} {g1.u2/gbtRxTx[36].gbtTxRx_inst} {g1.u2/gbtRxTx[37].fifo_inst} {g1.u2/gbtRxTx[37].gbtTxRx_inst} {g1.u2/gbtRxTx[38].fifo_inst} {g1.u2/gbtRxTx[38].gbtTxRx_inst} {g1.u2/gbtRxTx[39].fifo_inst} {g1.u2/gbtRxTx[39].gbtTxRx_inst} {g1.u2/gbtRxTx[40].fifo_inst} {g1.u2/gbtRxTx[40].gbtTxRx_inst} {g1.u2/gbtRxTx[41].fifo_inst} {g1.u2/gbtRxTx[41].gbtTxRx_inst} {g1.u2/gbtRxTx[42].fifo_inst} {g1.u2/gbtRxTx[42].gbtTxRx_inst} {g1.u2/gbtRxTx[43].fifo_inst} {g1.u2/gbtRxTx[43].gbtTxRx_inst} {g1.u2/gbtRxTx[44].fifo_inst} {g1.u2/gbtRxTx[44].gbtTxRx_inst} {g1.u2/gbtRxTx[45].fifo_inst} {g1.u2/gbtRxTx[45].gbtTxRx_inst} {g1.u2/gbtRxTx[46].fifo_inst} {g1.u2/gbtRxTx[46].gbtTxRx_inst} {g1.u2/gbtRxTx[47].fifo_inst} {g1.u2/gbtRxTx[47].gbtTxRx_inst}]]
-add_cells_to_pblock pblock_1 [get_cells [list {g1.u2/rxalign_auto[24].auto_rxrst} {g1.u2/rxalign_auto[24].rafsm} {g1.u2/rxalign_auto[13].auto_rxrst} {g1.u2/rxalign_auto[13].rafsm} {g1.u2/rxalign_auto[26].auto_rxrst} {g1.u2/rxalign_auto[26].rafsm} {g1.u2/rxalign_auto[27].auto_rxrst} {g1.u2/rxalign_auto[27].rafsm} {g1.u2/rxalign_auto[28].auto_rxrst} {g1.u2/rxalign_auto[28].rafsm} {g1.u2/rxalign_auto[29].auto_rxrst} {g1.u2/rxalign_auto[29].rafsm} {g1.u2/rxalign_auto[30].auto_rxrst} {g1.u2/rxalign_auto[30].rafsm} {g1.u2/rxalign_auto[31].auto_rxrst} {g1.u2/rxalign_auto[31].rafsm} {g1.u2/rxalign_auto[32].auto_rxrst} {g1.u2/rxalign_auto[32].rafsm} {g1.u2/rxalign_auto[33].auto_rxrst} {g1.u2/rxalign_auto[33].rafsm} {g1.u2/rxalign_auto[34].auto_rxrst} {g1.u2/rxalign_auto[34].rafsm} {g1.u2/rxalign_auto[35].auto_rxrst} {g1.u2/rxalign_auto[35].rafsm} {g1.u2/rxalign_auto[36].auto_rxrst} {g1.u2/rxalign_auto[36].rafsm} {g1.u2/rxalign_auto[37].auto_rxrst} {g1.u2/rxalign_auto[37].rafsm} {g1.u2/rxalign_auto[38].auto_rxrst} {g1.u2/rxalign_auto[38].rafsm} {g1.u2/rxalign_auto[39].auto_rxrst} {g1.u2/rxalign_auto[39].rafsm} {g1.u2/rxalign_auto[40].auto_rxrst} {g1.u2/rxalign_auto[40].rafsm} {g1.u2/rxalign_auto[41].auto_rxrst} {g1.u2/rxalign_auto[41].rafsm} {g1.u2/rxalign_auto[42].auto_rxrst} {g1.u2/rxalign_auto[42].rafsm} {g1.u2/rxalign_auto[43].auto_rxrst} {g1.u2/rxalign_auto[43].rafsm} {g1.u2/rxalign_auto[44].auto_rxrst} {g1.u2/rxalign_auto[44].rafsm} {g1.u2/rxalign_auto[45].auto_rxrst} {g1.u2/rxalign_auto[45].rafsm} {g1.u2/rxalign_auto[46].auto_rxrst} {g1.u2/rxalign_auto[46].rafsm} {g1.u2/rxalign_auto[47].auto_rxrst} {g1.u2/rxalign_auto[47].rafsm}]] -clear_locs
-resize_pblock [get_pblocks pblock_1] -add {CLOCKREGION_X0Y5:CLOCKREGION_X5Y9}
+#add_cells_to_pblock pblock_1 [get_cells [list {g1.u2/gbtRxTx[24].fifo_inst} {g1.u2/gbtRxTx[24].gbtTxRx_inst} {g1.u2/gbtRxTx[25].fifo_inst} {g1.u2/gbtRxTx[25].gbtTxRx_inst} {g1.u2/gbtRxTx[26].fifo_inst} {g1.u2/gbtRxTx[26].gbtTxRx_inst} {g1.u2/gbtRxTx[27].fifo_inst} {g1.u2/gbtRxTx[27].gbtTxRx_inst} {g1.u2/gbtRxTx[28].fifo_inst} {g1.u2/gbtRxTx[28].gbtTxRx_inst} {g1.u2/gbtRxTx[29].fifo_inst} {g1.u2/gbtRxTx[29].gbtTxRx_inst} {g1.u2/gbtRxTx[30].fifo_inst} {g1.u2/gbtRxTx[30].gbtTxRx_inst} {g1.u2/gbtRxTx[31].fifo_inst} {g1.u2/gbtRxTx[31].gbtTxRx_inst} {g1.u2/gbtRxTx[32].fifo_inst} {g1.u2/gbtRxTx[32].gbtTxRx_inst} {g1.u2/gbtRxTx[33].fifo_inst} {g1.u2/gbtRxTx[33].gbtTxRx_inst} {g1.u2/gbtRxTx[34].fifo_inst} {g1.u2/gbtRxTx[34].gbtTxRx_inst} {g1.u2/gbtRxTx[35].fifo_inst} {g1.u2/gbtRxTx[35].gbtTxRx_inst}]]
+#add_cells_to_pblock pblock_1 [get_cells [list {g1.u2/gbtRxTx[36].fifo_inst} {g1.u2/gbtRxTx[36].gbtTxRx_inst} {g1.u2/gbtRxTx[37].fifo_inst} {g1.u2/gbtRxTx[37].gbtTxRx_inst} {g1.u2/gbtRxTx[38].fifo_inst} {g1.u2/gbtRxTx[38].gbtTxRx_inst} {g1.u2/gbtRxTx[39].fifo_inst} {g1.u2/gbtRxTx[39].gbtTxRx_inst} {g1.u2/gbtRxTx[40].fifo_inst} {g1.u2/gbtRxTx[40].gbtTxRx_inst} {g1.u2/gbtRxTx[41].fifo_inst} {g1.u2/gbtRxTx[41].gbtTxRx_inst} {g1.u2/gbtRxTx[42].fifo_inst} {g1.u2/gbtRxTx[42].gbtTxRx_inst} {g1.u2/gbtRxTx[43].fifo_inst} {g1.u2/gbtRxTx[43].gbtTxRx_inst} {g1.u2/gbtRxTx[44].fifo_inst} {g1.u2/gbtRxTx[44].gbtTxRx_inst} {g1.u2/gbtRxTx[45].fifo_inst} {g1.u2/gbtRxTx[45].gbtTxRx_inst} {g1.u2/gbtRxTx[46].fifo_inst} {g1.u2/gbtRxTx[46].gbtTxRx_inst} {g1.u2/gbtRxTx[47].fifo_inst} {g1.u2/gbtRxTx[47].gbtTxRx_inst}]]
+#add_cells_to_pblock pblock_1 [get_cells [list {g1.u2/rxalign_auto[24].auto_rxrst} {g1.u2/rxalign_auto[24].rafsm} {g1.u2/rxalign_auto[13].auto_rxrst} {g1.u2/rxalign_auto[13].rafsm} {g1.u2/rxalign_auto[26].auto_rxrst} {g1.u2/rxalign_auto[26].rafsm} {g1.u2/rxalign_auto[27].auto_rxrst} {g1.u2/rxalign_auto[27].rafsm} {g1.u2/rxalign_auto[28].auto_rxrst} {g1.u2/rxalign_auto[28].rafsm} {g1.u2/rxalign_auto[29].auto_rxrst} {g1.u2/rxalign_auto[29].rafsm} {g1.u2/rxalign_auto[30].auto_rxrst} {g1.u2/rxalign_auto[30].rafsm} {g1.u2/rxalign_auto[31].auto_rxrst} {g1.u2/rxalign_auto[31].rafsm} {g1.u2/rxalign_auto[32].auto_rxrst} {g1.u2/rxalign_auto[32].rafsm} {g1.u2/rxalign_auto[33].auto_rxrst} {g1.u2/rxalign_auto[33].rafsm} {g1.u2/rxalign_auto[34].auto_rxrst} {g1.u2/rxalign_auto[34].rafsm} {g1.u2/rxalign_auto[35].auto_rxrst} {g1.u2/rxalign_auto[35].rafsm} {g1.u2/rxalign_auto[36].auto_rxrst} {g1.u2/rxalign_auto[36].rafsm} {g1.u2/rxalign_auto[37].auto_rxrst} {g1.u2/rxalign_auto[37].rafsm} {g1.u2/rxalign_auto[38].auto_rxrst} {g1.u2/rxalign_auto[38].rafsm} {g1.u2/rxalign_auto[39].auto_rxrst} {g1.u2/rxalign_auto[39].rafsm} {g1.u2/rxalign_auto[40].auto_rxrst} {g1.u2/rxalign_auto[40].rafsm} {g1.u2/rxalign_auto[41].auto_rxrst} {g1.u2/rxalign_auto[41].rafsm} {g1.u2/rxalign_auto[42].auto_rxrst} {g1.u2/rxalign_auto[42].rafsm} {g1.u2/rxalign_auto[43].auto_rxrst} {g1.u2/rxalign_auto[43].rafsm} {g1.u2/rxalign_auto[44].auto_rxrst} {g1.u2/rxalign_auto[44].rafsm} {g1.u2/rxalign_auto[45].auto_rxrst} {g1.u2/rxalign_auto[45].rafsm} {g1.u2/rxalign_auto[46].auto_rxrst} {g1.u2/rxalign_auto[46].rafsm} {g1.u2/rxalign_auto[47].auto_rxrst} {g1.u2/rxalign_auto[47].rafsm}]] -clear_locs
+#resize_pblock [get_pblocks pblock_1] -add {CLOCKREGION_X0Y5:CLOCKREGION_X5Y9}
-create_pblock pblock_0
-add_cells_to_pblock [get_pblocks pblock_0] [get_cells -quiet [list cr0 pcie0 fromHostFifo0 toHostFifo0]]
-add_cells_to_pblock pblock_0 [get_cells [list {g1.u2/CPLL_GEN.GTH_inst[0].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[1].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[2].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[3].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[4].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[5].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[6].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[7].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[8].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[9].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[10].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[11].GTH_TOP_INST}]]
-add_cells_to_pblock pblock_0 [get_cells [list {g1.u2/CPLL_GEN.GTH_inst[12].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[13].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[14].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[15].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[16].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[17].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[18].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[19].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[20].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[21].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[22].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[23].GTH_TOP_INST}]]
+#create_pblock pblock_0
+#add_cells_to_pblock [get_pblocks pblock_0] [get_cells -quiet [list cr0 pcie0 fromHostFifo0 toHostFifo0]]
+#add_cells_to_pblock pblock_0 [get_cells [list {g1.u2/CPLL_GEN.GTH_inst[0].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[1].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[2].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[3].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[4].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[5].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[6].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[7].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[8].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[9].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[10].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[11].GTH_TOP_INST}]]
+#add_cells_to_pblock pblock_0 [get_cells [list {g1.u2/CPLL_GEN.GTH_inst[12].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[13].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[14].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[15].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[16].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[17].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[18].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[19].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[20].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[21].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[22].GTH_TOP_INST} {g1.u2/CPLL_GEN.GTH_inst[23].GTH_TOP_INST}]]#
+
+#add_cells_to_pblock pblock_0 [get_cells [list {g1.u2/gbtRxTx[0].fifo_inst} {g1.u2/gbtRxTx[0].gbtTxRx_inst} {g1.u2/gbtRxTx[1].fifo_inst} {g1.u2/gbtRxTx[1].gbtTxRx_inst} {g1.u2/gbtRxTx[2].fifo_inst} {g1.u2/gbtRxTx[2].gbtTxRx_inst} {g1.u2/gbtRxTx[3].fifo_inst} {g1.u2/gbtRxTx[3].gbtTxRx_inst} {g1.u2/gbtRxTx[4].fifo_inst} {g1.u2/gbtRxTx[4].gbtTxRx_inst} {g1.u2/gbtRxTx[5].fifo_inst} {g1.u2/gbtRxTx[5].gbtTxRx_inst} {g1.u2/gbtRxTx[6].fifo_inst} {g1.u2/gbtRxTx[6].gbtTxRx_inst} {g1.u2/gbtRxTx[7].fifo_inst} {g1.u2/gbtRxTx[7].gbtTxRx_inst} {g1.u2/gbtRxTx[8].fifo_inst} {g1.u2/gbtRxTx[8].gbtTxRx_inst} {g1.u2/gbtRxTx[9].fifo_inst} {g1.u2/gbtRxTx[9].gbtTxRx_inst} {g1.u2/gbtRxTx[10].fifo_inst} {g1.u2/gbtRxTx[10].gbtTxRx_inst} {g1.u2/gbtRxTx[11].fifo_inst} {g1.u2/gbtRxTx[11].gbtTxRx_inst}]]
+#add_cells_to_pblock pblock_0 [get_cells [list {g1.u2/gbtRxTx[12].fifo_inst} {g1.u2/gbtRxTx[12].gbtTxRx_inst} {g1.u2/gbtRxTx[13].fifo_inst} {g1.u2/gbtRxTx[13].gbtTxRx_inst} {g1.u2/gbtRxTx[14].fifo_inst} {g1.u2/gbtRxTx[14].gbtTxRx_inst} {g1.u2/gbtRxTx[15].fifo_inst} {g1.u2/gbtRxTx[15].gbtTxRx_inst} {g1.u2/gbtRxTx[16].fifo_inst} {g1.u2/gbtRxTx[16].gbtTxRx_inst} {g1.u2/gbtRxTx[17].fifo_inst} {g1.u2/gbtRxTx[17].gbtTxRx_inst} {g1.u2/gbtRxTx[18].fifo_inst} {g1.u2/gbtRxTx[18].gbtTxRx_inst} {g1.u2/gbtRxTx[19].fifo_inst} {g1.u2/gbtRxTx[19].gbtTxRx_inst} {g1.u2/gbtRxTx[20].fifo_inst} {g1.u2/gbtRxTx[20].gbtTxRx_inst} {g1.u2/gbtRxTx[21].fifo_inst} {g1.u2/gbtRxTx[21].gbtTxRx_inst} {g1.u2/gbtRxTx[22].fifo_inst} {g1.u2/gbtRxTx[22].gbtTxRx_inst} {g1.u2/gbtRxTx[23].fifo_inst} {g1.u2/gbtRxTx[23].gbtTxRx_inst}]]
-add_cells_to_pblock pblock_0 [get_cells [list {g1.u2/gbtRxTx[0].fifo_inst} {g1.u2/gbtRxTx[0].gbtTxRx_inst} {g1.u2/gbtRxTx[1].fifo_inst} {g1.u2/gbtRxTx[1].gbtTxRx_inst} {g1.u2/gbtRxTx[2].fifo_inst} {g1.u2/gbtRxTx[2].gbtTxRx_inst} {g1.u2/gbtRxTx[3].fifo_inst} {g1.u2/gbtRxTx[3].gbtTxRx_inst} {g1.u2/gbtRxTx[4].fifo_inst} {g1.u2/gbtRxTx[4].gbtTxRx_inst} {g1.u2/gbtRxTx[5].fifo_inst} {g1.u2/gbtRxTx[5].gbtTxRx_inst} {g1.u2/gbtRxTx[6].fifo_inst} {g1.u2/gbtRxTx[6].gbtTxRx_inst} {g1.u2/gbtRxTx[7].fifo_inst} {g1.u2/gbtRxTx[7].gbtTxRx_inst} {g1.u2/gbtRxTx[8].fifo_inst} {g1.u2/gbtRxTx[8].gbtTxRx_inst} {g1.u2/gbtRxTx[9].fifo_inst} {g1.u2/gbtRxTx[9].gbtTxRx_inst} {g1.u2/gbtRxTx[10].fifo_inst} {g1.u2/gbtRxTx[10].gbtTxRx_inst} {g1.u2/gbtRxTx[11].fifo_inst} {g1.u2/gbtRxTx[11].gbtTxRx_inst}]]
-add_cells_to_pblock pblock_0 [get_cells [list {g1.u2/gbtRxTx[12].fifo_inst} {g1.u2/gbtRxTx[12].gbtTxRx_inst} {g1.u2/gbtRxTx[13].fifo_inst} {g1.u2/gbtRxTx[13].gbtTxRx_inst} {g1.u2/gbtRxTx[14].fifo_inst} {g1.u2/gbtRxTx[14].gbtTxRx_inst} {g1.u2/gbtRxTx[15].fifo_inst} {g1.u2/gbtRxTx[15].gbtTxRx_inst} {g1.u2/gbtRxTx[16].fifo_inst} {g1.u2/gbtRxTx[16].gbtTxRx_inst} {g1.u2/gbtRxTx[17].fifo_inst} {g1.u2/gbtRxTx[17].gbtTxRx_inst} {g1.u2/gbtRxTx[18].fifo_inst} {g1.u2/gbtRxTx[18].gbtTxRx_inst} {g1.u2/gbtRxTx[19].fifo_inst} {g1.u2/gbtRxTx[19].gbtTxRx_inst} {g1.u2/gbtRxTx[20].fifo_inst} {g1.u2/gbtRxTx[20].gbtTxRx_inst} {g1.u2/gbtRxTx[21].fifo_inst} {g1.u2/gbtRxTx[21].gbtTxRx_inst} {g1.u2/gbtRxTx[22].fifo_inst} {g1.u2/gbtRxTx[22].gbtTxRx_inst} {g1.u2/gbtRxTx[23].fifo_inst} {g1.u2/gbtRxTx[23].gbtTxRx_inst}]]
+#add_cells_to_pblock pblock_0 [get_cells [list {g1.u2/rxalign_auto[0].auto_rxrst} {g1.u2/rxalign_auto[0].rafsm} {g1.u2/rxalign_auto[1].auto_rxrst} {g1.u2/rxalign_auto[1].rafsm} {g1.u2/rxalign_auto[2].auto_rxrst} {g1.u2/rxalign_auto[2].rafsm} {g1.u2/rxalign_auto[3].auto_rxrst} {g1.u2/rxalign_auto[3].rafsm} {g1.u2/rxalign_auto[4].auto_rxrst} {g1.u2/rxalign_auto[4].rafsm} {g1.u2/rxalign_auto[5].auto_rxrst} {g1.u2/rxalign_auto[5].rafsm} {g1.u2/rxalign_auto[6].auto_rxrst} {g1.u2/rxalign_auto[6].rafsm} {g1.u2/rxalign_auto[7].auto_rxrst} {g1.u2/rxalign_auto[7].rafsm} {g1.u2/rxalign_auto[8].auto_rxrst} {g1.u2/rxalign_auto[8].rafsm} {g1.u2/rxalign_auto[9].auto_rxrst} {g1.u2/rxalign_auto[9].rafsm} {g1.u2/rxalign_auto[10].auto_rxrst} {g1.u2/rxalign_auto[10].rafsm} {g1.u2/rxalign_auto[11].auto_rxrst} {g1.u2/rxalign_auto[11].rafsm} {g1.u2/rxalign_auto[12].auto_rxrst} {g1.u2/rxalign_auto[12].rafsm} {g1.u2/rxalign_auto[13].auto_rxrst} {g1.u2/rxalign_auto[13].rafsm} {g1.u2/rxalign_auto[14].auto_rxrst} {g1.u2/rxalign_auto[14].rafsm} {g1.u2/rxalign_auto[15].auto_rxrst} {g1.u2/rxalign_auto[15].rafsm} {g1.u2/rxalign_auto[16].auto_rxrst} {g1.u2/rxalign_auto[16].rafsm} {g1.u2/rxalign_auto[17].auto_rxrst} {g1.u2/rxalign_auto[17].rafsm} {g1.u2/rxalign_auto[18].auto_rxrst} {g1.u2/rxalign_auto[18].rafsm} {g1.u2/rxalign_auto[19].auto_rxrst} {g1.u2/rxalign_auto[19].rafsm} {g1.u2/rxalign_auto[20].auto_rxrst} {g1.u2/rxalign_auto[20].rafsm} {g1.u2/rxalign_auto[21].auto_rxrst} {g1.u2/rxalign_auto[21].rafsm} {g1.u2/rxalign_auto[22].auto_rxrst} {g1.u2/rxalign_auto[22].rafsm} {g1.u2/rxalign_auto[23].auto_rxrst} {g1.u2/rxalign_auto[23].rafsm}]] -clear_locs
+#resize_pblock [get_pblocks pblock_0] -add {CLOCKREGION_X0Y0:CLOCKREGION_X5Y4}
-add_cells_to_pblock pblock_0 [get_cells [list {g1.u2/rxalign_auto[0].auto_rxrst} {g1.u2/rxalign_auto[0].rafsm} {g1.u2/rxalign_auto[1].auto_rxrst} {g1.u2/rxalign_auto[1].rafsm} {g1.u2/rxalign_auto[2].auto_rxrst} {g1.u2/rxalign_auto[2].rafsm} {g1.u2/rxalign_auto[3].auto_rxrst} {g1.u2/rxalign_auto[3].rafsm} {g1.u2/rxalign_auto[4].auto_rxrst} {g1.u2/rxalign_auto[4].rafsm} {g1.u2/rxalign_auto[5].auto_rxrst} {g1.u2/rxalign_auto[5].rafsm} {g1.u2/rxalign_auto[6].auto_rxrst} {g1.u2/rxalign_auto[6].rafsm} {g1.u2/rxalign_auto[7].auto_rxrst} {g1.u2/rxalign_auto[7].rafsm} {g1.u2/rxalign_auto[8].auto_rxrst} {g1.u2/rxalign_auto[8].rafsm} {g1.u2/rxalign_auto[9].auto_rxrst} {g1.u2/rxalign_auto[9].rafsm} {g1.u2/rxalign_auto[10].auto_rxrst} {g1.u2/rxalign_auto[10].rafsm} {g1.u2/rxalign_auto[11].auto_rxrst} {g1.u2/rxalign_auto[11].rafsm} {g1.u2/rxalign_auto[12].auto_rxrst} {g1.u2/rxalign_auto[12].rafsm} {g1.u2/rxalign_auto[13].auto_rxrst} {g1.u2/rxalign_auto[13].rafsm} {g1.u2/rxalign_auto[14].auto_rxrst} {g1.u2/rxalign_auto[14].rafsm} {g1.u2/rxalign_auto[15].auto_rxrst} {g1.u2/rxalign_auto[15].rafsm} {g1.u2/rxalign_auto[16].auto_rxrst} {g1.u2/rxalign_auto[16].rafsm} {g1.u2/rxalign_auto[17].auto_rxrst} {g1.u2/rxalign_auto[17].rafsm} {g1.u2/rxalign_auto[18].auto_rxrst} {g1.u2/rxalign_auto[18].rafsm} {g1.u2/rxalign_auto[19].auto_rxrst} {g1.u2/rxalign_auto[19].rafsm} {g1.u2/rxalign_auto[20].auto_rxrst} {g1.u2/rxalign_auto[20].rafsm} {g1.u2/rxalign_auto[21].auto_rxrst} {g1.u2/rxalign_auto[21].rafsm} {g1.u2/rxalign_auto[22].auto_rxrst} {g1.u2/rxalign_auto[22].rafsm} {g1.u2/rxalign_auto[23].auto_rxrst} {g1.u2/rxalign_auto[23].rafsm}]] -clear_locs
-resize_pblock [get_pblocks pblock_0] -add {CLOCKREGION_X0Y0:CLOCKREGION_X5Y4}
+#set_min_delay -from [get_pins clk0/clk0/inst/mmcme3_adv_inst/CLKOUT0] -to [get_pins {g1.u2/gbtRxTx[*].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/TX_FRAMECLK_I_r_reg*/D}] 24.95
+#set_max_delay -from [get_pins clk0/clk0/inst/mmcme3_adv_inst/CLKOUT0] -to [get_pins {g1.u2/gbtRxTx[*].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/TX_FRAMECLK_I_r_reg*/D}] 29.128
+#set_min_delay -from [get_pins clk0/clk0/inst/mmcme3_adv_inst/CLKOUT0] -to [get_pins {g1.u2/gbtRxTx[*].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/TX_FRAMECLK_I_4r_reg*/D}] 24.95
+#set_max_delay -from [get_pins clk0/clk0/inst/mmcme3_adv_inst/CLKOUT0] -to [get_pins {g1.u2/gbtRxTx[*].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/TX_FRAMECLK_I_4r_reg*/D}] 29.128
-set_min_delay -from [get_pins clk0/clk0/inst/mmcme3_adv_inst/CLKOUT0] -to [get_pins {g1.u2/gbtRxTx[*].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/TX_FRAMECLK_I_r_reg*/D}] 24.95
-set_max_delay -from [get_pins clk0/clk0/inst/mmcme3_adv_inst/CLKOUT0] -to [get_pins {g1.u2/gbtRxTx[*].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/TX_FRAMECLK_I_r_reg*/D}] 29.128
-set_min_delay -from [get_pins clk0/clk0/inst/mmcme3_adv_inst/CLKOUT0] -to [get_pins {g1.u2/gbtRxTx[*].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/TX_FRAMECLK_I_4r_reg*/D}] 24.95
-set_max_delay -from [get_pins clk0/clk0/inst/mmcme3_adv_inst/CLKOUT0] -to [get_pins {g1.u2/gbtRxTx[*].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/TX_FRAMECLK_I_4r_reg*/D}] 29.128
\ No newline at end of file
+set_max_delay -from [get_pins {g1.u2/clk_generate[0].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[0].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[1].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[1].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[2].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[2].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[3].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[3].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[4].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[4].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[5].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[5].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[6].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[6].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[7].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[7].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[8].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[8].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[9].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[9].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[10].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[10].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[11].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[11].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[12].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[12].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[13].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[13].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[14].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[14].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[15].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[15].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[16].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[16].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[17].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[17].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[18].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[18].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[19].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[19].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[20].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[20].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[21].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[21].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[22].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[22].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[23].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[23].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[24].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[24].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[25].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[25].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[26].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[26].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[27].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[27].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[28].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[28].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[29].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[29].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[30].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[30].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[31].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[31].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[32].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[32].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[33].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[33].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[34].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[34].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[35].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[35].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[36].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[36].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[37].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[37].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[38].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[38].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[39].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[39].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[40].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[40].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[41].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[41].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[42].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[42].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[43].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[43].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[44].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[44].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[45].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[45].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[46].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[46].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
+set_max_delay -from [get_pins {g1.u2/clk_generate[47].GTTXOUTCLK_BUFG/O}] -to [get_pins {g1.u2/gbtRxTx[47].gbtTxRx_inst/gbtTx_inst/FelixScrambler/timedomaincrossing_C/cdc_frame_clock/dest_clk}] 1
\ No newline at end of file
diff --git a/constraints/timing_constraints_ku.xdc b/constraints/timing_constraints_ku.xdc
index b2397bb47..a8cad8cde 100644
--- a/constraints/timing_constraints_ku.xdc
+++ b/constraints/timing_constraints_ku.xdc
@@ -55,7 +55,7 @@ set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clo
set_max_delay -datapath_only -from [get_clocks txoutclk*] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
set_max_delay -datapath_only -from [get_clocks {GT_RX_WORD_CLK[*]}] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
set_max_delay -datapath_only -from [get_clocks {GT_TX_WORD_CLK[*]}] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks ts_clk_adn_160] -to [get_clocks {GT_TX_WORD_CLK[0]}] 6.237
+#set_max_delay -datapath_only -from [get_clocks ts_clk_adn_160] -to [get_clocks {GT_TX_WORD_CLK[0]}] 6.237 #duplicated
set_max_delay -datapath_only -from [get_clocks ts_clk_adn_160] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks {GT_TX_WORD_CLK[*]}] 24.950
diff --git a/scripts/filesets/gbt_core_fileset.tcl b/scripts/filesets/gbt_core_fileset.tcl
index c086a7203..161e45831 100644
--- a/scripts/filesets/gbt_core_fileset.tcl
+++ b/scripts/filesets/gbt_core_fileset.tcl
@@ -71,3 +71,4 @@ set XCI_FILES_KU [concat $XCI_FILES_KU \
KCU_NORXBUF_PCS_CPLL_1CH.xci \
KCU_RXBUF_PMA_CPLL_1CH.xci \
KCU_RXBUF_PMA_QPLL_4CH.xci]
+# ila_LTDB.xci]
diff --git a/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd b/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd
index f7853ca91..83c980164 100644
--- a/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd
+++ b/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd
@@ -373,7 +373,9 @@ architecture Behavioral of FELIX_gbt_wrapper_KCU is
attribute use_dsp : string;
--attribute use_dsp of fec_error_cnt : signal is "yes";
-
+ signal Tx_Align_Signal : std_logic_vector(47 downto 0):=x"000000000000"; --test for LTDB
+ --signal TX_FRAMECLK_I_sync_out : std_logic_vector(47 downto 0);
+ signal ila_clk : std_logic; --debug clock for the ILA
begin
FRAME_LOCKED_O <= alignment_done_f(GBT_NUM-1 downto 0);
@@ -1087,8 +1089,9 @@ end generate g_refclk_48ch;
TX_WORDCLK_I => GT_TX_WORD_CLK(i),
--TX_ISDATA_SEL_I => TX_IS_DATA(i),
TX_DATA_120b_I => TX_120b_in(i),
- TX_DATA_20b_O => TX_DATA_20b(i)
-
+ TX_DATA_20b_O => TX_DATA_20b(i),
+ Tx_Align_Signal_O => Tx_Align_Signal(i)--,--test for LTDB
+ --TX_FRAMECLK_I_sync_out => TX_FRAMECLK_I_sync_out(i)
);
fifo_rst(i) <= rst_hw or (not alignment_done_f(i)) or RX_RESET_i_40(i) or General_ctrl(4);
@@ -1341,5 +1344,18 @@ end generate g_refclk_48ch;
end generate;
end generate;
+LTDB_test: entity work.ila_LTDB --test FLXUSER 594
+PORT MAP (
+ clk => ila_clk, --GT_TX_WORD_CLK(0),
+ probe0 => Tx_Align_Signal,
+ probe1 => (others => '0')--TX_FRAMECLK_I_sync_out
+);
+
+ clean_clk: BUFGCE
+ port map (
+ O => ila_clk, -- 1-bit output: Clock output
+ CE => cplllock(0), -- 1-bit input: Clock enable input for I0
+ I => GT_TX_WORD_CLK(0) -- 1-bit input: Primary clock
+ );
end Behavioral;
diff --git a/sources/GBT/gbt_code/gbtTxRx_FELIX.vhd b/sources/GBT/gbt_code/gbtTxRx_FELIX.vhd
index 464216561..ea690a9f4 100644
--- a/sources/GBT/gbt_code/gbtTxRx_FELIX.vhd
+++ b/sources/GBT/gbt_code/gbtTxRx_FELIX.vhd
@@ -109,7 +109,9 @@ entity gbtTxRx_FELIX is
TX_WORDCLK_I : in std_logic;
-- TX_ISDATA_SEL_I : in std_logic;
TX_DATA_120b_I : in std_logic_vector(119 downto 0);
- TX_DATA_20b_O : out std_logic_vector(19 downto 0)
+ TX_DATA_20b_O : out std_logic_vector(19 downto 0);
+ Tx_Align_Signal_O : out std_logic--; --test for LTDB
+ --TX_FRAMECLK_I_sync_out : out std_logic
);
end gbtTxRx_FELIX;
@@ -321,7 +323,10 @@ begin
TX_HEADER_I => TX_DATA_120b_I(119 downto 116),
TX_DATA_84b_I => TX_DATA_120b_I(115 downto 32),
TX_EXTRA_DATA_WIDEBUS_I => TX_DATA_120b_I(31 downto 0),
- TX_DATA_20b_O => TX_DATA_20b_O
+ TX_DATA_20b_O => TX_DATA_20b_O,
+ Tx_Align_Signal_O => Tx_Align_Signal_O--, --test for LTDB
+ --TX_FRAMECLK_I_sync_out => TX_FRAMECLK_I_sync_out
+
);
diff --git a/sources/GBT/gbt_code/gbtTx_FELIX.vhd b/sources/GBT/gbt_code/gbtTx_FELIX.vhd
index 2bd55032a..a0a04e3c3 100644
--- a/sources/GBT/gbt_code/gbtTx_FELIX.vhd
+++ b/sources/GBT/gbt_code/gbtTx_FELIX.vhd
@@ -81,7 +81,10 @@ entity gbtTx_FELIX is
TX_DATA_84b_I : in std_logic_vector(83 downto 0);
TX_EXTRA_DATA_WIDEBUS_I : in std_logic_vector(31 downto 0);
- TX_DATA_20b_O : out std_logic_vector(19 downto 0)
+ TX_DATA_20b_O : out std_logic_vector(19 downto 0);
+ Tx_Align_Signal_O : out std_logic--; --test for LTDB
+ --TX_FRAMECLK_I_sync_out : out std_logic
+
);
end gbtTx_FELIX;
@@ -122,10 +125,13 @@ begin
TX_DATA_I => TX_DATA_84b_I,
TX_COMMON_FRAME_O => TxCommon84b,
TX_EXTRA_DATA_WIDEBUS_I => TX_EXTRA_DATA_WIDEBUS_I,
- TX_EXTRA_FRAME_WIDEBUS_O => TxExtraWidebus32b
+ TX_EXTRA_FRAME_WIDEBUS_O => TxExtraWidebus32b--,
+ --TX_FRAMECLK_I_sync_out => TX_FRAMECLK_I_sync_out
+
);
-
+ Tx_Align_Signal_O <= Tx_Align_Signal; --test for LTDB
+
-- Encoder
encoder: entity work.gbt_tx_encoder_FELIX
diff --git a/sources/GBT/gbt_code/gbt_tx_scrambler_FELIX.vhd b/sources/GBT/gbt_code/gbt_tx_scrambler_FELIX.vhd
index 9f6fd8b6e..bbbf7abb4 100644
--- a/sources/GBT/gbt_code/gbt_tx_scrambler_FELIX.vhd
+++ b/sources/GBT/gbt_code/gbt_tx_scrambler_FELIX.vhd
@@ -16,84 +16,85 @@
--! See the License for the specific language governing permissions and
--! limitations under the License.
--------------------------------------------------------------------------------
--- Based on GBT-FPGA project v3
--- Modified by K. Chen @ Dec. 2014, Clock changed, in/out control signal added.
--- Crossing time domain logic is included, time margin is added, it can be
--- dynamic adjusted, or adjusted through the package file.
-
--- Low-level 16/21 bit scrambler is almost same with GBT-FPGA project, one
--- enable signal is added.
--------------------------------------------------------------------------------
-
-
-
-library ieee;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-use work.FELIX_gbt_package.all;
-
-entity gbt_tx_scrambler_FELIX is
- --generic
- --
- -- (
- -- channel : integer := 0
- -- );
- port
- (
-
- TX_TC_METHOD : in std_logic;
- Scrambler_Enable : in std_logic;
- Tx_Align_Signal : out std_logic;
- --TX_LATOPT_TC : in std_logic;
- TC_EDGE : in std_logic;
- TX_TC_DLY_VALUE : in std_logic_vector(2 downto 0);
-
- TX_WORDCLK_I : in std_logic;
- TX_RESET_I : in std_logic;
- TX_FRAMECLK_I : in std_logic;
-
- --TX_ISDATA_SEL_I : in std_logic;
- TX_HEADER_I : in std_logic_vector( 3 downto 0);
-
- TX_HEADER_O : out std_logic_vector(3 downto 0);
-
- TX_DATA_I : in std_logic_vector(83 downto 0);
- TX_COMMON_FRAME_O : out std_logic_vector(83 downto 0);
-
- TX_EXTRA_DATA_WIDEBUS_I : in std_logic_vector(31 downto 0);
- TX_EXTRA_FRAME_WIDEBUS_O : out std_logic_vector(31 downto 0)
-
- );
-end gbt_tx_scrambler_FELIX;
-
-
-architecture Behavior of gbt_tx_scrambler_FELIX is
-
-
-begin
---=================================================================================================--
-
- --==================================== User Logic =====================================--
-
-
- ------------------------------------------------------------------------------
- ---- Addde by K. Chen
- ---- Dec. 2014
-
- timedomaincrossing_C :entity work.gbt_tx_timedomaincrossing_FELIX
- --generic map
- --(
- -- channel => channel
- -- )
- port map
- (
-
+-------------------------------------------------------------------------------
+-- Based on GBT-FPGA project v3
+-- Modified by K. Chen @ Dec. 2014, Clock changed, in/out control signal added.
+-- Crossing time domain logic is included, time margin is added, it can be
+-- dynamic adjusted, or adjusted through the package file.
+
+-- Low-level 16/21 bit scrambler is almost same with GBT-FPGA project, one
+-- enable signal is added.
+-------------------------------------------------------------------------------
+
+
+
+library ieee;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+use work.FELIX_gbt_package.all;
+
+entity gbt_tx_scrambler_FELIX is
+ --generic
+ --
+ -- (
+ -- channel : integer := 0
+ -- );
+ port
+ (
+
+ TX_TC_METHOD : in std_logic;
+ Scrambler_Enable : in std_logic;
+ Tx_Align_Signal : out std_logic;
+ --TX_LATOPT_TC : in std_logic;
+ TC_EDGE : in std_logic;
+ TX_TC_DLY_VALUE : in std_logic_vector(2 downto 0);
+
+ TX_WORDCLK_I : in std_logic;
+ TX_RESET_I : in std_logic;
+ TX_FRAMECLK_I : in std_logic;
+
+ --TX_ISDATA_SEL_I : in std_logic;
+ TX_HEADER_I : in std_logic_vector( 3 downto 0);
+
+ TX_HEADER_O : out std_logic_vector(3 downto 0);
+
+ TX_DATA_I : in std_logic_vector(83 downto 0);
+ TX_COMMON_FRAME_O : out std_logic_vector(83 downto 0);
+
+ TX_EXTRA_DATA_WIDEBUS_I : in std_logic_vector(31 downto 0);
+ TX_EXTRA_FRAME_WIDEBUS_O : out std_logic_vector(31 downto 0)--;
+ --TX_FRAMECLK_I_sync_out : out std_logic
+
+ );
+end gbt_tx_scrambler_FELIX;
+
+
+architecture Behavior of gbt_tx_scrambler_FELIX is
+
+
+begin
+--=================================================================================================--
+
+ --==================================== User Logic =====================================--
+
+
+ ------------------------------------------------------------------------------
+ ---- Addde by K. Chen
+ ---- Dec. 2014
+
+ timedomaincrossing_C :entity work.gbt_tx_timedomaincrossing_FELIX
+ --generic map
+ --(
+ -- channel => channel
+ -- )
+ port map
+ (
+
Tx_Align_Signal => Tx_Align_Signal,
--TX_LATOPT_TC => TX_LATOPT_TC,
TX_TC_METHOD => TX_TC_METHOD,
@@ -101,31 +102,33 @@ begin
TX_TC_DLY_VALUE => TX_TC_DLY_VALUE,
TX_WORDCLK_I => TX_WORDCLK_I,
TX_RESET_I => TX_RESET_I,
- TX_FRAMECLK_I => TX_FRAMECLK_I
-
-
- );
-
-
-
-
-
- process(TX_WORDCLK_I)
- begin
- if TX_WORDCLK_I'event and TX_WORDCLK_I='1' then
- if Scrambler_Enable='1' then
- TX_HEADER_O <= TX_HEADER_I;
- end if;
- end if;
- end process;
-
-
-
- gbtFrameOrWideBus_gen: if (DATA_MODE = GBT_FRAME) or (DATA_MODE = WIDE_BUS) generate
- gbtTxScrambler84bit_gen: for i in 0 to 3 generate
- -- Comment: [83:63] & [62:42] & [41:21] & [20:0]
- gbtTxScrambler21bit: entity work.gbt_tx_scrambler_21bit
- port map(
+ TX_FRAMECLK_I => TX_FRAMECLK_I--,
+ --TX_FRAMECLK_I_sync_out => TX_FRAMECLK_I_sync_out
+
+
+
+ );
+
+
+
+
+
+ process(TX_WORDCLK_I)
+ begin
+ if TX_WORDCLK_I'event and TX_WORDCLK_I='1' then
+ if Scrambler_Enable='1' then
+ TX_HEADER_O <= TX_HEADER_I;
+ end if;
+ end if;
+ end process;
+
+
+
+ gbtFrameOrWideBus_gen: if (DATA_MODE = GBT_FRAME) or (DATA_MODE = WIDE_BUS) generate
+ gbtTxScrambler84bit_gen: for i in 0 to 3 generate
+ -- Comment: [83:63] & [62:42] & [41:21] & [20:0]
+ gbtTxScrambler21bit: entity work.gbt_tx_scrambler_21bit
+ port map(
Scrambler_Enable => Scrambler_Enable,
TX_RESET_I => TX_RESET_I,
RESET_PATTERN_I => SCRAMBLER_21BIT_RESET_PATTERNS(i),
@@ -133,22 +136,22 @@ begin
TX_FRAMECLK_I => TX_WORDCLK_I,
---------------------------------
TX_DATA_I => TX_DATA_I(((21*i)+20) downto (21*i)),
- TX_COMMON_FRAME_O => TX_COMMON_FRAME_O(((21*i)+20) downto (21*i))
- );
-
- end generate;
- end generate;
-
- -- 32 bit scrambler (Wide-Bus):
- -- Kept for dynamic data type change
- ------------------------------
-
- wideBus_gen: if (DATA_MODE = GBT_FRAME) or (DATA_MODE = WIDE_BUS) generate
-
- gbtTxScrambler32bit_gen: for i in 0 to 1 generate
- ---- Comment: [31:16] & [15:0]
- gbtTxScrambler16bit: entity work.gbt_tx_scrambler_16bit
- port map(
+ TX_COMMON_FRAME_O => TX_COMMON_FRAME_O(((21*i)+20) downto (21*i))
+ );
+
+ end generate;
+ end generate;
+
+ -- 32 bit scrambler (Wide-Bus):
+ -- Kept for dynamic data type change
+ ------------------------------
+
+ wideBus_gen: if (DATA_MODE = GBT_FRAME) or (DATA_MODE = WIDE_BUS) generate
+
+ gbtTxScrambler32bit_gen: for i in 0 to 1 generate
+ ---- Comment: [31:16] & [15:0]
+ gbtTxScrambler16bit: entity work.gbt_tx_scrambler_16bit
+ port map(
Scrambler_Enable => Scrambler_Enable, --'1',
TX_RESET_I => TX_RESET_I,
RESET_PATTERN_I => SCRAMBLER_16BIT_RESET_PATTERNS(i),
@@ -156,16 +159,16 @@ begin
TX_FRAMECLK_I => TX_WORDCLK_I,
---------------------------------
TX_EXTRA_DATA_WIDEBUS_I => TX_EXTRA_DATA_WIDEBUS_I(((16*i)+15) downto (16*i)),
- TX_EXTRA_FRAME_WIDEBUS_O => TX_EXTRA_FRAME_WIDEBUS_O(((16*i)+15) downto (16*i))
- );
-
- end generate;
- end generate;
-
-
-
- --=====================================================================================--
-end Behavior;
---=================================================================================================--
---#################################################################################################--
---=================================================================================================--
+ TX_EXTRA_FRAME_WIDEBUS_O => TX_EXTRA_FRAME_WIDEBUS_O(((16*i)+15) downto (16*i))
+ );
+
+ end generate;
+ end generate;
+
+
+
+ --=====================================================================================--
+end Behavior;
+--=================================================================================================--
+--#################################################################################################--
+--=================================================================================================--
diff --git a/sources/GBT/gbt_code/gbt_tx_timedomaincrossing_FELIX.vhd b/sources/GBT/gbt_code/gbt_tx_timedomaincrossing_FELIX.vhd
index a0d1bca2c..786b59e5e 100644
--- a/sources/GBT/gbt_code/gbt_tx_timedomaincrossing_FELIX.vhd
+++ b/sources/GBT/gbt_code/gbt_tx_timedomaincrossing_FELIX.vhd
@@ -74,8 +74,9 @@ entity gbt_tx_timedomaincrossing_FELIX is
TX_WORDCLK_I : in std_logic;
TX_RESET_I : in std_logic;
- TX_FRAMECLK_I : in std_logic
+ TX_FRAMECLK_I : in std_logic--;
+ --TX_FRAMECLK_I_sync_out : out std_logic
--TX_ISDATA_SEL_I : in std_logic;
);
@@ -103,8 +104,10 @@ architecture Behavior of gbt_tx_timedomaincrossing_FELIX is
signal TX_FRAMECLK_I_sync : std_logic;
begin
+
+ --TX_FRAMECLK_I_sync_out <= TX_FRAMECLK_I_sync;
--Add 6 clocks TX_WORDCLK_I (240MHz) to TX_FRAMECLK_I so it is exactly one period later, but synced to TX_WORDCLK_I
- cdc_header_found : xpm_cdc_single
+ cdc_frame_clock : xpm_cdc_single
generic map (
DEST_SYNC_FF => 6,
INIT_SYNC_FF => 0,
diff --git a/sources/ip_cores/kintexUltrascale/ila_LTDB.xci b/sources/ip_cores/kintexUltrascale/ila_LTDB.xci
new file mode 100644
index 000000000..04fd13075
--- /dev/null
+++ b/sources/ip_cores/kintexUltrascale/ila_LTDB.xci
@@ -0,0 +1,3252 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>xci</spirit:library>
+ <spirit:name>unknown</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>ila_LTDB</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ila" spirit:version="6.2"/>
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.ASSOCIATED_RESET"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.ADDR_WIDTH">48</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
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+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--
GitLab