diff --git a/constraints/timing_constraints_felig_gbt.xdc b/constraints/timing_constraints_felig_gbt.xdc
index 299393dad541709c939279a9440063a889c3359f..f9efed191727cf3743d2c6461f71b4b15f072f39 100644
--- a/constraints/timing_constraints_felig_gbt.xdc
+++ b/constraints/timing_constraints_felig_gbt.xdc
@@ -1,279 +1,93 @@
-#create 40 MHz TTC clock
-create_clock -name clk_ttc_40 -period 24.95 [get_pins */ttc_dec/from_cdr_to_AandB/clock_iter/O]
-
-
-#MT already felix_top*v20.xdc create_clock -period 6.237 -name clk_adn_160 [get_ports CLK_TTC_P]
+set GTHREFCLK_PERIOD 4.158
+set LMK_PERIOD 4.158
+#create 40 MHz TTC clock. RL: changed to 25 to stop errors in the implementation. this clock is not used in FELIG anyway
+create_clock -name clk_ttc_40 -period 25 [get_pins */ttc_dec/from_cdr_to_AandB/clock_iter/O]
 
+create_clock -period 6.25 -name clk_adn_160 [get_ports CLK_TTC_P]
 
 create_clock -period 10.000 -name sys_clk0_p -waveform {0.000 5.000} [get_ports {sys_clk_p[0]}]
 create_clock -quiet -period 10.000 -name sys_clk1_p -waveform {0.000 5.000} [get_ports {sys_clk_p[1]}]
 
-#MT already felix_top*v20.xdc create_clock -name emcclk -period 20.000 [get_ports emcclk]
-#create_clock -name u2/GT_TX_WORD_CLK[0] -period 4.158 [get_pins u2/clk_generate[0].GTTXOUTCLK_BUFG/O]
-
-#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk0/g_200M.clk0/inst/clk40]
-set_property -quiet CLOCK_DEDICATED_ROUTE FALSE [get_nets emcclk_IBUF_inst/O]
-
-#We need this line when we move to the second SRL
-create_clock -name GTHREFCLK_0 -period 4.158 [get_ports {GTREFCLK_P_IN[0]}]
-create_clock -quiet -name GTHREFCLK_1 -period 4.158 [get_ports {GTREFCLK_P_IN[1]}]
-create_clock -quiet -name GTHREFCLK_2 -period 4.158 [get_ports {GTREFCLK_P_IN[2]}]
-create_clock -quiet -name GTHREFCLK_3 -period 4.158 [get_ports {GTREFCLK_P_IN[3]}]
-create_clock -quiet -name GTHREFCLK_4 -period 4.158 [get_ports {GTREFCLK_P_IN[4]}]
-
-create_clock -name GT_TX_WORD_CLK[0] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[0].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[1] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[0].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[2] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[0].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[3] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[0].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[4] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[1].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[5] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[1].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[6] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[1].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[7] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[1].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[8] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[2].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[9] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[2].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[10] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[2].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[11] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[2].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[12] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[3].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[13] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[3].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[14] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[3].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[15] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[3].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[16] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[4].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[17] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[4].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[18] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[4].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[19] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[4].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[20] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[5].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[21] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[5].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[22] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[5].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[23] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[5].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[24] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[6].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[25] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[6].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[26] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[6].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[27] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[6].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[28] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[7].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[29] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[7].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[30] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[7].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[31] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[7].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[32] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[8].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[33] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[8].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[34] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[8].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[35] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[8].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[36] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[9].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[37] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[9].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[38] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[9].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[39] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[9].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[40] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[10].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[41] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[10].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[42] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[10].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[43] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[10].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[44] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[11].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[45] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[11].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[46] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[11].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[47] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[11].GTH_TOP_INST/txoutclk_out[3]"}]
-
-create_clock -name GT_RX_WORD_CLK[0] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[0].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[1] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[0].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[2] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[0].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[3] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[0].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[4] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[1].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[5] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[1].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[6] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[1].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[7] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[1].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[8] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[2].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[9] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[2].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[10] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[2].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[11] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[2].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[12] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[3].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[13] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[3].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[14] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[3].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[15] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[3].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[16] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[4].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[17] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[4].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[18] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[4].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[19] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[4].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[20] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[5].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[21] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[5].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[22] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[5].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[23] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[5].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[24] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[6].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[25] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[6].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[26] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[6].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[27] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[6].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[28] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[7].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[29] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[7].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[30] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[7].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[31] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[7].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[32] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[8].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[33] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[8].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[34] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[8].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[35] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[8].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[36] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[9].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[37] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[9].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[38] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[9].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[39] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[9].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[40] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[10].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[41] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[10].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[42] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[10].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[43] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[10].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[44] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[11].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[45] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[11].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[46] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[11].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[47] -period 4.167 [get_pins -hierarchical -filter {NAME =~ "*/g_GBTMODE.u1/*PLL_GEN.GTH_inst[11].GTH_TOP_INST/rxoutclk_out[3]"}]
+create_clock -name emcclk -period 20.000 [get_ports emcclk]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets emcclk_IBUF_inst/O]
+
+#GTREFCLKS up to 6, use -quiet for the ones that don't exist due to limited number of channels.
+create_clock -quiet -name GTHREFCLK_0 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[0]}]
+create_clock -quiet -name GTHREFCLK_1 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[1]}]
+create_clock -quiet -name GTHREFCLK_2 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[2]}]
+create_clock -quiet -name GTHREFCLK_3 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[3]}]
+create_clock -quiet -name GTHREFCLK_4 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[4]}]
+create_clock -quiet -name GTHREFCLK_5 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[5]}]
+create_clock -quiet -name GTHREFCLK_6 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[6]}]
+create_clock -quiet -name GTHREFCLK_7 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[7]}]
+create_clock -quiet -name GTHREFCLK_8 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[8]}]
+create_clock -quiet -name GTHREFCLK_9 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[9]}]
+create_clock -quiet -name GTHREFCLK_10 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[10]}]
+create_clock -quiet -name GTHREFCLK_11 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[11]}]
+
+create_clock -quiet -name LMK0_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[0]}]
+create_clock -quiet -name LMK1_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[1]}]
+create_clock -quiet -name LMK2_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[2]}]
+create_clock -quiet -name LMK3_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[3]}]
+create_clock -quiet -name LMK4_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[4]}]
+create_clock -quiet -name LMK5_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[5]}]
+create_clock -quiet -name LMK6_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[6]}]
+create_clock -quiet -name LMK7_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[7]}]
 
 create_clock -quiet -name i2c_clock_pex -period 2500 [get_pins hk0/g_711_712.pex_init0/data_clk_reg/Q]
 
-#added FELIG
-create_clock -period 4.167 -name cdrclk_in [get_pins g_GBTMODE.u1/ibufds_instq2_clk0/O]
-create_clock -period 4.167 -name CXP2_GTH_RefClk [get_pins g_GBTMODE.u1/ibufds_instq8_clk0/O]
-create_clock -period 4.167 -name CXP1_GTH_RefClk_LMK [get_pins g_GBTMODE.u1/ibufds_LMK1/O] 
-create_clock -period 4.167 -name CXP2_GTH_RefClk_LMK [get_pins g_GBTMODE.u1/ibufds_LMK2/O] 
-create_clock -period 4.167 -name CXP3_GTH_RefClk [get_pins g_GBTMODE.u1/ibufds_instq4_clk0/O]
-create_clock -period 4.167 -name CXP4_GTH_RefClk [get_pins g_GBTMODE.u1/ibufds_instq5_clk0/O]
-create_clock -period 4.167 -name CXP5_GTH_RefClk [get_pins g_GBTMODE.u1/refclkgen_v2p0.g_refclk12.ibufds_instq6_clk0/O]
-
-#Clock domain crossings within Central Router
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks clk240_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks clk160_clk_wiz_40_0*] 24.950
-
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_0*] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_0*] -to [get_clocks clk80_clk_wiz_40_0*] 12.475
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_0*] -to [get_clocks clk160_clk_wiz_40_0*] 6.237
-
-set_max_delay -datapath_only -from [get_clocks clk160_clk_wiz_40_0*] -to [get_clocks clk240_clk_wiz_40_0*] 4.170
-#set_max_delay -from [get_pins */rst0/cr_rst_rr_reg*/C] -to [get_clocks clk160_clk_wiz_40_0*] 6.237
-
-
-#Clock domain crossings in GBT
-set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks {GT_TX_WORD_CLK[*]}] 6.237
-set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks {GT_RX_WORD_CLK[*]}] 6.237
-set_max_delay -quiet -datapath_only -from [get_clocks clk40_clk_wiz_156_0*] -to [get_clocks {GT_TX_WORD_CLK[*]}] 24.950
-set_max_delay -from [get_pins -hierarchical -filter {NAME =~ "linkwrapper0/*/bit_synchronizer_rxcdrlock_inst/i_in_out_reg/C"}] -to [get_pins -hierarchical -filter {NAME =~ "linkwrapper0/*/gbtRxTx[*].BITSLIP_MANUAL_r_reg[*]/D"}] 24.95
-
-#Clock domain crossings in TTC decoder
-set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks clk_ttc_40] 6.237
-set_max_delay -datapath_only -from [get_clocks clk_ttc_40] -to [get_clocks clk_adn_160] 6.237
-set_max_delay -from [get_pins u2/ttc_dec/from_cdr_to_AandB/ttcclk_reg/Q] -to [get_pins u2/ttc_dec/from_cdr_to_AandB/ttcclk_reg/D] 6.237
-
-#Clock domain crossings between Wupper and Central Router
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_*] -to [get_clocks *rd_clk] 4.000
-
+#set_max_delay from timing_constraints.xdc
 
 #Register map to 400kHz I2C clock
-set_max_delay -datapath_only -from [get_clocks *] -to [get_clocks clk400] 100.000
-set_max_delay -datapath_only -from [get_clocks *] -to [get_clocks i2c_clock_pex] 100.000
-
-#Register map to central router clocks
-set_max_delay -datapath_only -from [get_clocks *rd_clk] -to [get_clocks clk80_clk_wiz_40_0*] 12.475
+set_max_delay -quiet -datapath_only -from [get_clocks -regexp ^((?!clk400).)*$] -to [get_clocks clk400] 100.000
+set_max_delay -quiet -datapath_only -from [get_clocks -regexp ^((?!i2c_clock_pex).)*$] -to [get_clocks i2c_clock_pex] 100.000
 
-
-#Register map control / monitor
-set_max_delay -datapath_only -from [get_clocks clk_out25*] -to [get_clocks *] 40.000
-set_max_delay -datapath_only -from [get_clocks *] -to [get_clocks clk_out25*] 40.000
-
-#Clock domain crossings in ttc decoder
-set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks clk_ttc_40] 24.95
-
-#Clock domain crossings between Central Router and GBT
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks txoutclk*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks {GT_RX_WORD_CLK[*]}] 24.950
-set_max_delay -datapath_only -from [get_clocks txoutclk*] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks {GT_RX_WORD_CLK[*]}] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks {GT_TX_WORD_CLK[*]}] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks {GT_TX_WORD_CLK[0]}] 6.237
-set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks {GT_TX_WORD_CLK[*]}] 24.950
-
-# added #FELIG
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks clk10_clk_wiz_200_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_200_0*] -to [get_clocks {GT_TX_WORD_CLK[*]}] 24.950
-set_max_delay -datapath_only -from [get_clocks GT_TX_WORD_CLK[*]] -to [get_clocks {GT_RX_WORD_CLK[*]}] 4.170
-
-set_max_delay -from [get_pins -hierarchical -filter {NAME =~ "g_endpoints[*].crth0/rst0/*/C"}] 24.95
-set_max_delay -from [get_pins -hierarchical -filter {NAME =~ "g_endpoints[*].crfh0/rst0/*/C"}] 24.95
-set_max_delay -from [get_pins -hierarchical -filter {NAME =~ "g_endpoints[*].pcie0/regsync0/register_map_40_control_reg*/C"}] 24.95
-set_max_delay -from [get_pins {g_endpoints[*].decoding0/g_gbtmode.g_GBT_Links[*].g_Egroups[*].PathEnable_reg[*]/C}] 24.95
-set_max_delay -from [get_pins {g_endpoints[*].pcie0/regsync0/rst_soft_40*/C}]  24.95
-set_max_delay -from [get_pins  -hierarchical -filter {NAME =~ "*/rxalign_auto[*].auto_rxrst/AUTO_GBT_RXRST_reg/C"}] 24.95
-set_max_delay -from [get_pins  -hierarchical -filter {NAME =~ "*/QPLL_GEN.GTH_inst[*].RxCdrLock_int_reg[*]/C"}] 24.95
-set_max_delay -from [get_pins  -hierarchical -filter {NAME =~ "*/rxalign_auto[*].rafsm/RxSlide_reg/C"}] 24.95
-set_max_delay -from [get_pins  -hierarchical -filter {NAME =~ "**/rxalign_auto[*].alignment_done_f_reg[*]/C"}] 24.95
-#set_max_delay -from [get_pins {g_endpoints[*].decoding0/g_gbtmode.g_GBT_Links[*].g_Egroups[*].eGroup0/g_Epaths[*].Epath0/toAxis0/g_onebyte.s_axis_reg[tuser][*]*/C}] -to [get_pins {g_endpoints[*].decoding0/g_gbtmode.g_GBT_Links[*].g_Egroups[*].eGroup0/g_Epaths[*].Epath0/toAxis0/fifo0/g_BIF.trunc_sync_v_reg*/D}] 4
-#set_max_delay -from [get_pins {g_endpoints[*].decoding0/g_gbtmode.g_GBT_Links[*].g_Egroups[*].eGroup0/g_Epaths[*].Epath0/toAxis0/g_onebyte.s_axis_reg[tuser][*]*/C}] -to [get_pins {g_endpoints[*].decoding0/g_gbtmode.g_GBT_Links[*].g_Egroups[*].eGroup0/g_Epaths[*].Epath0/toAxis0/fifo0/g_BIF.busy_sync_v_reg*/D}] 4
-
-#Only used so far to report busy.
-set_max_delay -datapath_only -from [get_clocks clk250_clk_wiz_250*] -to [get_clocks clk40_clk_wiz_40_0*] 24.95
-#Used for link alignment.
-set_max_delay -datapath_only -from [get_clocks rxoutclk_out*]  -to [get_clocks clk40_clk_wiz_40_0*] 24.95
-set_max_delay -datapath_only -from [get_clocks clk_adn_160*] -to [get_clocks clk40_clk_wiz_40_0*] 6.237
-set_max_delay -datapath_only -from [get_clocks clk_adn_160*] -to [get_clocks clk_ttc_40*] 6.237
-###TX240 sample TX_FRAME_CLK
-set_multicycle_path 2 -setup -from [get_pins clk0/clk0/inst/mmcme3_adv_inst/CLKOUT0] -to [get_pins -hierarchical -filter {NAME =~ "*timedomaincrossing_C/TX_FRAMECLK_I*/D"}]
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_*] -to [get_clocks clk40_clk_wiz_40_*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_0*] -to [get_clocks clk240_clk_wiz_40_0*] 4.170
+#Exceptions from and to the register map clock
+set_max_delay -datapath_only -from [get_clocks -regexp ^((?!clk_out25_clk_wiz_regmap).)*$] -to [get_clocks clk_out25_clk_wiz_regmap*] 40
+set_max_delay -datapath_only -from [get_clocks clk_out25_clk_wiz_regmap*] -to [get_clocks -regexp ^((?!clk_out25_clk_wiz_regmap).)*$] 40
 
 #switchable output clock can switch at any time
-set_false_path -from [get_clocks clk_adn_160] -to [get_clocks clk160_clk_wiz_40_0]
+set_max_delay -quiet -datapath_only -from [get_clocks clk_adn_160*] -to [get_clocks clk40_clk_wiz_40_0*] 6.238
+set_max_delay -quiet -datapath_only -from [get_clocks clk_adn_160*] -to [get_clocks clk_ttc_40*] 6.238
+set_max_delay -quiet -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks clk_ttc_40*] 24.95
+set_max_delay -quiet -datapath_only -from [get_clocks clk_ttc_40*] -to [get_clocks clk40_clk_wiz_40_0*] 24.95
 
-#RL
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_0*] -to [get_clocks GT_TX_WORD_CLK[*]] 4.170
-set_max_delay -datapath_only -from [get_clocks GT_TX_WORD_CLK[*]] -to [get_clocks clk240_clk_wiz_40_0*] 4.170
+#from timing_constraints
 
 #Multicycle paths in the RxGearbox
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/D" }] 4
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/D" }] 3
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*FelixDescrambler/RX_HEADER_O_reg[*]/D" }] 4
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*FelixDescrambler/RX_HEADER_O_reg[*]/D" }] 3
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*gbtRxDescrambler21bit/feedbackRegister_reg[*]/D" }] 4
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*gbtRxDescrambler21bit/feedbackRegister_reg[*]/D" }] 3
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*error_buf_reg/D" }] 4
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*error_buf_reg/D" }] 3
+set_multicycle_path -quiet -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/D" }] 4
+set_multicycle_path -quiet -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/D" }] 3
+set_multicycle_path -quiet -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*FelixDescrambler/RX_HEADER_O_reg[*]/D" }] 4
+set_multicycle_path -quiet -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*FelixDescrambler/RX_HEADER_O_reg[*]/D" }] 3
+set_multicycle_path -quiet -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*gbtRxDescrambler21bit/feedbackRegister_reg[*]/D" }] 4
+set_multicycle_path -quiet -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*gbtRxDescrambler21bit/feedbackRegister_reg[*]/D" }] 3
+set_multicycle_path -quiet -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*error_buf_reg/D" }] 4
+set_multicycle_path -quiet -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*error_buf_reg/D" }] 3
 
 #TX side
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 2
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 1
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 2
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 1
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 2
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 1
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler32bit_gen[0].gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 3
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler32bit_gen[0].gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 2
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler32bit_gen[1].gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 3
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler32bit_gen[1].gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 2
-
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*tx_buffer_reg[*]/D" }] 2
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*tx_buffer_reg[*]/D" }] 1
-
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*tx_buffer_reg[*]/D" }] 2
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*tx_buffer_reg[*]/D" }] 1
-
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 1
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 1
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 0
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 0
-
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler16bit/RX_EXTRA_DATA_WIDEBUS_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 1
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler16bit/RX_EXTRA_DATA_WIDEBUS_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 0
-
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*FelixDescrambler/RX_HEADER_O_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 1
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*FelixDescrambler/RX_HEADER_O_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 0
-
-##lpgbt
-#set_multicycle_path -setup -from [get_pins -hierarchical -filter {NAME =~ "*LpGBT_FPGA_Uplink_datapath_inst*descrambledData_reg[*]/C"}] 3
-#set_multicycle_path -hold -from [get_pins -hierarchical -filter {NAME =~ "*LpGBT_FPGA_Uplink_datapath_inst*descrambledData_reg[*]/C"}] 2
-
-#set_multicycle_path -setup -from [get_pins -hierarchical -filter {NAME =~ "*LpGBT_Model_dataPath_inst*scrambledData_reg[*]/C"}] 2
-#set_multicycle_path -hold -from [get_pins -hierarchical -filter {NAME =~ "*LpGBT_Model_dataPath_inst*scrambledData_reg[*]/C"}] 1
-
-#set_multicycle_path -setup -from [get_pins -hierarchical -filter { NAME =~ "*LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_pipelined_s_reg[*]/C"}] 3
-#set_multicycle_path -hold -from [get_pins -hierarchical -filter { NAME =~ "*LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_pipelined_s_reg[*]/C"}] 2
-#set_multicycle_path -setup -from [get_pins -hierarchical -filter {NAME =~ "*LpGBT_FPGA_Uplink_datapath_inst*descrambledData_reg[*]/C"}] 3
-#set_multicycle_path -hold -from [get_pins -hierarchical -filter {NAME =~ "*LpGBT_FPGA_Uplink_datapath_inst*descrambledData_reg[*]/C"}] 2
-
-#create_clock -period 3.125 -name LMK0_REFCLK [get_pins g_LPGBTMODE.u2/Reference_Clk_Gen/lmk0_gen/O]
-#create_clock -period 3.125 -name LMK1_REFCLK [get_pins g_LPGBTMODE.u2/Reference_Clk_Gen/lmk1_gen/O]
-#create_clock -period 3.125 -name LMK2_REFCLK [get_pins g_LPGBTMODE.u2/Reference_Clk_Gen/lmk2_gen/O]
-#create_clock -period 3.125 -name LMK3_REFCLK [get_pins g_LPGBTMODE.u2/Reference_Clk_Gen/lmk3_gen/O]
-#create_clock -period 3.125 -name LMK4_REFCLK [get_pins g_LPGBTMODE.u2/Reference_Clk_Gen/lmk4_gen/O]
-#create_clock -period 3.125 -name LMK5_REFCLK [get_pins g_LPGBTMODE.u2/Reference_Clk_Gen/lmk5_gen/O]
-#create_clock -period 3.125 -name LMK6_REFCLK [get_pins g_LPGBTMODE.u2/Reference_Clk_Gen/lmk6_gen/O]
-#create_clock -period 3.125 -name LMK7_REFCLK [get_pins g_LPGBTMODE.u2/Reference_Clk_Gen/lmk7_gen/O]
+set_multicycle_path -quiet -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 2
+set_multicycle_path -quiet -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 1
+set_multicycle_path -quiet -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 2
+set_multicycle_path -quiet -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 1
+set_multicycle_path -quiet -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 2
+set_multicycle_path -quiet -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 1
+set_multicycle_path -quiet -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler32bit_gen[0].gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 3
+set_multicycle_path -quiet -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler32bit_gen[0].gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 2
+set_multicycle_path -quiet -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler32bit_gen[1].gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 3
+set_multicycle_path -quiet -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler32bit_gen[1].gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 2
+
+set_multicycle_path -quiet -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*tx_buffer_reg[*]/D" }] 2
+set_multicycle_path -quiet -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*tx_buffer_reg[*]/D" }] 1
+ 
+set_multicycle_path -quiet -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*tx_buffer_reg[*]/D" }] 2
+set_multicycle_path -quiet -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*tx_buffer_reg[*]/D" }] 1
+ 
+set_multicycle_path -quiet -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 1
+set_multicycle_path -quiet -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 0
+ 
+set_multicycle_path -quiet -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler16bit/RX_EXTRA_DATA_WIDEBUS_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 1
+set_multicycle_path -quiet -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler16bit/RX_EXTRA_DATA_WIDEBUS_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 0
+ 
+set_multicycle_path -quiet -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*FelixDescrambler/RX_HEADER_O_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 1
+set_multicycle_path -quiet -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*FelixDescrambler/RX_HEADER_O_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 0
\ No newline at end of file
diff --git a/constraints/timing_constraints_felig_lpgbt.xdc b/constraints/timing_constraints_felig_lpgbt.xdc
index 24a227c572ca35f898875145c9eac29a7d398208..ad9fd6e48461ee1df9bf7ad54627c66102a2ba24 100644
--- a/constraints/timing_constraints_felig_lpgbt.xdc
+++ b/constraints/timing_constraints_felig_lpgbt.xdc
@@ -1,10 +1,10 @@
+set GTHREFCLK_PERIOD 3.125
+set LMK_PERIOD 4.158
 #create 40 MHz TTC clock. RL: changed to 25 to stop errors in the implementation. this clock is not used in FELIG anyway
 create_clock -name clk_ttc_40 -period 25 [get_pins */ttc_dec/from_cdr_to_AandB/clock_iter/O]
 
-
 create_clock -period 6.25 -name clk_adn_160 [get_ports CLK_TTC_P]
 
-
 create_clock -period 10.000 -name sys_clk0_p -waveform {0.000 5.000} [get_ports {sys_clk_p[0]}]
 create_clock -quiet -period 10.000 -name sys_clk1_p -waveform {0.000 5.000} [get_ports {sys_clk_p[1]}]
 
@@ -12,265 +12,43 @@ create_clock -name emcclk -period 20.000 [get_ports emcclk]
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets emcclk_IBUF_inst/O]
 
-#We need this line when we move to the second SRL
-#MT 4.158 -> 3.119
-create_clock -name GTHREFCLK_0 -period 3.119 [get_ports {GTREFCLK_P_IN[0]}]
-create_clock -quiet -name GTHREFCLK_1 -period 3.119 [get_ports {GTREFCLK_P_IN[1]}]
-create_clock -quiet -name GTHREFCLK_2 -period 3.119 [get_ports {GTREFCLK_P_IN[2]}]
-create_clock -quiet -name GTHREFCLK_3 -period 3.119 [get_ports {GTREFCLK_P_IN[3]}]
-create_clock -quiet -name GTHREFCLK_4 -period 3.119 [get_ports {GTREFCLK_P_IN[4]}]
-
-create_clock -period 4.158 -name LMK0_REFCLK [get_ports {LMK_P[0]}]
-create_clock -period 4.158 -name LMK1_REFCLK [get_ports {LMK_P[1]}]
-create_clock -period 4.158 -name LMK2_REFCLK [get_ports {LMK_P[2]}]
-create_clock -period 4.158 -name LMK3_REFCLK [get_ports {LMK_P[3]}]
-create_clock -period 4.158 -name LMK4_REFCLK [get_ports {LMK_P[4]}]
-create_clock -period 4.158 -name LMK5_REFCLK [get_ports {LMK_P[5]}]
-create_clock -period 4.158 -name LMK6_REFCLK [get_ports {LMK_P[6]}]
-create_clock -period 4.158 -name LMK7_REFCLK [get_ports {LMK_P[7]}]
-
-#linkwrapper0/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[0].GTH_TOP_INST/txoutclk_out[0]
-g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst
-create_clock -name GT_TX_WORD_CLK[0] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[0].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[1] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[0].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[2] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[0].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[3] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[0].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[4] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[1].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[5] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[1].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[6] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[1].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[7] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[1].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[8] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[2].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[9] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[2].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[10] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[2].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[11] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[2].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[12] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[3].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[13] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[3].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[14] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[3].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[15] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[3].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[16] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[4].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[17] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[4].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[18] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[4].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[19] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[4].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[20] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[5].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[21] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[5].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[22] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[5].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[23] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[5].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[24] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[6].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[25] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[6].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[26] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[6].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[27] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[6].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[28] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[7].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[29] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[7].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[30] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[7].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[31] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[7].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[32] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[8].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[33] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[8].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[34] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[8].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[35] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[8].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[36] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[9].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[37] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[9].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[38] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[9].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[39] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[9].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[40] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[10].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[41] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[10].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[42] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[10].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[43] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[10].GTH_TOP_INST/txoutclk_out[3]"}]
-create_clock -name GT_TX_WORD_CLK[44] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[11].GTH_TOP_INST/txoutclk_out[0]"}]
-create_clock -name GT_TX_WORD_CLK[45] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[11].GTH_TOP_INST/txoutclk_out[1]"}]
-create_clock -name GT_TX_WORD_CLK[46] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[11].GTH_TOP_INST/txoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[47] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[11].GTH_TOP_INST/txoutclk_out[3]"}]
-
-#linkwrapper0/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[0].GTH_TOP_INST/rxoutclk_out[0]
-create_clock -name GT_RX_WORD_CLK[0] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[0].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[1] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[0].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[2] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[0].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[3] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[0].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[4] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[1].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[5] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[1].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[6] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[1].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[7] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[1].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[8] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[2].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[9] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[2].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[10] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[2].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[11] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[2].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[12] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[3].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[13] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[3].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[14] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[3].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[15] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[3].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[16] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[4].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[17] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[4].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[18] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[4].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[19] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[4].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[20] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[5].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[21] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[5].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[22] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[5].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[23] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[5].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[24] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[6].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[25] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[6].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[26] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[6].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[27] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[6].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[28] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[7].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[29] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[7].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[30] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[7].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[31] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[7].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[32] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[8].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[33] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[8].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[34] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[8].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[35] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[8].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[36] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[9].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[37] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[9].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[38] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[9].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[39] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[9].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[40] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[10].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[41] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[10].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[42] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[10].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_RX_WORD_CLK[43] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[10].GTH_TOP_INST/rxoutclk_out[3]"}]
-create_clock -name GT_RX_WORD_CLK[44] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[11].GTH_TOP_INST/rxoutclk_out[0]"}]
-create_clock -name GT_RX_WORD_CLK[45] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[11].GTH_TOP_INST/rxoutclk_out[1]"}]
-create_clock -name GT_RX_WORD_CLK[46] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[11].GTH_TOP_INST/rxoutclk_out[2]"}]
-create_clock -name GT_TX_WORD_CLK[47] -period 3.119 [get_pins -hierarchical -filter {NAME =~ "*/g_lpGBTMODE.u2/FLX_LpGBT_FE_INST/mgt_notsim.GTH_inst[11].GTH_TOP_INST/rxoutclk_out[3]"}]
+#GTREFCLKS up to 6, use -quiet for the ones that don't exist due to limited number of channels.
+create_clock -quiet -name GTHREFCLK_0 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[0]}]
+create_clock -quiet -name GTHREFCLK_1 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[1]}]
+create_clock -quiet -name GTHREFCLK_2 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[2]}]
+create_clock -quiet -name GTHREFCLK_3 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[3]}]
+create_clock -quiet -name GTHREFCLK_4 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[4]}]
+create_clock -quiet -name GTHREFCLK_5 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[5]}]
+create_clock -quiet -name GTHREFCLK_6 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[6]}]
+create_clock -quiet -name GTHREFCLK_7 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[7]}]
+create_clock -quiet -name GTHREFCLK_8 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[8]}]
+create_clock -quiet -name GTHREFCLK_9 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[9]}]
+create_clock -quiet -name GTHREFCLK_10 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[10]}]
+create_clock -quiet -name GTHREFCLK_11 -period $GTHREFCLK_PERIOD [get_ports {GTREFCLK_P_IN[11]}]
+
+create_clock -quiet -name LMK0_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[0]}]
+create_clock -quiet -name LMK1_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[1]}]
+create_clock -quiet -name LMK2_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[2]}]
+create_clock -quiet -name LMK3_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[3]}]
+create_clock -quiet -name LMK4_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[4]}]
+create_clock -quiet -name LMK5_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[5]}]
+create_clock -quiet -name LMK6_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[6]}]
+create_clock -quiet -name LMK7_REFCLK -period $LMK_PERIOD [get_ports {LMK_P[7]}]
 
 create_clock -quiet -name i2c_clock_pex -period 2500 [get_pins hk0/g_711_712.pex_init0/data_clk_reg/Q]
 
-#Clock domain crossings within Central Router
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks clk240_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks clk160_clk_wiz_40_0*] 24.950
-
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_0*] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_0*] -to [get_clocks clk80_clk_wiz_40_0*] 12.475
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_0*] -to [get_clocks clk160_clk_wiz_40_0*] 6.238
-
-set_max_delay -datapath_only -from [get_clocks clk160_clk_wiz_40_0*] -to [get_clocks clk240_clk_wiz_40_0*] 6.238
-
-
-#Clock domain crossings in GBT
-set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks {GT_TX_WORD_CLK[*]}] 6.238
-set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks {GT_RX_WORD_CLK[*]}] 6.238
-
-#Clock domain crossings in TTC decoder
-set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks clk_ttc_40] 6.238
-set_max_delay -datapath_only -from [get_clocks clk_ttc_40] -to [get_clocks clk_adn_160] 6.238
+#set_max_delay from timing_constraints.xdc
 
 #Register map to 400kHz I2C clock
-set_max_delay -datapath_only -from [get_clocks *] -to [get_clocks clk400] 100.000
-set_max_delay -datapath_only -from [get_clocks *] -to [get_clocks i2c_clock_pex] 100.000
-
-#Register map to central router clocks
-
-
-#Register map control / monitor
-set_max_delay -datapath_only -from [get_clocks clk_out25*] -to [get_clocks *] 40.000
-set_max_delay -datapath_only -from [get_clocks *] -to [get_clocks clk_out25*] 40.000
-
-#Clock domain crossings in ttc decoder
-set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks clk_ttc_40] 24.95
-
-#Clock domain crossings between Central Router and GBT
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks txoutclk*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks {GT_RX_WORD_CLK[*]}] 24.950
-set_max_delay -datapath_only -from [get_clocks txoutclk*] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks {GT_RX_WORD_CLK[*]}] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks {GT_TX_WORD_CLK[*]}] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks {GT_TX_WORD_CLK[0]}] 6.238
-set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-#MT more aggressive for lpgbt
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks {GT_TX_WORD_CLK[*]}] 24.950
-
-# added #FELIG
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks clk10_clk_wiz_200_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_200_0*] -to [get_clocks {GT_TX_WORD_CLK[*]}] 24.950
-set_max_delay -datapath_only -from [get_clocks GT_TX_WORD_CLK[*]] -to [get_clocks {GT_RX_WORD_CLK[*]}] 3.119
-set_max_delay -datapath_only -from [get_clocks GT_TX_WORD_CLK[*]] -to [get_clocks {GT_TX_WORD_CLK[*]}] 3.119
-set_max_delay -datapath_only -from [get_clocks GT_RX_WORD_CLK[*]] -to [get_clocks {GT_RX_WORD_CLK[*]}] 3.119
-set_max_delay -datapath_only -from [get_clocks clk_out1_rxclkgen] -to [get_clocks {GT_RX_WORD_CLK[*]}] 3.119
-
-
-#set_max_delay -from [get_pins -hierarchical -filter {NAME =~ "g_endpoints[*].crth0/rst0/*/C"}] 24.95
-#set_max_delay -from [get_pins -hierarchical -filter {NAME =~ "g_endpoints[*].crfh0/rst0/*/C"}] 24.95
-set_max_delay -from [get_pins -hierarchical -filter {NAME =~ "g_endpoints[*].pcie0/regsync0/register_map_40_control_reg*/C"}] 24.95
-set_max_delay -from [get_pins {g_endpoints[*].decoding0/g_gbtmode.g_GBT_Links[*].g_Egroups[*].PathEnable_reg[*]/C}] 24.95
-set_max_delay -from [get_pins {g_endpoints[*].pcie0/regsync0/rst_soft_40*/C}]  24.95
+set_max_delay -quiet -datapath_only -from [get_clocks -regexp ^((?!clk400).)*$] -to [get_clocks clk400] 100.000
+set_max_delay -quiet -datapath_only -from [get_clocks -regexp ^((?!i2c_clock_pex).)*$] -to [get_clocks i2c_clock_pex] 100.000
 
-#Only used so far to report busy.
-set_max_delay -datapath_only -from [get_clocks clk250_clk_wiz_250*] -to [get_clocks clk40_clk_wiz_40_0*] 24.95
-#Used for link alignment.
-set_max_delay -datapath_only -from [get_clocks rxoutclk_out*]  -to [get_clocks clk40_clk_wiz_40_0*] 24.95
-set_max_delay -datapath_only -from [get_clocks clk_adn_160*] -to [get_clocks clk40_clk_wiz_40_0*] 6.238
-#MT added
-set_max_delay -datapath_only -from [get_clocks rxoutclk_out*]  -to [get_clocks clk_out25_clk_wiz_regmap*] 40.00
-set_max_delay -datapath_only -from [get_clocks txoutclk_out*]  -to [get_clocks clk_out25_clk_wiz_regmap*] 40.00
-#
-set_max_delay -datapath_only -from [get_clocks clk_adn_160*] -to [get_clocks clk_ttc_40*] 6.238
-###TX240 sample TX_FRAME_CLK
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_*] -to [get_clocks clk40_clk_wiz_40_*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_0*] -to [get_clocks clk240_clk_wiz_40_0*] 4.170
+#Exceptions from and to the register map clock
+set_max_delay -datapath_only -from [get_clocks -regexp ^((?!clk_out25_clk_wiz_regmap).)*$] -to [get_clocks clk_out25_clk_wiz_regmap*] 40
+set_max_delay -datapath_only -from [get_clocks clk_out25_clk_wiz_regmap*] -to [get_clocks -regexp ^((?!clk_out25_clk_wiz_regmap).)*$] 40
 
 #switchable output clock can switch at any time
-set_false_path -from [get_clocks clk_adn_160] -to [get_clocks clk160_clk_wiz_40_0]
-
-
-
-#lpgbt
-#set_multicycle_path -setup -from [get_pins -hierarchical -filter { NAME=~ "linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/gbtRxTx[*].lpgbt_inst/lpgbtfpga_uplink_fec*_inst/frame_pipelined_s_reg[*]/C" }] 3
-#set_multicycle_path -hold -from [get_pins -hierarchical -filter { NAME=~ "linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/gbtRxTx[*].lpgbt_inst/lpgbtfpga_uplink_fec*_inst/frame_pipelined_s_reg[*]/C" }] 2
-#set_multicycle_path -setup -from [get_pins -hierarchical -filter {NAME =~ */lpgbtfpga_uplink_fec*_inst/*descrambledData_reg[*]/C }] 3
-#set_multicycle_path -hold -from [get_pins -hierarchical -filter {NAME =~ */lpgbtfpga_uplink_fec*_inst/*descrambledData_reg[*]/C }] 2
-
-#lpgbt downlink
-#set_multicycle_path 3 -setup -from [get_pins clk0/clk0/inst/mmcme3_adv_inst/CLKOUT0] -to [get_pins -hierarchical -filter {NAME =~ "linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/gbtRxTx[*].lpgbt_inst/TXCLK40_r_reg/D"}]
-#set_multicycle_path 2 -hold -from [get_pins clk0/clk0/inst/mmcme3_adv_inst/CLKOUT0] -to [get_pins -hierarchical -filter {NAME =~ "linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/gbtRxTx[*].lpgbt_inst/TXCLK40_r_reg/D"}]
-#set_multicycle_path 3 -setup -from [get_pins clk0/clk0/inst/mmcme3_adv_inst/CLKOUT0] -to [get_pins -hierarchical -filter {NAME =~ "linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/gbtRxTx[*].lpgbt_inst/cnt_reg[*]/R"}]
-#set_multicycle_path 2 -hold -from [get_pins clk0/clk0/inst/mmcme3_adv_inst/CLKOUT0] -to [get_pins -hierarchical -filter {NAME =~ "linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/gbtRxTx[*].lpgbt_inst/cnt_reg[*]/R"}]
-
-
-#create_clock -period 3.119 -name LMK0_REFCLK [get_ports {LMK_P[0]}]
-#create_clock -period 3.119 -name LMK1_REFCLK [get_ports {LMK_P[1]}]
-#create_clock -period 3.119 -name LMK2_REFCLK [get_ports {LMK_P[2]}]
-#create_clock -period 3.119 -name LMK3_REFCLK [get_ports {LMK_P[3]}]
-#create_clock -period 3.119 -name LMK4_REFCLK [get_ports {LMK_P[4]}]
-#create_clock -period 3.119 -name LMK5_REFCLK [get_ports {LMK_P[5]}]
-#create_clock -period 3.119 -name LMK6_REFCLK [get_ports {LMK_P[6]}]
-#create_clock -period 3.119 -name LMK7_REFCLK [get_ports {LMK_P[7]}]
-
-#######################
-
-##RL NEW
-#set_max_delay -datapath_only -from [get_clocks clk320_clk_wiz_40_0*] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-#set_max_delay -datapath_only -from [get_clocks clk320_clk_wiz_40_0*] -to [get_clocks clk80_clk_wiz_40_0*] 12.475
-#set_max_delay -datapath_only -from [get_clocks clk320_clk_wiz_40_0*] -to [get_clocks clk160_clk_wiz_40_0*] 6.238
-#set_max_delay -datapath_only -from [get_clocks clk320_clk_wiz_40_0*] -to [get_clocks clk240_clk_wiz_40_0*] 4.170
-
-#set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks clk320_clk_wiz_40_0*] 24.950
-#set_max_delay -datapath_only -from [get_clocks clk80_clk_wiz_40_0*] -to [get_clocks clk320_clk_wiz_40_0*] 12.475
-#set_max_delay -datapath_only -from [get_clocks clk160_clk_wiz_40_0*] -to [get_clocks clk320_clk_wiz_40_0*] 6.238
-#set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_0*] -to [get_clocks clk320_clk_wiz_40_0*] 4.170
-
-#set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks clk250_clk_wiz_40_0*] 24.950
-
-set_max_delay -datapath_only -from [get_clocks clk10_clk_wiz_200_*] -to [get_clocks clk40_clk_wiz_200_*] 100
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_200_*] -to [get_clocks clk10_clk_wiz_200_*] 100
-
-set_max_delay -datapath_only -from [get_clocks GT_TX_WORD_CLK[*]] -to [get_clocks clk40_clk_wiz_200_*] 25
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_200_*] -to [get_clocks GT_TX_WORD_CLK[*]] 25
-
-#RL
-set_max_delay -datapath_only -from [get_clocks clk320_clk_wiz_40_0*] -to [get_clocks GT_TX_WORD_CLK[*]] 3.125
-set_max_delay -datapath_only -from [get_clocks GT_TX_WORD_CLK[*]] -to [get_clocks clk320_clk_wiz_40_0*] 3.125
-set_max_delay -datapath_only -from [get_clocks clk320_clk_wiz_40_0*] -to [get_clocks clk320_clk_wiz_40_0*] 3.125
-
-set_max_delay -datapath_only -from [get_clocks GT_RX_WORD_CLK[*]] -to [get_clocks {clk_out1_rxclkgen}] 3.125
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks clk40_clk_wiz_200_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks clk_out1_rxclkgen*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk_out1_rxclkgen*] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-
-
-#RL getting 40MHz for tx
-set_max_delay -datapath_only -from [get_clocks GT_TX_WORD_CLK[*]] -to [get_clocks {txclk40m*}] 24.950
-set_max_delay -datapath_only -from [get_clocks {txclk40m*}] -to [get_clocks GT_TX_WORD_CLK[*]] 24.950
-
-#set_max_delay -datapath_only -from [get_clocks GT_TX_WORD_CLK[*]] -to [get_clocks {ila_tx40MHz}] 24.950
-#set_max_delay -datapath_only -from [get_clocks {ila_tx40MHz}] -to [get_clocks GT_TX_WORD_CLK[*]] 24.950
-
-#set_max_delay -datapath_only -from [get_clocks GT_TX_WORD_CLK[*]] -to [get_clocks {ila_tx320MHz}] 3.125
-#set_max_delay -datapath_only -from [get_clocks {ila_tx320MHz}] -to [get_clocks GT_TX_WORD_CLK[*]] 3.125
+set_max_delay -quiet -datapath_only -from [get_clocks clk_adn_160*] -to [get_clocks clk40_clk_wiz_40_0*] 6.238
+set_max_delay -quiet -datapath_only -from [get_clocks clk_adn_160*] -to [get_clocks clk_ttc_40*] 6.238
+set_max_delay -quiet -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks clk_ttc_40*] 24.95
+set_max_delay -quiet -datapath_only -from [get_clocks clk_ttc_40*] -to [get_clocks clk40_clk_wiz_40_0*] 24.95
diff --git a/constraints/timing_constraints_kufelig.xdc b/constraints/timing_constraints_kufelig.xdc
deleted file mode 100644
index d4f91b5eb0efd2cda5edc50fe400cdce2c581ab1..0000000000000000000000000000000000000000
--- a/constraints/timing_constraints_kufelig.xdc
+++ /dev/null
@@ -1,140 +0,0 @@
-#create 40 MHz TTC clock
-create_clock -period 24.950 -name clk_ttc_40 [get_pins *u2/ttc_dec/from_cdr_to_AandB/ttcclk_reg/Q]
-
-create_clock -period 6.237 -name ts_clk_adn_160 [get_nets clk_adn_160]
-set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_adn_160_BUFG]
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets emcclk_buf/O]
-create_clock -period 4.166 -name cdrclk_in [get_pins g1.u2/ibufds_instq2_clk0/O]
-create_clock -period 4.166 -name CXP2_GTH_RefClk [get_pins g1.u2/ibufds_instq8_clk0/O]
-#SS
-create_clock -period 4.166 -name CXP1_GTH_RefClk_LMK [get_pins g1.u2/ibufds_LMK1/O] 
-create_clock -period 4.166 -name CXP2_GTH_RefClk_LMK [get_pins g1.u2/ibufds_LMK2/O] 
-
-create_clock -period 4.166 -name CXP3_GTH_RefClk [get_pins g1.u2/ibufds_instq4_clk0/O]
-create_clock -period 4.166 -name CXP4_GTH_RefClk [get_pins g1.u2/ibufds_instq5_clk0/O]
-create_clock -period 4.166 -name CXP5_GTH_RefClk [get_pins g1.u2/refclkgen_v2p0.g_refclk12.ibufds_instq6_clk0/O]
-
-#Clock domain crossings within Central Router
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks clk240_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_0*] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_0*] -to [get_clocks clk80_clk_wiz_40_0*] 12.475
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_0*] -to [get_clocks clk160_clk_wiz_40_0*] 6.237
-
-set_max_delay -datapath_only -from [get_clocks clk160_clk_wiz_40_0*] -to [get_clocks clk240_clk_wiz_40_0*] 4.170
-set_max_delay -from [get_pins */rst0/cr_rst_rr_reg*/C] -to [get_clocks clk160_clk_wiz_40_0*] 6.237
-
-#Clock domain crossings in GBT
-set_max_delay -datapath_only -from [get_clocks ts_clk_adn_160] -to [get_clocks {GT_TX_WORD_CLK[*]}] 6.237
-set_max_delay -datapath_only -from [get_clocks ts_clk_adn_160] -to [get_clocks {GT_RX_WORD_CLK[*]}] 6.237
-
-#Clock domain crossings in TTC decoder
-set_max_delay -datapath_only -from [get_clocks ts_clk_adn_160] -to [get_clocks clk_ttc_40] 6.237
-set_max_delay -datapath_only -from [get_clocks clk_ttc_40] -to [get_clocks ts_clk_adn_160] 6.237
-set_max_delay -from [get_pins u2/ttc_dec/from_cdr_to_AandB/ttcclk_reg/Q] -to [get_pins u2/ttc_dec/from_cdr_to_AandB/ttcclk_reg/D] 6.237
-
-#Clock domain crossings between Wupper and Central Router
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_*] -to [get_clocks *rd_clk] 4.000
-
-
-#Register map to 400kHz I2C clock
-set_max_delay -datapath_only -from [get_clocks *] -to [get_clocks clk400] 100.000
-
-#Register map to central router clocks
-set_max_delay -datapath_only -from [get_clocks *rd_clk] -to [get_clocks clk80_clk_wiz_40_0*] 12.475
-
-
-#Register map control / monitor
-set_max_delay -datapath_only -from [get_clocks clk_out25*] -to [get_clocks *] 40.000
-set_max_delay -datapath_only -from [get_clocks *] -to [get_clocks clk_out25*] 40.000
-
-#Clock domain crossings in ttc decoder
-set_max_delay -datapath_only -from [get_clocks ts_clk_adn_160] -to [get_clocks clk_ttc_40] 24.95
-
-#Clock domain crossings between Central Router and GBT
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks txoutclk*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks {GT_RX_WORD_CLK[*]}] 24.950
-set_max_delay -datapath_only -from [get_clocks txoutclk*] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks {GT_RX_WORD_CLK[*]}] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks {GT_TX_WORD_CLK[*]}] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks ts_clk_adn_160] -to [get_clocks {GT_TX_WORD_CLK[0]}] 6.237
-set_max_delay -datapath_only -from [get_clocks ts_clk_adn_160] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk_adn_160] -to [get_clocks clk40_clk_wiz_40_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks {GT_TX_WORD_CLK[*]}] 24.950
-# added SS
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_40_0*] -to [get_clocks clk10_clk_wiz_200_0*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk40_clk_wiz_200_0*] -to [get_clocks {GT_TX_WORD_CLK[*]}] 24.950
-# RL
-set_max_delay -datapath_only -from [get_clocks GT_TX_WORD_CLK[*]] -to [get_clocks {GT_RX_WORD_CLK[*]}] 4.170
-
-###TX240 sample TX_FRAME_CLK
-set_multicycle_path 2 -setup -from [get_pins clk0/clk0/inst/mmcme3_adv_inst/CLKOUT0] -to [get_pins -hierarchical -filter {NAME =~ "*timedomaincrossing_C/TX_FRAMECLK_I*/D"}]
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_*] -to [get_clocks clk40_clk_wiz_40_*] 24.950
-set_max_delay -datapath_only -from [get_clocks clk240_clk_wiz_40_0*] -to [get_clocks clk240_clk_wiz_40_0*] 4.170
-
-#switchable output clock can switch at any time
-set_false_path -from [get_clocks ts_clk_adn_160] -to [get_clocks clk160_clk_wiz_40_0]
-
-#Multicycle paths towards Wupper fifos
-set_multicycle_path -setup -start 3 -from [ get_pins pcie1/dma0/u0/fromHostFifo_din_reg[*]/C ] -to [ get_pins fromHostFifo1_din_pipe_reg[*]/D ]
-set_multicycle_path -hold  -end   2 -from [ get_pins pcie1/dma0/u0/fromHostFifo_din_reg[*]/C ] -to [ get_pins fromHostFifo1_din_pipe_reg[*]/D ]
-
-set_multicycle_path -setup -start 3 -from [ get_pins pcie1/dma0/u0/fromHostFifo_we_reg/C ] -to [ get_pins fromHostFifo1_wr_en_pipe_reg/D ]
-set_multicycle_path -hold  -end   2 -from [ get_pins pcie1/dma0/u0/fromHostFifo_we_reg/C ] -to [ get_pins fromHostFifo1_wr_en_pipe_reg/D ]
-
-set_multicycle_path -setup -start 3 -from [ get_pins cr1/cr_data_out_rdy_reg/C ] -to [ get_pins toHostFifo1_wr_en_pipe_reg/D]
-set_multicycle_path -hold  -end   2 -from [ get_pins cr1/cr_data_out_rdy_reg/C ] -to [ get_pins toHostFifo1_wr_en_pipe_reg/D]
-
-set_multicycle_path -setup -start 3 -from [ get_pins cr1/cr_data_out_reg[*]/C ] -to [ get_pins toHostFifo1_din_pipe_reg[*]/D]
-set_multicycle_path -hold  -end   2 -from [ get_pins cr1/cr_data_out_reg[*]/C ] -to [ get_pins toHostFifo1_din_pipe_reg[*]/D]
-
-set_multicycle_path -setup -start 3 -from [ get_pins pcie0/dma0/u0/fromHostFifo_din_reg[*]/C ] -to [ get_pins fromHostFifo0_din_pipe_reg[*]/D ]
-set_multicycle_path -hold  -end   2 -from [ get_pins pcie0/dma0/u0/fromHostFifo_din_reg[*]/C ] -to [ get_pins fromHostFifo0_din_pipe_reg[*]/D ]
-
-set_multicycle_path -setup -start 3 -from [ get_pins pcie0/dma0/u0/fromHostFifo_we_reg/C ] -to [ get_pins fromHostFifo0_wr_en_pipe_reg/D ]
-set_multicycle_path -hold  -end   2 -from [ get_pins pcie0/dma0/u0/fromHostFifo_we_reg/C ] -to [ get_pins fromHostFifo0_wr_en_pipe_reg/D ]
-
-set_multicycle_path -setup -start 3 -from [ get_pins cr0/cr_data_out_rdy_reg/C ] -to [ get_pins toHostFifo0_wr_en_pipe_reg/D]
-set_multicycle_path -hold  -end   2 -from [ get_pins cr0/cr_data_out_rdy_reg/C ] -to [ get_pins toHostFifo0_wr_en_pipe_reg/D]
-
-set_multicycle_path -setup -start 3 -from [ get_pins cr0/cr_data_out_reg[*]/C ] -to [ get_pins toHostFifo0_din_pipe_reg[*]/D]
-set_multicycle_path -hold  -end   2 -from [ get_pins cr0/cr_data_out_reg[*]/C ] -to [ get_pins toHostFifo0_din_pipe_reg[*]/D]
-
-
-#Multicycle paths in the RxGearbox
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/D" }] 4
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/D" }] 3
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*FelixDescrambler/RX_HEADER_O_reg[*]/D" }] 4
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*FelixDescrambler/RX_HEADER_O_reg[*]/D" }] 3
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*gbtRxDescrambler21bit/feedbackRegister_reg[*]/D" }] 4
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*gbtRxDescrambler21bit/feedbackRegister_reg[*]/D" }] 3
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*error_buf_reg/D" }] 4
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*FelixRxGearbox/reg_inv_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*error_buf_reg/D" }] 3
-
-#TX side
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 2
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 1
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 2
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 1
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 2
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 1
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler32bit_gen[0].gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 3
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler32bit_gen[0].gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 2
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler32bit_gen[1].gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 3
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler32bit_gen[1].gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*TX_WORD_O_reg[*]/D" }] 2
-
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*tx_buffer_reg[*]/D" }] 2
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler21bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*tx_buffer_reg[*]/D" }] 1
-
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*tx_buffer_reg[*]/D" }] 2
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtTxScrambler16bit/feedbackRegister_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*tx_buffer_reg[*]/D" }] 1
-
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 1
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 1
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 0
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler21bit/RX_DATA_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 0
-
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler16bit/RX_EXTRA_DATA_WIDEBUS_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 1
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*gbtRxDescrambler16bit/RX_EXTRA_DATA_WIDEBUS_I_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 0
-
-set_multicycle_path -setup -start -from [get_pins -hierarchical -filter { NAME =~  "*FelixDescrambler/RX_HEADER_O_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 1
-set_multicycle_path -hold -end -from [get_pins -hierarchical -filter { NAME =~  "*FelixDescrambler/RX_HEADER_O_reg[*]/C" }] -to [get_pins -hierarchical -filter { NAME =~ "*s_rx_120b_out_f00_reg[*]/D" }] 0
diff --git a/scripts/FELIX_top/FLX712_FELIG_import_vivado.tcl b/scripts/FELIX_top/FLX712_FELIG_import_vivado.tcl
index bcc938854fc93ec47889fc737948b3404e61f372..1896ddccd0593206d9e5ca0e4394eb1d1dc29102 100644
--- a/scripts/FELIX_top/FLX712_FELIG_import_vivado.tcl
+++ b/scripts/FELIX_top/FLX712_FELIG_import_vivado.tcl
@@ -28,8 +28,8 @@ source ../helper/clear_filesets.tcl
 set PROJECT_NAME FLX712_FELIG
 set BOARD_TYPE 712
 set TOPLEVEL felig_top_bnl712
-set TOPLEVEL_SIM felig_sim_top_bnl712
-set VIVADO_ADD_SIM_FILES true
+#set TOPLEVEL_SIM felig_sim_top_bnl712
+set VIVADO_ADD_SIM_FILES false
 
 #Import blocks for different filesets
 #source ../filesets/fullmode_toplevel_fileset.tcl
@@ -42,6 +42,8 @@ source ../filesets/wupper_fileset.tcl
 source ../filesets/gbt_core_fileset.tcl
 #source ../filesets/fullmode_gbt_core_fileset.tcl
 source ../filesets/lpgbt_fe_core_fileset.tcl
+#import lpgbt_core_fileset.tcl for simulation purposes
+#source ../filesets/lpgbt_core_fileset.tcl
 source ../filesets/housekeeping_fileset.tcl
 #source ../filesets/housekeeping_felig_fileset.tcl
 source ../filesets/gbt_fanout_fileset.tcl
diff --git a/scripts/FELIX_top/ci-felig-lpgbt.sh b/scripts/FELIX_top/ci-felig-lpgbt.sh
index cf008728efc069a47075a7abb159dcff9675c5e3..2af1ea401143b37a2e4117886ce8940919c81439 100755
--- a/scripts/FELIX_top/ci-felig-lpgbt.sh
+++ b/scripts/FELIX_top/ci-felig-lpgbt.sh
@@ -32,7 +32,7 @@ else
 fi
 
 vivado -mode batch -nojournal -nolog -notrace -source FLX712_FELIG_import_vivado.tcl
-vivado -mode batch -nojournal -nolog -notrace ../../Projects/FLX712_FELIG/FLX712_FELIG.xpr -source do_implementation_BNL712_FELIG_LPGBT.tcl 
+vivado -mode batch -nojournal -nolog -notrace ../../Projects/FLX712_FELIG/FLX712_FELIG.xpr -source do_implementation_BNL712_FELIG_LPGBT_24ch.tcl 
 
 cd ../../output
 rm -f *.bit
diff --git a/scripts/FELIX_top/ci-felig.sh b/scripts/FELIX_top/ci-felig.sh
index d82445c8fa6e69d901f0ca3cd8933facdb8bfa9e..9925348acaea33837d063222fe7375a49ba31f76 100755
--- a/scripts/FELIX_top/ci-felig.sh
+++ b/scripts/FELIX_top/ci-felig.sh
@@ -32,7 +32,7 @@ else
 fi
 
 vivado -mode batch -nojournal -nolog -notrace -source FLX712_FELIG_import_vivado.tcl
-vivado -mode batch -nojournal -nolog -notrace ../../Projects/FLX712_FELIG/FLX712_FELIG.xpr -source do_implementation_BNL712_FELIG.tcl 
+vivado -mode batch -nojournal -nolog -notrace ../../Projects/FLX712_FELIG/FLX712_FELIG.xpr -source do_implementation_BNL712_FELIG_GBT_24ch.tcl 
 
 cd ../../output
 rm -f *.bit
diff --git a/scripts/FELIX_top/do_implementation_BNL712_FELIG_GBT_24ch.tcl b/scripts/FELIX_top/do_implementation_BNL712_FELIG_GBT_24ch.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b2318059f2fedb548542e2fea092920f5ebfa70e
--- /dev/null
+++ b/scripts/FELIX_top/do_implementation_BNL712_FELIG_GBT_24ch.tcl
@@ -0,0 +1,77 @@
+
+# This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+# Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+# Authors:
+#               Andrea Borga
+#               Kai Chen
+#               Weihao Wu
+#               RHabraken
+#               Frans Schreuder
+#               Israel Grayzman
+#               Shelfali Saxena
+#               mtrovato
+#               Ricardo Luz
+# 
+#   Licensed under the Apache License, Version 2.0 (the "License");
+#   you may not use this file except in compliance with the License.
+#   You may obtain a copy of the License at
+#
+#       http://www.apache.org/licenses/LICENSE-2.0
+#
+#   Unless required by applicable law or agreed to in writing, software
+#   distributed under the License is distributed on an "AS IS" BASIS,
+#   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#   See the License for the specific language governing permissions and
+#   limitations under the License.
+
+#to be adapted to FELIG
+source ../helper/do_implementation_pre.tcl
+
+#set STOP_TO_ADD_ILA to 1 in order to stop after synthesis phase and add an ILA
+set STOP_TO_ADD_ILA 0
+
+set GBT_NUM 24
+set OPTO_TRX 4
+set CARD_TYPE 712
+set app_clk_freq 200
+set ENDPOINTS 2
+set GTREFCLKS 5
+
+set PLL_SEL $QPLL 
+
+#determine the FIRMWARE_MODE register value
+# 6: FELIG GBT
+# 11: FELIG lpGBT
+set FIRMWARE_MODE $FIRMWARE_MODE_FELIG_GBT
+
+# Defining the Egroup's capabilities
+if {$FIRMWARE_MODE == $FIRMWARE_MODE_FELIG_GBT} {
+    set IncludeDecodingEpath2_HDLC   7'b0011111 
+    set IncludeDecodingEpath2_8b10b  7'b0011111
+    set IncludeDecodingEpath4_8b10b  7'b0011111
+    set IncludeDecodingEpath8_8b10b  7'b0011111
+    set IncludeDecodingEpath16_8b10b 7'b0000000
+    set IncludeDecodingEpath32_8b10b 7'b0000000
+#
+    set IncludeEncodingEpath2_HDLC   5'b00000 
+    set IncludeEncodingEpath2_8b10b  5'b00000
+    set IncludeEncodingEpath4_8b10b  5'b00000
+    set IncludeEncodingEpath8_8b10b  5'b00000
+}
+#look into
+if {$FIRMWARE_MODE == $FIRMWARE_MODE_FELIG_LPGBT} {
+    set IncludeDecodingEpath2_HDLC   7'b0000000
+    set IncludeDecodingEpath2_8b10b  7'b0000000
+    set IncludeDecodingEpath4_8b10b  7'b0000000
+    set IncludeDecodingEpath8_8b10b  7'b0000000
+    set IncludeDecodingEpath16_8b10b 7'b0000000
+    set IncludeDecodingEpath32_8b10b 7'b0000000
+#
+    set IncludeEncodingEpath2_HDLC   5'b00000
+    set IncludeEncodingEpath2_8b10b  5'b00000
+    set IncludeEncodingEpath4_8b10b  5'b00000
+    set IncludeEncodingEpath8_8b10b  5'b00000
+}
+
+source ../helper/do_implementation_post.tcl
+
diff --git a/scripts/FELIX_top/do_implementation_BNL712_FELIG.tcl b/scripts/FELIX_top/do_implementation_BNL712_FELIG_GBT_4ch.tcl
similarity index 100%
rename from scripts/FELIX_top/do_implementation_BNL712_FELIG.tcl
rename to scripts/FELIX_top/do_implementation_BNL712_FELIG_GBT_4ch.tcl
diff --git a/scripts/FELIX_top/do_implementation_BNL712_FELIG_LPGBT_24ch.tcl b/scripts/FELIX_top/do_implementation_BNL712_FELIG_LPGBT_24ch.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..684aa8b567915ed9ab7f610b5a7e229f1ff7dce3
--- /dev/null
+++ b/scripts/FELIX_top/do_implementation_BNL712_FELIG_LPGBT_24ch.tcl
@@ -0,0 +1,76 @@
+
+# This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
+# Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
+# Authors:
+#               Andrea Borga
+#               Kai Chen
+#               Weihao Wu
+#               RHabraken
+#               Frans Schreuder
+#               Israel Grayzman
+#               Shelfali Saxena
+#               mtrovato
+#               Ricardo Luz
+# 
+#   Licensed under the Apache License, Version 2.0 (the "License");
+#   you may not use this file except in compliance with the License.
+#   You may obtain a copy of the License at
+#
+#       http://www.apache.org/licenses/LICENSE-2.0
+#
+#   Unless required by applicable law or agreed to in writing, software
+#   distributed under the License is distributed on an "AS IS" BASIS,
+#   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#   See the License for the specific language governing permissions and
+#   limitations under the License.
+
+#to be adapted to FELIG
+source ../helper/do_implementation_pre.tcl
+
+#set STOP_TO_ADD_ILA to 1 in order to stop after synthesis phase and add an ILA
+set STOP_TO_ADD_ILA 0
+
+set GBT_NUM 24
+set OPTO_TRX 4
+set CARD_TYPE 712
+set app_clk_freq 200
+set ENDPOINTS 2
+set GTREFCLKS 5
+
+set PLL_SEL $QPLL 
+
+#determine the FIRMWARE_MODE register value
+# 6: FELIG GBT
+# 11: FELIG lpGBT
+set FIRMWARE_MODE $FIRMWARE_MODE_FELIG_LPGBT
+
+# Defining the Egroup's capabilities
+if {$FIRMWARE_MODE == $FIRMWARE_MODE_FELIG_GBT} {
+    set IncludeDecodingEpath2_HDLC   7'b0011111 
+    set IncludeDecodingEpath2_8b10b  7'b0011111
+    set IncludeDecodingEpath4_8b10b  7'b0011111
+    set IncludeDecodingEpath8_8b10b  7'b0011111
+    set IncludeDecodingEpath16_8b10b 7'b0000000
+    set IncludeDecodingEpath32_8b10b 7'b0000000
+#
+    set IncludeEncodingEpath2_HDLC   5'b00000 
+    set IncludeEncodingEpath2_8b10b  5'b00000
+    set IncludeEncodingEpath4_8b10b  5'b00000
+    set IncludeEncodingEpath8_8b10b  5'b00000
+}
+#look into
+if {$FIRMWARE_MODE == $FIRMWARE_MODE_FELIG_LPGBT} {
+    set IncludeDecodingEpath2_HDLC   7'b1111111
+    set IncludeDecodingEpath2_8b10b  7'b0000000
+    set IncludeDecodingEpath4_8b10b  7'b0000000
+    set IncludeDecodingEpath8_8b10b  7'b1111111
+    set IncludeDecodingEpath16_8b10b 7'b1111111
+    set IncludeDecodingEpath32_8b10b 7'b1111111
+#
+    set IncludeEncodingEpath2_HDLC   5'b00000
+    set IncludeEncodingEpath2_8b10b  5'b00000
+    set IncludeEncodingEpath4_8b10b  5'b00000
+    set IncludeEncodingEpath8_8b10b  5'b00000
+}
+
+source ../helper/do_implementation_post.tcl
diff --git a/scripts/FELIX_top/do_implementation_BNL712_FELIG_LPGBT.tcl b/scripts/FELIX_top/do_implementation_BNL712_FELIG_LPGBT_4ch.tcl
similarity index 100%
rename from scripts/FELIX_top/do_implementation_BNL712_FELIG_LPGBT.tcl
rename to scripts/FELIX_top/do_implementation_BNL712_FELIG_LPGBT_4ch.tcl
diff --git a/scripts/filesets/felig_fileset.tcl b/scripts/filesets/felig_fileset.tcl
index dc381470a2f1ad90d96630360ac49662c34db0c1..0f9157bea4c9efd9acae9050d082abb740e1e7a2 100644
--- a/scripts/filesets/felig_fileset.tcl
+++ b/scripts/filesets/felig_fileset.tcl
@@ -41,7 +41,6 @@ set VHDL_FILES [concat $VHDL_FILES \
   FELIG/PRandomDGen/randomd_gen.vhd \
   FELIG/felix_modified/centralRouter/upstreamEpathFifoWrap_felig.vhd \
   ttc/ttc_decoder/TTC_hamming_decoder_alme.vhd \
-  FELIG/housekeeping/housekeeping_module_FELIG.vhd \
   FELIG/data_generator/elink_printer_v2.vhd \
   FELIG/data_generator/elink_printer_bit_feeder_v2.vhd \
   FELIG/aurora/64b66b_encoding.vhd \
@@ -101,6 +100,7 @@ set VHDL_FILES_KU [concat $VHDL_FILES_KU \
   FELIG/LinkWrapper/FLX_LpGBT_FE_Wrapper_FELIG.vhd\
   FELIG/LinkWrapper/FLX_LpGBT_GTH_FE_FELIG.vhd\
   LpGBT/LpGBT_FELIX/FLX_LpGBT_FE.vhd\
+  FELIG/LinkWrapper/LMK_FELIG_wrapper.vhd\
   FelixTop/felig_top_bnl712.vhd]
 
 set XCI_FILES_KU [concat $XCI_FILES_KU \
diff --git a/simulation/FELIG/felig_lpgbt_sim.vhd b/simulation/FELIG/felig_lpgbt_sim.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2239a7bc4919815e65a3a3bf3a9d850450718807
--- /dev/null
+++ b/simulation/FELIG/felig_lpgbt_sim.vhd
@@ -0,0 +1,311 @@
+
+library IEEE;
+    use IEEE.STD_LOGIC_1164.ALL;
+
+library ieee;
+    use ieee.std_logic_1164.all;
+    use IEEE.NUMERIC_STD.ALL;
+    use ieee.numeric_std_unsigned.all;
+
+library UNISIM;
+    use UNISIM.VComponents.all;
+
+    use work.FELIX_package.all;
+    use work.centralRouter_package.all;
+    use work.pcie_package.all;
+
+entity felig_lpgbt_sim is
+    generic(
+        CARD_TYPE       : integer := 712;
+        GBT_NUM         : integer := 4
+    );
+end felig_lpgbt_sim;
+
+architecture Behavioral of felig_lpgbt_sim is
+
+    component clk_wiz_40_0 -- @suppress "Component declaration is not equal to its matching entity"
+        port(
+            clk_in2    : in  STD_LOGIC;
+            clk_in_sel : in  STD_LOGIC;
+            clk40      : out STD_LOGIC;
+            clk80      : out STD_LOGIC;
+            clk160     : out STD_LOGIC;
+            clk320     : out STD_LOGIC;
+            clk240     : out STD_LOGIC;
+            clk100     : out STD_LOGIC;
+            reset      : in  STD_LOGIC;
+            locked     : out STD_LOGIC;
+            clk_40_in  : in  STD_LOGIC
+        );
+    end component clk_wiz_40_0;
+    signal clk40                : std_logic;
+    signal clk40_in             : std_logic;
+    signal clk160               : std_logic;
+    signal clk240               : std_logic;
+    signal clk320               : std_logic;
+
+    constant clk40_period       : time := 25 ns;
+    signal clk40_tmp            : std_logic:= '0';
+    signal clk_en               : boolean   := false;
+
+    signal reset                : std_logic := '0';
+    signal reset_done           : std_logic := '0';
+    signal reset_clk40          : std_logic := '0';
+    signal reset_done_clk40     : std_logic := '0';
+
+    signal timeout              : boolean := false;
+
+    type data16barray           is array (0 to GBT_NUM-1) of std_logic_vector(15 downto 0);
+    type data32barray           is array (0 to GBT_NUM-1) of std_logic_vector(31 downto 0);
+    type txrx234b_48ch_type     is array (GBT_NUM-1 downto 0) of std_logic_vector(233 downto 0);
+    type txrx36b_48ch_type      is array (GBT_NUM-1 downto 0) of std_logic_vector(35 downto 0);
+    --lpgbt BE
+    signal alignment_done_f_BE  : std_logic_vector(GBT_NUM-1 downto 0);
+    signal data_rdy_BE          : std_logic_vector(GBT_NUM-1 downto 0);
+    signal RxSlide_BE           : std_logic_vector(GBT_NUM-1 downto 0);
+    signal TX_DATA_BE           : data16barray := (others => ("0000000000000000"));
+    signal uplinkData_i_BE      : txrx234b_48ch_type;
+    signal fec_error_i_BE       : std_logic_vector(GBT_NUM-1 downto 0);
+    signal fec_err_cnt_i_BE     : array_32b(0 to GBT_NUM-1);
+
+    --lpgbt FE
+    signal RxSlide_FE               : std_logic_vector(GBT_NUM-1 downto 0);
+    signal alignment_done_f_FE      : std_logic_vector(GBT_NUM-1 downto 0);
+    signal sta_headerFlag_out_FE    : std_logic_vector(GBT_NUM-1 downto 0);
+    signal TX_DATA_FE               : data32barray := (others => ("00000000000000000000000000000000"));
+    signal downLinkData_i_FE        : txrx36b_48ch_type;
+    signal tx_flag_out_FE           : std_logic_vector(GBT_NUM-1 downto 0);
+
+    --data
+    signal data_to_back_end     : std_logic_vector(223 downto 0);-- := (others => '0');
+    signal data_to_front_end    : std_logic_vector(31 downto 0);
+
+begin
+
+    --clocks
+
+    clk40_tmp       <= not clk40_tmp        after clk40_period/2; --40 MHZ;
+    clk40_in        <= clk40_tmp            when  clk_en else '0';
+
+    clk_25d00 : clk_wiz_40_0
+        port map (
+            clk_in2 => clk40_in,
+            clk_in_sel => '0',
+            clk40 => clk40,
+            clk80 => open,
+            clk160 => clk160,
+            clk320 => clk320,
+            clk240 => clk240,
+            clk100 => open,
+            reset => '0',
+            locked => open,
+            clk_40_in => clk40_in
+        );
+
+    process(clk40)
+    begin
+        if clk40'event and clk40='1' then
+            reset_clk40 <= reset;
+            reset_done_clk40 <= reset_done;
+        end if;
+    end process;
+
+    -- lpgbt FELIX
+    limk_loop_BE : for i in 0 to GBT_NUM-1 generate
+        signal TXCLK40                      : std_logic;
+        signal RX_RESET_rxusrclk            : std_logic;
+        signal TX_RESET_txusrclk            : std_logic;
+        signal downlinkUserData_i           : std_logic_vector(31 downto 0);
+        signal downlinkEcData_i             : std_logic_vector(1 downto 0);
+        signal downlinkIcData_i             : std_logic_vector(1 downto 0);
+        signal uplinkMulticycleDelay        : std_logic_vector(2 downto 0);
+        signal GT_TX_WORD_CLK               : std_logic;
+        signal GT_RX_WORD_CLK               : std_logic;
+        signal GBT_General_ctrl             : std_logic_vector(63 downto 0);
+        signal CTRL_FECMODE                 : std_logic;
+        signal RX_DATA_32b                  : std_logic_vector(31 downto 0);
+        signal uplinkDATA                   : std_logic_vector(223 downto 0);
+        signal uplinkEC                     : std_logic_vector(1 downto 0);
+        signal uplinkIC                     : std_logic_vector(1 downto 0);
+    begin
+        TXCLK40                 <= clk40;
+        downlinkUserData_i      <= data_to_front_end;
+        downlinkIcData_i        <= "10";
+        downlinkEcData_i        <= "11";
+
+        GT_TX_WORD_CLK          <= clk320;
+        GT_RX_WORD_CLK          <= clk320;
+
+        CTRL_FECMODE            <= '0'; --FEC5
+        GBT_General_ctrl        <= (others => '0'); --all 0 is correct
+
+        RX_DATA_32b             <=  TX_DATA_FE(i);--(others => '0');
+
+        TX_RESET_txusrclk       <= reset_clk40;
+        RX_RESET_rxusrclk       <= reset_clk40;
+
+        uplinkMulticycleDelay   <= "011"; --(others => '0');
+
+        lpgbt_BE: entity work.FLX_LpGBT_BE
+            Port map (
+                downlinkUserData_i          => downlinkUserData_i,                  --in
+                downlinkEcData_i            => downlinkEcData_i,                    --in
+                downlinkIcData_i            => downlinkIcData_i,                    --in
+                TXCLK40                     => TXCLK40,                            --in
+                TXCLK320                    => GT_TX_WORD_CLK,                      --in
+                RXCLK320m                   => GT_RX_WORD_CLK,                      --in
+                uplinkSelectFEC_i           => CTRL_FECMODE,                        --in
+                data_rdy                    => data_rdy_BE(i),                      --out
+                Tx_scrambler_bypass         => '0',                                 --in
+                Tx_Interleaver_bypass       => '0',                                 --in
+                Tx_FEC_bypass               => '0',                                 --in
+                TxData_Out                  => TX_DATA_BE(i),                       --out
+                rxdatain                    => RX_DATA_32b,                         --in
+                GBT_TX_RST                  => TX_RESET_txusrclk,                   --in
+                GBT_RX_RST                  => RX_RESET_rxusrclk,                   --in
+                uplinkBypassInterleaver_i   => GBT_General_ctrl(35),                --in
+                uplinkBypassFECEncoder_i    => GBT_General_ctrl(36),                --in
+                uplinkBypassScrambler_i     => GBT_General_ctrl(37),                --in
+                uplinkMulticycleDelay_i     => uplinkMulticycleDelay,               --in
+                sta_headerFecLocked_o       => alignment_done_f_BE(i),              --out
+                ctr_clkSlip_o               => RxSlide_BE(i),                       --out
+                --sta_rxGbRdy_o             => open,                                --out
+                uplinkReady_o               => open, --UplinkRdy(i),                --out
+                uplinkUserData_o            => uplinkData_i_BE(i)(229 downto 0),    --out
+                uplinkEcData_o              => uplinkData_i_BE(i)(231 downto 230),  --out
+                uplinkIcData_o              => uplinkData_i_BE(i)(233 downto 232),  --out
+                fec_error_o                 => fec_error_i_BE(i),                   --out
+                fec_err_cnt_o               => fec_err_cnt_i_BE(i)                  --out
+            );
+        uplinkDATA  <= uplinkData_i_BE(i)(223 downto 0);
+        uplinkEC    <= uplinkData_i_BE(i)(231 downto 230);
+        uplinkIC    <= uplinkData_i_BE(i)(233 downto 232);
+    end generate;
+
+    -- lpgbt FELIG
+    limk_loop_FE : for i in 0 to GBT_NUM-1 generate
+        signal txclk40m             : std_logic;
+        signal rxrecclk40m          : std_logic;
+        signal GT_TX_WORD_CLK       : std_logic;
+        signal GT_RX_WORD_CLK       : std_logic;
+        signal TX_RESET_i           : std_logic;
+        signal RX_DATA_16b          : std_logic_vector(15 downto 0);
+        signal rst_dnlink           : std_logic;
+        signal rxresetdone          : std_logic;
+        signal GBT_General_ctrl     : std_logic_vector(63 downto 0);
+        signal CTRL_FECMODE         : std_logic;
+        signal CTRL_DATARATE        : std_logic;
+        signal FE_UPLINK_USER_DATA  : std_logic_vector(223 downto 0);
+        signal FE_UPLINK_IC_DATA    : std_logic_vector(1 downto 0);
+        signal FE_UPLINK_EC_DATA    : std_logic_vector(1 downto 0);
+        signal downlinkDATA         : std_logic_vector(31 downto 0);
+        signal downlinkEC           : std_logic_vector(1 downto 0);
+        signal downlinkIC           : std_logic_vector(1 downto 0);
+        signal count                : std_logic_vector(2 downto 0) := "000";
+        signal data_en              : std_logic;
+    begin
+
+        txclk40m             <= clk40;
+        rxrecclk40m          <= clk40;
+        GT_TX_WORD_CLK       <= clk320;
+        GT_RX_WORD_CLK       <= clk320;
+        TX_RESET_i           <= reset_clk40;
+        RX_DATA_16b          <= TX_DATA_BE(i);
+        rst_dnlink           <= reset_clk40;
+        rxresetdone          <= reset_done_clk40;
+        GBT_General_ctrl     <= (others => '0'); --all 0 is correct
+        CTRL_FECMODE         <= '0'; --FEC5
+        CTRL_DATARATE        <= '1'; --10.24 Gb/s
+        FE_UPLINK_USER_DATA  <= data_to_back_end;--(others => '0');
+        FE_UPLINK_IC_DATA    <= "01";
+        FE_UPLINK_EC_DATA    <= "10";
+
+        lpgbt_FE: entity work.FLX_LpGBT_FE
+            Port map
+        (
+                clk40_in                        => rxrecclk40m,
+                --TXCLK40                         => txclk40m,--clk40_in,                 --in
+                --RXCLK40                         => rxrecclk40m,                         --in
+                TXCLK320                        => GT_TX_WORD_CLK,                      --in
+                RXCLK320                        => GT_RX_WORD_CLK,                      --in
+                rst_uplink_i                    => TX_RESET_i,                          --in
+                ctr_clkSlip_s                   => RxSlide_FE(i),                       --out
+                aligned                         => alignment_done_f_FE(i),              --out
+                sta_headerFlag_o                => sta_headerFlag_out_FE(i),            --out
+                sta_headerFlag_shift            => open,                                --out
+                clk_dataFlag_rxGb_s_o           => open,                                --out
+                dat_upLinkWord_fromGb_s         => TX_DATA_FE(i),                       --out
+                dat_downLinkWord_fromMgt_s16    => RX_DATA_16b,                         --in
+                rst_dnlink_i                    => rst_dnlink,--RL                      --in
+                sta_mgtRxRdy_s                  => rxresetdone,                         --in
+                downLinkBypassDeinterleaver     => '0',                                 --in
+                downLinkBypassFECDecoder        => '0',                                 --in
+                downLinkBypassDescsrambler      => '0',                                 --in
+                enableFECErrCounter             => '0',                                 --in
+                upLinkScramblerBypass           => GBT_General_ctrl(32),                --in
+                --upLinkFecBypass                 => GBT_General_ctrl(33),                --in
+                upLinkInterleaverBypass         => GBT_General_ctrl(34),                --in
+                fecMode                         => CTRL_FECMODE,                        --in
+                txDataRate                      => CTRL_DATARATE,                       --in
+                phase_sel                       => "100",                               --in
+                upLinkData                      => FE_UPLINK_USER_DATA,                 --in
+                upLinkDataIC                    => FE_UPLINK_IC_DATA,                   --in
+                upLinkDataEC                    => FE_UPLINK_EC_DATA,                   --in
+                upLinkDataREADY                 => data_en,
+                downLinkData                    => downLinkData_i_FE(i)(31 downto 0),   --out
+                downLinkDataIC                  => downLinkData_i_FE(i)(33 downto 32),  --out
+                downLinkDataEC                  => downLinkData_i_FE(i)(35 downto 34),  --out
+                tx_flag_out                     => tx_flag_out_FE(i)                    --out
+            );
+        downlinkDATA    <= downLinkData_i_FE(i)(31 downto 0);
+        downlinkEC      <= downLinkData_i_FE(i)(33 downto 32);
+        downlinkIC      <= downLinkData_i_FE(i)(35 downto 34);
+
+        process(GT_TX_WORD_CLK)
+        begin
+            if GT_TX_WORD_CLK'event and GT_TX_WORD_CLK='1' then
+                count <= count + "001";
+                if count = "111" then
+                    data_en <= '1';
+                else
+                    data_en <= '0';
+                end if;
+            end if;
+        end process;
+
+    end generate;
+
+    --sim process
+    mainproc : process
+    begin
+        assert false
+            report "START SIMULATION"
+            severity NOTE;
+        clk_en  <= true;
+        data_to_back_end    <= (others => '0');
+        data_to_front_end   <= (others => '0');
+        wait for 2 us;
+        reset   <= '1';
+        wait for 2 us;
+        reset   <='0';
+        reset_done  <= '1';
+        wait for 5 us;
+        while true loop
+            if timeout then
+                exit;
+            end if;
+            data_to_back_end    <= data_to_back_end + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
+            data_to_front_end   <= data_to_front_end + "00000000000000000000000000000001";
+            wait for 3 us;
+        end loop;
+        wait for 1000 us;
+    end process;
+
+    timeoutproc : process
+    begin
+        wait for 1000 us;
+        timeout <= true;
+    end process;
+
+
+end Behavioral;
diff --git a/simulation/FELIG/felig_lpgbt_sim.wcfg b/simulation/FELIG/felig_lpgbt_sim.wcfg
new file mode 100644
index 0000000000000000000000000000000000000000..693d91c8c58801bb51520872a247e72fa229d779
--- /dev/null
+++ b/simulation/FELIG/felig_lpgbt_sim.wcfg
@@ -0,0 +1,256 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="felig_lpgbt_sim_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="centralrouter_package" />
+            <top_module name="felig_lpgbt_sim" />
+            <top_module name="felix_package" />
+            <top_module name="glbl" />
+            <top_module name="lpgbtfpga_package" />
+            <top_module name="pcie_package" />
+            <top_module name="vcomponents" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="977.931 ns"></ZoomStartTime>
+      <ZoomEndTime time="1,004.414 ns"></ZoomEndTime>
+      <Cursor1Time time="1,000.000 ns"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="203"></NameColumnWidth>
+      <ValueColumnWidth column_width="160"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="56" />
+   <wvobject fp_name="divider1259" type="divider">
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/dat_downLinkWord_fromMgt_s64">
+      <obj_property name="ElementShortName">dat_downLinkWord_fromMgt_s64[63:0]</obj_property>
+      <obj_property name="ObjectShortName">dat_downLinkWord_fromMgt_s64[63:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/dat_downLinkWord_fromGb_s">
+      <obj_property name="ElementShortName">dat_downLinkWord_fromGb_s[63:0]</obj_property>
+      <obj_property name="ObjectShortName">dat_downLinkWord_fromGb_s[63:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/dat_downLinkWord_fromGb_en">
+      <obj_property name="ElementShortName">dat_downLinkWord_fromGb_en</obj_property>
+      <obj_property name="ObjectShortName">dat_downLinkWord_fromGb_en</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/dat_downLinkWord_fromGb_s_buf">
+      <obj_property name="ElementShortName">dat_downLinkWord_fromGb_s_buf[63:0]</obj_property>
+      <obj_property name="ObjectShortName">dat_downLinkWord_fromGb_s_buf[63:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider31" type="divider">
+      <obj_property name="label">clocks and resets</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/clk40">
+      <obj_property name="ElementShortName">clk40</obj_property>
+      <obj_property name="ObjectShortName">clk40</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/clk40_in">
+      <obj_property name="ElementShortName">clk40_in</obj_property>
+      <obj_property name="ObjectShortName">clk40_in</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/clk320">
+      <obj_property name="ElementShortName">clk320</obj_property>
+      <obj_property name="ObjectShortName">clk320</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/reset">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/reset_done">
+      <obj_property name="ElementShortName">reset_done</obj_property>
+      <obj_property name="ObjectShortName">reset_done</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/reset_clk40">
+      <obj_property name="ElementShortName">reset_clk40</obj_property>
+      <obj_property name="ObjectShortName">reset_clk40</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/reset_done_clk40">
+      <obj_property name="ElementShortName">reset_done_clk40</obj_property>
+      <obj_property name="ObjectShortName">reset_done_clk40</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider305" type="divider">
+      <obj_property name="label">to back end</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="BkColor">#FF0000</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_BE(0)\/RX_DATA_32b">
+      <obj_property name="ElementShortName">RX_DATA_32b[31:0]</obj_property>
+      <obj_property name="ObjectShortName">RX_DATA_32b[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/alignment_done_f_BE">
+      <obj_property name="ElementShortName">alignment_done_f_BE[3:0]</obj_property>
+      <obj_property name="ObjectShortName">alignment_done_f_BE[3:0]</obj_property>
+      <obj_property name="CustomSignalColor">#00FFFF</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/FE_UPLINK_USER_DATA">
+      <obj_property name="ElementShortName">FE_UPLINK_USER_DATA[223:0]</obj_property>
+      <obj_property name="ObjectShortName">FE_UPLINK_USER_DATA[223:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/FE_UPLINK_IC_DATA">
+      <obj_property name="ElementShortName">FE_UPLINK_IC_DATA[1:0]</obj_property>
+      <obj_property name="ObjectShortName">FE_UPLINK_IC_DATA[1:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/FE_UPLINK_EC_DATA">
+      <obj_property name="ElementShortName">FE_UPLINK_EC_DATA[1:0]</obj_property>
+      <obj_property name="ObjectShortName">FE_UPLINK_EC_DATA[1:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_BE(0)\/uplinkDATA">
+      <obj_property name="ElementShortName">uplinkDATA[223:0]</obj_property>
+      <obj_property name="ObjectShortName">uplinkDATA[223:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_BE(0)\/uplinkIC">
+      <obj_property name="ElementShortName">uplinkIC[1:0]</obj_property>
+      <obj_property name="ObjectShortName">uplinkIC[1:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_BE(0)\/uplinkEC">
+      <obj_property name="ElementShortName">uplinkEC[1:0]</obj_property>
+      <obj_property name="ObjectShortName">uplinkEC[1:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/uplinkData_i_BE">
+      <obj_property name="ElementShortName">uplinkData_i_BE[3:0][233:0]</obj_property>
+      <obj_property name="ObjectShortName">uplinkData_i_BE[3:0][233:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/\limk_loop_BE(3)\/lpgbt_BE/lpgbtfpga_uplink_fec5_inst/rst_pattsearch_s">
+      <obj_property name="ElementShortName">rst_pattsearch_s</obj_property>
+      <obj_property name="ObjectShortName">rst_pattsearch_s</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider302" type="divider">
+      <obj_property name="label">to front end</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="BkColor">#FF0000</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/rst_pattsearch_s">
+      <obj_property name="ElementShortName">rst_pattsearch_s</obj_property>
+      <obj_property name="ObjectShortName">rst_pattsearch_s</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/RX_DATA_16b">
+      <obj_property name="ElementShortName">RX_DATA_16b[15:0]</obj_property>
+      <obj_property name="ObjectShortName">RX_DATA_16b[15:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_BE(0)\/downlinkUserData_i">
+      <obj_property name="ElementShortName">downlinkUserData_i[31:0]</obj_property>
+      <obj_property name="ObjectShortName">downlinkUserData_i[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_BE(0)\/downlinkEcData_i">
+      <obj_property name="ElementShortName">downlinkEcData_i[1:0]</obj_property>
+      <obj_property name="ObjectShortName">downlinkEcData_i[1:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_BE(0)\/downlinkIcData_i">
+      <obj_property name="ElementShortName">downlinkIcData_i[1:0]</obj_property>
+      <obj_property name="ObjectShortName">downlinkIcData_i[1:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/alignment_done_f_FE">
+      <obj_property name="ElementShortName">alignment_done_f_FE[3:0]</obj_property>
+      <obj_property name="ObjectShortName">alignment_done_f_FE[3:0]</obj_property>
+      <obj_property name="CustomSignalColor">#00FFFF</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/downlinkDATA">
+      <obj_property name="ElementShortName">downlinkDATA[31:0]</obj_property>
+      <obj_property name="ObjectShortName">downlinkDATA[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/downlinkEC">
+      <obj_property name="ElementShortName">downlinkEC[1:0]</obj_property>
+      <obj_property name="ObjectShortName">downlinkEC[1:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/downlinkIC">
+      <obj_property name="ElementShortName">downlinkIC[1:0]</obj_property>
+      <obj_property name="ObjectShortName">downlinkIC[1:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/downLinkData_i_FE">
+      <obj_property name="ElementShortName">downLinkData_i_FE[3:0][35:0]</obj_property>
+      <obj_property name="ObjectShortName">downLinkData_i_FE[3:0][35:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider854" type="divider">
+      <obj_property name="label">FLX_LpGBT_FE</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="BkColor">#FFD700</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/dat_downLinkWord_fromMgt_s16">
+      <obj_property name="ElementShortName">dat_downLinkWord_fromMgt_s16[15:0]</obj_property>
+      <obj_property name="ObjectShortName">dat_downLinkWord_fromMgt_s16[15:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/dat_downLinkWord_fromMgt_s">
+      <obj_property name="ElementShortName">dat_downLinkWord_fromMgt_s[31:0]</obj_property>
+      <obj_property name="ObjectShortName">dat_downLinkWord_fromMgt_s[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/dat_downLinkWord_fromMgt_s64">
+      <obj_property name="ElementShortName">dat_downLinkWord_fromMgt_s64[63:0]</obj_property>
+      <obj_property name="ObjectShortName">dat_downLinkWord_fromMgt_s64[63:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/dat_downLinkWord_fromMgt_s8">
+      <obj_property name="ElementShortName">dat_downLinkWord_fromMgt_s8[7:0]</obj_property>
+      <obj_property name="ObjectShortName">dat_downLinkWord_fromMgt_s8[7:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider859" type="divider">
+      <obj_property name="label">mgt_framealigner_inst</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="BkColor">#FAAFBE</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/mgt_framealigner_inst/clk_pcsRx_i">
+      <obj_property name="ElementShortName">clk_pcsRx_i</obj_property>
+      <obj_property name="ObjectShortName">clk_pcsRx_i</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/mgt_framealigner_inst/rst_pattsearch_i">
+      <obj_property name="ElementShortName">rst_pattsearch_i</obj_property>
+      <obj_property name="ObjectShortName">rst_pattsearch_i</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/mgt_framealigner_inst/dat_word_i">
+      <obj_property name="ElementShortName">dat_word_i[15:0]</obj_property>
+      <obj_property name="ObjectShortName">dat_word_i[15:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/mgt_framealigner_inst/cmd_bitslipCtrl_o">
+      <obj_property name="ElementShortName">cmd_bitslipCtrl_o</obj_property>
+      <obj_property name="ObjectShortName">cmd_bitslipCtrl_o</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/mgt_framealigner_inst/sta_headerLocked_o">
+      <obj_property name="ElementShortName">sta_headerLocked_o</obj_property>
+      <obj_property name="ObjectShortName">sta_headerLocked_o</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/mgt_framealigner_inst/sta_headerFlag_o">
+      <obj_property name="ElementShortName">sta_headerFlag_o</obj_property>
+      <obj_property name="ObjectShortName">sta_headerFlag_o</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/mgt_framealigner_inst/sta_bitSlipEven_o">
+      <obj_property name="ElementShortName">sta_bitSlipEven_o</obj_property>
+      <obj_property name="ObjectShortName">sta_bitSlipEven_o</obj_property>
+   </wvobject>
+   <wvobject type="other" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/mgt_framealigner_inst/state">
+      <obj_property name="ElementShortName">state</obj_property>
+      <obj_property name="ObjectShortName">state</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/mgt_framealigner_inst/rst_pattsearch_i">
+      <obj_property name="ElementShortName">rst_pattsearch_i</obj_property>
+      <obj_property name="ObjectShortName">rst_pattsearch_i</obj_property>
+   </wvobject>
+   <wvobject type="other" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/mgt_framealigner_inst/psAddress">
+      <obj_property name="ElementShortName">psAddress</obj_property>
+      <obj_property name="ObjectShortName">psAddress</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/mgt_framealigner_inst/cmd_bitslipDone_s">
+      <obj_property name="ElementShortName">cmd_bitslipDone_s</obj_property>
+      <obj_property name="ObjectShortName">cmd_bitslipDone_s</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/mgt_framealigner_inst/cmd_bitslipDone_s">
+      <obj_property name="ElementShortName">cmd_bitslipDone_s</obj_property>
+      <obj_property name="ObjectShortName">cmd_bitslipDone_s</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/mgt_framealigner_inst/bitSlipCmd_s">
+      <obj_property name="ElementShortName">bitSlipCmd_s</obj_property>
+      <obj_property name="ObjectShortName">bitSlipCmd_s</obj_property>
+   </wvobject>
+   <wvobject type="other" fp_name="/felig_lpgbt_sim/\limk_loop_FE(0)\/lpgbt_FE/mgt_framealigner_inst/stateBitSlip">
+      <obj_property name="ElementShortName">stateBitSlip</obj_property>
+      <obj_property name="ObjectShortName">stateBitSlip</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider1099" type="divider">
+   </wvobject>
+</wave_config>
diff --git a/simulation/FELIG/felig_sim_top_bnl712.vhd b/simulation/FELIG/felig_sim_top_bnl712.vhd
index 057f2dead7b9e0c3cd613e6c4665f2171b8f1ac9..f5100041e0f2a594037979d395666b5101cc5e0d 100644
--- a/simulation/FELIG/felig_sim_top_bnl712.vhd
+++ b/simulation/FELIG/felig_sim_top_bnl712.vhd
@@ -119,6 +119,8 @@ architecture Behavioral of felig_sim_top_bnl712 is
     signal lpgbt_downlink0: std_logic_vector(223 downto 0);
     signal aclk_tmp       : std_logic:= '0';
     signal clk40_in_b     : std_logic:= '0';
+    signal data_ready_tx_to_link_wrapper : std_logic_vector(0 to GBT_NUM-1);
+
 begin
 
     ---------------------------------------------------------------------------------------------------------------
@@ -132,7 +134,7 @@ begin
     LINKSconfig       <= '0' & DATARATE & FECMODE when FIRMWARE_MODE = 6 else
                          '1' & DATARATE & FECMODE when FIRMWARE_MODE = 11;
 
-    MSB               <= '0'; --0 for LSB first, 1 for MSB first
+    MSB               <= '1'; --0 for LSB first, 1 for MSB first
     data_format       <= "01"; --00 for direct, 01 for 8b10b, 10 for AURORA
     input_width       <= '0' when data_format = "00" else '1';--0 for 8b, 1 for 10b
 
@@ -244,25 +246,34 @@ begin
         lane_control(i).global.a_ch_bit_sel    <= "0000001";
         lane_control(i).global.b_ch_bit_sel    <= "0000010";
         lane_control(i).global.MSB                <= MSB;
-        lane_control(i).clock.gth_tx_pi_hold    <= '0';
-        lane_control(i).clock.picxo_offset_en    <= '0';
-        lane_control(i).clock.picxo_offset_ppm    <= (others => '0');
-        lane_control(i).gbt.rxslide_select    <= '0';
-        lane_control(i).gbt.rx_reset      <= gbt_rx_reset;
-        lane_control(i).gbt.tc_edge      <= '0';
-        lane_control(i).gbt.tx_reset      <= gbt_tx_reset;
-        lane_control(i).gbt.tx_tc_method      <= '0';
-        lane_control(i).gbt.rx_data_format    <= "00";
-        lane_control(i).gbt.tx_data_format    <= "00";
-        lane_control(i).gbt.tx_tc_dly_value    <= X"0";
-        lane_control(i).gbt.loopback_enable    <= '0';
-        lane_control(i).gbt.rxslide_count_reset    <= '0';
-        lane_control(i).gth.manual_gth_rxreset    <= '0';
-        lane_control(i).gth.txpolarity      <= '0';
-        lane_control(i).gth.rxpolarity      <= '0';
-        lane_control(i).gth.loopback_enable    <= '0';
+        --        lane_control(i).clock.gth_tx_pi_hold    <= '0';
+        --        lane_control(i).clock.picxo_offset_en    <= '0';
+        --        lane_control(i).clock.picxo_offset_ppm    <= (others => '0');
+        --        lane_control(i).gbt.rxslide_select    <= '0';
+        --        lane_control(i).gbt.rx_reset      <= gbt_rx_reset;
+        --        lane_control(i).gbt.tc_edge      <= '0';
+        --        lane_control(i).gbt.tx_reset      <= gbt_tx_reset;
+        --        lane_control(i).gbt.tx_tc_method      <= '0';
+        --        lane_control(i).gbt.rx_data_format    <= "00";
+        --        lane_control(i).gbt.tx_data_format    <= "00";
+        --        lane_control(i).gbt.tx_tc_dly_value    <= X"0";
+        --        lane_control(i).gbt.loopback_enable    <= '0';
+        --        lane_control(i).gbt.rxslide_count_reset    <= '0';
+        --        lane_control(i).gth.manual_gth_rxreset    <= '0';
+        --        lane_control(i).gth.txpolarity      <= '0';
+        --        lane_control(i).gth.rxpolarity      <= '0';
+        --        lane_control(i).gth.loopback_enable    <= '0';
         lane_control(i).emulator          <= emu_control;
         lane_control(i).elink              <= elink_control;
+        --lane_control(i).global.PROTOCOL <= '0' when FIRMWARE_MODE = FIRMWARE_MODE_FELIG_GBT else '1';
+        lane_control(i).global.FEC      <= '0';--register_map_control.LPGBT_FEC(0)
+        lane_control(i).global.DATARATE <= '1';-- not register_map_control.LPGBT_DATARATE(0)
+        lane_control(i).global.aligned <= linkValid_array(i);
+        lane_control(i).fmemu_random.SELECT_RANDOM           <= pcie0_register_map_40_control.FMEMU_RANDOM_CONTROL.SELECT_RANDOM;
+        lane_control(i).fmemu_random.FMEMU_RANDOM_RAM_ADDR   <= pcie0_register_map_40_control.FMEMU_RANDOM_RAM_ADDR;
+        lane_control(i).fmemu_random.FMEMU_RANDOM_RAM        <= pcie0_register_map_40_control.FMEMU_RANDOM_RAM;
+        lane_control(i).fmemu_random.FMEMU_RANDOM_CONTROL    <= pcie0_register_map_40_control.FMEMU_RANDOM_CONTROL;
+        lane_control(i).global.l1a_max_count                  <= pcie0_register_map_40_control.FELIG_GLOBAL_CONTROL.FAKE_L1A_RATE;
     end generate gen_lane_control;
 
     gen_emu_control : for i in emu_control'range generate
@@ -288,12 +299,12 @@ begin
     --emu_control(3).output_width  <= "001";--4-bit
     --emu_control(4).output_width  <= "010";--8-bit
 
-    emu_control(0).output_width  <= "000";-- 2b--"000";--2-bit
-    emu_control(1).output_width  <= "001";-- 4b--"000";--2-bit
-    emu_control(2).output_width  <= "010";-- 8b--"001";--4-bit
-    emu_control(3).output_width  <= "010";-- 8b--"001";--4-bit
-    emu_control(4).output_width  <= "011";--16b--"010";--8-bit
-    emu_control(5).output_width  <= "011";--16b--"010";--8-bit
+    emu_control(0).output_width  <= "010";-- 2b--"000";--2-bit
+    emu_control(1).output_width  <= "010";-- 4b--"000";--2-bit
+    emu_control(2).output_width  <= "011";-- 8b--"001";--4-bit
+    emu_control(3).output_width  <= "011";-- 8b--"001";--4-bit
+    emu_control(4).output_width  <= "100";--16b--"010";--8-bit
+    emu_control(5).output_width  <= "100";--16b--"010";--8-bit
     emu_control(6).output_width  <= "100";--32b--"011";--16-bit
     --  emu_control(0).output_width  <= "100";--32b
     --  emu_control(1).output_width  <= "100";--32b
@@ -448,14 +459,64 @@ begin
     gbt_downlink0 <= GBT_DOWNLINK_USER_DATA(0);
     lpgbt_downlink0 <= lpGBT_DOWNLINK_USER_DATA(0);
 
+    --    linkwrapper0: entity work.link_wrapper_FELIG
+    --        generic map(
+    --            GBT_NUM => GBT_NUM,
+    --            FIRMWARE_MODE => FIRMWARE_MODE,
+    --            sim_emulator => true)
+    --        port map(
+    --            register_map_control => pcie0_register_map_40_control,
+    --            register_map_link_monitor => open,
+    --            clk40 => clk40_in,
+    --            clk240 => clk240_in,
+    --            clk320 => clk320,
+    --            clk40_xtal => clk_xtal_40,
+    --            GTREFCLK_N_in => (others=>'0'),
+    --            GTREFCLK_P_in => (others=>'0'),
+    --            rst_hw => rst_hw,
+    --            OPTO_LOS => (others=>'0'),
+    --            RXUSRCLK_OUT => gt_rxusrclk_i,
+    --            GBT_DOWNLINK_USER_DATA => GBT_DOWNLINK_USER_DATA,
+    --            GBT_UPLINK_USER_DATA => GBT_UPLINK_USER_DATA,
+    --            lpGBT_DOWNLINK_USER_DATA => lpGBT_DOWNLINK_USER_DATA,
+    --            lpGBT_DOWNLINK_IC_DATA => lpGBT_DOWNLINK_IC_DATA,
+    --            lpGBT_DOWNLINK_EC_DATA => lpGBT_DOWNLINK_EC_DATA,
+    --            lpGBT_UPLINK_USER_DATA => lpGBT_UPLINK_USER_DATA,
+    --            lpGBT_UPLINK_EC_DATA => lpGBT_UPLINK_EC_DATA,
+    --            lpGBT_UPLINK_IC_DATA => lpGBT_UPLINK_IC_DATA,
+    --            LinkAligned => linkValid_array,
+    --            TX_P => open,
+    --            TX_N => open,
+    --            RX_P => (others=>'0'),
+    --            RX_N => (others=>'0'),
+    --            GTH_FM_RX_33b_out => GTH_FM_RX_33b_out,
+    --            LMK_P => (others=>'0'),
+    --            LMK_N => (others=>'0'),
+    --            link_rx_flag_i=>link_rx_flag_i,
+    --            link_tx_flag_i=>link_tx_flag_i,
+    --            TXUSRCLK_OUT => gt_txusrclk_i,
+    --            appreg_clk => '0',
+    --            CLK40_FPGA2LMK_N => open,
+    --            CLK40_FPGA2LMK_P => open,
+    --            LMK_LD => '0',
+    --            --RESET_TO_LMK => open,
+    --            clk40_rxusrclk => open,
+    --            clk320_in => clk320_in,
+    --            LINKSconfig => LINKSconfig);
+
     linkwrapper0: entity work.link_wrapper_FELIG
         generic map(
             GBT_NUM => GBT_NUM,
+            --CARD_TYPE => CARD_TYPE,
+            --GTHREFCLK_SEL => GTHREFCLK_SEL,
             FIRMWARE_MODE => FIRMWARE_MODE,
+            --PLL_SEL => PLL_SEL,
+            --GTREFCLKS => GTREFCLKS,
+            --OPTO_TRX => NUM_OPTO_LOS(CARD_TYPE),
             sim_emulator => true)
         port map(
-            register_map_control => pcie0_register_map_40_control,
-            register_map_link_monitor => open,
+            register_map_control => pcie0_register_map_40_control, --its cool
+            register_map_link_monitor => open, -- needs confirnation
             clk40 => clk40_in,
             clk240 => clk240_in,
             clk40_xtal => clk_xtal_40,
@@ -469,6 +530,7 @@ begin
             lpGBT_DOWNLINK_USER_DATA => lpGBT_DOWNLINK_USER_DATA,
             lpGBT_DOWNLINK_IC_DATA => lpGBT_DOWNLINK_IC_DATA,
             lpGBT_DOWNLINK_EC_DATA => lpGBT_DOWNLINK_EC_DATA,
+            data_ready_DOWNLINK => data_ready_tx_to_link_wrapper,
             lpGBT_UPLINK_USER_DATA => lpGBT_UPLINK_USER_DATA,
             lpGBT_UPLINK_EC_DATA => lpGBT_UPLINK_EC_DATA,
             lpGBT_UPLINK_IC_DATA => lpGBT_UPLINK_IC_DATA,
@@ -477,20 +539,27 @@ begin
             TX_N => open,
             RX_P => (others=>'0'),
             RX_N => (others=>'0'),
-            GTH_FM_RX_33b_out => GTH_FM_RX_33b_out,
+            --GTH_FM_RX_33b_out => GTH_FM_RX_33b_out,
             LMK_P => (others=>'0'),
             LMK_N => (others=>'0'),
+            --GBT FELIG specific
             link_rx_flag_i=>link_rx_flag_i,
             link_tx_flag_i=>link_tx_flag_i,
             TXUSRCLK_OUT => gt_txusrclk_i,
-            appreg_clk => '0',
             CLK40_FPGA2LMK_N => open,
             CLK40_FPGA2LMK_P => open,
+            --LMK_LD => LMK_LD(0),
+            --RESET_TO_LMK => RESET_TO_LMK_i,
+            --clk40_rxusrclk => clk40_rxusrclk,
+            clk320_in => clk320_in, --simulation only
+            clk10_xtal => '0',
+            LMK_DATA => open,
+            LMK_CLK => open,
+            LMK_LE => open,
+            LMK_GOE => open,
             LMK_LD => '0',
-            RESET_TO_LMK => open,
-            clk40_rxusrclk => open,
-            clk320_in => clk320_in,
-            LINKSconfig => LINKSconfig);
+            LMK_SYNCn => open,
+            LMK_LOCKED => open);
 
     ---------------------------------------------------------------------------------------------------------------
     ---------------------------------------------------------------------------------------------------------------
@@ -503,25 +572,24 @@ begin
         generic map(
             GBT_NUM                     => GBT_NUM,
             NUMELINKmax                 => NUMELINKmax,
-            NUMEGROUPmax                => NUMEGROUPmax
+            NUMEGROUPmax                => NUMEGROUPmax,
+            FIRMWARE_MODE               => FIRMWARE_MODE
         )
         port map (
-            clk_xtal_40                => clk_xtal_40      ,
+            clk40                => clk40_in,
             gt_txusrclk_in              => gt_txusrclk_i,
             gt_rxusrclk_in              => gt_rxusrclk_i,
-            gt_rx_clk_div_2_mon         => open,
-            gt_tx_clk_div_2_mon         => open,
-            l1a_trigger_out            => open,
             link_tx_data_228b_array_out  => link_tx_data_228b_array_tmp,
+            data_ready_tx_out            => data_ready_tx_to_link_wrapper,
             link_rx_data_120b_array_in   => link_rx_data_120b_array_tmp,
 
             link_tx_flag_in              => link_tx_flag_i, --gbt_tx_flag_i,
             link_rx_flag_in              => link_rx_flag_i, -- gbt_rx_flag_i,
             lane_control      => lane_control,
-            lane_monitor      => open, --lane_monitor,
-            register_map_control_40xtal => pcie0_register_map_40_control,
-            link_frame_locked_array_in   => linkValid_array,
-            LINKSconfig       => LINKSconfig
+            lane_monitor      => open --lane_monitor,
+        --            register_map_control_40xtal => pcie0_register_map_40_control,
+        --            link_frame_locked_array_in   => linkValid_array,
+        --            LINKSconfig       => LINKSconfig
         );
 
 ---------------------------------------------------------------------------------------------------------------
diff --git a/simulation/FELIG/waveforms/FELIG_phase2_behav.wcfg b/simulation/FELIG/waveforms/FELIG_phase2_behav.wcfg
index fcc6ceb6a9e35c2304f8bebf437f1773bba92c66..89b4285e65068329908b7c8e9269279991625146 100644
--- a/simulation/FELIG/waveforms/FELIG_phase2_behav.wcfg
+++ b/simulation/FELIG/waveforms/FELIG_phase2_behav.wcfg
@@ -7,7 +7,6 @@
          <top_modules>
             <top_module name="axi_stream_package" />
             <top_module name="centralrouter_package" />
-            <top_module name="data_width_package" />
             <top_module name="felig_sim_top_bnl712" />
             <top_module name="felix_gbt_package" />
             <top_module name="felix_package" />
@@ -23,19 +22,175 @@
       </db_ref>
    </db_ref_list>
    <zoom_setting>
-      <ZoomStartTime time="704496fs"></ZoomStartTime>
-      <ZoomEndTime time="1247371fs"></ZoomEndTime>
-      <Cursor1Time time="637662fs"></Cursor1Time>
+      <ZoomStartTime time="19,924.467 ns"></ZoomStartTime>
+      <ZoomEndTime time="20,015.107 ns"></ZoomEndTime>
+      <Cursor1Time time="20,000.000 ns"></Cursor1Time>
    </zoom_setting>
    <column_width_setting>
-      <NameColumnWidth column_width="173"></NameColumnWidth>
+      <NameColumnWidth column_width="194"></NameColumnWidth>
       <ValueColumnWidth column_width="66"></ValueColumnWidth>
    </column_width_setting>
-   <WVObjectSize size="265" />
+   <WVObjectSize size="291" />
    <wave_markers>
       <marker label="" time="43811000" />
       <marker label="" time="43811000" />
    </wave_markers>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(3)\/gbt/elink_muxer_v2/PROTOCOL">
+      <obj_property name="ElementShortName">PROTOCOL</obj_property>
+      <obj_property name="ObjectShortName">PROTOCOL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(3)\/gbt/elink_muxer_v2/\gen_elink_printers(1)\/elink_bit_feeder/PROTOCOL">
+      <obj_property name="ElementShortName">PROTOCOL</obj_property>
+      <obj_property name="ObjectShortName">PROTOCOL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/lpGBT_DOWNLINK_USER_DATA">
+      <obj_property name="ElementShortName">lpGBT_DOWNLINK_USER_DATA[0:3][223:0]</obj_property>
+      <obj_property name="ObjectShortName">lpGBT_DOWNLINK_USER_DATA[0:3][223:0]</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/data_ready_tx_to_link_wrapper">
+      <obj_property name="ElementShortName">data_ready_tx_to_link_wrapper[0:3]</obj_property>
+      <obj_property name="ObjectShortName">data_ready_tx_to_link_wrapper[0:3]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/lpGBT_DOWNLINK_IC_DATA">
+      <obj_property name="ElementShortName">lpGBT_DOWNLINK_IC_DATA[0:3][1:0]</obj_property>
+      <obj_property name="ObjectShortName">lpGBT_DOWNLINK_IC_DATA[0:3][1:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/lpGBT_DOWNLINK_EC_DATA">
+      <obj_property name="ElementShortName">lpGBT_DOWNLINK_EC_DATA[0:3][1:0]</obj_property>
+      <obj_property name="ObjectShortName">lpGBT_DOWNLINK_EC_DATA[0:3][1:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/clk40_in">
+      <obj_property name="ElementShortName">clk40_in</obj_property>
+      <obj_property name="ObjectShortName">clk40_in</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/clk240_in">
+      <obj_property name="ElementShortName">clk240_in</obj_property>
+      <obj_property name="ObjectShortName">clk240_in</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/clk320_in">
+      <obj_property name="ElementShortName">clk320_in</obj_property>
+      <obj_property name="ObjectShortName">clk320_in</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/clk_xtal_40">
+      <obj_property name="ElementShortName">clk_xtal_40</obj_property>
+      <obj_property name="ObjectShortName">clk_xtal_40</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/link_tx_data_228b_array_out">
+      <obj_property name="ElementShortName">link_tx_data_228b_array_out[0:3][227:0]</obj_property>
+      <obj_property name="ObjectShortName">link_tx_data_228b_array_out[0:3][227:0]</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/lane_control">
+      <obj_property name="ElementShortName">lane_control</obj_property>
+      <obj_property name="ObjectShortName">lane_control</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/linkValid_array">
+      <obj_property name="ElementShortName">linkValid_array[3:0]</obj_property>
+      <obj_property name="ObjectShortName">linkValid_array[3:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/l1a_int_trigger">
+      <obj_property name="ElementShortName">l1a_int_trigger</obj_property>
+      <obj_property name="ObjectShortName">l1a_int_trigger</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/l1a_int_max_count">
+      <obj_property name="ElementShortName">l1a_int_max_count[31:0]</obj_property>
+      <obj_property name="ObjectShortName">l1a_int_max_count[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/elink_data">
+      <obj_property name="ElementShortName">elink_data[0:111][9:0]</obj_property>
+      <obj_property name="ObjectShortName">elink_data[0:111][9:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/clk40">
+      <obj_property name="ElementShortName">clk40</obj_property>
+      <obj_property name="ObjectShortName">clk40</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/lane_rxclk">
+      <obj_property name="ElementShortName">lane_rxclk</obj_property>
+      <obj_property name="ObjectShortName">lane_rxclk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/lane_txclk">
+      <obj_property name="ElementShortName">lane_txclk</obj_property>
+      <obj_property name="ObjectShortName">lane_txclk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/l1a_int_trigger">
+      <obj_property name="ElementShortName">l1a_int_trigger</obj_property>
+      <obj_property name="ObjectShortName">l1a_int_trigger</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/l1a_int_int_id">
+      <obj_property name="ElementShortName">l1a_int_int_id[15:0]</obj_property>
+      <obj_property name="ObjectShortName">l1a_int_int_id[15:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/gt_txusrclk_in">
+      <obj_property name="ElementShortName">gt_txusrclk_in[3:0]</obj_property>
+      <obj_property name="ObjectShortName">gt_txusrclk_in[3:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/gt_rxusrclk_in">
+      <obj_property name="ElementShortName">gt_rxusrclk_in[3:0]</obj_property>
+      <obj_property name="ObjectShortName">gt_rxusrclk_in[3:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider642" type="divider">
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/clk">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/elink_control">
+      <obj_property name="ElementShortName">elink_control[0:111]</obj_property>
+      <obj_property name="ObjectShortName">elink_control[0:111]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/elink_sync">
+      <obj_property name="ElementShortName">elink_sync</obj_property>
+      <obj_property name="ObjectShortName">elink_sync</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/elink_data">
+      <obj_property name="ElementShortName">elink_data[0:111][9:0]</obj_property>
+      <obj_property name="ObjectShortName">elink_data[0:111][9:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/tx_flag">
+      <obj_property name="ElementShortName">tx_flag</obj_property>
+      <obj_property name="ObjectShortName">tx_flag</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/PROTOCOL">
+      <obj_property name="ElementShortName">PROTOCOL</obj_property>
+      <obj_property name="ObjectShortName">PROTOCOL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/MSBfirst">
+      <obj_property name="ElementShortName">MSBfirst</obj_property>
+      <obj_property name="ObjectShortName">MSBfirst</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/elink_read_enable">
+      <obj_property name="ElementShortName">elink_read_enable[0:111]</obj_property>
+      <obj_property name="ObjectShortName">elink_read_enable[0:111]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/gbt_payload">
+      <obj_property name="ElementShortName">gbt_payload[223:0]</obj_property>
+      <obj_property name="ObjectShortName">gbt_payload[223:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/aurora_en">
+      <obj_property name="ElementShortName">aurora_en[0:111]</obj_property>
+      <obj_property name="ObjectShortName">aurora_en[0:111]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/bit_stream">
+      <obj_property name="ElementShortName">bit_stream[0:111][31:0]</obj_property>
+      <obj_property name="ObjectShortName">bit_stream[0:111][31:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(0)\/elink_bit_feeder/enable">
+      <obj_property name="ElementShortName">enable</obj_property>
+      <obj_property name="ObjectShortName">enable</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(0)\/elink_bit_feeder/elink_endian_mode">
+      <obj_property name="ElementShortName">elink_endian_mode</obj_property>
+      <obj_property name="ObjectShortName">elink_endian_mode</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(0)\/elink_bit_feeder/elink_output_width">
+      <obj_property name="ElementShortName">elink_output_width[2:0]</obj_property>
+      <obj_property name="ObjectShortName">elink_output_width[2:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(0)\/elink_bit_feeder/elink_input_width">
+      <obj_property name="ElementShortName">elink_input_width</obj_property>
+      <obj_property name="ObjectShortName">elink_input_width</obj_property>
+   </wvobject>
    <wvobject fp_name="divider2497" type="divider">
       <obj_property name="label">New printer</obj_property>
       <obj_property name="DisplayName">label</obj_property>
@@ -123,10 +278,6 @@
       <obj_property name="ElementShortName">payload_egroup6_ph2[31:0]</obj_property>
       <obj_property name="ObjectShortName">payload_egroup6_ph2[31:0]</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/payload_224b_ph2">
-      <obj_property name="ElementShortName">payload_224b_ph2[223:0]</obj_property>
-      <obj_property name="ObjectShortName">payload_224b_ph2[223:0]</obj_property>
-   </wvobject>
    <wvobject fp_name="divider349" type="divider">
       <obj_property name="label">AURORA</obj_property>
       <obj_property name="DisplayName">label</obj_property>
@@ -545,10 +696,6 @@
       <obj_property name="ElementShortName">count</obj_property>
       <obj_property name="ObjectShortName">count</obj_property>
    </wvobject>
-   <wvobject type="other" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(0)\/elink_bit_feeder/count_n">
-      <obj_property name="ElementShortName">count_n</obj_property>
-      <obj_property name="ObjectShortName">count_n</obj_property>
-   </wvobject>
    <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(0)\/elink_bit_feeder/count_to_five">
       <obj_property name="ElementShortName">count_to_five[2:0]</obj_property>
       <obj_property name="ObjectShortName">count_to_five[2:0]</obj_property>
@@ -1250,20 +1397,6 @@
       <obj_property name="ElementShortName">cycle_count_q[2:0]</obj_property>
       <obj_property name="ObjectShortName">cycle_count_q[2:0]</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(64)\/elink_bit_feeder/counter">
-      <obj_property name="ElementShortName">counter[7:0]</obj_property>
-      <obj_property name="ObjectShortName">counter[7:0]</obj_property>
-      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(64)\/elink_bit_feeder/counter_sta">
-      <obj_property name="ElementShortName">counter_sta[7:0]</obj_property>
-      <obj_property name="ObjectShortName">counter_sta[7:0]</obj_property>
-      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(64)\/elink_bit_feeder/flag_cc">
-      <obj_property name="ElementShortName">flag_cc</obj_property>
-      <obj_property name="ObjectShortName">flag_cc</obj_property>
-   </wvobject>
    <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(64)\/elink_bit_feeder/shift_op">
       <obj_property name="ElementShortName">shift_op[2:0]</obj_property>
       <obj_property name="ObjectShortName">shift_op[2:0]</obj_property>
@@ -1304,10 +1437,6 @@
       <obj_property name="ElementShortName">count</obj_property>
       <obj_property name="ObjectShortName">count</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(64)\/elink_bit_feeder/counter">
-      <obj_property name="ElementShortName">counter[7:0]</obj_property>
-      <obj_property name="ObjectShortName">counter[7:0]</obj_property>
-   </wvobject>
    <wvobject type="vbus" fp_name="vbus767">
       <obj_property name="label">0</obj_property>
       <obj_property name="DisplayName">label</obj_property>
@@ -1968,34 +2097,6 @@
       <obj_property name="ElementShortName">wr_to_reg_final</obj_property>
       <obj_property name="ObjectShortName">wr_to_reg_final</obj_property>
    </wvobject>
-   <wvobject type="other" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(64)\/elink_bit_feeder/count_n">
-      <obj_property name="ElementShortName">count_n</obj_property>
-      <obj_property name="ObjectShortName">count_n</obj_property>
-   </wvobject>
-   <wvobject type="other" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(48)\/elink_bit_feeder/count_n">
-      <obj_property name="ElementShortName">count_n</obj_property>
-      <obj_property name="ObjectShortName">count_n</obj_property>
-   </wvobject>
-   <wvobject type="other" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(32)\/elink_bit_feeder/count_n">
-      <obj_property name="ElementShortName">count_n</obj_property>
-      <obj_property name="ObjectShortName">count_n</obj_property>
-   </wvobject>
-   <wvobject type="other" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(16)\/elink_bit_feeder/count_n">
-      <obj_property name="ElementShortName">count_n</obj_property>
-      <obj_property name="ObjectShortName">count_n</obj_property>
-   </wvobject>
-   <wvobject type="other" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(0)\/elink_bit_feeder/count_n">
-      <obj_property name="ElementShortName">count_n</obj_property>
-      <obj_property name="ObjectShortName">count_n</obj_property>
-   </wvobject>
-   <wvobject type="other" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(80)\/elink_bit_feeder/count_n">
-      <obj_property name="ElementShortName">count_n</obj_property>
-      <obj_property name="ObjectShortName">count_n</obj_property>
-   </wvobject>
-   <wvobject type="other" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(96)\/elink_bit_feeder/count_n">
-      <obj_property name="ElementShortName">count_n</obj_property>
-      <obj_property name="ObjectShortName">count_n</obj_property>
-   </wvobject>
    <wvobject type="logic" fp_name="/felig_sim_top_bnl712/EmulatorWrapper_comp/\emulator_inst(0)\/gbt/elink_muxer_v2/\gen_elink_printers(64)\/elink_bit_feeder/reg_160_8b10b[9]">
       <obj_property name="ElementShortName">[9]</obj_property>
       <obj_property name="ObjectShortName">[9]</obj_property>
diff --git a/sources/FELIG/LinkWrapper/FELIG_LpGBT_Wrapper.vhd b/sources/FELIG/LinkWrapper/FELIG_LpGBT_Wrapper.vhd
index e3afe3d61e8bc580ec445570665807bc3125db15..ee746fbe8a82ab361e5c8bdb3bd4b9316670ae9b 100644
--- a/sources/FELIG/LinkWrapper/FELIG_LpGBT_Wrapper.vhd
+++ b/sources/FELIG/LinkWrapper/FELIG_LpGBT_Wrapper.vhd
@@ -41,213 +41,122 @@ library UNISIM;
     use work.FELIX_package.all;
     use work.pcie_package.all;
 
+Library xpm;
+    use xpm.vcomponents.all;
+
 entity FELIX_LpGBT_Wrapper_FELIG is
     Generic (
         STABLE_CLOCK_PERIOD         : integer   := 24;
-        -- period of the drp_clock
         GBT_NUM                     : integer   := 24;
-        PRBS_TEST_EN                : integer := 1;
+        PRBS_TEST_EN                : integer   := 1;
         GTHREFCLK_SEL               : std_logic := '0';
-        -- GREFCLK              : std_logic := '1';
-        -- MGTREFCLK            : std_logic := '0';
         CARD_TYPE                   : integer   := 712;
-        --        FE_EMU_EN                   : integer   := 1;    --MT commented
         CLK_CHIP_SEL                : integer   := 1;
-        -- SI5345               : integer   := 0;
-        -- LMK03200             : integer   := 1;
-        PLL_SEL                     : std_logic := '0';
-        -- CPLL : '0'
-        -- QPLL : '1'
-        --MT SIMU+
-        sim_emulator            : boolean       := false
-    --
-
-
+        PLL_SEL                     : std_logic := '1';
+        sim_emulator                : boolean   := false
     );
     Port (
         rst_hw                      : in std_logic;
         rxrecclk40m_out             : out std_logic;
         register_map_control        : in register_map_control_type;
-        register_map_link_monitor    : out register_map_link_monitor_type;
-
+        register_map_link_monitor   : out register_map_link_monitor_type;
         CLK40_IN                    : in std_logic;
-        clk320_in                   : in std_logic; --MT SIMU+
+        clk320_in                   : in std_logic;
         GREFCLK_IN                  : in std_logic;
-        RX320_CH0                   : out std_logic;
-
         GTREFCLK_P_s                : in std_logic_vector(4 downto 0);
         GTREFCLK_N_s                : in std_logic_vector(4 downto 0);
         LMK_P                       : in std_logic_vector(7 downto 0);
         LMK_N                       : in std_logic_vector(7 downto 0);
-
         RX_LINK_LCK                 : out std_logic_vector(GBT_NUM-1 downto 0);
-        --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-
-        --IC (2b) & EC (2b) & D (224b)
-        --TX_256b_in                  : in  txrx256b_type(0 to GBT_NUM-1); --MT txrx120b_type(0 to GBT_NUM-1);
-        TX_2b_IC_in                : in txrx2b_type(0 to GBT_NUM-1); --RL
-        TX_2b_EC_in                : in txrx2b_type(0 to GBT_NUM-1); --RL
-        TX_224b_DATA_in            : in txrx224b_type(0 to GBT_NUM-1); --RL
-        --IC (2b) & EC (2b) & D (32b)
-        --RX_36b_out                 : out txrx36b_type(0 to GBT_NUM-1); --MT txrx120b_type(0 to GBT_NUM-1);
-        RX_2b_IC_out                : out txrx2b_type(0 to GBT_NUM-1); --RL
-        RX_2b_EC_out                : out txrx2b_type(0 to GBT_NUM-1); --RL
-        RX_32b_DATA_out             : out txrx32b_type(0 to GBT_NUM-1); --RL
-        --MT externalizing gtrx/txusrclk for FELIG logic
-        --
+        TX_2b_IC_in                 : in txrx2b_type(0 to GBT_NUM-1);
+        TX_2b_EC_in                 : in txrx2b_type(0 to GBT_NUM-1);
+        TX_224b_DATA_in             : in txrx224b_type(0 to GBT_NUM-1);
+        TX_ready_in                 : in std_logic_vector(0 to GBT_NUM-1);
+        RX_2b_IC_out                : out txrx2b_type(0 to GBT_NUM-1);
+        RX_2b_EC_out                : out txrx2b_type(0 to GBT_NUM-1);
+        RX_32b_DATA_out             : out txrx32b_type(0 to GBT_NUM-1);
         GT_TXUSRCLK_OUT             : out std_logic_vector(GBT_NUM-1 downto 0);
         GT_RXUSRCLK_OUT             : out std_logic_vector(GBT_NUM-1 downto 0);
-        --MT 40 MHZ rxusr clk to drive LMK
-        clk40_rxusrclk_out          : out std_logic;
-
-        TX_P                        : out std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-        TX_N                        : out std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-        RX_P                        : in  std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-        RX_N                        : in  std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-        --MT for FELIG from mgt_framealigner . 1 pulse every c_wordRatio (=8)
+        TX_P                        : out std_logic_vector(GBT_NUM-1 downto 0);
+        TX_N                        : out std_logic_vector(GBT_NUM-1 downto 0);
+        RX_P                        : in std_logic_vector(GBT_NUM-1 downto 0);
+        RX_N                        : in std_logic_vector(GBT_NUM-1 downto 0);
         sta_headerFlag_out          : out std_logic_vector(GBT_NUM-1 downto 0);
-        --MT added: needed by FELIG to latch tx payload to generated data. Need to
-        --be synchronized with emulator logic
         tx_flag_out                 : out std_logic_vector(GBT_NUM-1 downto 0);
-        --MT added: alignment flag needed by the emulator
         alignment_done_out          : out std_logic_vector(GBT_NUM-1 downto 0);
-        --MT added
-        RESET_TO_LMK                : out  std_logic;
-        --MT LMK lock signal
-        LMK_LD                      : in  std_logic;
-        --
-        LINKSconfig                 : in std_logic_vector(2 downto 0);
-        -- LMK03200 clock input pins added --MT/SS
-        CLK40_FPGA2LMK_out_P         : out std_logic;
-        CLK40_FPGA2LMK_out_N         : out std_logic
+        LMK_LD                      : in std_logic;
+        GT_RXCLK40                  : out std_logic;
+        alignment_done_to_LMK       : out std_logic;
+        RxCdrLock_to_LMK            : out std_logic
     );
 end FELIX_LpGBT_Wrapper_FELIG;
 
 
 architecture Behavioral of FELIX_LpGBT_Wrapper_FELIG is
 
-
-    signal GTH_REFCLK_LMK_OUT           : std_logic_vector(GBT_NUM-1 downto 0); --added
-    signal GTH_REFCLK_OUT           : std_logic_vector(GBT_NUM-1 downto 0);
-    --signal GTH_EMU_REFCLK_OUT       : std_logic_vector(GBT_NUM-1 downto 0);
-    ----MT commented
-
-    signal CTRL_TXPOLARITY           : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-    signal CTRL_RXPOLARITY           : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-    signal CTRL_GBTTXRST             : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-    signal CTRL_GBTRXRST             : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-    signal CTRL_FECMODE              : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-    signal CTRL_CHANNEL_DISABLE      : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-    signal MON_RXRSTDONE             : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-    signal MON_TXRSTDONE             : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-    signal MON_RXPMARSTDONE          : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-    signal MON_TXPMARSTDONE          : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-    signal MON_RXCDR_LCK             : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-    signal MON_CPLL_LCK              : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-    signal MON_ALIGNMENT_DONE        : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-    signal MON_LPGBT_ERRFLG          : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-
-    signal MON_RXRSTDONE_QUAD        : std_logic_vector(GBT_NUM/4-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0);
-    signal MON_TXRSTDONE_QUAD        : std_logic_vector(GBT_NUM/4-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0);
-    signal MON_RXCDR_LCK_QUAD        : std_logic_vector(GBT_NUM/4-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0);
-    signal MON_QPLL_LCK              : std_logic_vector(GBT_NUM/4-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0);
-
-
-    signal CTRL_SOFT_RESET           : std_logic_vector(GBT_NUM/4-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0);
-    signal CTRL_TXPLL_DATAPATH_RESET : std_logic_vector(GBT_NUM/4-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0);
-    signal CTRL_RXPLL_DATAPATH_RESET : std_logic_vector(GBT_NUM/4-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0);
-    signal CTRL_TX_DATAPATH_RESET    : std_logic_vector(GBT_NUM/4-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0);
-    signal CTRL_RX_DATAPATH_RESET    : std_logic_vector(GBT_NUM/4-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0);
-
-    signal CTRL_GBT_General_ctrl    : std_logic_vector(63 downto 0);
-    signal MON_FEC_ERROR            : std_logic_vector(GBT_NUM-1 downto 0);
-
-    --MT commented
-    --signal FELIX_DOWNLINK_USER_DATA    : txrx32b_type(GBT_NUM-1 downto 0);
-    --signal FELIX_DOWNLINK_IC_DATA    : txrx2b_type(GBT_NUM-1 downto 0);
-    --signal FELIX_DOWNLINK_EC_DATA    : txrx2b_type(GBT_NUM-1 downto 0);
-    --signal FELIX_UPLINK_USER_DATA      : txrx230b_type(GBT_NUM-1 downto 0);
-    --signal FELIX_UPLINK_EC_DATA        : txrx2b_type(GBT_NUM-1 downto 0);
-    --signal FELIX_UPLINK_IC_DATA        : txrx2b_type(GBT_NUM-1 downto 0);
-    --
-
-
-    signal FE_DOWNLINK_USER_DATA    : txrx32b_type(GBT_NUM-1 downto 0);
-    signal FE_DOWNLINK_IC_DATA    : txrx2b_type(GBT_NUM-1 downto 0);
-    signal FE_DOWNLINK_EC_DATA    : txrx2b_type(GBT_NUM-1 downto 0);
-    signal FE_UPLINK_USER_DATA      : txrx224b_type(GBT_NUM-1 downto 0);
-    signal FE_UPLINK_EC_DATA        : txrx2b_type(GBT_NUM-1 downto 0);
-    signal FE_UPLINK_IC_DATA        : txrx2b_type(GBT_NUM-1 downto 0);
-
-
-
-    --MT added
-    signal sta_headerFlag_i : std_logic_vector(GBT_NUM-1 downto 0);
-    signal LMK_PIPE               : std_logic_vector(3 downto 0);
-    signal LMK_RESET              : std_logic;
-
-    --
-    --RL
-    signal DATARATE             : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-    signal FECMODE              : std_logic_vector(GBT_NUM-1 downto 0); --MT std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0);
-
-
-    --RL
-
-    signal GT_RXUSRCLK_40MHz    : std_logic;
-    signal RxCdrLock_o          : std_logic_vector(GBT_NUM-1 downto 0);
-    signal alignment_done_o     : std_logic_vector(GBT_NUM-1 downto 0);
-
-    signal alignment_done_o_40rec   : std_logic;
-    signal sta_headerFlag_i_40rec   : std_logic;
-    signal RxCdrLock_o_40rec        : std_logic;
-
-    type STATEM  is (st_idle, st_wait_for_aligment, st_LMK_reseted);
-    signal state            : STATEM := st_idle;
-    signal LMK_RESET_b      : std_logic;
-
-    --RL this are lpgbt BE counters, not implemented in FE. signals are initiated to comply with Regs_RW inputs
-    signal MON_FEC_ERR_CNT          : array_32b(0 to GBT_NUM-1) := (others => (others => '0'));
-    signal MON_AUTO_RX_RESET_CNT    : array_32b(0 to GBT_NUM-1) := (others => (others => '0'));
-
---COMPONENT ila_SM_LMK IS
---PORT (
---    clk : IN STD_LOGIC;
---    probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
---    probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
---    probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
---    probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
---    probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
---    probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
---    probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
---);
---END COMPONENT;
-
---signal ila_st_idle                    : std_logic;
---signal ila_st_wait_for_aligment       : std_logic;
---signal ila_st_LMK_reseted             : std_logic;
---signal ila_ila_st_idle                : std_logic;
---signal ila_ila_st_wait_for_aligment   : std_logic;
---signal ila_ila_st_LMK_reseted         : std_logic;
---signal ila_RxCdrLock_o                : std_logic;
---signal ila_sta_headerFlag_i           : std_logic;
---signal ila_LMK_RESET_b                : std_logic;
---signal ila_alignment_done_o           : std_logic;
-
+    signal GTH_REFCLK_LMK_OUT           : std_logic_vector(GBT_NUM-1 downto 0);
+    signal GTH_REFCLK_OUT               : std_logic_vector(GBT_NUM-1 downto 0);
+
+    signal CTRL_TXPOLARITY              : std_logic_vector(GBT_NUM-1 downto 0);
+    signal CTRL_RXPOLARITY              : std_logic_vector(GBT_NUM-1 downto 0);
+    signal CTRL_GBTTXRST                : std_logic_vector(GBT_NUM-1 downto 0);
+    signal CTRL_GBTRXRST                : std_logic_vector(GBT_NUM-1 downto 0);
+    --signal CTRL_DATARATE             : std_logic_vector(GBT_NUM-1 downto 0);
+    signal CTRL_FECMODE                 : std_logic_vector(GBT_NUM-1 downto 0);
+    signal CTRL_CHANNEL_DISABLE         : std_logic_vector(GBT_NUM-1 downto 0);
+    signal MON_RXRSTDONE                : std_logic_vector(GBT_NUM-1 downto 0);
+    signal MON_TXRSTDONE                : std_logic_vector(GBT_NUM-1 downto 0);
+    signal MON_RXPMARSTDONE             : std_logic_vector(GBT_NUM-1 downto 0);
+    signal MON_TXPMARSTDONE              : std_logic_vector(GBT_NUM-1 downto 0);
+    signal MON_RXCDR_LCK                : std_logic_vector(GBT_NUM-1 downto 0);
+    signal MON_CPLL_LCK                 : std_logic_vector(GBT_NUM-1 downto 0);
+    signal MON_ALIGNMENT_DONE           : std_logic_vector(GBT_NUM-1 downto 0);
+    signal MON_LPGBT_ERRFLG             : std_logic_vector(GBT_NUM-1 downto 0);
+    --signal MON_RXRSTDONE_QUAD        : std_logic_vector(GBT_NUM/4-1 downto 0);
+    --signal MON_TXRSTDONE_QUAD        : std_logic_vector(GBT_NUM/4-1 downto 0);
+    --signal MON_RXCDR_LCK_QUAD        : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal MON_QPLL_LCK                 : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal CTRL_SOFT_RESET              : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal CTRL_TXPLL_DATAPATH_RESET    : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal CTRL_RXPLL_DATAPATH_RESET    : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal CTRL_TX_DATAPATH_RESET       : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal CTRL_RX_DATAPATH_RESET       : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal CTRL_GBT_General_ctrl        : std_logic_vector(63 downto 0);
+    signal MON_FEC_ERROR                : std_logic_vector(GBT_NUM-1 downto 0);
+    signal MON_FEC_ERR_CNT              : array_32b(0 to GBT_NUM-1) := (others => (others => '0'));
+    signal MON_AUTO_RX_RESET_CNT        : array_32b(0 to GBT_NUM-1) := (others => (others => '0'));
+    signal CTRL_AUTO_RX_RESET_CNT_CLEAR :  std_logic_vector(GBT_NUM-1 downto 0);
+
+    signal FE_DOWNLINK_USER_DATA        : txrx32b_type(0 to GBT_NUM-1);
+    signal FE_DOWNLINK_IC_DATA          : txrx2b_type(0 to GBT_NUM-1);
+    signal FE_DOWNLINK_EC_DATA          : txrx2b_type(0 to GBT_NUM-1);
+    signal FE_UPLINK_USER_DATA          : txrx224b_type(0 to GBT_NUM-1);
+    signal FE_UPLINK_EC_DATA            : txrx2b_type(0 to GBT_NUM-1);
+    signal FE_UPLINK_IC_DATA            : txrx2b_type(0 to GBT_NUM-1);
+
+    signal sta_headerFlag_i             : std_logic_vector(GBT_NUM-1 downto 0);
+
+
+    signal DATARATE                     : std_logic_vector(GBT_NUM-1 downto 0);
+    signal FECMODE                      : std_logic_vector(GBT_NUM-1 downto 0);
+
+    signal RxCdrLock_o                  : std_logic_vector(GBT_NUM-1 downto 0);
+    signal alignment_done_o             : std_logic_vector(GBT_NUM-1 downto 0);
+
+    signal alignment_done_o_40rec       : std_logic;
+    signal sta_headerFlag_i_40rec       : std_logic;
+    signal RxCdrLock_o_40rec            : std_logic;
 begin
 
-    --MT commented: data to/from _BE_ or PRBS. Not needed. RL: removed commented lines
-
     refclk_notsim : if sim_emulator = false generate
+        --SI5345
         Reference_Clk_Gen_SI5345 : entity work.RefClk_Gen
             Generic Map(
                 GBT_NUM => GBT_NUM,
                 CARD_TYPE                   => CARD_TYPE,
-                CLK_CHIP_SEL                => 0 -- SI5345
+                CLK_CHIP_SEL                => 0
             )
             Port Map(
-                --GREFCLK_IN                  => GREFCLK_IN, --not used
-
                 SI53XX_0_P                  => GTREFCLK_P_s(0),
                 SI53XX_0_N                  => GTREFCLK_N_s(0),
                 SI53XX_2_P                  => GTREFCLK_P_s(1),
@@ -281,16 +190,14 @@ begin
 
                 GTH_REFCLK_OUT              => GTH_REFCLK_OUT
             );
-
+        -- LMK03200
         Reference_Clk_Gen_LMK03200 : entity work.RefClk_Gen
             Generic Map(
                 GBT_NUM => GBT_NUM,
                 CARD_TYPE                   => CARD_TYPE,
-                CLK_CHIP_SEL                => 1 -- LMK03200
+                CLK_CHIP_SEL                => 1
             )
             Port Map(
-                --GREFCLK_IN                  => GREFCLK_IN, --not used
-
                 SI53XX_0_P                  => GTREFCLK_P_s(0),
                 SI53XX_0_N                  => GTREFCLK_N_s(0),
                 SI53XX_2_P                  => GTREFCLK_P_s(1),
@@ -329,68 +236,43 @@ begin
     REGS_INTERFACE : entity work.Regs_RW
         Generic map(
             GBT_NUM                     => GBT_NUM,
-            --FE_EMU_EN                   => 0 --MT FE_EMU_EN
             CARD_TYPE                   => CARD_TYPE
         )
         Port map(
 
-            CTRL_SOFT_RESET             => CTRL_SOFT_RESET,
-            CTRL_TXPLL_DATAPATH_RESET   => CTRL_TXPLL_DATAPATH_RESET,
-            CTRL_RXPLL_DATAPATH_RESET   => CTRL_RXPLL_DATAPATH_RESET,
-            CTRL_TX_DATAPATH_RESET      => CTRL_TX_DATAPATH_RESET,
-            CTRL_RX_DATAPATH_RESET      => CTRL_RX_DATAPATH_RESET,
-            CTRL_TXPOLARITY             => CTRL_TXPOLARITY,
-            CTRL_RXPOLARITY             => CTRL_RXPOLARITY,
-            CTRL_GBTTXRST               => CTRL_GBTTXRST,
-            CTRL_GBTRXRST               => CTRL_GBTRXRST,
-            CTRL_CHANNEL_DISABLE        => CTRL_CHANNEL_DISABLE,
-            CTRL_FECMODE                => CTRL_FECMODE,
-            --CTRL_DATARATE               => CTRL_DATARATE,--RL
-            CTRL_GBT_General_ctrl       => CTRL_GBT_General_ctrl,
-
-
-
-            MON_RXRSTDONE               => MON_RXRSTDONE,
-            MON_TXRSTDONE               => MON_TXRSTDONE,
-
-            -- RL: used for 709, not relevant here
-            MON_TXFSMRESETDONE          => (others => '0'),
-            MON_RXFSMRESETDONE          => (others => '0'),
-            --MON_RXRSTDONE_QUAD          => MON_RXRSTDONE_QUAD,--RL
-            --MON_TXRSTDONE_QUAD          => MON_TXRSTDONE_QUAD,--RL
-            MON_RXPMARSTDONE            => MON_RXPMARSTDONE,
-            MON_TXPMARSTDONE            => MON_TXPMARSTDONE,
-            MON_RXCDR_LCK               => MON_RXCDR_LCK,
-            --MON_RXCDR_LCK_QUAD          => MON_RXCDR_LCK_QUAD,--RL
-            MON_QPLL_LCK                => MON_QPLL_LCK,
-            MON_CPLL_LCK                => MON_CPLL_LCK,
-
-            MON_ALIGNMENT_DONE          => MON_ALIGNMENT_DONE,
-            --MON_LPGBT_ERRFLG            => MON_LPGBT_ERRFLG, --RL
-
-            MON_FEC_ERROR               =>  MON_FEC_ERROR,
-            MON_FEC_ERR_CNT             => MON_FEC_ERR_CNT, --RL see comment at signal definition july 2023
-            MON_AUTO_RX_RESET_CNT       => MON_AUTO_RX_RESET_CNT, --RL see comment at signal definition july 2023
-            --CTRL_PRBS_ERR_CLR           => PRBS_ERR_CLR,
-            --CTRL_ERROR_CNT_SEL          => PRBS_CH_SEL,
-
-            clk40_in                    => CLK40_IN, --RL add july 2023
-            register_map_control        => register_map_control,
-            register_map_link_monitor    => register_map_link_monitor
+            CTRL_SOFT_RESET                 => CTRL_SOFT_RESET,
+            CTRL_TXPLL_DATAPATH_RESET       => CTRL_TXPLL_DATAPATH_RESET,
+            CTRL_RXPLL_DATAPATH_RESET       => CTRL_RXPLL_DATAPATH_RESET,
+            CTRL_TX_DATAPATH_RESET          => CTRL_TX_DATAPATH_RESET,
+            CTRL_RX_DATAPATH_RESET          => CTRL_RX_DATAPATH_RESET,
+            CTRL_TXPOLARITY                 => CTRL_TXPOLARITY,
+            CTRL_RXPOLARITY                 => CTRL_RXPOLARITY,
+            CTRL_GBTTXRST                   => CTRL_GBTTXRST,
+            CTRL_GBTRXRST                   => CTRL_GBTRXRST,
+            CTRL_CHANNEL_DISABLE            => CTRL_CHANNEL_DISABLE,
+            CTRL_FECMODE                    => CTRL_FECMODE,
+            CTRL_GBT_General_ctrl           => CTRL_GBT_General_ctrl,
+            MON_RXRSTDONE                   => MON_RXRSTDONE,
+            MON_TXRSTDONE                   => MON_TXRSTDONE,
+            MON_TXFSMRESETDONE              => (others => '0'),
+            MON_RXFSMRESETDONE              => (others => '0'),
+            MON_RXPMARSTDONE                => MON_RXPMARSTDONE,
+            MON_TXPMARSTDONE                => MON_TXPMARSTDONE,
+            MON_RXCDR_LCK                   => MON_RXCDR_LCK,
+            MON_QPLL_LCK                    => MON_QPLL_LCK,
+            MON_CPLL_LCK                    => MON_CPLL_LCK,
+            MON_ALIGNMENT_DONE              => MON_ALIGNMENT_DONE,
+            MON_FEC_ERROR                   => MON_FEC_ERROR,
+            MON_FEC_ERR_CNT                 => MON_FEC_ERR_CNT,
+            MON_AUTO_RX_RESET_CNT           => MON_AUTO_RX_RESET_CNT,
+            CTRL_AUTO_RX_RESET_CNT_CLEAR    => CTRL_AUTO_RX_RESET_CNT_CLEAR,
+
+            clk40_in                        => CLK40_IN,
+            register_map_control            => register_map_control,
+            register_map_link_monitor       => register_map_link_monitor
 
         );
 
-    --RL removed commented lines with
-    --PRBS_TEST: if PRBS_TEST_EN = 1 generate
-    --and
-    --FLX_LpGBT_BE_INST: entity work.FLX_LpGBT_BE_Wrapper
-
-    --MT commented
-    --    FLX_LpGBT_FE_EMU_INST: if FE_EMU_EN = 1 generate
-    --
-    --
-
-    --MT added. RL: changed to match link_wrapper inputs
     RX_DOWNLINK_inst: for I in 0 to GBT_NUM - 1 generate
         RX_2b_IC_out(I) <= FE_DOWNLINK_IC_DATA(I);
         RX_2b_EC_out(I) <= FE_DOWNLINK_EC_DATA(I);
@@ -403,9 +285,8 @@ begin
         FE_UPLINK_USER_DATA(I) <= TX_224b_DATA_in(I);
     end generate TX_UPLINK_inst;
 
-    --RL: Added DATARATE and FECMODE for FELIG
-    DATARATE <= (others => LINKSconfig(1));
-    FECMODE  <= (others => LINKSconfig(0));
+    DATARATE <= (others => '1'); --10.24
+    FECMODE  <= CTRL_FECMODE;
 
     FLX_LpGBT_FE_INST: entity work.FLX_LpGBT_FE_Wrapper_FELIG
         Generic map(
@@ -413,39 +294,22 @@ begin
             sim_emulator                => sim_emulator
         )
         Port map(
-
             clk40_in                    => clk40_in,
-            clk320_in                   => clk320_in, --MT SIMU+
+            clk320_in                   => clk320_in,
             rst_hw                      => rst_hw,
-            --MT commented
-            --        FE_SIDE_RX40MCLK            => FE_SIDE_RX40MCLK,
-            --MT added
-            FE_SIDE_RX40MCLK            => clk40_rxusrclk_out, --40 MHZ CLK from
-            --CLKWIZ (input
-            --RXUSRCLK 320)
-            --MT commented
-            --GTHREFCLK                   => GTH_REFCLK_OUT, --MT GTH_EMU_REFCLK_OUT,
-            --MT added
-            GTHREFCLK0                   => GTH_REFCLK_OUT,     --SI  RX 320
-            GTHREFCLK1                   => GTH_REFCLK_LMK_OUT, --LMK TX 240
-            --
-            --MT externalizing gtrx/txusrclk for FELIG logic
-            GT_TXUSRCLK_OUT           => GT_TXUSRCLK_OUT,
-            GT_RXUSRCLK_OUT           => GT_RXUSRCLK_OUT,
-            --
-
-            --MT commented
-            --RX_P                        => RX_P(GBT_NUM*2-1 downto GBT_NUM),
-            --RX_N                        => RX_N(GBT_NUM*2-1 downto GBT_NUM),
-            --TX_P                        => TX_P(GBT_NUM*2-1 downto GBT_NUM),
-            --TX_N                        => TX_N(GBT_NUM*2-1 downto GBT_NUM),
-            --MT added
+
+            GTHREFCLK0                   => GTH_REFCLK_OUT,
+            GTHREFCLK1                   => GTH_REFCLK_LMK_OUT,
+
+            GT_TXUSRCLK_OUT             => GT_TXUSRCLK_OUT,
+            GT_RXUSRCLK_OUT             => GT_RXUSRCLK_OUT,
+            GT_RXCLK40_OUT              => GT_RXCLK40,
+
             RX_P                        => RX_P(GBT_NUM-1 downto 0),
             RX_N                        => RX_N(GBT_NUM-1 downto 0),
             TX_P                        => TX_P(GBT_NUM-1 downto 0),
             TX_N                        => TX_N(GBT_NUM-1 downto 0),
 
-
             FE_DOWNLINK_USER_DATA       => FE_DOWNLINK_USER_DATA,
             FE_DOWNLINK_EC_DATA         => FE_DOWNLINK_EC_DATA,
             FE_DOWNLINK_IC_DATA         => FE_DOWNLINK_IC_DATA,
@@ -453,37 +317,7 @@ begin
             FE_UPLINK_USER_DATA         => FE_UPLINK_USER_DATA,
             FE_UPLINK_EC_DATA           => FE_UPLINK_EC_DATA,
             FE_UPLINK_IC_DATA           => FE_UPLINK_IC_DATA,
-
-            --MT using _BE_ reg ranges instead
-            --CTRL_SOFT_RESET             => CTRL_SOFT_RESET(GBT_NUM/2-1 downto GBT_NUM/4),
-            --CTRL_TXPLL_DATAPATH_RESET   => CTRL_TXPLL_DATAPATH_RESET(GBT_NUM/2-1 downto GBT_NUM/4),
-            --CTRL_RXPLL_DATAPATH_RESET   => CTRL_RXPLL_DATAPATH_RESET(GBT_NUM/2-1 downto GBT_NUM/4),
-            --CTRL_TX_DATAPATH_RESET      => CTRL_TX_DATAPATH_RESET(GBT_NUM/2-1 downto GBT_NUM/4),
-            --CTRL_RX_DATAPATH_RESET      => CTRL_RX_DATAPATH_RESET(GBT_NUM/2-1 downto GBT_NUM/4),
-            --CTRL_TXPOLARITY             => CTRL_TXPOLARITY(2*GBT_NUM-1 downto GBT_NUM),
-            --CTRL_RXPOLARITY             => CTRL_TXPOLARITY(2*GBT_NUM-1 downto GBT_NUM),
-            --CTRL_GBTTXRST               => CTRL_GBTTXRST(2*GBT_NUM-1 downto GBT_NUM),
-            --CTRL_GBTRXRST               => CTRL_GBTRXRST(2*GBT_NUM-1 downto GBT_NUM),
-            --CTRL_DATARATE               => CTRL_DATARATE(2*GBT_NUM-1 downto GBT_NUM),
-            --CTRL_FECMODE                => CTRL_FECMODE(2*GBT_NUM-1 downto GBT_NUM),
-            --CTRL_CHANNEL_DISABLE        => CTRL_CHANNEL_DISABLE(2*GBT_NUM-1 downto GBT_NUM),
-            --CTRL_GBT_General_ctrl       => CTRL_GBT_General_ctrl,
-
-
-
-            --MON_RXRSTDONE               => MON_RXRSTDONE(2*GBT_NUM-1 downto GBT_NUM),
-            --MON_TXRSTDONE               => MON_TXRSTDONE(2*GBT_NUM-1 downto GBT_NUM),
-            --MON_RXRSTDONE_QUAD          => MON_RXRSTDONE_QUAD(GBT_NUM/2-1 downto GBT_NUM/4),
-            --MON_TXRSTDONE_QUAD          => MON_TXRSTDONE_QUAD(GBT_NUM/2-1 downto GBT_NUM/4),
-            --MON_RXPMARSTDONE            => MON_RXPMARSTDONE(2*GBT_NUM-1 downto GBT_NUM),
-            --MON_TXPMARSTDONE            => MON_TXPMARSTDONE(2*GBT_NUM-1 downto GBT_NUM),
-            --MON_RXCDR_LCK               => MON_RXCDR_LCK(2*GBT_NUM-1 downto GBT_NUM),
-            --MON_RXCDR_LCK_QUAD          => MON_RXCDR_LCK_QUAD(GBT_NUM/2-1 downto GBT_NUM/4),
-            --MON_QPLL_LCK                => MON_QPLL_LCK(GBT_NUM/2-1 downto GBT_NUM/4),
-            --MON_CPLL_LCK                => MON_CPLL_LCK(2*GBT_NUM-1 downto GBT_NUM),
-
-            --MON_ALIGNMENT_DONE          => MON_ALIGNMENT_DONE(2*GBT_NUM-1 downto GBT_NUM),
-            --MON_LPGBT_ERRFLG            => MON_LPGBT_ERRFLG(2*GBT_NUM-1 downto GBT_NUM),
+            FE_UPLINK_READY             => TX_ready_in,
 
             CTRL_SOFT_RESET             => CTRL_SOFT_RESET(GBT_NUM/4-1 downto 0),
             CTRL_TXPLL_DATAPATH_RESET   => CTRL_TXPLL_DATAPATH_RESET(GBT_NUM/4-1 downto 0),
@@ -494,177 +328,36 @@ begin
             CTRL_RXPOLARITY             => CTRL_TXPOLARITY(GBT_NUM-1 downto 0),
             CTRL_GBTTXRST               => CTRL_GBTTXRST(GBT_NUM-1 downto 0),
             CTRL_GBTRXRST               => CTRL_GBTRXRST(GBT_NUM-1 downto 0),
-            CTRL_DATARATE               => DATARATE,--CTRL_DATARATE(GBT_NUM-1 downto 0), --RL removed from Reg_RW
-            CTRL_FECMODE                => FECMODE,--CTRL_FECMODE(GBT_NUM-1 downto 0),
+            CTRL_DATARATE               => DATARATE,
+            CTRL_FECMODE                => FECMODE,
             CTRL_CHANNEL_DISABLE        => CTRL_CHANNEL_DISABLE(GBT_NUM-1 downto 0),
             CTRL_GBT_General_ctrl       => CTRL_GBT_General_ctrl,
-
-
-
             MON_RXRSTDONE               => MON_RXRSTDONE(GBT_NUM-1 downto 0),
             MON_TXRSTDONE               => MON_TXRSTDONE(GBT_NUM-1 downto 0),
-            MON_RXRSTDONE_QUAD          => MON_RXRSTDONE_QUAD(GBT_NUM/4-1 downto 0), --RL removed from Reg_RW
-            MON_TXRSTDONE_QUAD          => MON_TXRSTDONE_QUAD(GBT_NUM/4-1 downto 0), --RL removed from Reg_RW
+            MON_RXRSTDONE_QUAD          => open,
+            MON_TXRSTDONE_QUAD          => open,
             MON_RXPMARSTDONE            => MON_RXPMARSTDONE(GBT_NUM-1 downto 0),
             MON_TXPMARSTDONE            => MON_TXPMARSTDONE(GBT_NUM-1 downto 0),
             MON_RXCDR_LCK               => MON_RXCDR_LCK(GBT_NUM-1 downto 0),
-            MON_RXCDR_LCK_QUAD          => MON_RXCDR_LCK_QUAD(GBT_NUM/4-1 downto 0), --RL removed from Reg_RW
+            MON_RXCDR_LCK_QUAD          => open,
             MON_QPLL_LCK                => MON_QPLL_LCK(GBT_NUM/4-1 downto 0),
             MON_CPLL_LCK                => MON_CPLL_LCK(GBT_NUM-1 downto 0),
-
             MON_ALIGNMENT_DONE          => MON_ALIGNMENT_DONE(GBT_NUM-1 downto 0),
-            MON_LPGBT_ERRFLG            => MON_LPGBT_ERRFLG(GBT_NUM-1 downto 0),  --RL removed from Reg_RW
-
-            --MT for FELIG from mgt_framealigner . 1 pulse every c_wordRatio (=8)
-            sta_headerFlag_out         => sta_headerFlag_i,
-            --
-            --MT added: needed by FELIG to latch tx payload to generated data. Need to
-            --be synchronized with emulator logic
-            tx_flag_out                => tx_flag_out,
-            --MT LMK lock signal
-            LMK_LD                     => LMK_LD,
-            RxCdrLock_o                => RxCdrLock_o,
-            alignment_done_o           => alignment_done_o
+            MON_LPGBT_ERRFLG            => MON_LPGBT_ERRFLG(GBT_NUM-1 downto 0),
+
+            sta_headerFlag_out          => sta_headerFlag_i,
+            tx_flag_out                 => tx_flag_out,
+            LMK_LD                      => LMK_LD,
+            RxCdrLock_o                 => RxCdrLock_o,
+            alignment_done_o            => alignment_done_o,
+            MON_AUTO_RX_RESET_CNT       => MON_AUTO_RX_RESET_CNT,
+            CTRL_AUTO_RX_RESET_CNT_CLEAR=> CTRL_AUTO_RX_RESET_CNT_CLEAR,
+            MON_FEC_ERROR               => MON_FEC_ERROR,
+            MON_FEC_ERR_CNT             => MON_FEC_ERR_CNT
         );
-    sta_headerFlag_out <= sta_headerFlag_i; --MT added
-    alignment_done_out <= MON_ALIGNMENT_DONE; --MT added
-
-    --MT commented
-    --    end generate;
-    --
-
-    --RL: coppied from GBT wrapper. sends the RX clock to the LMK
-    bufgceobuf_notsim : if sim_emulator = false generate
-        -- BUFGCE_DIV instantiation: added MT/SS
-        BUFGCE_DIV_inst : BUFGCE_DIV
-            generic map (
-                BUFGCE_DIVIDE => 8, -- 1-8 -divide by 8 to get 40 MHz
-                -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
-                IS_CE_INVERTED => '0', -- Optional inversion for CE
-                IS_CLR_INVERTED => '0', -- Optional inversion for CLR
-                IS_I_INVERTED => '0' -- Optional inversion for I
-            )
-            port map (
-                O => GT_RXUSRCLK_40MHz, -- 1-bit output: Buffer
-                CE => '1', -- 1-bit input: Buffer enable
-                CLR => '0', -- 1-bit input: Asynchronous clear
-                I => GT_RXUSRCLK_OUT(0) -- 1-bit input: Buffer 240 MHz RXUSER_CLK after BUFG_GT
-            );
-        -- End of BUFGCE_DIV_inst instantiation
-
-        --OBUFDS to route the 240 MHz RXUSER CLK into the LMK03200 jitter cleaner  to create the TXREFCLK --MT/SS
-        OBUF240_LMK03200: OBUFDS
-            generic map (
-                IOSTANDARD => "LVDS",
-                SLEW       => "FAST")
-            port map(
-                I => GT_RXUSRCLK_40MHz,
-                O => CLK40_FPGA2LMK_out_P,
-                OB => CLK40_FPGA2LMK_out_N);
-    end generate; --bufgceobuf_notsim
-
-    --- LMK Reset Process----- MT
-    --   alignment_done_inv <= not sta_headerFlag_i(0);
-    --MT SIMU+
-    resetlmk_sim : if sim_emulator = true generate
-        RESET_TO_LMK <= '0';
-    end generate;
-    --
-
-    resetlmk_notsim : if sim_emulator = false generate
-        process(clk40_in)
-        begin
-            if (clk40_in'event and clk40_in='1') then  --rising_edge(clk40_in)
-                LMK_PIPE(3 downto 1) <= LMK_PIPE(2 downto 0);
-                LMK_PIPE(0) <= LMK_RESET_b; --sta_headerFlag_i(0)
-                if ((LMK_PIPE(3) = '0') AND (LMK_PIPE(0) = '1')) then --rising edge
-                    LMK_RESET  <= '1';
-                else
-                    LMK_RESET  <= '0';
-                end if;
-            end if;
-        end process;
-        RESET_TO_LMK <= LMK_RESET; -- MT
-    end generate;  --resetlmk_notsim
-
-    --RL state machine that generates LMK_RESET
-
-    process(clk40_rxusrclk_out)
-    begin
-        if (clk40_rxusrclk_out'event and clk40_rxusrclk_out='1') then
-            sta_headerFlag_i_40rec <= sta_headerFlag_i(0);
-            RxCdrLock_o_40rec <= RxCdrLock_o(0);
-            alignment_done_o_40rec <= alignment_done_o(0);
-        end if;
-    end process;
-
-    process(clk40_rxusrclk_out)
-    begin
-        if (clk40_rxusrclk_out'event and clk40_rxusrclk_out='1') then
-       sm_lmk_reset: case state is
-                when st_idle =>
-                    --           ila_st_idle              <= '1';
-                    --           ila_st_wait_for_aligment <= '0';
-                    --           ila_st_LMK_reseted       <= '0';
-                    LMK_RESET_b <= '0';
-                    if RxCdrLock_o_40rec = '1' then
-                        state <= st_wait_for_aligment;
-                    else
-                        state <= st_idle;
-                    end if;
-                when st_wait_for_aligment =>
-                    --           ila_st_idle              <= '0';
-                    --           ila_st_wait_for_aligment <= '1';
-                    --           ila_st_LMK_reseted       <= '0';
-                    if alignment_done_o_40rec = '1'then
-                        LMK_RESET_b <= '1';
-                        state <= st_LMK_reseted;
-                    elsif RxCdrLock_o_40rec = '0' then
-                        LMK_RESET_b <= '0';
-                        state <= st_idle;
-                    else
-                        LMK_RESET_b <= '0';
-                        state <= st_wait_for_aligment;
-                    end if;
-                when st_LMK_reseted =>
-                    --           ila_st_idle              <= '0';
-                    --           ila_st_wait_for_aligment <= '0';
-                    --           ila_st_LMK_reseted       <= '1';
-                    LMK_RESET_b <= '0';
-                    if RxCdrLock_o_40rec = '0' and LMK_RESET_b <= '0'then
-                        state <= st_idle;
-                    else
-                        state <= st_LMK_reseted;
-                    end if;
-                when others =>
-                    state <= st_idle;
-            end case sm_lmk_reset;
-        end if;
-    end process;
-
---  process(clk40_in)
---  begin
---    if (clk40_in'event and clk40_in='1') then
---      ila_RxCdrLock_o <= RxCdrLock_o_40rec;
---      ila_sta_headerFlag_i <= sta_headerFlag_i_40rec;
---      ila_LMK_RESET_b <= LMK_RESET_b;
---      ila_alignment_done_o <= alignment_done_o_40rec;
---      ila_ila_st_idle <= ila_st_idle;
---      ila_ila_st_wait_for_aligment <= ila_st_wait_for_aligment;
---      ila_ila_st_LMK_reseted <= ila_st_LMK_reseted;
---    end if;
---  end process;
-
---  ila_STATE_LMK : ila_SM_LMK
---    port map(
---      clk       => clk40_in,
---      probe0(0) => ila_ila_st_idle,
---      probe1(0) => ila_ila_st_wait_for_aligment,
---      probe2(0) => ila_ila_st_LMK_reseted,
---      probe3(0) => ila_RxCdrLock_o,
---      probe4(0) => ila_sta_headerFlag_i,
---      probe5(0) => ila_LMK_RESET_b,
---      probe6(0) => ila_alignment_done_o
---    );
+    sta_headerFlag_out      <= sta_headerFlag_i;
+    alignment_done_out      <= alignment_done_o;
+    RxCdrLock_to_LMK        <= RxCdrLock_o(0);
+    alignment_done_to_LMK   <= MON_ALIGNMENT_DONE(0);
 
 end Behavioral;
diff --git a/sources/FELIG/LinkWrapper/FELIX_gbt_wrapper_FELIGKCU.vhd b/sources/FELIG/LinkWrapper/FELIX_gbt_wrapper_FELIGKCU.vhd
index 8590af1226cd1d09af57bd69a3050496f50340e1..cdd2b77e399858205cdd43d87737e55396a29248 100644
--- a/sources/FELIG/LinkWrapper/FELIX_gbt_wrapper_FELIGKCU.vhd
+++ b/sources/FELIG/LinkWrapper/FELIX_gbt_wrapper_FELIGKCU.vhd
@@ -41,41 +41,20 @@ library UNISIM;
     use work.pcie_package.all;
     use ieee.numeric_std.all;
     use work.sim_lib.all; --MT SIMU+
-
+library XPM;
+    use XPM.VComponents.all;
 entity FELIX_gbt_wrapper_FELIGKCU is
     Generic (
-        STABLE_CLOCK_PERIOD         : integer   := 24;  --period of the drp_clock
         GBT_NUM                     : integer := 24;
         GTHREFCLK_SEL               : std_logic := '1'; --GREFCLK        : std_logic := '1';
-        --MGTREFCLK      : std_logic := '0';
         CARD_TYPE                   : integer := 712;
-        PLL_SEL                     : std_logic := '0';  -- CPLL : '0'
-        -- QPLL : '1'
-        --QUAD_NUM                  : integer := 6
-        --MT added for simu
-        sim_emulator            : boolean       := false
-    --
+        PLL_SEL                     : std_logic := '0';  -- CPLL : '0' -- QPLL : '1'
+        sim_emulator                : boolean := false
     );
     Port (
-        -------------------
-        ---- For debug
-        -------------------
-        -- For Debugging
-        RX_FLAG_O                   : out std_logic_vector(GBT_NUM-1 downto 0);
-        TX_FLAG_O                   : out std_logic_vector(GBT_NUM-1 downto 0);
-        REFCLK_CXP1                 : out std_logic;
-        REFCLK_CXP2                 : out std_logic;
-        -- added MT/SS for LMK03200
-        REFCLK_CXP1_LMK                 : out std_logic;
-        REFCLK_CXP2_LMK                 : out std_logic;
-        --
         rst_hw                      : in std_logic;
-
         register_map_control        : in register_map_control_type;
         register_map_gbt_monitor    : out register_map_link_monitor_type;
-
-        -- GTH REFCLK, DRPCLK, GREFCLK
-        DRP_CLK_IN                  : in std_logic;
         Q2_CLK0_GTREFCLK_PAD_N_IN   : in std_logic;
         Q2_CLK0_GTREFCLK_PAD_P_IN   : in std_logic;
         Q8_CLK0_GTREFCLK_PAD_N_IN   : in std_logic;
@@ -87,337 +66,229 @@ entity FELIX_gbt_wrapper_FELIGKCU is
         Q6_CLK0_GTREFCLK_PAD_N_IN   : in std_logic;
         Q6_CLK0_GTREFCLK_PAD_P_IN   : in std_logic;
         GREFCLK_IN                  : in std_logic;
-        -- LMK03200 GTH REF clocks -- MT/SS
-        LMK_GTH_REFCLK1_P         : in     std_logic;
-        LMK_GTH_REFCLK1_N         : in     std_logic;
-        LMK_GTH_REFCLK3_P         : in     std_logic;
-        LMK_GTH_REFCLK3_N         : in     std_logic;
-        --
+        LMK_GTH_REFCLK1_P           : in std_logic;
+        LMK_GTH_REFCLK1_N           : in std_logic;
+        LMK_GTH_REFCLK3_P           : in std_logic;
+        LMK_GTH_REFCLK3_N           : in std_logic;
         clk40_in                    : in std_logic;
         clk240_in                   : in std_logic;
-        -- for CentralRouter
-        TX_120b_in                  : in  txrx120b_type(0 to GBT_NUM-1);
+        TX_120b_in                  : in txrx120b_type(0 to GBT_NUM-1);
         RX_120b_out                 : out txrx120b_type(0 to GBT_NUM-1);
         FRAME_LOCKED_O              : out std_logic_vector(GBT_NUM-1 downto 0);
-        -- TX_ISDATA_I              : in std_logic_vector(GBT_NUM-1 downto 0);
-        -- RX_ISDATA_O              : out std_logic_vector(GBT_NUM-1 downto 0);
-        -- RX_FRAME_CLK_O           : out std_logic_vector(GBT_NUM-1 downto 0);
         TX_FRAME_CLK_I              : in std_logic_vector(GBT_NUM-1 downto 0);
-
-        -- FIFO_RD_CLK              : in std_logic_vector(GBT_NUM-1 downto 0);
-        -- FIFO_RD_EN               : in std_logic_vector(GBT_NUM-1 downto 0);
-        -- FIFO_FULL                : out std_logic_vector(GBT_NUM-1 downto 0);
-        -- FIFO_EMPTY               : out std_logic_vector(GBT_NUM-1 downto 0);
-
-        --MT externalizing gtrx/txusrclk for FELIG logic
         GT_TXUSRCLK_OUT             : out std_logic_vector(GBT_NUM-1 downto 0);
         GT_RXUSRCLK_OUT             : out std_logic_vector(GBT_NUM-1 downto 0);
-        --
-        -- GTH Data pins
         TX_P                        : out std_logic_vector(GBT_NUM-1 downto 0);
         TX_N                        : out std_logic_vector(GBT_NUM-1 downto 0);
-        RX_P                        : in  std_logic_vector(GBT_NUM-1 downto 0);
-        RX_N                        : in  std_logic_vector(GBT_NUM-1 downto 0);
-        -- LMK03200 clock input pins added --MT/SS
-        CLK40_FPGA2LMK_out_P        : out std_logic;
-        CLK40_FPGA2LMK_out_N        : out std_logic;
-        --
-        --    clk_adn_160                 : in  std_logic; --added and then commented
-        --    since is unused MT/SS
-        LMK_LD                      : in  std_logic; -- added MT/SS LMK lock signal
-        RESET_TO_LMK                : out  std_logic --added MT/SS
-
+        RX_P                        : in std_logic_vector(GBT_NUM-1 downto 0);
+        RX_N                        : in std_logic_vector(GBT_NUM-1 downto 0);
+        RX_FLAG_O                   : out std_logic_vector(GBT_NUM-1 downto 0);
+        TX_FLAG_O                   : out std_logic_vector(GBT_NUM-1 downto 0);
+        LMK_LD                      : in std_logic;
+        GT_RXCLK40                  : out std_logic;
+        alignment_done_to_LMK       : out std_logic;
+        RxCdrLock_to_LMK            : out std_logic
     );
 end FELIX_gbt_wrapper_FELIGKCU;
 
 architecture Behavioral of FELIX_gbt_wrapper_FELIGKCU is
+    signal RxSlide_Manual           : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal RxSlide_c                : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal RxSlide_i                : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal RxSlide_Sel              : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal TXUSRRDY                 : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal RXUSRRDY                 : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal GTTX_RESET               : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal GTTX_RESET_MERGE         : std_logic_vector(GBT_NUM/4-1 downto 0) := (others=>'0');
+    signal GTRX_RESET               : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal GTRX_RESET_MERGE         : std_logic_vector(GBT_NUM/4-1 downto 0) := (others=>'0');
+    signal SOFT_RESET               : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal SOFT_RESET_f             : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal CPLL_RESET               : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal QPLL_RESET               : std_logic_vector(GBT_NUM/4-1 downto 0) := (others=>'0');
+    signal txresetdone              : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'1');
+    signal txresetdone_clk40        : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'1');
+    signal rxresetdone              : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'1');
+    signal rxresetdone_clk40        : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'1');
+    signal cplllock                 : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal qplllock                 : std_logic_vector(GBT_NUM/4-1 downto 0) := (others=>'0');
+    signal qplllock_inv             : std_logic_vector(GBT_NUM/4-1 downto 0) := (others=>'0');
+    signal rxcdrlock                : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'1');
+    signal rxcdrlock_int            : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'1');
+    signal rxcdrlock_a              : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal rxcdrlock_quad           : std_logic_vector(GBT_NUM/4-1 downto 0) := (others=>'0');
+    signal rxcdrlock_out            : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal cdr_cnt                  : std_logic_vector(19 downto 0) := (others=>'0');
+    signal TX_RESET                 : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal TX_RESET_i               : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal RX_RESET                 : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal RX_RESET_i               : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal GT_TXUSRCLK              : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal GT_RXUSRCLK              : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal RX_FLAG_Oi               : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal outsel_i                 : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal outsel_ii                : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal outsel_o                 : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal RX_120b_out_i            : txrx120b_type(0 to (GBT_NUM-1));
+    signal RX_IS_HEADER             : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal RX_HEADER_FOUND          : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal alignment_done           : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal alignment_done_f         : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal alignment_done_a         : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal alignment_done_chk_cnt   : std_logic_vector(12 downto 0) := (others=>'0');
+    signal alignment_chk_rst_c      : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal alignment_chk_rst_c1     : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal alignment_chk_rst        : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal alignment_chk_rst_f      : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal alignment_chk_rst_i      : std_logic := '0';
+    signal RxSlide                  : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal GT_TX_WORD_CLK           : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal GT_RX_WORD_CLK           : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal TX_TC_METHOD             : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal TC_EDGE                  : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    type data20barray               is array (0 to GBT_NUM-1) of std_logic_vector(19 downto 0);
+    signal TX_DATA_20b              : data20barray := (others => (others => '0'));
+    signal RX_DATA_20b              : data20barray := (others => (others => '0'));
+    signal DESMUX_USE_SW            : std_logic := '0';
+    signal DATA_TXFORMAT            : std_logic_vector(95 downto 0) := (others=>'0');
+    signal DATA_TXFORMAT_i          : std_logic_vector(95 downto 0) := (others=>'0');
+    signal DATA_RXFORMAT            : std_logic_vector(95 downto 0) := (others=>'0');
+    signal DATA_RXFORMAT_i          : std_logic_vector(95 downto 0) := (others=>'0');
+    signal General_ctrl             : std_logic_vector(63 downto 0) := (others=>'0');
+    SIGNAL GBT_TXRESET_DONE         : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    SIGNAL GBT_RXRESET_DONE         : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal txpmaresetdone           : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal rxpmaresetdone           : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal userclk_rx_reset_in      : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal userclk_tx_reset_in      : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal Channel_disable          : std_logic_vector(63 downto 0) := (others=>'0');
+    signal TX_TC_DLY_VALUE          : std_logic_vector(191 downto 0) := (others=>'0');
+    signal GTH_RefClk               : std_logic_vector(47 downto 0) := (others=>'0');
+    signal GTH_RefClk_LMK           : std_logic_vector(23 downto 0) := (others=>'0');
+    signal pulse_cnt                : std_logic_vector(29 downto 0) := (others=>'0');
+    signal pulse_lg                 : std_logic := '0';
+    signal CXP1_GTH_RefClk          : std_logic := '0';
+    signal CXP2_GTH_RefClk          : std_logic := '0';
+    signal CXP4_GTH_RefClk          : std_logic := '0';
+    signal CXP3_GTH_RefClk          : std_logic := '0';
+    signal CXP5_GTH_RefClk          : std_logic := '0';
+    signal CXP1_GTH_RefClk_LMK      : std_logic := '0';
+    signal CXP2_GTH_RefClk_LMK      : std_logic := '0';
+    signal error_orig               : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal error_f                  : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal FSM_RST                  : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal auto_gth_rxrst           : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal auto_gbt_rxrst           : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal GT_RXOUTCLK              : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal GT_TXOUTCLK              : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal BITSLIP_MANUAL_r         : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal BITSLIP_MANUAL_2r        : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    signal BITSLIP_MANUAL_3r        : std_logic_vector(GBT_NUM-1 downto 0) := (others=>'0');
+    type txrx80b_type               is array (GBT_NUM/4-1 downto 0) of std_logic_vector(79 downto 0);
+    signal RX_DATA_80b              : txrx80b_type;
+    signal TX_DATA_80b              : txrx80b_type;
+    signal RX_N_i                   : std_logic_vector(GBT_NUM-1 downto 0):= (others => '0');
+    signal RX_P_i                   : std_logic_vector(GBT_NUM-1 downto 0):= (others => '0');
+    signal TX_N_i                   : std_logic_vector(GBT_NUM-1 downto 0):= (others => '0');
+    signal TX_P_i                   : std_logic_vector(GBT_NUM-1 downto 0):= (others => '0');
+    signal drpclk_in                : std_logic_vector(0 downto 0) := (others=>'0');
+    signal GT_RXUSRCLK_40MHz        : std_logic;
+    signal QPLL_RESET_LMK           : std_logic_vector(GBT_NUM/4-1 downto 0) := (others=>'0');
+    signal QPLL_PIPE                : std_logic_vector(3 downto 0) := (others=>'0');
+    signal TXPOLARITY               : std_logic_vector(GBT_NUM-1 downto 0);
+    signal RXPOLARITY               : std_logic_vector(GBT_NUM-1 downto 0);
+begin
 
+    GT_TXUSRCLK_OUT             <= GT_TXUSRCLK(GBT_NUM-1 downto 0);
+    GT_RXUSRCLK_OUT             <= GT_RXUSRCLK(GBT_NUM-1 downto 0);
+    FRAME_LOCKED_O              <= alignment_done_f(GBT_NUM-1 downto 0);
+    GT_RXCLK40                  <= GT_RXUSRCLK_40MHz;
+    alignment_done_to_LMK       <= alignment_done_f(0);
+    RxCdrLock_to_LMK            <= rxcdrlock(0);
 
+    --Reference_Clk_Gen
 
-    component fifo_GBT2CR IS
-        PORT (
-            wr_clk    : IN STD_LOGIC;
-            wr_rst    : IN STD_LOGIC;
-            rd_clk    : IN STD_LOGIC;
-            rd_rst    : IN STD_LOGIC;
-            din       : IN STD_LOGIC_VECTOR(119 DOWNTO 0);
-            wr_en     : IN STD_LOGIC;
-            rd_en     : IN STD_LOGIC;
-            dout      : OUT STD_LOGIC_VECTOR(119 DOWNTO 0);
-            full      : OUT STD_LOGIC;
-            empty     : OUT STD_LOGIC;
-            prog_empty : OUT STD_LOGIC
-        );
-    END component;
-
-    -- constant QUAD_NUM : integer := GBT_NUM / 4;
-
-    signal rxslide_manual : STD_LOGIC_VECTOR(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal RxSlide_c      : STD_LOGIC_VECTOR(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal RxSlide_i      : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal rxslide_sel    : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal txusrrdy       : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal rxusrrdy       : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal gttx_reset     : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-
-    signal gtrx_reset     : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal soft_reset     : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal cpll_reset     : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal qpll_reset     : std_logic_vector(11 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal txresetdone    : std_logic_vector(47 downto 0) := (others=>'1'); --MT SIMU+ defaults
-
-    signal clk_sampled    : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-
-    signal rxresetdone    : std_logic_vector(47 downto 0) := (others=>'1'); --MT SIMU+ defaults
-    signal cpllfbclklost  : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal cplllock       : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal rxcdrlock      : std_logic_vector(47 downto 0) := (others=>'1'); --MT SIMU+ defaults
-    signal RxCdrLock_int  : std_logic_vector(47 downto 0) := (others=>'1'); --MT SIMU+ defaults
-    signal qplllock       : std_logic_vector(11 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal cdr_cnt        : std_logic_vector(19 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-
-    signal TX_RESET       : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal TX_RESET_i     : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-
-    signal RX_RESET       : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal RX_RESET_i     : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal GT_TXUSRCLK    : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal GT_RXUSRCLK    : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal RX_FLAG_Oi     : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-
-    signal RX_ALIGN_SW    : std_logic                     := '0'; --MT SIMU+ added defaults;
-    signal RX_ALIGN_TB_SW : std_logic                     := '0'; --MT SIMU+ added defaults;
-
-    signal outsel_i       : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal outsel_ii      : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal outsel_o       : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal RX_120b_out_i  : txrx120b_type(0 to (GBT_NUM-1));
-    signal RX_120b_out_ii : txrx120b_type(0 to (GBT_NUM-1));
-
-    signal rx_is_header   : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal alignment_done : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal rx_is_data     : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal RX_HEADER_FOUND: std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-
-    --  signal RxSlide_tmp    : std_logic_vector(47 downto 0);
-    signal RxSlide        : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-
-    signal GT_TX_WORD_CLK : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal TX_TC_METHOD   : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal TC_EDGE        : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-
-    type data20barray     is array (0 to 47) of std_logic_vector(19 downto 0);
-    signal TX_DATA_20b    : data20barray := (others => ("00000000000000000000"));
-    signal RX_DATA_20b    : data20barray := (others => ("00000000000000000000"));
-
-    signal GT_RX_WORD_CLK         : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal alignment_chk_rst_c    : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal alignment_chk_rst_c1   : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal alignment_chk_rst      : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal alignment_chk_rst_f    : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-
-    signal alignment_chk_rst_i    : std_logic := '0'; --MT SIMU+ added defaults;
-
-    signal DESMUX_USE_SW          : std_logic := '0'; --MT SIMU+ added defaults;
-
-    signal SOFT_TXRST_GT          : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal TopBot                 : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal TopBot_C               : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal SOFT_RXRST_GT          : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal SOFT_TXRST_ALL         : std_logic_vector(11 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal SOFT_RXRST_ALL         : std_logic_vector(11 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    SIGNAL DATA_TXFORMAT          : std_logic_vector(95 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal DATA_TXFORMAT_i        : std_logic_vector(95 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    SIGNAL DATA_RXFORMAT          : std_logic_vector(95 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal DATA_RXFORMAT_i        : std_logic_vector(95 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-
-    SIGNAL OddEven                : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-
-    signal General_ctrl           : std_logic_vector(63 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-
-    signal TXPMARESETDONE         : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal RXPMARESETDONE         : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal alignment_done_f       : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal soft_reset_f           : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal fifo_empty             : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal userclk_rx_reset_in    : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal userclk_tx_reset_in    : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal rxcdrlock_a            : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-
-    SIGNAL Channel_disable        : std_logic_vector(63 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    SIGNAL TX_TC_DLY_VALUE        : std_logic_vector(191 downto 0) := (others=>'0'); --MT SIMU+ added defaults);
-
-    signal GTH_RefClk             : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal GTH_RefClk_LMK         : std_logic_vector(23 downto 0) := (others=>'0'); --MT SIMU+ added defaults; --added MT/SS
-    signal pulse_cnt              : std_logic_vector(29 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal pulse_lg               : std_logic := '0'; --MT SIMU+;
-
-    signal CXP1_GTH_RefClk        : std_logic := '0'; --MT SIMU+ added defaults;
-    signal CXP2_GTH_RefClk        : std_logic := '0'; --MT SIMU+ added defaults;
-    signal CXP4_GTH_RefClk        : std_logic := '0'; --MT SIMU+ added defaults;
-    signal CXP3_GTH_RefClk        : std_logic := '0'; --MT SIMU+ added defaults;
-    signal CXP5_GTH_RefClk        : std_logic := '0'; --MT SIMU+ added defaults;
-    signal CXP1_GTH_RefClk_LMK    : std_logic := '0'; --MT SIMU+ added defaults; -- added MT/SS
-    signal CXP2_GTH_RefClk_LMK    : std_logic := '0'; --MT SIMU+ added defaults; -- added MT/SS
-
-    signal alignment_done_chk_cnt : std_logic_vector(12 downto 0) := (others=>'0'); --MT SIMU+ added defaults
-    signal alignment_done_a       : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults
-    signal fifo_rst               : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults
-    signal fifo_rden              : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults
-    signal error_orig             : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults
-    signal error_f                : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults
-    signal FSM_RST                : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults
-    signal auto_gth_rxrst         : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults
-    signal auto_gbt_rxrst         : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults
-    signal gtrx_reset_i           : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults
-
-    signal GT_RXOUTCLK            : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults
-    signal GT_TXOUTCLK            : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults
-
-    signal BITSLIP_MANUAL_r       : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults
-    signal BITSLIP_MANUAL_2r      : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults
-    signal BITSLIP_MANUAL_3r      : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults
-    type txrx80b_12ch_type        is array (11 downto 0) of std_logic_vector(79 downto 0);
-    signal RX_DATA_80b            : txrx80b_12ch_type;
-    signal TX_DATA_80b            : txrx80b_12ch_type;
-
-    signal gttx_reset_merge       : std_logic_vector(11 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal gtrx_reset_merge       : std_logic_vector(11 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal rxcdrlock_quad         : std_logic_vector(11 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal rxresetdone_quad       : std_logic_vector(11 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal txresetdone_quad       : std_logic_vector(11 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal rxcdrlock_out          : std_logic_vector(47 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-
-    signal RX_N_i                 : std_logic_vector(47 downto 0):=x"000000000000";
-    signal RX_P_i                 : std_logic_vector(47 downto 0):=x"000000000000";
-    signal TX_N_i                 : std_logic_vector(47 downto 0):=x"000000000000";
-    signal TX_P_i                 : std_logic_vector(47 downto 0):=x"000000000000";
-
-    signal drpclk_in              : std_logic_vector(0 downto 0) := (others=>'0'); --MT SIMU+ added defaults;
-    signal GT_RXUSRCLK_40MHz      : std_logic; -- added MT/SS
-    signal QPLL_RESET_LMK         : std_logic_vector(11 downto 0) := (others=>'0'); --MT SIMU+ added defaults; -- added MT/SS (others=>'0');
-    signal QpllLock_inv           : std_logic_vector(11 downto 0) := (others=>'0'); --MT SIMU+ added defaults; -- added MT/SS
-    signal alignment_done_inv     : std_logic := '0'; --MT SIMU+
-    signal QPLL_PIPE              : std_logic_vector(3 downto 0) := (others=>'0'); --MT SIMU+ added defaults; -- added MT/SS
-    signal LMK_PIPE               : std_logic_vector(3 downto 0) := (others=>'0'); --MT SIMU+ added defaults; -- added MT/SS
-    signal LMK_RESET              : std_logic := '0'; --MT SIMU+
-
---ila RL
---  signal ila_TX_120b_in         : txrx120b_type(0 to GBT_NUM-1);
---  signal ila_GT_TX_WORD_CLK     : std_logic_vector(47 downto 0);
---  signal ila_cplllock           : std_logic_vector(47 downto 0); --MT SIMU+ added defaults;
---  signal ila_qplllock           : std_logic_vector(11 downto 0);
-
---  COMPONENT  ila_link_frame IS
---    PORT (
---        clk : IN STD_LOGIC;
---        probe0 : IN STD_LOGIC_VECTOR(119 DOWNTO 0);
---        probe1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
---        probe2 : IN STD_LOGIC_VECTOR(11 DOWNTO 0));
---  END COMPONENT  ;
-begin
-
-    FRAME_LOCKED_O <= alignment_done_f(GBT_NUM-1 downto 0);
-    --MT SIMU+
     outclk_sim : if sim_emulator = true generate
         GT_RXOUTCLK <= (others => clk240_in);
         GT_TXOUTCLK <= (others => clk240_in);
     end generate;
 
     refclk_notsim : if sim_emulator = false generate
-        -- GTHREFCLK_1 : if GTHREFCLK_SEL = '0' generate
-        -- IBUFDS_GTE2
-        REFCLK_CXP1 <= CXP1_GTH_RefClk;
-        REFCLK_CXP2 <= CXP2_GTH_RefClk;
-
         --bank 126, 127, 128 use clk from bank 127
         ibufds_instq2_clk0 : IBUFDS_GTE3
-            port map
-    (
-                O               =>   CXP1_GTH_RefClk,
-                ODIV2           =>    open,
-                CEB             =>   '0',
-                I               =>   Q2_CLK0_GTREFCLK_PAD_P_IN,
-                IB              =>   Q2_CLK0_GTREFCLK_PAD_N_IN
+            port map(
+                O => CXP1_GTH_RefClk,
+                ODIV2 => open,
+                CEB => '0',
+                I => Q2_CLK0_GTREFCLK_PAD_P_IN,
+                IB => Q2_CLK0_GTREFCLK_PAD_N_IN
             );
 
         --bank 131, 132, 133 use clk from bank 132
         ibufds_instq8_clk0 : IBUFDS_GTE3
             port map
     (
-                O               =>     CXP2_GTH_RefClk,
-                ODIV2           =>    open,
-                CEB             =>     '0',
-                I               =>     Q8_CLK0_GTREFCLK_PAD_P_IN,
-                IB              =>     Q8_CLK0_GTREFCLK_PAD_N_IN
+                O => CXP2_GTH_RefClk,
+                ODIV2 => open,
+                CEB => '0',
+                I => Q8_CLK0_GTREFCLK_PAD_P_IN,
+                IB => Q8_CLK0_GTREFCLK_PAD_N_IN
             );
 
         --bank 231, 232, 233,use clk from bank 232
         ibufds_instq4_clk0 : IBUFDS_GTE3
-            port map
-    (
-                O               =>     CXP3_GTH_RefClk,
-                ODIV2           =>    open,
-                CEB             =>     '0',
-                I               =>     Q4_CLK0_GTREFCLK_PAD_P_IN,
-                IB              =>     Q4_CLK0_GTREFCLK_PAD_N_IN
+            port map(
+                O => CXP3_GTH_RefClk,
+                ODIV2 => open,
+                CEB => '0',
+                I => Q4_CLK0_GTREFCLK_PAD_P_IN,
+                IB => Q4_CLK0_GTREFCLK_PAD_N_IN
             );
 
         --bank 228 use clk from bank 228
         ibufds_instq5_clk0 : IBUFDS_GTE3
-            port map
-    (
-                O               =>     CXP4_GTH_RefClk,
-                ODIV2           =>    open,
-                CEB             =>     '0',
-                I               =>     Q5_CLK0_GTREFCLK_PAD_P_IN,
-                IB              =>     Q5_CLK0_GTREFCLK_PAD_N_IN
+            port map(
+                O => CXP4_GTH_RefClk,
+                ODIV2 => open,
+                CEB => '0',
+                I => Q5_CLK0_GTREFCLK_PAD_P_IN,
+                IB => Q5_CLK0_GTREFCLK_PAD_N_IN
             );
 
         --bank 224, 225 use clk from bank 225
         CXP5: if (CARD_TYPE = 712) generate
             ibufds_instq6_clk0 : IBUFDS_GTE3
-                port map
-      (
-                    O               =>     CXP5_GTH_RefClk,
-                    ODIV2           =>    open,
-                    CEB             =>     '0',
-                    I               =>     Q6_CLK0_GTREFCLK_PAD_P_IN,
-                    IB              =>     Q6_CLK0_GTREFCLK_PAD_N_IN
+                port map(
+                    O => CXP5_GTH_RefClk,
+                    ODIV2 => open,
+                    CEB => '0',
+                    I => Q6_CLK0_GTREFCLK_PAD_P_IN,
+                    IB => Q6_CLK0_GTREFCLK_PAD_N_IN
                 );
         end generate CXP5;
     end generate; --refclk_notsim
 
-
-    --================================================================-----
-    ----- Jitter cleaner LMK03200 GTH REF clks------------------------------
-    --================================================================------
     refclk_notsim2 : if sim_emulator = false generate
         -- GTHREFCLK_1 : if GTHREFCLK_SEL = '0' generate -- Jitter cleaner LMK03200
         -- IBUFDS_GTE2
-        REFCLK_CXP1_LMK <= CXP1_GTH_RefClk_LMK;  -- Jitter cleaner LMK03200
-        REFCLK_CXP2_LMK <= CXP2_GTH_RefClk_LMK;  -- Jitter cleaner LMK03200
-
         --bank 126, 127, 128 use clk from bank 127 -- Jitter cleaner LMK03200
         ibufds_LMK1 : IBUFDS_GTE3
-            port map
-    (
-                O               =>   CXP1_GTH_RefClk_LMK,
-                ODIV2           =>    open,
-                CEB             =>   '0',
-                I               =>   LMK_GTH_REFCLK1_P,
-                IB              =>   LMK_GTH_REFCLK1_N
+            port map(
+                O => CXP1_GTH_RefClk_LMK,
+                ODIV2 => open,
+                CEB => '0',
+                I => LMK_GTH_REFCLK1_P,
+                IB => LMK_GTH_REFCLK1_N
             );
 
         --bank 131, 132, 133 use clk from bank 132 -- Jitter cleaner LMK03200
         ibufds_LMK2 : IBUFDS_GTE3
-            port map
-    (
-                O               =>     CXP2_GTH_RefClk_LMK,
-                ODIV2           =>    open,
-                CEB             =>     '0',
-                I               =>     LMK_GTH_REFCLK3_P,
-                IB              =>     LMK_GTH_REFCLK3_N
+            port map(
+                O => CXP2_GTH_RefClk_LMK,
+                ODIV2 => open,
+                CEB => '0',
+                I => LMK_GTH_REFCLK3_P,
+                IB => LMK_GTH_REFCLK3_N
             );
         --================================================================-----
         ----- End Jitter cleaner LMK03200 GTH REF clks-------------------------
@@ -601,258 +472,65 @@ begin
         end generate g_refclk_24ch_LMK;
     end generate; -- refclk_notsim2;
 
-    --IG  GTH_RefClk(0)         <= CXP1_GTH_RefClk;
-    --IG  GTH_RefClk(1)         <= CXP1_GTH_RefClk;
-    --IG  GTH_RefClk(2)         <= CXP1_GTH_RefClk;
-    --IG  GTH_RefClk(3)         <= CXP1_GTH_RefClk;
-    --IG  GTH_RefClk(4)         <= CXP1_GTH_RefClk;
-    --IG  GTH_RefClk(5)         <= CXP1_GTH_RefClk;
-    --IG  GTH_RefClk(6)         <= CXP1_GTH_RefClk;
-    --IG  GTH_RefClk(7)         <= CXP1_GTH_RefClk;
-    --IG
-    --IG    -- For 16 channels (and below) put 8 channels in SRL0, channel 8..15 in SRL1.
-    --IG  g_refclk0: if GBT_NUM <= 16 generate
-    --IG    GTH_RefClk(8)       <= CXP2_GTH_RefClk;
-    --IG    GTH_RefClk(9)       <= CXP2_GTH_RefClk;
-    --IG    GTH_RefClk(10)      <= CXP2_GTH_RefClk;
-    --IG    GTH_RefClk(11)      <= CXP2_GTH_RefClk;
-    --IG  end generate;
-    --IG
-    --IG  -- For 24 channels put 12 channels in SRL0, channel 12..23 in SRL1.
-    --IG  g_refclk1: if GBT_NUM > 16 generate
-    --IG    GTH_RefClk(8)       <= CXP1_GTH_RefClk;
-    --IG    GTH_RefClk(9)       <= CXP1_GTH_RefClk;
-    --IG    GTH_RefClk(10)      <= CXP1_GTH_RefClk;
-    --IG    GTH_RefClk(11)      <= CXP1_GTH_RefClk;
-    --IG  end generate;
-    --IG
-    --IG refclkgen_v2p0 : if CARD_TYPE=712 generate
-    --IG    g_refclk11: if GBT_NUM <25 generate
-    --IG   --IBUFDS_GTE2
-    --IG
-    --IG    GTH_RefClk(12)        <= CXP2_GTH_RefClk;
-    --IG    GTH_RefClk(13)        <= CXP2_GTH_RefClk;
-    --IG    GTH_RefClk(14)        <= CXP2_GTH_RefClk;
-    --IG    GTH_RefClk(15)        <= CXP2_GTH_RefClk;
-    --IG    GTH_RefClk(16)        <= CXP2_GTH_RefClk;
-    --IG    GTH_RefClk(17)        <= CXP2_GTH_RefClk;
-    --IG    GTH_RefClk(18)        <= CXP2_GTH_RefClk;
-    --IG    GTH_RefClk(19)        <= CXP2_GTH_RefClk;
-    --IG    GTH_RefClk(20)        <= CXP2_GTH_RefClk;
-    --IG    GTH_RefClk(21)        <= CXP2_GTH_RefClk;
-    --IG    GTH_RefClk(22)        <= CXP2_GTH_RefClk;
-    --IG    GTH_RefClk(23)        <= CXP2_GTH_RefClk;
-    --IG  end generate;
-    --IG  g_refclk12: if GBT_NUM >24 generate
-    --IG     GTH_RefClk(24)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(25)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(26)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(27)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(28)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(29)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(30)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(31)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(32)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(33)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(34)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(35)        <= CXP2_GTH_RefClk;
-    --IG
-    --IG      GTH_RefClk(36)        <= CXP3_GTH_RefClk;
-    --IG GTH_RefClk(37)        <= CXP3_GTH_RefClk;
-    --IG GTH_RefClk(38)        <= CXP3_GTH_RefClk;
-    --IG GTH_RefClk(39)        <= CXP3_GTH_RefClk;
-    --IG GTH_RefClk(40)        <= CXP3_GTH_RefClk;
-    --IG GTH_RefClk(41)        <= CXP3_GTH_RefClk;
-    --IG GTH_RefClk(42)        <= CXP3_GTH_RefClk;
-    --IG GTH_RefClk(43)        <= CXP3_GTH_RefClk;
-    --IG GTH_RefClk(44)        <= CXP3_GTH_RefClk;
-    --IG GTH_RefClk(45)        <= CXP3_GTH_RefClk;
-    --IG GTH_RefClk(46)        <= CXP3_GTH_RefClk;
-    --IG GTH_RefClk(47)        <= CXP3_GTH_RefClk;
-    --IG
-    --IG GTH_RefClk(12)        <= CXP4_GTH_RefClk;
-    --IG GTH_RefClk(13)        <= CXP4_GTH_RefClk;
-    --IG GTH_RefClk(14)        <= CXP4_GTH_RefClk;
-    --IG GTH_RefClk(15)        <= CXP4_GTH_RefClk;
-    --IG
-    --IG GTH_RefClk(16)        <= CXP5_GTH_RefClk;
-    --IG GTH_RefClk(17)        <= CXP5_GTH_RefClk;
-    --IG GTH_RefClk(18)        <= CXP5_GTH_RefClk;
-    --IG GTH_RefClk(19)        <= CXP5_GTH_RefClk;
-    --IG GTH_RefClk(20)        <= CXP5_GTH_RefClk;
-    --IG GTH_RefClk(21)        <= CXP5_GTH_RefClk;
-    --IG GTH_RefClk(22)        <= CXP5_GTH_RefClk;
-    --IG GTH_RefClk(23)        <= CXP5_GTH_RefClk;
-    --IG
-    --IG--bank 224, 225 use clk from bank 225
-    --IG    ibufds_instq6_clk0 : IBUFDS_GTE3
-    --IG  port map
-    --IG  (
-    --IG    O               =>     CXP5_GTH_RefClk,
-    --IG    ODIV2           =>    open,
-    --IG    CEB             =>     '0',
-    --IG    I               =>     Q6_CLK0_GTREFCLK_PAD_P_IN,
-    --IG    IB              =>     Q6_CLK0_GTREFCLK_PAD_N_IN
-    --IG    );
-    --IG
-    --IG end generate;
-    --IG
-    --IG end generate;
-    --IG
-    --IGrefclkgen_v1p5 : if CARD_TYPE=711 generate
-    --IG
-    --IG
-    --IG  GTH_RefClk(12)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(13)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(14)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(15)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(16)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(17)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(18)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(19)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(20)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(21)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(22)        <= CXP2_GTH_RefClk;
-    --IG  GTH_RefClk(23)        <= CXP2_GTH_RefClk;
-    --IG
-    --IG
-    --IG  GTH_RefClk(24)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(25)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(26)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(27)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(28)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(29)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(30)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(31)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(32)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(33)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(34)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(35)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(40)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(41)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(42)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(43)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(44)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(45)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(46)        <= CXP3_GTH_RefClk;
-    --IG  GTH_RefClk(47)        <= CXP3_GTH_RefClk;
-    --IG
-    --IG
-    --IG  GTH_RefClk(36)        <= CXP4_GTH_RefClk;
-    --IG  GTH_RefClk(37)        <= CXP4_GTH_RefClk;
-    --IG  GTH_RefClk(38)        <= CXP4_GTH_RefClk;
-    --IG  GTH_RefClk(39)        <= CXP4_GTH_RefClk;
-    --IG
-    --IG   end generate;
-
-    Channel_disable(47 downto 0)          <= register_map_control.GBT_CHANNEL_DISABLE;
-    General_ctrl                          <= register_map_control.GBT_GENERAL_CTRL;
-
-    RxSlide_Manual(47 downto 0)           <= register_map_control.GBT_RXSLIDE_MANUAL(47 downto 0);
-    RxSlide_Sel(47 downto 0)              <= register_map_control.GBT_RXSLIDE_SELECT(47 downto 0);
-    TXUSRRDY(47 downto 0)             <= register_map_control.GBT_TXUSRRDY(47 downto 0);
-    RXUSRRDY(47 downto 0)             <= register_map_control.GBT_RXUSRRDY(47 downto 0);
-    GTTX_RESET(47 downto 0)           <= register_map_control.GBT_GTTX_RESET(47 downto 0);
-    GTRX_RESET(47 downto 0)           <= register_map_control.GBT_GTRX_RESET(47 downto 0);
-    SOFT_RESET(47 downto 0)           <= register_map_control.GBT_SOFT_RESET(47 downto 0);
-    CPLL_RESET(47 downto 0)           <= register_map_control.GBT_PLL_RESET.CPLL_RESET(47 downto 0);
-    QPLL_RESET(11 downto 0)           <= register_map_control.GBT_PLL_RESET.QPLL_RESET(59 downto 48) or QPLL_RESET_LMK;
-
-    SOFT_TXRST_GT(47 downto 0)     <= register_map_control.GBT_SOFT_TX_RESET.RESET_GT;  -- Default: 0b000
-    SOFT_RXRST_GT(47 downto 0)     <= register_map_control.GBT_SOFT_RX_RESET.RESET_GT; -- Default: 0b000
-    SOFT_TXRST_ALL(11 downto 0)    <= register_map_control.GBT_SOFT_TX_RESET.RESET_ALL(59 downto 48);
-    SOFT_RXRST_ALL(11 downto 0)    <= register_map_control.GBT_SOFT_RX_RESET.RESET_ALL(59 downto 48);
-
-    OddEven(47 downto 0)              <= register_map_control.GBT_ODD_EVEN(47 downto 0);
-    TopBot(47 downto 0)               <= register_map_control.GBT_TOPBOT(47 downto 0);
-
-    TX_TC_DLY_VALUE(47 downto 0)  <= register_map_control.GBT_TX_TC_DLY_VALUE1;
-    TX_TC_DLY_VALUE(95 downto 48) <=register_map_control.GBT_TX_TC_DLY_VALUE2;
-    TX_TC_DLY_VALUE(143 downto 96)  <= register_map_control.GBT_TX_TC_DLY_VALUE3;
-    TX_TC_DLY_VALUE(191 downto 144) <= register_map_control.GBT_TX_TC_DLY_VALUE4;
-
-
-    -- TX_OPT(47 downto 0)           <= GBT_TX_OPT(47 DOWNTO 0);  --
-    -- RX_OPT(47 downto 0)           <= GBT_RX_OPT(47 DOWNTO 0);  --
-
-
-    -- GBT_TX_OPT(47 downto 0)               <= x"000000555555"; -- ! TODO:Register was removed in RM4.0 register_map_control.GBT_TX_OPT;
-    -- GBT_RX_OPT(47 downto 0)               <= x"000000555555"; -- ! TODO:Register was removed in RM4.0 register_map_control.GBT_RX_OPT;
-    DATA_TXFORMAT(47 downto 0)        <= register_map_control.GBT_DATA_TXFORMAT1(47 downto 0);
-    DATA_RXFORMAT(47 downto 0)        <= register_map_control.GBT_DATA_RXFORMAT1(47 downto 0);
-    DATA_TXFORMAT(95 downto 48)       <= register_map_control.GBT_DATA_TXFORMAT2(47 downto 0);
-    DATA_RXFORMAT(95 downto 48)       <= register_map_control.GBT_DATA_RXFORMAT2(47 downto 0);
-
-    TX_RESET(47 downto 0)             <= register_map_control.GBT_TX_RESET(47 downto 0);
-    RX_RESET(47 downto 0)             <= register_map_control.GBT_RX_RESET(47 downto 0);
-    TX_TC_METHOD(47 downto 0)         <= register_map_control.GBT_TX_TC_METHOD(47 downto 0);
-    TC_EDGE(47 downto 0)              <= register_map_control.GBT_TC_EDGE(47 downto 0);
-    outsel_i(47 downto 0)             <= register_map_control.GBT_OUTMUX_SEL(47 downto 0);
-
-    register_map_gbt_monitor.GBT_VERSION.DATE             <=  GBT_VERSION(63 downto 48);
-    register_map_gbt_monitor.GBT_VERSION.GBT_VERSION(35 downto 32)      <=  GBT_VERSION(23 downto 20);
-    register_map_gbt_monitor.GBT_VERSION.GTH_IP_VERSION(19 downto 16)   <=  GBT_VERSION(19 downto 16);
-    register_map_gbt_monitor.GBT_VERSION.RESERVED         <=  GBT_VERSION(15 downto 3);
-    register_map_gbt_monitor.GBT_VERSION.GTHREFCLK_SEL    <=  (others => GTHREFCLK_SEL);
-    register_map_gbt_monitor.GBT_VERSION.RX_CLK_SEL       <=  GBT_VERSION(1 downto 1);
-    register_map_gbt_monitor.GBT_VERSION.PLL_SEL          <=  GBT_VERSION(0 downto 0);
-    --
-
-    register_map_gbt_monitor.GBT_TXRESET_DONE(47 downto 0)        <= TxResetDone(47 downto 0);
-    register_map_gbt_monitor.GBT_RXRESET_DONE(47 downto 0)        <= RxResetDone(47 downto 0);
-    register_map_gbt_monitor.GBT_TXFSMRESET_DONE(47 downto 0)     <= txpmaresetdone(47 downto 0);
-    register_map_gbt_monitor.GBT_RXFSMRESET_DONE(47 downto 0)     <= rxpmaresetdone(47 downto 0);
-    register_map_gbt_monitor.GBT_CPLL_FBCLK_LOST(47 downto 0)     <= CpllFbClkLost (47 downto 0);
-    register_map_gbt_monitor.GBT_PLL_LOCK.CPLL_LOCK(47 downto 0)  <= CpllLock(47 downto 0);
-    register_map_gbt_monitor.GBT_PLL_LOCK.QPLL_LOCK(59 downto 48) <= QpllLock(11 downto 0);
-    register_map_gbt_monitor.GBT_RXCDR_LOCK(47 downto 0)          <= RxCdrLock(47 downto 0);
-    register_map_gbt_monitor.GBT_CLK_SAMPLED(47 downto 0)         <= clk_sampled(47 downto 0);
-
-    register_map_gbt_monitor.GBT_RX_IS_HEADER(47 downto 0)        <= RX_IS_HEADER(47 downto 0);
-    register_map_gbt_monitor.GBT_RX_IS_DATA(47 downto 0)          <= RX_IS_DATA(47 downto 0);
-    register_map_gbt_monitor.GBT_RX_HEADER_FOUND(47 downto 0)     <= RX_HEADER_FOUND(47 downto 0);
-
-    register_map_gbt_monitor.GBT_ALIGNMENT_DONE(47 downto 0)      <= alignment_done_f(47 downto 0);
-
-    --    register_map_monitor.register_map_link_monitor.GBT_ALIGNMENT_DONE(i)            <= lane_monitor(i).gbt.frame_locked        ;
-    --    register_map_monitor.register_map_link_monitor.GBT_RX_IS_HEADER(i)                <= lane_monitor(i).gbt.rx_is_header        ;
-    --    register_map_monitor.register_map_link_monitor.GBT_RX_HEADER_FOUND(i)              <= lane_monitor(i).gbt.rx_header_found      ;
-    --    register_map_monitor.register_map_link_monitor.GBT_ERROR(i)                    <= lane_monitor(i).gbt.error          ;
-    --    register_map_monitor.register_map_link_monitor.GBT_TXRESET_DONE(i)                <= lane_monitor(i).gth.txreset_done        ;
-    --    register_map_monitor.register_map_link_monitor.GBT_RXRESET_DONE(i)                <= lane_monitor(i).gth.rxreset_done        ;
-    --    register_map_monitor.register_map_link_monitor.GBT_TXFSMRESET_DONE(i)              <= lane_monitor(i).gth.txfsmreset_done      ;
-    --    register_map_monitor.register_map_link_monitor.GBT_RXFSMRESET_DONE(i)              <= lane_monitor(i).gth.rxfsmreset_done      ;
-
-    -- aligndone_gen : for i in 23 downto 0 generate
-    --   alignment_done_f(i) <=  RxCdrLock(i) and alignment_done(i);
-    -- end generate;
-
-    register_map_gbt_monitor.GBT_OUT_MUX_STATUS(47 downto 0)    <= outsel_o(47 downto 0);
-    register_map_gbt_monitor.GBT_ERROR(47 downto 0)             <= error_f(47 downto 0);
-
-    error_gen : for i in 47 downto 0 generate
+    --Registers mapping
+
+    Channel_disable(GBT_NUM-1 downto 0)     <= register_map_control.GBT_CHANNEL_DISABLE(GBT_NUM-1 downto 0);
+    General_ctrl                            <= register_map_control.GBT_GENERAL_CTRL;
+
+    RxSlide_Manual                          <= register_map_control.GBT_RXSLIDE_MANUAL(GBT_NUM-1 downto 0);
+    RxSlide_Sel                             <= register_map_control.GBT_RXSLIDE_SELECT(GBT_NUM-1 downto 0);
+    TXUSRRDY                                <= register_map_control.GBT_TXUSRRDY(GBT_NUM-1 downto 0);
+    RXUSRRDY                                <= register_map_control.GBT_RXUSRRDY(GBT_NUM-1 downto 0);
+    GTTX_RESET                              <= register_map_control.GBT_GTTX_RESET(GBT_NUM-1 downto 0);
+    GTRX_RESET                              <= register_map_control.GBT_GTRX_RESET(GBT_NUM-1 downto 0);
+    SOFT_RESET                              <= register_map_control.GBT_SOFT_RESET(GBT_NUM-1 downto 0);
+    CPLL_RESET                              <= register_map_control.GBT_PLL_RESET.CPLL_RESET(GBT_NUM-1 downto 0);
+    QPLL_RESET                              <= register_map_control.GBT_PLL_RESET.QPLL_RESET(GBT_NUM/4-1+48 downto 48) or QPLL_RESET_LMK;
+
+    TX_TC_DLY_VALUE(47 downto 0)            <= register_map_control.GBT_TX_TC_DLY_VALUE1;
+    TX_TC_DLY_VALUE(95 downto 48)           <=register_map_control.GBT_TX_TC_DLY_VALUE2;
+    TX_TC_DLY_VALUE(143 downto 96)          <= register_map_control.GBT_TX_TC_DLY_VALUE3;
+    TX_TC_DLY_VALUE(191 downto 144)         <= register_map_control.GBT_TX_TC_DLY_VALUE4;
+
+    DATA_TXFORMAT(47 downto 0)      <= register_map_control.GBT_DATA_TXFORMAT1(47 downto 0);
+    DATA_RXFORMAT(47 downto 0)      <= register_map_control.GBT_DATA_RXFORMAT1(47 downto 0);
+    DATA_TXFORMAT(95 downto 48)     <= register_map_control.GBT_DATA_TXFORMAT2(47 downto 0);
+    DATA_RXFORMAT(95 downto 48)     <= register_map_control.GBT_DATA_RXFORMAT2(47 downto 0);
+
+    TX_RESET                                <= register_map_control.GBT_TX_RESET(GBT_NUM-1 downto 0);
+    RX_RESET                                <= register_map_control.GBT_RX_RESET(GBT_NUM-1 downto 0);
+    TX_TC_METHOD                            <= register_map_control.GBT_TX_TC_METHOD(GBT_NUM-1 downto 0);
+    TC_EDGE                                 <= register_map_control.GBT_TC_EDGE(GBT_NUM-1 downto 0);
+    outsel_i                                <= register_map_control.GBT_OUTMUX_SEL(GBT_NUM-1 downto 0);
+    DESMUX_USE_SW                           <= register_map_control.GBT_MODE_CTRL.DESMUX_USE_SW(0);
+
+    alignment_chk_rst_i                     <= General_ctrl(0);
+
+    register_map_gbt_monitor.GBT_VERSION.DATE                                   <=  GBT_VERSION(63 downto 48);
+    register_map_gbt_monitor.GBT_VERSION.GBT_VERSION(35 downto 32)              <=  GBT_VERSION(23 downto 20);
+    register_map_gbt_monitor.GBT_VERSION.GTH_IP_VERSION(19 downto 16)           <=  GBT_VERSION(19 downto 16);
+    register_map_gbt_monitor.GBT_VERSION.RESERVED                               <=  GBT_VERSION(15 downto 3);
+    register_map_gbt_monitor.GBT_VERSION.GTHREFCLK_SEL                          <=  (others => GTHREFCLK_SEL);
+    register_map_gbt_monitor.GBT_VERSION.RX_CLK_SEL                             <=  GBT_VERSION(1 downto 1);
+    register_map_gbt_monitor.GBT_VERSION.PLL_SEL                                <=  GBT_VERSION(0 downto 0);
+    register_map_gbt_monitor.GBT_TXRESET_DONE(GBT_NUM-1 downto 0)               <= txresetdone_clk40;
+    register_map_gbt_monitor.GBT_RXRESET_DONE(GBT_NUM-1 downto 0)               <= rxresetdone_clk40;
+    register_map_gbt_monitor.GBT_TXFSMRESET_DONE(GBT_NUM-1 downto 0)            <= txpmaresetdone;
+    register_map_gbt_monitor.GBT_RXFSMRESET_DONE(GBT_NUM-1 downto 0)            <= rxpmaresetdone;
+    register_map_gbt_monitor.GBT_PLL_LOCK.CPLL_LOCK(GBT_NUM-1 downto 0)         <= cplllock;
+    register_map_gbt_monitor.GBT_PLL_LOCK.QPLL_LOCK(GBT_NUM/4-1+48 downto 48)   <= qplllock;
+    register_map_gbt_monitor.GBT_RXCDR_LOCK(GBT_NUM-1 downto 0)                 <= rxcdrlock;
+    register_map_gbt_monitor.GBT_RX_IS_HEADER(GBT_NUM-1 downto 0)               <= RX_IS_HEADER;
+    register_map_gbt_monitor.GBT_RX_HEADER_FOUND(GBT_NUM-1 downto 0)            <= RX_HEADER_FOUND;
+    register_map_gbt_monitor.GBT_ALIGNMENT_DONE(GBT_NUM-1 downto 0)             <= alignment_done_f;
+    register_map_gbt_monitor.GBT_OUT_MUX_STATUS(GBT_NUM-1 downto 0)             <= outsel_o;
+    register_map_gbt_monitor.GBT_ERROR(GBT_NUM-1 downto 0)                      <= error_f;
+
+    error_gen : for i in GBT_NUM-1 downto 0 generate
         error_f(i) <= error_orig(i) and alignment_done_f(i);
     end generate;
 
-    register_map_gbt_monitor.GBT_GBT_TOPBOT_C(47 downto 0)      <= TopBot_c(47 downto 0);
-
-
-    ----------------------------------------
-    ------ REGISTERS MAPPING
-    ----------------------------------------
-    alignment_chk_rst_i           <= General_ctrl(0);
-
-
-    DESMUX_USE_SW                 <= register_map_control.GBT_MODE_CTRL.DESMUX_USE_SW(0);
-    RX_ALIGN_SW                   <= register_map_control.GBT_MODE_CTRL.RX_ALIGN_SW(1);
-    RX_ALIGN_TB_SW                <= register_map_control.GBT_MODE_CTRL.RX_ALIGN_TB_SW(2);
-
-
-
-
-
-
-    -------
+    --GBT FE
 
     datamod_gen1 : if DYNAMIC_DATA_MODE_EN='1' generate
         DATA_TXFORMAT_i <= DATA_TXFORMAT;
@@ -884,56 +562,129 @@ begin
     end process;
 
     rxalign_auto : for i in GBT_NUM-1 downto 0 generate
-
-        --  process(clk40_in)
-        --  begin
-        --    if clk40_in'event and clk40_in='1' then
-        --      if pulse_lg = '1' then
-        --        gbt_sel(i) <= lock_lg(i);
-        --      end if;
-        --      if  pulse_lg = '1' then
-        --        lock_lg(i) <='1';
-        --      elsif alignment_done_f(i)='0' then
-        --        lock_lg(i) <='0';
-        --      end if;
-        --    end if;
-        --  end process;
-
+        signal TX_RESET40   : std_logic;
+        signal RxSlide_c_RX_WORD_CLOCK: std_logic;
+        signal rxcdrlock_RX_WORD_CLOCK: std_logic;
+        --signal rxresetdone_40: std_logic;
+        --signal alignment_done_40: std_logic;
+        signal alignment_done_f_RXCLK: std_logic;
+    begin
         process(clk40_in)
         begin
             if clk40_in'event and clk40_in='1' then
                 if alignment_done_chk_cnt="0000000000000" then
-                    alignment_done_a(i) <= RxCdrLock(i) and alignment_done(i);
+                    alignment_done_a(i) <= rxcdrlock(i) and alignment_done(i);
                 else
-                    alignment_done_a(i) <= RxCdrLock(i) and alignment_done(i) and alignment_done_a(i);
+                    alignment_done_a(i) <= rxcdrlock(i) and alignment_done(i) and alignment_done_a(i);
                 end if;
                 if alignment_done_chk_cnt="0000000000000" then
-                    alignment_done_f(i) <=  RxCdrLock(i) and alignment_done_a(i);
+                    alignment_done_f(i) <=  rxcdrlock(i) and alignment_done_a(i);
                 end if;
             end if;
         end process;
 
+        sync_alignment_done: xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 4,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 1
+            )
+            port map (
+                src_clk => clk40_in,
+                src_in => alignment_done_f(i),
+                dest_clk => GT_RX_WORD_CLK(i),
+                dest_out => alignment_done_f_RXCLK
+            );
 
-        RX_120b_out(i) <= RX_120b_out_ii(i) when alignment_done_f(i)='1'
+        RX_120b_out(i) <= RX_120b_out_i(i) when alignment_done_f_RXCLK='1' --in FELIG RX_120b stays in GT_RX_WORD_CLK
                             else (others =>'0');
 
+        --not needed since aligment_done is all in the 40MHz clk
+        --sync_alignment_done: xpm_cdc_single
+        --    generic map (
+        --        DEST_SYNC_FF => 2,
+        --        INIT_SYNC_FF => 0,
+        --        SIM_ASSERT_CHK => 0,
+        --        SRC_INPUT_REG => 0
+        --    )
+        --    port map (
+        --        src_clk => '0',
+        --        src_in => alignment_done(i),
+        --        dest_clk => clk40_in,
+        --        dest_out => alignment_done_40
+        --    );
+
+        xpm_cdc_rxresetdone : xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0
+            )
+            port map (
+                src_clk => '0',
+                src_in => rxresetdone(i),
+                dest_clk => clk40_in,
+                dest_out => rxresetdone_clk40(i)
+            );
+
+        xpm_cdc_TX_RESET : xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 4,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 1
+            )
+            port map (
+                src_clk => clk40_in,
+                src_in => TX_RESET40,
+                dest_clk => GT_TX_WORD_CLK(i),
+                dest_out => TX_RESET_i(i)
+            );
+
+        xpm_cdc_TXPOLARITY : xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0
+            )
+            port map (
+                src_clk => '0',
+                src_in => register_map_control.GBT_TXPOLARITY(i),
+                dest_clk => GT_TX_WORD_CLK(i),
+                dest_out => TXPOLARITY(i)
+            );
+
+        xpm_cdc_RXPOLARITY : xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0
+            )
+            port map (
+                src_clk => '0',
+                src_in => register_map_control.GBT_RXPOLARITY(i),
+                dest_clk => GT_RX_WORD_CLK(i),
+                dest_out => RXPOLARITY(i)
+            );
+
         auto_rxrst : entity work.FELIX_GBT_RX_AUTO_RST
-            port map
-      (
+            port map(
                 FSM_CLK                 => clk40_in,
                 pulse_lg                => pulse_lg,
-                GTHRXRESET_DONE         => RxResetDone(i),-- and RxFsmResetDone(i),
+                GTHRXRESET_DONE         => rxresetdone_clk40(i),
                 alignment_chk_rst       => alignment_chk_rst_c1(i),
-                GBT_LOCK                => alignment_done_f(i),--alignment_done(i),
+                GBT_LOCK                => alignment_done_f(i),
                 AUTO_GTH_RXRST          => auto_gth_rxrst(i),
-                ext_trig_realign        => open,--ext_trig_realign(i),
+                ext_trig_realign        => open,
                 AUTO_GBT_RXRST          => auto_gbt_rxrst(i)
             );
 
         rafsm : entity work.FELIX_GBT_RXSLIDE_FSM
-            port map
-      (
-                --ext_trig_realign        => ext_trig_realign(i),
+            port map(
                 FSM_RST                 => FSM_RST(i),
                 FSM_CLK                 => clk40_in,
                 GBT_LOCK                => alignment_done(i),
@@ -941,73 +692,182 @@ begin
                 alignment_chk_rst       => alignment_chk_rst_c(i)
             );
 
-        FSM_RST(i)          <= RX_RESET(i);-- or RX_ALIGN_SW;
-        -- GTRX_RESET_i(i)     <= --GTRX_RESET(i) when RX_ALIGN_SW='1' else
-        --                      (GTRX_RESET(i) or auto_gth_rxrst(i));
-        RX_RESET_i(i)       <= --RX_RESET(i) when RX_ALIGN_SW='1' else
-                               (RX_RESET(i) or auto_gbt_rxrst(i));
-        alignment_chk_rst(i)        <= --alignment_chk_rst_i when RX_ALIGN_SW='1' else
-                                       (alignment_chk_rst_i or alignment_chk_rst_c(i) or alignment_chk_rst_c1(i));
-        RxSlide_i(i)             <= RxSlide_c(i) and RxCdrLock(i);
-        TX_RESET_i(i)       <= TX_RESET(i) or (not TxResetDone(i));-- or (not TxFsmResetDone(i));
-    end generate;
+        FSM_RST(i)              <= RX_RESET(i);
+        RX_RESET_i(i)           <= (RX_RESET(i) or auto_gbt_rxrst(i));
+        alignment_chk_rst(i)    <= (alignment_chk_rst_i or alignment_chk_rst_c(i) or alignment_chk_rst_c1(i));
 
-    outsel_ii             <= outsel_o when DESMUX_USE_SW = '0' else
-                             outsel_i;
+        sync_RxSlide_c : xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0
+            )
+            port map (
+                src_clk => '0',
+                src_in => RxSlide_c(i),
+                dest_clk => GT_RX_WORD_CLK(i),
+                dest_out => RxSlide_c_RX_WORD_CLOCK
+            );
+        sync_cdrlock: xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0
+            )
+            port map (
+                src_clk => '0',
+                src_in => rxcdrlock(i),
+                dest_clk => GT_RX_WORD_CLK(i),
+                dest_out => rxcdrlock_RX_WORD_CLOCK
+            );
 
-    --  OddEven_i           <= OddEven_c when RX_ALIGN_SW ='0' else
-    --                      OddEven;
+        RxSlide_i(i)            <= RxSlide_c_RX_WORD_CLOCK and rxcdrlock_RX_WORD_CLOCK;--<= RxSlide_c(i) and rxcdrlock(i);
+        TX_RESET40              <= TX_RESET(i) or (not txresetdone_clk40(i));-- or (not TxFsmResetDone(i));
 
-    --  TopBot_i            <= TopBot_c when RX_ALIGN_SW='0' else --and RX_ALIGN_TB_SW='0'  else
-    --                      TopBot;
+    end generate;
 
-    --RxSlide_i             <= RxSlide_c;-- when RX_ALIGN_SW='0' else
-    --                     RxSlide_Manual;
+    outsel_ii             <= outsel_o when DESMUX_USE_SW = '0' else
+                             outsel_i;
 
     RX_FLAG_O             <= RX_FLAG_Oi(GBT_NUM-1 downto 0);
 
     gbtRxTx : for i in GBT_NUM-1 downto 0 generate
+        signal TXFORMAT : std_logic_vector(1 downto 0);
+        signal RXFORMAT : std_logic_vector(1 downto 0);
+        signal RX_RESET_i_GT_RX_WORD_CLK: std_logic;
+        signal TX_TC_DLY_VALUE_sync : std_logic_vector(2 downto 0);
+        signal TC_EDGE_sync: std_logic;
+        signal TX_RESET_sync: std_logic;
+        signal TX_TC_METHOD_sync: std_logic;
+    begin
         process(GT_RX_WORD_CLK(i))
         begin
             if GT_RX_WORD_CLK(i)'event and GT_RX_WORD_CLK(i)='1' then
                 BITSLIP_MANUAL_r(i)     <= RxSlide_i(i);
                 BITSLIP_MANUAL_2r(i)    <= BITSLIP_MANUAL_r(i);
                 BITSLIP_MANUAL_3r(i)    <= BITSLIP_MANUAL_2r(i);
-
                 RxSlide(i)              <= BITSLIP_MANUAL_r(i) and (not BITSLIP_MANUAL_2r(i));
-            --MT
-            --        RxSlide_tmp(i)              <= BITSLIP_MANUAL_r(i) and (not BITSLIP_MANUAL_2r(i));
             end if;
         end process;
 
-        --MT added ******to check wheter RxSlide_tmp is exactly what John had (ie: from
-        --gbtrxslide_fsm and then through bitspli manual)*****
-        --    RxSlide(i) <= RxSlide_tmp(i) when (RxSlide_Sel(i) = '0') else fc_rx_slide_in(i);
-        --
+        alignment_chk_rst_f(i)      <= alignment_chk_rst(i);-- or (not RxCdrLock(i));
 
+        xpm_DATA_TXFORMAT : xpm_cdc_array_single generic map(
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0,
+                WIDTH => 2
+            )
+            port map(
+                src_clk => '0',
+                src_in => DATA_TXFORMAT_i(2*i+1 downto 2*i),
+                dest_clk => GT_TX_WORD_CLK(i),
+                dest_out => TXFORMAT
+            );
 
-        alignment_chk_rst_f(i)      <= alignment_chk_rst(i);-- or (not RxCdrLock(i));
-        gbtTxRx_inst: entity work.gbtTxRx_FELIX
-            generic map
-      (
-                channel => i
+        xpm_DATA_RXFORMATl : xpm_cdc_array_single generic map(
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0,
+                WIDTH => 2
             )
-            port map
-      (
+            port map(
+                src_clk => '0',
+                src_in => DATA_RXFORMAT_i(2*i+1 downto 2*i),
+                dest_clk => GT_RX_WORD_CLK(i),
+                dest_out => RXFORMAT
+            );
+
+        sync_RX_RESET_i : xpm_cdc_sync_rst
+            generic map (
+                DEST_SYNC_FF => 2,
+                INIT => 1,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0
+            )
+            port map (
+                src_rst => RX_RESET_i(i),
+                dest_clk => GT_RX_WORD_CLK(i),
+                dest_rst => RX_RESET_i_GT_RX_WORD_CLK
+            );
+
+        sync_TX_TC_DLY_VALUE : xpm_cdc_array_single
+            generic map (
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0,
+                WIDTH => 3
+            )
+            port map (
+                src_clk => '0',
+                src_in => TX_TC_DLY_VALUE(4*i+2 downto 4*i),
+                dest_clk => GT_TXUSRCLK(i),
+                dest_out => TX_TC_DLY_VALUE_sync
+            );
+
+        sync_TC_EDGE : xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0
+            )
+            port map (
+                src_clk => '0',
+                src_in => TC_EDGE(i),
+                dest_clk => GT_TXUSRCLK(i),
+                dest_out => TC_EDGE_sync
+            );
+
+        sync_TX_TC_METHOD : xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0
+            )
+            port map (
+                src_clk => '0',
+                src_in => TX_TC_METHOD(i),
+                dest_clk => GT_TXUSRCLK(i),
+                dest_out => TX_TC_METHOD_sync
+            );
+
+        sync_TX_RESET : xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0
+            )
+            port map (
+                src_clk => '0',
+                src_in => TX_RESET_i(i),
+                dest_clk => GT_TXUSRCLK(i),
+                dest_out => TX_RESET_sync
+            );
+
+        gbtTxRx_inst: entity work.gbtTxRx_FELIX
+            generic map(
+                channel => i)
+            port map(
                 error_o                 => error_orig(i),
-                RX_FLAG                 => RX_FLAG_Oi(i),--RX_FLAG_O(i),
+                RX_FLAG                 => RX_FLAG_Oi(i),
                 TX_FLAG                 => TX_FLAG_O(i),
 
-                Tx_DATA_FORMAT          => DATA_TXFORMAT_i(2*i+1 downto 2*i),
-                Rx_DATA_FORMAT          => DATA_RXFORMAT_i(2*i+1 downto 2*i),
+                Tx_DATA_FORMAT          => TXFORMAT,
+                Rx_DATA_FORMAT          => RXFORMAT,
 
-                --Tx_latopt_tc            => '1',--TX_OPT(i),
-                --Tx_latopt_scr           => '1',--TX_OPT(24+i),
-                RX_LATOPT_DES           => '1',--RX_OPT(i),
+                RX_LATOPT_DES           => '1',
 
-                TX_TC_METHOD            => TX_TC_METHOD(i),
-                TC_EDGE                 => TC_EDGE(i),
-                TX_TC_DLY_VALUE    => TX_TC_DLY_VALUE(4*i+2 downto 4*i),
+                TX_TC_METHOD            => TX_TC_METHOD_sync,
+                TC_EDGE                 => TC_EDGE_sync,
+                TX_TC_DLY_VALUE         => TX_TC_DLY_VALUE_sync,
 
                 alignment_chk_rst       => alignment_chk_rst_f(i),
                 alignment_done_O        => alignment_done(i),
@@ -1015,78 +875,32 @@ begin
                 outsel_i                => outsel_ii(i),
                 outsel_o                => outsel_o(i),
 
-                --BITSLIP_MANUAL        => RxSlide_i(i),
-                --BITSLIP_SEL           => RxSlide_Sel(i),
-                --GT_RXSLIDE    => RxSlide(i),
-                --OddEven      => '0',--OddEven_i(i),
-                --TopBot                  => '0',--TopBot_i(i),
-                --data_sel                => data_sel(4*i+3 downto 4*i),
-
-                TX_RESET_I     => TX_RESET_i(i),
-                TX_FRAMECLK_I          => TX_FRAME_CLK_I(i),
-                TX_WORDCLK_I           => GT_TX_WORD_CLK(i),
-                --TX_ISDATA_SEL_I  => TX_IS_DATA(i),
+                TX_RESET_I              => TX_RESET_sync,
+                TX_FRAMECLK_I           => TX_FRAME_CLK_I(i),
+                TX_WORDCLK_I            => GT_TX_WORD_CLK(i),
                 TX_DATA_120b_I          => TX_120b_in(i),
-                TX_DATA_20b_O          => TX_DATA_20b(i),
+                TX_DATA_20b_O           => TX_DATA_20b(i),
 
-                RX_RESET_I      => RX_RESET_i(i),
-                RX_FRAME_CLK_O     => open,--RX_FRAME_CLK_O(i),
+                RX_RESET_I              => RX_RESET_i_GT_RX_WORD_CLK,
+                RX_FRAME_CLK_O          => open,--RX_FRAME_CLK_O(i),
                 RX_WORD_IS_HEADER_O     => RX_IS_HEADER(i),
-                RX_HEADER_FOUND          => RX_HEADER_FOUND(i),
-                --RX_ISDATA_FLAG_O        => RX_IS_DATA(i),
-                RX_DATA_20b_I      => RX_DATA_20b(i),
-                RX_DATA_120b_O      => RX_120b_out_i(i),
+                RX_HEADER_FOUND         => RX_HEADER_FOUND(i),
+                RX_DATA_20b_I           => RX_DATA_20b(i),
+                RX_DATA_120b_O          => RX_120b_out_i(i),
                 des_rxusrclk            => GT_RX_WORD_CLK(i),
-                RX_WORDCLK_I        => GT_RX_WORD_CLK(i)
-
+                RX_WORDCLK_I            => GT_RX_WORD_CLK(i)
             );
 
-        fifo_rst(i) <= rst_hw or (not alignment_done_f(i)) or RX_RESET_i(i) or General_ctrl(4);
-        fifo_rden(i) <= not fifo_empty(i);
-
-        fifo_inst: fifo_GBT2CR
-            PORT MAP(
-                rd_rst          => fifo_rst(i),--rst_hw,
-                wr_rst          => fifo_rst(i),--rst_hw,
-                wr_clk          => GT_RX_WORD_CLK(i),
-                rd_clk          => clk40_in,--FIFO_RD_CLK(i),
-                din             => RX_120b_out_i(i),
-                wr_en           => RX_FLAG_Oi(i),
-                rd_en           => fifo_rden(i),--not fifo_empty(i),--'1',--FIFO_RD_EN(i),
-                dout            => RX_120b_out_ii(i),
-                full            => open,
-                empty           => open,
-                prog_empty      => fifo_empty(i)--FIFO_EMPTY(i)
-            );
 
     end generate;
 
-    --  ila_TX_120b_in <= TX_120b_in;
-    --  ila_GT_TX_WORD_CLK <= GT_TX_WORD_CLK;
-    --  ila_cplllock <= cplllock; --48
-    --  ila_qplllock <= qplllock; --12
-
-    --  ila_gen : for i in 0 to 1 generate
-    --    ila_one_link : ila_link_frame
-    --      port map(
-    --        clk => ila_GT_TX_WORD_CLK(i),
-    --        probe0 => ila_TX_120b_in(i),
-    --        probe1 => ila_cplllock,
-    --        probe2 => ila_qplllock
-    --      );
-    --  end generate ila_gen;
-
-    -------------------------------
-    ------ GTH TOP WRAPPER
-    -------------------------------
-
     clk_generate : for i in GBT_NUM-1 downto 0 generate
 
         GTTXOUTCLK_BUFG: bufg_gt
             port map(
                 i       => GT_TXOUTCLK(i),
                 div     => "000",
-                clr     => '0',--userclk_tx_reset_in,--'0',
+                clr     => '0',
                 cemask  => '0',
                 clrmask => '0',
                 ce      => '1',
@@ -1099,32 +913,25 @@ begin
             port map(
                 i       => GT_RXOUTCLK(i),
                 div     => "000",
-                clr     => '0',--userclk_tx_reset_in,--'0',
+                clr     => '0',
                 cemask  => '0',
                 clrmask => '0',
                 ce      => '1',
                 o       => GT_RX_WORD_CLK(i) --changed MT/SS
             );
 
-        -- GT_RXUSRCLK(i) <=  clk240_in;
-
 
         GT_RXUSRCLK(i) <= GT_RX_WORD_CLK(i); -- changed MT/SS
-    --RXUSRCLK_OUT(i)   <= GT_RXUSRCLK(i);
-
     end generate;
 
-    --MT SIMU+
     rxcdrlock_sim : if sim_emulator = true generate
         rxcdrlock_gen : for i in GBT_NUM-1 downto 0 generate
-            RxCdrLock(i) <= '1'; --hard coding to 1 since MGT has been commented out
+            rxcdrlock(i) <= '1'; --hard coding to 1 since MGT has been commented out
         end generate;
-    end generate; --rxcdrlock_sim
-    --
+    end generate;
 
-    -- QPLL Reset Process----- added MT/SS
     qpllreset_notsim : if sim_emulator = false generate
-        QpllLock_inv <= not QpllLock;
+        qplllock_inv <= not qplllock;
 
         process(clk40_in)
         begin
@@ -1132,29 +939,12 @@ begin
                 QPLL_PIPE(3 downto 1) <= QPLL_PIPE(2 downto 0);
                 QPLL_PIPE(0) <= LMK_LD;
                 if ((QPLL_PIPE(3) = '0') AND (QPLL_PIPE(0) = '1')) then --rising edge
-                    QPLL_RESET_LMK  <= QpllLock_inv;
-                else
-                    QPLL_RESET_LMK  <=x"000";
-                end if;
-            end if;
-        end process;
-
-        --- LMK Reset Process----- added MT/SS
-        alignment_done_inv <= not alignment_done_f(0);
-
-        process(clk40_in)
-        begin
-            if (clk40_in'event and clk40_in='1') then  --rising_edge(clk40_in)
-                LMK_PIPE(3 downto 1) <= LMK_PIPE(2 downto 0);
-                LMK_PIPE(0) <= alignment_done_f(0);
-                if ((LMK_PIPE(3) = '0') AND (LMK_PIPE(0) = '1')) then --rising edge
-                    LMK_RESET  <= '1';
+                    QPLL_RESET_LMK  <= qplllock_inv;
                 else
-                    LMK_RESET  <= '0';
+                    QPLL_RESET_LMK  <= (others =>'0');
                 end if;
             end if;
         end process;
-        RESET_TO_LMK <= LMK_RESET; -- added MT/SS
     end generate; --qpllreset_notsim
 
     qpllgen_sim : if sim_emulator = true generate
@@ -1164,192 +954,114 @@ begin
     qpllgen_notsim : if sim_emulator = false generate
         drpclk_in(0) <= clk40_in;
 
-        QPLL_GEN: if PLL_SEL = QPLL generate
-
-            port_trans : for i in GBT_NUM-1 downto 0 generate
-                RX_N_i(i)   <= RX_N(i);
-                RX_P_i(i)   <= RX_P(i);
-                TX_N(i)     <= TX_N_i(i);
-                TX_P(i)     <= TX_P_i(i);
-
-            end generate;
-
-            GTH_inst : for i in (GBT_NUM-1)/4 downto 0 generate
-
-                RX_DATA_20b(4*i+0) <= RX_DATA_80b(i)(19 downto 0);
-                RX_DATA_20b(4*i+1) <= RX_DATA_80b(i)(39 downto 20);
-                RX_DATA_20b(4*i+2) <= RX_DATA_80b(i)(59 downto 40);
-                RX_DATA_20b(4*i+3) <= RX_DATA_80b(i)(79 downto 60);
-
-
-                TX_DATA_80b(i) <= TX_DATA_20b(4*i+3) & TX_DATA_20b(4*i+2) & TX_DATA_20b(4*i+1) & TX_DATA_20b(4*i+0);
-
-                --REFCLK_SEL : if (i > 0) generate
-
-                GTH_TOP_INST: entity work.GTH_QPLL_Wrapper_FELIG
-                    Port map(
-                        gthrxn_in                       => RX_N_i(4*i+3 downto 4*i),
-                        gthrxp_in                       => RX_P_i(4*i+3 downto 4*i),
-                        gthtxn_out                      => TX_N_i(4*i+3 downto 4*i),
-                        gthtxp_out                      => TX_P_i(4*i+3 downto 4*i),
-
-                        drpclk_in                       => drpclk_in,--(others=>clk40_in),
-                        gtrefclk0_in                    => GTH_RefClk(4*i downto 4*i), -- for RX REFCLK from Si
-                        gtrefclk1_in                    => GTH_RefClk_LMK(4*i downto 4*i), --added for TX MGTREFCLK from LMK--MT/SS
-                        gt_rxusrclk_in                  => GT_RX_WORD_CLK(4*i+3 downto 4*i),
-                        gt_rxoutclk_out                 => GT_RXOUTCLK(4*i+3 downto 4*i),
-                        gt_txusrclk_in                  => GT_TX_WORD_CLK(4*i+3 downto 4*i),
-                        gt_txoutclk_out                 => GT_TXOUTCLK(4*i+3 downto 4*i),
-
-                        userdata_tx_in                  =>  TX_DATA_80b(i),
-                        userdata_rx_out                 =>  RX_DATA_80b(i),
-                        rxpolarity_in                   => register_map_control.GBT_RXPOLARITY(4*i+3 downto 4*i),
-                        txpolarity_in                   => register_map_control.GBT_TXPOLARITY(4*i+3 downto 4*i),
-
-
-                        -- for loopback: default, both signal need to be all '0'
-                        -- read kcu gth manual for the details. NOTE: the TXBUFFER is disabled, so some type of loopbhack may be
-                        -- not supported.
-                        -- for loopback rxcdrhold needs to be set, a register needs to be added, check KCU GTH manual for details
-                        -- not tested yet
-                        loopback_in                     => register_map_control.GTH_LOOPBACK_CONTROL,
-                        rxcdrhold_in                    => '0',
-
-                        userclk_rx_reset_in             => userclk_rx_reset_in(i downto i),--(others=>(not rxpmaresetdone_out(i))),--locked,
-                        userclk_tx_reset_in             => userclk_tx_reset_in(i downto i),--(others=>(not txpmaresetdone_out(i))),--,--locked,
-
-                        -- reset_clk_freerun_in                    : in std_logic_vector(0 downto 0);
-                        reset_all_in                           => SOFT_RESET_f(i downto i),
-                        reset_tx_pll_and_datapath_in           => QPLL_RESET(i downto i),
-                        reset_tx_datapath_in                   => GTTX_RESET_MERGE(i downto i),
-                        reset_rx_pll_and_datapath_in           => CPLL_RESET(i downto i), -- changed MT/SS
-                        reset_rx_datapath_in                   => GTRX_RESET_MERGE(i downto i),
-
-                        qpll0lock_out                          => open,
-                        qpll1lock_out                          => QpllLock(i downto i),
-                        qpll1fbclklost_out                     => open,--
-                        qpll0fbclklost_out                     => open,
-                        rxslide_in                             => RxSlide(4*i+3 downto 4*i),
-
-                        cplllock_out                           => cplllock(4*i+3 downto 4*i), --RL
-
-                        rxresetdone_out                         => rxresetdone(4*i+3 downto 4*i),
-                        txresetdone_out                         => txresetdone(4*i+3 downto 4*i),
-                        rxpmaresetdone_out                      => rxpmaresetdone(4*i+3 downto 4*i),
-                        txpmaresetdone_out                      => txpmaresetdone(4*i+3 downto 4*i),
-                        reset_tx_done_out                       => txresetdone_quad(i downto i),
-                        reset_rx_done_out                       => rxresetdone_quad(i downto i),
-                        reset_rx_cdr_stable_out                 => RxCdrLock_quad(i downto i),
-                        rxcdrlock_out                           => rxcdrlock_out(4*i+3 downto 4*i)
-                    );
-                --end generate;
-
-                --this was done to test the firmware with fibers connected in loopback. In this case the quad 0 TX  gets recovered clock from Si and all other
-                --  quads TX get revovered clock from LMK.
-
-                --  REFCLK_SEL_1 : if (i = 0) generate
-                --    GTH_TOP_INST_1: entity work.GTH_QPLL_Wrapper_FELIG
-                --      Port map(
-                --        gthrxn_in                       => RX_N_i(4*i+3 downto 4*i),
-                --        gthrxp_in                       => RX_P_i(4*i+3 downto 4*i),
-                --        gthtxn_out                      => TX_N_i(4*i+3 downto 4*i),
-                --        gthtxp_out                      => TX_P_i(4*i+3 downto 4*i),
-
-                --        drpclk_in                       => drpclk_in,--(others=>clk40_in),
-                --        gtrefclk0_in                    => GTH_RefClk(4*i downto 4*i), -- for RX REFCLK from Si --MT/SS
-                --        gtrefclk1_in                    => GTH_RefClk(4*i downto 4*i), --added for TX MGTREFCLK from Si-MT/SS
-                --        gt_rxusrclk_in                  => GT_RX_WORD_CLK(4*i+3 downto 4*i),
-                --        gt_rxoutclk_out                 => GT_RXOUTCLK(4*i+3 downto 4*i),
-                --        gt_txusrclk_in                  => GT_TX_WORD_CLK(4*i+3 downto 4*i),
-                --        gt_txoutclk_out                 => GT_TXOUTCLK(4*i+3 downto 4*i),
-
-                --        userdata_tx_in                  =>  TX_DATA_80b(i),
-                --        userdata_rx_out                 =>  RX_DATA_80b(i),
-                --        rxpolarity_in                   => register_map_control.GBT_RXPOLARITY(4*i+3 downto 4*i),
-                --        txpolarity_in                   => register_map_control.GBT_TXPOLARITY(4*i+3 downto 4*i),
-
-
-                --        -- for loopback: default, both signal need to be all '0'
-                --        -- read kcu gth manual for the details. NOTE: the TXBUFFER is disabled, so some type of loopbhack may be
-                --        -- not supported.
-                --        -- for loopback rxcdrhold needs to be set, a register needs to be added, check KCU GTH manual for details
-                --        -- not tested yet
-                --        loopback_in                     => register_map_control.GTH_LOOPBACK_CONTROL,
-                --        rxcdrhold_in                    => '0',
-
-                --        userclk_rx_reset_in             => userclk_rx_reset_in(i downto i),--(others=>(not rxpmaresetdone_out(i))),--locked,
-                --        userclk_tx_reset_in             => userclk_tx_reset_in(i downto i),--(others=>(not txpmaresetdone_out(i))),--,--locked,
-
-                --        -- reset_clk_freerun_in                    : in std_logic_vector(0 downto 0);
-                --        reset_all_in                           => SOFT_RESET_f(i downto i),
-                --        reset_tx_pll_and_datapath_in           => QPLL_RESET(i downto i),
-                --        reset_tx_datapath_in                   => GTTX_RESET_MERGE(i downto i),
-                --        reset_rx_pll_and_datapath_in           => CPLL_RESET(i downto i),
-                --        reset_rx_datapath_in                   => GTRX_RESET_MERGE(i downto i),
-
-                --        qpll0lock_out                          => open,
-                --        qpll1lock_out                          => QpllLock(i downto i),
-                --        qpll1fbclklost_out                     => open,--
-                --        qpll0fbclklost_out                     => open,
-                --        rxslide_in                             => RxSlide(4*i+3 downto 4*i),
-
-                --        rxresetdone_out                         => rxresetdone(4*i+3 downto 4*i),
-                --        txresetdone_out                         => txresetdone(4*i+3 downto 4*i),
-                --        rxpmaresetdone_out                      => rxpmaresetdone(4*i+3 downto 4*i),
-                --        txpmaresetdone_out                      => txpmaresetdone(4*i+3 downto 4*i),
-                --        reset_tx_done_out                       => txresetdone_quad(i downto i),
-                --        reset_rx_done_out                       => rxresetdone_quad(i downto i),
-                --        reset_rx_cdr_stable_out                 => RxCdrLock_quad(i downto i),
-                --        rxcdrlock_out                           => rxcdrlock_out(4*i+3 downto 4*i)
-                --        );
-                --  end generate;
-
-
-                process(clk40_in)
-                begin
-                    if clk40_in'event and clk40_in='1' then
-                        if cdr_cnt ="00000000000000000000" then
-                            RxCdrLock_a(4*i)     <= rxcdrlock_out(4*i);
-                            RxCdrLock_a(4*i+1)   <= rxcdrlock_out(4*i+1);
-                            RxCdrLock_a(4*i+2)   <= rxcdrlock_out(4*i+2);
-                            RxCdrLock_a(4*i+3)   <= rxcdrlock_out(4*i+3);
-                        else
-                            RxCdrLock_a(4*i) <= RxCdrLock_a(4*i) and rxcdrlock_out(4*i);
-                            RxCdrLock_a(4*i+1) <= RxCdrLock_a(4*i+1) and rxcdrlock_out(4*i+1);
-                            RxCdrLock_a(4*i+2) <= RxCdrLock_a(4*i+2) and rxcdrlock_out(4*i+2);
-                            RxCdrLock_a(4*i+3) <= RxCdrLock_a(4*i+3) and rxcdrlock_out(4*i+3);
-                        end if;
-                        if cdr_cnt="00000000000000000000" then
-                            RxCdrLock_int(4*i) <=RxCdrLock_a(4*i);
-                            RxCdrLock_int(4*i+1) <=RxCdrLock_a(4*i+1);
-                            RxCdrLock_int(4*i+2) <=RxCdrLock_a(4*i+2);
-                            RxCdrLock_int(4*i+3) <=RxCdrLock_a(4*i+3);
-                        end if;
-                    end if;
-                end process;
-                RxCdrLock(4*i) <= (not Channel_disable(4*i)) and RxCdrLock_int(4*i);
-                RxCdrLock(4*i+1) <= (not Channel_disable(4*i+1)) and RxCdrLock_int(4*i+1);
-                RxCdrLock(4*i+2) <= (not Channel_disable(4*i+2)) and RxCdrLock_int(4*i+2);
-                RxCdrLock(4*i+3) <= (not Channel_disable(4*i+3)) and RxCdrLock_int(4*i+3);
+        port_trans : for i in GBT_NUM-1 downto 0 generate
+            RX_N_i(i)   <= RX_N(i);
+            RX_P_i(i)   <= RX_P(i);
+            TX_N(i)     <= TX_N_i(i);
+            TX_P(i)     <= TX_P_i(i);
 
-                SOFT_RESET_f(i) <= SOFT_RESET(i) or QPLL_RESET(i);--or rst_hw;-- or GTRX_RESET(i);
+        end generate;
+
+        GTH_inst : for i in (GBT_NUM-1)/4 downto 0 generate
+
+            RX_DATA_20b(4*i+0) <= RX_DATA_80b(i)(19 downto 0);
+            RX_DATA_20b(4*i+1) <= RX_DATA_80b(i)(39 downto 20);
+            RX_DATA_20b(4*i+2) <= RX_DATA_80b(i)(59 downto 40);
+            RX_DATA_20b(4*i+3) <= RX_DATA_80b(i)(79 downto 60);
+
+
+            TX_DATA_80b(i) <= TX_DATA_20b(4*i+3) & TX_DATA_20b(4*i+2) & TX_DATA_20b(4*i+1) & TX_DATA_20b(4*i+0);
+
+            GTH_TOP_INST: entity work.GTH_QPLL_Wrapper_FELIG
+                Port map(
+                    gthrxn_in                       => RX_N_i(4*i+3 downto 4*i),
+                    gthrxp_in                       => RX_P_i(4*i+3 downto 4*i),
+                    gthtxn_out                      => TX_N_i(4*i+3 downto 4*i),
+                    gthtxp_out                      => TX_P_i(4*i+3 downto 4*i),
+
+                    drpclk_in                       => drpclk_in,
+                    gtrefclk0_in                    => GTH_RefClk(4*i downto 4*i),
+                    gtrefclk1_in                    => GTH_RefClk_LMK(4*i downto 4*i),
+                    gt_rxusrclk_in                  => GT_RX_WORD_CLK(4*i+3 downto 4*i),
+                    gt_rxoutclk_out                 => GT_RXOUTCLK(4*i+3 downto 4*i),
+                    gt_txusrclk_in                  => GT_TX_WORD_CLK(4*i+3 downto 4*i),
+                    gt_txoutclk_out                 => GT_TXOUTCLK(4*i+3 downto 4*i),
+
+                    userdata_tx_in                  => TX_DATA_80b(i),
+                    userdata_rx_out                 => RX_DATA_80b(i),
+                    rxpolarity_in                   => RXPOLARITY(4*i+3 downto 4*i),
+                    txpolarity_in                   => TXPOLARITY(4*i+3 downto 4*i),
+
+                    loopback_in                     => register_map_control.GTH_LOOPBACK_CONTROL,
+                    rxcdrhold_in                    => '0',
+
+                    userclk_rx_reset_in             => userclk_rx_reset_in(i downto i),
+                    userclk_tx_reset_in             => userclk_tx_reset_in(i downto i),
+
+                    reset_all_in                    => SOFT_RESET_f(i downto i),
+                    reset_tx_pll_and_datapath_in    => QPLL_RESET(i downto i),
+                    reset_tx_datapath_in            => GTTX_RESET_MERGE(i downto i),
+                    reset_rx_pll_and_datapath_in    => CPLL_RESET(i downto i),
+                    reset_rx_datapath_in            => GTRX_RESET_MERGE(i downto i),
+
+                    qpll0lock_out                   => open,
+                    qpll1lock_out                   => qplllock(i downto i),
+                    qpll1fbclklost_out              => open,--
+                    qpll0fbclklost_out              => open,
+                    rxslide_in                      => RxSlide(4*i+3 downto 4*i),
+
+                    cplllock_out                    => cplllock(4*i+3 downto 4*i),
+
+                    rxresetdone_out                 => rxresetdone(4*i+3 downto 4*i),
+                    txresetdone_out                 => txresetdone(4*i+3 downto 4*i),
+                    rxpmaresetdone_out              => rxpmaresetdone(4*i+3 downto 4*i),
+                    txpmaresetdone_out              => txpmaresetdone(4*i+3 downto 4*i),
+                    reset_tx_done_out               => open,--txresetdone_quad(i downto i),
+                    reset_rx_done_out               => open,--rxresetdone_quad(i downto i),
+                    reset_rx_cdr_stable_out         => rxcdrlock_quad(i downto i),
+                    rxcdrlock_out                   => rxcdrlock_out(4*i+3 downto 4*i)
+                );
 
-                userclk_rx_reset_in(i) <=not (rxpmaresetdone(4*i+0) or rxpmaresetdone(4*i+1) or rxpmaresetdone(4*i+2) or rxpmaresetdone(4*i+3));
-                userclk_tx_reset_in(i) <=not (txpmaresetdone(4*i+0) or txpmaresetdone(4*i+1) or txpmaresetdone(4*i+2) or txpmaresetdone(4*i+3));
+            process(clk40_in)
+            begin
+                if clk40_in'event and clk40_in='1' then
+                    if cdr_cnt ="00000000000000000000" then
+                        rxcdrlock_a(4*i)     <= rxcdrlock_out(4*i);
+                        rxcdrlock_a(4*i+1)   <= rxcdrlock_out(4*i+1);
+                        rxcdrlock_a(4*i+2)   <= rxcdrlock_out(4*i+2);
+                        rxcdrlock_a(4*i+3)   <= rxcdrlock_out(4*i+3);
+                    else
+                        rxcdrlock_a(4*i) <= rxcdrlock_a(4*i) and rxcdrlock_out(4*i);
+                        rxcdrlock_a(4*i+1) <= rxcdrlock_a(4*i+1) and rxcdrlock_out(4*i+1);
+                        rxcdrlock_a(4*i+2) <= rxcdrlock_a(4*i+2) and rxcdrlock_out(4*i+2);
+                        rxcdrlock_a(4*i+3) <= rxcdrlock_a(4*i+3) and rxcdrlock_out(4*i+3);
+                    end if;
+                    if cdr_cnt="00000000000000000000" then
+                        rxcdrlock_int(4*i) <=rxcdrlock_a(4*i);
+                        rxcdrlock_int(4*i+1) <=rxcdrlock_a(4*i+1);
+                        rxcdrlock_int(4*i+2) <=rxcdrlock_a(4*i+2);
+                        rxcdrlock_int(4*i+3) <=rxcdrlock_a(4*i+3);
+                    end if;
+                end if;
+            end process;
+            rxcdrlock(4*i) <= (not Channel_disable(4*i)) and rxcdrlock_int(4*i);
+            rxcdrlock(4*i+1) <= (not Channel_disable(4*i+1)) and rxcdrlock_int(4*i+1);
+            rxcdrlock(4*i+2) <= (not Channel_disable(4*i+2)) and rxcdrlock_int(4*i+2);
+            rxcdrlock(4*i+3) <= (not Channel_disable(4*i+3)) and rxcdrlock_int(4*i+3);
 
-                GTTX_RESET_MERGE(i) <= GTTX_RESET(4*i) or GTTX_RESET(4*i+1) or GTTX_RESET(4*i+2) or GTTX_RESET(4*i+3);
-                GTRX_RESET_MERGE(i) <= (GTRX_RESET(4*i) or (auto_gth_rxrst(4*i) and RxCdrLock(4*i)))
-                                       or (GTRX_RESET(4*i+1) or (auto_gth_rxrst(4*i+1) and RxCdrLock(4*i+1)))
-                                       or (GTRX_RESET(4*i+2) or (auto_gth_rxrst(4*i+2) and RxCdrLock(4*i+2)))
-                                       or (GTRX_RESET(4*i+3) or (auto_gth_rxrst(4*i+3) and RxCdrLock(4*i+3))) ;
-            --GTRX_RESET_MERGE(i) <= GTRX_RESET(4*i) or GTRX_RESET(4*i+1) or GTRX_RESET(4*i+2) or GTRX_RESET(4*i+3);
+            SOFT_RESET_f(i) <= SOFT_RESET(i) or QPLL_RESET(i);--or rst_hw;-- or GTRX_RESET(i);
 
-            --CpllLock(i) <= '1';
+            userclk_rx_reset_in(i) <=not (rxpmaresetdone(4*i+0) or rxpmaresetdone(4*i+1) or rxpmaresetdone(4*i+2) or rxpmaresetdone(4*i+3));
+            userclk_tx_reset_in(i) <=not (txpmaresetdone(4*i+0) or txpmaresetdone(4*i+1) or txpmaresetdone(4*i+2) or txpmaresetdone(4*i+3));
 
-            end generate;--GTH_TOP_INST
+            GTTX_RESET_MERGE(i) <= GTTX_RESET(4*i) or GTTX_RESET(4*i+1) or GTTX_RESET(4*i+2) or GTTX_RESET(4*i+3);
+            GTRX_RESET_MERGE(i) <= (GTRX_RESET(4*i) or (auto_gth_rxrst(4*i) and rxcdrlock(4*i)))
+                                   or (GTRX_RESET(4*i+1) or (auto_gth_rxrst(4*i+1) and rxcdrlock(4*i+1)))
+                                   or (GTRX_RESET(4*i+2) or (auto_gth_rxrst(4*i+2) and rxcdrlock(4*i+2)))
+                                   or (GTRX_RESET(4*i+3) or (auto_gth_rxrst(4*i+3) and rxcdrlock(4*i+3))) ;
 
-        end generate; --QPLL_GEN
-    end generate; --qpllgen_notsim
+        end generate;
+    end generate;
 
     process(clk40_in)
     begin
@@ -1359,89 +1071,7 @@ begin
     end process;
 
 
-    cpllgen_notsim : if sim_emulator = false generate
-        CPLL_GEN: if  PLL_SEL = CPLL generate
-            GTH_inst : for i in GBT_NUM-1 downto 0 generate
-
-                GTH_TOP_INST: entity work.GTH_CPLL_Wrapper
-                    Port map(
-                        gthrxn_in                              => RX_N(i downto i),
-                        gthrxp_in                              => RX_P(i downto i),
-                        gthtxn_out                             => TX_N(i downto i),
-                        gthtxp_out                             => TX_P(i downto i),
-                        drpclk_in                              => drpclk_in,--(others=>clk40_in),
-                        gtrefclk0_in                           => GTH_RefClk(i downto i),
-
-                        gt0_rxusrclk_in                        => GT_RX_WORD_CLK(i downto i),
-                        gt0_rxoutclk_out                       => GT_RXOUTCLK(i downto i),
-                        gt0_txusrclk_in                        => GT_TX_WORD_CLK(i downto i),
-                        gt0_txoutclk_out                       => GT_TXOUTCLK(i downto i),
-
-                        userdata_tx_in                         =>  TX_DATA_20b(i),
-                        userdata_rx_out                        =>  RX_DATA_20b(i),
-                        rxpolarity_in                          => register_map_control.GBT_RXPOLARITY(i downto i),
-                        txpolarity_in                          => register_map_control.GBT_TXPOLARITY(i downto i),
-
-                        -- for loopback: default, both signal need to be all '0'
-                        -- read kcu gth manual for the details. NOTE: the TXBUFFER is disabled, so some type of loopbhack may be
-                        -- not supported.
-                        -- for loopback rxcdrhold needs to be set, a register needs to be added, check KCU GTH manual for details
-                        -- not tested yet
-                        loopback_in                            => register_map_control.GTH_LOOPBACK_CONTROL,
-                        rxcdrhold_in                           => '0',
-
-
-                        userclk_rx_reset_in                    => userclk_rx_reset_in(i downto i),--(others=>(not rxpmaresetdone_out(i))),--locked,
-                        userclk_tx_reset_in                    => userclk_tx_reset_in(i downto i),--(others=>(not txpmaresetdone_out(i))),--,--locked,
-
-                        -- reset_clk_freerun_in                    : in std_logic_vector(0 downto 0);
-                        reset_all_in                           => SOFT_RESET_f(i downto i),
-                        reset_tx_pll_and_datapath_in           => CPLL_RESET(i downto i),
-                        reset_tx_datapath_in                   => GTTX_RESET(i downto i),
-                        reset_rx_pll_and_datapath_in           => CPLL_RESET(i downto i),
-                        reset_rx_datapath_in                   => GTRX_RESET_i(i downto i),-- and RxCdrLock(i downto i),
-
-
-                        cpllfbclklost_out                      => cpllfbclklost(i downto i),
-                        cplllock_out                           => cplllock(i downto i),
-
-
-                        rxslide_in                             => RxSlide(i downto i),
-
-
-
-                        rxpmaresetdone_out                     => rxpmaresetdone(i downto i),
-                        txpmaresetdone_out                     => txpmaresetdone(i downto i),
-
-                        reset_tx_done_out                      => txresetdone(i downto i),
-                        reset_rx_done_out                      => rxresetdone(i downto i),
-                        reset_rx_cdr_stable_out                => RxCdrLock_int(i downto i)
-
-                    );
-
-
-                RxCdrLock(i) <= (not Channel_disable(i)) and RxCdrLock_int(i);
-                GTRX_RESET_i(i) <= --GTRX_RESET(i) when RX_ALIGN_SW='1' else
-                                   GTRX_RESET(i) or (auto_gth_rxrst(i) and RxCdrLock(i));
-
-                SOFT_RESET_f(i) <= SOFT_RESET(i/4) or CPLL_RESET(i);--or rst_hw; -- or GTRX_RESET(i);
-
-                userclk_rx_reset_in(i) <=not rxpmaresetdone(i);
-                userclk_tx_reset_in(i) <=not txpmaresetdone(i);
-            --RxResetDone_f(i) <= RxResetDone(i);
-
-            end generate; --GTH_TOP_INST
-        end generate; --CPLL_GEN
-    end generate; --cpllgen_notsim
-
-    --MT externalizing gtrx/txusrclk for FELIG logic
-    GT_TXUSRCLK_OUT <= GT_TXUSRCLK(GBT_NUM-1 downto 0);
-    GT_RXUSRCLK_OUT <= GT_RXUSRCLK(GBT_NUM-1 downto 0);
-    --
-
-
     bufgceobuf_notsim : if sim_emulator = false generate
-        -- BUFGCE_DIV instantiation: added MT/SS
         BUFGCE_DIV_inst : BUFGCE_DIV
             generic map (
                 BUFGCE_DIVIDE => 6, -- 1-8 -divide by 6 to get 40 MHz
@@ -1456,16 +1086,7 @@ begin
                 CLR => '0', -- 1-bit input: Asynchronous clear
                 I => GT_RX_WORD_CLK(0) -- 1-bit input: Buffer 240 MHz RXUSER_CLK after BUFG_GT
             );
-        -- End of BUFGCE_DIV_inst instantiation
 
-        --OBUFDS to route the 240 MHz RXUSER CLK into the LMK03200 jitter cleaner  to create the TXREFCLK --MT/SS
-        OBUF240_LMK03200: OBUFDS
-            generic map (
-                IOSTANDARD => "LVDS",
-                SLEW       => "FAST")
-            port map(
-                I => GT_RXUSRCLK_40MHz,
-                O => CLK40_FPGA2LMK_out_P,
-                OB => CLK40_FPGA2LMK_out_N);
-    end generate; --bufgceobuf_notsim
+    end generate;
+
 end Behavioral;
diff --git a/sources/FELIG/LinkWrapper/FLX_LpGBT_FE_Wrapper_FELIG.vhd b/sources/FELIG/LinkWrapper/FLX_LpGBT_FE_Wrapper_FELIG.vhd
index e5d1588d43745528b60799d0db09c9d316ede060..7ade4ec058f4b08d4778f9673cfa0e13ad6496ad 100644
--- a/sources/FELIG/LinkWrapper/FLX_LpGBT_FE_Wrapper_FELIG.vhd
+++ b/sources/FELIG/LinkWrapper/FLX_LpGBT_FE_Wrapper_FELIG.vhd
@@ -40,11 +40,13 @@ library UNISIM;
     use work.FELIX_package.all;
     use work.pcie_package.all;
 
+Library xpm;
+    use xpm.vcomponents.all;
+
 entity FLX_LpGBT_FE_Wrapper_FELIG is
     Generic (
-        GBT_NUM                     : integer   := 24;
-        --MT SIMU+
-        sim_emulator            : boolean       := false
+        GBT_NUM                     : integer := 24;
+        sim_emulator                : boolean := false
     --
     );
     Port (
@@ -52,29 +54,22 @@ entity FLX_LpGBT_FE_Wrapper_FELIG is
         FE_DOWNLINK_USER_DATA       : out txrx32b_type(0 to GBT_NUM-1);
         FE_DOWNLINK_EC_DATA         : out txrx2b_type(0 to GBT_NUM-1);
         FE_DOWNLINK_IC_DATA         : out txrx2b_type(0 to GBT_NUM-1);
-
         FE_UPLINK_USER_DATA         : in txrx224b_type(0 to GBT_NUM-1);
         FE_UPLINK_EC_DATA           : in txrx2b_type(0 to GBT_NUM-1);
         FE_UPLINK_IC_DATA           : in txrx2b_type(0 to GBT_NUM-1);
-
+        FE_UPLINK_READY             : in std_logic_vector(0 to GBT_NUM-1);
         clk40_in                    : in std_logic;
-        clk320_in                   : in std_logic; --MT SIMU+
+        clk320_in                   : in std_logic;
         rst_hw                      : in std_logic;
-        FE_SIDE_RX40MCLK         : out std_logic;
-
         RX_P                        : in std_logic_vector(GBT_NUM-1 downto 0);
         RX_N                        : in std_logic_vector(GBT_NUM-1 downto 0);
         TX_P                        : out std_logic_vector(GBT_NUM-1 downto 0);
         TX_N                        : out std_logic_vector(GBT_NUM-1 downto 0);
-        --MT commented
-        --GTHREFCLK                   : in std_logic_vector(GBT_NUM-1 downto 0);
-        --MT added
         GTHREFCLK0                  : in std_logic_vector(GBT_NUM-1 downto 0); --RX
         GTHREFCLK1                  : in std_logic_vector(GBT_NUM-1 downto 0); --TX
-        --MT externalizing gtrx/txusrclk for FELIG logic
         GT_TXUSRCLK_OUT             : out std_logic_vector(GBT_NUM-1 downto 0);
         GT_RXUSRCLK_OUT             : out std_logic_vector(GBT_NUM-1 downto 0);
-
+        GT_RXCLK40_OUT              : out std_logic;
         CTRL_SOFT_RESET             : in std_logic_vector(GBT_NUM/4-1 downto 0);
         CTRL_TXPLL_DATAPATH_RESET   : in std_logic_vector(GBT_NUM/4-1 downto 0);
         CTRL_RXPLL_DATAPATH_RESET   : in std_logic_vector(GBT_NUM/4-1 downto 0);
@@ -86,12 +81,8 @@ entity FLX_LpGBT_FE_Wrapper_FELIG is
         CTRL_GBTRXRST               : in std_logic_vector(GBT_NUM-1 downto 0);
         CTRL_DATARATE               : in std_logic_vector(GBT_NUM-1 downto 0);
         CTRL_FECMODE                : in std_logic_vector(GBT_NUM-1 downto 0);
-
         CTRL_CHANNEL_DISABLE        : in std_logic_vector(GBT_NUM-1 downto 0);
         CTRL_GBT_General_ctrl       : in std_logic_vector(63 downto 0);
-
-
-
         MON_RXRSTDONE               : out std_logic_vector(GBT_NUM-1 downto 0);
         MON_TXRSTDONE               : out std_logic_vector(GBT_NUM-1 downto 0);
         MON_RXRSTDONE_QUAD          : out std_logic_vector(GBT_NUM/4-1 downto 0);
@@ -102,138 +93,94 @@ entity FLX_LpGBT_FE_Wrapper_FELIG is
         MON_RXCDR_LCK_QUAD          : out std_logic_vector(GBT_NUM/4-1 downto 0);
         MON_QPLL_LCK                : out std_logic_vector(GBT_NUM/4-1 downto 0);
         MON_CPLL_LCK                : out std_logic_vector(GBT_NUM-1 downto 0);
-
         MON_ALIGNMENT_DONE          : out std_logic_vector(GBT_NUM-1 downto 0);
         MON_LPGBT_ERRFLG            : out std_logic_vector(GBT_NUM-1 downto 0);
-        --MT for FELIG from mgt_framealigner . 1 pulse every c_wordRatio (=8)
         sta_headerFlag_out          : out std_logic_vector(GBT_NUM-1 downto 0);
-        --MT added: needed by FELIG to latch tx payload to generated data. Need to
-        --be synchronized with emulator logic
         tx_flag_out                 : out std_logic_vector(GBT_NUM-1 downto 0);
-        --MT LMK lock signal
         LMK_LD                      : in  std_logic;
         RxCdrLock_o                 : out std_logic_vector(GBT_NUM-1 downto 0);
-        alignment_done_o            : out std_logic_vector(GBT_NUM-1 downto 0)
-
-
+        alignment_done_o            : out std_logic_vector(GBT_NUM-1 downto 0);
+        MON_AUTO_RX_RESET_CNT       : out array_32b(0 to GBT_NUM-1);
+        CTRL_AUTO_RX_RESET_CNT_CLEAR: in  std_logic_vector(GBT_NUM-1 downto 0);
+        MON_FEC_ERROR               : out std_logic_vector(GBT_NUM-1 downto 0);
+        MON_FEC_ERR_CNT             : out array_32b(0 to GBT_NUM-1)
     );
 end FLX_LpGBT_FE_Wrapper_FELIG;
 
 
 architecture Behavioral of FLX_LpGBT_FE_Wrapper_FELIG is
-
-    component fifo_generator_fe IS
-        PORT (
-            rst : IN STD_LOGIC;
-            wr_clk : IN STD_LOGIC;
-            rd_clk : IN STD_LOGIC;
-            din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
-            wr_en : IN STD_LOGIC;
-            rd_en : IN STD_LOGIC;
-            dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-            full : OUT STD_LOGIC;
-            empty : OUT STD_LOGIC;
-            prog_full : OUT STD_LOGIC;
-            prog_empty : OUT STD_LOGIC;
-            wr_rst_busy : OUT STD_LOGIC;
-            rd_rst_busy : OUT STD_LOGIC
-        );
-    END component;
-
-    component rxclkgen is
-        port
- (
-
-            clk_out1 : out std_logic;
-
-            reset : in std_logic;
-            locked: out std_logic;
-
-            clk_in1: in std_logic
-        );
-    end component;
-
-    signal rxrecclk40m          : std_logic;
-    signal pulse_lg             : std_logic;
-    signal rxclk_locked         : std_logic;
-    signal alignment_done_f     : std_logic_vector(GBT_NUM-1 downto 0);
+    signal pulse_lg                 : std_logic;
+    signal alignment_done_f         : std_logic_vector(GBT_NUM-1 downto 0);
+    signal alignment_done_f_clk40   : std_logic_vector(GBT_NUM-1 downto 0);
     signal alignment_done_f_latched : std_logic_vector(GBT_NUM-1 downto 0);
-    signal RX_RESET_i           : std_logic_vector(GBT_NUM-1 downto 0);
-    signal TX_RESET_i           : std_logic_vector(GBT_NUM-1 downto 0);
-    signal TxResetDone          : std_logic_vector(GBT_NUM-1 downto 0);
-    signal GT_TX_WORD_CLK       : std_logic_vector(GBT_NUM-1 downto 0);
-    signal GT_RX_WORD_CLK       : std_logic_vector(GBT_NUM-1 downto 0);
-    signal rxresetdone          : std_logic_vector(GBT_NUM-1 downto 0);
-    --signal data_rdy             : std_logic_vector(GBT_NUM-1 downto 0); --RL not commented check
-    signal RxSlide              : std_logic_vector(GBT_NUM-1 downto 0);
-    --signal UplinkRdy            : std_logic_vector(GBT_NUM-1 downto 0); --RL not commented check
-    signal fifo_rst             : std_logic_vector(GBT_NUM-1 downto 0);
-    signal fifo_empty           : std_logic_vector(GBT_NUM-1 downto 0);
-    signal fifo_rden            : std_logic_vector(GBT_NUM-1 downto 0);
-    signal GT_TXOUTCLK          : std_logic_vector(GBT_NUM-1 downto 0);
-    signal GT_RXOUTCLK          : std_logic_vector(GBT_NUM-1 downto 0);
-    signal GT_TXUSRCLK          : std_logic_vector(GBT_NUM-1 downto 0);
-    signal GT_RXUSRCLK          : std_logic_vector(GBT_NUM-1 downto 0);
-    signal RX_N_i               : std_logic_vector(GBT_NUM-1 downto 0);
-    signal RX_P_i               : std_logic_vector(GBT_NUM-1 downto 0);
-    signal TX_N_i               : std_logic_vector(GBT_NUM-1 downto 0);
-    signal TX_P_i               : std_logic_vector(GBT_NUM-1 downto 0);
-    signal rxpmaresetdone       : std_logic_vector(GBT_NUM-1 downto 0);
-    signal txpmaresetdone       : std_logic_vector(GBT_NUM-1 downto 0);
-    signal RxCdrLock            : std_logic_vector(GBT_NUM-1 downto 0);
-    signal RxCdrLock_int        : std_logic_vector(GBT_NUM-1 downto 0);
-    signal RxCdrLock_a          : std_logic_vector(GBT_NUM-1 downto 0);
-    signal rxcdrlock_out        : std_logic_vector(GBT_NUM-1 downto 0);
-    signal auto_gth_rxrst       : std_logic_vector(GBT_NUM-1 downto 0);
-    signal drpclk_vec           : std_logic_vector(GBT_NUM/4-1 downto 0);
-    signal rxresetdone_quad     : std_logic_vector(GBT_NUM/4-1 downto 0);
-    signal txresetdone_quad     : std_logic_vector(GBT_NUM/4-1 downto 0);
-    signal RxCdrLock_quad       : std_logic_vector(GBT_NUM/4-1 downto 0);
-    signal userclk_rx_reset_in  : std_logic_vector(GBT_NUM/4-1 downto 0);
-    signal userclk_tx_reset_in  : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal TX_RESET_i               : std_logic_vector(GBT_NUM-1 downto 0);
+    signal TxResetDone              : std_logic_vector(GBT_NUM-1 downto 0);
+    signal TxResetDone_clk40        : std_logic_vector(GBT_NUM-1 downto 0);
+    signal GT_TX_WORD_CLK           : std_logic_vector(GBT_NUM-1 downto 0);
+    signal GT_RX_WORD_CLK           : std_logic_vector(GBT_NUM-1 downto 0);
+    signal rxresetdone              : std_logic_vector(GBT_NUM-1 downto 0);
+    signal rxresetdone_clk40        : std_logic_vector(GBT_NUM-1 downto 0);
+    signal RxSlide                  : std_logic_vector(GBT_NUM-1 downto 0);
+    signal GT_TXOUTCLK              : std_logic_vector(GBT_NUM-1 downto 0);
+    signal GT_RXOUTCLK              : std_logic_vector(GBT_NUM-1 downto 0);
+    signal GT_TXUSRCLK              : std_logic_vector(GBT_NUM-1 downto 0);
+    signal GT_RXUSRCLK              : std_logic_vector(GBT_NUM-1 downto 0);
+    signal RX_N_i                   : std_logic_vector(GBT_NUM-1 downto 0);
+    signal RX_P_i                   : std_logic_vector(GBT_NUM-1 downto 0);
+    signal TX_N_i                   : std_logic_vector(GBT_NUM-1 downto 0);
+    signal TX_P_i                   : std_logic_vector(GBT_NUM-1 downto 0);
+    signal rxpmaresetdone           : std_logic_vector(GBT_NUM-1 downto 0);
+    signal txpmaresetdone           : std_logic_vector(GBT_NUM-1 downto 0);
+    signal RxCdrLock                : std_logic_vector(GBT_NUM-1 downto 0);
+    signal RxCdrLock_int            : std_logic_vector(GBT_NUM-1 downto 0);
+    signal RxCdrLock_a              : std_logic_vector(GBT_NUM-1 downto 0);
+    signal rxcdrlock_out            : std_logic_vector(GBT_NUM-1 downto 0);
+    signal auto_gth_rxrst           : std_logic_vector(GBT_NUM-1 downto 0);
+    signal drpclk_vec               : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal rxresetdone_quad         : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal rxresetdone_quad_clk40   : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal txresetdone_quad         : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal txresetdone_quad_clk40   : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal RxCdrLock_quad           : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal userclk_rx_reset_in      : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal userclk_tx_reset_in      : std_logic_vector(GBT_NUM/4-1 downto 0);
     signal RX_DATAPATH_RESET_FINL   : std_logic_vector(GBT_NUM/4-1 downto 0);
-    signal GBT_General_ctrl     : std_logic_vector(63 downto 0);
-
-
-    --type txrx80b_12ch_type        is array (GBT_NUM/4-1 downto 0) of std_logic_vector(79 downto 0);  --RL not commented check
-    --signal RX_DATA_80b            : txrx80b_12ch_type; --RL not commented check
-    type data16barray       is array (0 to GBT_NUM-1) of std_logic_vector(15 downto 0);
-    type data32barray       is array (0 to GBT_NUM-1) of std_logic_vector(31 downto 0);
-    type data128barray       is array (0 to GBT_NUM/4-1) of std_logic_vector(127 downto 0);
-    signal RX_DATA_16b      : data16barray := (others => ("0000000000000000"));
-    signal TX_DATA_32b      : data32barray := (others => ("00000000000000000000000000000000"));
-    signal TX_DATA_128b      : data128barray := (others => (x"00000000000000000000000000000000"));
-    type data64barray       is array (0 to GBT_NUM-1) of std_logic_vector(63 downto 0);
-    signal RX_DATA_64b      : data64barray;
-    type data36barray       is array (0 to GBT_NUM-1) of std_logic_vector(35 downto 0);
-    signal downLinkData_i   : data36barray;
-    signal downLinkData_o   : data36barray;
-
-    signal cdr_cnt        : std_logic_vector(19 downto 0);
-    signal pulse_cnt      : std_logic_vector(29 downto 0);
-
-    --MT added
-    signal QpllLock_inv           : std_logic_vector(GBT_NUM/4-1 downto 0); --(11 downto 0);
-    signal QPLL_RESET_LMK         : std_logic_vector(GBT_NUM/4-1 downto 0); --(11 downto 0);
-    signal QPLL_PIPE              : std_logic_vector(3 downto 0);
-    signal qpll1_lck_i            : std_logic_vector(GBT_NUM/4-1 downto 0);
-
-    --RL
-    signal reset_rxclkgen   : std_logic;
-    signal reset_tx_pll_and_datapath_in : std_logic_vector(GBT_NUM/4-1 downto 0);
-    signal txclk40m         : std_logic_vector(GBT_NUM-1 downto 0);
+    signal GBT_General_ctrl         : std_logic_vector(63 downto 0);
+    type data16barray   is array (0 to GBT_NUM-1) of std_logic_vector(15 downto 0);
+    type data32barray   is array (0 to GBT_NUM-1) of std_logic_vector(31 downto 0);
+    type data128barray  is array (0 to GBT_NUM/4-1) of std_logic_vector(127 downto 0);
+    signal RX_DATA_16b              : data16barray := (others => ("0000000000000000"));
+    signal TX_DATA_32b              : data32barray := (others => ("00000000000000000000000000000000"));
+    signal TX_DATA_128b             : data128barray := (others => (x"00000000000000000000000000000000"));
+    type data64barray   is array (0 to GBT_NUM-1) of std_logic_vector(63 downto 0);
+    signal RX_DATA_64b              : data64barray;
+    signal cdr_cnt                  : std_logic_vector(19 downto 0);
+    signal pulse_cnt                : std_logic_vector(29 downto 0);
+
+    signal QpllLock_inv             : std_logic_vector(GBT_NUM/4-1 downto 0); --(11 downto 0);
+    signal QPLL_RESET_LMK           : std_logic_vector(GBT_NUM/4-1 downto 0); --(11 downto 0);
+    signal QPLL_PIPE                : std_logic_vector(3 downto 0);
+    signal qpll1_lck_i              : std_logic_vector(GBT_NUM/4-1 downto 0);
+
+    signal reset_tx_pll_dpath_in    : std_logic_vector(GBT_NUM/4-1 downto 0);
+    signal GT_RXCLK40               : std_logic;
+    signal tx_polarity              : std_logic_vector(GBT_NUM-1 downto 0);
+    signal rx_polarity              : std_logic_vector(GBT_NUM-1 downto 0);
 
 begin
 
-    GBT_General_ctrl <= CTRL_GBT_General_ctrl;
+    GBT_General_ctrl    <= CTRL_GBT_General_ctrl;
+
+    MON_ALIGNMENT_DONE  <= alignment_done_f_clk40 when GBT_General_ctrl(43)='0' else alignment_done_f_latched;
+    MON_LPGBT_ERRFLG    <= (others=>'0');
 
+    GT_RXCLK40_OUT      <= GT_RXCLK40;
+    RxCdrLock_o         <= RxCdrLock;
+    alignment_done_o    <= alignment_done_f;
 
-    MON_ALIGNMENT_DONE <= alignment_done_f when GBT_General_ctrl(43)='0' else alignment_done_f_latched;
-    MON_LPGBT_ERRFLG <= (others=>'0'); --unused
+    GT_TXUSRCLK_OUT     <= GT_TXUSRCLK;
+    GT_RXUSRCLK_OUT     <= GT_RXUSRCLK;
 
-    FE_SIDE_RX40MCLK <= rxrecclk40m;
-    RxCdrLock_o <= RxCdrLock;
-    alignment_done_o <= alignment_done_f;
 
     process(clk40_in)
     begin
@@ -248,22 +195,25 @@ begin
     end process;
 
     gbtRxTx : for i in 0 to GBT_NUM-1 generate
-        signal rst_dnlink : std_logic;--RL
+        signal rst_dnlink                   : std_logic;
+        signal fecCorrectionCount           : std_logic_vector(15 downto 0) := (others => '0');
+        signal fecCorrectionCount_clk40     : std_logic_vector(15 downto 0) := (others => '0');
+        signal fecCorrectionCount_zero      : std_logic_vector(15 downto 0) := (others => '0');
+        signal fecErrorCount                : std_logic_vector(31 downto 0) := (others => '0');
+        signal fecError                     : std_logic := '0';
     begin
-        RX_RESET_i(i)       <= CTRL_GBTRXRST(i);
         TX_RESET_i(i)       <= CTRL_GBTTXRST(i) or (not TxResetDone(i));
-
         process(clk40_in)
         begin
             if clk40_in'event and clk40_in='1' then
                 if GBT_General_ctrl(45)='1' then
                     alignment_done_f_latched(i) <='1';
                 else
-                    alignment_done_f_latched(i) <= alignment_done_f_latched(i) and alignment_done_f(i);
+                    alignment_done_f_latched(i) <= alignment_done_f_latched(i) and alignment_done_f_clk40(i);
                 end if;
 
                 if pulse_lg = '1' then
-                    if alignment_done_f(i)='0' and rxresetdone_quad(i/4)='1' and rxresetdone(i)='1' then
+                    if alignment_done_f_clk40(i)='0' and rxresetdone_quad_clk40(i/4)='1' and rxresetdone_clk40(i)='1' then
                         auto_gth_rxrst(i) <='1';
                     else
                         auto_gth_rxrst(i) <='0';
@@ -273,94 +223,85 @@ begin
                 end if;
             end if;
         end process;
-        rst_dnlink <= (not rxclk_locked) or RX_RESET_i(i); --RL
+
         lpgbtemu: entity work.FLX_LpGBT_FE
             Port map
-    (
-                TXCLK40 => txclk40m(i),--clk40_in,
-                RXCLK40 => rxrecclk40m,
-                TXCLK320 => GT_TX_WORD_CLK(i),
-                RXCLK320 => GT_RX_WORD_CLK(i),
-                rst_uplink_i => TX_RESET_i(i), --RL: not?
-                --uplinkClkEn_i               => '1',
-                ctr_clkSlip_s => RxSlide(i),
-                aligned => alignment_done_f(i),
-                --uplinkRdy_o                 => open,  --RL uncommented in FELIG
-                --downlinkRdy_o               => open,--downlinkrdy(i), --RL uncommented in FELIG
-                sta_headerFlag_o => sta_headerFlag_out(i),
-                sta_headerFlag_shift => open, --sta_headerFlag_shift(i),
-                --sta_rxgbxRdy_o              => open,--sta_rxgbxRdy_o(i), --RL uncommented in FELIG
-                clk_dataFlag_rxGb_s_o => open,--clk_dataFlag_rxGb_s_o(i),
-                dat_upLinkWord_fromGb_s => TX_DATA_32b(i),
-                dat_downLinkWord_fromMgt_s16 => RX_DATA_16b(i),
-                --sta_mgtTxRdy_s              => txresetdone(i),  --RL uncommented in FELIG
-                rst_dnlink_i => rst_dnlink,--RL
-                sta_mgtRxRdy_s => rxresetdone(i),
-
-                downLinkBypassDeinterleaver => '0',
-                downLinkBypassFECDecoder=> '0',
-                downLinkBypassDescsrambler => '0',
-
-                enableFECErrCounter => '0',
-
-                upLinkScramblerBypass => GBT_General_ctrl(32),
-
-                upLinkFecBypass => GBT_General_ctrl(33),
-                upLinkInterleaverBypass => GBT_General_ctrl(34),
-                fecMode => CTRL_FECMODE(i),
-                txDataRate => CTRL_DATARATE(i),
-                phase_sel => "100",
-                upLinkData => FE_UPLINK_USER_DATA(i),
-                upLinkDataIC => FE_UPLINK_IC_DATA(i),
-                upLinkDataEC => FE_UPLINK_EC_DATA(i),
-                downLinkData => downLinkData_i(i)(31 downto 0),
-                downLinkDataIC => downLinkData_i(i)(33 downto 32),
-                downLinkDataEC => downLinkData_i(i)(35 downto 34),
-                --MT added: needed by FELIG to latch tx payload to generated data. Need to
-                --be synchronized with emulator logic
-                tx_flag_out                 => tx_flag_out(i)
+            (
+                clk40_in                        => GT_RXCLK40,
+                TXCLK320                        => GT_TX_WORD_CLK(i),
+                RXCLK320                        => GT_RX_WORD_CLK(i),
+                rst_uplink_i                    => TX_RESET_i(i),
+                ctr_clkSlip_s                   => RxSlide(i),
+                aligned                         => alignment_done_f(i),
+                sta_headerFlag_o                => sta_headerFlag_out(i),
+                dat_upLinkWord_fromGb_s         => TX_DATA_32b(i),
+                dat_downLinkWord_fromMgt_s16    => RX_DATA_16b(i),
+                rst_dnlink_i                    => rst_dnlink,
+                sta_mgtRxRdy_s                  => rxresetdone(i),
+                downLinkBypassDeinterleaver     => '0',
+                downLinkBypassFECDecoder        => '0',
+                downLinkBypassDescsrambler      => '0',
+                enableFECErrCounter             => '0',
+                upLinkScramblerBypass           => GBT_General_ctrl(32),
+                upLinkInterleaverBypass         => GBT_General_ctrl(34),
+                fecMode                         => CTRL_FECMODE(i),
+                txDataRate                      => CTRL_DATARATE(i),
+                phase_sel                       => "100",
+                upLinkData                      => FE_UPLINK_USER_DATA(i),
+                upLinkDataIC                    => FE_UPLINK_IC_DATA(i),
+                upLinkDataEC                    => FE_UPLINK_EC_DATA(i),
+                upLinkDataREADY                 => FE_UPLINK_READY(i),
+                downLinkData                    => FE_DOWNLINK_USER_DATA(i),
+                downLinkDataIC                  => FE_DOWNLINK_IC_DATA(i),
+                downLinkDataEC                  => FE_DOWNLINK_EC_DATA(i),
+                tx_flag_out                     => tx_flag_out(i),
+                fecCorrectionCount              => fecCorrectionCount
             );
 
-        FE_DOWNLINK_USER_DATA(i) <= downLinkData_o(i)(31 downto 0);
-        FE_DOWNLINK_IC_DATA(i) <= downLinkData_o(i)(33 downto 32);
-        FE_DOWNLINK_EC_DATA(i) <= downLinkData_o(i)(35 downto 34);
-        fifo_rst(i) <= (not alignment_done_f(i)) or rst_hw or (not rxclk_locked) or GBT_General_ctrl(4);
-        fifo_rden(i) <= not fifo_empty(i);
-
-        fifo_inst: fifo_generator_fe
-            PORT MAP(
-                rst => fifo_rst(i),--rst_hw,
-                wr_clk => rxrecclk40m,
-                rd_clk => rxrecclk40m,
-                din => downLinkData_i(i),
-                wr_en => '1',--fifo_wr(i),
-                rd_en => fifo_rden(i),
-                dout => downLinkData_o(i),
-                full  => open,
-                empty  => fifo_empty(i),
-                prog_full  => open,
-                prog_empty  => open,
-                wr_rst_busy  => open,
-                rd_rst_busy  => open
+        xpm_fecCorrectionCount : xpm_cdc_array_single generic map(
+                DEST_SYNC_FF => 4,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 1,
+                WIDTH => 16
+            )
+            port map(
+                src_clk => GT_RX_WORD_CLK(i),
+                src_in => fecCorrectionCount,
+                dest_clk => clk40_in,
+                dest_out => fecCorrectionCount_clk40
             );
 
-    end generate;
-
-    reset_rxclkgen <=(not alignment_done_f(0)) or GBT_General_ctrl(41);--RL
-
-    rxclkgen_inst: rxclkgen
-        port map
-    (
-
-            clk_out1 => rxrecclk40m,
+        process(clk40_in)
+        begin
+            if clk40_in'event and clk40_in='1' then
+                if fecCorrectionCount_clk40 /= fecCorrectionCount_zero then
+                    fecErrorCount   <= fecErrorCount + "1";
+                    fecError        <= '1';
+                else
+                    fecError        <= '0';
+                end if;
+            end if;
+        end process;
+        MON_FEC_ERR_CNT(i)  <= fecErrorCount;
+        MON_FEC_ERROR(i)    <= fecError;
 
-            reset => reset_rxclkgen,--RL
-            locked => rxclk_locked,
+    end generate;
 
-            clk_in1=> GT_RX_WORD_CLK(0)
+    BUFGCE_DIV_RX_inst : BUFGCE_DIV
+        generic map (
+            BUFGCE_DIVIDE => 8,
+            IS_CE_INVERTED => '0',
+            IS_CLR_INVERTED => '0',
+            IS_I_INVERTED => '0'
+        )
+        port map (
+            O => GT_RXCLK40,
+            CE => '1',
+            CLR => '0',
+            I => GT_RX_WORD_CLK(0)
         );
 
-    --MT SIMU+
     outclk_sim : if sim_emulator = true generate
         GT_TXOUTCLK <= (others => clk320_in);
         GT_RXOUTCLK <= (others => clk320_in);
@@ -368,12 +309,12 @@ begin
 
     clk_generate : for i in 0 to GBT_NUM-1 generate
 
-        GTTXOUTCLK_BUFG: bufg_gt -- @suppress "Generic map uses default values. Missing optional actuals: SIM_DEVICE, STARTUP_SYNC"
+        GTTXOUTCLK_BUFG: bufg_gt
             port map(
                 o => GT_TXUSRCLK(i),
                 ce => '1',
                 cemask => '0',
-                clr => '0', --userclk_tx_reset_in,--'0',
+                clr => '0',
                 clrmask => '0',
                 div => "000",
                 i => GT_TXOUTCLK(i)
@@ -381,35 +322,18 @@ begin
 
         GT_TX_WORD_CLK(i) <= GT_TXUSRCLK(i);
 
-        GTRXOUTCLK_BUFG: bufg_gt -- @suppress "Generic map uses default values. Missing optional actuals: SIM_DEVICE, STARTUP_SYNC"
+        GTRXOUTCLK_BUFG: bufg_gt
             port map(
                 o => GT_RXUSRCLK(i),
                 ce => '1',
                 cemask => '0',
-                clr => '0', --userclk_tx_reset_in,--'0',
+                clr => '0',
                 clrmask => '0',
                 div => "000",
                 i => GT_RXOUTCLK(i)
             );
 
         GT_RX_WORD_CLK(i) <= GT_RXUSRCLK(i);
-
-        --RL
-        BUFGCE_DIV_inst : BUFGCE_DIV
-            generic map (
-                BUFGCE_DIVIDE => 8, -- 1-8 -divide by 8 to get 40 MHz
-                -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
-                IS_CE_INVERTED => '0', -- Optional inversion for CE
-                IS_CLR_INVERTED => '0', -- Optional inversion for CLR
-                IS_I_INVERTED => '0' -- Optional inversion for I
-            )
-            port map (
-                O => txclk40m(i), -- 1-bit output: Buffer
-                CE => '1', -- 1-bit input: Buffer enable
-                CLR => '0', -- 1-bit input: Asynchronous clear
-                I => GT_TX_WORD_CLK(i) -- 1-bit input: Buffer 240 MHz RXUSER_CLK after BUFG_GT
-            );
-    -- End of BUFGCE_DIV_inst instantiation
     end generate;
 
 
@@ -437,90 +361,79 @@ begin
             TX_P(i)     <= TX_P_i(i);
         end generate;
 
-        GTH_inst : for i in 0 to (GBT_NUM/4)-1 generate
+        process(clk40_in)
+        begin
+            if clk40_in'event and clk40_in='1' then
+                QPLL_PIPE(3 downto 1) <= QPLL_PIPE(2 downto 0);
+                QPLL_PIPE(0) <= LMK_LD;
+                if ((QPLL_PIPE(3) = '0') AND (QPLL_PIPE(0) = '1')) then --rising edge
+                    QPLL_RESET_LMK  <= QpllLock_inv;
+                else
+                    QPLL_RESET_LMK  <= (others =>'0');
+                end if;
+            end if;
+        end process;
 
-            RX_DATA_16b(4*i+0) <= RX_DATA_64b(i)(15 downto 0);
-            RX_DATA_16b(4*i+1) <= RX_DATA_64b(i)(31 downto 16);
-            RX_DATA_16b(4*i+2) <= RX_DATA_64b(i)(47 downto 32);
-            RX_DATA_16b(4*i+3) <= RX_DATA_64b(i)(63 downto 48);
-            drpclk_vec(i)       <= clk40_in;
-            TX_DATA_128b(i) <= TX_DATA_32b(4*i+3) & TX_DATA_32b(4*i+2) & TX_DATA_32b(4*i+1) & TX_DATA_32b(4*i+0);
+        GTH_inst : for i in 0 to (GBT_NUM/4)-1 generate
+            RX_DATA_16b(4*i+0)              <= RX_DATA_64b(i)(15 downto 0);
+            RX_DATA_16b(4*i+1)              <= RX_DATA_64b(i)(31 downto 16);
+            RX_DATA_16b(4*i+2)              <= RX_DATA_64b(i)(47 downto 32);
+            RX_DATA_16b(4*i+3)              <= RX_DATA_64b(i)(63 downto 48);
+            drpclk_vec(i)                   <= clk40_in;
+            TX_DATA_128b(i)                 <= TX_DATA_32b(4*i+3) & TX_DATA_32b(4*i+2) & TX_DATA_32b(4*i+1) & TX_DATA_32b(4*i+0);
+            MON_QPLL_LCK(i)                 <= qpll1_lck_i(i);
+            reset_tx_pll_dpath_in(i)        <= CTRL_TXPLL_DATAPATH_RESET(i) or QPLL_RESET_LMK(i);
+            QpllLock_inv(i)                 <= not qpll1_lck_i(i);
 
-            --- QPLL Reset Process----- MT
-            QpllLock_inv <= not qpll1_lck_i;
 
-            process(clk40_in)
-            begin
-                if clk40_in'event and clk40_in='1' then
-                    QPLL_PIPE(3 downto 1) <= QPLL_PIPE(2 downto 0);
-                    QPLL_PIPE(0) <= LMK_LD;
-                    if ((QPLL_PIPE(3) = '0') AND (QPLL_PIPE(0) = '1')) then --rising edge
-                        QPLL_RESET_LMK  <= QpllLock_inv;
-                    else
-                        QPLL_RESET_LMK  <= (others =>'0');
-                    end if;
-                end if;
-            end process;
 
-            --MT added
-            MON_QPLL_LCK <= qpll1_lck_i;
-            --
-            --RL
-            reset_tx_pll_and_datapath_in(i) <= CTRL_TXPLL_DATAPATH_RESET(i) or QPLL_RESET_LMK(i);
             GTH_TOP_INST: entity work.FLX_LpGBT_GTH_FE_FELIG
-                Port map
-        (
-                    gthrxn_in => RX_N_i(4*i+3 downto 4*i),
-                    gthrxp_in => RX_P_i(4*i+3 downto 4*i),
-                    gthtxn_out => TX_N_i(4*i+3 downto 4*i),
-                    gthtxp_out => TX_P_i(4*i+3 downto 4*i),
-                    drpclk_in => drpclk_vec(i downto i),
-                    --MT commented
-                    --gtrefclk0_in => GTHREFCLK(4*i downto 4*i), --in master
-                    --MT added
-                    gtrefclk0_in => GTHREFCLK0(4*i downto 4*i), --RX 320
-                    gtrefclk1_in => GTHREFCLK1(4*i downto 4*i), --TX 240
-                    gt_rxusrclk_in => GT_RX_WORD_CLK(4*i+3 downto 4*i),
-                    gt_rxoutclk_out => GT_RXOUTCLK(4*i+3 downto 4*i),
-                    gt_txusrclk_in => GT_TX_WORD_CLK(4*i+3 downto 4*i),
-                    gt_txoutclk_out => GT_TXOUTCLK(4*i+3 downto 4*i),
-                    userdata_tx_in => TX_DATA_128b(i),
-                    userdata_rx_out => RX_DATA_64b(i),
-                    rxpolarity_in => CTRL_RXPOLARITY(4*i+3 downto 4*i),
-                    txpolarity_in => CTRL_TXPOLARITY(4*i+3 downto 4*i),
-                    loopback_in => "000",
-                    rxcdrhold_in => '0',
-                    userclk_rx_reset_in => userclk_rx_reset_in(i downto i), --(others=>(not rxpmaresetdone_out(i))),--locked,
-                    userclk_tx_reset_in => userclk_tx_reset_in(i downto i), --(others=>(not txpmaresetdone_out(i))),--,--locked,
-                    reset_all_in => CTRL_SOFT_RESET(i downto i),
-                    --MT commented
-                    --reset_tx_pll_and_datapath_in => CTRL_TXPLL_DATAPATH_RESET(i downto i), --RL replaced with line below
-                    reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath_in(i downto i),
-                    reset_tx_datapath_in => CTRL_TX_DATAPATH_RESET(i downto i),
-                    reset_rx_pll_and_datapath_in => CTRL_RXPLL_DATAPATH_RESET(i downto i),
-                    reset_rx_datapath_in => RX_DATAPATH_RESET_FINL(i downto i),
-                    qpll0lock_out => open,
-                    qpll1lock_out => qpll1_lck_i(i downto i), --MT MON_QPLL_LCK(i downto i),--RL changed in FELIG
-                    qpll1fbclklost_out => open,
-                    qpll0fbclklost_out => open,
-                    rxslide_in => RxSlide(4*i+3 downto 4*i),
-                    cplllock_out => MON_CPLL_LCK(4*i+3 downto 4*i),
-                    rxresetdone_out => rxresetdone(4*i+3 downto 4*i),
-                    txresetdone_out => TxResetDone(4*i+3 downto 4*i),
-                    rxpmaresetdone_out => rxpmaresetdone(4*i+3 downto 4*i),
-                    txpmaresetdone_out => txpmaresetdone(4*i+3 downto 4*i),
-
-                    reset_tx_done_out => txresetdone_quad(i downto i),
-                    reset_rx_done_out => rxresetdone_quad(i downto i),
-                    reset_rx_cdr_stable_out => RxCdrLock_quad(i downto i),
-                    rxcdrlock_out => rxcdrlock_out(4*i+3 downto 4*i)
+                Port map(
+                    gthrxn_in                       => RX_N_i(4*i+3 downto 4*i),
+                    gthrxp_in                       => RX_P_i(4*i+3 downto 4*i),
+                    gthtxn_out                      => TX_N_i(4*i+3 downto 4*i),
+                    gthtxp_out                      => TX_P_i(4*i+3 downto 4*i),
+                    drpclk_in                       => drpclk_vec(i downto i),
+                    gtrefclk0_in                    => GTHREFCLK0(4*i downto 4*i), --RX 320
+                    gtrefclk1_in                    => GTHREFCLK1(4*i downto 4*i), --TX 240
+                    gt_rxusrclk_in                  => GT_RX_WORD_CLK(4*i+3 downto 4*i),
+                    gt_rxoutclk_out                 => GT_RXOUTCLK(4*i+3 downto 4*i),
+                    gt_txusrclk_in                  => GT_TX_WORD_CLK(4*i+3 downto 4*i),
+                    gt_txoutclk_out                 => GT_TXOUTCLK(4*i+3 downto 4*i),
+                    userdata_tx_in                  => TX_DATA_128b(i),
+                    userdata_rx_out                 => RX_DATA_64b(i),
+                    rxpolarity_in                   => rx_polarity(4*i+3 downto 4*i),
+                    txpolarity_in                   => tx_polarity(4*i+3 downto 4*i),
+                    loopback_in                     => "000",
+                    rxcdrhold_in                    => '0',
+                    userclk_rx_reset_in             => userclk_rx_reset_in(i downto i),
+                    userclk_tx_reset_in             => userclk_tx_reset_in(i downto i),
+                    reset_all_in                    => CTRL_SOFT_RESET(i downto i),
+                    reset_tx_pll_and_datapath_in    => reset_tx_pll_dpath_in(i downto i),
+                    reset_tx_datapath_in            => CTRL_TX_DATAPATH_RESET(i downto i),
+                    reset_rx_pll_and_datapath_in    => CTRL_RXPLL_DATAPATH_RESET(i downto i),
+                    reset_rx_datapath_in            => RX_DATAPATH_RESET_FINL(i downto i),
+                    qpll0lock_out                   => open,
+                    qpll1lock_out                   => qpll1_lck_i(i downto i),
+                    qpll1fbclklost_out              => open,
+                    qpll0fbclklost_out              => open,
+                    rxslide_in                      => RxSlide(4*i+3 downto 4*i),
+                    cplllock_out                    => MON_CPLL_LCK(4*i+3 downto 4*i),
+                    rxresetdone_out                 => rxresetdone(4*i+3 downto 4*i),
+                    txresetdone_out                 => TxResetDone(4*i+3 downto 4*i),
+                    rxpmaresetdone_out              => rxpmaresetdone(4*i+3 downto 4*i),
+                    txpmaresetdone_out              => txpmaresetdone(4*i+3 downto 4*i),
+                    reset_tx_done_out               => txresetdone_quad(i downto i),
+                    reset_rx_done_out               => rxresetdone_quad(i downto i),
+                    reset_rx_cdr_stable_out         => RxCdrLock_quad(i downto i),
+                    rxcdrlock_out                   => rxcdrlock_out(4*i+3 downto 4*i)
                 );
 
 
-            MON_RXRSTDONE(4*i+3 downto 4*i)             <= rxresetdone(4*i+3 downto 4*i);
-            MON_TXRSTDONE(4*i+3 downto 4*i)             <= TxResetDone(4*i+3 downto 4*i);
-            MON_RXRSTDONE_QUAD(i downto i)              <= rxresetdone_quad(i downto i);
-            MON_TXRSTDONE_QUAD(i downto i)              <= txresetdone_quad(i downto i);
+            MON_RXRSTDONE(4*i+3 downto 4*i)             <= rxresetdone_clk40(4*i+3 downto 4*i);
+            MON_TXRSTDONE(4*i+3 downto 4*i)             <= TxResetDone_clk40(4*i+3 downto 4*i);
+            MON_RXRSTDONE_QUAD(i downto i)              <= rxresetdone_quad_clk40(i downto i);
+            MON_TXRSTDONE_QUAD(i downto i)              <= txresetdone_quad_clk40(i downto i);
             MON_RXPMARSTDONE(4*i+3 downto 4*i)          <= rxpmaresetdone(4*i+3 downto 4*i);
             MON_TXPMARSTDONE(4*i+3 downto 4*i)          <= txpmaresetdone(4*i+3 downto 4*i);
             MON_RXCDR_LCK(4*i+3 downto 4*i)             <= RxCdrLock(4*i+3 downto 4*i);
@@ -530,56 +443,169 @@ begin
             begin
                 if clk40_in'event and clk40_in='1' then
                     if cdr_cnt ="00000000000000000000" then
-                        RxCdrLock_a(4*i)     <= rxcdrlock_out(4*i);
-                        RxCdrLock_a(4*i+1)   <= rxcdrlock_out(4*i+1);
-                        RxCdrLock_a(4*i+2)   <= rxcdrlock_out(4*i+2);
-                        RxCdrLock_a(4*i+3)   <= rxcdrlock_out(4*i+3);
+                        RxCdrLock_a(4*i)        <= rxcdrlock_out(4*i);
+                        RxCdrLock_a(4*i+1)      <= rxcdrlock_out(4*i+1);
+                        RxCdrLock_a(4*i+2)      <= rxcdrlock_out(4*i+2);
+                        RxCdrLock_a(4*i+3)      <= rxcdrlock_out(4*i+3);
                     else
-                        RxCdrLock_a(4*i) <= RxCdrLock_a(4*i) and rxcdrlock_out(4*i);
-                        RxCdrLock_a(4*i+1) <= RxCdrLock_a(4*i+1) and rxcdrlock_out(4*i+1);
-                        RxCdrLock_a(4*i+2) <= RxCdrLock_a(4*i+2) and rxcdrlock_out(4*i+2);
-                        RxCdrLock_a(4*i+3) <= RxCdrLock_a(4*i+3) and rxcdrlock_out(4*i+3);
+                        RxCdrLock_a(4*i)        <= RxCdrLock_a(4*i) and rxcdrlock_out(4*i);
+                        RxCdrLock_a(4*i+1)      <= RxCdrLock_a(4*i+1) and rxcdrlock_out(4*i+1);
+                        RxCdrLock_a(4*i+2)      <= RxCdrLock_a(4*i+2) and rxcdrlock_out(4*i+2);
+                        RxCdrLock_a(4*i+3)      <= RxCdrLock_a(4*i+3) and rxcdrlock_out(4*i+3);
                     end if;
                     if cdr_cnt="00000000000000000000" then
-                        RxCdrLock_int(4*i) <=RxCdrLock_a(4*i);
-                        RxCdrLock_int(4*i+1) <=RxCdrLock_a(4*i+1);
-                        RxCdrLock_int(4*i+2) <=RxCdrLock_a(4*i+2);
-                        RxCdrLock_int(4*i+3) <=RxCdrLock_a(4*i+3);
+                        RxCdrLock_int(4*i)      <= RxCdrLock_a(4*i);
+                        RxCdrLock_int(4*i+1)    <= RxCdrLock_a(4*i+1);
+                        RxCdrLock_int(4*i+2)    <= RxCdrLock_a(4*i+2);
+                        RxCdrLock_int(4*i+3)    <= RxCdrLock_a(4*i+3);
                     end if;
                 end if;
             end process;
 
-            RxCdrLock(4*i) <= (not CTRL_CHANNEL_DISABLE(4*i)) and RxCdrLock_int(4*i);
-            RxCdrLock(4*i+1) <= (not CTRL_CHANNEL_DISABLE(4*i+1)) and RxCdrLock_int(4*i+1);
-            RxCdrLock(4*i+2) <= (not CTRL_CHANNEL_DISABLE(4*i+2)) and RxCdrLock_int(4*i+2);
-            RxCdrLock(4*i+3) <= (not CTRL_CHANNEL_DISABLE(4*i+3)) and RxCdrLock_int(4*i+3);
+            RxCdrLock(4*i)      <= (not CTRL_CHANNEL_DISABLE(4*i)) and RxCdrLock_int(4*i);
+            RxCdrLock(4*i+1)    <= (not CTRL_CHANNEL_DISABLE(4*i+1)) and RxCdrLock_int(4*i+1);
+            RxCdrLock(4*i+2)    <= (not CTRL_CHANNEL_DISABLE(4*i+2)) and RxCdrLock_int(4*i+2);
+            RxCdrLock(4*i+3)    <= (not CTRL_CHANNEL_DISABLE(4*i+3)) and RxCdrLock_int(4*i+3);
 
 
-            userclk_rx_reset_in(i) <=not (rxpmaresetdone(4*i+0) or rxpmaresetdone(4*i+1) or rxpmaresetdone(4*i+2) or rxpmaresetdone(4*i+3));
-            userclk_tx_reset_in(i) <=not (txpmaresetdone(4*i+0) or txpmaresetdone(4*i+1) or txpmaresetdone(4*i+2) or txpmaresetdone(4*i+3));
+            userclk_rx_reset_in(i) <= not (rxpmaresetdone(4*i+0) or rxpmaresetdone(4*i+1) or rxpmaresetdone(4*i+2) or rxpmaresetdone(4*i+3));
+            userclk_tx_reset_in(i) <= not (txpmaresetdone(4*i+0) or txpmaresetdone(4*i+1) or txpmaresetdone(4*i+2) or txpmaresetdone(4*i+3));
 
             RX_DATAPATH_RESET_FINL(i) <= CTRL_RX_DATAPATH_RESET(i) or (auto_gth_rxrst(4*i) and RxCdrLock(4*i))
                                          or (auto_gth_rxrst(4*i+1) and RxCdrLock(4*i+1))
                                          or (auto_gth_rxrst(4*i+2) and RxCdrLock(4*i+2))
                                          or (auto_gth_rxrst(4*i+3) and RxCdrLock(4*i+3)) ;
-
-
-
         end generate;
 
-
         process(clk40_in)
         begin
             if clk40_in'event and clk40_in='1' then
                 cdr_cnt <=cdr_cnt+'1';
             end if;
         end process;
-    end generate; --mgt_notsim
+    end generate;
 
-    --MT externalizing gtrx/txusrclk for FELIG logic
-    GT_TXUSRCLK_OUT <= GT_TXUSRCLK(GBT_NUM-1 downto 0);
-    GT_RXUSRCLK_OUT <= GT_RXUSRCLK(GBT_NUM-1 downto 0);
+    --autoreset counter
+    lpgbtModeAutoRxReset_cnt_g: for i in 0 to GBT_NUM-1 generate
+        signal RXRESET_AUTO_CNT: std_logic_vector(31 downto 0);
+        signal RXRESET_AUTO_p1: std_logic;
+    begin
+        cnt_proc: process(clk40_in)
+        begin
+            if rising_edge(clk40_in) then
+                RXRESET_AUTO_p1 <= auto_gth_rxrst(i);
+                if rst_hw = '1' or CTRL_AUTO_RX_RESET_CNT_CLEAR(i) = '1' then
+                    RXRESET_AUTO_CNT <= (others => '0');
+                elsif auto_gth_rxrst(i) = '1' and RXRESET_AUTO_p1 = '0' then
+                    RXRESET_AUTO_CNT <= RXRESET_AUTO_CNT + 1;
+                end if;
+            end if;
+        end process;
+        MON_AUTO_RX_RESET_CNT(i) <= RXRESET_AUTO_CNT;
+    end generate;
 
+    channel_cdc: for i in 0 to GBT_NUM-1 generate
+        xpm_cdc_rxresetdone : xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0
+            )
+            port map (
+                src_clk => '0',
+                src_in => rxresetdone(i),
+                dest_clk => clk40_in,
+                dest_out => rxresetdone_clk40(i)
+            );
 
+        xpm_cdc_txresetdone : xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0
+            )
+            port map (
+                src_clk => '0',
+                src_in => TxResetDone(i),
+                dest_clk => clk40_in,
+                dest_out => TxResetDone_clk40(i)
+            );
+
+        xpm_cdc_alignment_done_f : xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 4,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 1
+            )
+            port map (
+                src_clk => GT_RX_WORD_CLK(i),
+                src_in => alignment_done_f(i),
+                dest_clk => clk40_in,
+                dest_out => alignment_done_f_clk40(i)
+            );
+
+        xpm_cdc_txpolarity : xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0
+            )
+            port map (
+                src_clk => '0',
+                src_in => CTRL_TXPOLARITY(i),
+                dest_clk => GT_TX_WORD_CLK(i),
+                dest_out => tx_polarity(i)
+            );
+
+        xpm_cdc_rxpolarity : xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0
+            )
+            port map (
+                src_clk => '0',
+                src_in => CTRL_RXPOLARITY(i),
+                dest_clk => GT_RX_WORD_CLK(i),
+                dest_out => rx_polarity(i)
+            );
+
+    end generate;
+
+    quad_cdc: for i in 0 to GBT_NUM/4-1 generate
+
+        xpm_cdc_rxresetdone_quad : xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 4,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 1
+            )
+            port map (
+                src_clk => GT_RX_WORD_CLK(4*i),
+                src_in => rxresetdone_quad(i),
+                dest_clk => clk40_in,
+                dest_out => rxresetdone_quad_clk40(i)
+            );
+
+        xpm_cdc_txresetdone_quad : xpm_cdc_single
+            generic map (
+                DEST_SYNC_FF => 4,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 1
+            )
+            port map (
+                src_clk => GT_TX_WORD_CLK(4*i),
+                src_in => txresetdone_quad(i),
+                dest_clk => clk40_in,
+                dest_out => txresetdone_quad_clk40(i)
+            );
+    end generate;
 
 end Behavioral;
diff --git a/sources/FELIG/LinkWrapper/LMK_FELIG_wrapper.vhd b/sources/FELIG/LinkWrapper/LMK_FELIG_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9d64d127a8097746d5a232d2132da0bf81f2efff
--- /dev/null
+++ b/sources/FELIG/LinkWrapper/LMK_FELIG_wrapper.vhd
@@ -0,0 +1,131 @@
+--ricardo luz, argonne
+
+library ieee;
+    use ieee.std_logic_1164.all;
+    use work.pcie_package.all;
+    use work.FELIX_package.all;
+    use work.centralRouter_package.all;
+library UNISIM;
+    use UNISIM.VComponents.all;
+
+library xpm;
+    use xpm.vcomponents.all;
+
+entity LMK_FELIG_wrapper is
+    Port (
+        clk40_in                : in std_logic;
+        clk10_xtal              : in std_logic;
+        GT_RXCLK40              : in std_logic;
+        rst_hw                  : in std_logic;
+        LMK_DATA                : out std_logic;
+        LMK_CLK                 : out std_logic;
+        LMK_LE                  : out std_logic;
+        LMK_GOE                 : out std_logic;
+        LMK_LD                  : in std_logic;
+        LMK_SYNCn               : out std_logic;
+        LMK_LOCKED              : out std_logic;
+        RxCdrLock               : in std_logic;
+        alignment_done          : in std_logic;
+        CLK40_FPGA2LMK_out_P    : out std_logic;
+        CLK40_FPGA2LMK_out_N    : out std_logic
+    );
+end LMK_FELIG_wrapper;
+
+architecture Behavioral of LMK_FELIG_wrapper is
+    signal LMK_PIPE                     : std_logic_vector(3 downto 0);
+    signal LMK_RESET                    : std_logic;
+    type STATEM  is (st_idle, st_wait_for_aligment, st_LMK_reseted);
+    signal state                        : STATEM := st_idle;
+    signal LMK_RESET_b                  : std_logic := '0';
+    signal RESET_TO_LMK                 : std_logic;
+    signal RESET_TO_LMK_CLK10           : std_logic;
+begin
+
+    lmk_init : entity work.LMK03200_wrapper
+        generic map(
+            freq => 240)
+        port map(
+            rst_lmk => RESET_TO_LMK_CLK10,--'0',
+            hw_rst => rst_hw,
+            LMK_locked => LMK_LOCKED,
+            clk40m_in => '0',--clk40_rxusrclk,
+            clk10m_in => clk10_xtal,
+            CLK40_FPGA2LMK_P => open,
+            CLK40_FPGA2LMK_N => open,
+            LMK_DATA => LMK_DATA,
+            LMK_CLK => LMK_CLK,
+            LMK_LE => LMK_LE,
+            LMK_GOE => LMK_GOE,
+            LMK_LD => LMK_LD,
+            LMK_SYNCn => LMK_SYNCn);
+
+    xpm_cdc_RESET_LMK : xpm_cdc_single
+        generic map (
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 1
+        )
+        port map (
+            src_clk => clk40_in,
+            src_in => RESET_TO_LMK,
+            dest_clk => clk10_xtal,
+            dest_out => RESET_TO_LMK_CLK10
+        );
+
+    OBUF240_LMK03200: OBUFDS
+        generic map (
+            IOSTANDARD => "LVDS",
+            SLEW       => "FAST")
+        port map(
+            I => GT_RXCLK40,
+            O => CLK40_FPGA2LMK_out_P,
+            OB => CLK40_FPGA2LMK_out_N);
+
+
+    process(clk40_in)
+    begin
+        if (clk40_in'event and clk40_in='1') then
+            LMK_PIPE(3 downto 1) <= LMK_PIPE(2 downto 0);
+            LMK_PIPE(0) <= LMK_RESET_b;
+        end if;
+    end process;
+    LMK_RESET <= LMK_PIPE(0) or LMK_PIPE(1) or LMK_PIPE(2) or LMK_PIPE(3); --this way the pulse is 4 clks long. the lti clock is 10MHz
+    RESET_TO_LMK <= LMK_RESET;
+
+
+    process(clk40_in)
+    begin
+        if (clk40_in'event and clk40_in='1') then
+       sm_lmk_reset: case state is
+                when st_idle =>
+                    LMK_RESET_b <= '0';
+                    if RxCdrLock = '1' then
+                        state <= st_wait_for_aligment;
+                    else
+                        state <= st_idle;
+                    end if;
+                when st_wait_for_aligment =>
+                    if alignment_done = '1'then
+                        LMK_RESET_b <= '1';
+                        state <= st_LMK_reseted;
+                    elsif RxCdrLock = '0' then
+                        LMK_RESET_b <= '0';
+                        state <= st_idle;
+                    else
+                        LMK_RESET_b <= '0';
+                        state <= st_wait_for_aligment;
+                    end if;
+                when st_LMK_reseted =>
+                    LMK_RESET_b <= '0';
+                    if RxCdrLock = '0' and LMK_RESET_b <= '0'then
+                        state <= st_idle;
+                    else
+                        state <= st_LMK_reseted;
+                    end if;
+                when others =>
+                    state <= st_idle;
+            end case sm_lmk_reset;
+        end if;
+    end process;
+end Behavioral;
diff --git a/sources/FELIG/LinkWrapper/link_wrapper_FELIG.vhd b/sources/FELIG/LinkWrapper/link_wrapper_FELIG.vhd
index b23524ba2929e4412ec64615f983640ff825f251..ca8e6fe0ef6d9f7488fc6440825b97df590c4138 100644
--- a/sources/FELIG/LinkWrapper/link_wrapper_FELIG.vhd
+++ b/sources/FELIG/LinkWrapper/link_wrapper_FELIG.vhd
@@ -4,60 +4,70 @@ library ieee;
     use work.pcie_package.all;
     use work.FELIX_package.all;
     use work.centralRouter_package.all;
-
+Library xpm;
+    use xpm.vcomponents.all;
 entity link_wrapper_FELIG is --Modified from link_wrapper by Ricardo Luz rluz@anl.gov
     generic(
-        GBT_NUM : integer := 4; -- number of GBT channels
-        CARD_TYPE : integer := 712;
-        GTHREFCLK_SEL : std_logic := '0'; -- GREFCLK: '1', MGTREFCLK: '0'
-        FIRMWARE_MODE : integer := 0;
-        PLL_SEL : std_logic := '1'; -- 0: CPLL, 1: QPLL
-        GTREFCLKS : integer := 5;
-        OPTO_TRX : integer := 4;  -- number of optical transceivers
-        sim_emulator : boolean := false);
+        GBT_NUM         : integer := 4; -- number of GBT channels
+        CARD_TYPE       : integer := 712;
+        GTHREFCLK_SEL   : std_logic := '0'; -- GREFCLK: '1', MGTREFCLK: '0'
+        FIRMWARE_MODE   : integer := 0;
+        PLL_SEL         : std_logic := '1'; -- 0: CPLL, 1: QPLL
+        GTREFCLKS       : integer := 5;
+        OPTO_TRX        : integer := 4;  -- number of optical transceivers
+        sim_emulator    : boolean := false);
     port (
-        register_map_control : in register_map_control_type;
-        register_map_link_monitor : out register_map_link_monitor_type;
-        clk40 : in std_logic;
-        clk240 : in std_logic;
-        clk40_xtal : in std_logic;
-        GTREFCLK_N_in : in std_logic_vector(GTREFCLKS-1 downto 0);
-        GTREFCLK_P_in : in std_logic_vector(GTREFCLKS-1 downto 0);
-        rst_hw : in  std_logic;
-        OPTO_LOS : in std_logic_vector(OPTO_TRX-1 downto 0);
-        RXUSRCLK_OUT : out std_logic_vector(GBT_NUM-1 downto 0);
-        GBT_DOWNLINK_USER_DATA : in txrx120b_type(0 to (GBT_NUM-1));
-        GBT_UPLINK_USER_DATA : out txrx120b_type(0 to (GBT_NUM-1));
-        lpGBT_DOWNLINK_USER_DATA : in  txrx224b_type(0 to GBT_NUM-1); --RL; FELIG is different from FELIX. It recieves (UPLINK) the txrx32b and it sends (downlink) the txrx224b
-        lpGBT_DOWNLINK_IC_DATA   : in  txrx2b_type(0 to GBT_NUM-1);
-        lpGBT_DOWNLINK_EC_DATA   : in  txrx2b_type(0 to GBT_NUM-1);
-        lpGBT_UPLINK_USER_DATA   : out txrx32b_type(0 to GBT_NUM-1);
-        lpGBT_UPLINK_EC_DATA     : out txrx2b_type(0 to GBT_NUM-1);
-        lpGBT_UPLINK_IC_DATA     : out txrx2b_type(0 to GBT_NUM-1);
-        LinkAligned : out std_logic_vector(GBT_NUM-1 downto 0);
-        TX_P : out std_logic_vector(GBT_NUM-1 downto 0);
-        TX_N : out std_logic_vector(GBT_NUM-1 downto 0);
-        RX_P : in std_logic_vector(GBT_NUM-1 downto 0);
-        RX_N : in std_logic_vector(GBT_NUM-1 downto 0);
-        GTH_FM_RX_33b_out : out txrx33b_type;
-        LMK_P : in std_logic_vector(7 downto 0);
-        LMK_N : in std_logic_vector(7 downto 0);
+        register_map_control        : in register_map_control_type;
+        register_map_link_monitor   : out register_map_link_monitor_type;
+        clk40                       : in std_logic;
+        clk240                      : in std_logic;
+        clk40_xtal                  : in std_logic;
+        GTREFCLK_N_in               : in std_logic_vector(GTREFCLKS-1 downto 0);
+        GTREFCLK_P_in               : in std_logic_vector(GTREFCLKS-1 downto 0);
+        rst_hw                      : in  std_logic;
+        OPTO_LOS                    : in std_logic_vector(OPTO_TRX-1 downto 0);
+        RXUSRCLK_OUT                : out std_logic_vector(GBT_NUM-1 downto 0);
+        GBT_DOWNLINK_USER_DATA      : in txrx120b_type(0 to (GBT_NUM-1));
+        GBT_UPLINK_USER_DATA        : out txrx120b_type(0 to (GBT_NUM-1));
+        lpGBT_DOWNLINK_USER_DATA    : in  txrx224b_type(0 to GBT_NUM-1);
+        lpGBT_DOWNLINK_IC_DATA      : in  txrx2b_type(0 to GBT_NUM-1);
+        lpGBT_DOWNLINK_EC_DATA      : in  txrx2b_type(0 to GBT_NUM-1);
+        data_ready_DOWNLINK         : in std_logic_vector(0 to GBT_NUM-1);
+        lpGBT_UPLINK_USER_DATA      : out txrx32b_type(0 to GBT_NUM-1);
+        lpGBT_UPLINK_EC_DATA        : out txrx2b_type(0 to GBT_NUM-1);
+        lpGBT_UPLINK_IC_DATA        : out txrx2b_type(0 to GBT_NUM-1);
+        LinkAligned                 : out std_logic_vector(GBT_NUM-1 downto 0);
+        TX_P                        : out std_logic_vector(GBT_NUM-1 downto 0);
+        TX_N                        : out std_logic_vector(GBT_NUM-1 downto 0);
+        RX_P                        : in std_logic_vector(GBT_NUM-1 downto 0);
+        RX_N                        : in std_logic_vector(GBT_NUM-1 downto 0);
+        --GTH_FM_RX_33b_out           : out txrx33b_type;
+        LMK_P                       : in std_logic_vector(7 downto 0);
+        LMK_N                       : in std_logic_vector(7 downto 0);
         --FELIG specific signals
-        link_rx_flag_i : out std_logic_vector(GBT_NUM-1 downto 0);
-        link_tx_flag_i : out std_logic_vector(GBT_NUM-1 downto 0);
-        TXUSRCLK_OUT : out std_logic_vector(GBT_NUM-1 downto 0);
-        appreg_clk : in std_logic; --global_appreg_clk
-        CLK40_FPGA2LMK_N : out std_logic;
-        CLK40_FPGA2LMK_P : out std_logic;
-        LMK_LD : in std_logic;
-        RESET_TO_LMK : out std_logic;
-        clk40_rxusrclk : out std_logic;
-        clk320_in: in std_logic; --MT/RL simulation only
-        LINKSconfig : in std_logic_vector(2 downto 0)
+        link_rx_flag_i              : out std_logic_vector(GBT_NUM-1 downto 0);
+        link_tx_flag_i              : out std_logic_vector(GBT_NUM-1 downto 0);
+        TXUSRCLK_OUT                : out std_logic_vector(GBT_NUM-1 downto 0);
+        CLK40_FPGA2LMK_N            : out std_logic;
+        CLK40_FPGA2LMK_P            : out std_logic;
+        --LMK_LD : in std_logic;
+        --RESET_TO_LMK : out std_logic;
+        --clk40_rxusrclk              : out std_logic;
+        clk320_in                   : in std_logic; --MT/RL simulation only
+        clk10_xtal                  : in std_logic;
+        LMK_DATA                    : out std_logic;
+        LMK_CLK                     : out std_logic;
+        LMK_LE                      : out std_logic;
+        LMK_GOE                     : out std_logic;
+        LMK_LD                      : in std_logic;
+        LMK_SYNCn                   : out std_logic;
+        LMK_LOCKED                  : out std_logic
     );
 end entity link_wrapper_FELIG;
-
 architecture rtl of link_wrapper_FELIG is
+    signal GT_RXCLK40                : std_logic := '0';
+    signal alignment_done_to_LMK     : std_logic := '0';
+    signal RxCdrLock_to_LMK          : std_logic := '0';
 begin
 
     --GBT, copied from phase1
@@ -74,46 +84,37 @@ begin
 
         gbt_tx_data_120b_array_i <= GBT_DOWNLINK_USER_DATA;
         GBT_UPLINK_USER_DATA <= gbt_rx_data_120b_array_i;
-
-        u1: entity work.FELIX_gbt_wrapper_FELIGKCU --_sim
+        u1: entity work.FELIX_gbt_wrapper_FELIGKCU
             generic map(
-                STABLE_CLOCK_PERIOD       => 24,
                 GBT_NUM                   => GBT_NUM,
                 CARD_TYPE                 => CARD_TYPE,
                 PLL_SEL                   => PLL_SEL,
                 GTHREFCLK_SEL             => GTHREFCLK_SEL,
                 sim_emulator              => sim_emulator)
             port map(
-                RX_FLAG_O                 => link_rx_flag_i, --MT open,
-                TX_FLAG_O                 => link_tx_flag_i, --MT open,
-                REFCLK_CXP1               => open, --REFCLK_CXP1,RL: not used
-                REFCLK_CXP2               => open,
-                REFCLK_CXP1_LMK            => open, -- added MT/SS for LMK03200
-                REFCLK_CXP2_LMK            => open,
                 rst_hw                    => rst_hw,
                 register_map_control      => register_map_control,
                 register_map_gbt_monitor  => register_map_link_monitor,
-                DRP_CLK_IN                => appreg_clk,
-                Q2_CLK0_GTREFCLK_PAD_N_IN => GTREFCLK_N_in(0), -- copied from phase2 link wrapper Q2_CLK0_GTREFCLK_PAD_N_IN
-                Q2_CLK0_GTREFCLK_PAD_P_IN => GTREFCLK_P_in(0), --Q2_CLK0_GTREFCLK_PAD_P_IN
-                Q8_CLK0_GTREFCLK_PAD_N_IN => GTREFCLK_N_in(1), --Q8_CLK0_GTREFCLK_PAD_N_IN
-                Q8_CLK0_GTREFCLK_PAD_P_IN => GTREFCLK_P_in(1), --Q8_CLK0_GTREFCLK_PAD_P_IN
-                Q4_CLK0_GTREFCLK_PAD_N_IN => GTREFCLK_N_in(2), --Q4_CLK0_GTREFCLK_PAD_N_IN
-                Q4_CLK0_GTREFCLK_PAD_P_IN => GTREFCLK_P_in(2), --Q4_CLK0_GTREFCLK_PAD_P_IN
-                Q5_CLK0_GTREFCLK_PAD_N_IN => GTREFCLK_N_in(3), --Q5_CLK0_GTREFCLK_PAD_N_IN
-                Q5_CLK0_GTREFCLK_PAD_P_IN => GTREFCLK_P_in(3), --Q5_CLK0_GTREFCLK_PAD_P_IN
-                Q6_CLK0_GTREFCLK_PAD_N_IN => GTREFCLK_N_in(4), --Q6_CLK0_GTREFCLK_PAD_N_IN
-                Q6_CLK0_GTREFCLK_PAD_P_IN => GTREFCLK_P_in(4), --Q6_CLK0_GTREFCLK_PAD_P_IN
-                LMK_GTH_REFCLK1_P         => LMK_P(1), --LMK_GTH_REFCLK1_P, -- LMK03200 GTH REF clocks
-                LMK_GTH_REFCLK1_N         => LMK_N(1), --LMK_GTH_REFCLK1_N,
-                LMK_GTH_REFCLK3_P         => LMK_P(3), --LMK_GTH_REFCLK3_P,
-                LMK_GTH_REFCLK3_N         => LMK_N(3), --LMK_GTH_REFCLK3_N,
+                Q2_CLK0_GTREFCLK_PAD_N_IN => GTREFCLK_N_in(0),
+                Q2_CLK0_GTREFCLK_PAD_P_IN => GTREFCLK_P_in(0),
+                Q8_CLK0_GTREFCLK_PAD_N_IN => GTREFCLK_N_in(1),
+                Q8_CLK0_GTREFCLK_PAD_P_IN => GTREFCLK_P_in(1),
+                Q4_CLK0_GTREFCLK_PAD_N_IN => GTREFCLK_N_in(2),
+                Q4_CLK0_GTREFCLK_PAD_P_IN => GTREFCLK_P_in(2),
+                Q5_CLK0_GTREFCLK_PAD_N_IN => GTREFCLK_N_in(3),
+                Q5_CLK0_GTREFCLK_PAD_P_IN => GTREFCLK_P_in(3),
+                Q6_CLK0_GTREFCLK_PAD_N_IN => GTREFCLK_N_in(4),
+                Q6_CLK0_GTREFCLK_PAD_P_IN => GTREFCLK_P_in(4),
+                LMK_GTH_REFCLK1_P         => LMK_P(1),
+                LMK_GTH_REFCLK1_N         => LMK_N(1),
+                LMK_GTH_REFCLK3_P         => LMK_P(3),
+                LMK_GTH_REFCLK3_N         => LMK_N(3),
                 GREFCLK_IN                => clk240,
                 clk40_in                  => clk40,
                 clk240_in                 => clk240,
-                TX_120b_in                => gbt_tx_data_120b_array_i, --MT TX_120b_in_combined,
-                RX_120b_out               => gbt_rx_data_120b_array_i, --MT RX_120b_out,
-                FRAME_LOCKED_O            => LinkAligned,  --MT route this lane_monitor.gbt.frame_locked as John does?
+                TX_120b_in                => gbt_tx_data_120b_array_i,
+                RX_120b_out               => gbt_rx_data_120b_array_i,
+                FRAME_LOCKED_O            => LinkAligned,
                 TX_FRAME_CLK_I            => TX_FRAME_CLK_I,
                 GT_TXUSRCLK_OUT           => TXUSRCLK_OUT,
                 GT_RXUSRCLK_OUT           => RXUSRCLK_OUT,
@@ -121,11 +122,12 @@ begin
                 TX_N                      => TX_N,
                 RX_P                      => RX_P,
                 RX_N                      => RX_N,
-                CLK40_FPGA2LMK_out_P      => CLK40_FPGA2LMK_P, -- LMK03200 clock input pins added --MT/SS
-                CLK40_FPGA2LMK_out_N      => CLK40_FPGA2LMK_N, -- LMK03200 clock input pins added --MT/SS
+                RX_FLAG_O                 => link_rx_flag_i,
+                TX_FLAG_O                 => link_tx_flag_i,
                 LMK_LD                    => LMK_LD,
-                RESET_TO_LMK              => RESET_TO_LMK
-            --
+                GT_RXCLK40                => GT_RXCLK40,
+                alignment_done_to_LMK     => alignment_done_to_LMK,
+                RxCdrLock_to_LMK          => RxCdrLock_to_LMK
             );
 
 
@@ -139,7 +141,6 @@ begin
         signal RX_2b_IC_out                : txrx2b_type(0 to GBT_NUM-1);
         signal RX_2b_EC_out                : txrx2b_type(0 to GBT_NUM-1);
         signal RX_32b_DATA_out             : txrx32b_type(0 to GBT_NUM-1);
-        signal clk40_rxusrclk_lp           : std_logic;
     begin
 
         TX_2b_IC_in              <= lpGBT_DOWNLINK_IC_DATA;
@@ -148,8 +149,6 @@ begin
         lpGBT_UPLINK_IC_DATA     <= RX_2b_IC_out;
         lpGBT_UPLINK_EC_DATA     <= RX_2b_EC_out;
         lpGBT_UPLINK_USER_DATA   <= RX_32b_DATA_out;
-        clk40_rxusrclk           <= clk40_rxusrclk_lp;
-
         u2: entity work.FELIX_LpGBT_Wrapper_FELIG
             generic map(       STABLE_CLOCK_PERIOD => 24,
                 GBT_NUM                   => GBT_NUM,
@@ -162,39 +161,61 @@ begin
             port map(
                 rst_hw                    => rst_hw,
                 rxrecclk40m_out           => open,
-                register_map_control      => register_map_control, --RL changed to match module
+                register_map_control      => register_map_control,
                 register_map_link_monitor => register_map_link_monitor,
                 CLK40_IN                  => clk40,
-                clk320_in                 => clk320_in, --MT SIMU+
-                GREFCLK_IN                => clk240, --MT comment: it is not connected anywhere other than simu (added by me)
-                RX320_CH0                 => open,
-                GTREFCLK_P_s              => GTREFCLK_P_in,--GTREFCLK_P_s,
-                GTREFCLK_N_s              => GTREFCLK_N_in,--GTREFCLK_N_s,
+                clk320_in                 => clk320_in,
+                GREFCLK_IN                => clk240,
+                GTREFCLK_P_s              => GTREFCLK_P_in,
+                GTREFCLK_N_s              => GTREFCLK_N_in,
                 LMK_P                     => LMK_P,
                 LMK_N                     => LMK_N,
                 RX_LINK_LCK               => open,
-                TX_2b_IC_in               => TX_2b_IC_in, --RL: TX_256b_in divided into components
+                TX_2b_IC_in               => TX_2b_IC_in,
                 TX_2b_EC_in               => TX_2b_EC_in,
                 TX_224b_DATA_in           => TX_224b_DATA_in,
-                RX_2b_IC_out              => RX_2b_IC_out,  --RL: RX_36b_out divided into components
+                TX_ready_in               => data_ready_DOWNLINK,
+                RX_2b_IC_out              => RX_2b_IC_out,
                 RX_2b_EC_out              => RX_2b_EC_out,
                 RX_32b_DATA_out           => RX_32b_DATA_out,
-                GT_TXUSRCLK_OUT           => TXUSRCLK_OUT, --gt_txusrclk_i,
-                GT_RXUSRCLK_OUT           => RXUSRCLK_OUT, --gt_rxusrclk_i,
-                clk40_rxusrclk_out        => clk40_rxusrclk_lp, --MT 40 MHZ rxusr clk to drive LMK
+                GT_TXUSRCLK_OUT           => TXUSRCLK_OUT,
+                GT_RXUSRCLK_OUT           => RXUSRCLK_OUT,
                 TX_P                      => TX_P,
                 TX_N                      => TX_N,
                 RX_P                      => RX_P,
                 RX_N                      => RX_N,
-                sta_headerFlag_out        => link_rx_flag_i,--lpgbt_rx_flag_i --MT for FELIG from mgt_framealigner . 1 pulse every c_wordRatio (=8)
-                tx_flag_out               => link_tx_flag_i,--lpgbt_tx_flag_i --MT added: needed by FELIG to latch tx payload to generated data. Need to be synchronized with emulator logic
-                alignment_done_out        => LinkAligned, --MT added: alignment flag needed by the emulator,
-                RESET_TO_LMK              => RESET_TO_LMK, --MT added
-                LMK_LD                    => LMK_LD, --MT LMK lock signal
-                LINKSconfig               => LINKSconfig, --RL added
-                CLK40_FPGA2LMK_out_P      => CLK40_FPGA2LMK_P, -- LMK03200 clock input pins added --MT/SS/RL
-                CLK40_FPGA2LMK_out_N      => CLK40_FPGA2LMK_N  -- LMK03200 clock input pins added --MT/SS/RL
+                sta_headerFlag_out        => link_rx_flag_i,
+                tx_flag_out               => link_tx_flag_i,
+                alignment_done_out        => LinkAligned,
+                LMK_LD                    => LMK_LD,
+                GT_RXCLK40                => GT_RXCLK40,
+                alignment_done_to_LMK     => alignment_done_to_LMK,
+                RxCdrLock_to_LMK          => RxCdrLock_to_LMK
             );
+
+
     end generate g_lpGBTMODE;
+
+    LMK : entity work.LMK_FELIG_wrapper
+        port map(
+            clk40_in                => clk40,
+            clk10_xtal              => clk10_xtal,
+            GT_RXCLK40              => GT_RXCLK40,
+            rst_hw                  => rst_hw,
+            LMK_DATA                => LMK_DATA,
+            LMK_CLK                 => LMK_CLK,
+            LMK_LE                  => LMK_LE,
+            LMK_GOE                 => LMK_GOE,
+            LMK_LD                  => LMK_LD,
+            LMK_SYNCn               => LMK_SYNCn,
+            LMK_LOCKED              => LMK_LOCKED,
+            RxCdrLock               => RxCdrLock_to_LMK,
+            alignment_done          => alignment_done_to_LMK,
+            CLK40_FPGA2LMK_out_P    => CLK40_FPGA2LMK_P,
+            CLK40_FPGA2LMK_out_N    => CLK40_FPGA2LMK_N
+        );
+
+
 end architecture rtl ; -- of link_wrapper_FELIG
 
+
diff --git a/sources/FELIG/PRandomDGen/randomd_gen.vhd b/sources/FELIG/PRandomDGen/randomd_gen.vhd
index a8023164d7020c859741a8aa7fe65a1df86087e5..1a3ec78789de0707ff344086224b14b09d73e013 100644
--- a/sources/FELIG/PRandomDGen/randomd_gen.vhd
+++ b/sources/FELIG/PRandomDGen/randomd_gen.vhd
@@ -30,7 +30,8 @@ library ieee, UNISIM;
     use ieee.numeric_std_unsigned.all;
     use ieee.std_logic_1164.all;
     use work.pcie_package.all;
-
+Library xpm;
+    use xpm.vcomponents.all;
 entity Random_gen is
     generic (
         LANE_ID              : integer := 0
@@ -88,8 +89,34 @@ architecture rtl of Random_gen is
 
 begin
     ---- %%%%%%% for test only
-    rG_POLY <= FMEMU_RANDOM_CONTROL.POLYNOMIAL; --MT register_map_control.FMEMU_RANDOM_CONTROL.POLYNOMIAL;
-    rSeed <= FMEMU_RANDOM_CONTROL.SEED; --MT register_map_control.FMEMU_RANDOM_CONTROL.SEED;
+    --rG_POLY <= FMEMU_RANDOM_CONTROL.POLYNOMIAL; --MT register_map_control.FMEMU_RANDOM_CONTROL.POLYNOMIAL;
+    --rSeed <= FMEMU_RANDOM_CONTROL.SEED; --MT register_map_control.FMEMU_RANDOM_CONTROL.SEED;
+    xpm_rG_POLY : xpm_cdc_array_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0,
+            WIDTH => 10
+        )
+        port map(
+            src_clk => '0',
+            src_in => FMEMU_RANDOM_CONTROL.POLYNOMIAL,
+            dest_clk => clk,
+            dest_out => rG_POLY
+        );
+    xpm_rSeed : xpm_cdc_array_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0,
+            WIDTH => 10
+        )
+        port map(
+            src_clk => '0',
+            src_in => FMEMU_RANDOM_CONTROL.SEED,
+            dest_clk => clk,
+            dest_out => rSeed
+        );
     --  random_rst <= register_map_control.GEN_FM_CONTROL1.PACKAGE_LENGTH(15);
     ----%%%%%%%% write LUT
     rg_addra   <= FMEMU_RANDOM_RAM_ADDR; --MT register_map_control.FMEMU_RANDOM_RAM_ADDR;
diff --git a/sources/FELIG/data_generator/elink_data_emulator.vhd b/sources/FELIG/data_generator/elink_data_emulator.vhd
index 1b7cd6515de890192d88bcdc3440841dd56391a9..e6722a4aae877e2a0a80ed739d950c296bcf0e81 100644
--- a/sources/FELIG/data_generator/elink_data_emulator.vhd
+++ b/sources/FELIG/data_generator/elink_data_emulator.vhd
@@ -38,189 +38,256 @@
 
 library IEEE;
     use IEEE.STD_LOGIC_1164.ALL;
-    --MT
     use ieee.numeric_std.all;
     use ieee.numeric_std_unsigned.all;
-    --
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
 
     use work.type_lib.ALL;
-
     use work.centralRouter_package.all;
-
---Frans 1
     use work.pcie_package.all;
+
+Library xpm;
+    use xpm.vcomponents.all;
+
 entity elink_data_emulator is
     generic (
-        epath        : std_logic_vector (4 downto 0);
-        egroup        : std_logic_vector (2 downto 0);
-        --Frans 2
-        LANE_ID             : integer := 0
+        epath           : std_logic_vector (4 downto 0);
+        egroup          : std_logic_vector (2 downto 0);
+        LANE_ID         : integer := 0;
+        PROTOCOL        : std_logic := '0'
     );
     port (
-        clk40        : in STD_LOGIC;
-        --        clk240        : in STD_LOGIC;
-        clk            : in STD_LOGIC;
-        emu_control      : in lane_emulator_control;
-        elink_data_out    : out STD_LOGIC_VECTOR (9 downto 0);
-        elink_data_re    : in  std_logic;
-        l1a_trig      : in STD_LOGIC;
-        l1a_id        : in STD_LOGIC_VECTOR (15 downto 0);
+        clk40               : in STD_LOGIC;
+        clk                 : in STD_LOGIC;
+        emu_control         : in lane_emulator_control;
+        elink_data_out      : out STD_LOGIC_VECTOR (9 downto 0);
+        elink_data_re       : in  std_logic;
+        l1a_trig            : in STD_LOGIC;
+        l1a_id              : in STD_LOGIC_VECTOR (15 downto 0);
         flag_data_gen       : out std_logic; --RL added to be used to sync the read enables
-        ila_data_gen_out  : out std_logic_vector (17 downto 0);
-        ila_fifo_out    : out std_logic_vector ( 9 downto 0);
-        ila_data_gen_we    : out std_logic;
-        --MT checker upstream fifo
-        ila_count_upstfifochk   : out std_logic_vector(10 downto 0);
-        ila_fifo_flush          : out std_logic;
-        --MT
-        ila_count_chk_out       : out std_logic_vector(10 downto 0);
-        ila_count_chk_out2      : out std_logic_vector(10 downto 0);
-        ila_isEOP_chk2          : out std_logic;
-        ila_efifoDout_8b10b     : out std_logic_vector(9 downto 0);
-        ila_enc10bitRdy         : out std_logic;
-
-        ila_efifoFull : out std_logic;
-        ila_efifoEmpty : out std_logic;
-        ila_efifoPfull : out std_logic;
-        ila_elink_data_re : out std_logic;
-        ila_efifoDoutRdy : out std_logic;
-        --Frans 1
-        SELECT_RANDOM : in std_logic_vector(0 downto 0);
-        chunk_length_out : out std_logic_vector(11 downto 0)        ;
-        --
-        --MT 2 (Fran 2)
-        FMEMU_RANDOM_RAM_ADDR          : in std_logic_vector(9 downto 0);    -- Controls the address of the ramblock for the random number generator
-        FMEMU_RANDOM_RAM               : in bitfield_fmemu_random_ram_t_type;
-        FMEMU_RANDOM_CONTROL           : in bitfield_fmemu_random_control_w_type;
-        aurora_en                      : out std_logic
-    --SS (SWAP LSB MSB)
-    --fhCR_REVERSE_10B               : in  std_logic
+        fmemu_random        : in lane_emu_random_control;
+        chunk_length_out    : out std_logic_vector(11 downto 0)
     );
 end entity elink_data_emulator;
 
 architecture Behavioral of elink_data_emulator is
-    signal elinkdata_o    : std_logic_vector(17 downto 0); -- 18 bit input to the elinkinterface
-    signal elinkdata_rdy_o  : std_logic;
-
+    signal elinkdata_o          : std_logic_vector(17 downto 0); -- 18 bit input to the elinkinterface
+    signal elinkdata_rdy_o      : std_logic;
     --RC outputs of the NSW packet gen:
-    signal elinkdata_o_nsw    : std_logic_vector(17 downto 0); -- 18 bit input to the elinkinterface
+    signal elinkdata_o_nsw      : std_logic_vector(17 downto 0); -- 18 bit input to the elinkinterface
     signal elinkdata_rdy_o_nsw  : std_logic;
-
-
     --RC outputs of the default elink packet gen:
-    signal elinkdata_o_def    : std_logic_vector(17 downto 0); -- 18 bit input to the elinkinterface
+    signal elinkdata_o_def      : std_logic_vector(17 downto 0); -- 18 bit input to the elinkinterface
     signal elinkdata_rdy_o_def  : std_logic;
-
-
-    signal elink_tx_rst    : std_logic;
-    signal fifo_flush    : std_logic;
-    signal efifoPfull    : std_logic;
-
-    signal efifoDoutRdy, efifoFull, efifoEmpty : std_logic := '0';
-    signal EDATA_OUT : std_logic_vector(9 downto 0) := (others => '0');
-    signal efifoDout_8b10b: std_logic_vector(9 downto 0) := (others => '0');
-    signal enc10bit : std_logic_vector (9 downto 0);
-    signal enc10bitRdy : std_logic;
-
-    --Frans 1
-    signal chunk_length : std_logic_vector(11 downto 0);
-    --Frans 2
-    signal chunk_length_trig: std_logic;
-    signal random_chunk_length : std_logic_vector(15 downto 0);
+    signal elink_tx_rst         : std_logic;
+    signal fifo_flush           : std_logic;
+    signal efifoPfull           : std_logic;
+    signal efifoDoutRdy         : std_logic := '0';
+    signal efifoFull            : std_logic := '0';
+    signal efifoEmpty           : std_logic := '0';
+    signal EDATA_OUT            : std_logic_vector(9 downto 0) := (others => '0');
+    signal efifoDout_8b10b      : std_logic_vector(9 downto 0) := (others => '0');
+    signal enc10bit             : std_logic_vector (9 downto 0);
+    signal enc10bitRdy          : std_logic;
+    signal chunk_length         : std_logic_vector(11 downto 0);
+    signal chunk_length_trig    : std_logic;
+    signal random_chunk_length  : std_logic_vector(15 downto 0);
     --RC outputs of each generator:
     signal chunk_length_trig_nsw: std_logic;
     signal chunk_length_trig_def: std_logic;
-
-
     --MT checker
-    signal rst_chk : std_logic:= '0';
-    signal datacode_chk : std_logic_vector(1 downto 0) := (others => '0');
-    signal data_chk : std_logic_vector(15 downto 0) := (others => '0');
-    signal valid_chk : std_logic := '0';
-    signal count_chk : std_logic_vector(10 downto 0) := (others => '0');
+    signal rst_chk              : std_logic:= '0';
+    signal datacode_chk         : std_logic_vector(1 downto 0) := (others => '0');
+    signal data_chk             : std_logic_vector(15 downto 0) := (others => '0');
+    signal valid_chk            : std_logic := '0';
+    signal count_chk            : std_logic_vector(10 downto 0) := (others => '0');
     type STCHK  is (st_idl, st_start, st_count) ;
-    signal state_chk : STCHK := st_idl;
-    signal err_chk : std_logic := '0';
+    signal state_chk            : STCHK := st_idl;
+    signal err_chk              : std_logic := '0';
     --upstreamEpathFifoWrap
-    signal count_fifochk : std_logic_vector(15 downto 0) := (others => '0');
+    signal count_fifochk        : std_logic_vector(15 downto 0) := (others => '0');
     --MT checker upstream fifo
-    signal data_upstfifochk : std_logic_vector(9 downto 0) := (others => '0');
-    signal valid_upstfifochk : std_logic := '0';
-    signal count_upstfifochk : std_logic_vector(10 downto 0) := (others => '0');
-    signal state_upstfifochk : STCHK := st_idl;
-    signal err_upstfifochk : std_logic := '0';
+    signal data_upstfifochk     : std_logic_vector(9 downto 0) := (others => '0');
+    signal valid_upstfifochk    : std_logic := '0';
+    signal count_upstfifochk    : std_logic_vector(10 downto 0) := (others => '0');
+    signal state_upstfifochk    : STCHK := st_idl;
+    signal err_upstfifochk      : std_logic := '0';
     --MT checker2
-    signal rst_chk2 : std_logic:= '0';
-    signal data_chk2 : std_logic_vector(9 downto 0) := (others => '0');
-    signal count_chk2 : std_logic_vector(10 downto 0) := (others => '0');
-    signal state_chk2 : STCHK := st_idl;
-    signal err_chk2 : std_logic := '0';
-    signal isEOP_chk2 : std_logic := '0';
-    signal valid_chk2 : std_logic := '0';
-
+    signal rst_chk2             : std_logic:= '0';
+    signal data_chk2            : std_logic_vector(9 downto 0) := (others => '0');
+    signal count_chk2           : std_logic_vector(10 downto 0) := (others => '0');
+    signal state_chk2           : STCHK := st_idl;
+    signal err_chk2             : std_logic := '0';
+    signal isEOP_chk2           : std_logic := '0';
+    signal valid_chk2           : std_logic := '0';
     --signal aurora_std           : std_logic := '0';
-    signal elink_data_re_final      : std_logic := '0';
-    signal elink_data_re_aurora     : std_logic := '0';
-    signal elink_data_out_pre       : std_logic_vector(9 downto 0) := (others => '0');
-    signal elink_data_out_aurora    : std_logic_vector(9 downto 0) := (others => '0');
-    signal elink_data_out_aurora_b  : std_logic_vector(9 downto 0) := (others => '0');
+    signal elink_data_re_final  : std_logic := '0';
+    --    signal elink_data_re_aurora     : std_logic := '0';
+    --    signal elink_data_out_pre       : std_logic_vector(9 downto 0) := (others => '0');
+    --    signal elink_data_out_aurora    : std_logic_vector(9 downto 0) := (others => '0');
+    --    signal elink_data_out_aurora_b  : std_logic_vector(9 downto 0) := (others => '0');
+    signal ec_reset             : std_logic;
+    signal ec_output_width      : std_logic_vector(2 downto 0);
+    signal ec_pattern_select    : std_logic_vector(1 downto 0);
+    signal ec_userdata          : std_logic_vector(15 downto 0);
+    signal ec_sw_busy           : std_logic;
+    signal ec_nsw_even_parity   : std_logic;
+    signal ec_pack_gen_select   : std_logic;
+    signal ec_chunk_length      : std_logic_vector(15 downto 0);
+    signal ec_data_format       : std_logic_vector(1 downto 0);
+    signal select_random        : std_logic;
 
 begin
-    ila_data_gen_out  <= elinkdata_o;
-    ila_fifo_out    <= EDATA_OUT;
-    ila_data_gen_we    <= elinkdata_rdy_o;
 
-    --MT
-    ila_efifoFull           <= efifoFull;
-    ila_efifoEmpty          <= efifoEmpty;
-    ila_efifoPfull          <= efifoPfull;
-    ila_elink_data_re       <= elink_data_re;
-    ila_efifoDoutRdy        <= efifoDoutRdy;
+    xpm_reset : xpm_cdc_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0
+        )
+        port map(
+            src_clk => '0',
+            src_in => emu_control.reset,
+            dest_clk => clk,
+            dest_out => ec_reset
+        );
 
-    --MT checker upstream fifo
-    ila_count_upstfifochk <= count_upstfifochk;
-    ila_fifo_flush <= fifo_flush;
-
-    --MT
-    ila_count_chk_out       <= count_chk;
-    ila_count_chk_out2      <= count_chk2;
-    ila_isEOP_chk2          <= isEOP_chk2;
-    ila_efifoDout_8b10b     <= efifoDout_8b10b;
-    ila_enc10bitRdy         <= enc10bitRdy;
-    --
-
-    --RC: added NSW packet generator & muxes
-    nsw_data_gen : entity work.nsw_packet_generator
-        generic map (
-            epath      => epath,
-            egroup      => egroup
+    xpm_output_width : xpm_cdc_array_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0,
+            WIDTH => 3
         )
-        port map (
-            clk_i      => clk, --clk240,
-            rst_i      => emu_control.reset,
-            ewidth      => emu_control.output_width,
-            pattern_sel_i  => emu_control.pattern_select,
-            userdata_i    => emu_control.userdata,
-            chunk_length_i  => chunk_length, --Frans 1 emu_control.chunk_length(11 downto 0),  -- length of packet in bytes, 12bits = 4kBytes
-            sw_busy_i    => emu_control.sw_busy,
-            elinkdata_o    => elinkdata_o_nsw,          -- 18bit = 2bit datacode & 16bit data
-            l1trigger_i    => l1a_trig,          -- L1 trigger
-            l1a_id      => l1a_id,
-            elinkdata_rdy_o  => elinkdata_rdy_o_nsw,
-            --Frans 2
-            chunk_length_trig_o => chunk_length_trig_nsw,
-            even_parity_i   => emu_control.nsw_even_parity
+        port map(
+            src_clk => '0',
+            src_in => emu_control.output_width,
+            dest_clk => clk,
+            dest_out => ec_output_width
         );
 
+    xpm_pattern_select : xpm_cdc_array_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0,
+            WIDTH => 2
+        )
+        port map(
+            src_clk => '0',
+            src_in => emu_control.pattern_select,
+            dest_clk => clk,
+            dest_out => ec_pattern_select
+        );
+
+    xpm_userdata : xpm_cdc_array_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0,
+            WIDTH => 16
+        )
+        port map(
+            src_clk => '0',
+            src_in => emu_control.userdata,
+            dest_clk => clk,
+            dest_out => ec_userdata
+        );
+
+    xpm_sw_busy : xpm_cdc_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0
+        )
+        port map(
+            src_clk => '0',
+            src_in => emu_control.sw_busy,
+            dest_clk => clk,
+            dest_out => ec_sw_busy
+        );
+
+    xpm_nsw_even_parity : xpm_cdc_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0
+        )
+        port map(
+            src_clk => '0',
+            src_in => emu_control.nsw_even_parity,
+            dest_clk => clk,
+            dest_out => ec_nsw_even_parity
+        );
+
+    xpm_pack_gen_select : xpm_cdc_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0
+        )
+        port map(
+            src_clk => '0',
+            src_in => emu_control.pack_gen_select,
+            dest_clk => clk,
+            dest_out => ec_pack_gen_select
+        );
+
+    xpm_chunk_length : xpm_cdc_array_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0,
+            WIDTH => 16
+        )
+        port map(
+            src_clk => '0',
+            src_in => emu_control.chunk_length,
+            dest_clk => clk,
+            dest_out => ec_chunk_length
+        );
+
+    xpm_data_format : xpm_cdc_array_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0,
+            WIDTH => 2
+        )
+        port map(
+            src_clk => '0',
+            src_in => emu_control.data_format,
+            dest_clk => clk,
+            dest_out => ec_data_format
+        );
+
+    g_GBT: if PROTOCOL = '0' generate
+        --RC: added NSW packet generator & muxes
+        nsw_data_gen : entity work.nsw_packet_generator --FLX-1454
+            generic map (
+                epath      => epath,
+                egroup      => egroup
+            )
+            port map (
+                clk_i               => clk, --clk240,
+                rst_i               => ec_reset,
+                ewidth              => ec_output_width,
+                pattern_sel_i       => ec_pattern_select,
+                userdata_i          => ec_userdata,
+                chunk_length_i      => chunk_length, --Frans 1 emu_control.chunk_length(11 downto 0),  -- length of packet in bytes, 12bits = 4kBytes
+                sw_busy_i           => ec_sw_busy,
+                elinkdata_o         => elinkdata_o_nsw,-- 18bit = 2bit datacode & 16bit data
+                l1trigger_i         => l1a_trig,-- L1 trigger
+                l1a_id              => l1a_id,
+                elinkdata_rdy_o     => elinkdata_rdy_o_nsw,
+                chunk_length_trig_o => chunk_length_trig_nsw,
+                even_parity_i       => ec_nsw_even_parity
+            );
+    end generate;
+
+    g_lpGBT: if PROTOCOL = '1' generate
+        elinkdata_o_nsw     <= (others => '0');
+        elinkdata_rdy_o_nsw <= '0';
+    end generate;
 
     def_data_gen : entity work.elink_packet_generator
         generic map (
@@ -228,100 +295,84 @@ begin
             egroup      => egroup
         )
         port map (
-            clk_i      => clk, --clk240,
-            rst_i      => emu_control.reset,
-            ewidth      => emu_control.output_width,
-            pattern_sel_i  => emu_control.pattern_select,
-            userdata_i    => emu_control.userdata,
-            chunk_length_i  => chunk_length, --Frans 1 emu_control.chunk_length(11 downto 0),  -- length of packet in bytes, 12bits = 4kBytes
-            sw_busy_i    => emu_control.sw_busy,
-            elinkdata_o    => elinkdata_o_def,          -- 18bit = 2bit datacode & 16bit data
-            l1trigger_i    => l1a_trig,          -- L1 trigger
-            l1a_id      => l1a_id,
-            elinkdata_rdy_o  => elinkdata_rdy_o_def,
-            --Frans 2
+            clk_i               => clk, --clk240,
+            rst_i               => ec_reset,
+            ewidth              => ec_output_width,
+            pattern_sel_i       => ec_pattern_select,
+            userdata_i          => ec_userdata,
+            chunk_length_i      => chunk_length, --Frans 1 emu_control.chunk_length(11 downto 0),  -- length of packet in bytes, 12bits = 4kBytes
+            sw_busy_i           => ec_sw_busy,
+            elinkdata_o         => elinkdata_o_def,          -- 18bit = 2bit datacode & 16bit data
+            l1trigger_i         => l1a_trig,          -- L1 trigger
+            l1a_id              => l1a_id,
+            elinkdata_rdy_o     => elinkdata_rdy_o_def,
             chunk_length_trig_o => chunk_length_trig_def
         );
 
-    elinkdata_o <= elinkdata_o_nsw when (emu_control.pack_gen_select = '1')  else
+    elinkdata_o <= elinkdata_o_nsw when (ec_pack_gen_select = '1')  else
                    elinkdata_o_def;
 
-    elinkdata_rdy_o <= elinkdata_rdy_o_nsw when (emu_control.pack_gen_select = '1') else
+    elinkdata_rdy_o <= elinkdata_rdy_o_nsw when (ec_pack_gen_select = '1') else
                        elinkdata_rdy_o_def;
 
-    chunk_length_trig <= chunk_length_trig_nsw when (emu_control.pack_gen_select = '1') else
+    chunk_length_trig <= chunk_length_trig_nsw when (ec_pack_gen_select = '1') else
                          chunk_length_trig_def;
 
-    --Frans 1
-
-    --chunkLengthSel: process(register_map_control_40xtal, emu_control) --, random_chunk_length)
-    --begin
-    --   if register_map_control_40xtal.FMEMU_RANDOM_CONTROL.SELECT_RANDOM = "0" then
-    --      chunk_length <= emu_control.chunk_length(11 downto 0);
-    --   else
-    --      chunk_length <= X"01A"; --random_chunk_length(11 downto 0);
-    --   end if;
-    --end process;
-    --
-    --    chunk_length <= emu_control.chunk_length(11 downto 0) when (SELECT_RANDOM = "0") else
-    --                    X"01A";
-
     chunk_length_out <= chunk_length;
 
-    --Frans 2
-    chunk_length <= emu_control.chunk_length(11 downto 0) when (SELECT_RANDOM = "0") else
-                    random_chunk_length(11 downto 0);
+    xpm_select_random : xpm_cdc_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0
+        )
+        port map(
+            src_clk => '0',
+            src_in => fmemu_random.SELECT_RANDOM(0),
+            dest_clk => clk,
+            dest_out => select_random
+        );
 
+    chunk_length <= ec_chunk_length(11 downto 0) when (select_random = '0') else
+                    random_chunk_length(11 downto 0);
 
     random_gen0: entity work.Random_gen
         generic map(
             LANE_ID  => LANE_ID
         )
         port map(
-            rst                  => elink_tx_rst,--: in     std_logic;
-            clk40                => clk40,--: in     std_logic;
-            --        clk240               => clk240,--: in     std_logic;
-            clk                  => clk,--: in     std_logic;
-            --        register_map_control => register_map_control_40xtal,--: in     register_map_control_type;
-            rg_rst               => elink_tx_rst,--: in     std_logic;
-            rg_enb               => chunk_length_trig,--: in     std_logic;
-            rg_doutb             => random_chunk_length, --: out    std_logic_vector(15 downto 0)
-            --MT 2 (Fran 2)
-            FMEMU_RANDOM_RAM_ADDR          => FMEMU_RANDOM_RAM_ADDR ,
-            FMEMU_RANDOM_RAM               => FMEMU_RANDOM_RAM      ,
-            FMEMU_RANDOM_CONTROL           => FMEMU_RANDOM_CONTROL
+            rst                     => elink_tx_rst,
+            clk40                   => clk40,
+            clk                     => clk,
+            rg_rst                  => elink_tx_rst,
+            rg_enb                  => chunk_length_trig,
+            rg_doutb                => random_chunk_length,
+            FMEMU_RANDOM_RAM_ADDR   => fmemu_random.FMEMU_RANDOM_RAM_ADDR ,
+            FMEMU_RANDOM_RAM        => fmemu_random.FMEMU_RANDOM_RAM      ,
+            FMEMU_RANDOM_CONTROL    => fmemu_random.FMEMU_RANDOM_CONTROL
         );
-    --
-
 
-    --MT checker
-    --datacode: elinkdata_o(17 downto 16)
-    --data:  elinkdata_o(15 downto 0)
-    --valid  elinkdata_rdy_o
-    rst_chk <= emu_control.reset;
+    rst_chk <= ec_reset;
     datacode_chk <= elinkdata_o(17 downto 16);
     data_chk <= elinkdata_o(15 downto 0);
     valid_chk <= elinkdata_rdy_o;
-    --        checker: process (clk240, rst_chk)
+
     checker: process (clk, rst_chk)
     begin
         if rst_chk = '1' then
             state_chk <= st_idl;
             count_chk <= (others => '0');
             err_chk <= '0';
-        --          elsif clk240'event and clk240='1' then
         elsif clk'event and clk='1' then
             if valid_chk = '1' then
               sm_checker: case state_chk is
                     when st_idl =>
                         count_chk <= (others => '0');
                         err_chk <= '0';
-                        --                  if data_chk = X"AA00" and datacode_chk = "10" then
                         if datacode_chk = "10" then
                             state_chk <= st_start;
                         end if;
                     when st_start =>
-                        --                  if data_chk = X"0000" and datacode_chk = "01" then
                         if datacode_chk = "01" then
                             state_chk <= st_idl;
                             count_chk <= (others => '0');
@@ -346,39 +397,30 @@ begin
         end if;
     end process;
 
-    ------------------------------------------------------------
     -- EPATH_FIFO
-    ------------------------------------------------------------
     UEF_IN : entity work.upstreamEpathFifoWrap_felig
         port map(
             bitCLK    => '0',
             rst      => elink_tx_rst,
             fifoFLUSH  => fifo_flush,
-            --    clk      => clk240,
             clk      => clk,
-            ---
             wr_en    => elinkdata_rdy_o,
             din      => elinkdata_o,
-            ---
             rd_en    => elink_data_re_final,--elink_data_re,
             dout    => EDATA_OUT,
             doutRdy    => efifoDoutRdy,
-            ---
             full    => efifoFull,
             empty    => efifoEmpty,
             prog_full  => efifoPfull
         );
-    elink_data_re_final <= elink_data_re_aurora  when (emu_control.data_format = "10") else
-                           elink_data_re;
+    --    elink_data_re_final <= elink_data_re_aurora  when (ec_data_format = "10") else
+    --                           elink_data_re;
+    elink_data_re_final <= elink_data_re;
 
-
-    --MT count data in the fifo
-    --        fifochk: process (clk240, elink_tx_rst, fifo_flush)
     fifochk: process (clk, elink_tx_rst, fifo_flush)
     begin
         if elink_tx_rst = '1' or fifo_flush = '1' then
             count_fifochk <= (others => '0');
-        --          elsif clk240'event and clk240='1' then
         elsif clk'event and clk='1' then
             if elinkdata_rdy_o = '1' and elink_data_re_final = '1' then
                 count_fifochk <= count_fifochk; --+1 -1
@@ -391,19 +433,14 @@ begin
             end if;
         end if;
     end process;
-    --
 
-    --MT
-    --MT checker upstream fifo
     data_upstfifochk <= EDATA_OUT;
     valid_upstfifochk <= efifoDoutRdy;
-    --        checker_upstfifo: process (clk240, elink_tx_rst, fifo_flush)
     checker_upstfifo: process (clk, elink_tx_rst, fifo_flush)
     begin
         if elink_tx_rst = '1' or fifo_flush = '1' then
             count_upstfifochk <= (others => '0');
             err_upstfifochk <= '0';
-        --          elsif clk240'event and clk240='1' then
         elsif clk'event and clk='1' then
             if valid_upstfifochk = '1' then
               fifo_checker: case state_upstfifochk is
@@ -438,12 +475,11 @@ begin
         end if;
     end process;
 
-    --  elink_data_out_pre <= efifoDout_8b10b when (emu_control.data_format = "01") else EDATA_OUT;
-    elink_data_out <= EDATA_OUT               when (emu_control.data_format = "00") else
-                      efifoDout_8b10b         when (emu_control.data_format = "01") else
-                      elink_data_out_aurora   when (emu_control.data_format = "10");
+    elink_data_out <= EDATA_OUT               when (ec_data_format = "00") else
+                      efifoDout_8b10b         when (ec_data_format = "01");-- else
+    --elink_data_out_aurora   when (ec_data_format = "10");
 
-    aurora_en <= '1' when (emu_control.data_format = "10") else '0';
+    --aurora_en <= '1' when (ec_data_format = "10") else '0';
 
     enc8b10bx : entity work.enc8b10_wrap
         port map (
@@ -470,7 +506,7 @@ begin
     --SOP/EOP=K28.1/K28.6=3c/dc (centralrouter_package) are encoded as in https://en.wikipedia.org/wiki/8b/10b_encoding
     --SOP/EOP after the encoding can assume two numbers, depending on
     --current parity (estimated from previous packet)
-    rst_chk2 <= emu_control.reset;
+    rst_chk2 <= ec_reset;
     data_chk2 <= efifoDout_8b10b;
     valid_chk2 <= enc10bitRdy;
     --isEOP_chk2 <= '0';
@@ -487,7 +523,6 @@ begin
             state_chk2 <= st_idl;
             count_chk2 <= (others => '0');
             err_chk2 <= '0';
-        --          elsif clk240'event and clk240='1' then
         elsif clk'event and clk='1' then
             if valid_chk2 = '1' then
               sm_checker2: case state_chk2 is
@@ -517,11 +552,6 @@ begin
                             state_chk2 <= st_count;
                             count_chk2 <= count_chk2 + 1;
                             isEOP_chk2 <= '0';
-                        --else
-                        --  state_chk2 <= st_idl;
-                        --  err_chk2 <= '1';
-                        --  count_chk2 <= (others => '0');
-                        --  isEOP_chk2 <= '0';
                         end if;
                 end case sm_checker2;
             end if;
@@ -533,30 +563,30 @@ begin
         port map (
             --    clk40           => clk240,
             clk40           => clk,
-            rst             => emu_control.reset,
+            rst             => ec_reset,
             clk40_stable    => '1',
             cr_rst          => elink_tx_rst,
             cr_fifo_flush   => fifo_flush
         );
 
-    --RL 64b66b
-    --    aurora_wrapper_FELIG: entity work.aurora_wrapper_FELIG
-    --  port map (
-    --    clk           => clk,
-    --    rst           => elink_tx_rst,
-    --    read_en_in    => elink_data_re,
-    --    count_fifochk => count_fifochk,
-    --    data_in       => EDATA_OUT,
-    --    --output_width  => emu_control.output_width,
-    --    read_en_out   => elink_data_re_aurora,
-    --    data_out      => elink_data_out_aurora_b
-    --    );
-
-    elink_data_out_aurora <= elink_data_out_aurora_b(0) & elink_data_out_aurora_b(1)
-                             & elink_data_out_aurora_b(2) & elink_data_out_aurora_b(3)
-                             & elink_data_out_aurora_b(4) & elink_data_out_aurora_b(5)
-                             & elink_data_out_aurora_b(6) & elink_data_out_aurora_b(7)
-                             & elink_data_out_aurora_b(8) & elink_data_out_aurora_b(9);-- when (fhCR_REVERSE_10B = '1')
+--RL 64b66b
+--    aurora_wrapper_FELIG: entity work.aurora_wrapper_FELIG
+--  port map (
+--    clk           => clk,
+--    rst           => elink_tx_rst,
+--    read_en_in    => elink_data_re,
+--    count_fifochk => count_fifochk,
+--    data_in       => EDATA_OUT,
+--    --output_width  => emu_control.output_width,
+--    read_en_out   => elink_data_re_aurora,
+--    data_out      => elink_data_out_aurora_b
+--    );
+
+--    elink_data_out_aurora <= elink_data_out_aurora_b(0) & elink_data_out_aurora_b(1)
+--                             & elink_data_out_aurora_b(2) & elink_data_out_aurora_b(3)
+--                             & elink_data_out_aurora_b(4) & elink_data_out_aurora_b(5)
+--                             & elink_data_out_aurora_b(6) & elink_data_out_aurora_b(7)
+--                             & elink_data_out_aurora_b(8) & elink_data_out_aurora_b(9);-- when (fhCR_REVERSE_10B = '1')
 --                      else elink_data_out_aurora_b(9) & elink_data_out_aurora_b(8)
 --                         & elink_data_out_aurora_b(7) & elink_data_out_aurora_b(6)
 --                         & elink_data_out_aurora_b(5) & elink_data_out_aurora_b(4)
diff --git a/sources/FELIG/data_generator/elink_printer_bit_feeder_v2.vhd b/sources/FELIG/data_generator/elink_printer_bit_feeder_v2.vhd
index deee02372871d95d00e7b3dcb9f1e878ab980248..85514bcf2864e3df887bd85e1cfc9059a3f8daab 100644
--- a/sources/FELIG/data_generator/elink_printer_bit_feeder_v2.vhd
+++ b/sources/FELIG/data_generator/elink_printer_bit_feeder_v2.vhd
@@ -35,7 +35,9 @@ library UNISIM;
     use UNISIM.VComponents.all;
 
 entity elink_printer_bit_feeder_v2 is
-    port (
+    generic (
+        PROTOCOL                      : std_logic := '0'
+    );    port (
         clk                : in  std_logic;
         enable            : in  std_logic;                    -- enable output, read_enable
         elink_endian_mode    : in  std_logic;                    -- bitwise endianness: '0' little endian (8b10b), '1' big endian.
@@ -44,7 +46,6 @@ entity elink_printer_bit_feeder_v2 is
         word_in            : in  std_logic_vector(9 downto 0); -- from upstreamEpathFifoWrap
         bit_stream_en      : in  std_logic_vector(3 downto 0); -- enable for (0): 2b/4b (1): 8b (2): 16b (3): 32b                                                                          --
         bit_stream_sync      : in  std_logic;                    -- sync by zeroing the counter
-        LINKSconfig           : in  std_logic_vector(2 downto 0);
         gbt_word_latch        : in  std_logic;
         MSBfirst              : in  std_logic;
         aurora                : in  std_logic;
@@ -90,15 +91,9 @@ architecture Behavioral of elink_printer_bit_feeder_v2 is
     signal bit_stream           : std_logic_vector(31 downto 0);
     signal bit_stream_t         : std_logic_vector(31 downto 0);
     signal flag_count           : std_logic := '0';
-    signal lpgbt                 : std_logic := '0';
+--signal lpgbt                 : std_logic := '0';
 
 begin
-    shift_en_d    <= bit_stream_en(0) when (output_width = "000") else  -- Mux input 0:  2 bit output, use 1 clock wide enable
-                     bit_stream_en(0) when (output_width = "001") else  -- Mux input 1:  4 bit output, use 1 clock wide enable
-                     bit_stream_en(1) when (output_width = "010") else  -- Mux input 2:  8 bit output, use 2 clock wide enable
-                     bit_stream_en(2) when (output_width = "011") else  -- Mux input 3: 16 bit output, use 4 clock wide enable
-                     bit_stream_en(3) when (output_width = "100") else  -- Mux input 4: 32 bit output, use 6/8 clock wide enable
-                     '0';
 
     cycle_count_d  <=  "001" when (shift_mode = '0' and input_width = '0' and cycle_count_q = "000") else  -- 2b. direct
                       "010" when (shift_mode = '0' and input_width = '0' and cycle_count_q = "001") else  -- 2b. direct
@@ -119,11 +114,7 @@ begin
                      "011" when (shift_mode = '1' and cycle_count_q(1 downto 0) = "11") else
                      "000";
 
-    lpgbt <= LINKSconfig(2); --0 is gbt, 1 is lpgbt
-
     read_enable_dddd <= '1' when ((enable = '1' ) and (shift_en_q = '1') and (shift_op(1) = '0')) else '0';
-    read_enable_buf <= read_enable_dd when lpgbt = '0' else
-                       read_enable_pr when lpgbt = '1';
     read_enable <= read_enable_buf;
 
     reg_input : process(clk)
@@ -169,140 +160,250 @@ begin
     -- 16*5 =  80  8 words
     -- 32*5 = 160 16 words
 
-    count_max <=  0 when output_width = "000" else -- 2b
-                 1 when output_width = "001" else -- 4b
-                 3 when output_width = "010" else -- 8b
-                 7 when output_width = "011" else --16b
-                 15 when output_width = "100" else --32b
-                 0;
-
     wr_to_reg <= '1' when flag = '1' and flag_d = '0' and output_width /= "010" else
                  '1' when flag = '0' and flag_d = '1' and output_width = "010" else
                  '0';
 
-    wr_to_reg_final <= wr_to_reg_2b when output_width = "000" else
-                       wr_to_reg;
+    g_GBT: if PROTOCOL = '0' generate
+        shift_en_d <=   bit_stream_en(0) when (output_width = "000") else  -- Mux input 0:  2 bit output, use 1 clock wide enable
+                      bit_stream_en(0) when (output_width = "001") else  -- Mux input 1:  4 bit output, use 1 clock wide enable
+                      bit_stream_en(1) when (output_width = "010") else  -- Mux input 2:  8 bit output, use 2 clock wide enable
+                      bit_stream_en(2) when (output_width = "011") else  -- Mux input 3: 16 bit output, use 4 clock wide enable
+                      '0';
+        read_enable_buf <= read_enable_dd;
+        count_max <=    0 when output_width = "000" else -- 2b
+                     1 when output_width = "001" else -- 4b
+                     3 when output_width = "010" else -- 8b
+                     7 when output_width = "011" else --16b
+                     0;
 
-    output_reg : process (clk)
-    begin
-        if clk'event and clk ='1' then
-            flag_d <= flag;
-            if MSBfirst = '0' then
-                word_in_d <= word_in;
-            else
-                for i in 0 to 9 loop
-                    word_in_d(9-i) <= word_in(i);
-                end loop;
-            end if;
-            wr_to_reg_final_d <= wr_to_reg_final;
-            if flag = '0' and flag_d = '1' and (output_width = "010") and input_width = '1' then
-                word_test <= word_in_d;
-            elsif flag = '1' and flag_d = '0' and (output_width = "000" or output_width = "001" or output_width = "011" or output_width = "100") and input_width = '1' then
-                word_test <= word_in_d;
-            end if;
-            if wr_to_reg_final_d = '1' then
-                reg_160_8b10b((count+1)*10 - 1 downto count*10) <= word_test;
-                reg_160_direc((count+1)*8  - 1 downto count*8 ) <= word_test(7 downto 0);
-                if flag_count <= '0' then
-                    if count = count_max then
-                        count <= 0;
+        wr_to_reg_final <=  wr_to_reg_2b when output_width = "000" else wr_to_reg;
+
+        output_reg : process (clk)
+        begin
+            if clk'event and clk ='1' then
+                flag_d <= flag;
+                if MSBfirst = '0' then
+                    word_in_d <= word_in;
+                else
+                    for i in 0 to 9 loop
+                        word_in_d(9-i) <= word_in(i);
+                    end loop;
+                end if;
+                wr_to_reg_final_d <= wr_to_reg_final;
+                if flag = '0' and flag_d = '1' and (output_width = "010") and input_width = '1' then
+                    word_test <= word_in_d;
+                elsif flag = '1' and flag_d = '0' and (output_width = "000" or output_width = "001" or output_width = "011" or output_width = "100") and input_width = '1' then
+                    word_test <= word_in_d;
+                end if;
+                if wr_to_reg_final_d = '1' then
+                    reg_160_8b10b((count+1)*10 - 1 downto count*10) <= word_test;
+                    reg_160_direc((count+1)*8  - 1 downto count*8 ) <= word_test(7 downto 0);
+                    if flag_count <= '0' then
+                        if count = count_max then
+                            count <= 0;
+                        else
+                            count <= count + 1;
+                        end if;
+                    else --reseting after a bit_stream_sync
+                        if output_width = "000" then --2b
+                            flag_count <= '0';
+                        elsif output_width = "001" and count_to_five = "001" then -- 4b
+                            count <= 0;
+                            flag_count <= '0';
+                        elsif output_width = "010" and count_to_five = "001" then --8b
+                            count <= 2;
+                            flag_count <= '0';
+                        elsif output_width = "011" and count_to_five = "011" then --16b
+                            count <= 7;
+                            flag_count <= '0';
+                        end if;
+                    end if;
+                end if;
+
+                if gbt_word_latch = '1' then
+                    bit_stream <= bit_stream_t;
+                    if (count_to_five = "100" and input_width = '1') or (count_to_five = "011" and input_width = '0') then
+                        count_to_five <= "000";
+                        wr_to_reg_2b <= '1';
                     else
-                        count <= count + 1;
+                        count_to_five <= count_to_five + "001"; -- can be moved to the module above.
+                        wr_to_reg_2b <= '0';
                     end if;
-                else --reseting after a bit_stream_sync
-                    if output_width = "000" then --2b
-                        flag_count <= '0';
-                    elsif output_width = "001" and ((count_to_five = "001" and lpgbt = '0') or (count_to_five = "000" and lpgbt = '1')) then -- 4b
-                        count <= 0;
-                        flag_count <= '0';
-                    elsif output_width = "010" and ((count_to_five = "001" and lpgbt = '0') or (count_to_five = "000" and lpgbt = '1')) then --8b
-                        count <= 2;
-                        flag_count <= '0';
-                    elsif output_width = "011" and ((count_to_five = "011" and lpgbt = '0') or (count_to_five = "010" and lpgbt = '1')) then --16b
-                        count <= 7;
-                        flag_count <= '0';
-                    elsif output_width = "100" and count_to_five = "001" and lpgbt = '1' then --32b only lpgbt
-                        count <= 7;
-                        flag_count <= '0';
+                else
+                    wr_to_reg_2b <= '0';
+                end if;
+
+                if (bit_stream_sync = '1') then
+                    flag_count <= '1';
+                    reg_160_8b10b <= (others => '0');
+                    reg_160_direc <= (others => '0');
+                    if input_width = '1' then
+                        count_to_five <= "100";
+                    else
+                        count_to_five <= "011";
                     end if;
                 end if;
             end if;
+        end process output_reg;
+
+        reg_160 <= reg_160_8b10b when input_width = '1' else reg_160_direc;
+
+        bit_stream_t<=bit_stream_zero(29 downto 0) & reg_160(  1 downto   0) when output_width = "000" and count_to_five= "000" else -- 2b elink
+                       bit_stream_zero(29 downto 0) & reg_160(  3 downto   2) when output_width = "000" and count_to_five= "001" else
+                       bit_stream_zero(29 downto 0) & reg_160(  5 downto   4) when output_width = "000" and count_to_five= "010" else
+                       bit_stream_zero(29 downto 0) & reg_160(  7 downto   6) when output_width = "000" and count_to_five= "011" else
+                       bit_stream_zero(29 downto 0) & reg_160(  9 downto   8) when output_width = "000" and count_to_five= "100" else
+                       bit_stream_zero(27 downto 0) & reg_160(  3 downto   0) when output_width = "001" and count_to_five= "000" else -- 4b elink
+                       bit_stream_zero(27 downto 0) & reg_160(  7 downto   4) when output_width = "001" and count_to_five= "001" else
+                       bit_stream_zero(27 downto 0) & reg_160( 11 downto   8) when output_width = "001" and count_to_five= "010" else
+                       bit_stream_zero(27 downto 0) & reg_160( 15 downto  12) when output_width = "001" and count_to_five= "011" else
+                       bit_stream_zero(27 downto 0) & reg_160( 19 downto  16) when output_width = "001" and count_to_five= "100" else
+                       bit_stream_zero(23 downto 0) & reg_160(  7 downto   0) when output_width = "010" and count_to_five= "000" else -- 8b elink
+                       bit_stream_zero(23 downto 0) & reg_160( 15 downto   8) when output_width = "010" and count_to_five= "001" else
+                       bit_stream_zero(23 downto 0) & reg_160( 23 downto  16) when output_width = "010" and count_to_five= "010" else
+                       bit_stream_zero(23 downto 0) & reg_160( 31 downto  24) when output_width = "010" and count_to_five= "011" else
+                       bit_stream_zero(23 downto 0) & reg_160( 39 downto  32) when output_width = "010" and count_to_five= "100" else
+                       bit_stream_zero(15 downto 0) & reg_160( 15 downto   0) when output_width = "011" and count_to_five= "000" else --16b elink
+                       bit_stream_zero(15 downto 0) & reg_160( 31 downto  16) when output_width = "011" and count_to_five= "001" else
+                       bit_stream_zero(15 downto 0) & reg_160( 47 downto  32) when output_width = "011" and count_to_five= "010" else
+                       bit_stream_zero(15 downto 0) & reg_160( 63 downto  48) when output_width = "011" and count_to_five= "011" else
+                       bit_stream_zero(15 downto 0) & reg_160( 79 downto  64) when output_width = "011" and count_to_five= "100" else
+                       bit_stream_zero;
+
+        --add endianess
+        bit_stream_out <= bit_stream
+                          when MSBfirst = '0' and enable = '1' else
+                          bit_stream(29 downto 0)
+                          & bit_stream(0) & bit_stream(1)
+                          when MSBfirst = '1' and output_width = "000" and enable = '1' else
+                          bit_stream_zero(27 downto 0)
+                          & bit_stream(0) & bit_stream(1) & bit_stream(2) & bit_stream(3)
+                          when MSBfirst = '1' and output_width = "001" and enable = '1' else
+                          bit_stream_zero(23 downto 0)
+                          & bit_stream(0) & bit_stream(1) & bit_stream(2)  & bit_stream(3)  & bit_stream(4)  & bit_stream(5)  & bit_stream(6)  & bit_stream(7)
+                          when MSBfirst = '1' and output_width = "010" and enable = '1' else
+                          bit_stream_zero(15 downto 0)
+                          & bit_stream(0) & bit_stream(1) & bit_stream(2)  & bit_stream(3)  & bit_stream(4)  & bit_stream(5)  & bit_stream(6)  & bit_stream(7)
+                          & bit_stream(8) & bit_stream(9) & bit_stream(10) & bit_stream(11) & bit_stream(12) & bit_stream(13) & bit_stream(14) & bit_stream(15)
+                          when MSBfirst = '1' and output_width = "011" and enable = '1' else
+                          bit_stream_zero;
+    end generate;
 
-            if gbt_word_latch = '1' then
-                bit_stream <= bit_stream_t;
-                if (count_to_five = "100" and input_width = '1') or (count_to_five = "011" and input_width = '0') then
-                    count_to_five <= "000";
-                    wr_to_reg_2b <= '1';
+    g_lpGBT: if PROTOCOL = '1' generate
+        shift_en_d  <= bit_stream_en(1) when (output_width = "010") else  -- Mux input 2:  8 bit output, use 2 clock wide enable
+                       bit_stream_en(2) when (output_width = "011") else  -- Mux input 3: 16 bit output, use 4 clock wide enable
+                       bit_stream_en(3) when (output_width = "100") else  -- Mux input 4: 32 bit output, use 6/8 clock wide enable
+                       '0';
+        read_enable_buf <= read_enable_pr;
+        count_max <= 3  when output_width = "010" else -- 8b
+                     7  when output_width = "011" else --16b
+                     15 when output_width = "100" else --32b
+                     0;
+
+        wr_to_reg_final <= wr_to_reg;
+
+        output_reg : process (clk)
+        begin
+            if clk'event and clk ='1' then
+                flag_d <= flag;
+                if MSBfirst = '0' then
+                    word_in_d <= word_in;
                 else
-                    count_to_five <= count_to_five + "001"; -- can be moved to the module above.
-                    wr_to_reg_2b <= '0';
+                    for i in 0 to 9 loop
+                        word_in_d(9-i) <= word_in(i);
+                    end loop;
+                end if;
+                wr_to_reg_final_d <= wr_to_reg_final;
+                if flag = '0' and flag_d = '1' and (output_width = "010") and input_width = '1' then
+                    word_test <= word_in_d;
+                elsif flag = '1' and flag_d = '0' and (output_width = "000" or output_width = "001" or output_width = "011" or output_width = "100") and input_width = '1' then
+                    word_test <= word_in_d;
+                end if;
+                if wr_to_reg_final_d = '1' then
+                    reg_160_8b10b((count+1)*10 - 1 downto count*10) <= word_test;
+                    reg_160_direc((count+1)*8  - 1 downto count*8 ) <= word_test(7 downto 0);
+                    if flag_count <= '0' then
+                        if count = count_max then
+                            count <= 0;
+                        else
+                            count <= count + 1;
+                        end if;
+                    else --reseting after a bit_stream_sync
+                        if output_width = "010" and count_to_five = "000" then --8b
+                            count <= 2;
+                            flag_count <= '0';
+                        elsif output_width = "011" and count_to_five = "010" then --16b
+                            count <= 7;
+                            flag_count <= '0';
+                        elsif output_width = "100" and count_to_five = "001" then --32b
+                            count <= 7;
+                            flag_count <= '0';
+                        end if;
+                    end if;
                 end if;
-            else
-                wr_to_reg_2b <= '0';
-            end if;
 
-            if (bit_stream_sync = '1') then
-                flag_count <= '1';
-                reg_160_8b10b <= (others => '0');
-                reg_160_direc <= (others => '0');
-                if input_width = '1' then
-                    count_to_five <= "100";
+                if gbt_word_latch = '1' then
+                    bit_stream <= bit_stream_t;
+                    if (count_to_five = "100" and input_width = '1') or (count_to_five = "011" and input_width = '0') then
+                        count_to_five <= "000";
+                        wr_to_reg_2b <= '1';
+                    else
+                        count_to_five <= count_to_five + "001"; -- can be moved to the module above.
+                        wr_to_reg_2b <= '0';
+                    end if;
                 else
-                    count_to_five <= "011";
+                    wr_to_reg_2b <= '0';
+                end if;
+
+                if (bit_stream_sync = '1') then
+                    flag_count <= '1';
+                    reg_160_8b10b <= (others => '0');
+                    reg_160_direc <= (others => '0');
+                    if input_width = '1' then
+                        count_to_five <= "100";
+                    else
+                        count_to_five <= "011";
+                    end if;
                 end if;
             end if;
-        end if;
-    end process output_reg;
-
-    reg_160 <= reg_160_8b10b when input_width = '1' else reg_160_direc;
-
-    bit_stream_t<=bit_stream_zero(29 downto 0) & reg_160(  1 downto   0) when output_width = "000" and count_to_five= "000" else -- 2b elink
-                   bit_stream_zero(29 downto 0) & reg_160(  3 downto   2) when output_width = "000" and count_to_five= "001" else
-                   bit_stream_zero(29 downto 0) & reg_160(  5 downto   4) when output_width = "000" and count_to_five= "010" else
-                   bit_stream_zero(29 downto 0) & reg_160(  7 downto   6) when output_width = "000" and count_to_five= "011" else
-                   bit_stream_zero(29 downto 0) & reg_160(  9 downto   8) when output_width = "000" and count_to_five= "100" else
-                   bit_stream_zero(27 downto 0) & reg_160(  3 downto   0) when output_width = "001" and count_to_five= "000" else -- 4b elink
-                   bit_stream_zero(27 downto 0) & reg_160(  7 downto   4) when output_width = "001" and count_to_five= "001" else
-                   bit_stream_zero(27 downto 0) & reg_160( 11 downto   8) when output_width = "001" and count_to_five= "010" else
-                   bit_stream_zero(27 downto 0) & reg_160( 15 downto  12) when output_width = "001" and count_to_five= "011" else
-                   bit_stream_zero(27 downto 0) & reg_160( 19 downto  16) when output_width = "001" and count_to_five= "100" else
-                   bit_stream_zero(23 downto 0) & reg_160(  7 downto   0) when output_width = "010" and count_to_five= "000" else -- 8b elink
-                   bit_stream_zero(23 downto 0) & reg_160( 15 downto   8) when output_width = "010" and count_to_five= "001" else
-                   bit_stream_zero(23 downto 0) & reg_160( 23 downto  16) when output_width = "010" and count_to_five= "010" else
-                   bit_stream_zero(23 downto 0) & reg_160( 31 downto  24) when output_width = "010" and count_to_five= "011" else
-                   bit_stream_zero(23 downto 0) & reg_160( 39 downto  32) when output_width = "010" and count_to_five= "100" else
-                   bit_stream_zero(15 downto 0) & reg_160( 15 downto   0) when output_width = "011" and count_to_five= "000" else --16b elink
-                   bit_stream_zero(15 downto 0) & reg_160( 31 downto  16) when output_width = "011" and count_to_five= "001" else
-                   bit_stream_zero(15 downto 0) & reg_160( 47 downto  32) when output_width = "011" and count_to_five= "010" else
-                   bit_stream_zero(15 downto 0) & reg_160( 63 downto  48) when output_width = "011" and count_to_five= "011" else
-                   bit_stream_zero(15 downto 0) & reg_160( 79 downto  64) when output_width = "011" and count_to_five= "100" else
-                   reg_160( 31 downto   0) when output_width = "100" and count_to_five= "000" else --32b elink
-                   reg_160( 63 downto  32) when output_width = "100" and count_to_five= "001" else
-                   reg_160( 95 downto  64) when output_width = "100" and count_to_five= "010" else
-                   reg_160(127 downto  96) when output_width = "100" and count_to_five= "011" else
-                   reg_160(159 downto 128) when output_width = "100" and count_to_five= "100" else
-                   bit_stream_zero;
-
-    --add endianess
-    bit_stream_out <= bit_stream
-                      when MSBfirst = '0' and enable = '1' else
-                      bit_stream(29 downto 0)
-                      & bit_stream(0) & bit_stream(1)
-                      when MSBfirst = '1' and output_width = "000" and enable = '1' else
-                      bit_stream_zero(27 downto 0)
-                      & bit_stream(0) & bit_stream(1) & bit_stream(2) & bit_stream(3)
-                      when MSBfirst = '1' and output_width = "001" and enable = '1' else
-                      bit_stream_zero(23 downto 0)
-                      & bit_stream(0) & bit_stream(1) & bit_stream(2)  & bit_stream(3)  & bit_stream(4)  & bit_stream(5)  & bit_stream(6)  & bit_stream(7)
-                      when MSBfirst = '1' and output_width = "010" and enable = '1' else
-                      bit_stream_zero(15 downto 0)
-                      & bit_stream(0) & bit_stream(1) & bit_stream(2)  & bit_stream(3)  & bit_stream(4)  & bit_stream(5)  & bit_stream(6)  & bit_stream(7)
-                      & bit_stream(8) & bit_stream(9) & bit_stream(10) & bit_stream(11) & bit_stream(12) & bit_stream(13) & bit_stream(14) & bit_stream(15)
-                      when MSBfirst = '1' and output_width = "011" and enable = '1' else
-                      bit_stream(0)  & bit_stream(1)  & bit_stream(2)  & bit_stream(3)  & bit_stream(4)  & bit_stream(5)  & bit_stream(6)  & bit_stream(7)
-                      & bit_stream(8)  & bit_stream(9)  & bit_stream(10) & bit_stream(11) & bit_stream(12) & bit_stream(13) & bit_stream(14) & bit_stream(15)
-                      & bit_stream(16) & bit_stream(17) & bit_stream(18) & bit_stream(19) & bit_stream(20) & bit_stream(21) & bit_stream(22) & bit_stream(23)
-                      & bit_stream(24) & bit_stream(25) & bit_stream(26) & bit_stream(27) & bit_stream(28) & bit_stream(29) & bit_stream(30) & bit_stream(31)
-                      when MSBfirst = '1' and output_width = "100" and enable = '1' else
-                      bit_stream_zero;
+        end process output_reg;
+
+        reg_160 <= reg_160_8b10b when input_width = '1' else reg_160_direc;
+
+        bit_stream_t<= bit_stream_zero(23 downto 0) & reg_160(  7 downto   0) when output_width = "010" and count_to_five= "000" else -- 8b elink
+                       bit_stream_zero(23 downto 0) & reg_160( 15 downto   8) when output_width = "010" and count_to_five= "001" else
+                       bit_stream_zero(23 downto 0) & reg_160( 23 downto  16) when output_width = "010" and count_to_five= "010" else
+                       bit_stream_zero(23 downto 0) & reg_160( 31 downto  24) when output_width = "010" and count_to_five= "011" else
+                       bit_stream_zero(23 downto 0) & reg_160( 39 downto  32) when output_width = "010" and count_to_five= "100" else
+                       bit_stream_zero(15 downto 0) & reg_160( 15 downto   0) when output_width = "011" and count_to_five= "000" else --16b elink
+                       bit_stream_zero(15 downto 0) & reg_160( 31 downto  16) when output_width = "011" and count_to_five= "001" else
+                       bit_stream_zero(15 downto 0) & reg_160( 47 downto  32) when output_width = "011" and count_to_five= "010" else
+                       bit_stream_zero(15 downto 0) & reg_160( 63 downto  48) when output_width = "011" and count_to_five= "011" else
+                       bit_stream_zero(15 downto 0) & reg_160( 79 downto  64) when output_width = "011" and count_to_five= "100" else
+                       reg_160( 31 downto   0) when output_width = "100" and count_to_five= "000" else --32b elink
+                       reg_160( 63 downto  32) when output_width = "100" and count_to_five= "001" else
+                       reg_160( 95 downto  64) when output_width = "100" and count_to_five= "010" else
+                       reg_160(127 downto  96) when output_width = "100" and count_to_five= "011" else
+                       reg_160(159 downto 128) when output_width = "100" and count_to_five= "100" else
+                       bit_stream_zero;
+
+        --add endianess
+        bit_stream_out <= bit_stream
+                          when MSBfirst = '0' and enable = '1' else
+                          bit_stream_zero(23 downto 0)
+                          & bit_stream(0) & bit_stream(1) & bit_stream(2)  & bit_stream(3)  & bit_stream(4)  & bit_stream(5)  & bit_stream(6)  & bit_stream(7)
+                          when MSBfirst = '1' and output_width = "010" and enable = '1' else
+                          bit_stream_zero(15 downto 0)
+                          & bit_stream(0) & bit_stream(1) & bit_stream(2)  & bit_stream(3)  & bit_stream(4)  & bit_stream(5)  & bit_stream(6)  & bit_stream(7)
+                          & bit_stream(8) & bit_stream(9) & bit_stream(10) & bit_stream(11) & bit_stream(12) & bit_stream(13) & bit_stream(14) & bit_stream(15)
+                          when MSBfirst = '1' and output_width = "011" and enable = '1' else
+                          bit_stream(0)  & bit_stream(1)  & bit_stream(2)  & bit_stream(3)  & bit_stream(4)  & bit_stream(5)  & bit_stream(6)  & bit_stream(7)
+                          & bit_stream(8)  & bit_stream(9)  & bit_stream(10) & bit_stream(11) & bit_stream(12) & bit_stream(13) & bit_stream(14) & bit_stream(15)
+                          & bit_stream(16) & bit_stream(17) & bit_stream(18) & bit_stream(19) & bit_stream(20) & bit_stream(21) & bit_stream(22) & bit_stream(23)
+                          & bit_stream(24) & bit_stream(25) & bit_stream(26) & bit_stream(27) & bit_stream(28) & bit_stream(29) & bit_stream(30) & bit_stream(31)
+                          when MSBfirst = '1' and output_width = "100" and enable = '1' else
+                          bit_stream_zero;
+    end generate;
+
 end Behavioral;
diff --git a/sources/FELIG/data_generator/elink_printer_v2.vhd b/sources/FELIG/data_generator/elink_printer_v2.vhd
index 734253d682d122654f8b20a1a70b4a8e816f9db1..618cb8b96c9b5f4a4457f9f7fad700a20ab3d9e1 100644
--- a/sources/FELIG/data_generator/elink_printer_v2.vhd
+++ b/sources/FELIG/data_generator/elink_printer_v2.vhd
@@ -31,188 +31,433 @@ LIBRARY IEEE;
 library UNISIM;
     use UNISIM.VComponents.all;
 
+Library xpm;
+    use xpm.vcomponents.all;
+
 entity gbt_word_printer_v2 is
     generic (
-        NUMELINKmax                   : integer := 112
+        NUMELINKmax     : integer := 112;
+        NUMEGROUPmax    : integer := 7;
+        PROTOCOL        : std_logic := '0'
     );
     port (
-        clk            : in  std_logic;
-        elink_control    : in  lane_elink_control_array(0 to NUMELINKmax-1);
-        elink_sync      : in  std_logic;
-        elink_data      : in  array_of_slv_9_0(0 to NUMELINKmax-1);
-        tx_flag        : in  std_logic;
-        LINKSconfig         : in  std_logic_vector(2 downto 0);
+        clk                 : in  std_logic;
+        elink_control       : in  lane_elink_control_array(0 to NUMELINKmax-1);
+        elink_sync_reg      : in  std_logic;
+        elink_data          : in  array_of_slv_9_0(0 to NUMELINKmax-1);
+        tx_flag             : in  std_logic;
+        l1a_trigger         : in  std_logic;
+        --std_logic_vector(2 downto 0);
         MSBfirst            : in  std_logic;
-        elink_read_enable  : out std_logic_vector(0 to NUMELINKmax-1);
-        gbt_payload      : out std_logic_vector(223 downto 0);
-        aurora_en           : in  std_logic_vector(0 to NUMELINKmax-1)
+        elink_read_enable   : out std_logic_vector(0 to NUMELINKmax-1);
+        gbt_payload         : out std_logic_vector(223 downto 0);
+        aurora_en           : in  std_logic_vector(0 to NUMELINKmax-1);
+        data_ready          : out std_logic;
+        or_out_of_sync      : in  std_logic;
+        flag_sync           : in  std_logic_vector(0 to NUMEGROUPmax-1)
     );
 end gbt_word_printer_v2;
 
 architecture Behavioral of gbt_word_printer_v2 is
-    signal gbt_shift_count    : std_logic_vector(  3 downto 0) := (others => '0');
-    signal bit_stream_en    : std_logic_vector(  3 downto 0) := (others => '0');
-    signal bit_stream_sync    : std_logic := '0';
-    signal elink_sync_lat    : std_logic := '0';
-    signal gbt_word_latch    : std_logic := '0';
-    signal bit_stream           : array_of_slv_31_0(0 to NUMELINKmax-1);
-    signal gbt_bit_stream    : std_logic_vector(223 downto 0) := (others => '0');
-    signal gbt_payload_i      : std_logic_vector(223 downto 0) := (others => '0');
-    signal elink_read_enable_i  : std_logic_vector(0 to NUMELINKmax-1);
-    signal lpgbt                : std_logic := '0';
+    signal gbt_shift_count                  : std_logic_vector(3 downto 0) := (others => '0');
+    signal bit_stream_en                    : std_logic_vector(3 downto 0) := (others => '0');
+    signal bit_stream_sync                  : std_logic := '0';
+    signal elink_sync_lat                   : std_logic := '0';
+    signal gbt_word_latch                   : std_logic := '0';
+    signal bit_stream                       : array_of_slv_31_0(0 to NUMELINKmax-1);
+    signal gbt_bit_stream                   : std_logic_vector(223 downto 0) := (others => '0');
+    signal gbt_payload_i                    : std_logic_vector(223 downto 0) := (others => '0');
+    signal elink_read_enable_i              : std_logic_vector(0 to NUMELINKmax-1);
+    --signal lpgbt                            : std_logic := '0';
+    signal elink_control_output_width_array : array_of_slv_2_0(0 to NUMELINKmax-1);
+
+    type STATEM  is (st_idle, st_sync, st_generate) ;
+    signal state                            : STATEM := st_idle;
+    signal elink_sync                       :  std_logic;
+    signal start_gen                        : std_logic;
+    signal gen_done                         : std_logic_vector(0 to NUMEGROUPmax-1) := (others => '0');
+    constant gen_done_1                     : std_logic_vector(0 to NUMEGROUPmax-1) := (others => '1');
+    constant gen_done_0                     : std_logic_vector(0 to NUMEGROUPmax-1) := (others => '0');
+
+    signal count_sync                       : std_logic_vector(0 to 5) := "000000";
+    signal sync_read_enable                 : std_logic :='0';
+
+
+    signal will_sync                        : std_logic := '0';
+    signal flag_will_sync                   : std_logic := '0';
 begin
 
     gbt_payload <= gbt_payload_i;
     elink_read_enable <= elink_read_enable_i;
-    lpgbt <= LINKSconfig(2); --0 is gbt, 1 is lpgbt
+    --lpgbt <= PROTOCOL;--LINKSconfig(2); --0 is gbt, 1 is lpgbt
 
-    reg_input : process(clk)
+    gen_elink_printers : for i in 0 to NUMELINKmax-1 generate
+        signal elink_control_enable         : std_logic;
+        signal elink_control_endian_mode    : std_logic;
+        signal elink_control_output_width   : std_logic_vector(2 downto 0);
+        signal elink_control_input_width    : std_logic;
+        signal MSBfirst_d       : std_logic;
     begin
-        if clk'event and clk ='1' then
-            if (tx_flag = '1' ) then
-                gbt_shift_count <= (others => '0');
-                if gbt_shift_count /= "0101" and lpgbt = '0' then
-                    elink_sync_lat <= '1';
-                elsif gbt_shift_count /= "0111" and lpgbt = '1' then
-                    elink_sync_lat <= '1';
-                end if;
-            elsif (gbt_shift_count /= "1111") then
-                gbt_shift_count <= gbt_shift_count + 1;
-            end if;
-            --------
-            if (gbt_word_latch = '1') then
-                gbt_payload_i <= gbt_bit_stream;
+
+        xpm_enable : xpm_cdc_single generic map(
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0
+            )
+            port map(
+                src_clk => '0',
+                src_in => elink_control(i).enable,
+                dest_clk => clk,
+                dest_out => elink_control_enable
+            );
+
+        xpm_endian_mode : xpm_cdc_single generic map(
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0
+            )
+            port map(
+                src_clk => '0',
+                src_in => elink_control(i).endian_mode,
+                dest_clk => clk,
+                dest_out => elink_control_endian_mode
+            );
+
+        xpm_output_width : xpm_cdc_array_single generic map(
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0,
+                WIDTH => 3
+            )
+            port map(
+                src_clk => '0',
+                src_in => elink_control(i).output_width,
+                dest_clk => clk,
+                dest_out => elink_control_output_width
+            );
+
+        xpm_input_width : xpm_cdc_single generic map(
+                DEST_SYNC_FF => 2,
+                INIT_SYNC_FF => 0,
+                SIM_ASSERT_CHK => 0,
+                SRC_INPUT_REG => 0
+            )
+            port map(
+                src_clk => '0',
+                src_in => elink_control(i).input_width,
+                dest_clk => clk,
+                dest_out => elink_control_input_width
+            );
+        elink_control_output_width_array(i) <= elink_control_output_width;
+
+        reg_input : process(clk)
+        begin
+            if clk'event and clk ='1' then
+                MSBfirst_d <= MSBfirst; --register so it can be delayed to avoid high fanout
             end if;
-            --------
-            case gbt_shift_count is
-                when "0000" =>
-                    bit_stream_en <= "1000";
-                    bit_stream_sync <= '0';
-                    gbt_word_latch <= '0';
-                    if (elink_sync = '1') then
-                        elink_sync_lat <= '1';
-                    end if;
-                when "0001" =>
-                    bit_stream_en <= "1000";
-                    bit_stream_sync <= '0';
-                    gbt_word_latch <= '0';
-                    if (elink_sync = '1') then
+        end process;
+        elink_bit_feeder : entity work.elink_printer_bit_feeder_v2
+            generic map (
+                PROTOCOL            => PROTOCOL
+            )
+            port map (
+                clk                 => clk,
+                enable              => elink_control_enable,
+                elink_endian_mode   => elink_control_endian_mode,
+                elink_output_width  => elink_control_output_width,
+                elink_input_width   => elink_control_input_width,
+                word_in             => elink_data(i),
+                bit_stream_en       => bit_stream_en,
+                bit_stream_sync     => bit_stream_sync,
+                --protocol            => protocol,
+                gbt_word_latch      => gbt_word_latch,
+                MSBfirst            => MSBfirst_d,
+                aurora              => aurora_en(i),
+                read_enable         => elink_read_enable_i(i),
+                bit_stream_out      => bit_stream(i)
+            );
+    end generate gen_elink_printers;
+
+    g_GBT: if PROTOCOL = '0' generate
+
+        reg_input : process(clk)
+        begin
+            if clk'event and clk ='1' then
+                if (tx_flag = '1' ) then
+                    gbt_shift_count <= (others => '0');
+                    if gbt_shift_count /= "0101" then
                         elink_sync_lat <= '1';
                     end if;
-                when "0010" =>
-                    bit_stream_en <= "1100";
-                    bit_stream_sync <= elink_sync_lat;
-                    gbt_word_latch <= '0';
-                    elink_sync_lat <= elink_sync;
-                when "0011" =>
-                    bit_stream_en <= "1111";
-                    bit_stream_sync <= '0';
-                    if lpgbt = '0' then
+                elsif (gbt_shift_count /= "1111") then
+                    gbt_shift_count <= gbt_shift_count + 1;
+                end if;
+                --------
+                if (gbt_word_latch = '1') then
+                    gbt_payload_i <= gbt_bit_stream;
+                end if;
+                --------
+                case gbt_shift_count is
+                    when "0000" =>
+                        bit_stream_en <= "1000";
+                        bit_stream_sync <= '0';
+                        gbt_word_latch <= '0';
+                        if (elink_sync = '1') then
+                            elink_sync_lat <= '1';
+                        end if;
+                    when "0001" =>
+                        bit_stream_en <= "1000";
+                        bit_stream_sync <= '0';
+                        gbt_word_latch <= '0';
+                        if (elink_sync = '1') then
+                            elink_sync_lat <= '1';
+                        end if;
+                    when "0010" =>
+                        bit_stream_en <= "1100";
+                        bit_stream_sync <= elink_sync_lat;
+                        gbt_word_latch <= '0';
+                        elink_sync_lat <= elink_sync;
+                    when "0011" =>
+                        bit_stream_en <= "1111";
+                        bit_stream_sync <= '0';
                         gbt_word_latch <= '1';
-                    else
+                        if (elink_sync = '1') then
+                            elink_sync_lat <= '1';
+                        end if;
+                    when "0100" =>
+                        bit_stream_en <= "1110";
+                        bit_stream_sync <= '0';
+                        gbt_word_latch <= '0';
+                        if (elink_sync = '1') then
+                            elink_sync_lat <= '1';
+                        end if;
+                    when "0101" =>
+                        bit_stream_en <= "1100";
+                        bit_stream_sync <= '0';
+                        gbt_word_latch <= '0';
+                        if (elink_sync = '1') then
+                            elink_sync_lat <= '1';
+                        end if;
+                    when "0110" =>
+                        bit_stream_en <= "1000";
+                        bit_stream_sync <= '0';
+                        gbt_word_latch <= '0';
+                        if (elink_sync = '1') then
+                            elink_sync_lat <= '1';
+                        end if;
+                    when "0111" =>
+                        bit_stream_en <= "1000";
+                        bit_stream_sync <= '0';
+                        gbt_word_latch <= '0';
+                        if (elink_sync = '1') then
+                            elink_sync_lat <= '1';
+                        end if;
+                    when others =>
+                        bit_stream_en <= "0000";
+                        bit_stream_sync <= '0';
                         gbt_word_latch <= '0';
-                    end if;
-                    if (elink_sync = '1') then
                         elink_sync_lat <= '1';
-                    end if;
-                when "0100" =>
-                    bit_stream_en <= "1110";
-                    bit_stream_sync <= '0';
-                    gbt_word_latch <= '0';
-                    if (elink_sync = '1') then
+                end case;
+            end if;
+        end process reg_input;
+
+        gen_gbt_stream : for i in 0 to 6 generate
+            signal output_width : std_logic_vector(2 downto 0);
+        begin
+            output_width <= elink_control_output_width_array(i*16);--elink_control(i*16).output_width;
+            gbt_bit_stream(32*(i+1)-1 downto 32*i)
+                       <= bit_stream(i*16+15)( 1 downto 0) &
+                          bit_stream(i*16+14)( 1 downto 0) &
+                          bit_stream(i*16+13)( 1 downto 0) &
+                          bit_stream(i*16+12)( 1 downto 0) &
+                          bit_stream(i*16+11)( 1 downto 0) &
+                          bit_stream(i*16+10)( 1 downto 0) &
+                          bit_stream(i*16+ 9)( 1 downto 0) &
+                          bit_stream(i*16+ 8)( 1 downto 0) &
+                          bit_stream(i*16+ 7)( 1 downto 0) &
+                          bit_stream(i*16+ 6)( 1 downto 0) &
+                          bit_stream(i*16+ 5)( 1 downto 0) &
+                          bit_stream(i*16+ 4)( 1 downto 0) &
+                          bit_stream(i*16+ 3)( 1 downto 0) &
+                          bit_stream(i*16+ 2)( 1 downto 0) &
+                          bit_stream(i*16+ 1)( 1 downto 0) &
+                          bit_stream(i*16+ 0)( 1 downto 0) when output_width="000" else
+                          bit_stream(i*16+14)( 3 downto 0) &
+                          bit_stream(i*16+12)( 3 downto 0) &
+                          bit_stream(i*16+10)( 3 downto 0) &
+                          bit_stream(i*16+ 8)( 3 downto 0) &
+                          bit_stream(i*16+ 6)( 3 downto 0) &
+                          bit_stream(i*16+ 4)( 3 downto 0) &
+                          bit_stream(i*16+ 2)( 3 downto 0) &
+                          bit_stream(i*16+ 0)( 3 downto 0) when output_width="001" else
+                          bit_stream(i*16+12)( 7 downto 0) &
+                          bit_stream(i*16+ 8)( 7 downto 0) &
+                          bit_stream(i*16+ 4)( 7 downto 0) &
+                          bit_stream(i*16+ 0)( 7 downto 0) when output_width="010" else
+                          bit_stream(i*16+ 8)(15 downto 0) &
+                          bit_stream(i*16+ 0)(15 downto 0) when output_width="011" else
+                          (others => '0');
+        end generate gen_gbt_stream;
+    end generate;
+
+    g_lpGBT: if PROTOCOL = '1' generate
+
+        reg_input : process(clk)
+        begin
+            if clk'event and clk ='1' then
+                if (tx_flag = '1' ) then
+                    gbt_shift_count <= (others => '0');
+                    if gbt_shift_count /= "0111" then
                         elink_sync_lat <= '1';
                     end if;
-                when "0101" =>
-                    bit_stream_en <= "1100";
-                    bit_stream_sync <= '0';
-                    gbt_word_latch <= '0';
-                    if (elink_sync = '1') then
+                elsif (gbt_shift_count /= "1111") then
+                    gbt_shift_count <= gbt_shift_count + 1;
+                end if;
+                --------
+                if (gbt_word_latch = '1') then
+                    gbt_payload_i <= gbt_bit_stream;
+                    data_ready    <= '1';
+                else
+                    data_ready    <= '0';
+                end if;
+                --------
+                case gbt_shift_count is
+                    when "0000" =>
+                        bit_stream_en <= "1000";
+                        bit_stream_sync <= '0';
+                        gbt_word_latch <= '0';
+                        if (elink_sync = '1') then
+                            elink_sync_lat <= '1';
+                        end if;
+                    when "0001" =>
+                        bit_stream_en <= "1000";
+                        bit_stream_sync <= '0';
+                        gbt_word_latch <= '0';
+                        if (elink_sync = '1') then
+                            elink_sync_lat <= '1';
+                        end if;
+                    when "0010" =>
+                        bit_stream_en <= "1100";
+                        bit_stream_sync <= elink_sync_lat;
+                        gbt_word_latch <= '0';
+                        elink_sync_lat <= elink_sync;
+                    when "0011" =>
+                        bit_stream_en <= "1111";
+                        bit_stream_sync <= '0';
+                        gbt_word_latch <= '0';
+                        if (elink_sync = '1') then
+                            elink_sync_lat <= '1';
+                        end if;
+                    when "0100" =>
+                        bit_stream_en <= "1110";
+                        bit_stream_sync <= '0';
+                        gbt_word_latch <= '0';
+                        if (elink_sync = '1') then
+                            elink_sync_lat <= '1';
+                        end if;
+                    when "0101" =>
+                        bit_stream_en <= "1100";
+                        bit_stream_sync <= '0';
+                        gbt_word_latch <= '0';
+                        if (elink_sync = '1') then
+                            elink_sync_lat <= '1';
+                        end if;
+                    when "0110" =>
+                        bit_stream_en <= "1000";
+                        bit_stream_sync <= '0';
+                        gbt_word_latch <= '0';
+                        if (elink_sync = '1') then
+                            elink_sync_lat <= '1';
+                        end if;
+                    when "0111" =>
+                        bit_stream_en <= "1000";
+                        bit_stream_sync <= '0';
+                        gbt_word_latch <= '1';
+                        if (elink_sync = '1') then
+                            elink_sync_lat <= '1';
+                        end if;
+                    when others =>
+                        bit_stream_en <= "0000";
+                        bit_stream_sync <= '0';
+                        gbt_word_latch <= '0';
                         elink_sync_lat <= '1';
+                end case;
+            end if;
+        end process reg_input;
+
+        gen_gbt_stream : for i in 0 to 6 generate
+            signal output_width : std_logic_vector(2 downto 0);
+        begin
+            output_width <= elink_control_output_width_array(i*16);--elink_control(i*16).output_width;
+            gbt_bit_stream(32*(i+1)-1 downto 32*i)
+                       <= bit_stream(i*16+12)( 7 downto 0) &
+                          bit_stream(i*16+ 8)( 7 downto 0) &
+                          bit_stream(i*16+ 4)( 7 downto 0) &
+                          bit_stream(i*16+ 0)( 7 downto 0) when output_width="010" else
+                          bit_stream(i*16+ 8)(15 downto 0) &
+                          bit_stream(i*16+ 0)(15 downto 0) when output_width="011" else
+                          bit_stream(i*16+ 0)(31 downto 0) when output_width="100" else
+                          (others => '0');
+        end generate gen_gbt_stream;
+    end generate;
+
+    --state machine to control elink_sync.
+    start_gen <= elink_sync_reg;
+    sync_readenable : process(clk)
+    begin
+        if clk'event and clk ='1' then
+            sm_sync: case state is
+                when st_idle =>
+                    sync_read_enable <= '0';
+                    count_sync<="000000";
+                    if l1a_trigger = '1' then
+                        state <= st_generate;
+                    elsif start_gen = '1' then
+                        state <= st_sync;
+                    else
+                        state <= st_idle;
                     end if;
-                when "0110" =>
-                    bit_stream_en <= "1000";
-                    bit_stream_sync <= '0';
-                    gbt_word_latch <= '0';
-                    if (elink_sync = '1') then
-                        elink_sync_lat <= '1';
+                when st_sync =>
+                    gen_done <= gen_done_0;
+                    if(count_sync = "111111") then
+                        if(will_sync = '1') then
+                            sync_read_enable <= '1';--'1';
+                            will_sync <= '0';
+                        end if;
+                        count_sync<="000000";
+                    else
+                        sync_read_enable <= '0';
+                        count_sync <= count_sync + '1';
                     end if;
-                when "0111" =>
-                    bit_stream_en <= "1000";
-                    bit_stream_sync <= '0';
-                    if lpgbt = '1' then
-                        gbt_word_latch <= '1';
+                    if l1a_trigger = '1' then
+                        state <= st_generate;
+                        count_sync<="000000";
                     else
-                        gbt_word_latch <= '0';
+                        state <= st_sync;
                     end if;
-                    if (elink_sync = '1') then
-                        elink_sync_lat <= '1';
+                when st_generate =>
+                    sync_read_enable <= '0';
+                    for i in 0 to NUMEGROUPmax-1 loop
+                        if(flag_sync(i) = '1') then
+                            gen_done(i) <= '1';
+                        end if;
+                    end loop;
+                    if gen_done = gen_done_1 or start_gen = '1' then
+                        state <= st_sync;
+                    else
+                        state <= st_generate;
                     end if;
-                when others =>
-                    bit_stream_en <= "0000";
-                    bit_stream_sync <= '0';
-                    gbt_word_latch <= '0';
-                    elink_sync_lat <= '1';
-            end case;
+            end case sm_sync;
+            if ( elink_sync_reg = '1' or or_out_of_sync = '1' ) and flag_will_sync = '0' then
+                will_sync <= '1';
+                flag_will_sync <= '1';
+            elsif elink_sync_reg = '0' and or_out_of_sync = '0' and will_sync = '0' then
+                flag_will_sync <= '0';
+            end if;
         end if;
-    end process reg_input;
-
-    gen_elink_printers : for i in 0 to NUMELINKmax-1 generate
-        elink_bit_feeder : entity work.elink_printer_bit_feeder_v2
-            port map (
-                clk              => clk,
-                enable          => elink_control(i).enable,
-                elink_endian_mode      => elink_control(i).endian_mode,
-                elink_output_width  => elink_control(i).output_width,
-                elink_input_width      => elink_control(i).input_width,
-                word_in          => elink_data(i),
-                bit_stream_en        => bit_stream_en,
-                bit_stream_sync    => bit_stream_sync,
-                LINKSconfig           => LINKSconfig,
-                gbt_word_latch        => gbt_word_latch,
-                MSBfirst              => MSBfirst,
-                aurora                => aurora_en(i),
-                read_enable        => elink_read_enable_i(i),
-                bit_stream_out        => bit_stream(i)
-            );
-    end generate gen_elink_printers;
-
-    gen_gbt_stream : for i in 0 to 6 generate
-        signal output_width : std_logic_vector(2 downto 0);
-    begin
-        output_width <= elink_control(i*16).output_width;
-        gbt_bit_stream(32*(i+1)-1 downto 32*i)
-                   <= bit_stream(i*16+15)( 1 downto 0) &
-                      bit_stream(i*16+14)( 1 downto 0) &
-                      bit_stream(i*16+13)( 1 downto 0) &
-                      bit_stream(i*16+12)( 1 downto 0) &
-                      bit_stream(i*16+11)( 1 downto 0) &
-                      bit_stream(i*16+10)( 1 downto 0) &
-                      bit_stream(i*16+ 9)( 1 downto 0) &
-                      bit_stream(i*16+ 8)( 1 downto 0) &
-                      bit_stream(i*16+ 7)( 1 downto 0) &
-                      bit_stream(i*16+ 6)( 1 downto 0) &
-                      bit_stream(i*16+ 5)( 1 downto 0) &
-                      bit_stream(i*16+ 4)( 1 downto 0) &
-                      bit_stream(i*16+ 3)( 1 downto 0) &
-                      bit_stream(i*16+ 2)( 1 downto 0) &
-                      bit_stream(i*16+ 1)( 1 downto 0) &
-                      bit_stream(i*16+ 0)( 1 downto 0) when output_width="000" else
-                      bit_stream(i*16+14)( 3 downto 0) &
-                      bit_stream(i*16+12)( 3 downto 0) &
-                      bit_stream(i*16+10)( 3 downto 0) &
-                      bit_stream(i*16+ 8)( 3 downto 0) &
-                      bit_stream(i*16+ 6)( 3 downto 0) &
-                      bit_stream(i*16+ 4)( 3 downto 0) &
-                      bit_stream(i*16+ 2)( 3 downto 0) &
-                      bit_stream(i*16+ 0)( 3 downto 0) when output_width="001" else
-                      bit_stream(i*16+12)( 7 downto 0) &
-                      bit_stream(i*16+ 8)( 7 downto 0) &
-                      bit_stream(i*16+ 4)( 7 downto 0) &
-                      bit_stream(i*16+ 0)( 7 downto 0) when output_width="010" else
-                      bit_stream(i*16+ 8)(15 downto 0) &
-                      bit_stream(i*16+ 0)(15 downto 0) when output_width="011" else
-                      bit_stream(i*16+ 0)(31 downto 0) when output_width="100" else
-                      (others => '0');
-    end generate gen_gbt_stream;
+    end process sync_readenable;
 
+    elink_sync <= sync_read_enable;
 end Behavioral;
diff --git a/sources/FELIG/emulator/Emulator.vhd b/sources/FELIG/emulator/Emulator.vhd
index 6156d6cedebd27dedb64cd9cb210b82597deb5df..1cd9d00fad48d5b7505575ac6585bb4445c06656 100644
--- a/sources/FELIG/emulator/Emulator.vhd
+++ b/sources/FELIG/emulator/Emulator.vhd
@@ -53,290 +53,255 @@ library UNISIM;
     use work.pcie_package.all;
     use work.centralRouter_package.all;
 
+Library xpm;
+    use xpm.vcomponents.all;
+
 entity Emulator is
     generic (
-        GEN_ILA          : boolean  := false;
-        useGBTdataEmulator    : boolean  := false;
-        sim_emulator        : boolean  := false;
-        LANE_ID          : integer   := 0;
-        NUMELINKmax           : integer := 112;
-        NUMEGROUPmax          : integer := 7
+        useGBTdataEmulator      : boolean  := false;
+        sim_emulator            : boolean  := false;
+        LANE_ID                 : integer   := 0;
+        NUMELINKmax             : integer := 112;
+        NUMEGROUPmax            : integer := 7;
+        PROTOCOL                : std_logic := '0'
     );
     port (
-        --================================
-        -- Clocks & Reset
-        --================================
-        clk_xtal_40      : in  std_logic;
-        --MT
-        --  lane_rxclk_240    : in  std_logic;
-        --  lane_txclk_240    : in  std_logic;
-        lane_rxclk            : in  std_logic;
-        lane_txclk            : in  std_logic;
-
-        rx_clk_div_2_mon          : out  std_logic;
-        tx_clk_div_2_mon          : out  std_logic;
-
-        gth_rxusrclk2            : in  std_logic;
-        gth_txusrclk2            : in  std_logic;
+        clk40                   : in std_logic;
+        lane_rxclk              : in std_logic;
+        lane_txclk              : in std_logic;
+        l1a_int_trigger         : in std_logic;
+        l1a_int_int_id          : in std_logic_vector(15 downto 0);
+        l1a_trigger_out         : out std_logic;
+        gbt_tx_data_228b_out    : out std_logic_vector(227 downto 0);
+        data_ready_tx_out       : out std_logic; --to link_wrapper_fifo
+        gbt_rx_data_120b_in     : in std_logic_vector(119 downto 0);
+        gbt_tx_flag_in          : in std_logic;
+        gbt_rx_flag_in          : in std_logic;
+        lane_control            : in lane_control_type;
+        lane_monitor            : out lane_monitor_type
 
-        --================================
-        -- L1A Interface
-        --================================
-        --internally generated trigger l1a and id. Generation in gt_core_exdes
-        l1a_int_trigger    : in  std_logic;
-        l1a_int_int_id    : in  std_logic_vector(15 downto 0);
-        l1a_trigger_out    : out  std_logic;
-
-        --================================
-        -- DATA
-        --================================
-        --MT
-        --  gbt_tx_data_120b_out          : out std_logic_vector(119 downto 0);
-        --  gbt_rx_data_120b_in           : in  std_logic_vector(119 downto 0);
-        --gbt_tx_data_256b_out          : out std_logic_vector(255 downto 0);
-        gbt_tx_data_228b_out          : out std_logic_vector(227 downto 0);
-        gbt_rx_data_120b_in           : in  std_logic_vector(119 downto 0);
-        gbt_tx_flag_in                : in std_logic;
-        gbt_rx_flag_in                : in std_logic;
-        --================================
-        -- Control and Status Interface
-        --================================
-        lane_control            : in  lane_control_type;
-        lane_monitor            : out  lane_monitor_type;
-        SELECT_RANDOM : in std_logic_vector(0 downto 0);
-        FMEMU_RANDOM_RAM_ADDR         : in std_logic_vector(9 downto 0);    -- Controls the address of the ramblock for the random number generator
-        FMEMU_RANDOM_RAM              : in bitfield_fmemu_random_ram_t_type;
-        FMEMU_RANDOM_CONTROL          : in bitfield_fmemu_random_control_w_type;
-        gbt_frame_locked_in           : in std_logic;
-        --SS (SWAP LSB MSB)
-        --fhCR_REVERSE_10B              : in  std_logic;
-        LINKSconfig                   : in std_logic_vector(2 downto 0)
     );
 end entity Emulator;
 
 architecture Behavioral of Emulator is
-    signal emu_data_120b        : std_logic_vector(119 downto 0)  := (others => '0');
-    signal ext_l1a_id          : std_logic_vector( 15 downto 0)  := (others => '0');
-    signal ext_l1a_pipe          : std_logic_vector(  3 downto 0)  := (others => '0');
-    signal ext_l1a_select        : std_logic              := '0';
-    signal ext_l1a_trigger        : std_logic              := '0';
-    signal ext_l1id            : std_logic              := '0';
-    signal freq_rx_clk          : std_logic_vector( 31 downto 0)  := (others => '0');
-    signal freq_tx_clk          : std_logic_vector( 31 downto 0)  := (others => '0');
-    signal gbt_extracted_bchan      : std_logic              := '0';
-    signal gbt_extractedl1a        : std_logic              := '0';
-    signal l1a_int_trigger_pipe        : std_logic_vector(  3 downto 0)  := (others => '0');
-    signal l1a_int_trigger_piped    : std_logic              := '0';
-    signal gbt_frame_locked        : std_logic              := '0';
-    signal gbt_frame_locked_a      : std_logic_vector( 47 downto 0)  := (others => '0');
-    signal gbt_frame_locked_c      : std_logic              := '0';
-    signal gbt_rx_data_120b        : std_logic_vector(119 downto 0)  := (others => '0');
-    signal gbt_rx_flag          : std_logic              := '0';
-    signal gbt_tx_data_120b        : std_logic_vector(119 downto 0)  := (others => '0');
-    signal gbt_tx_flag          : std_logic              := '0';
-    signal gbtbitsel          : std_logic_vector(  6 downto 0)  := (others => '0');
-    signal b_ch_bit_sel          : std_logic_vector(  6 downto 0)  := (others => '0');
-    signal l1a_id            : std_logic_vector( 15 downto 0)  := (others => '0');
-    signal l1a_trigger          : std_logic              := '0';
-    signal l1id              : std_logic_vector( 15 downto 0)  := (others => '0');
-    signal l1a_ext_int_id              : std_logic_vector( 15 downto 0)  := (others => '0'); --MT
-    signal l1a_ext_int_id_extra              : std_logic_vector( 31 downto 0)  := (others => '0'); --MT
-    signal lane_reset          : std_logic              := '0';
-    --signal tx_120b_from_mach      : std_logic_vector(119 downto  0)  := (others => '0');
-
-    --Phase1: 80b, Phase2: max payload 224
-    signal chB_l1a_id          : std_logic_vector( 23 downto  0)  := (others => '0');
-    signal chB_busy            : std_logic              := '0';
-    signal elink_sync          : std_logic              := '0';
-
-    signal emu_data_re          : std_logic_vector(0 to NUMEGROUPmax-1); --(0 to  4);
-    signal emu_data_out          : array_of_slv_9_0(0 to NUMEGROUPmax-1); --(0 to  4);
-    --ph1
-    --signal elink_data_in        : array_of_slv_9_0(0 to 39);
-    --signal elink_data_re        : std_logic_vector(0 to 39) ;
-    --ph2
-    signal elink_data_in        : array_of_slv_9_0(0 to NUMELINKmax-1);
-    signal elink_data_in_pipe       : array_of_slv_9_0(0 to NUMELINKmax-1);
-    signal elink_data_in_zero       : array_of_slv_9_0(0 to NUMELINKmax-41);
-    signal elink_data_re        : std_logic_vector(0 to NUMELINKmax-1) ;
-    --signal elink_data_re_ph1      : std_logic_vector(0 to NUMELINKmax-1) ;
-    signal elink_data_re_ph2      : std_logic_vector(0 to NUMELINKmax-1) ;
-
-    signal elink_control        : lane_elink_control_array(0 to NUMELINKmax-1);
-    signal emu_control          : lane_emulator_control_array(0 to NUMEGROUPmax-1); --(4 downto 0);
-    constant epath            : std_logic_vector(4 downto 0) := (others => '0');
-    signal TTC_out            : std_logic_vector(9 downto 0) := (others => '0');
-    signal TTC_ToHost_Data        : TTC_ToHost_data_type;
-
-
-    signal ila_data_gen_out      : array_of_slv_17_0  (0 to NUMEGROUPmax-1); --(0 to 4);
-    signal ila_fifo_out        : array_of_slv_9_0  (0 to NUMEGROUPmax-1); --(0 to 4);
-    signal ila_data_gen_we      : std_logic_vector  (0 to NUMEGROUPmax-1); --(0 to 4);
-    signal ila_gbt_word_gen_state  : std_logic_vector  (3 downto 0);
-
-    signal ila_count_chk_out        : array_of_slv_10_0_MT (0 to NUMEGROUPmax-1); --(0 to 4);
-    signal ila_count_chk_out2        : array_of_slv_10_0_MT(0 to NUMEGROUPmax-1); --(0 to 4);
-    signal ila_count_upstfifochk     : array_of_slv_10_0_MT(0 to NUMEGROUPmax-1); --(0 to 4);
-    signal ila_fifo_flush            : std_logic_vector    (0 to NUMEGROUPmax-1); --(0 to 4);
-    signal ila_isEOP_chk2 : std_logic_vector               (0 to NUMEGROUPmax-1); --(0 to 4);
-    signal ila_efifoDout_8b10b      : array_of_slv_9_0     (0 to NUMEGROUPmax-1); --(0 to 4);
-    signal ila_enc10bitRdy          : std_logic_vector     (0 to NUMEGROUPmax-1); --(0 to 4);
-    signal ila_efifoFull : std_logic_vector                (0 to NUMEGROUPmax-1); --(0 to 4);
-    signal ila_efifoEmpty : std_logic_vector               (0 to NUMEGROUPmax-1); --(0 to 4);
-    signal ila_efifoPfull : std_logic_vector               (0 to NUMEGROUPmax-1); --(0 to 4);
-    signal ila_elink_data_re : std_logic_vector            (0 to NUMEGROUPmax-1); --(0 to 4);
-    signal ila_efifoDoutRdy : std_logic_vector             (0 to NUMEGROUPmax-1); --(0 to 4);
-    signal chunk_length_out : array_of_slv_11_0_MT         (0 to NUMEGROUPmax-1); --(0 to 4);
-    --
-
-    signal ila_count_pyld : std_logic_vector(8 downto 0) := (others => '0');
-
-    signal ila_testpass_gwchk : std_logic_vector(3 downto 0) := "0000";
-    signal ila_dist_gwchk : std_logic_vector(3 downto 0) := "0000";
-    signal ila_word10b_gwchk : std_logic_vector(9 downto 0) := (others => '0');
-
-    signal ila_phlck_gwchk : std_logic := '0';  --decide the 2b phase in the 10b word
-    signal ila_en_gwchk : std_logic := '0';
-    signal ila_count_gwchk : std_logic_vector(2 downto 0) := "000";
-    signal ila_count_start_gwchk : std_logic_vector(1 downto 0) := "00";
-    --
-
-    signal payload_224b        : std_logic_vector(223 downto  0)  := (others => '0');
-    signal payload_224b_pipe  : array_of_slv_223_0(0 to 1);
-    --signal payload_224b_ph1        : std_logic_vector(223 downto  0)  := (others => '0');
-    signal payload_224b_ph2        : std_logic_vector(223 downto  0)  := (others => '0');
-    --signal payload_224b_pipe_ph1  : array_of_slv_223_0(0 to 1);
-    signal payload_224b_pipe_ph2  : array_of_slv_223_0(0 to 1);
-    signal HDR_4b             : std_logic_vector(3 downto 0);
-    signal HDR_4b_pipe        : array_of_slv_3_0(0 to 1);
-    signal IC_2b              : std_logic_vector(1 downto 0);
-    signal IC_2b_pipe         : array_of_slv_1_0(0 to 1);
-    signal EC_2b              : std_logic_vector(1 downto 0);
-    signal EC_2b_pipe         : array_of_slv_1_0(0 to 1);
-    signal FEC_48b            : std_logic_vector(47 downto 0);
-    signal FEC_48b_pipe       : array_of_slv_47_0(0 to 1);
-    signal LM_2b              : std_logic_vector(1 downto 0);
-    signal LM_2b_pipe         : array_of_slv_1_0(0 to 1);
-
-    --RL payload
+    constant epath                          : std_logic_vector(4 downto 0) := (others => '0');
+
+    signal ext_l1a_id                       : std_logic_vector( 15 downto 0)  := (others => '0');
+    signal ext_l1a_select                   : std_logic              := '0';
+    signal ext_l1a_trigger                  : std_logic              := '0';
+    signal gbt_extracted_bchan              : std_logic              := '0';
+    signal gbt_extractedl1a                 : std_logic              := '0';
+    signal l1a_int_trigger_clktx            : std_logic              := '0';
+    signal l1a_int_trigger_clktx_onecycle   : std_logic              := '0';
+    signal l1a_int_trigger_clktx_delay      : std_logic              := '0';
+    signal link_aligned                     : std_logic              := '0';
+    signal gbt_frame_locked_a               : std_logic_vector( 47 downto 0)  := (others => '0');
+    signal gbt_frame_locked_c               : std_logic              := '0';
+    signal gbt_rx_data_120b                 : std_logic_vector(119 downto 0)  := (others => '0');
+    signal gbt_rx_flag                      : std_logic              := '0';
+    signal gbt_tx_flag                      : std_logic              := '0';
+    signal gbtbitsel                        : std_logic_vector(  6 downto 0)  := (others => '0');
+    signal b_ch_bit_sel                     : std_logic_vector(  6 downto 0)  := (others => '0');
+    signal l1a_id                           : std_logic_vector( 15 downto 0)  := (others => '0');
+    signal l1a_trigger                      : std_logic              := '0';
+    signal l1id                             : std_logic_vector( 15 downto 0)  := (others => '0');
+    signal l1a_ext_int_id                   : std_logic_vector( 15 downto 0)  := (others => '0'); --MT
+    signal l1a_ext_int_id_extra             : std_logic_vector( 31 downto 0)  := (others => '0'); --MT
+    signal l1a_int_int_id_tx_clk            : std_logic_vector(15 downto 0);
+    signal elink_sync                       : std_logic              := '0';
+    signal elink_sync_reg                   : std_logic;
+    signal emu_data_re                      : std_logic_vector(0 to NUMEGROUPmax-1); --(0 to  4);
+    signal emu_data_out                     : array_of_slv_9_0(0 to NUMEGROUPmax-1); --(0 to  4);
+    signal elink_data_in                    : array_of_slv_9_0(0 to NUMELINKmax-1);
+    signal elink_data_re                    : std_logic_vector(0 to NUMELINKmax-1) ;
+    signal elink_control                    : lane_elink_control_array(0 to NUMELINKmax-1);
+    signal emu_control                      : lane_emulator_control_array(0 to NUMEGROUPmax-1); --(4 downto 0);
+    signal fmemu_random                     : lane_emu_random_control;
+    signal TTC_out                          : std_logic_vector(9 downto 0) := (others => '0');
+    signal payload_225b_ph2                 : std_logic_vector(224 downto  0)  := (others => '0');
+    signal payload_225b_pipe_ph2            : array_of_slv_224_0(0 to 1);
+    signal HDR_4b                           : std_logic_vector(3 downto 0);
+    signal HDR_4b_pipe                      : array_of_slv_3_0(0 to 1);
+    signal IC_2b                            : std_logic_vector(1 downto 0);
+    signal IC_2b_pipe                       : array_of_slv_1_0(0 to 1);
+    signal EC_2b                            : std_logic_vector(1 downto 0);
+    signal EC_2b_pipe                       : array_of_slv_1_0(0 to 1);
+    signal FEC_48b                          : std_logic_vector(47 downto 0);
+    signal FEC_48b_pipe                     : array_of_slv_47_0(0 to 1);
+    signal MSBfirst                         : std_logic := '0';
+    signal l1a_counter_reset                : std_logic;
+    --signal FEC                              : std_logic;
+    signal DATARATE                         : std_logic;
+    signal l1a_ext_counter_reset            : std_logic := '0';
+    signal flag_ext_counter_reset           : std_logic := '0';
+    signal ext_counter_l1a_trigger          : std_logic := '0';
+    signal ECR                              : std_logic := '0';
+    signal ttc_fifo_rst                     : std_logic := '1';
+    signal ttc_fifo_wr_en                   : std_logic := '0';
+    signal ttc_fifo_rd_en                   : std_logic := '0';
+    signal ttc_fifo_full                    : std_logic := '0';
+    signal ttc_fifo_empty                   : std_logic := '0';
+    signal ttc_fifo_din, ttc_fifo_dout      : std_logic_vector(9 downto 0) := (others => '0');
+    signal TTC_out_fifo                     : std_logic_vector(9 downto 0) := (others => '0');
+    signal TTC_out_fifo_dly                 : std_logic_vector(9 downto 0) := (others => '0');
+    signal lane_reset                       : std_logic := '0';
+    signal egroup_enable                    : std_logic_vector(0 to NUMEGROUPmax-1);
+    signal flag_data_gen                    : std_logic_vector(0 to NUMEGROUPmax-1);
+    signal out_of_sync                      : std_logic_vector(NUMEGROUPmax-1 downto 0) := (others => '0');
+    signal or_out_of_sync                   : std_logic;
+    signal flag_sync                        : std_logic_vector(0 to NUMEGROUPmax-1);
+
+--RL to be implemented
+--signal aurora_en                    : std_logic_vector(0 to NUMELINKmax-1);
+--signal aurora_en_EGROUP             : std_logic_vector(0 to NUMEGROUPmax-1);
+begin
 
-    --signal payload_80b_gbt                        : std_logic_vector( 79 downto  0)  := (others => '0');
-    --signal payload_112b_lpgbt_DR512_FEC5        : std_logic_vector(111 downto  0)  := (others => '0');
-    --signal payload_96b_lpgbt_DR512_FEC12        : std_logic_vector( 95 downto  0)  := (others => '0');
-    --signal payload_224b_lpgbt_DR1024_FEC5        : std_logic_vector(223 downto  0)  := (others => '0');
-    --signal payload_192b_lpgbt_DR1024_FEC12      : std_logic_vector(191 downto  0)  := (others => '0');
+    lane_monitor.global.l1a_id      <= X"0000" & l1a_id;
+    lane_monitor.gbt.frame_locked   <= gbt_frame_locked_c;
 
-    -- RL sim only. delete later
-    --signal payload_egroup0    : std_logic_vector (31 downto 0)  := (others => '0');
-    --signal payload_egroup1    : std_logic_vector (31 downto 0)  := (others => '0');
-    --signal payload_egroup2    : std_logic_vector (31 downto 0)  := (others => '0');
-    --signal payload_egroup3    : std_logic_vector (31 downto 0)  := (others => '0');
-    --signal payload_egroup4    : std_logic_vector (31 downto 0)  := (others => '0');
-    --signal payload_egroup5    : std_logic_vector (31 downto 0)  := (others => '0');
-    --signal payload_egroup6    : std_logic_vector (31 downto 0)  := (others => '0');
+    l1a_trigger_out                 <= l1a_trigger;
 
-    signal payload_egroup0_ph2    : std_logic_vector (31 downto 0)  := (others => '0');
-    signal payload_egroup1_ph2    : std_logic_vector (31 downto 0)  := (others => '0');
-    signal payload_egroup2_ph2    : std_logic_vector (31 downto 0)  := (others => '0');
-    signal payload_egroup3_ph2    : std_logic_vector (31 downto 0)  := (others => '0');
-    signal payload_egroup4_ph2    : std_logic_vector (31 downto 0)  := (others => '0');
-    signal payload_egroup5_ph2    : std_logic_vector (31 downto 0)  := (others => '0');
-    signal payload_egroup6_ph2    : std_logic_vector (31 downto 0)  := (others => '0');
+    gbt_rx_data_120b                <= gbt_rx_data_120b_in;
+    gbt_rx_flag                     <= gbt_rx_flag_in;  --from gbtTxRx_FELIX
+    gbt_tx_flag                     <= gbt_tx_flag_in;  --from gbtTxRx_FELIX
 
-    --RL others
+    emu_control                     <= lane_control.emulator;
+    elink_control                   <= lane_control.elink;
+    fmemu_random                    <= lane_control.fmemu_random;
+    link_aligned                    <= lane_control.global.aligned; --(not anymore) clock is correct, GT_RX_WORD_CLK. from alignment_done_f in sources/FELIG/LinkWrapper/FLX_LpGBT_FE_Wrapper_FELIG.vhd
+    --FEC                             <= lane_control.global.FEC; -- not used
+    DATARATE                        <= lane_control.global.DATARATE; -- XPM not needed, no clocks involved
 
-    type STATEM  is (st_idle, st_sync, st_generate) ;
-    signal state : STATEM := st_idle;
+    xpm_lane_reset : xpm_cdc_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0
+        )
+        port map(
+            src_clk => '0',
+            src_in => lane_control.global.lane_reset,
+            dest_clk => lane_rxclk,
+            dest_out => lane_reset
+        );
 
-    signal start_gen        : std_logic;
-    signal gen_done         : std_logic_vector(0 to NUMEGROUPmax-1) := (others => '0');
-    constant gen_done_1     : std_logic_vector(0 to NUMEGROUPmax-1) := (others => '1');
-    constant gen_done_0     : std_logic_vector(0 to NUMEGROUPmax-1) := (others => '0');
-    signal egroup_enable    : std_logic_vector(0 to NUMEGROUPmax-1);
-    signal flag_data_gen    : std_logic_vector(0 to NUMEGROUPmax-1);
-    signal flag_sync        : std_logic_vector(0 to NUMEGROUPmax-1);
-    signal count_sync       : std_logic_vector(0 to 5) := "000000";
-    signal sync_read_enable : std_logic :='0';
+    xpm_ext_l1a_select : xpm_cdc_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0
+        )
+        port map(
+            src_clk => '0',
+            src_in => lane_control.global.l1a_source,
+            dest_clk => lane_txclk,
+            dest_out => ext_l1a_select
+        );
 
-    signal or_enable        : std_logic;
-    signal fifo_empty       : std_logic_vector(0 to 6);
+    xpm_gbtbitsel : xpm_cdc_array_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0,
+            WIDTH => 7
+        )
+        port map(
+            src_clk => '0',
+            src_in => lane_control.global.a_ch_bit_sel,
+            dest_clk => lane_rxclk,
+            dest_out => gbtbitsel
+        );
 
-    signal out_of_sync      : std_logic_vector(NUMEGROUPmax-1 downto 0) := (others => '0');
-    signal or_out_of_sync   : std_logic;
-    signal will_sync        : std_logic := '0';
-    signal flag_will_sync   : std_logic := '0';
+    xpm_b_ch_bit_sel : xpm_cdc_array_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0,
+            WIDTH => 7
+        )
+        port map(
+            src_clk => '0',
+            src_in => lane_control.global.b_ch_bit_sel,
+            dest_clk => lane_rxclk,
+            dest_out => b_ch_bit_sel
+        );
 
-    --signal elink_control_enable_array   : array_of_slv_7_0  (NUMEGROUP-1 downto 0);
-    --signal elink_data_re_array          : array_of_slv_7_0  (NUMEGROUP-1 downto 0);
-    --signal elink_data_re_array_0        : array_of_slv_7_0  (NUMEGROUP-1 downto 0);
+    xpm_MSBfirst : xpm_cdc_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0
+        )
+        port map(
+            src_clk => '0',
+            src_in => lane_control.global.MSB,
+            dest_clk => lane_txclk,
+            dest_out => MSBfirst
+        );
 
-    --adding l1id external counter reset.
-    signal l1a_ext_counter_reset    : std_logic := '0';
-    signal flag_ext_counter_reset   : std_logic := '0';
-    signal MSBfirst         : std_logic := '0';
+    xpm_elink_sync : xpm_cdc_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0
+        )
+        port map(
+            src_clk => '0',
+            src_in => lane_control.global.elink_sync,
+            dest_clk => lane_txclk,
+            dest_out => elink_sync_reg
+        );
 
-    --signal  gbt_tx_data_256b_out_temp  : std_logic_vector(255 downto 0);
-    signal  gbt_tx_data_228b_out_temp  : std_logic_vector(227 downto 0);
-    --signal  gbt_tx_data_228b_out_temp_ph1  : std_logic_vector(227 downto 0);
-    signal  gbt_tx_data_228b_out_temp_ph2  : std_logic_vector(227 downto 0);
+    xpm_l1a_counter_reset : xpm_cdc_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0
+        )
+        port map(
+            src_clk => '0',
+            src_in => lane_control.global.l1a_counter_reset,
+            dest_clk => lane_txclk,
+            dest_out => l1a_counter_reset
+        );
 
-    --RL ILA
-    --signal ila_l1a_trigger              : std_logic;
-    --signal ila_l1a_id                   : std_logic_vector(15 downto 0);
-    --signal ila_payload_80b_gbt          : std_logic_vector(79 downto 0);
-    --signal ila_clk_xtal_40              : std_logic;
-    --signal ila_gbt_tx_data_120b         : std_logic_vector(119 downto 0);
-    --signal ila_emu_data_out             : array_of_slv_9_0(0 to NUMEGROUPmax-1);
-    --signal ila_emu_control_output_width : array_of_slv_2_0(0 to NUMEGROUPmax-1);
+    xpm_l1a_int_trigger : xpm_cdc_single generic map(
+            DEST_SYNC_FF => 4,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 1
+        )
+        port map(
+            src_clk => clk40,
+            src_in => l1a_int_trigger,
+            dest_clk => lane_txclk,
+            dest_out => l1a_int_trigger_clktx
+        );
 
-    --signal payload_80b_gbt_test         : std_logic_vector(79 downto 0);
-    --signal payload_80b_gbt_test_ph1     : std_logic_vector(79 downto 0);
-    signal payload_80b_gbt_test_ph2     : std_logic_vector(79 downto 0);
-    signal aurora_en                    : std_logic_vector(0 to NUMELINKmax-1);
-    signal aurora_en_EGROUP             : std_logic_vector(0 to NUMEGROUPmax-1);
---
---    COMPONENT  ila_0 IS
---    PORT (
---    clk : IN STD_LOGIC;
---    probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
---    probe1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
---    probe2 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
---    probe3 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
---    probe4 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
---    probe5 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
---    probe6 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
---    probe7 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
---    probe8 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
---    probe9 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
---    probe10 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
---    probe11 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
---    probe12 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
---    probe13 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
---    probe14 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
---    probe15 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
---    probe16 : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
---    probe17 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
---    probe18 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
---    probe19 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
---    probe20 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
---    probe21 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
---    probe22 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
---    probe23 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
---    probe24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
---    probe25 : IN STD_LOGIC_VECTOR(119 DOWNTO 0));
---  END COMPONENT;
-begin
+    xpm_l1a_int_int_id : xpm_cdc_array_single generic map(
+            DEST_SYNC_FF => 4,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 1,
+            WIDTH => 16
+        )
+        port map(
+            src_clk => clk40,
+            src_in => l1a_int_int_id,
+            dest_clk => lane_txclk,
+            dest_out => l1a_int_int_id_tx_clk
+        );
 
-    l1a_trigger_out <= l1a_trigger;
+    --================================================================
+    -- Frame Locked monitoring
+    --================================================================
 
-    --MT  u0_mon: process(lane_rxclk_240)
     u0_mon: process(lane_rxclk)
     begin
-        --MT    if rising_edge(lane_rxclk_240) then
         if rising_edge(lane_rxclk) then
             if (gbt_rx_flag = '1') then
                 gbt_frame_locked_a(47 downto 1) <= gbt_frame_locked_a(46 downto 0);
-                gbt_frame_locked_a(0) <= gbt_frame_locked;
+                gbt_frame_locked_a(0) <= link_aligned;
                 if gbt_frame_locked_a = x"FFFFFFFFFFFF" then
                     gbt_frame_locked_c <= '1';
                 else
@@ -346,237 +311,176 @@ begin
         end if;
     end process u0_mon;
 
-    lane_monitor.gbt.frame_locked    <= gbt_frame_locked_c  ;
-    ext_l1a_select            <= lane_control.global.l1a_source      ;
-    gbtbitsel              <= lane_control.global.a_ch_bit_sel      ;
-    b_ch_bit_sel        <= lane_control.global.b_ch_bit_sel      ;
-    emu_control        <= lane_control.emulator          ;
-    elink_control        <= lane_control.elink            ;
-    lane_monitor.global.l1a_id      <= X"0000" & l1a_id                         ; --RL
-    MSBfirst <= lane_control.global.MSB;
-    --================================================================
-    -- Frequency Monitors
-    --================================================================
-    gen_freq_counter : if sim_emulator = false generate
-        --MT    freq_counter_lane_rxclk_240: entity work.clock_frequncy_counter
-        freq_counter_lane_rxclk: entity work.clock_frequncy_counter
-            generic map (
-                clk_timebase_frequency    => 40000000.0,  -- Units: Hz
-                accumulation_period    => 32.0,      -- Units: Seconds  / 32-bit counter allows max 4,294,967,295 counts; @ 1 second can only count to 50,000,000
-                clk_meas_prescale_factor  => 5 -- 4 should be enough, but just to be sure...
-            -- clk_meas_prescale divides down the clk_meas frequency
-            -- (clk_meas freq) / (2^clk_meas_prescale_factor)  must be less than (clk_timebase freq) / 2
-            -- values other than 1 will limit resolution.
-            -- Minimum value = 1
-            )
-            -- Port list
-            port map (
-                -- stable local clock input
-                -- must be at least twice as fast at the clk_meas / clk_meas_prescale
-                clk_timebase      => clk_xtal_40,
-                -- clk to measure
-                --MT        clk_meas      => lane_rxclk_240,
-                clk_meas      => lane_rxclk,
-                -- output count
-                frequency      => freq_rx_clk, -- because prescale and accumulation are the same value, unit here will be in Hz.
-                div_2_clock_signal    => rx_clk_div_2_mon,
-                prescaled_clock_signal          => open
-            );
-
-        --    freq_counter_lane_txclk_240: entity work.clock_frequncy_counter
-        freq_counter_lane_txclk: entity work.clock_frequncy_counter
-            generic map (
-                clk_timebase_frequency    => 40000000.0,  -- Units: Hz
-                accumulation_period    => 32.0,      -- Units: Seconds  / 32-bit counter allows max 4,294,967,295 counts; @ 1 second can only count to 50,000,000
-                clk_meas_prescale_factor  => 5 -- 4 should be enough, but just to be sure...
-            -- clk_meas_prescale divides down the clk_meas frequency
-            -- (clk_meas freq) / (2^clk_meas_prescale_factor)  must be less than (clk_timebase freq) / 2
-            -- values other than 1 will limit resolution.
-            -- Minimum value = 1
-            )
-            -- Port list
-            port map (
-                -- stable local clock input
-                -- must be at least twice as fast at the clk_meas / clk_meas_prescale
-                clk_timebase      => clk_xtal_40,
-                -- clk to measure
-                --MT        clk_meas      => lane_txclk_240,
-                clk_meas      => lane_txclk,
-                -- output count
-                frequency      => freq_tx_clk, -- because prescale and accumulation are the same value, unit here will be in Hz.
-                div_2_clock_signal    => tx_clk_div_2_mon,
-                prescaled_clock_signal          => open
-            );
-    end generate gen_freq_counter;
-
-    gbt_frame_locked <= gbt_frame_locked_in;
-    gbt_rx_data_120b <= gbt_rx_data_120b_in;
-    gbt_rx_flag <=  gbt_rx_flag_in;  --from gbtTxRx_FELIX
-    gbt_tx_flag <= gbt_tx_flag_in;  --from gbtTxRx_FELIX
-
     --================================================================
     -- L1A Extraction
     --================================================================
-    --****************************
-    --*******EXTERNAL TRIGGER*****
-    --*******EXT L1A, INT L1AID***
-    --****************************
-    --1a) Extraction from RX_DATA (External)
+    -- External trigger
+
+    --a channel select
     l1a_mux: entity work.mux_128_sync
         port map (
-            --    clk              => rx_frame_clk_bufr,
-            --MT      clk      => lane_rxclk_240,
-            clk      => lane_rxclk,
+            clk              => lane_rxclk,
             bit_input(127 downto 121)  => "0000000" ,
-            bit_input(120)    => '1',
-            bit_input(119 downto 0)  => gbt_rx_data_120b,
-            bit_select    => gbtbitsel,
-            bit_output_sync    => gbt_extractedl1a,
-            bit_output_aync    => open
+            bit_input(120)        => '1',
+            bit_input(119 downto 0)    => gbt_rx_data_120b,
+            bit_select          => gbtbitsel,
+            bit_output_sync        => gbt_extractedl1a,
+            bit_output_aync        => open
         );
 
+    --b channel select
     bchan_mux: entity work.mux_128_sync
         port map (
-            --    clk              => rx_frame_clk_bufr,
-            --MT      clk      => lane_rxclk_240,
-            clk      => lane_rxclk,
+            clk              => lane_rxclk,
             bit_input(127 downto 121)  => "0000000" ,
-            bit_input(120)    => '1',
-            bit_input(119 downto 0)  => gbt_rx_data_120b,
-            bit_select    => b_ch_bit_sel,
-            bit_output_sync    => gbt_extracted_bchan,
-            bit_output_aync    => open
+            bit_input(120)        => '1',
+            bit_input(119 downto 0)    => gbt_rx_data_120b,
+            bit_select          => b_ch_bit_sel,
+            bit_output_sync        => gbt_extracted_bchan,
+            bit_output_aync        => open
         );
 
-    --1b) L1A Domain Cross (External)
-    --MT  ext_l1a_generator_domain_cross_a: process(TTC_out(0), lane_txclk_240)
-    ext_l1a_generator_domain_cross_a: process(TTC_out(0), lane_txclk)
-    begin
-        if (TTC_out(0) = '1') then
-            ext_l1a_pipe(0) <= '1';
-        --MT    elsif lane_txclk_240'event and lane_txclk_240='1' then
-        elsif lane_txclk'event and lane_txclk='1' then
-            if (ext_l1a_pipe(2) = '1') then
-                ext_l1a_pipe(0) <= '0';
-            end if;
-        end if;
-    end process;
+    --ttc decoder
+    ttc_wrapper_comp : entity work.ttc_wrapper_felig
+        port map (
+            a_data_in      => gbt_extractedl1a,
+            b_data_in      => gbt_extracted_bchan,
+            ttc_strobe      => gbt_rx_flag,
+            TTC_out        => TTC_out,
+            clk240        => lane_rxclk,
+            BUSY        => open,
+            L1ID_Bch      => open,
+            TTC_ToHost_Data_out  => open
+        );
 
-    --MT  ext_l1a_generator_domain_cross_b: process(lane_txclk_240)
-    ext_l1a_generator_domain_cross_b: process(lane_txclk)
-    begin
-        --MT    if lane_txclk_240'event and lane_txclk_240='1' then
-        if lane_txclk'event and lane_txclk='1' then
-            ext_l1a_pipe(1)  <= ext_l1a_pipe(0);
-            ext_l1a_pipe(2)  <= ext_l1a_pipe(1);
-            ext_l1a_pipe(3)  <= ext_l1a_pipe(2);
-        end if;
-    end process;
+    --clock domain crossing
+    ttc_fifo_rst    <= (not link_aligned) or lane_reset;
+    ttc_fifo_wr_en  <= '1';
+    ttc_fifo_rd_en  <= not ttc_fifo_empty;
+    ttc_fifo_din    <= TTC_out;
+    TTC_out_fifo    <= ttc_fifo_dout;
+
+    ttc_fifo: xpm_fifo_async
+        generic map
+    (
+            FIFO_MEMORY_TYPE => "auto",
+            FIFO_WRITE_DEPTH => 16,
+            RELATED_CLOCKS => 0,
+            WRITE_DATA_WIDTH => 10,
+            READ_MODE => "fwft",
+            FIFO_READ_LATENCY => 0,
+            FULL_RESET_VALUE => 1,
+            USE_ADV_FEATURES => "0000",
+            READ_DATA_WIDTH => 10,
+            CDC_SYNC_STAGES => 2,
+            WR_DATA_COUNT_WIDTH => 1,
+            PROG_FULL_THRESH => 10,
+            RD_DATA_COUNT_WIDTH => 1,
+            PROG_EMPTY_THRESH => 6,
+            DOUT_RESET_VALUE => "0",
+            ECC_MODE => "no_ecc"
+        )
+        port map(
+            sleep => '0',
+            rst => ttc_fifo_rst,
+            wr_clk => lane_rxclk,
+            wr_en => ttc_fifo_wr_en,
+            din => ttc_fifo_din,
+            full => ttc_fifo_full,
+            prog_full => open,
+            wr_data_count => open,
+            overflow => open,
+            wr_rst_busy => open,
+            almost_full => open,
+            wr_ack => open,
+            rd_clk => lane_txclk,
+            rd_en => ttc_fifo_rd_en,
+            dout => ttc_fifo_dout,
+            empty => ttc_fifo_empty,
+            prog_empty => open,
+            rd_data_count => open,
+            underflow => open,
+            rd_rst_busy => open,
+            almost_empty => open,
+            data_valid => open,
+            injectsbiterr => '0',
+            injectdbiterr => '0',
+            sbiterr => open,
+            dbiterr => open
+        );
 
-    --MT  ext_l1a_generator: process(lane_txclk_240)
+    --generates external l1a and final for counting
     ext_l1a_generator: process(lane_txclk)
     begin
-        --MT    if lane_txclk_240'event and lane_txclk_240='1' then
         if lane_txclk'event and lane_txclk='1' then
-            if (ext_l1a_pipe (3) = '0' and ext_l1a_pipe(2) = '1') then
-                ext_l1a_trigger <= '1';
-                --internally generated, but relying on external l1a
-                ext_l1a_id <= l1a_ext_int_id;
+            TTC_out_fifo_dly <= TTC_out_fifo;
+            if TTC_out_fifo_dly(0) = '1' and TTC_out_fifo(0) = '0' then
+                ext_l1a_trigger         <= '1';
+                ext_counter_l1a_trigger <= '0';
+                ext_l1a_id              <= l1a_ext_int_id;
+            elsif TTC_out_fifo_dly(0) = '0' and TTC_out_fifo(0) = '1' then
+                ext_l1a_trigger         <= '0';
+                ext_counter_l1a_trigger <= '1';
             else
-                ext_l1a_trigger <= '0';
+                ext_l1a_trigger         <= '0';
+                ext_counter_l1a_trigger <= '0';
             end if;
         end if;
     end process;
 
+    ECR <= TTC_out_fifo(3);
 
-
-    --1c) L1A ID internal generation based on External trigger
-    l1a_ext_int_id_counter : dsp_counter
-        PORT MAP (
-            --MT      CLK          => lane_txclk_240,
-            CLK          => lane_txclk,
-            CE              => ext_l1a_trigger,
-            SCLR          => '0',
-            UP    => '1',
-            LOAD          => l1a_ext_counter_reset,--'0',
-            L    => X"000000000000",
-            Q(47 downto 16)  => l1a_ext_int_id_extra, --open,
-            Q(15 downto  0)  => l1a_ext_int_id
-        );
-    --
-    --RL: adding l1id external counter reset.
+    --generates load signal for counter
     process(lane_txclk)
     begin
         if lane_txclk'event and lane_txclk='1' then
-            if lane_control.global.l1a_counter_reset = '1' and flag_ext_counter_reset = '0' then
+            if (l1a_counter_reset = '1' or ECR = '1') and flag_ext_counter_reset = '0' then
                 l1a_ext_counter_reset <= '1';
                 flag_ext_counter_reset <= '1';
             elsif l1a_ext_int_id  = X"0000" then
                 l1a_ext_counter_reset <= '0';
-                if lane_control.global.l1a_counter_reset = '0' then
+                if l1a_counter_reset = '0' and ECR = '0' then
                     flag_ext_counter_reset <= '0';
                 end if;
             end if;
         end if;
     end process;
 
+    --l1a id counter
+    l1a_ext_int_id_counter : dsp_counter
+        PORT MAP (
+            CLK                => lane_txclk,
+            CE                => ext_counter_l1a_trigger,
+            SCLR              => '0',
+            UP              => '1',
+            LOAD              => l1a_ext_counter_reset,
+            L                 => X"000000000000",
+            Q(47 downto 16)   => l1a_ext_int_id_extra,
+            Q(15 downto  0)   => l1a_ext_int_id
+        );
 
-    --****************************
-    --*******INTERNAL TRIGGER*****
-    --*******INT L1A, INT L1AID***
-    --****************************
-    --2) From generated trigger in EmulatorWrapper (Internal)
-    --MT  l1a_generator_domain_cross_a: process(l1a_int_trigger, lane_txclk_240)
-    l1a_generator_domain_cross_a: process(l1a_int_trigger, lane_txclk)
-    begin
-        --    if (gbt_extractedl1a = '1') then
-        if (l1a_int_trigger = '1') then
-            l1a_int_trigger_pipe(0) <= '1';
-        --MT    elsif (lane_txclk_240'event and lane_txclk_240='1') then
-        elsif (lane_txclk'event and lane_txclk='1') then
-            if (l1a_int_trigger_pipe(2) = '1') then
-                l1a_int_trigger_pipe(0) <= '0';
-            end if;
-        end if;
-    end process;
-
-    --MT  l1a_generator_domain_cross_b: process(lane_txclk_240)
-    l1a_generator_domain_cross_b: process(lane_txclk)
-    begin
-        --MT    if (lane_txclk_240'event and lane_txclk_240='1') then
-        if (lane_txclk'event and lane_txclk='1') then
-            l1a_int_trigger_pipe(1)  <= l1a_int_trigger_pipe(0);
-            l1a_int_trigger_pipe(2)  <= l1a_int_trigger_pipe(1);
-            l1a_int_trigger_pipe(3)  <= l1a_int_trigger_pipe(2);
-        end if;
-    end process;
-
-    --MT  l1a_generator: process(lane_txclk_240)
+    -- Internal trigger
     l1a_generator: process(lane_txclk)
     begin
-        --MT    if (lane_txclk_240'event and lane_txclk_240='1') then
-        if (lane_txclk'event and lane_txclk='1') then
-            if (l1a_int_trigger_pipe (3) = '0' and l1a_int_trigger_pipe(2) = '1') then
-                l1a_int_trigger_piped <= '1';
-                l1id <= l1a_int_int_id; --MT for debugging set to const X"2DE4";
+        if lane_txclk'event and lane_txclk='1' then
+            l1a_int_trigger_clktx_delay <= l1a_int_trigger_clktx;
+            if l1a_int_trigger_clktx_delay = '0' and l1a_int_trigger_clktx = '1' then
+                l1a_int_trigger_clktx_onecycle <= '1';
+                l1id <= l1a_int_int_id_tx_clk;
             else
-                l1a_int_trigger_piped <= '0';
+                l1a_int_trigger_clktx_onecycle <= '0';
             end if;
         end if;
     end process;
 
-    --****************************
-    --*****L1a Selection Mux******
-    --****************************
-    --****************************
-    --3) Selection between External and Internal trigger
-    --MT  l1a_ext_mux: process(lane_txclk_240)
+    -- Trigger select mux
+
     l1a_ext_mux: process(lane_txclk)
     begin
         --MT    if lane_txclk_240'event and lane_txclk_240='1' then
         if lane_txclk'event and lane_txclk='1' then
             if (ext_l1a_select = '0') then
-                l1a_trigger  <= l1a_int_trigger_piped;
+                l1a_trigger  <= l1a_int_trigger_clktx_onecycle;
                 l1a_id    <= l1id;
             else
                 l1a_trigger  <= ext_l1a_trigger;
@@ -585,29 +489,9 @@ begin
         end if;
     end process;
 
-
-
     --================================================================
     -- Data Emulator
     --================================================================
-    --****************************
-    --****************************
-    --1a) data generation: payload
-
-    --  gbt_tx_data_120b_out <= gbt_tx_data_120b;
-
-    --gbt_loopback_fifo_control: process (lane_txclk_240)
-    --begin
-    --  if (lane_txclk_240'event and lane_txclk_240 = '1') then
-    --    gbt_tx_data_120b <= emu_data_120b;
-    --  end if;
-    --end process gbt_loopback_fifo_control;
-    --EMU_DATA_MUX: process(lane_txclk_240)
-    --begin
-    --  if lane_txclk_240'event and lane_txclk_240='1' then
-    --    emu_data_120b <= tx_120b_from_mach;
-    --  end if;
-    --end process;
 
     --PROTOCOL, DATARATE, FEC. 0.X,X = 4.8 Gbps    (GBT   Phase1),
     --                         1,0.0 = 5.12 FEC5   (lpGBT Phase2),
@@ -615,85 +499,33 @@ begin
     --                         1.1,0 = 10.24 FEC5  (lpGBT Phase2),
     --                         1.1,1 = 10.24 FEC12 (lpGBT Phase2)
 
-    gbt_tx_data_228b_out <= gbt_tx_data_228b_out_temp_ph2;
-    --RL restructured. only 224 data bits, IC an EC are used in the lpgbt wrapper
-    --  gbt_tx_data_228b_out_temp <= x"000000000000000000000000000"       &
-    --                               HDR_4b_pipe(1)                       &
-    --                               IC_2b_pipe(1)                        &
-    --                               EC_2b_pipe(1)                        &
-    --                               payload_224b_pipe(1)(159 downto 144) &
-    --                               payload_224b_pipe(1)(127 downto 112) &
-    --                               payload_224b_pipe(1)( 95 downto  80) &
-    --                               payload_224b_pipe(1)( 63 downto  48) &
-    --                               payload_224b_pipe(1)( 31 downto  16) &
-    --                               FEC_48b_pipe(1)(31 downto 0)         when (LINKSconfig(2) = '0') else
-    --                               IC_2b_pipe(1)                        &
-    --                               EC_2b_pipe(1)                        &
-    --                               payload_224b_pipe(1)                 ; --when lpgbt
-    gbt_tx_data_228b_out_temp <= gbt_tx_data_228b_out_temp_ph2; --only used for ila
-
-
-    --  gbt_tx_data_228b_out_temp_ph1 <= x"000000000000000000000000000"       &
-    --                                  HDR_4b_pipe(1)                       &
-    --                                  IC_2b_pipe(1)                        &
-    --                                  EC_2b_pipe(1)                        &
-    --                                  payload_224b_pipe_ph1(1)(159 downto 144) &
-    --                                  payload_224b_pipe_ph1(1)(127 downto 112) &
-    --                                  payload_224b_pipe_ph1(1)( 95 downto  80) &
-    --                                  payload_224b_pipe_ph1(1)( 63 downto  48) &
-    --                                  payload_224b_pipe_ph1(1)( 31 downto  16) &
-    --                                  FEC_48b_pipe(1)(31 downto 0)         when (LINKSconfig(2) = '0') else
-    --                                  IC_2b_pipe(1)                        &
-    --                                  EC_2b_pipe(1)                        &
-    --                                  payload_224b_pipe_ph1(1)             ; --when lpgbt
-
-    gbt_tx_data_228b_out_temp_ph2 <= x"000000000000000000000000000"       &
-                                     HDR_4b_pipe(1)                       &
-                                     IC_2b_pipe(1)                        &
-                                     EC_2b_pipe(1)                        &
-                                     payload_224b_pipe_ph2(1)(143 downto 128) &
-                                     payload_224b_pipe_ph2(1)(111 downto  96) &
-                                     payload_224b_pipe_ph2(1)( 79 downto  64) &
-                                     payload_224b_pipe_ph2(1)( 47 downto  32) &
-                                     payload_224b_pipe_ph2(1)( 15 downto  0) &
-                                     FEC_48b_pipe(1)(31 downto 0)         when (LINKSconfig(2) = '0') else
-                                     IC_2b_pipe(1)                        &
-                                     EC_2b_pipe(1)                        &
-                                     payload_224b_pipe_ph2(1)             ; --when lpgbt
-
-
-
-    --  payload_80b_gbt_test_ph1 <= gbt_tx_data_228b_out_temp_ph1(111 downto 32);
-    payload_80b_gbt_test_ph2 <= gbt_tx_data_228b_out_temp_ph2(111 downto 32);
-
-    --sim monitoring only, delete later
-    --  payload_egroup0 <= payload_224b_pipe(1)( 31 downto   0);
-    --  payload_egroup1 <= payload_224b_pipe(1)( 63 downto  32);
-    --  payload_egroup2 <= payload_224b_pipe(1)( 95 downto  64);
-    --  payload_egroup3 <= payload_224b_pipe(1)(127 downto  96);
-    --  payload_egroup4 <= payload_224b_pipe(1)(159 downto 128);
-    --  payload_egroup5 <= payload_224b_pipe(1)(191 downto 160);
-    --  payload_egroup6 <= payload_224b_pipe(1)(223 downto 192);
-
-    payload_egroup0_ph2 <= payload_224b_pipe_ph2(1)( 31 downto   0);
-    payload_egroup1_ph2 <= payload_224b_pipe_ph2(1)( 63 downto  32);
-    payload_egroup2_ph2 <= payload_224b_pipe_ph2(1)( 95 downto  64);
-    payload_egroup3_ph2 <= payload_224b_pipe_ph2(1)(127 downto  96);
-    payload_egroup4_ph2 <= payload_224b_pipe_ph2(1)(159 downto 128);
-    payload_egroup5_ph2 <= payload_224b_pipe_ph2(1)(191 downto 160);
-    payload_egroup6_ph2 <= payload_224b_pipe_ph2(1)(223 downto 192);
+    gbt_tx_data_228b_out <= x"000000000000000000000000000"       &
+                            HDR_4b_pipe(1)                       &
+                            IC_2b_pipe(1)                        &
+                            EC_2b_pipe(1)                        &
+                            payload_225b_pipe_ph2(1)(143 downto 128) &
+                            payload_225b_pipe_ph2(1)(111 downto  96) &
+                            payload_225b_pipe_ph2(1)( 79 downto  64) &
+                            payload_225b_pipe_ph2(1)( 47 downto  32) &
+                            payload_225b_pipe_ph2(1)( 15 downto  0) &
+                            FEC_48b_pipe(1)(31 downto 0)         when PROTOCOL = '0' else
+                            IC_2b_pipe(1)                        &
+                            EC_2b_pipe(1)                        &
+                            payload_225b_pipe_ph2(1)(223 downto 0); --when lpgbt
+    data_ready_tx_out  <= payload_225b_pipe_ph2(1)(224);
+
+    --HEADER IC EC and FEC are hardcoded
+    HDR_4b <= "0101"      when PROTOCOL = '0' else "00" & "01";
+    IC_2b  <= "11";
+    EC_2b  <= "11";
+    FEC_48b <= (others=>'0');
 
-    --  EMU_DATA_MUX: process(lane_txclk_240)
+    --delaying data
     EMU_DATA_MUX: process(lane_txclk)
     begin
-        --MT    if lane_txclk_240'event and lane_txclk_240='1' then
         if lane_txclk'event and lane_txclk='1' then
-            payload_224b_pipe(1) <= payload_224b_pipe(0);
-            payload_224b_pipe(0) <= payload_224b;
-            --      payload_224b_pipe_ph1(1) <= payload_224b_pipe_ph1(0);
-            --      payload_224b_pipe_ph1(0) <= payload_224b_ph1;
-            payload_224b_pipe_ph2(1) <= payload_224b_pipe_ph2(0);
-            payload_224b_pipe_ph2(0) <= payload_224b_ph2;
+            payload_225b_pipe_ph2(1) <= payload_225b_pipe_ph2(0);
+            payload_225b_pipe_ph2(0) <= payload_225b_ph2;
             HDR_4b_pipe(1)       <= HDR_4b_pipe(0);
             HDR_4b_pipe(0)       <= HDR_4b;
             IC_2b_pipe(1)        <= IC_2b_pipe(0);
@@ -702,234 +534,67 @@ begin
             EC_2b_pipe(0)        <= EC_2b;
             FEC_48b_pipe(1)      <= FEC_48b_pipe(0);
             FEC_48b_pipe(0)      <= FEC_48b;
-            LM_2b_pipe(1)        <= LM_2b_pipe(0);
-            LM_2b_pipe(0)        <= LM_2b;
         end if;
     end process;
 
-
-    --  gen_elink_muxer : if sim_emulator = false generate
-
-    --RL: state machine that controls elink_sync.
-
-    start_gen <= lane_control.global.elink_sync;
-    sync_readenable : process(lane_txclk)
-    begin
-        if lane_txclk'event and lane_txclk ='1' then
-            sm_sync: case state is
-                when st_idle =>
-                    sync_read_enable <= '0';
-                    count_sync<="000000";
-                    if l1a_trigger = '1' then
-                        state <= st_generate;
-                    elsif start_gen = '1' then
-                        state <= st_sync;
-                    else
-                        state <= st_idle;
-                    end if;
-                when st_sync =>
-                    gen_done <= gen_done_0;
-                    if(count_sync = "111111") then
-                        if(will_sync = '1') then
-                            sync_read_enable <= '1';--'1';
-                            will_sync <= '0';
-                        end if;
-                        count_sync<="000000";
-                    else
-                        sync_read_enable <= '0';
-                        count_sync <= count_sync + '1';
-                    end if;
-                    if l1a_trigger = '1' then
-                        state <= st_generate;
-                        count_sync<="000000";
-                    else
-                        state <= st_sync;
-                    end if;
-                when st_generate =>
-                    sync_read_enable <= '0';
-                    for i in 0 to NUMEGROUPmax-1 loop
-                        if(flag_sync(i) = '1') then
-                            gen_done(i) <= '1';
-                        end if;
-                    end loop;
-                    if gen_done = gen_done_1 or start_gen = '1' then
-                        state <= st_sync;
-                    else
-                        state <= st_generate;
-                    end if;
-            end case sm_sync;
-            if ( lane_control.global.elink_sync = '1' or or_out_of_sync = '1' ) and flag_will_sync = '0' then
-                will_sync <= '1';
-                flag_will_sync <= '1';
-            elsif lane_control.global.elink_sync = '0' and or_out_of_sync = '0' and will_sync = '0' then
-                flag_will_sync <= '0';
-            end if;
-        end if;
-    end process sync_readenable;
-
-    --elink_sync <= lane_control.global.elink_sync;--
-    elink_sync <= sync_read_enable;
-
-    --RL replaced with the new word_printer below.
-    --  elink_muxer:   entity work.gbt_word_printer
-    --    generic map (
-    --      enable_endian_control  => '1',  -- if '0', then operation is always in little endian.
-    ----      DATARATE            => DATARATE,
-    ----      NUMELINK            => NUMELINK,
-    ----      FEC                 => FEC
-    --        NUMELINKmax         => NUMELINKmax
-    --      )
-    --    port map (
-    ----MT      clk240      => lane_txclk_240,
-    --      clk      => lane_txclk,
-    --      elink_sync    => elink_sync,
-    --      elink_control    => elink_control,
-    --      elink_data    => elink_data_in,
-    --      elink_read_enable    => elink_data_re_ph1,
-    ----      gbt_payload    => tx_120b_from_mach( 79+32 downto 32),
-    --      gbt_payload    => payload_224b_ph1,
-    --      tx_flag      => gbt_tx_flag,
-    --      ila_gbt_word_gen_state  => ila_gbt_word_gen_state,
-    --      LINKSconfig       => LINKSconfig
-    --      );
-    ----  end generate gen_elink_muxer;
-
+    --gbt/lpgbt printer
     elink_muxer_v2:   entity work.gbt_word_printer_v2
         generic map (
-            NUMELINKmax         => NUMELINKmax
+            NUMELINKmax         => NUMELINKmax,
+            NUMEGROUPmax        => NUMEGROUPmax,
+            PROTOCOL            => PROTOCOL
         )
         port map (
-            clk      => lane_txclk,
-            elink_sync    => elink_sync,
-            elink_control    => elink_control,
-            elink_data    => elink_data_in,
-            tx_flag      => gbt_tx_flag,
-            LINKSconfig       => LINKSconfig,
-            MSBfirst          => MSBfirst,
-            gbt_payload    => payload_224b_ph2,
-            elink_read_enable  => elink_data_re_ph2,
-            aurora_en         => aurora_en
+            clk                 => lane_txclk,
+            elink_sync_reg      => elink_sync_reg,
+            elink_control       => elink_control,
+            elink_data          => elink_data_in,
+            tx_flag             => gbt_tx_flag,
+            l1a_trigger         => l1a_trigger,
+            MSBfirst            => MSBfirst,
+            gbt_payload         => payload_225b_ph2(223 downto 0),
+            elink_read_enable   => elink_data_re,
+            aurora_en           => (others => '0'),
+            data_ready          => payload_225b_ph2(224),
+            or_out_of_sync      => or_out_of_sync,
+            flag_sync           => flag_sync
         );
-    --  end generate ge
-    elink_data_re <= elink_data_re_ph2;
-    payload_224b  <= payload_224b_ph2;
-    --****************************
-    --****************************
-    --1b) Set Header, IC, EC (Hardcoded)
-    HDR_4b <= "0101"      when (LINKSconfig(2) = '0'  ) else "00" & "01";
-    --  HDR_4b <= "0101"      when (LINKSconfig(2) = '0'  ) else
-    --            "00" & "01" when (LINKSconfig    = "100") else
-    --            "00" & "01" when (LINKSconfig    = "101") else
-    --            "00" & "01" when (LINKSconfig    = "110") else
-    --            "00" & "01" when (LINKSconfig    = "111") ;
-    IC_2b  <= "11";
-    --  IC_2b  <= "11"        when (LINKSconfig(2) = '0'  ) else
-    --            "11"        when (LINKSconfig    = "100") else
-    --            "11"        when (LINKSconfig    = "101") else
-    --            "11"        when (LINKSconfig    = "110") else
-    --            "11"        when (LINKSconfig    = "111") ;
-    EC_2b  <= "11";
-    --  EC_2b  <= "11"        when (LINKSconfig(2) = '0'  ) else
-    --            "11"        when (LINKSconfig    = "100") else
-    --            "11"        when (LINKSconfig    = "101") else
-    --            "11"        when (LINKSconfig    = "110") else
-    --            "11"        when (LINKSconfig    = "111") ;
-
-    --****************************
-    --****************************
-    --1c) Set FEC (Hardcoded until I import the right module)
-    FEC_48b <= (others=>'0');
-    --  FEC_48b <= (others=>'0')      when (LINKSconfig(2) = '0'  ) else
-    --             (others=>'0')      when (LINKSconfig    = "100") else
-    --             (others=>'0')      when (LINKSconfig    = "101") else
-    --             (others=>'0')      when (LINKSconfig    = "110") else
-    --             (others=>'0')      when (LINKSconfig    = "111") ;
-
-    --****************************
-    --****************************
-    --1d) Set LM (Hardcoded)
-    LM_2b  <= "00";
-    --  LM_2b  <= (others=>'0')      when (LINKSconfig(2) = '0'  ) else
-    --             (others=>'0')      when (LINKSconfig    = "100") else
-    --             (others=>'0')      when (LINKSconfig    = "101") else
-    --             (others=>'0')      when (LINKSconfig    = "110") else
-    --             (others=>'0')      when (LINKSconfig    = "111") ;
-
-
-    --****************************
-    --****************************
-    --1e) data checker: just for debug purposes (implemented only for 2bit elinks
-    --in Phase1)
-
-    ----MT checker gbt word
-    ----goal: for 2b elink (e.g: group1 with current config) accumulate 10b
-    ----over 5xgbt_tx_flag and look for following pattern: 0xaa,
-    ----chunk_length(2bytes), L1ID 2bytes), 0xbb, 0xaa
-    ----count distance between 0xaa & 0x00 & 0x3C  and 0xbb + 0xaa (assuming
-    ----chunk_lenght is = 0x03C)
-
-    --gbtword_checker:   entity work.gbtword_checker
-    --  port map (
-    --    lane_txclk_240    => lane_txclk_240    ,
-    --    gbt_tx_flag             => gbt_tx_flag          ,
-    --    tx_120b_from_mach       => tx_120b_from_mach    ,
-
-    --    ila_phlck_gwchk         => ila_phlck_gwchk      ,
-    --    ila_en_gwchk            => ila_en_gwchk         ,
-    --    ila_count_gwchk         => ila_count_gwchk      ,
-    --    ila_count_start_gwchk   => ila_count_start_gwchk,
-    --    ila_testpass_gwchk      => ila_testpass_gwchk   ,
-    --    ila_dist_gwchk          => ila_dist_gwchk       ,
-    --    ila_word10b_gwchk       => ila_word10b_gwchk    ,
-    --    ila_count_pyld          => ila_count_pyld
-
-    --    );
-
-    --PROTOCOL, DATARATE, FEC. 0.X,X = 4.8 Gbps    (GBT   Phase1) 5 Egroups  40 links,
-    --                         1,0.0 = 5.12 FEC5   (lpGBT Phase2) 7 Egroups  56 links,
-    --                         1,0.1 = 5.12 FEC12  (lpGBT Phase2) 6 Egroups  48 links,
-    --                         1.1,0 = 10.24 FEC5  (lpGBT Phase2) 7 Egroups 112 limks,
-    --                         1.1,1 = 10.24 FEC12 (lpGBT Phase2) 6 Egroups  96 links
 
     or_out_of_sync <= or_reduce(out_of_sync);
 
-    --  gen_elink_data_in_zero : for i in 0 to NUMELINKmax-41 generate
-    --    elink_data_in_zero(i) <= "0000000000";
-    --  end generate gen_elink_data_in_zero;
-
-    --  gen_dgen_group : if sim_emulator = false generate
-    --ph1
-    --  dgen_group: for i in 0 to 4 generate
     dgen_group: for i in 0 to NUMEGROUPmax-1 generate
-        signal elink_control_enable_array : std_logic_vector(15 downto 0);
-        signal elink_data_re_array        : std_logic_vector(15 downto 0);
-        signal elink_data_re_array_0      : std_logic_vector(15 downto 0) := (others => '0');
+        signal elink_control_enable_array       : std_logic_vector(15 downto 0);
+        signal elink_data_re_array              : std_logic_vector(15 downto 0);
+        signal elink_data_re_array_0            : std_logic_vector(15 downto 0) := (others => '0');
     begin
-        --  MT if any of the elink in the egroup is active generate data for the
-        --  all group (processed data by bit_feeder will have _we=1 only if
-        --  enable for that elink is 1)
-        --  emu_data_re(i) <= elink_data_re(i*8);
-        --  emu_data_re(i) <=  elink_data_re(i*8) or elink_data_re(i*8+1) or elink_data_re(i*8+2) or elink_data_re(i*8+3) or elink_data_re(i*8+4) or elink_data_re(i*8+5) or elink_data_re(i*8+6) or elink_data_re(i*8+7);
-        emu_data_re(i) <= or_reduce(elink_data_re_array);
-        egroup_enable(i) <= or_reduce(elink_control_enable_array);
-
-        --elink_data_in_tmp <= elink_data_in when
+        emu_data_re(i)      <= or_reduce(elink_data_re_array);
+        egroup_enable(i)    <= or_reduce(elink_control_enable_array);
 
         generate_arrays : for j in 0 to 15 generate
-            elink_control_enable_array(j)     <=  elink_control(i*16+j).enable;
+            xpm_enable_array : xpm_cdc_single generic map(
+                    DEST_SYNC_FF => 2,
+                    INIT_SYNC_FF => 0,
+                    SIM_ASSERT_CHK => 0,
+                    SRC_INPUT_REG => 0
+                )
+                port map(
+                    src_clk => '0',
+                    src_in => elink_control(i*16+j).enable,
+                    dest_clk => lane_txclk,
+                    dest_out => elink_control_enable_array(j)
+                );
             elink_data_re_array(j)            <=  elink_data_re(i*16+j);
-            --elink_data_in_pipe(i*16+j)        <= emu_data_out(i) when egroup_enable = '1' else 0;
-            aurora_en(i*16+j) <= aurora_en_EGROUP(i);  -- RL Check LATER
+        --aurora_en(i*16+j) <= aurora_en_EGROUP(i);  -- Check LATER
         end generate generate_arrays;
 
         dmap : for j in 0 to 7 generate
             elink_data_in(i*16+j)   <= emu_data_out(i) when egroup_enable(i) = '1' else "0000000000";
-            elink_data_in(i*16+j+8) <= emu_data_out(i) when (LINKSconfig(2) = '1' and LINKSconfig(1) = '1' and egroup_enable(i) = '1') else "0000000000";
+            elink_data_in(i*16+j+8) <= emu_data_out(i) when (PROTOCOL = '1' and DATARATE = '1' and egroup_enable(i) = '1') else "0000000000";
         end generate dmap;
 
         flag_sync(i) <= (not egroup_enable(i)) or flag_data_gen(i);
 
-        --RL read enable should always be either equal to 0 or the enable vector. If not they are desynced.
+        --read enable should always be either equal to 0 or the enable vector. If not they are desynced.
         check_read_enables : process(lane_txclk)
         begin
             if lane_txclk'event and lane_txclk ='1' then
@@ -946,124 +611,24 @@ begin
 
         emu_0: entity work.elink_data_emulator
             generic map (
-                epath    => epath,
-                egroup    => to_std_logic_vector(i,3),
-                LANE_ID     => LANE_ID
+                epath       => epath,
+                egroup      => to_std_logic_vector(i,3),
+                LANE_ID     => LANE_ID,
+                PROTOCOL    => PROTOCOL
             )
             port map (
-                clk40        => clk_xtal_40,  --Frans1
-                --        clk240        => lane_txclk_240,
-                clk        => lane_txclk,
-                emu_control      => emu_control(i),
-                elink_data_out    => emu_data_out(i),
-                elink_data_re    => emu_data_re(i),
-                l1a_trig      => l1a_trigger,
-                l1a_id        => l1a_id,
+                clk40               => clk40,  --Frans1
+                clk                 => lane_txclk,
+                emu_control         => emu_control(i),
+                elink_data_out      => emu_data_out(i),
+                elink_data_re       => emu_data_re(i),
+                l1a_trig            => l1a_trigger,
+                l1a_id              => l1a_id,
                 flag_data_gen       => flag_data_gen(i),
-                ila_data_gen_out  => ila_data_gen_out(i),
-                ila_fifo_out    => ila_fifo_out(i),
-                ila_data_gen_we    => ila_data_gen_we(i),
-                --MT checker upstream fifo
-                ila_count_upstfifochk   => ila_count_upstfifochk(i),
-                ila_fifo_flush          => ila_fifo_flush(i),
-                ila_count_chk_out       => ila_count_chk_out(i),
-                ila_count_chk_out2      => ila_count_chk_out2(i),
-                ila_isEOP_chk2          => ila_isEOP_chk2(i),
-                ila_efifoDout_8b10b     => ila_efifoDout_8b10b(i),
-                ila_enc10bitRdy         => ila_enc10bitRdy(i),
-
-                ila_efifoFull           => ila_efifoFull(i)     ,
-                ila_efifoEmpty          => ila_efifoEmpty(i)    ,
-                ila_efifoPfull          => ila_efifoPfull(i),
-                ila_elink_data_re       => ila_elink_data_re(i) ,
-                ila_efifoDoutRdy        => ila_efifoDoutRdy(i)  ,
-                --Frans 1
-                SELECT_RANDOM => SELECT_RANDOM,
-                chunk_length_out => chunk_length_out(i),
-                --MT 2 (Fran 2)
-                FMEMU_RANDOM_RAM_ADDR          => FMEMU_RANDOM_RAM_ADDR ,
-                FMEMU_RANDOM_RAM               => FMEMU_RANDOM_RAM      ,
-                FMEMU_RANDOM_CONTROL           => FMEMU_RANDOM_CONTROL  ,
-                --SS (SWAP LSB MSB)
-                --fhCR_REVERSE_10B               => MSBfirst ,
-                aurora_en               => aurora_en_EGROUP(i)
+                fmemu_random        => fmemu_random,
+                chunk_length_out    => open
             );
 
-
-
-    --ph1
-    --    dmap : for j in 0 to 7 generate
-    --MT ph2 (16 2b virtual elinks
-    --    dmap : for j in 0 to 15 generate
-    --      elink_data_in(i*8+j) <= emu_data_out(i);
-    --    end generate dmap;
-    --  end generate dgen_group;
-    --  end generate gen_dgen_group;
-
     end generate dgen_group;
 
-
-    --  gen_ttc_wrapper_comp : if sim_emulator = false generate
-    ttc_wrapper_comp : entity work.ttc_wrapper_felig
-        port map (
-            a_data_in      => gbt_extractedl1a,
-            b_data_in      => gbt_extracted_bchan,
-            ttc_strobe    => gbt_rx_flag,
-            TTC_out      => TTC_out,
-            --MT      clk240      => lane_rxclk_240,
-            clk240      => lane_rxclk, --Q.: what if is 320 MHZ?
-            BUSY      => chB_busy,
-            L1ID_Bch      => chB_l1a_id,
-            TTC_ToHost_Data_out  => TTC_ToHost_Data
-        );
---  end generate gen_ttc_wrapper_comp;
-
---ila
---  ila_l1a_trigger <= l1a_trigger;
---  ila_l1a_id <= l1a_id;
---  ila_payload_80b_gbt <= gbt_tx_data_228b_out_temp(111 downto 32);
---  ila_clk_xtal_40 <= clk_xtal_40;
---  ila_gbt_tx_data_120b <= gbt_tx_data_228b_out_temp(119 downto 0);
---  ila_gen: for i in 0 to NUMEGROUPmax-1 generate
---    ila_emu_data_out(i) <= emu_data_out(i);
---    ila_emu_control_output_width(i) <= emu_control(i).output_width;
---  end generate ila_gen;
-
-
---  ila_lane: if LANE_ID < 2 generate
---    ila_one_link : ila_0
---      port map(
---        clk => lane_txclk,
---        probe0(0)   => ila_l1a_trigger, --0:0
---        probe1      => ila_l1a_id, --15:0
---        probe2      => ila_fifo_out(0), -- 9:0
---        probe3      => ila_fifo_out(1), -- 9:0
---        probe4      => ila_fifo_out(2), -- 9:0
---        probe5      => ila_fifo_out(3), -- 9:0
---        probe6      => ila_fifo_out(4), -- 9:0
---        probe7      => ila_fifo_out(5), -- 9:0
---        probe8      => ila_fifo_out(6), -- 9:0
---        probe9      => ila_emu_data_out(0), -- 9:0
---        probe10     => ila_emu_data_out(1), -- 9:0
---        probe11     => ila_emu_data_out(2), -- 9:0
---        probe12     => ila_emu_data_out(3), -- 9:0
---        probe13     => ila_emu_data_out(4), -- 9:0
---        probe14     => ila_emu_data_out(5), -- 9:0
---        probe15     => ila_emu_data_out(6), -- 9:0
---        probe16     => ila_payload_80b_gbt, --79:0
---        probe17     => ila_emu_control_output_width(0), --2:0
---        probe18     => ila_emu_control_output_width(1), --2:0
---        probe19     => ila_emu_control_output_width(2), --2:0
---        probe20     => ila_emu_control_output_width(3), --2:0
---        probe21     => ila_emu_control_output_width(4), --2:0
---        probe22     => ila_emu_control_output_width(5), --2:0
---        probe23     => ila_emu_control_output_width(6), --2:0
---        probe24(0)  => ila_clk_xtal_40,--0:0
---        probe25     => ila_gbt_tx_data_120b); --79:0
---    end generate ila_lane;
-
-
-
-
-
 end architecture Behavioral;
diff --git a/sources/FELIG/emulator/EmulatorWrapper.vhd b/sources/FELIG/emulator/EmulatorWrapper.vhd
index 19234f2e5d57bf29b39c8f9dc3fb9d66dc0c749c..e2da90097e575e98cb1c6442e2d76106d9c2066d 100644
--- a/sources/FELIG/emulator/EmulatorWrapper.vhd
+++ b/sources/FELIG/emulator/EmulatorWrapper.vhd
@@ -45,127 +45,66 @@ library UNISIM;
 
     use work.type_lib.ALL;
     use work.ip_lib.ALL;
---use work.FELIX_gbt_package.all;
     use work.FELIX_package.all;
     use work.pcie_package.all;
     use work.centralRouter_package.all;
 
---***********************************Entity Declaration************************
 
 entity EmulatorWrapper is
-    generic
-(
+    generic(
         STABLE_CLOCK_PERIOD         : integer := 10;
-        --  DATARATE                    : integer := 0;  --0=4.8 Gbps (GBT, Phase1),
-        --                                                 --1=5.12 Gbps (LPGBT, Phase2)
-        --                                                 --2=10.24 Gbps(LPGBT, Phase2)
-        --  FEC                         : integer := 0; --0=FEC5, 1=FEC12
-        --  NUMELINK                    : integer := 40;
-        --  NUMEGROUP                   : integer := 5;
-        --  ELINKdivEGROUP              : integer := 8;
         GBT_NUM                     : integer := 24;
         NUMELINKmax                 : integer := 112;
-        NUMEGROUPmax                : integer := 7
+        NUMEGROUPmax                : integer := 7;
+        FIRMWARE_MODE               : integer := 0
     );
-    port
-(
-
-        --================================
-        -- Clocks & Reset
-        --================================
-
-        clk_xtal_40        : in  std_logic;
-        --either 240 MHZ (DATARATE=0) or 320 MHZ (DATARATE=1)
-        gt_txusrclk_in                        : in std_logic_vector(GBT_NUM-1 downto 0);
-        gt_rxusrclk_in                        : in std_logic_vector(GBT_NUM-1 downto 0);
-        gt_rx_clk_div_2_mon      : out std_logic_vector      (23 downto 0);
-        gt_tx_clk_div_2_mon      : out std_logic_vector      (23 downto 0);
-
-        --================================
-        -- L1A Interface
-        --================================
-
-        l1a_trigger_out      : out std_logic_vector      (23 downto 0);
-
-        --================================
-        -- Data
-        --================================
-
-        link_tx_data_228b_array_out            : out txrx228b_type(0 to GBT_NUM-1);
-        --cernphase1 only the ls120b will be used
-        link_rx_data_120b_array_in             : in  txrx120b_type(0 to GBT_NUM-1);
-        --cernphase2 only the ls36b will be used
-
-        link_tx_flag_in                        : in std_logic_vector(GBT_NUM-1 downto 0);
-        link_rx_flag_in                        : in std_logic_vector(GBT_NUM-1 downto 0);
-
-        --================================
-        -- Control and Status Interface
-        --================================
-
-        lane_control        : in  array_of_lane_control_type(GBT_NUM-1 downto 0);
-        lane_monitor        : out array_of_lane_monitor_type(GBT_NUM-1 downto 0);
-        --  lane_control        : in  array_of_lane_control_type(23 downto 0);
-        --  lane_monitor        : out array_of_lane_monitor_type(23 downto 0);
-        register_map_control_40xtal          : in  register_map_control_type;
-
-        link_frame_locked_array_in             : in std_logic_vector(GBT_NUM-1 downto 0);
-        --MT preserve the same order as the lpgbt wrapper (0 to GBT_NUM-1);
-        --SS (SWAP LSB MSB)
-        --fhCR_REVERSE_10B                      : in  std_logic
-        LINKSconfig          : in std_logic_vector(2 downto 0)
+    port(
+        clk40                       : in  std_logic;
+        gt_txusrclk_in              : in std_logic_vector(GBT_NUM-1 downto 0);
+        gt_rxusrclk_in              : in std_logic_vector(GBT_NUM-1 downto 0);
+        link_tx_data_228b_array_out : out txrx228b_type(0 to GBT_NUM-1);
+        data_ready_tx_out           : out std_logic_vector(0 to GBT_NUM-1);
+        link_rx_data_120b_array_in  : in  txrx120b_type(0 to GBT_NUM-1);
+        link_tx_flag_in             : in std_logic_vector(GBT_NUM-1 downto 0);
+        link_rx_flag_in             : in std_logic_vector(GBT_NUM-1 downto 0);
+        lane_control                : in  array_of_lane_control_type(GBT_NUM-1 downto 0);
+        lane_monitor                : out array_of_lane_monitor_type(GBT_NUM-1 downto 0)
     );
 
 
 end EmulatorWrapper;
 
 architecture RTL of EmulatorWrapper is
-    attribute DowngradeIPIdentifiedWarnings: string;
-    attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-
-    attribute CORE_GENERATION_INFO : string;
-    attribute CORE_GENERATION_INFO of RTL : architecture is "gt_core,gtwizard_v3_6_3,{protocol_file=Start_from_scratch}";
-
-    ------------------------------- Global Signals -----------------------------
-
-    signal  tied_to_ground_i                : std_logic;
-    signal  tied_to_ground_vec_i            : std_logic_vector(63 downto 0);
-    signal  tied_to_vcc_i                   : std_logic;
-    signal  tied_to_vcc_vec_i               : std_logic_vector(7 downto 0);
-
-    attribute keep: string;
-    ------------------------------- User Clocks ---------------------------------
-    signal l1a_int_trigger        : std_logic;
-    signal l1a_int_int_id          : std_logic_vector(15 downto 0);
+    function FM_TO_PROTOCOL(FIRMWARE_MODE:integer)
+        return std_logic is
+    begin
+        if FIRMWARE_MODE = FIRMWARE_MODE_FELIG_GBT then
+            return '0';
+        elsif FIRMWARE_MODE = FIRMWARE_MODE_FELIG_LPGBT then
+            return '1';
+        else
+            return '0';
+        end if;
+    end function;
+    signal l1a_int_trigger                  : std_logic;
+    signal l1a_int_int_id                   : std_logic_vector(15 downto 0);
     signal l1a_int_int_id_extra             : std_logic_vector(31 downto 0);
-    signal l1a_int_count ,L1A_INT_MAX_COUNT  : std_logic_vector(31 downto 0);
+    signal l1a_int_count, l1a_int_max_count : std_logic_vector(31 downto 0);
     signal l1a_int_max_count_extra          : std_logic_vector(15 downto 0) := (others=>'0');
+    signal l1a_int_count_load               : std_logic;
+    signal l1a_int_int_id_sclr              : std_logic;
+    signal l1a_int_counter_reset            : std_logic := '0';
+    signal flag_int_counter_reset           : std_logic := '0';
+    signal counter_reset                    : std_logic;
 
-    signal l1a_int_count_load : std_logic;
-    signal l1a_int_int_id_sclr : std_logic;
-
-    --RL: adding l1id internal counter reset.
-    signal l1a_int_counter_reset : std_logic := '0';
-    signal flag_int_counter_reset : std_logic := '0';
-
---**************************** Main Body of Code *******************************
 begin
 
-    --  Static signal Assigments
-    tied_to_ground_i                             <= '0';
-    tied_to_ground_vec_i                         <= x"0000000000000000";
-    tied_to_vcc_i                                <= '1';
-    tied_to_vcc_vec_i                            <= "11111111";
-
-
-
-    L1A_INT_MAX_COUNT    <= "0000" & register_map_control_40xtal.FELIG_GLOBAL_CONTROL.FAKE_L1A_RATE;
-
-
+    l1a_int_max_count   <= "0000" & lane_control(0).global.l1a_max_count;--"0000" & register_map_control_40xtal.FELIG_GLOBAL_CONTROL.FAKE_L1A_RATE;
+    counter_reset       <= lane_control(0).global.l1a_counter_reset;
 
     l1a_int_counter : dsp_counter
         PORT MAP (
-            CLK    => clk_xtal_40,
+            CLK    => clk40,
             CE    => '1',
             SCLR  => '0',
             UP    => '0',
@@ -178,7 +117,7 @@ begin
 
     l1a_int_int_id_counter : dsp_counter
         PORT MAP (
-            CLK    => clk_xtal_40,
+            CLK    => clk40,
             CE    => l1a_int_trigger,
             SCLR  => l1a_int_int_id_sclr,
             UP    => '1',
@@ -188,25 +127,24 @@ begin
             Q(15 downto  0)    => l1a_int_int_id
         );
 
-    --RL: adding l1id internal counter reset.
-    process(clk_xtal_40)
+    process(clk40)
     begin
-        if clk_xtal_40'event and clk_xtal_40='1' then
-            if lane_control(0).global.l1a_counter_reset = '1' and flag_int_counter_reset = '0' then
+        if clk40'event and clk40='1' then
+            if counter_reset = '1' and flag_int_counter_reset = '0' then
                 l1a_int_counter_reset <= '1';
                 flag_int_counter_reset <= '1';
             elsif l1a_int_int_id  = X"0000" then
                 l1a_int_counter_reset <= '0';
-                if lane_control(0).global.l1a_counter_reset = '0' then
+                if counter_reset = '0' then
                     flag_int_counter_reset <= '0';
                 end if;
             end if;
         end if;
     end process;
 
-    process(clk_xtal_40)
+    process(clk40)
     begin
-        if clk_xtal_40'event and clk_xtal_40='1' then
+        if clk40'event and clk40='1' then
             if l1a_int_max_count = 0 then
                 l1a_int_trigger <= '0';
                 l1a_int_int_id_sclr <= '1';
@@ -224,69 +162,30 @@ begin
         end if;
     end process;
 
-    -- CXP1 links 1/2   ( gt2/ gt0)
-    -- CXP1 links 3/4   ( gt3/ gt1)
-    -- CXP1 links 5/6   ( gt5/ gt4)
-    -- CXP1 links 7/8   ( gt7/ gt6)
-    -- CXP1 links 9/10  ( gt8/gt10)
-    -- CXP1 links 11/12 ( gt9/gt11)
-    -- CXP2 links 1/2   (gt14/gt12)
-    -- CXP2 links 3/4   (gt15/gt13)
-    -- CXP2 links 5/6   (gt17/gt16)
-    -- CXP2 links 7/8   (gt19/gt18)
-    -- CXP2 links 9/10  (gt20/gt22)
-    -- CXP2 links 11/12 (gt21/gt23)
-
-
-    emulator_inst : for igbt in GBT_NUM-1 downto 0 generate
+    emulator_inst : for link in GBT_NUM-1 downto 0 generate
 
         gbt : entity work.emulator
             generic map (
-                GEN_ILA      => false,
-                useGBTdataEmulator          => false,
-                sim_emulator                  => false,
-                LANE_ID                  => igbt
+                useGBTdataEmulator       => false,
+                sim_emulator             => false,
+                LANE_ID                  => link,
+                PROTOCOL                 => FM_TO_PROTOCOL(FIRMWARE_MODE)
             )
             port map (
-                clk_xtal_40            => clk_xtal_40,
-                --MT
-                --          lane_rxclk_240    => gt_rxusrclk_in(igbt),
-                --          lane_txclk_240    => gt_txusrclk_in(igbt),
-                lane_rxclk            => gt_rxusrclk_in(igbt),
-                lane_txclk          => gt_txusrclk_in(igbt),
-
-                rx_clk_div_2_mon          => gt_rx_clk_div_2_mon(igbt),
-                tx_clk_div_2_mon          => gt_tx_clk_div_2_mon(igbt),
-
-                gth_rxusrclk2            => gt_rxusrclk_in(igbt),
-                gth_txusrclk2            => gt_txusrclk_in(igbt),
-
-
-                l1a_int_trigger    => l1a_int_trigger,
-                l1a_int_int_id    => l1a_int_int_id,
-                l1a_trigger_out    => l1a_trigger_out(igbt),
-
-                --MT
-                --          gbt_tx_data_120b_out    => gbt_tx_data_120b_array_out(igbt),
-                --          gbt_rx_data_120b_in     => gbt_rx_data_120b_array_in(igbt),
-                gbt_tx_data_228b_out    => link_tx_data_228b_array_out(igbt),
-                gbt_rx_data_120b_in     => link_rx_data_120b_array_in(igbt),
-                gbt_tx_flag_in          => link_tx_flag_in(igbt),
-                gbt_rx_flag_in          => link_tx_flag_in(igbt),
-
-                lane_control    => lane_control(igbt),
-                lane_monitor    => lane_monitor(igbt),
-
-                --Other registers
+                clk40                   => clk40,
+                lane_rxclk              => gt_rxusrclk_in(link),
+                lane_txclk              => gt_txusrclk_in(link),
+                l1a_int_trigger         => l1a_int_trigger,
+                l1a_int_int_id          => l1a_int_int_id,
+                l1a_trigger_out         => open,--l1a_trigger_out(link),
+                gbt_tx_data_228b_out    => link_tx_data_228b_array_out(link),
+                data_ready_tx_out       => data_ready_tx_out(link),-- out std_logic;
+                gbt_rx_data_120b_in     => link_rx_data_120b_array_in(link),
+                gbt_tx_flag_in          => link_tx_flag_in(link),
+                gbt_rx_flag_in          => link_rx_flag_in(link),
+                lane_control            => lane_control(link),
+                lane_monitor            => lane_monitor(link)--,
 
-                SELECT_RANDOM           => register_map_control_40xtal.FMEMU_RANDOM_CONTROL.SELECT_RANDOM,
-                FMEMU_RANDOM_RAM_ADDR   => register_map_control_40xtal.FMEMU_RANDOM_RAM_ADDR ,
-                FMEMU_RANDOM_RAM        => register_map_control_40xtal.FMEMU_RANDOM_RAM      ,
-                FMEMU_RANDOM_CONTROL    => register_map_control_40xtal.FMEMU_RANDOM_CONTROL,
-                gbt_frame_locked_in     => link_frame_locked_array_in(igbt),
-                --SS (SWAP LSB MSB). RL changed so it works
-                --fhCR_REVERSE_10B        => register_map_control_40xtal.ENCODING_REVERSE_10B(register_map_control_40xtal.ENCODING_REVERSE_10B'low),--fhCR_REVERSE_10B ,
-                LINKSconfig       => LINKSconfig
             );
 
     end generate;
diff --git a/sources/FELIG/housekeeping/housekeeping_module_FELIG.vhd b/sources/FELIG/housekeeping/housekeeping_module_FELIG.vhd
index 0fe527f06d233ea03f15a0565e19407d55099624..79a446b05239e336918012e3539ef36c5ae18339 100644
--- a/sources/FELIG/housekeeping/housekeeping_module_FELIG.vhd
+++ b/sources/FELIG/housekeeping/housekeeping_module_FELIG.vhd
@@ -61,7 +61,7 @@ entity housekeeping_module_FELIG is
         clk10_xtal                  : in     std_logic;
         clk40_xtal                  : in     std_logic;
         clk40                       : in     std_logic; --MT added
-        clk40_rxusrclk              : in     std_logic; --MT added RXUSRCLK scaled down to 40 MHZ
+        --clk40_rxusrclk              : in     std_logic; --MT added RXUSRCLK scaled down to 40 MHZ
         RESET_TO_LMK                : in     std_logic; --MT added
         leds                        : out    std_logic_vector(7 downto 0);
         opto_inhibit                : out    std_logic_vector(OPTO_TRX-1 downto 0);
diff --git a/sources/FELIG/packages/type_lib.vhd b/sources/FELIG/packages/type_lib.vhd
index 0404388bda6b1f2f8c56332c0612558f35651f47..287d22b892d05318a58d283b8d97481520f5aeca 100644
--- a/sources/FELIG/packages/type_lib.vhd
+++ b/sources/FELIG/packages/type_lib.vhd
@@ -92,6 +92,7 @@ package type_lib is
     type array_of_slv_87_0   is array (integer range <>) of std_logic_vector(87 downto 0);
     type array_of_slv_111_0  is array (integer range <>) of std_logic_vector(111 downto 0);
     type array_of_slv_119_0  is array (integer range <>) of std_logic_vector(119 downto 0);
+    type array_of_slv_224_0  is array (integer range <>) of std_logic_vector(224 downto 0);
     type array_of_slv_223_0  is array (integer range <>) of std_logic_vector(223 downto 0);
 
     type array_of_array_0_2_slv_9_0 is array (integer range <>) of array_of_slv_9_0( 0 to 2);
@@ -106,19 +107,6 @@ package type_lib is
     type bitfield_felig_elink_config_w_type_array    is array (integer range <>) of bitfield_felig_elink_config_w_type;
     type bitfield_felig_lane_config_w_type_array    is array (integer range <>) of bitfield_felig_lane_config_w_type;
 
-    type lane_gbt_control is record
-        rxslide_select    : std_logic;
-        rx_reset      : std_logic;
-        tc_edge        : std_logic;
-        tx_reset      : std_logic;
-        tx_tc_method    : std_logic;
-        rx_data_format    : std_logic_vector(1 downto 0);
-        tx_data_format    : std_logic_vector(1 downto 0);
-        tx_tc_dly_value    : std_logic_vector(3 downto 0);
-        loopback_enable    : std_logic;
-        rxslide_count_reset  : std_logic;
-    end record lane_gbt_control;
-
     type lane_gbt_monitor is record
         frame_locked  : std_logic;
         rx_is_header  : std_logic;
@@ -127,13 +115,6 @@ package type_lib is
         rxslide_count  : std_logic_vector(31 downto 0);
     end record lane_gbt_monitor;
 
-    type lane_gth_control is record
-        manual_gth_rxreset  : std_logic;
-        txpolarity      : std_logic;
-        rxpolarity      : std_logic;
-        loopback_enable    : std_logic;
-    end record lane_gth_control;
-
     type lane_gth_monitor is record
         txreset_done  : std_logic;
         rxreset_done  : std_logic;
@@ -146,7 +127,6 @@ package type_lib is
         data_format    : std_logic_vector(1 downto 0);
         sw_busy      : std_logic;
         reset      : std_logic;
-        --MT    output_width  : std_logic_vector(1 downto 0);
         output_width  : std_logic_vector(2 downto 0);
         chunk_length  : std_logic_vector(15 downto 0);
         userdata    : std_logic_vector(15 downto 0);
@@ -157,7 +137,6 @@ package type_lib is
     type lane_emulator_control_array  is array (integer range <>) of lane_emulator_control;
 
     type lane_elink_control is record
-        --MT    output_width  : std_logic_vector(1 downto 0);    -- bit per e-link
         output_width  : std_logic_vector(2 downto 0);    -- bit per e-link
         input_width    : std_logic;            -- bit per e-link
         endian_mode    : std_logic;            -- bit per e-link
@@ -179,20 +158,26 @@ package type_lib is
         b_ch_bit_sel    : std_logic_vector(6 downto 0);
         l1a_counter_reset   : std_logic;
         MSB                 : std_logic;
+        l1a_max_count       : std_logic_vector(27 downto 0);
+        aligned             : std_logic;
+        --PROTOCOL            : std_logic;
+        FEC                 : std_logic;
+        DATARATE            : std_logic;
     end record lane_global_control;
 
+    type lane_emu_random_control is record
+        SELECT_RANDOM           : std_logic_vector(0 downto 0);
+        FMEMU_RANDOM_RAM_ADDR   : std_logic_vector(9 downto 0);    -- Controls the address of the ramblock for the random number generator
+        FMEMU_RANDOM_RAM        : bitfield_fmemu_random_ram_t_type;
+        FMEMU_RANDOM_CONTROL    : bitfield_fmemu_random_control_w_type;
+    end record lane_emu_random_control;
+
     type lane_global_monitor is record
         ttc_mon        : TTC_ToHost_data_type;
         l1a_id        : std_logic_vector(31 downto 0);
         fc_error_count    : std_logic_vector(31 downto 0);
     end record lane_global_monitor;
 
-    type lane_clock_control is record
-        gth_tx_pi_hold    : std_logic;
-        picxo_offset_en    : std_logic;
-        picxo_offset_ppm  : std_logic_vector(21 downto 0);
-    end record lane_clock_control;
-
     type lane_clock_monitor is record
         freq_rx_clk  : std_logic_vector(31 downto 0);
         freq_tx_clk  : std_logic_vector(31 downto 0);
@@ -202,13 +187,9 @@ package type_lib is
 
     type lane_control_type is record
         global    : lane_global_control;
-        clock    : lane_clock_control;
-        gbt      : lane_gbt_control;
-        gth      : lane_gth_control;
         emulator  : lane_emulator_control_array(0 to 6);
         elink    : lane_elink_control_array(0 to 111);
-    --    emulator  : lane_emulator_control_array(0 to 4);
-    --    elink    : lane_elink_control_array(0 to 39);
+        fmemu_random : lane_emu_random_control;
     end record lane_control_type;
 
     type lane_monitor_type is record
diff --git a/sources/FELIG/templates/LaneRegisterRemapper.vhd b/sources/FELIG/templates/LaneRegisterRemapper.vhd
index 285bdcc48e56b63e4091bf12d5514c691ea3b711..f53e89fe74c665454b1023b733366110e1e4acab 100644
--- a/sources/FELIG/templates/LaneRegisterRemapper.vhd
+++ b/sources/FELIG/templates/LaneRegisterRemapper.vhd
@@ -55,294 +55,176 @@ entity LaneRegisterRemapper is
 (
         GBT_NUM                     : integer := 24;
         FIRMWARE_MODE               : integer := FIRMWARE_MODE_FELIG_GBT
-    --    ILA                         : integer := 1
     );
     port(
-        register_map_monitor  : out  register_map_monitor_type;
-        register_map_control  : in  register_map_control_type;
-
-        lane_control      : out  array_of_lane_control_type(GBT_NUM-1 downto 0);
-        lane_monitor      : in  array_of_lane_monitor_type(GBT_NUM-1 downto 0);
-        LINKSconfig             : out   std_logic_vector(2 downto 0)
+        register_map_monitor        : out  register_map_monitor_type;
+        register_map_control        : in  register_map_control_type;
+        register_map_hk_monitor_in  : in register_map_hk_monitor_type;
+        register_map_hk_monitor_out : out register_map_hk_monitor_type;
+        LMK_LOCKED                  : in std_logic;
+        LinkAligned                 : in std_logic_vector(GBT_NUM-1 downto 0);
+        lane_control                : out  array_of_lane_control_type(GBT_NUM-1 downto 0);
+        lane_monitor                : in  array_of_lane_monitor_type(GBT_NUM-1 downto 0)
     );
 end entity LaneRegisterRemapper;
 
 architecture RTL of LaneRegisterRemapper is
-    signal felig_counter_rx_slide  : array_of_slv_31_0(lane_control'range);
-    signal felig_counter_fc_error  : array_of_slv_31_0(lane_control'range);
-    signal felig_counter_freq_tx  : array_of_slv_31_0(lane_control'range);
-    signal felig_counter_freq_rx  : array_of_slv_31_0(lane_control'range);
-    signal felig_mon_picxo_error  : array_of_slv_20_0(lane_control'range);
-    signal felig_mon_picxo_volt    : array_of_slv_21_0(lane_control'range);
-    signal felig_mon_l1_id      : array_of_slv_31_0(lane_control'range);
-    signal felig_mon_ttc_bch_mon  : array_of_array_0_3_slv_31_0(lane_control'range);
-
-
-    signal felig_data_gen_config          : bitfield_felig_data_gen_config_w_type_array(lane_control'range);
-    signal felig_elink_config            : bitfield_felig_elink_config_w_type_array(lane_control'range);
+    signal felig_data_gen_config            : bitfield_felig_data_gen_config_w_type_array(lane_control'range);
+    signal felig_elink_config               : bitfield_felig_elink_config_w_type_array(lane_control'range);
     signal felig_data_gen_config_userdata   : array_of_slv_15_0(lane_control'range);
     signal felig_elink_enable_orig          : array_of_slv_39_0(lane_control'range);
     signal felig_elink_enable               : array_of_slv_111_0(lane_control'range);
     signal felig_elink_endian_mode          : array_of_slv_111_0(lane_control'range);
     signal felig_elink_input_width          : array_of_slv_111_0(lane_control'range);
-    --MT  signal felig_elink_output_width  : array_of_array_0_39_slv_1_0(lane_control'range);
-    signal felig_elink_output_width  : array_of_array_0_111_slv_2_0(lane_control'range);
-    signal felig_lane_config    : bitfield_felig_lane_config_w_type_array(lane_control'range);
-    signal LINKSconfig_int          : std_logic_vector(2 downto 0) := "000";
-    signal DATARATE                 : std_logic := '1';
-    signal FECMODE                  : std_logic := '0';
+    signal felig_elink_output_width         : array_of_array_0_111_slv_2_0(lane_control'range);
+    signal felig_lane_config                : bitfield_felig_lane_config_w_type_array(lane_control'range);
 begin
 
-    DATARATE          <= '1';--register_map_control.LPGBT_DATARATE(0)
-    FECMODE           <= '0';--register_map_control.LPGBT_FEC(0)
-
-    --for reference upLinkTxDataPath FECMODE and DATARATE parameters
-    --localparam FEC5           = 1'b0;
-    --localparam FEC12          = 1'b1;
-    --localparam TxDataRate5G12 = 1'b0;
-    --localparam TxDataRate10G24= 1'b1;
-    LINKSconfig_int  <= '0' & DATARATE & FECMODE when FIRMWARE_MODE = FIRMWARE_MODE_FELIG_GBT else
-                        '1' & DATARATE & FECMODE when FIRMWARE_MODE = FIRMWARE_MODE_FELIG_LPGBT;
-    LINKSconfig <= LINKSconfig_int;
-    --RL modified to convert the old rm with 5 egroups into up to 7. egroups 5 and 6 always equal to 4
-    GEN_WIDTHS : for i in lane_control'range generate
-        GEN_GEN_WIDTHS : for j in lane_control(0).emulator'range generate
-            signal felig_output_width : std_logic_vector(2 downto 0);
-            signal felig_output_width_array :   array_of_slv_2_0(15 downto 0);
-            signal felig_input_width : std_logic;
-            signal felig_endian_mode : std_logic;
+    --loop over links
+    GEN_LANE_CONTROL_MAP : for i in lane_control'range generate
+        lane_control(i).global.FEC                          <= register_map_control.LPGBT_FEC(i);  --FEC5 0 FEC12 1
+        lane_control(i).global.DATARATE                     <= '1'; -- not register_map_control.LPGBT_DATARATE(0) --data rate 5.12 not implemented and not needed --5.12 0 10.24 1 (register needs to be negated)
+        lane_control(i).global.aligned                      <= LinkAligned(i);
+        felig_data_gen_config(i)                            <= register_map_control.FELIG_DATA_GEN_CONFIG(i)                ;
+        felig_data_gen_config_userdata(i)                   <= register_map_control.FELIG_DATA_GEN_CONFIG_USERDATA(i)       ;
+        felig_elink_config(i)                               <= register_map_control.FELIG_ELINK_CONFIG(i)                   ;
+        felig_elink_enable_orig(i)                          <= register_map_control.FELIG_ELINK_ENABLE(i)                   ;
+        felig_lane_config(i)                                <= register_map_control.FELIG_LANE_CONFIG(i)                    ;
+        lane_control(i).global.lane_reset                   <= register_map_control.FELIG_RESET.LANE            (i+register_map_control.FELIG_RESET.LANE'low);
+        lane_control(i).global.framegen_reset               <= register_map_control.FELIG_RESET.FRAMEGEN          (i+register_map_control.FELIG_RESET.FRAMEGEN'low);
+        lane_control(i).global.elink_sync                   <= felig_lane_config(i).ELINK_SYNC                (felig_lane_config(i).ELINK_SYNC'low);
+        lane_control(i).global.framegen_data_select         <= felig_lane_config(i).FG_SOURCE                (felig_lane_config(i).FG_SOURCE'low);
+        lane_control(i).global.emu_data_select              <= felig_lane_config(i).GBT_EMU_SOURCE              (felig_lane_config(i).GBT_EMU_SOURCE'low);
+        lane_control(i).global.l1a_source                   <= felig_lane_config(i).L1A_SOURCE                (felig_lane_config(i).L1A_SOURCE'low);
+        lane_control(i).global.loopback_fifo_delay          <= felig_lane_config(i).LB_FIFO_DELAY              ;
+        lane_control(i).global.loopback_fifo_reset          <= register_map_control.FELIG_RESET.LB_FIFO            (register_map_control.FELIG_RESET.LB_FIFO'low);
+        lane_control(i).global.a_ch_bit_sel                 <= felig_lane_config(i).A_CH_BIT_SEL              ;
+        lane_control(i).global.b_ch_bit_sel                 <= felig_lane_config(i).B_CH_BIT_SEL(48 downto 42)              ;
+        lane_control(i).global.l1a_counter_reset            <= register_map_control.FELIG_L1ID_RESET                        (register_map_control.FELIG_L1ID_RESET'low);
+        lane_control(i).global.MSB                          <= register_map_control.ENCODING_REVERSE_10B                    (register_map_control.ENCODING_REVERSE_10B'low);
+        lane_control(i).global.l1a_max_count                <= register_map_control.FELIG_GLOBAL_CONTROL.FAKE_L1A_RATE;
+        lane_control(i).fmemu_random.SELECT_RANDOM          <= register_map_control.FMEMU_RANDOM_CONTROL.SELECT_RANDOM;
+        lane_control(i).fmemu_random.FMEMU_RANDOM_RAM_ADDR  <= register_map_control.FMEMU_RANDOM_RAM_ADDR;
+        lane_control(i).fmemu_random.FMEMU_RANDOM_RAM       <= register_map_control.FMEMU_RANDOM_RAM;
+        lane_control(i).fmemu_random.FMEMU_RANDOM_CONTROL   <= register_map_control.FMEMU_RANDOM_CONTROL;
+
+        --loop over egroups
+        GEN_EGROUPS: for j in lane_control(0).emulator'range generate
+            signal felig_output_width       : std_logic_vector(2 downto 0);
+            signal felig_output_width_array : array_of_slv_2_0(15 downto 0);
+            signal felig_input_width        : std_logic;
+            signal felig_endian_mode        : std_logic;
         begin
-            --            less_that_five : if j<5 generate
-            --                felig_output_width <= "0" & felig_elink_config(i).OUTPUT_WIDTH(j*2+1 downto j*2);
-            --                felig_input_width <= felig_elink_config(i).INPUT_WIDTH(j+felig_elink_config(i).INPUT_WIDTH'low);
-            --                felig_endian_mode <= felig_elink_config(i).ENDIAN_MOD(j+felig_elink_config(i).ENDIAN_MOD'low);
-            --                felig_elink_enable(i)(j*16+7 downto j*16) <= felig_elink_enable_orig(i)(j*8+7 downto j*8);
-            --                felig_elink_enable(i)(j*16+15 downto j*16+8) <= felig_elink_enable_orig(i)(j*8+7 downto j*8)  when (LINKSconfig_int(2 downto 1) = "11") else X"00";
-            --            end generate less_that_five;
-            --            more_that_five : if j>4 generate
-            --                felig_output_width <= "0" & felig_elink_config(i).OUTPUT_WIDTH(9 downto 8);
-            --                felig_input_width <= felig_elink_config(i).INPUT_WIDTH(4+felig_elink_config(i).INPUT_WIDTH'low);
-            --                felig_endian_mode <= felig_elink_config(i).ENDIAN_MOD(4+felig_elink_config(i).ENDIAN_MOD'low);
-            --                felig_elink_enable(i)(j*16+7 downto j*16) <= felig_elink_enable_orig(i)(4*8+7 downto 4*8);
-            --                felig_elink_enable(i)(j*16+15 downto j*16+8) <= felig_elink_enable_orig(i)(4*8+7 downto 4*8) when (LINKSconfig_int(2 downto 1) = "11") else X"00";
-            --            end generate more_that_five;
+            lane_control(i).emulator(j).pattern_select(0)   <= felig_data_gen_config(i).PATTERN_SEL(j+felig_data_gen_config(i).PATTERN_SEL'low);
+            lane_control(i).emulator(j).pattern_select(1)   <= '0';
+            lane_control(i).emulator(j).data_format(0)      <= felig_data_gen_config(i).DATA_FORMAT(2*j+felig_data_gen_config(i).DATA_FORMAT'low);
+            lane_control(i).emulator(j).data_format(1)      <= felig_data_gen_config(i).DATA_FORMAT(2*j+1+felig_data_gen_config(i).DATA_FORMAT'low);
+            lane_control(i).emulator(j).sw_busy             <= felig_data_gen_config(i).SW_BUSY(j+felig_data_gen_config(i).SW_BUSY'low);
+            lane_control(i).emulator(j).reset               <= felig_data_gen_config(i).RESET(j+felig_data_gen_config(i).RESET'low);
+            lane_control(i).emulator(j).chunk_length        <= felig_data_gen_config(i).CHUNK_LENGTH ;
+            lane_control(i).emulator(j).userdata            <= felig_data_gen_config_userdata(i);
+
             felig_output_width <= felig_elink_config(i).OUTPUT_WIDTH(j*3+2 downto j*3);
             felig_input_width  <= felig_elink_config(i).INPUT_WIDTH(j+felig_elink_config(i).INPUT_WIDTH'low);
             felig_endian_mode  <= felig_elink_config(i).ENDIAN_MOD(j+felig_elink_config(i).ENDIAN_MOD'low);
 
             GEN_ENABLES_GBT : if FIRMWARE_MODE = FIRMWARE_MODE_FELIG_GBT generate
-                --RL 40bits used. maximum of 8 E-Links (2b) per E-group. 5 EGroups x 8 E-Links = 40.
                 less_that_five : if j<5 generate
-                    felig_elink_enable(i)(j*16+7 downto j*16)    <= felig_elink_enable_orig(i)(j*8+7 downto j*8);
-                    felig_elink_enable(i)(j*16+15 downto j*16+8) <= X"00";
+                    felig_elink_enable(i)(j*16+7 downto j*16)       <= felig_elink_enable_orig(i)(j*8+7 downto j*8);
+                    felig_elink_enable(i)(j*16+15 downto j*16+8)    <= X"00";
                 end generate less_that_five;
                 more_that_five : if j>4 generate
-                    felig_elink_enable(i)(j*16+15 downto j*16) <= (others=>'0');
+                    felig_elink_enable(i)(j*16+15 downto j*16)      <= (others=>'0');
                 end generate more_that_five;
             end generate GEN_ENABLES_GBT;
 
             GEN_ENABLES_LPGBT : if FIRMWARE_MODE = FIRMWARE_MODE_FELIG_LPGBT generate
-                --RL 28bits used. Maximum of 4 E-Links (8b) per E-group. 7 EGroups x 4 E-Links = 28.
                 felig_elink_enable(i)(j*16+15 downto j*16)  <= "000" & felig_elink_enable_orig(i)(4*j+3) &
                                                                "000" & felig_elink_enable_orig(i)(4*j+2) &
                                                                "000" & felig_elink_enable_orig(i)(4*j+1) &
                                                                "000" & felig_elink_enable_orig(i)(4*j);
             end generate GEN_ENABLES_LPGBT;
 
-            felig_output_width_array(0)  <= felig_output_width;
-            felig_output_width_array(1)  <= "000";
-            felig_output_width_array(2)  <= "00" & felig_output_width(0);
-            felig_output_width_array(3)  <= "000";
-            felig_output_width_array(4)  <= '0' & felig_output_width(1 downto 0);
-            felig_output_width_array(5)  <= "000";
-            felig_output_width_array(6)  <= "00" & felig_output_width(0);
-            felig_output_width_array(7)  <= "000";
-            felig_output_width_array(8)  <= '0' & felig_output_width(1 downto 0);
-            felig_output_width_array(9)  <= "000";
-            felig_output_width_array(10) <= "00" & felig_output_width(0);
-            felig_output_width_array(11) <= "000";
-            felig_output_width_array(12) <= '0' & felig_output_width(1 downto 0);
-            felig_output_width_array(13) <= "000";
-            felig_output_width_array(14) <= "00" & felig_output_width(0);
-            felig_output_width_array(15) <= "000";
-
-            lane_control(i).emulator(j).output_width <= felig_output_width;
-
-            GEN_GEN_GEN_WIDTHS : for h in 0 to 15 generate
-                felig_elink_output_width(i)(j*16+h)   <= felig_output_width_array(h);
-                --felig_elink_output_width(i)(j*16+h+8) <= felig_output_width_array(h) when (LINKSconfig_int(2 downto 1) = "11") else "111";
-                felig_elink_input_width(i)(j*16+h)    <= felig_input_width;
-                --felig_elink_input_width(i)(j*16+h+8)  <= felig_input_width;
-                felig_elink_endian_mode(i)(j*16+h)    <= felig_endian_mode;
-            --felig_elink_endian_mode(i)(j*16+h+8)  <= felig_endian_mode;
-            end generate GEN_GEN_GEN_WIDTHS;
-        end generate GEN_GEN_WIDTHS;
-    end generate GEN_WIDTHS;
-
-    GEN_LANE_CONTROL_MAP : for i in lane_control'range generate
-        felig_data_gen_config(i)                    <= register_map_control.FELIG_DATA_GEN_CONFIG(i)                ;
-        felig_data_gen_config_userdata(i)           <= register_map_control.FELIG_DATA_GEN_CONFIG_USERDATA(i)       ;
-        felig_elink_config(i)                       <= register_map_control.FELIG_ELINK_CONFIG(i)                   ;
-        felig_elink_enable_orig(i)                  <= register_map_control.FELIG_ELINK_ENABLE(i)                   ;
-        felig_lane_config(i)                        <= register_map_control.FELIG_LANE_CONFIG(i)                    ;
-
-        lane_control(i).global.lane_reset      <= register_map_control.FELIG_RESET.LANE            (i+register_map_control.FELIG_RESET.LANE'low);
-        lane_control(i).global.framegen_reset    <= register_map_control.FELIG_RESET.FRAMEGEN          (i+register_map_control.FELIG_RESET.FRAMEGEN'low);
-        lane_control(i).global.elink_sync      <= felig_lane_config(i).ELINK_SYNC                (felig_lane_config(i).ELINK_SYNC'low);
-        lane_control(i).global.framegen_data_select  <= felig_lane_config(i).FG_SOURCE                (felig_lane_config(i).FG_SOURCE'low);
-        lane_control(i).global.emu_data_select    <= felig_lane_config(i).GBT_EMU_SOURCE              (felig_lane_config(i).GBT_EMU_SOURCE'low);
-        lane_control(i).global.l1a_source      <= felig_lane_config(i).L1A_SOURCE                (felig_lane_config(i).L1A_SOURCE'low);
-        lane_control(i).global.loopback_fifo_delay  <= felig_lane_config(i).LB_FIFO_DELAY              ;
-        lane_control(i).global.loopback_fifo_reset  <= register_map_control.FELIG_RESET.LB_FIFO            (register_map_control.FELIG_RESET.LB_FIFO'low);
-        lane_control(i).global.a_ch_bit_sel      <= felig_lane_config(i).A_CH_BIT_SEL              ;
-        --MT tmp
-        --    lane_control(i).global.b_ch_bit_sel      <= felig_lane_config(i).B_CH_BIT_SEL              ;
-        lane_control(i).global.b_ch_bit_sel      <= felig_lane_config(i).B_CH_BIT_SEL(48 downto 42)              ;
-        lane_control(i).global.l1a_counter_reset    <= '0';--register_map_control.FELIG_L1ID_RESET                        (register_map_control.FELIG_L1ID_RESET'low);
-        lane_control(i).global.MSB                  <= register_map_control.ENCODING_REVERSE_10B                    (register_map_control.ENCODING_REVERSE_10B'low);
-        lane_control(i).clock.gth_tx_pi_hold    <= felig_lane_config(i).PI_HOLD                  (felig_lane_config(i).PI_HOLD'low);
-        lane_control(i).clock.picxo_offset_en    <= felig_lane_config(i).PICXO_OFFEST_EN              (felig_lane_config(i).PICXO_OFFEST_EN'low);
-        --lane_control(i).clock.picxo_offset_ppm    <= register_map_control.FELIG_GLOBAL_CONTROL.PICXO_OFFSET_PPM  ;
-        lane_control(i).clock.picxo_offset_ppm    <= (others=> '0');
-        lane_control(i).gbt.rxslide_select      <= register_map_control.GBT_RXSLIDE_SELECT            (i+register_map_control.GBT_RXSLIDE_SELECT'low);
-        lane_control(i).gbt.rx_reset        <= register_map_control.GBT_RX_RESET              (i+register_map_control.GBT_RX_RESET'low);
-        lane_control(i).gbt.tc_edge          <= register_map_control.GBT_TC_EDGE                (i+register_map_control.GBT_TC_EDGE'low);
-        lane_control(i).gbt.tx_reset        <= register_map_control.GBT_TX_RESET              (i+register_map_control.GBT_TX_RESET'low);
-        lane_control(i).gbt.tx_tc_method      <= register_map_control.GBT_TX_TC_METHOD            (i+register_map_control.GBT_TX_TC_METHOD'low);
-        lane_control(i).gbt.rx_data_format(0)    <= register_map_control.GBT_DATA_RXFORMAT1            (i+register_map_control.GBT_DATA_RXFORMAT1'low);
-        lane_control(i).gbt.rx_data_format(1)    <= register_map_control.GBT_DATA_RXFORMAT2            (i+register_map_control.GBT_DATA_RXFORMAT2'low);
-        lane_control(i).gbt.tx_data_format(0)    <= register_map_control.GBT_DATA_TXFORMAT1            (i+register_map_control.GBT_DATA_TXFORMAT1'low);
-        lane_control(i).gbt.tx_data_format(1)    <= register_map_control.GBT_DATA_TXFORMAT2            (i+register_map_control.GBT_DATA_TXFORMAT2'low);
-        lane_control(i).gbt.tx_tc_dly_value(0)    <= register_map_control.GBT_TX_TC_DLY_VALUE1          (i+register_map_control.GBT_TX_TC_DLY_VALUE1'low);
-        lane_control(i).gbt.tx_tc_dly_value(1)    <= register_map_control.GBT_TX_TC_DLY_VALUE2          (i+register_map_control.GBT_TX_TC_DLY_VALUE2'low);
-        lane_control(i).gbt.tx_tc_dly_value(2)    <= register_map_control.GBT_TX_TC_DLY_VALUE3          (i+register_map_control.GBT_TX_TC_DLY_VALUE3'low);
-        lane_control(i).gbt.tx_tc_dly_value(3)    <= register_map_control.GBT_TX_TC_DLY_VALUE4          (i+register_map_control.GBT_TX_TC_DLY_VALUE4'low);
-        lane_control(i).gbt.loopback_enable      <= felig_lane_config(i).GBH_LB_ENABLE              (felig_lane_config(i).GBH_LB_ENABLE'low);
-        lane_control(i).gbt.rxslide_count_reset    <= register_map_control.FELIG_RX_SLIDE_RESET          (i+register_map_control.FELIG_RX_SLIDE_RESET'low);
-        lane_control(i).gth.manual_gth_rxreset    <= register_map_control.GBT_SOFT_RX_RESET.RESET_GT        (i+register_map_control.GBT_SOFT_RX_RESET.RESET_GT'low);
-        lane_control(i).gth.txpolarity        <= register_map_control.GBT_TXPOLARITY              (i+register_map_control.GBT_TXPOLARITY'low);
-        lane_control(i).gth.rxpolarity        <= register_map_control.GBT_RXPOLARITY              (i+register_map_control.GBT_RXPOLARITY'low);
-        lane_control(i).gth.loopback_enable      <= felig_lane_config(i).GBT_LB_ENABLE              (felig_lane_config(i).GBT_LB_ENABLE'low);
-        GEN_LANE_EGROUP_CONTROL_MAP : for j in lane_control(0).emulator'range generate --RL:changed so it compiles. sizes need to match 0 to 4 generate
-            --            less_that_five : if j<5 generate
-            lane_control(i).emulator(j).pattern_select(0)  <= felig_data_gen_config(i).PATTERN_SEL    (j+felig_data_gen_config(i).PATTERN_SEL'low);
-            lane_control(i).emulator(j).pattern_select(1)  <= '0'                                      ;
-            lane_control(i).emulator(j).data_format(0)    <= felig_data_gen_config(i).DATA_FORMAT    (2*j+felig_data_gen_config(i).DATA_FORMAT'low);
-            lane_control(i).emulator(j).data_format(1)      <= felig_data_gen_config(i).DATA_FORMAT    (2*j+1+felig_data_gen_config(i).DATA_FORMAT'low);
-            lane_control(i).emulator(j).sw_busy        <= felig_data_gen_config(i).SW_BUSY      (j+felig_data_gen_config(i).SW_BUSY'low);
-            lane_control(i).emulator(j).reset        <= felig_data_gen_config(i).RESET      (j+felig_data_gen_config(i).RESET'low);
-            lane_control(i).emulator(j).chunk_length    <= felig_data_gen_config(i).CHUNK_LENGTH  ;
-            lane_control(i).emulator(j).userdata            <= felig_data_gen_config_userdata(i)        ;
-        --lane_control(i).emulator(j).output_width    <= felig_elink_output_width          (i)(j*8);
-        --lane_control(i).emulator(j).userdata      <= felig_data_gen_config(i).USERDATA    ;
-        --          end generate less_that_five;
-        --          more_that_five : if j>4 generate
-        --          lane_control(i).emulator(j).pattern_select(0)  <= felig_data_gen_config(i).PATTERN_SEL    (4+felig_data_gen_config(i).PATTERN_SEL'low);
-        --          lane_control(i).emulator(j).pattern_select(1)  <= '0'                                      ;
-        --          lane_control(i).emulator(j).data_format      <= felig_data_gen_config(i).DATA_FORMAT    (4+felig_data_gen_config(i).DATA_FORMAT'low);
-        --          lane_control(i).emulator(j).sw_busy        <= felig_data_gen_config(i).SW_BUSY      (4+felig_data_gen_config(i).SW_BUSY'low);
-        --          lane_control(i).emulator(j).reset        <= felig_data_gen_config(i).RESET      (4+felig_data_gen_config(i).RESET'low);
-        --          --lane_control(i).emulator(j).output_width    <= felig_elink_output_width          (i)(4*8);
-        --          lane_control(i).emulator(j).chunk_length    <= felig_data_gen_config(i).CHUNK_LENGTH  ;
-        --          --lane_control(i).emulator(j).userdata      <= felig_data_gen_config(i).USERDATA    ;
-        --          lane_control(i).emulator(j).userdata            <= felig_data_gen_config_userdata(i)        ;
-        --        end generate more_that_five;
-        end generate GEN_LANE_EGROUP_CONTROL_MAP;
+            felig_output_width_array(0)                 <= felig_output_width;
+            felig_output_width_array(1)                 <= "000";
+            felig_output_width_array(2)                 <= "00" & felig_output_width(0);
+            felig_output_width_array(3)                 <= "000";
+            felig_output_width_array(4)                 <= '0' & felig_output_width(1 downto 0);
+            felig_output_width_array(5)                 <= "000";
+            felig_output_width_array(6)                 <= "00" & felig_output_width(0);
+            felig_output_width_array(7)                 <= "000";
+            felig_output_width_array(8)                 <= '0' & felig_output_width(1 downto 0);
+            felig_output_width_array(9)                 <= "000";
+            felig_output_width_array(10)                <= "00" & felig_output_width(0);
+            felig_output_width_array(11)                <= "000";
+            felig_output_width_array(12)                <= '0' & felig_output_width(1 downto 0);
+            felig_output_width_array(13)                <= "000";
+            felig_output_width_array(14)                <= "00" & felig_output_width(0);
+            felig_output_width_array(15)                <= "000";
+
+            lane_control(i).emulator(j).output_width    <= felig_output_width;
+
+            GEN_WIDTHS : for h in 0 to 15 generate
+                felig_elink_output_width(i)(j*16+h)     <= felig_output_width_array(h);
+                felig_elink_input_width(i)(j*16+h)      <= felig_input_width;
+                felig_elink_endian_mode(i)(j*16+h)      <= felig_endian_mode;
+            end generate GEN_WIDTHS;
+        end generate GEN_EGROUPS;
+        --loop over epaths
         GEN_LANE_ELINK_CONTROL_MAP : for j in lane_control(0).elink'range generate --RL:changed so it compiles. sizes need to match 0 to 39 generate --
-            lane_control(i).elink(j).output_width        <= felig_elink_output_width  (i)(j);
-            lane_control(i).elink(j).input_width        <= felig_elink_input_width  (i)(j);
-            lane_control(i).elink(j).endian_mode        <= felig_elink_endian_mode  (i)(j);
-            lane_control(i).elink(j).enable            <= felig_elink_enable    (i)(j);
+            lane_control(i).elink(j).output_width       <= felig_elink_output_width(i)(j);
+            lane_control(i).elink(j).input_width        <= felig_elink_input_width(i)(j);
+            lane_control(i).elink(j).endian_mode        <= felig_elink_endian_mode(i)(j);
+            lane_control(i).elink(j).enable             <= felig_elink_enable(i)(j);
         end generate GEN_LANE_ELINK_CONTROL_MAP;
     end generate GEN_LANE_CONTROL_MAP;
 
     GEN_LANE_MONITOR_MAP : for i in lane_monitor'range generate
-        register_map_monitor.register_map_link_monitor.GBT_ALIGNMENT_DONE(i)            <= lane_monitor(i).gbt.frame_locked        ;
-        register_map_monitor.register_map_link_monitor.GBT_RX_IS_HEADER(i)                <= lane_monitor(i).gbt.rx_is_header        ;
-        register_map_monitor.register_map_link_monitor.GBT_RX_HEADER_FOUND(i)              <= lane_monitor(i).gbt.rx_header_found      ;
-        register_map_monitor.register_map_link_monitor.GBT_ERROR(i)                    <= lane_monitor(i).gbt.error          ;
-        register_map_monitor.register_map_link_monitor.GBT_TXRESET_DONE(i)                <= lane_monitor(i).gth.txreset_done        ;
-        register_map_monitor.register_map_link_monitor.GBT_RXRESET_DONE(i)                <= lane_monitor(i).gth.rxreset_done        ;
-        register_map_monitor.register_map_link_monitor.GBT_TXFSMRESET_DONE(i)              <= lane_monitor(i).gth.txfsmreset_done      ;
-        register_map_monitor.register_map_link_monitor.GBT_RXFSMRESET_DONE(i)              <= lane_monitor(i).gth.rxfsmreset_done      ;
-        felig_counter_rx_slide(i)                                    <= lane_monitor(i).gbt.rxslide_count      ;
-        felig_mon_l1_id(i)                                        <= lane_monitor(i).global.l1a_id        ;
-        felig_counter_fc_error(i)                                    <= lane_monitor(i).global.fc_error_count    ;
-        felig_counter_freq_rx(i)                                    <= lane_monitor(i).clock.freq_rx_clk      ;
-        felig_counter_freq_tx(i)                                    <= lane_monitor(i).clock.freq_tx_clk      ;
-        felig_mon_picxo_error(i)                                    <= lane_monitor(i).clock.picxo_error      ;
-        felig_mon_picxo_volt(i)                                      <= lane_monitor(i).clock.picxo_volt        ;
-
-        register_map_monitor.register_map_generators.FELIG_MON_COUNTERS(i).SLIDE_COUNT      <= felig_counter_rx_slide(i)                    ;
-        register_map_monitor.register_map_generators.FELIG_MON_COUNTERS(i).FC_ERROR_COUNT   <= felig_counter_fc_error(i)                    ;
-        register_map_monitor.register_map_generators.FELIG_MON_FREQ(i).RX                   <= felig_counter_freq_rx(i)                     ;
-        register_map_monitor.register_map_generators.FELIG_MON_FREQ(i).TX                   <= felig_counter_freq_tx(i)                     ;
-        register_map_monitor.register_map_generators.FELIG_MON_PICXO(i).VLOT                <= felig_mon_picxo_volt(i)                      ;
-        register_map_monitor.register_map_generators.FELIG_MON_PICXO(i).ERROR               <= felig_mon_picxo_error(i)                     ;
-        register_map_monitor.register_map_generators.FELIG_MON_L1A_ID(i)                    <= felig_mon_l1_id(i)                           ;
-        register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).FMT                 <= lane_monitor(i).global.ttc_mon.FMT           ;
-        register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).LEN                 <= lane_monitor(i).global.ttc_mon.LEN           ;
-        register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).reserved0           <= lane_monitor(i).global.ttc_mon.reserved0     ;
-        register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).BCID                <= lane_monitor(i).global.ttc_mon.BCID          ;
-        register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).XL1ID               <= lane_monitor(i).global.ttc_mon.XL1ID         ;
-        register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).L1ID                <= lane_monitor(i).global.ttc_mon.L1ID          ;
-        register_map_monitor.register_map_generators.FELIG_MON_TTC_1(i).orbit               <= lane_monitor(i).global.ttc_mon.orbit         ;
-        register_map_monitor.register_map_generators.FELIG_MON_TTC_1(i).trigger_type        <= lane_monitor(i).global.ttc_mon.trigger_type  ;
-        register_map_monitor.register_map_generators.FELIG_MON_TTC_1(i).reserved1           <= lane_monitor(i).global.ttc_mon.reserved1     ;
+        register_map_monitor.register_map_link_monitor.GBT_ALIGNMENT_DONE(i)                <= lane_monitor(i).gbt.frame_locked;
+        register_map_monitor.register_map_link_monitor.GBT_RX_IS_HEADER(i)                  <= lane_monitor(i).gbt.rx_is_header;
+        register_map_monitor.register_map_link_monitor.GBT_RX_HEADER_FOUND(i)               <= lane_monitor(i).gbt.rx_header_found;
+        register_map_monitor.register_map_link_monitor.GBT_ERROR(i)                         <= lane_monitor(i).gbt.error;
+        register_map_monitor.register_map_link_monitor.GBT_TXRESET_DONE(i)                  <= lane_monitor(i).gth.txreset_done;
+        register_map_monitor.register_map_link_monitor.GBT_RXRESET_DONE(i)                  <= lane_monitor(i).gth.rxreset_done;
+        register_map_monitor.register_map_link_monitor.GBT_TXFSMRESET_DONE(i)               <= lane_monitor(i).gth.txfsmreset_done;
+        register_map_monitor.register_map_link_monitor.GBT_RXFSMRESET_DONE(i)               <= lane_monitor(i).gth.rxfsmreset_done;
+        register_map_monitor.register_map_generators.FELIG_MON_COUNTERS(i).SLIDE_COUNT      <= lane_monitor(i).gbt.rxslide_count;
+        register_map_monitor.register_map_generators.FELIG_MON_COUNTERS(i).FC_ERROR_COUNT   <= lane_monitor(i).global.fc_error_count;
+        register_map_monitor.register_map_generators.FELIG_MON_FREQ(i).RX                   <= lane_monitor(i).clock.freq_rx_clk;
+        register_map_monitor.register_map_generators.FELIG_MON_FREQ(i).TX                   <= lane_monitor(i).clock.freq_tx_clk;
+        register_map_monitor.register_map_generators.FELIG_MON_PICXO(i).VLOT                <= lane_monitor(i).clock.picxo_volt;
+        register_map_monitor.register_map_generators.FELIG_MON_PICXO(i).ERROR               <= lane_monitor(i).clock.picxo_error;
+        register_map_monitor.register_map_generators.FELIG_MON_L1A_ID(i)                    <= lane_monitor(i).global.l1a_id;
+        register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).FMT                 <= lane_monitor(i).global.ttc_mon.FMT;
+        register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).LEN                 <= lane_monitor(i).global.ttc_mon.LEN;
+        register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).reserved0           <= lane_monitor(i).global.ttc_mon.reserved0;
+        register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).BCID                <= lane_monitor(i).global.ttc_mon.BCID;
+        register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).XL1ID               <= lane_monitor(i).global.ttc_mon.XL1ID;
+        register_map_monitor.register_map_generators.FELIG_MON_TTC_0(i).L1ID                <= lane_monitor(i).global.ttc_mon.L1ID;
+        register_map_monitor.register_map_generators.FELIG_MON_TTC_1(i).orbit               <= lane_monitor(i).global.ttc_mon.orbit;
+        register_map_monitor.register_map_generators.FELIG_MON_TTC_1(i).trigger_type        <= lane_monitor(i).global.ttc_mon.trigger_type;
+        register_map_monitor.register_map_generators.FELIG_MON_TTC_1(i).reserved1           <= lane_monitor(i).global.ttc_mon.reserved1;
     end generate GEN_LANE_MONITOR_MAP;
 
---  GEN_ILA: if ILA = 1 generate
---     signal ila_enable          : std_logic_vector(111 downto 0);
---     signal ila_REG_ENABLE      : std_logic_vector( 39 downto 0);
---     signal ila_REG_RESET       : std_logic_vector(  6 downto 0);
---     signal ila_REG_SW_BUSY     : std_logic_vector(  6 downto 0);
---     signal ila_REG_DATA_FORMAT : std_logic_vector( 13 downto 0);
---     signal ila_REG_PATTERN_SEL : std_logic_vector(  6 downto 0);
---     signal ila_REG_ENDIAN      : std_logic_vector(  6 downto 0);
---     signal ila_REG_INWIDTH     : std_logic_vector(  6 downto 0);
---     signal ila_REG_OUTWIDTH    : std_logic_vector( 20 downto 0);
---     signal ila_clock           : std_logic;
-
---     COMPONENT ila_REG IS
---        PORT (
---            clk : IN STD_LOGIC;
---            probe0 : IN STD_LOGIC_VECTOR(111 DOWNTO 0);
---            probe1 : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
---            probe2 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
---            probe3 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
---            probe4 : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
---            probe5 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
---            probe6 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
---            probe7 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
---            probe8 : IN STD_LOGIC_VECTOR(20 DOWNTO 0)
---            );
---        END COMPONENT;
-
---  begin
---     ila_enable          <= felig_elink_enable(0);
---     ila_REG_ENABLE      <= register_map_control.FELIG_ELINK_ENABLE(0);
---     ila_REG_RESET       <= register_map_control.FELIG_DATA_GEN_CONFIG(0).RESET;
---     ila_REG_SW_BUSY     <= register_map_control.FELIG_DATA_GEN_CONFIG(0).SW_BUSY;
---     ila_REG_DATA_FORMAT <= register_map_control.FELIG_DATA_GEN_CONFIG(0).DATA_FORMAT;
---     ila_REG_PATTERN_SEL <= register_map_control.FELIG_DATA_GEN_CONFIG(0).PATTERN_SEL;
---     ila_REG_ENDIAN      <= register_map_control.FELIG_ELINK_CONFIG(0).ENDIAN_MOD;
---     ila_REG_INWIDTH     <= register_map_control.FELIG_ELINK_CONFIG(0).INPUT_WIDTH;
---     ila_REG_OUTWIDTH    <= register_map_control.FELIG_ELINK_CONFIG(0).OUTPUT_WIDTH;
---     ila_clock           <= clk;
 
---     ila_REGISTER: ila_REG
---         port map(
---             clk    => ila_clock,
---             probe0 => ila_enable,
---             probe1 => ila_REG_ENABLE,
---             probe2 => ila_REG_RESET,
---             probe3 => ila_REG_SW_BUSY,
---             probe4 => ila_REG_DATA_FORMAT,
---             probe5 => ila_REG_PATTERN_SEL,
---             probe6 => ila_REG_ENDIAN,
---             probe7 => ila_REG_INWIDTH,
---             probe8 => ila_REG_OUTWIDTH
---               );
---  end generate GEN_ILA;
+    register_map_hk_monitor_out.LMK_LOCKED(0)                                <= LMK_LOCKED;
+    register_map_hk_monitor_out.I2C_RD                                       <= register_map_hk_monitor_in.I2C_RD;
+    register_map_hk_monitor_out.I2C_WR                                       <= register_map_hk_monitor_in.I2C_WR;
+    register_map_hk_monitor_out.FPGA_CORE_TEMP                               <= register_map_hk_monitor_in.FPGA_CORE_TEMP;
+    register_map_hk_monitor_out.FPGA_CORE_VCCINT                             <= register_map_hk_monitor_in.FPGA_CORE_VCCINT;
+    register_map_hk_monitor_out.FPGA_CORE_VCCAUX                             <= register_map_hk_monitor_in.FPGA_CORE_VCCAUX;
+    register_map_hk_monitor_out.FPGA_CORE_VCCBRAM                            <= register_map_hk_monitor_in.FPGA_CORE_VCCBRAM;
+    register_map_hk_monitor_out.FPGA_DNA                                     <= register_map_hk_monitor_in.FPGA_DNA;
+    register_map_hk_monitor_out.CONFIG_FLASH_RD                              <= register_map_hk_monitor_in.CONFIG_FLASH_RD;
+    register_map_hk_monitor_out.RXUSRCLK_FREQ.VAL                            <= register_map_hk_monitor_in.RXUSRCLK_FREQ.VAL;
+    register_map_hk_monitor_out.RXUSRCLK_FREQ.VALID                          <= register_map_hk_monitor_in.RXUSRCLK_FREQ.VALID;
+    register_map_hk_monitor_out.HK_CTRL_FMC.SI5345_INTR_B                    <= register_map_hk_monitor_in.HK_CTRL_FMC.SI5345_INTR_B;
+    register_map_hk_monitor_out.HK_CTRL_FMC.SI5345_LOL                       <= register_map_hk_monitor_in.HK_CTRL_FMC.SI5345_LOL;
+    register_map_hk_monitor_out.HK_CTRL_FMC.SI5345_INTR_B                    <= register_map_hk_monitor_in.HK_CTRL_FMC.SI5345_INTR_B;
+    register_map_hk_monitor_out.HK_CTRL_FMC.SI5345_LOL_LATCHED               <= register_map_hk_monitor_in.HK_CTRL_FMC.SI5345_LOL_LATCHED;
+    register_map_hk_monitor_out.MMCM_MAIN.MAIN_INPUT                         <= register_map_hk_monitor_in.MMCM_MAIN.MAIN_INPUT;
+    register_map_hk_monitor_out.MMCM_MAIN.PLL_LOCK                           <= register_map_hk_monitor_in.MMCM_MAIN.PLL_LOCK;
+    register_map_hk_monitor_out.MMCM_MAIN.LOL_LATCHED                        <= register_map_hk_monitor_in.MMCM_MAIN.LOL_LATCHED;
+    register_map_hk_monitor_out.TACH_CNT                                     <= register_map_hk_monitor_in.TACH_CNT;
 
 end RTL;
diff --git a/sources/FelixTop/felig_top_bnl712.vhd b/sources/FelixTop/felig_top_bnl712.vhd
index f57cd7aed6834009f41102ca9ad862bb684f747f..20e80c9ca309b18e74c572e2778ca42d2d563937 100644
--- a/sources/FelixTop/felig_top_bnl712.vhd
+++ b/sources/FelixTop/felig_top_bnl712.vhd
@@ -65,6 +65,8 @@ library ieee, UNISIM;
     use work.axi_stream_package.all;
     use work.type_lib.ALL;                  --MT added
     use work.interlaken_package.slv_67_array;
+library xpm;
+    use xpm.vcomponents.all;
 
 entity felig_top_bnl712 is
     generic(
@@ -102,6 +104,7 @@ entity felig_top_bnl712 is
         IncludeEncodingEpath8_8b10b     : std_logic_vector(4 downto 0) := "00000";
         IncludeDirectEncoding           : std_logic_vector(4 downto 0) := "00000";
         INCLUDE_TTC                     : std_logic_vector(4 downto 0) := "00000";
+        TTC_SYS_SEL                     : std_logic := '0'; -- 0: TTC, 1: LTITTC P2P
         INCLUDE_RD53                    : std_logic_vector(4 downto 0) := "00000";
         DATA_WIDTH                      : integer := 256;
         PCIE_LANES                      : integer := 8;
@@ -118,6 +121,7 @@ entity felig_top_bnl712 is
         AddFULLMODEForDUNE              : boolean := false; --Add an additional FULL mode decoder without superchunk factor for DUNE
         SUPPORT_HDLC_DELAY              : boolean := false; -- support for inter-packet delays in HDLC encoders
         INCLUDE_XOFF                    : boolean := true;
+        USE_VERSAL_CPM                  : boolean := false; --set to true for BNL182
         ENABLE_XVC                      : boolean := false;
         TOP_ILA                         : integer := 0
     );
@@ -202,108 +206,67 @@ entity felig_top_bnl712 is
         sys_clk_n                 : in     std_logic_vector(ENDPOINTS-1 downto 0);
         sys_clk_p                 : in     std_logic_vector(ENDPOINTS-1 downto 0); --! 100MHz PCIe reference clock
         sys_reset_n               : in     std_logic; --! Active-low system reset from PCIe interface);
-        uC_reset_N            : out    std_logic_vector(NUM_UC_RESET_N(CARD_TYPE)-1 downto 0));
+        uC_reset_N                : out    std_logic_vector(NUM_UC_RESET_N(CARD_TYPE)-1 downto 0)
+    );
 end entity felig_top_bnl712;
 
 
 architecture structure of felig_top_bnl712 is
-
-    constant STREAMS_TOHOST    : integer := STREAMS_TOHOST_MODE(FIRMWARE_MODE);
-    constant NUMELINKmax       : integer := 112;
-    constant NUMEGROUPmax      : integer := 7;
-    signal rst_hw                              : std_logic;
-
-    signal global_reset_soft_appreg_clk        : std_logic;
-    signal global_rst_soft_40                  : std_logic;
-
-    signal clk10_xtal                          : std_logic;
-    signal clk40_xtal                          : std_logic;
-    signal clk40_rxusrclk                      : std_logic;  --MT added
-    signal clk40                               : std_logic;
-    --signal clk80                               : std_logic;--not used
-    signal clk160                              : std_logic;
-    signal clk240                              : std_logic;
-    signal clk250                              : std_logic;
-    signal clk320                              : std_logic;
-    signal clk_ttc_40_s                        : std_logic;
-    signal clk_adn_160                         : std_logic;
-    signal global_appreg_clk                   : std_logic;
-
-    signal global_register_map_control_appreg_clk : register_map_control_type;
-    signal global_register_map_40_control      : register_map_control_type;
-    signal register_map_gen_board_info         : register_map_gen_board_info_type;
-    signal register_map_link_monitor           : register_map_link_monitor_type;
-    signal register_map_ttc_monitor            : register_map_ttc_monitor_type;
-    signal register_map_ltittc_monitor          : register_map_ltittc_monitor_type;
-    signal register_map_hk_monitor             : register_map_hk_monitor_type;
-    signal register_map_generators             : register_map_generators_type;
-
-    signal BUSY_OUT_s                          : std_logic;
-
-    signal MMCM_Locked_out                     : std_logic;
-    signal MMCM_OscSelect_out                  : std_logic;
-    signal GBT_DOWNLINK_USER_DATA              : txrx120b_type(0 to (GBT_NUM-1));
-    signal GBT_UPLINK_USER_DATA                : txrx120b_type(0 to (GBT_NUM-1));
-    signal GTH_FM_RX_33b_out                   : txrx33b_type(0 to (GBT_NUM-1));
-    signal lpGBT_DOWNLINK_USER_DATA            : txrx224b_type(0 to GBT_NUM-1);
-    signal lpGBT_DOWNLINK_IC_DATA              : txrx2b_type(0 to GBT_NUM-1);
-    signal lpGBT_DOWNLINK_EC_DATA              : txrx2b_type(0 to GBT_NUM-1);
-    signal lpGBT_UPLINK_USER_DATA              : txrx32b_type(0 to GBT_NUM-1);
-    signal lpGBT_UPLINK_EC_DATA                : txrx2b_type(0 to GBT_NUM-1);
-    signal lpGBT_UPLINK_IC_DATA                : txrx2b_type(0 to GBT_NUM-1);
-
-
-
-
-    signal BUSY_REQUESTs                       : busyOut_array_type(0 to (GBT_NUM-1));
-    signal TTC_ToHost_Data                     : TTC_ToHost_data_type;
-
-    --signal cdrlocked_out                       : std_logic;
-    signal lnk_up                              : std_logic_vector(1 downto 0);
-
-    signal dma_busy_arr : std_logic_vector(ENDPOINTS-1 downto 0);
-    signal fifo_busy_arr : std_logic_vector(ENDPOINTS-1 downto 0);
-
-    signal GTREFCLK_N_s : std_logic_vector(GTREFCLKS-1 downto 0);
-    signal GTREFCLK_P_s : std_logic_vector(GTREFCLKS-1 downto 0);
-
-    signal RXUSRCLK                            : std_logic_vector(GBT_NUM-1 downto 0);
-    --signal opto_los_s : std_logic_vector(OPTO_TRX-1 downto 0);
-
-    --signal GBTFrameLocked: std_logic_vector(GBT_NUM-1 downto 0);
-
-    --MT added: usrclks from MGT (GTB wrapper) to FELIG logic
-    signal lane_control      : array_of_lane_control_type(GBT_NUM-1 downto 0);
-    signal lane_monitor      : array_of_lane_monitor_type(GBT_NUM-1 downto 0);
-    --signal pcie0_register_map_40_control        : register_map_control_type;
-    --signal pcie0_register_map_monitor           : register_map_monitor_type;
-
-    signal register_map_lane_remapper_output   : register_map_monitor_type;
-    signal linkValid_array                   : std_logic_vector(GBT_NUM-1 downto 0);
-    --MT preserve the same order as in the LPGBT Wrappwe (0 to (GBT_NUM-1));
-
-    --signal gt_txusrclk_i                        : std_logic_vector(GBT_NUM-1 downto 0);
-    --signal gt_rxusrclk_i                        : std_logic_vector(GBT_NUM-1 downto 0);
-    signal TXUSRCLK                            : std_logic_vector(GBT_NUM-1 downto 0);
-    --  signal link_tx_data_256b_array_i           : txrx256b_type(0 to GBT_NUM-1);
-    --  signal link_tx_data_256b_array_tmp         : txrx256b_type(0 to GBT_NUM-1);
-    signal link_tx_data_228b_array_tmp         : txrx228b_type(0 to GBT_NUM-1);
-    signal link_rx_data_120b_array_tmp         : txrx120b_type(0 to GBT_NUM-1);
-    signal lpgbt_rx_data_120b_array_tmp        : txrx120b_type(0 to GBT_NUM-1);
-
-    signal link_tx_flag_i : std_logic_vector(GBT_NUM-1 downto 0);
-    signal link_rx_flag_i : std_logic_vector(GBT_NUM-1 downto 0);
-
-    signal RESET_TO_LMK_i : std_logic;
-    --
-    --RL
-    signal LINKSconfig    : std_logic_vector(2 downto 0);
-
-    signal CLK40_FPGA2LMK_N_link : std_logic;
-    signal CLK40_FPGA2LMK_P_link : std_logic;
-    signal leds8 : std_logic_vector(7 downto 0);
-
-
+    constant NUMELINKmax                            : integer := 112;
+    constant NUMEGROUPmax                           : integer := 7;
+    signal rst_hw                                   : std_logic;
+    signal global_reset_soft_appreg_clk             : std_logic;
+    signal global_rst_soft_40                       : std_logic;
+    signal clk10_xtal                               : std_logic;
+    signal clk40_xtal                               : std_logic;
+    signal clk40                                    : std_logic;
+    signal clk240                                   : std_logic;
+    signal clk_adn_160                              : std_logic;
+    signal global_appreg_clk                        : std_logic;
+    signal global_register_map_control_appreg_clk   : register_map_control_type;
+    signal global_register_map_40_control           : register_map_control_type;
+    signal register_map_gen_board_info              : register_map_gen_board_info_type;
+    signal register_map_link_monitor                : register_map_link_monitor_type;
+    signal register_map_ttc_monitor                 : register_map_ttc_monitor_type;
+    signal register_map_ltittc_monitor              : register_map_ltittc_monitor_type;
+    signal register_map_hk_monitor                  : register_map_hk_monitor_type;
+    signal register_map_hk_monitor_wupper           : register_map_hk_monitor_type;
+    signal register_map_generators                  : register_map_generators_type;
+    signal MMCM_Locked_out                          : std_logic;
+    signal MMCM_OscSelect_out                       : std_logic;
+    signal LinkAligned                              : std_logic_vector(GBT_NUM-1 downto 0);
+    signal GBT_DOWNLINK_USER_DATA                   : txrx120b_type(0 to (GBT_NUM-1));
+    signal GBT_UPLINK_USER_DATA                     : txrx120b_type(0 to (GBT_NUM-1));
+    signal lpGBT_DOWNLINK_USER_DATA                 : txrx224b_type(0 to GBT_NUM-1);
+    signal lpGBT_DOWNLINK_IC_DATA                   : txrx2b_type(0 to GBT_NUM-1);
+    signal lpGBT_DOWNLINK_EC_DATA                   : txrx2b_type(0 to GBT_NUM-1);
+    signal lpGBT_UPLINK_USER_DATA                   : txrx32b_type(0 to GBT_NUM-1);
+    signal lpGBT_UPLINK_EC_DATA                     : txrx2b_type(0 to GBT_NUM-1);
+    signal lpGBT_UPLINK_IC_DATA                     : txrx2b_type(0 to GBT_NUM-1);
+    signal lpGBT_UPLINK_USER_DATA_FOSEL             : txrx224b_type(0 to GBT_NUM/ENDPOINTS-1);
+    signal lnk_up                                   : std_logic_vector(1 downto 0);
+    signal GTREFCLK_N_s                             : std_logic_vector(GTREFCLKS-1 downto 0);
+    signal GTREFCLK_P_s                             : std_logic_vector(GTREFCLKS-1 downto 0);
+    signal RXUSRCLK                                 : std_logic_vector(GBT_NUM-1 downto 0);
+    signal lane_control                             : array_of_lane_control_type(GBT_NUM-1 downto 0);
+    signal lane_monitor                             : array_of_lane_monitor_type(GBT_NUM-1 downto 0);
+    signal register_map_lane_remapper_output        : register_map_monitor_type;
+    signal TXUSRCLK                                 : std_logic_vector(GBT_NUM-1 downto 0);
+    signal link_tx_data_228b_array_tmp              : txrx228b_type(0 to GBT_NUM-1);
+    signal link_rx_data_120b_array_tmp              : txrx120b_type(0 to GBT_NUM-1);
+    signal lpgbt_rx_data_120b_array_tmp             : txrx120b_type(0 to GBT_NUM-1);
+    signal link_tx_flag_i                           : std_logic_vector(GBT_NUM-1 downto 0);
+    signal link_rx_flag_i                           : std_logic_vector(GBT_NUM-1 downto 0);
+    signal CLK40_FPGA2LMK_N_link                    : std_logic;
+    signal CLK40_FPGA2LMK_P_link                    : std_logic;
+    signal leds7                                    : std_logic_vector(6 downto 0);
+    signal LMK_LOCKED                               : std_logic;
+    signal WupperToCPM                              : WupperToCPM_array_type(0 to 1);
+    signal CPMToWupper                              : CPMToWupper_array_type(0 to 1);
+    signal data_ready_tx_to_link_wrapper            : std_logic_vector(0 to GBT_NUM-1);
+    signal DDR_inout                                : DDR_inout_array_type(0 to NUM_DDR(CARD_TYPE)-1);
+    signal LPDDR_inout                              : LPDDR_inout_array_type(0 to NUM_LPDDR(CARD_TYPE)-1);
+    signal axi_miso_ttc_lti                         : axi_miso_type;
 begin
 
     NT_PORTSEL <= "111";
@@ -317,20 +280,6 @@ begin
     SmaOut(3 downto 1)  <= (others => '0');
     I2C_nRESET_PCIe(0)  <= '1';
     uC_reset_N(0)       <= '1';
-    --opto_los_s <= OPTO_LOS;
-
-    --  g_refclk_select_0: if USE_Si5324_RefCLK generate
-    --    GTREFCLK_N_s(0) <= GTREFCLK_Si5324_N_IN;
-    --    GTREFCLK_P_s(0) <= GTREFCLK_Si5324_P_IN;
-    --  end generate;
-
-    --  g_refclk_select_1: if USE_Si5324_RefCLK = false generate
-    --    GTREFCLK_N_s(0) <= GTREFCLK_N_IN(0);
-    --    GTREFCLK_P_s(0) <= GTREFCLK_P_IN(0);
-    --  end generate;
-
-    --  GTREFCLK_N_s(GTREFCLKS-1 downto 1) <= GTREFCLK_N_IN(GTREFCLKS-1 downto 1);
-    --  GTREFCLK_P_s(GTREFCLKS-1 downto 1) <= GTREFCLK_P_IN(GTREFCLKS-1 downto 1);
 
     GTREFCLK_N_s <= GTREFCLK_N_IN;
     GTREFCLK_P_s <= GTREFCLK_P_IN;
@@ -345,12 +294,12 @@ begin
             CARD_TYPE => CARD_TYPE,
             GTHREFCLK_SEL => GTHREFCLK_SEL,
             FIRMWARE_MODE => FIRMWARE_MODE,
-            PLL_SEL => PLL_SEL,
+            PLL_SEL => '1', --CPLL not implemented
             GTREFCLKS => GTREFCLKS,
             OPTO_TRX => NUM_OPTO_LOS(CARD_TYPE))
         port map(
-            register_map_control => global_register_map_40_control, --its cool
-            register_map_link_monitor => register_map_link_monitor, -- needs confirnation
+            register_map_control => global_register_map_40_control,
+            register_map_link_monitor => register_map_link_monitor,
             clk40 => clk40,
             clk240 => clk240,
             clk40_xtal => clk40_xtal,
@@ -367,26 +316,29 @@ begin
             lpGBT_UPLINK_USER_DATA => lpGBT_UPLINK_USER_DATA,
             lpGBT_UPLINK_EC_DATA => lpGBT_UPLINK_EC_DATA,
             lpGBT_UPLINK_IC_DATA => lpGBT_UPLINK_IC_DATA,
-            LinkAligned => linkValid_array,
+            data_ready_DOWNLINK => data_ready_tx_to_link_wrapper,
+            LinkAligned => LinkAligned,
             TX_P => TX_P,
             TX_N => TX_N,
             RX_P => RX_P,
             RX_N => RX_N,
-            GTH_FM_RX_33b_out => GTH_FM_RX_33b_out,
             LMK_P => LMK_P,
             LMK_N => LMK_N,
-            --GBT FELIG specific
             link_rx_flag_i=>link_rx_flag_i,
             link_tx_flag_i=>link_tx_flag_i,
             TXUSRCLK_OUT => TXUSRCLK,
-            appreg_clk => global_appreg_clk,
             CLK40_FPGA2LMK_N => CLK40_FPGA2LMK_N_link,
             CLK40_FPGA2LMK_P => CLK40_FPGA2LMK_P_link,
-            LMK_LD => LMK_LD(0),
-            RESET_TO_LMK => RESET_TO_LMK_i,
-            clk40_rxusrclk => clk40_rxusrclk,
             clk320_in => '0', --simulation only
-            LINKSconfig => LINKSconfig);
+            clk10_xtal => clk10_xtal,
+            LMK_DATA => LMK_DATA(0),
+            LMK_CLK => LMK_CLK(0),
+            LMK_LE => LMK_LE(0),
+            LMK_GOE => LMK_GOE(0),
+            LMK_LD => LMK_LD(0),
+            LMK_SYNCn => LMK_SYNCn(0),
+            LMK_LOCKED => LMK_LOCKED
+        );
 
     clk0: entity work.clock_and_reset
         generic map(
@@ -399,21 +351,18 @@ begin
             MMCM_OscSelect_out   => MMCM_OscSelect_out,
             app_clk_in_n         => app_clk_in_n,
             app_clk_in_p         => app_clk_in_p,
-            --cdrlocked_in         => cdrlocked_out, --commented in master
-            clk10_xtal           => clk10_xtal,--open,
-            clk160               => clk160,
+            clk10_xtal           => clk10_xtal,
+            clk160               => open,
             clk240               => clk240,
-            clk250               => clk250,
-            clk320                 => clk320,
+            clk250               => open,
+            clk320               => open,
             clk40                => clk40,
             clk40_xtal           => clk40_xtal,
-            clk80                => open, --clk80, not used
+            clk80                => open,
             clk_adn_160          => clk_adn_160,
             clk_adn_160_out_n    => clk_adn_160_out_n,
             clk_adn_160_out_p    => clk_adn_160_out_p,
-            clk_ttc_40           => clk_ttc_40_s,
-            --            clk_ttcfx_mon1       => open,
-            --            clk_ttcfx_mon2       => open,
+            clk_ttc_40           => '0',
             clk_ttcfx_ref_out_n  => clk40_ttc_ref_out_n,
             clk_ttcfx_ref_out_p  => clk40_ttc_ref_out_p,
             register_map_control => global_register_map_control_appreg_clk,
@@ -432,116 +381,40 @@ begin
         lpGBT_DOWNLINK_IC_DATA(I)   <= link_tx_data_228b_array_tmp(I)(227 downto 226);
     end generate TXRXDATA_inst;
 
-    GEN_ILA: if TOP_ILA = 1 generate
-        signal ila_link_tx_data_224b_array_tmp  : txrx224b_type (3 downto 0);
-        signal ila_LINKSconfig                  : std_logic_vector(2 downto 0);
-        signal ila_clk                          : std_logic;
-        COMPONENT ila_downlink IS
-            PORT (
-                clk : IN STD_LOGIC;
-                probe0 : IN STD_LOGIC_VECTOR(223 DOWNTO 0);
-                probe1 : IN STD_LOGIC_VECTOR(223 DOWNTO 0);
-                probe2 : IN STD_LOGIC_VECTOR(223 DOWNTO 0);
-                probe3 : IN STD_LOGIC_VECTOR(223 DOWNTO 0);
-                probe4 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
-                probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
-            );
-        END COMPONENT;
-    begin
-        CLK_LPGBT: if FIRMWARE_MODE = FIRMWARE_MODE_FELIG_LPGBT generate
-            ila_clk <= clk320;
-        end generate CLK_LPGBT;
-        CLK_GBT: if FIRMWARE_MODE = FIRMWARE_MODE_FELIG_GBT generate
-            ila_clk <= clk240;
-        end generate CLK_GBT;
-        process(ila_clk)
-        begin
-            if (ila_clk'event and ila_clk='1') then
-                ila_link_tx_data_224b_array_tmp(0) <= link_tx_data_228b_array_tmp(0)(223 downto 0);
-                ila_link_tx_data_224b_array_tmp(1) <= link_tx_data_228b_array_tmp(1)(223 downto 0);
-                ila_link_tx_data_224b_array_tmp(2) <= link_tx_data_228b_array_tmp(2)(223 downto 0);
-                ila_link_tx_data_224b_array_tmp(3) <= link_tx_data_228b_array_tmp(3)(223 downto 0);
-                ila_LINKSconfig <= LINKSconfig;
-            end if;
-        end process;
-
-        ila_dlink : ila_downlink
-            port map(
-                clk       => ila_clk,
-                probe0    => ila_link_tx_data_224b_array_tmp(0),
-                probe1    => ila_link_tx_data_224b_array_tmp(1),
-                probe2    => ila_link_tx_data_224b_array_tmp(2),
-                probe3    => ila_link_tx_data_224b_array_tmp(3),
-                probe4    => ila_LINKSconfig,
-                probe5(0) => '1'
-            );
-    end generate GEN_ILA;
-
     emulatorwrapper_i : entity work.EmulatorWrapper
         generic map(
-            GBT_NUM                     => GBT_NUM,
-            NUMELINKmax                 => NUMELINKmax,
-            NUMEGROUPmax                => NUMEGROUPmax)
+            GBT_NUM                         => GBT_NUM,
+            NUMELINKmax                     => NUMELINKmax,
+            NUMEGROUPmax                    => NUMEGROUPmax,
+            FIRMWARE_MODE                   => FIRMWARE_MODE)
         port map(
-            clk_xtal_40            => clk40_xtal,
-            gt_txusrclk_in              => TXUSRCLK,--gt_txusrclk_i,
-            gt_rxusrclk_in              => RXUSRCLK,--gt_rxusrclk_i,
-            gt_rx_clk_div_2_mon        => open,
-            gt_tx_clk_div_2_mon      => open,
-            l1a_trigger_out        => open,
-            link_tx_data_228b_array_out       => link_tx_data_228b_array_tmp,
-            --cern-phase1: use only the ls 120b
-            --NB: TX: parallel uplink data out for emulator (or FE)  (for BE TX is parallel
-            --downlink data)
-            link_rx_data_120b_array_in        => link_rx_data_120b_array_tmp,
-            --cern-phase2: use only the ls 36b
-            --NB: RX : parallel downlink data in for emulator (or FE) (for BE RX is
-            --parallel uplink data)
-            --tx/rx_flag_i must come from lpgbtwrapper as in phase1
-            --was comming from TX/RX_FLAG_O of the gbt_wrapper (RX_FLAG_O 1
-            --every 6 clock to enable scrambler input scrambler 120b (need
-            --6 clks to form120b))
-            --
-            link_tx_flag_in                   => link_tx_flag_i, --gbt_tx_flag_i,
-            link_rx_flag_in                   => link_rx_flag_i, -- gbt_rx_flag_i,
-            lane_control        => lane_control,
-            lane_monitor        => lane_monitor,
-            register_map_control_40xtal  => global_register_map_40_control,
-            --MT must come from lpgbtwrapper as in phase1 was coming from frame_lock_o.
-            --rx_link_lck equivalent to frame_lock_o?
-            link_frame_locked_array_in => linkValid_array,
-            --MT/SS (SWAP LSB MSB)
-            --fhCR_REVERSE_10B            => to_sl(pcie0_register_map_40_control.CR_REVERSE_10B.FROMHOST)
-            LINKSconfig       => LINKSconfig--,
+            clk40                           => clk40,
+            gt_txusrclk_in                  => TXUSRCLK,
+            gt_rxusrclk_in                  => RXUSRCLK,
+            link_tx_data_228b_array_out     => link_tx_data_228b_array_tmp,
+            data_ready_tx_out               => data_ready_tx_to_link_wrapper,
+            link_rx_data_120b_array_in      => link_rx_data_120b_array_tmp,
+            link_tx_flag_in                 => link_tx_flag_i,
+            link_rx_flag_in                 => link_rx_flag_i,
+            lane_control                    => lane_control,
+            lane_monitor                    => lane_monitor
         );
 
     comp_LaneRegisterRemapper : entity work.LaneRegisterRemapper
         generic map(
-            GBT_NUM  => GBT_NUM,
-            FIRMWARE_MODE => FIRMWARE_MODE)
+            GBT_NUM                     => GBT_NUM,
+            FIRMWARE_MODE               => FIRMWARE_MODE)
         port map (
-            register_map_monitor  => register_map_lane_remapper_output,
-            register_map_control  => global_register_map_40_control,
-            lane_control      => lane_control,
-            lane_monitor      => lane_monitor,
-            LINKSconfig           => LINKSconfig--,
-        --    clk                   => clk40
+            register_map_monitor        => register_map_lane_remapper_output,
+            register_map_control        => global_register_map_40_control,
+            register_map_hk_monitor_in  => register_map_hk_monitor,
+            register_map_hk_monitor_out => register_map_hk_monitor_wupper,
+            LMK_LOCKED                  => LMK_LOCKED,
+            LinkAligned                 => LinkAligned,
+            lane_control                => lane_control,
+            lane_monitor                => lane_monitor
         );
 
-    --sync to appreg clk : pcie0_register_map_monitor goes to wupper
-    --appreg_sync: process(global_appreg_clk)
-    --begin
-    --  if(rising_edge(global_appreg_clk)) then
-    --    pcie0_register_map_monitor.register_map_generators    <= register_map_lane_remapper_output.register_map_generators; --needs to be checked. this type is no longer a thing. frans commented when he updated felig wupper.
-    --pcie0_register_map_monitor.register_map_gbt_monitor  <= register_map_lane_remapper_output.register_map_gbt_monitor;
-    ----commented for now as it is already done in the
-    ----register_map_sync (register_map_gbt_monitor from
-    ----FELIX_gbt_wrapper_KCU). Am I missing anything that was saved
-    ----in lane_monitor?
-    --  end if;
-    --end process;
-
-
     appreg_sync: process(global_appreg_clk)
     begin
         if(rising_edge(global_appreg_clk)) then
@@ -550,46 +423,18 @@ begin
     end process;
 
     g_endpoints: for pcie_endpoint in 0 to ENDPOINTS-1 generate
-        --signal register_map_cr_monitor             : register_map_cr_monitor_type;--not in mater
         signal register_map_crtohost_monitor       : register_map_crtohost_monitor_type;--in master
         signal register_map_crfromhost_monitor     : register_map_crfromhost_monitor_type;--in master
         signal register_map_xoff_monitor           : register_map_xoff_monitor_type;
         signal register_map_gbtemu_monitor         : register_map_gbtemu_monitor_type;
         signal register_map_decoding_monitor       : register_map_decoding_monitor_type;
-        signal register_map_encoding_monitor       : register_map_encoding_monitor_type;--in master
-        signal decoding_aclk                       : std_logic;
-        signal decoding_axis                       : axis_32_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_TOHOST-1);
-        signal decoding_axis_tready                : axis_tready_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_TOHOST-1);
-        signal decoding_axis_prog_empty            : axis_tready_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_TOHOST-1);
-        signal decoding_axis_aux                   : axis_32_array_type(0 to 1);
-        signal decoding_axis_aux_tready            : axis_tready_array_type(0 to 1);
-        signal decoding_axis_aux_prog_empty        : axis_tready_array_type(0 to 1);
-        signal Interlaken_RX_Data                  : slv_67_array(0 to GBT_NUM - 1); --RL added to comply with decoder inputs july 2023
-        signal Interlaken_RX_Datavalid             : std_logic_vector(GBT_NUM - 1 downto 0); --RL added to comply with decoder inputs july 2023
-        signal toHost_axis64_tready                : axis_tready_array_type(0 to GBT_NUM/ENDPOINTS - 1); --RL added to comply with decoder inputs july 2023
-        --signal encoding_aclk                       : std_logic;--in master, not needed
-        --signal encoding_axis                       : axis_8_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_FROMHOST-1);--in master, not needed
-        --signal encoding_axis_tready                : axis_tready_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_FROMHOST-1);--in master, not needed
+        signal register_map_encoding_monitor       : register_map_encoding_monitor_type;
+        signal wr_data_count                       : slv12_array(0 to NUMBER_OF_DESCRIPTORS-2);
         signal rst_soft_40                         : std_logic;
         signal reset_soft_appreg_clk               : std_logic;
-        signal fanout_sel_axis                       : axis_32_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_TOHOST-1);
-        signal fanout_sel_axis_tready                : axis_tready_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_TOHOST-1);
-        signal fanout_sel_axis_prog_empty            : axis_tready_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_TOHOST-1);
         signal appreg_clk: std_logic;
         signal register_map_control_appreg_clk       : register_map_control_type;
         signal register_map_40_control               : register_map_control_type;
-        signal GBT_UPLINK_USER_DATA_FOSEL : txrx120b_type (0 to GBT_NUM/ENDPOINTS-1);
-        signal lpGBT_UPLINK_USER_DATA_FOSEL      : txrx224b_type(0 to GBT_NUM/ENDPOINTS-1);--in master
-        signal lpGBT_UPLINK_EC_DATA_FOSEL        : txrx2b_type(0 to GBT_NUM/ENDPOINTS-1);--in master
-        signal lpGBT_UPLINK_IC_DATA_FOSEL        : txrx2b_type(0 to GBT_NUM/ENDPOINTS-1);--in master
-        signal LinkAligned_FOSEL : std_logic_vector(GBT_NUM/ENDPOINTS-1 downto 0);
-        signal aresetn                             : std_logic;
-        signal ElinkBusy : busyOut_array_type(0 to GBT_NUM/ENDPOINTS-1);
-        signal clk250_out_pcie : std_logic;
-        signal CPMToWupper : CPMToWupper_type;
-        signal WupperToCPM : WupperToCPM_type;
-        signal daq_reset: std_logic;
-        signal daq_fifo_flush: std_logic;
 
     begin
         g_assign_endpoint0: if pcie_endpoint = 0 generate
@@ -600,26 +445,18 @@ begin
             global_rst_soft_40 <= rst_soft_40;
         end generate;
 
-        aresetn <= not(rst_hw or rst_soft_40);
-        daq_reset <= rst_hw or rst_soft_40;
-        daq_fifo_flush <= rst_soft_40;
-
         pcie0: entity work.wupper
             generic map(
                 NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS,
                 NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS,
                 BUILD_DATETIME => BUILD_DATETIME,
-                --SVN_VERSION => 0,--not in master
                 CARD_TYPE => CARD_TYPE,
                 GIT_HASH => GIT_HASH,
                 COMMIT_DATETIME => COMMIT_DATETIME,
                 GIT_TAG => GIT_TAG,
                 GIT_COMMIT_NUMBER => GIT_COMMIT_NUMBER,
-                --                GBT_GENERATE_ALL_REGS => true,
-                --                EMU_GENERATE_REGS => true,
-                --                MROD_GENERATE_REGS => false,--in master
-                GBT_NUM => GBT_NUM,--in master
-                FIRMWARE_MODE => FIRMWARE_MODE,--in master
+                GBT_NUM => GBT_NUM,
+                FIRMWARE_MODE => FIRMWARE_MODE,
                 PCIE_ENDPOINT => pcie_endpoint,
                 PCIE_LANES => PCIE_LANES,
                 DATA_WIDTH => DATA_WIDTH,
@@ -651,181 +488,65 @@ begin
                 register_map_ttc_monitor => register_map_ttc_monitor,
                 register_map_ltittc_monitor => register_map_ltittc_monitor,
                 register_map_xoff_monitor => register_map_xoff_monitor,
-                register_map_hk_monitor => register_map_hk_monitor,
-                register_map_generators => register_map_generators, --register_map_lane_remapper_output.register_map_generators,--register_map_generators_c,
+                register_map_hk_monitor => register_map_hk_monitor_wupper,
+                register_map_generators => register_map_generators,
                 wishbone_monitor => wishbone_monitor_c,
                 ipbus_monitor => ipbus_monitor_c,
                 regmap_mrod_monitor => regmap_mrod_monitor_c,
                 reset_hard => open,
                 reset_soft => open,
                 reset_soft_appreg_clk => reset_soft_appreg_clk,
-                --reset_hw_in => rst_hw,
                 sys_clk_n => sys_clk_n(pcie_endpoint),
                 sys_clk_p => sys_clk_p(pcie_endpoint),
                 sys_reset_n => sys_reset_n,
                 tohost_busy_out => open,
                 fromHostFifo_dout => open,
                 fromHostFifo_empty => open,
-                fromHostFifo_rd_clk => clk250_out_pcie,
+                fromHostFifo_rd_clk => clk40,
                 fromHostFifo_rd_en => '0',
                 fromHostFifo_rst => rst_hw,
                 toHostFifo_din => (others=> (others=> '0')),
                 toHostFifo_prog_full => open,
                 toHostFifo_rst => rst_hw,
-                toHostFifo_wr_clk => clk250_out_pcie,
+                toHostFifo_wr_clk => clk40,
                 toHostFifo_wr_en => (others=> '0'),
-                clk250_out => clk250_out_pcie,
+                clk250_out => open,
                 master_busy_in => '0',
-                CPMToWupper => CPMToWupper,
-                WupperToCPM => WupperToCPM
+                CPMToWupper => CPMToWupper(pcie_endpoint),
+                WupperToCPM => WupperToCPM(pcie_endpoint)
             );
 
-        --    decoding0: entity work.decoding
-        --      generic map(
-        --        GBT_NUM => GBT_NUM/ENDPOINTS,
-        --        FIRMWARE_MODE => FIRMWARE_MODE,
-        --        STREAMS_TOHOST => STREAMS_TOHOST,
-        --        BLOCKSIZE => BLOCKSIZE,
-        --        LOCK_PERIOD => LOCK_PERIOD,
-        --        IncludeDecodingEpath2_HDLC =>IncludeDecodingEpath2_HDLC,
-        --        IncludeDecodingEpath2_8b10b =>IncludeDecodingEpath2_8b10b,
-        --        IncludeDecodingEpath4_8b10b =>IncludeDecodingEpath4_8b10b,
-        --        IncludeDecodingEpath8_8b10b =>IncludeDecodingEpath8_8b10b,
-        --        IncludeDecodingEpath16_8b10b =>IncludeDecodingEpath16_8b10b,
-        --        IncludeDecodingEpath32_8b10b =>IncludeDecodingEpath32_8b10b)
-        --      port map(
-        --        RXUSRCLK                      => RXUSRCLK(((GBT_NUM/ENDPOINTS)*(pcie_endpoint+1))-1 downto (GBT_NUM/ENDPOINTS)*pcie_endpoint),
-        --        FULL_UPLINK_USER_DATA         => GTH_FM_RX_33b_out((GBT_NUM/ENDPOINTS)*pcie_endpoint to((GBT_NUM/ENDPOINTS)*(pcie_endpoint+1))-1),
-        --        GBT_UPLINK_USER_DATA          => GBT_UPLINK_USER_DATA((GBT_NUM/ENDPOINTS)*pcie_endpoint to((GBT_NUM/ENDPOINTS)*(pcie_endpoint+1))-1),--GBT_UPLINK_USER_DATA_FOSEL,
-        --        lpGBT_UPLINK_USER_DATA        => (others => (others => '0')), --lpGBT_UPLINK_USER_DATA_FOSEL TODO: connect lpGBT data : in  txrx230b_type(GBT_NUM-1 downto 0); --lpGBT data input
-        --        lpGBT_UPLINK_EC_DATA          => (others => (others => '0')), --lpGBT_UPLINK_EC_DATA_FOSEL TODO: connect lpGBT data : in  txrx2b_type(GBT_NUM-1 downto 0);   --lpGBT EC data input
-        --        lpGBT_UPLINK_IC_DATA          => (others => (others => '0')), --lpGBT_UPLINK_IC_DATA_FOSEL TODO: connect lpGBT data : in  txrx2b_type(GBT_NUM-1 downto 0);   --lpGBT IC data input
-        --        LinkAligned                   => LinkAligned(((GBT_NUM/ENDPOINTS)*(pcie_endpoint+1))-1 downto (GBT_NUM/ENDPOINTS)*pcie_endpoint),--LinkAligned_FOSEL,
-        --        clk160                        => clk160,
-        --        clk250                        => clk250,
-        --        clk40                         => clk40,
-        --        aclk                          => decoding_aclk,
-        --        aresetn                       => aresetn,
-        --        m_axis                        => decoding_axis,
-        --        m_axis_tready                 => decoding_axis_tready,
-        --        m_axis_prog_empty             => decoding_axis_prog_empty,
-        --        register_map_control          => register_map_40_control,
-        --        register_map_decoding_monitor => register_map_decoding_monitor);
-
-        decoding0: entity work.decoding
-            generic map(
-                GBT_NUM => GBT_NUM/ENDPOINTS,
-                FIRMWARE_MODE => FIRMWARE_MODE,
-                STREAMS_TOHOST => STREAMS_TOHOST,
-                BLOCKSIZE => BLOCKSIZE,
-                LOCK_PERIOD => LOCK_PERIOD,
-                IncludeDecodingEpath2_HDLC => IncludeDecodingEpath2_HDLC,
-                IncludeDecodingEpath2_8b10b => IncludeDecodingEpath2_8b10b,
-                IncludeDecodingEpath4_8b10b => IncludeDecodingEpath4_8b10b,
-                IncludeDecodingEpath8_8b10b => IncludeDecodingEpath8_8b10b,
-                IncludeDecodingEpath16_8b10b => IncludeDecodingEpath16_8b10b,
-                IncludeDecodingEpath32_8b10b => IncludeDecodingEpath32_8b10b,
-                PCIE_ENDPOINT  => pcie_endpoint
-            )
-            Port map(
-                RXUSRCLK                        => RXUSRCLK(((GBT_NUM/ENDPOINTS)*(pcie_endpoint+1))-1 downto (GBT_NUM/ENDPOINTS)*pcie_endpoint),
-                FULL_UPLINK_USER_DATA           => GTH_FM_RX_33b_out((GBT_NUM/ENDPOINTS)*pcie_endpoint to((GBT_NUM/ENDPOINTS)*(pcie_endpoint+1))-1),
-                GBT_UPLINK_USER_DATA            => GBT_UPLINK_USER_DATA_FOSEL,
-                lpGBT_UPLINK_USER_DATA          => lpGBT_UPLINK_USER_DATA_FOSEL,
-                lpGBT_UPLINK_EC_DATA            => lpGBT_UPLINK_EC_DATA_FOSEL,
-                lpGBT_UPLINK_IC_DATA            => lpGBT_UPLINK_IC_DATA_FOSEL,
-                LinkAligned                     => LinkAligned_FOSEL,
-                clk160                          => clk160,
-                clk240                          => '0', --
-                clk250                          => clk250,
-                clk40                           => clk40,
-                clk365                          => '0', --
-                aclk_out                        => decoding_aclk,
-                daq_reset                       => daq_reset, --aresetn                         => aresetn,
-                daq_fifo_flush                  => daq_fifo_flush,
-                m_axis                          => decoding_axis,
-                m_axis_tready                   => decoding_axis_tready,
-                m_axis_prog_empty               => decoding_axis_prog_empty,
-                m_axis_noSC                     => open,
-                m_axis_noSC_tready              => (others =>(others=>'0')),
-                m_axis_noSC_prog_empty          => open,
-                TTC_ToHost_Data_in              => TTC_ToHost_Data,
-                ElinkBusyIn                     => ElinkBusy,
-                DmaBusyIn                       => dma_busy_arr(pcie_endpoint),
-                FifoBusyIn                      => fifo_busy_arr(pcie_endpoint),
-                BusySumIn                       => BUSY_OUT_s,
-                m_axis_aux                      => decoding_axis_aux,
-                m_axis_aux_prog_empty           => decoding_axis_aux_prog_empty,
-                m_axis_aux_tready               => decoding_axis_aux_tready,
-                register_map_control            => register_map_40_control,
-                register_map_decoding_monitor   => register_map_decoding_monitor,
-                TTCin                           => TTC_zero,
-
-                --RL added july2023
-                Interlaken_RX_Data_In           => Interlaken_RX_Data(pcie_endpoint*(GBT_NUM/ENDPOINTS) to ((pcie_endpoint+1)*(GBT_NUM/ENDPOINTS))-1),
-                Interlaken_RX_Datavalid         => Interlaken_RX_Datavalid(((pcie_endpoint+1)*(GBT_NUM/ENDPOINTS))-1 downto pcie_endpoint*(GBT_NUM/ENDPOINTS)),
-                Interlaken_RX_Gearboxslip       => open,
-                Interlaken_Decoder_Aligned_out  => open,
-                m_axis64                        => open,
-                m_axis64_tready                 => toHost_axis64_tready,
-                m_axis64_prog_empty             => open,
-                toHost_axis64_aclk_out          => open
-            --                CBOPT                         => CBOPT_vio,
-            --                DIS_LANE_IN                   => DIS_LANE_vio,
-            --                mask_k_char                   => mask_k_char_vio
-            );
-
-
-
-        g_DisableFullModeEmulator: if FIRMWARE_MODE /= FIRMWARE_MODE_FULL generate
-            fanout_sel_axis <= decoding_axis;
-            decoding_axis_tready <= fanout_sel_axis_tready;
-            fanout_sel_axis_prog_empty <= decoding_axis_prog_empty;
-        end generate;
-
-        g_busy0: for i in 0 to GBT_NUM/ENDPOINTS-1 generate
-            g_elinks_busy: for j in 0 to STREAMS_TOHOST-1 generate
-                BUSY_REQUESTs(i + pcie_endpoint* GBT_NUM/ENDPOINTS)(j) <= fanout_sel_axis(i,j).tuser(2);
-            end generate;
-            g_unimplemented: for j in STREAMS_TOHOST to 51 generate
-                BUSY_REQUESTs(i + pcie_endpoint* GBT_NUM/ENDPOINTS)(j) <= '0';
-            end generate;
-        end generate;
-
     end generate;
 
-    hk0: entity work.housekeeping_module_FELIG
+    hk0: entity work.housekeeping_module
         generic map(
             CARD_TYPE => CARD_TYPE,
-            OPTO_TRX => NUM_OPTO_LOS(CARD_TYPE),
             GBT_NUM => GBT_NUM/ENDPOINTS,
             ENDPOINTS => ENDPOINTS,
             generateTTCemu => generateTTCemu,
-            --GENERATE_GBT => false,--not in master
-            --wideMode => false,--not in master
             AUTOMATIC_CLOCK_SWITCH => AUTOMATIC_CLOCK_SWITCH,
             FIRMWARE_MODE => FIRMWARE_MODE,
-            --generate_IC_EC_TTC_only => false,--not in master
-            --GTHREFCLK_SEL => GTHREFCLK_SEL,--not in master
             USE_Si5324_RefCLK => USE_Si5324_RefCLK,
-            --MT added: =1 to use RXUSRCKL scaled down to 40 MHZ for TX GTREFCLK, =0
-            --to use xtal_40
-            --USE_LMK_RXUSRCLK => true,--RL: removed not needed with protocol
             GENERATE_XOFF => GENERATE_XOFF,
             IncludeDecodingEpath2_HDLC => IncludeDecodingEpath2_HDLC,
             IncludeDecodingEpath2_8b10b => IncludeDecodingEpath2_8b10b,
             IncludeDecodingEpath4_8b10b => IncludeDecodingEpath4_8b10b,
             IncludeDecodingEpath8_8b10b => IncludeDecodingEpath8_8b10b,
             IncludeDecodingEpath16_8b10b => IncludeDecodingEpath16_8b10b,
-            --IncludeDecodingEpath32_8b10b => IncludeDecodingEpath32_8b10b,
+            IncludeDecodingEpath32_8b10b => IncludeDecodingEpath32_8b10b,
+            IncludeDirectDecoding => IncludeDirectDecoding,
             IncludeEncodingEpath2_HDLC      => IncludeEncodingEpath2_HDLC,
             IncludeEncodingEpath2_8b10b     => IncludeEncodingEpath2_8b10b,
             IncludeEncodingEpath4_8b10b     => IncludeEncodingEpath4_8b10b,
             IncludeEncodingEpath8_8b10b     => IncludeEncodingEpath8_8b10b,
-            --GENERATE_FEI4B => false,--not in master
+            IncludeDirectEncoding => IncludeDirectEncoding,
             BLOCKSIZE => BLOCKSIZE,
-            CHUNK_TRAILER_32B => CHUNK_TRAILER_32B)
-        --SUPER_CHUNK_FACTOR => SUPER_CHUNK_FACTOR) --not in master
+            DATA_WIDTH => DATA_WIDTH,
+            FULL_HALFRATE => FULL_HALFRATE,
+            SUPPORT_HDLC_DELAY => SUPPORT_HDLC_DELAY,
+            TTC_SYS_SEL => TTC_SYS_SEL,
+            USE_VERSAL_CPM => USE_VERSAL_CPM
+        )
         port map(
             MMCM_Locked_in => MMCM_Locked_out,
             MMCM_OscSelect_in => MMCM_OscSelect_out,
@@ -833,62 +554,84 @@ begin
             SDA => SDA,
             SI5345_A => SI5345_A,
             SI5345_INSEL => SI5345_INSEL,
-            SI5345_OE => SI5345_OE(0),
-            SI5345_RSTN => SI5345_RSTN(0),
-            SI5345_SEL => SI5345_SEL(0),
-            SI5345_nLOL => SI5345_nLOL(0),
+            SI5345_OE => SI5345_OE,
+            SI5345_RSTN => SI5345_RSTN,
+            SI5345_SEL => SI5345_SEL,
+            SI5345_nLOL => SI5345_nLOL,
+            SI5345_FINC_B => open,
+            SI5345_FDEC_B => open,
+            SI5345_INTR_B => (others => '0'),
             appreg_clk => global_appreg_clk,
-            emcclk => emcclk(0),
-            flash_SEL => flash_SEL(0),
+            emcclk => emcclk,
+            flash_SEL => flash_SEL,
             flash_a => flash_a,
             flash_a_msb => flash_a_msb,
-            flash_adv => flash_adv(0),
-            flash_cclk => flash_cclk(0),
-            flash_ce => flash_ce(0),
+            flash_adv => flash_adv,
+            flash_cclk => flash_cclk,
+            flash_ce => flash_ce,
             flash_d => flash_d,
-            flash_re => flash_re(0),
-            flash_we => flash_we(0),
-            i2cmux_rst => i2cmux_rst(0),
-            TACH => TACH(0),
+            flash_re => flash_re,
+            flash_we => flash_we,
+            i2cmux_rst => i2cmux_rst,
+            TACH => TACH,
+            FAN_FAIL_B => (others => '0'),
+            FAN_FULLSP => (others => '0'),
+            FAN_OT_B => (others => '0'),
+            FAN_PWM => open,
+            FF3_PRSNT_B => (others => '0'),
+            IOEXPAN_INTR_B => (others => '0'),
+            IOEXPAN_RST_B => open,
             clk10_xtal => clk10_xtal,
             clk40_xtal => clk40_xtal,
-            clk40 => clk40, --MT added
-            --MT added
-            clk40_rxusrclk => clk40_rxusrclk,--not in master
-            RESET_TO_LMK => RESET_TO_LMK_i,--not in master
-            --
-            leds => leds8,
+            leds => leds7,
             opto_inhibit => opto_inhibit,
-            --opto_los => OPTO_LOS,--commented in master
             register_map_control => global_register_map_control_appreg_clk,
             register_map_gen_board_info => register_map_gen_board_info,
             register_map_hk_monitor => register_map_hk_monitor,
             rst_soft => global_reset_soft_appreg_clk,
             sys_reset_n => sys_reset_n,
+            PCIE_PWRBRK => (others => '0'),
+            PCIE_WAKE_B => (others => '0'),
+            QSPI_RST_B => open,
             rst_hw => rst_hw,
-            CLK40_FPGA2LMK_P => open, --RL from link_wrapper
-            CLK40_FPGA2LMK_N => open, --RL from link_wrapper
-            LMK_DATA => LMK_DATA(0),
-            LMK_CLK => LMK_CLK(0),
-            LMK_LE => LMK_LE(0),
-            LMK_GOE => LMK_GOE(0),
-            LMK_LD => LMK_LD(0),
-            LMK_SYNCn => LMK_SYNCn(0),
-            I2C_SMB => I2C_SMB(0),
-            I2C_SMBUS_CFG_nEN => I2C_SMBUS_CFG_nEN(0),
-            MGMT_PORT_EN => MGMT_PORT_EN(0),
-            PCIE_PERSTn1 => PCIE_PERSTn_out(0),
-            PCIE_PERSTn2 => PCIE_PERSTn_out(1),
-            PEX_PERSTn => PEX_PERSTn(0),
-            PEX_SCL => PEX_SCL(0),
-            PEX_SDA => PEX_SDA(0),
+            CLK40_FPGA2LMK_P => open,--CLK40_FPGA2LMK_P,
+            CLK40_FPGA2LMK_N => open,--CLK40_FPGA2LMK_N,
+            LMK_DATA => open,--LMK_DATA,
+            LMK_CLK => open,--LMK_CLK,
+            LMK_LE => open,--LMK_LE,
+            LMK_GOE => open,--LMK_GOE,
+            LMK_LD => (others => '0'),--LMK_LD,
+            LMK_SYNCn => open,--LMK_SYNCn,
+            I2C_SMB => I2C_SMB,
+            I2C_SMBUS_CFG_nEN => I2C_SMBUS_CFG_nEN,
+            MGMT_PORT_EN => MGMT_PORT_EN,
+            PCIE_PERSTn_out => PCIE_PERSTn_out,
+            PEX_PERSTn => PEX_PERSTn,
+            PEX_SCL => PEX_SCL,
+            PEX_SDA => PEX_SDA,
             PORT_GOOD => PORT_GOOD,
-            SHPC_INT => SHPC_INT(0),
+            SHPC_INT => SHPC_INT,
             lnk_up => lnk_up,
             select_bifurcation => select_bifurcation,
-            RXUSRCLK_IN => RXUSRCLK);
-
-    leds <= leds8(NUM_LEDS(CARD_TYPE)-1 downto 0);
+            RXUSRCLK_IN => RXUSRCLK,
+            versal_sys_reset_n_out => open,
+            WupperToCPM => WupperToCPM,
+            CPMToWupper => CPMToWupper,
+            clk100_out => open,
+            DDR_in => (others => (others => "0")),
+            DDR_out => open,
+            DDR_inout => DDR_inout,
+            axi_miso_ttc_lti => axi_miso_ttc_lti,
+            axi_mosi_ttc_lti => open,
+            apb3_axi_clk => open,
+            LTI2cips_gpio => (others => '0'),
+            cips2LTI_gpio => open,
+
+            LPDDR_in => (others => (others => "0")),
+            LPDDR_out => open,
+            LPDDR_inout => LPDDR_inout
+        );
 
+    leds <= leds7(NUM_LEDS(CARD_TYPE)-1 downto 0);
 end architecture structure ; -- of felig_top_bnl712
 
diff --git a/sources/LpGBT/LpGBT_CERN/FE/lpgbt-emul b/sources/LpGBT/LpGBT_CERN/FE/lpgbt-emul
index 131a56e917b6c6ce59b284f48321b2f9681c55ea..8cbbdea3025598f9c2719e5fe4ad1f2f357a9d79 160000
--- a/sources/LpGBT/LpGBT_CERN/FE/lpgbt-emul
+++ b/sources/LpGBT/LpGBT_CERN/FE/lpgbt-emul
@@ -1 +1 @@
-Subproject commit 131a56e917b6c6ce59b284f48321b2f9681c55ea
+Subproject commit 8cbbdea3025598f9c2719e5fe4ad1f2f357a9d79
diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE.vhd
index 6e55e0b42889f1128c1e1c83bdd34b99a8b29573..d1e7d7bc5b29ba769b6a13831a9e2d6bbf0e0dfd 100644
--- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE.vhd
@@ -49,35 +49,22 @@ library XPM;
 entity FLX_LpGBT_FE is
     Port
     (
-        TXCLK40                         : in std_logic;
-        RXCLK40                         : in std_logic;
+        clk40_in                        : in std_logic;
         TXCLK320                        : in std_logic;
         RXCLK320                        : in std_logic;
         rst_uplink_i                    : in std_logic;
-        --uplinkClkEn_i                   : in std_logic;
         ctr_clkSlip_s                   : out std_logic;
         aligned                         : out std_logic;
-        --uplinkRdy_o                     : out std_logic;
-        --downlinkRdy_o                   : out std_logic;
         sta_headerFlag_o                : out std_logic;
-        sta_headerFlag_shift            : out std_logic;
-        --sta_rxgbxRdy_o                  : out std_logic;
-        clk_dataFlag_rxGb_s_o           : out std_logic;
         dat_upLinkWord_fromGb_s         : out std_logic_vector(31 downto 0);
         dat_downLinkWord_fromMgt_s16    : in std_logic_vector(15 downto 0);
-        --sta_mgtTxRdy_s                  : in std_logic;
         rst_dnlink_i                    : in std_logic;
         sta_mgtRxRdy_s                  : in std_logic;
-
         downLinkBypassDeinterleaver     : in std_logic;
         downLinkBypassFECDecoder        : in std_logic;
         downLinkBypassDescsrambler      : in std_logic;
-
         enableFECErrCounter             : in std_logic;
-
         upLinkScramblerBypass           : in std_logic;
-
-        upLinkFecBypass                 : in std_logic;
         upLinkInterleaverBypass         : in std_logic;
         fecMode                         : in std_logic;
         txDataRate                      : in std_logic;
@@ -85,72 +72,37 @@ entity FLX_LpGBT_FE is
         upLinkData                      : in std_logic_vector(223 downto 0);
         upLinkDataIC                    : in std_logic_vector(1 downto 0);
         upLinkDataEC                    : in std_logic_vector(1 downto 0);
+        upLinkDataREADY                 : in std_logic;
         downLinkData                    : out std_logic_vector(31 downto 0);
         downLinkDataIC                  : out std_logic_vector(1 downto 0);
         downLinkDataEC                  : out std_logic_vector(1 downto 0);
-        --MT added: needed by FELIG to latch tx payload to generated data. Need to
-        --be synchronized with emulator logic
-        tx_flag_out                     : out std_logic
-
-
+        tx_flag_out                     : out std_logic;
+        fecCorrectionCount              : out std_logic_vector(15 downto 0)
     );
 end FLX_LpGBT_FE;
 
 architecture Behavioral of FLX_LpGBT_FE is
-
-    --signal clk_mgtTxUsrclkToEmul_s              : std_logic;
-    --signal clk_mgtRxUsrclkToEmul_s              : std_logic;
-
-
     signal rst_pattsearch_s                     : std_logic;
     signal sta_headeLocked_s                    : std_logic;
     signal sta_headerFlag_s                     : std_logic;
     signal sta_headerFlag_s_r1                  : std_logic;
     signal sta_headerFlag_s_r2                  : std_logic;
-
-    --signal sta_rxgbxRdy_s                       : std_logic;
     signal sta_headerFlag_s_r3                  : std_logic;
     signal sta_headerFlag_s_r4                  : std_logic;
-
-    --signal rstn_datapath_s                      : std_logic;
-    --signal rst_datapath_s                       : std_logic;
-
     signal dat_downLinkWord_fromGb_s            : std_logic_vector(63 downto 0);
-    --signal dat_downLinkWord_fromGbInv_s         : std_logic_vector(63 downto 0);
     signal dat_downLinkWord_toPattSrch_s        : std_logic_vector(15 downto 0);
-
-    --signal downlinkRdy_s0                       : std_logic;
-    --signal downlinkRdy_s1                       : std_logic;
-
-    --signal uplinkClkEn_sh_s                     : std_logic;
-    --signal uplinkClkEn_shgb_s                   : std_logic;
-    --signal sta_txGbRdy_s                        : std_logic;
-
     signal dat_upLinkWord_fromLpGBT_s           : std_logic_vector(255 downto 0);
-    --signal dat_upLinkWord_fromLpGBT_pipeline_s  : std_logic_vector(255 downto 0);
-    --signal dat_upLinkWord_toGb_s                : std_logic_vector(255 downto 0);
     signal dat_upLinkWord_toGb_pipeline_s       : std_logic_vector(255 downto 0);
     signal dat_upLinkWord_toGb_pipeline_s_r     : std_logic_vector(255 downto 0);
     signal dat_upLinkWord_toGb_pipeline_s_inv   : std_logic_vector(255 downto 0);
-
-    --signal rst_uplinkGb_s                       : std_logic;
     signal RXCLK40_r                            : std_logic;
-    --signal rst_uplinkGb_synch_s                 : std_logic;
-    --signal rst_uplinkMgt_s                      : std_logic;
     signal sel                                  : std_logic;
-    --signal rst_uplinkInitDone_s                 : std_logic;
-    --signal rst_downlinkInitDone_s               : std_logic;
-
-    --signal RX_CLKEn_s                           : std_logic;
-    --signal RX_CLK40_s                           : std_logic;
     signal TXCLK40_r                            : std_logic;
-
     signal downLinkDataIc_s                     : std_logic_vector(1 downto 0);
     signal downLinkDataEc_s                     : std_logic_vector(1 downto 0);
     signal downLinkDataGroup1_s                 : std_logic_vector(15 downto 0);
     signal downLinkDataGroup0_s                 : std_logic_vector(15 downto 0);
-
-    constant clk_dataFlag_rxGb_s                  : std_logic := '0';
+    constant clk_dataFlag_rxGb_s                : std_logic := '0';
     signal txcnt                                : std_logic_vector(2 downto 0);
     signal count_rx                             : std_logic_vector(2 downto 0);
     signal upLinkData0_s                        : std_logic_vector(31 downto 0);
@@ -161,100 +113,24 @@ architecture Behavioral of FLX_LpGBT_FE is
     signal upLinkData5_s                        : std_logic_vector(31 downto 0);
     signal dat_downLinkWord_fromMgt_s           : std_logic_vector(31 downto 0);
     signal upLinkData6_s                        : std_logic_vector(31 downto 0);
-    --signal upLinkDataIC_s                       : std_logic_vector(1 downto 0);
-    --signal upLinkDataEC_s                       : std_logic_vector(1 downto 0);
     signal dat_downLinkWord_fromMgt_s64         : std_logic_vector(63 downto 0);
     signal dat_downLinkWord_fromGb_s_buf        : std_logic_vector(63 downto 0);
     signal dat_downLinkWord_fromMgt_s8          : std_logic_vector(7 downto 0);
-
-    signal sta_headerFlag_s_vec: std_logic_vector(9 downto 0);
-    signal sta_headerFlag_s0: std_logic;
-
-    signal TXCLK40_320: std_logic; --CDC synchronized version of TXCLK40 in 8 320MHz clocks
-    signal RXCLK40_320: std_logic; --CDC synchronized version of RXCLK40 in 8 320MHz clocks
-
-    component upLinkTxDataPath
-        port (
-            clk                 : in  std_logic;
-            dataEnable          : in  std_logic;
-            txDataGroup0        : in  std_logic_vector(31 downto 0);
-            txDataGroup1        : in  std_logic_vector(31 downto 0);
-            txDataGroup2        : in  std_logic_vector(31 downto 0);
-            txDataGroup3        : in  std_logic_vector(31 downto 0);
-            txDataGroup4        : in  std_logic_vector(31 downto 0);
-            txDataGroup5        : in  std_logic_vector(31 downto 0);
-            txDataGroup6        : in  std_logic_vector(31 downto 0);
-
-            txIC                : in  std_logic_vector(  1 downto 0);
-            txEC                : in  std_logic_vector(  1 downto 0);
-            txDummyFec5         : in  std_logic_vector(  5 downto 0);
-            txDummyFec12        : in  std_logic_vector(  9 downto 0);
-            scramblerBypass     : in  std_logic;
-            interleaverBypass   : in  std_logic;
-            fecMode             : in  std_logic;
-            txDataRate          : in  std_logic;
-            fecDisable          : in  std_logic;
-            scramblerReset      : in  std_logic;
-            upLinkFrame         : out std_logic_vector(255 downto 0)
-        );
-    end component;
-
-    component downLinkRxDataPath
-        port (
-            clk                 : in  std_logic;
-            downLinkFrame       : in  std_logic_vector( 63 downto 0);
-            dataStrobe          : out std_logic;
-            dataOut             : out std_logic_vector( 31 downto 0);
-            dataEC              : out std_logic_vector(  1 downto 0);
-            dataIC              : out std_logic_vector(  1 downto 0);
-            header              : out std_logic_vector(  3 downto 0);
-            dataEnable          : in  std_logic;
-            bypassDeinterleaver : in  std_logic;
-            bypassFECDecoder    : in  std_logic;
-            bypassDescrambler   : in  std_logic;
-            fecCorrectionCount  : out std_logic_vector( 15 downto 0)
-        );
-    end component;
-
-    COMPONENT mgt_framealigner IS
-        GENERIC (
-            c_wordRatio                      : integer;             --! Word ration: frameclock / mgt_wordclock
-            c_wordSize                       : integer;             --! Size of the mgt word
-            c_headerPattern                  : std_logic_vector;    --! Header pattern specified by the standard
-            c_allowedFalseHeader             : integer;             --! Number of false header allowed to avoid unlock on frame error
-            c_allowedFalseHeaderOverN        : integer;             --! Number of header checked to know wether the lock is lost or not
-            c_requiredTrueHeader             : integer;             --! Number of true header required to go in locked state
-
-            c_bitslip_mindly                 : integer := 1;        --! Number of clock cycle required WHEN asserting the bitslip SIGNAL
-            c_bitslip_waitdly                : integer := 40        --! Number of clock cycle required before being back in a stable state
-        );
-        PORT (
-            -- Clock(s)
-            clk_pcsRx_i                      : in  std_logic;       --! MGT Wordclock
-
-            -- Reset(s)
-            rst_pattsearch_i                 : in  std_logic;       --! Rst the pattern search state machines
-
-            -- Control
-            cmd_bitslipCtrl_o                : out std_logic;       --! Bitslip SIGNAL to shift the parrallel word
-
-            -- Status
-            sta_headerLocked_o               : out std_logic;       --! Status: header is locked
-            sta_headerFlag_o                 : out std_logic;       --! Status: header flag (1 pulse over c_wordRatio)
-            sta_bitSlipEven_o                : out std_logic;       --!  Status: number of bit slips is even
-
-            -- Data
-            dat_word_i                       : in  std_logic_vector(c_headerPattern'length-1 downto 0)  --! Header bits from the MGT word (compared with c_headerPattern)
-        );
-    END COMPONENT;
-
+    signal dat_downLinkWord_fromGb_en           : std_logic := '0';
+    signal sta_headerFlag_s_vec                 : std_logic_vector(9 downto 0);
+    signal sta_headerFlag_s0                    : std_logic;
+    signal TXCLK40_320                          : std_logic;
+    signal RXCLK40_320                          : std_logic;
+    signal rst_uplink_tx320                     : std_logic;
+    signal upLinkScramblerBypass_clk320         : std_logic;
+    signal upLinkInterleaverBypass_clk320       : std_logic;
+    signal fecMode_clk320                       : std_logic;
+    signal txDataRate_clk320                    : std_logic;
 begin
 
-    --MTcomment: doubling bits to compensate oversamplngratio=2 (all modules in
-    --LpGBT_CERN meant for 10g24 rate...see lpgbtemul_top in lpgbt-fpga-kcu105
-    --v1.1.0 tag)
-    dat_downLinkWord_fromMgt_s <=
-                                  dat_downLinkWord_fromMgt_s16(15) & dat_downLinkWord_fromMgt_s16(15) &
+    --RX
+    --MTcomment: doubling bits to compensate oversamplngratio=2 (all modules in LpGBT_CERN meant for 10g24 rate...see lpgbtemul_top in lpgbt-fpga-kcu105 v1.1.0 tag)
+    dat_downLinkWord_fromMgt_s <= dat_downLinkWord_fromMgt_s16(15) & dat_downLinkWord_fromMgt_s16(15) &
                                   dat_downLinkWord_fromMgt_s16(14) & dat_downLinkWord_fromMgt_s16(14) &
                                   dat_downLinkWord_fromMgt_s16(13) & dat_downLinkWord_fromMgt_s16(13) &
                                   dat_downLinkWord_fromMgt_s16(12) & dat_downLinkWord_fromMgt_s16(12) &
@@ -271,84 +147,58 @@ begin
                                   dat_downLinkWord_fromMgt_s16(1) & dat_downLinkWord_fromMgt_s16(1) &
                                   dat_downLinkWord_fromMgt_s16(0) & dat_downLinkWord_fromMgt_s16(0);
 
-    aligned                 <= sta_headeLocked_s;
-    sta_headerFlag_o        <= sta_headerFlag_s0;
-    sta_headerFlag_shift    <= sta_headerFlag_s;
-    --sta_rxgbxRdy_o          <= sta_rxgbxRdy_s;
-    clk_dataFlag_rxGb_s_o   <= clk_dataFlag_rxGb_s;
+    dat_downLinkWord_toPattSrch_s <= dat_downLinkWord_fromMgt_s(24) & dat_downLinkWord_fromMgt_s(25) & dat_downLinkWord_fromMgt_s(26) & dat_downLinkWord_fromMgt_s(27) &
+                                     dat_downLinkWord_fromMgt_s(16) & dat_downLinkWord_fromMgt_s(17) & dat_downLinkWord_fromMgt_s(18) & dat_downLinkWord_fromMgt_s(19) &
+                                     dat_downLinkWord_fromMgt_s(8) & dat_downLinkWord_fromMgt_s(9) & dat_downLinkWord_fromMgt_s(10) & dat_downLinkWord_fromMgt_s(11) &
+                                     dat_downLinkWord_fromMgt_s(3) & dat_downLinkWord_fromMgt_s(2) & dat_downLinkWord_fromMgt_s(1) & dat_downLinkWord_fromMgt_s(0);
 
+    --MT comment : throwing out 3 bits out 4 to ramp down from 10.12 Gbps to 2.56 Gbps
+    dat_downLinkWord_fromMgt_s8 <= dat_downLinkWord_fromMgt_s(3) & dat_downLinkWord_fromMgt_s(7) & dat_downLinkWord_fromMgt_s(11) & dat_downLinkWord_fromMgt_s(15)
+                                   & dat_downLinkWord_fromMgt_s(19) & dat_downLinkWord_fromMgt_s(23) &dat_downLinkWord_fromMgt_s(27) & dat_downLinkWord_fromMgt_s(31);
+
+    aligned                         <= sta_headeLocked_s;
+    sta_headerFlag_o                <= sta_headerFlag_s0;
+    --sta_headerFlag_shift            <= sta_headerFlag_s;
+    --clk_dataFlag_rxGb_s_o           <= clk_dataFlag_rxGb_s;
     downLinkData(15 downto 0)       <= downLinkDataGroup0_s;
     downLinkData(31 downto 16)      <= downLinkDataGroup1_s;
     downLinkDataEC                  <= downLinkDataEc_s;
     downLinkDataIC                  <= downLinkDataIc_s;
-
     rst_pattsearch_s                <= not(sta_mgtRxRdy_s);
-    --rst_datapath_s                  <= not(sta_headeLocked_s);
-    --rst_uplinkGb_s                  <= rst_uplink_i or not(sta_mgtTxRdy_s);-- or not(sta_headeLocked_s);
-    --uplinkRdy_o                     <= sta_txGbRdy_s;
 
-    -- RL: updated mgt_framealigner with version 2.0
-    -- Pattern aligner
     mgt_framealigner_inst: entity work.mgt_framealigner
-        generic map
-    (
-            c_wordRatio                      => 8,
-            c_headerPattern                  => x"F00F",
-            c_wordSize                       => 32,
-            c_allowedFalseHeader             => 32,
-            c_allowedFalseHeaderOverN        => 40,
-            c_requiredTrueHeader             => 30,
-            -- c_resetOnEven                    => 0,
-            c_bitslip_mindly                 => 1, --RL: to match old implementation
-            c_bitslip_waitdly                => 40 --RL: to match old implementation
+        generic map(
+            c_wordRatio                 => 8,
+            c_headerPattern             => x"F00F",
+            c_wordSize                  => 32,
+            c_allowedFalseHeader        => 32,
+            c_allowedFalseHeaderOverN   => 40,
+            c_requiredTrueHeader        => 30,
+            c_bitslip_mindly            => 1,
+            c_bitslip_waitdly           => 40
         )
         port map (
-            -- Clock(s)
-            clk_pcsRx_i                      => RXCLK320,
-            --clk_freeRunningClk_i             => '0',                  -- Not used: rst on even is not enabled
-
-            -- Reset(s)
-            rst_pattsearch_i                 => rst_pattsearch_s,
-            --rst_mgtctrler_i                  => '0',                  -- Not used: rst on even is not enabled
-            --rst_rstoneven_o                  => open,                 -- Not used: rst on even is not enabled
-
-            -- Control
-            cmd_bitslipCtrl_o                => ctr_clkSlip_s,
-            --cmd_rstonevenoroddsel_i          => '0',                  -- Not used: rst on even is not enabled
-
-            -- Status
-            sta_headerLocked_o               => sta_headeLocked_s,
-            sta_headerFlag_o                 => sta_headerFlag_s0,
-            sta_bitSlipEven_o => open,
-            -- Data
-            dat_word_i                       => dat_downLinkWord_toPattSrch_s
+            clk_pcsRx_i                 => RXCLK320,
+            rst_pattsearch_i            => rst_pattsearch_s,
+            cmd_bitslipCtrl_o           => ctr_clkSlip_s,
+            sta_headerLocked_o          => sta_headeLocked_s,
+            sta_headerFlag_o            => sta_headerFlag_s0,
+            sta_bitSlipEven_o           => open,
+            dat_word_i                  => dat_downLinkWord_toPattSrch_s
         );
 
-    dat_downLinkWord_toPattSrch_s <=
-                                     dat_downLinkWord_fromMgt_s(24) & dat_downLinkWord_fromMgt_s(25) & dat_downLinkWord_fromMgt_s(26) & dat_downLinkWord_fromMgt_s(27) &
-                                     dat_downLinkWord_fromMgt_s(16) & dat_downLinkWord_fromMgt_s(17) & dat_downLinkWord_fromMgt_s(18) & dat_downLinkWord_fromMgt_s(19) &
-                                     dat_downLinkWord_fromMgt_s(8) & dat_downLinkWord_fromMgt_s(9) & dat_downLinkWord_fromMgt_s(10) & dat_downLinkWord_fromMgt_s(11) &
-                                     dat_downLinkWord_fromMgt_s(3) & dat_downLinkWord_fromMgt_s(2) & dat_downLinkWord_fromMgt_s(1) & dat_downLinkWord_fromMgt_s(0);
-
-
-    --MT comment : throwing out 3 bits out 4 to ramp down from 10.12 Gbps to
-    --2.56 Gbps
-    dat_downLinkWord_fromMgt_s8 <=
-                                   dat_downLinkWord_fromMgt_s(3) & dat_downLinkWord_fromMgt_s(7) & dat_downLinkWord_fromMgt_s(11) & dat_downLinkWord_fromMgt_s(15)
-                                   & dat_downLinkWord_fromMgt_s(19) & dat_downLinkWord_fromMgt_s(23) &dat_downLinkWord_fromMgt_s(27) & dat_downLinkWord_fromMgt_s(31);
-
     xpm_cdc_single_inst_RX : xpm_cdc_single
         generic map (
-            DEST_SYNC_FF => 8, --equivalent to 1 40 MHz clock cycle at 320 MHz
+            DEST_SYNC_FF => 8,
             INIT_SYNC_FF => 0,
             SIM_ASSERT_CHK => 0,
-            SRC_INPUT_REG => 0 --Cannot sync a clock to itself
+            SRC_INPUT_REG => 0
         )
         port map (
             dest_out => RXCLK40_320,
-            dest_clk => RXCLK320, --TXCLK320
+            dest_clk => RXCLK320,
             src_clk => '0',
-            src_in => RXCLK40
+            src_in => clk40_in
         );
 
     process(RXCLK320)
@@ -375,8 +225,6 @@ begin
             end case;
             RXCLK40_r <= RXCLK40_320;
             dat_downLinkWord_fromMgt_s64 <= dat_downLinkWord_fromMgt_s64(55 downto 0) & dat_downLinkWord_fromMgt_s8;
-            --MTcomment sta_headerFlag_s=1 1 pulse every 8 (=c_wordration in mgtframealigner) clks.
-            --This is because
             if sta_headerFlag_s='1' then
                 dat_downLinkWord_fromGb_s_buf <= dat_downLinkWord_fromMgt_s64;
             end if;
@@ -398,8 +246,12 @@ begin
             end if;
             if sta_headerFlag_s='1'  and  sel='0' then
                 dat_downLinkWord_fromGb_s <=  dat_downLinkWord_fromMgt_s64;
+                dat_downLinkWord_fromGb_en <= '1';
             elsif sta_headerFlag_s_r4='1'  and  sel='1' then
                 dat_downLinkWord_fromGb_s <= dat_downLinkWord_fromGb_s_buf;
+                dat_downLinkWord_fromGb_en <= '1';
+            else
+                dat_downLinkWord_fromGb_en <= '0';
             end if;
             sta_headerFlag_s_r1       <= sta_headerFlag_s;
             sta_headerFlag_s_r2       <= sta_headerFlag_s_r1;
@@ -409,38 +261,60 @@ begin
         end if;
     end process;
 
-    --------------------------------------------------------------------------------------
-    --------------------------------------------------------------------------------------
-    --------------------------------------------------------------------------------------
-    ------------------------------------------TX------------------------------------------
-    --------------------------------------------------------------------------------------
-    --------------------------------------------------------------------------------------
-    --------------------------------------------------------------------------------------
+    rxdatapath_inst : entity work.downLinkRxDataPath
+        port map (
+            clk                   => RXCLK320,
+            downLinkFrame         => dat_downLinkWord_fromGb_s(63 downto 0),
+            dataStrobe            => open,
+            dataOut(15 downto  0) => downLinkDataGroup0_s,
+            dataOut(31 downto 16) => downLinkDataGroup1_s,
+            dataEC                => downLinkDataEc_s,
+            dataIC                => downLinkDataIc_s,
+            header                => open,
+            dataEnable            => dat_downLinkWord_fromGb_en,
+            bypassDeinterleaver   => downLinkBypassDeinterleaver,
+            bypassFECDecoder      => downLinkBypassFECDecoder,
+            bypassDescrambler     => downLinkBypassDescsrambler,
+            fecCorrectionCount    => fecCorrectionCount
+        );
+
 
-    -- Comment: Bits are inverted to transmit the MSB first on the MGT.
     frameInverter: for i in 255 downto 0 generate
-        dat_upLinkWord_toGb_pipeline_s_inv(i)             <= dat_upLinkWord_toGb_pipeline_s(255-i);
+        dat_upLinkWord_toGb_pipeline_s_inv(i) <= dat_upLinkWord_toGb_pipeline_s(255-i);
     end generate;
 
     xpm_cdc_single_inst_TX : xpm_cdc_single
         generic map (
-            DEST_SYNC_FF => 8, --equivalent to 1 40 MHz clock cycle at 320 MHz
+            DEST_SYNC_FF => 8,
             INIT_SYNC_FF => 0,
             SIM_ASSERT_CHK => 0,
-            SRC_INPUT_REG => 0 --Cannot sync a clock to itself
+            SRC_INPUT_REG => 0
         )
         port map (
             dest_out => TXCLK40_320,
-            dest_clk => TXCLK320, --TXCLK320
+            dest_clk => TXCLK320,
             src_clk => '0',
-            src_in => TXCLK40
+            src_in => clk40_in
+        );
+
+    sync_rst_uplink_tx320 : xpm_cdc_sync_rst
+        generic map (
+            DEST_SYNC_FF => 2,
+            INIT => 1,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0
+        )
+        port map (
+            src_rst => rst_uplink_i,
+            dest_clk => TXCLK320,
+            dest_rst => rst_uplink_tx320
         );
 
     process(TXCLK320)
     begin
         if TXCLK320'event and TXCLK320='1' then
             TXCLK40_r <= TXCLK40_320;
-            if rst_uplink_i= '1' THEN
+            if rst_uplink_tx320= '1' THEN
                 if TXCLK40_320 ='0' and TXCLK40_r='1' then
                     txcnt <="000";
                 else
@@ -452,15 +326,10 @@ begin
 
             if txcnt="010" then
                 dat_upLinkWord_toGb_pipeline_s_r <=dat_upLinkWord_toGb_pipeline_s_inv;
-                --MT added: needed by FELIG to latch tx payload to generated data. Need to
-                --be synchronized with emulator logic
                 tx_flag_out <= '1';
-            --
             else
                 dat_upLinkWord_toGb_pipeline_s_r <= dat_upLinkWord_toGb_pipeline_s_r;
-                --MT added: needed by FELIG
                 tx_flag_out <= '0';
-            --
             end if;
             case txcnt is
                 when "011" =>
@@ -494,28 +363,63 @@ begin
     --upLinkDataIC_s      <= upLinkDataIC;
     --upLinkDataEC_s      <= upLinkDataEC;
 
-    -- RL replaced LpGBT_Model_dataPath with downLinkRxDataPath and upLinkTxDataPath, as in mgt_framealigner
-    rxdatapath_inst : downLinkRxDataPath
-        port map (
-            clk                   => RXCLK40, --RXCLK320,
-            downLinkFrame         => dat_downLinkWord_fromGb_s(63 downto 0),
-            dataStrobe            => open,
-            dataOut(15 downto  0) => downLinkDataGroup0_s,
-            dataOut(31 downto 16) => downLinkDataGroup1_s,
-            dataEC                => downLinkDataEc_s,
-            dataIC                => downLinkDataIc_s,
-            header                => open,
-            dataEnable            => '1',--RX_CLKEn_s,
-            bypassDeinterleaver   => downLinkBypassDeinterleaver,--'0',
-            bypassFECDecoder      => downLinkBypassFECDecoder,--'0',
-            bypassDescrambler     => downLinkBypassDescsrambler,--'0',
-            fecCorrectionCount    => open
+    sync_upLinkScramblerBypass : xpm_cdc_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0
+        )
+        port map(
+            src_clk => '0',
+            src_in => upLinkScramblerBypass,
+            dest_clk => TXCLK320,
+            dest_out => upLinkScramblerBypass_clk320
         );
 
-    txdatapath_inst : upLinkTxDataPath
+    sync_upLinkInterleaverBypass : xpm_cdc_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0
+        )
+        port map(
+            src_clk => '0',
+            src_in => upLinkInterleaverBypass,
+            dest_clk => TXCLK320,
+            dest_out => upLinkInterleaverBypass_clk320
+        );
+
+    sync_fecMode : xpm_cdc_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0
+        )
+        port map(
+            src_clk => '0',
+            src_in => fecMode,
+            dest_clk => TXCLK320,
+            dest_out => fecMode_clk320
+        );
+
+    sync_txDataRate : xpm_cdc_single generic map(
+            DEST_SYNC_FF => 2,
+            INIT_SYNC_FF => 0,
+            SIM_ASSERT_CHK => 0,
+            SRC_INPUT_REG => 0
+        )
+        port map(
+            src_clk => '0',
+            src_in => txDataRate,
+            dest_clk => TXCLK320,
+            dest_out => txDataRate_clk320
+        );
+
+
+    txdatapath_inst : entity work.upLinkTxDataPath
         port map (
-            clk                   => TXCLK40,--TXCLK320
-            dataEnable            => '1',--uplinkClkEn_i,
+            clk                   => TXCLK320,
+            dataEnable            => upLinkDataREADY,
             txDataGroup0          => upLinkData0_s,
             txDataGroup1          => upLinkData1_s,
             txDataGroup2          => upLinkData2_s,
@@ -523,23 +427,23 @@ begin
             txDataGroup4          => upLinkData4_s,
             txDataGroup5          => upLinkData5_s,
             txDataGroup6          => upLinkData6_s,
-            txIC                  => upLinkDataIC,--upLinkDataIC_s,
-            txEC                  => upLinkDataEC,--_s,
-            txDummyFec5           => (others =>'0'),--"001100",
-            txDummyFec12          => (others =>'0'),--"1001110011",
-            scramblerBypass       => upLinkScramblerBypass,--'0',
-            interleaverBypass     => upLinkInterleaverBypass,--'0',
-            fecMode               => fecMode,
-            txDataRate            => txDataRate,
+            txIC                  => upLinkDataIC,
+            txEC                  => upLinkDataEC,
+            txDummyFec5           => (others =>'0'),
+            txDummyFec12          => (others =>'0'),
+            scramblerBypass       => upLinkScramblerBypass_clk320,
+            interleaverBypass     => upLinkInterleaverBypass_clk320,
+            fecMode               => fecMode_clk320,
+            txDataRate            => txDataRate_clk320,
             fecDisable            => '0',
-            scramblerReset        => rst_uplink_i,--rst_datapath_s, rst_uplinkGb_s,
+            scramblerReset        => rst_uplink_tx320,
             upLinkFrame           => dat_upLinkWord_fromLpGBT_s
         );
 
     -- Uplink oversampler
     oversampler_gen: for i in 0 to 127 generate
         oversampler_ph_gen: for j in 0 to 1 generate
-            dat_upLinkWord_toGb_pipeline_s((i*2)+j) <=  dat_upLinkWord_fromLpGBT_s(i) when txDataRate = '0' else
+            dat_upLinkWord_toGb_pipeline_s((i*2)+j) <= dat_upLinkWord_fromLpGBT_s(i) when txDataRate = '0' else
                                                        dat_upLinkWord_fromLpGBT_s((i*2)+j);
         end generate;
     end generate;
diff --git a/sources/LpGBT/LpGBT_FELIX/Regs_RW.vhd b/sources/LpGBT/LpGBT_FELIX/Regs_RW.vhd
index b32de27f85847a7f041317b4342b60c5312c6ce9..e8a4ee46285ee3a1338e6c2fc429b67234728847 100644
--- a/sources/LpGBT/LpGBT_FELIX/Regs_RW.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/Regs_RW.vhd
@@ -155,7 +155,7 @@ begin
     register_map_link_monitor.GBT_ERROR(GBT_NUM-1 downto 0) <= MON_FEC_ERROR;
 
     g_FEC_channels: for i in 0 to GBT_NUM-1 generate
-        g_limit24: if i < 23 generate
+        g_limit24: if i < 24 generate
             register_map_link_monitor.GT_FEC_ERR_CNT(i) <= MON_FEC_ERR_CNT(i);
             register_map_link_monitor.GT_AUTO_RX_RESET_CNT(i).VALUE <= MON_AUTO_RX_RESET_CNT(i);
         end generate;
diff --git a/sources/decoding/decoding.vhd b/sources/decoding/decoding.vhd
index 4af7eb63cbaf0a1040160a063274ad72cb6485de..913f4becc00e6661e048165fb6fca7b9a4a3c639 100644
--- a/sources/decoding/decoding.vhd
+++ b/sources/decoding/decoding.vhd
@@ -225,8 +225,7 @@ begin
 
     g_gbtmode: if FIRMWARE_MODE = FIRMWARE_MODE_GBT or
                   FIRMWARE_MODE = FIRMWARE_MODE_LTDB or
-                  FIRMWARE_MODE = FIRMWARE_MODE_FEI4 or
-                  FIRMWARE_MODE = FIRMWARE_MODE_FELIG_GBT
+                  FIRMWARE_MODE = FIRMWARE_MODE_FEI4
                   generate
         signal AlignmentPulseAlign: std_logic;
         signal AlignmentPulseDeAlign: std_logic;
@@ -1073,8 +1072,7 @@ begin
             );
     end generate;
 
-    g_lpgbt8b10b: if FIRMWARE_MODE = FIRMWARE_MODE_LPGBT or
-                     FIRMWARE_MODE = FIRMWARE_MODE_FELIG_LPGBT generate
+    g_lpgbt8b10b: if FIRMWARE_MODE = FIRMWARE_MODE_LPGBT generate
         signal AlignmentPulseAlign: std_logic;
         signal AlignmentPulseDeAlign: std_logic;
     begin
diff --git a/sources/ip_cores/kintexUltrascale/KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH.xci b/sources/ip_cores/kintexUltrascale/KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH.xci
index ee76389411bbaf3580347e4a348337a870d126dd..56f3669c48defec24c421d1167b51c8109a7ae02 100644
--- a/sources/ip_cores/kintexUltrascale/KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH.xci
+++ b/sources/ip_cores/kintexUltrascale/KCU_TXQPLLREFCLK10g24_RXCPLLREFCLK05g12_FELIG4CH.xci
@@ -70,9 +70,9 @@
         "RX_COMMA_P_VAL": [ { "value": "0101111100", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "RX_COMMA_M_VAL": [ { "value": "1010000011", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "RX_COMMA_MASK": [ { "value": "0000000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
-        "RX_COMMA_ALIGN_WORD": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
-        "RX_COMMA_SHOW_REALIGN_ENABLE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "RX_SLIDE_MODE": [ { "value": "OFF", "resolve_type": "user", "usage": "all" } ],
+        "RX_COMMA_ALIGN_WORD": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "RX_COMMA_SHOW_REALIGN_ENABLE": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RX_SLIDE_MODE": [ { "value": "PMA", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "RX_CB_NUM_SEQ": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "RX_CB_LEN_SEQ": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "RX_CB_MAX_SKEW": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
@@ -901,4 +901,4 @@
       }
     }
   }
-}
\ No newline at end of file
+}
diff --git a/sources/packages/FELIX_package.vhd b/sources/packages/FELIX_package.vhd
index 593af752ff5b9871341bf2517e504eab693a25eb..279974bd7d0a5d8eac3c7c7ae607c095a4fa744d 100644
--- a/sources/packages/FELIX_package.vhd
+++ b/sources/packages/FELIX_package.vhd
@@ -107,7 +107,7 @@ package FELIX_package is
       42,  --FELIX mrod
       30,   --LPGBT mode: 28 EPaths + IC + EC
       1,   -- Interlaken mode
-      30,  -- FELIG LPGBT
+      1,  -- FELIG LPGBT
       30,  -- HGTD luminosity (14 lpGBT e-links splitted into aggregated and per-event lumi) + IC + EC
       30,   --BCMPRIME
       1,   --FELIG pixel
@@ -127,7 +127,7 @@ package FELIX_package is
       (8,8,8,8,8,2,0,0), -- FELIX mrod
       (4,4,4,4,2,0,0,0), -- LPGBT mode  16 EPATH = 4x4 + IC + EC
       (1,0,0,0,0,0,0,0), -- Interlaken mode
-      (4,4,4,4,2,0,0,0),  -- FELIG LPGBT
+      (1,0,0,0,0,0,0,0),  -- FELIG LPGBT
       (2,0,0,0,0,0,0,0),  -- HGTD luminosity readout (only IC/EC)
       (4,4,4,4,2,0,0,0), -- ITK BCM: 16 EPATH = 4x4 + IC + EC.
       (1,0,0,0,0,0,0,0),   --FELIG pixel
@@ -449,15 +449,15 @@ package body FELIX_package is
             when FIRMWARE_MODE_FEI4        => return 160;
             when FIRMWARE_MODE_PIXEL       => return 240;
             when FIRMWARE_MODE_STRIP       => return 240;
-            when FIRMWARE_MODE_FELIG_GBT   => return 160;
+            when FIRMWARE_MODE_FELIG_GBT   => return 0;
             when FIRMWARE_MODE_FMEMU       => return 0;
             when FIRMWARE_MODE_MROD        => return 160;
             when FIRMWARE_MODE_LPGBT       => return 240;
             when FIRMWARE_MODE_INTERLAKEN  => return 250; --Using AXI-Stream 64b for Interlaken, this frequency is used for AUX E-Links.
-            when FIRMWARE_MODE_FELIG_LPGBT => return 160;
+            when FIRMWARE_MODE_FELIG_LPGBT => return 0;
             when FIRMWARE_MODE_HGTD_LUMI   => return 160; -- reducing clock from 240 to 160 for better timing in CRToHost, should be changed back with better timing
             when FIRMWARE_MODE_BCM_PRIME   => return 240;
-            when FIRMWARE_MODE_FELIG_PIXEL => return 160;
+            when FIRMWARE_MODE_FELIG_PIXEL => return 0;
             when FIRMWARE_MODE_FELIG_STRIP => return 160;
             when FIRMWARE_MODE_WUPPER      => return 250;