From ca4959b06a46226af8a5d4a7593c7638e8f43aa2 Mon Sep 17 00:00:00 2001 From: Frans Schreuder <f.schreuder@nikhef.nl> Date: Wed, 2 Feb 2022 08:54:22 +0100 Subject: [PATCH] Fixed crresetmanager instantiation in felig (Thanks Ricardo for the fix) --- .../data_generator/elink_data_emulator.vhd | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/sources/feligHG710/data_generator/elink_data_emulator.vhd b/sources/feligHG710/data_generator/elink_data_emulator.vhd index ce583c9ad..4250272ea 100644 --- a/sources/feligHG710/data_generator/elink_data_emulator.vhd +++ b/sources/feligHG710/data_generator/elink_data_emulator.vhd @@ -426,19 +426,19 @@ begin rst0: entity work.CRresetManager port map ( - clk40 => clk40, + clk40 => clk240, clk80 => '0', clk160 => '0', - clk240 => clk240, + clk240 => '0', rst => emu_control.reset, - cr_rst_40 => open, + cr_rst_40 => elink_tx_rst, cr_rst_80 => open, cr_rst_160 => open, - cr_rst_240 => elink_tx_rst, - cr_fifo_flush_40 => open, + cr_rst_240 => open, + cr_fifo_flush_40 => fifo_flush, cr_fifo_flush_80 => open, cr_fifo_flush_160 => open, - cr_fifo_flush_240 => fifo_flush + cr_fifo_flush_240 => open ); end Behavioral; -- GitLab