diff --git a/simulation/ItkStrip/tb_lcb_axi_encoder.vhd b/simulation/ItkStrip/tb_lcb_axi_encoder.vhd
index c030b21168a166cc62b945c6003d8afe4af6f8f0..d07623cdfd567fd65ce23e5b1df92402857f286d 100644
--- a/simulation/ItkStrip/tb_lcb_axi_encoder.vhd
+++ b/simulation/ItkStrip/tb_lcb_axi_encoder.vhd
@@ -121,6 +121,7 @@ architecture RTL of tb_lcb_axi_encoder is
-- TTC signals
signal bcr : std_logic := '0';
+ signal enable_bcr : std_logic := '0';
signal bcr_expected : std_logic := '0';
signal l0a : std_logic := '0';
signal l0id : std_logic_vector(6 downto 0) := (others => '0');
@@ -264,6 +265,7 @@ begin
p_test : process is
variable frame_rnd : std_logic_vector(11 downto 0); -- L0 frame
+ variable frame_sent : std_logic_vector(11 downto 0); -- L0 frame
variable next_frame : t_decoder_record;
variable next_frame_timeout : boolean := false;
variable bypass_data : t_bypass_data_record;
@@ -321,8 +323,9 @@ begin
--bcr <= '0';
--l0a <= '0';
- l0id <= tag when (not randomize_tag) else random(tag'length);
+ l0id <= tag;-- when (not randomize_tag) else random(tag'length);
l0a_trig_i <= mask; --"000";
+ frame_rnd(11) := bcr_expected;
wait until rising_edge(clk);
l0id <= (others => '0');
l0a_trig_i <= "0000";
@@ -336,6 +339,7 @@ begin
while frame_rnd(11 downto 7) = "00000" loop
frame_rnd := random(frame_rnd'length);
end loop;
+
send_L0A(frame_rnd(10 downto 7), frame_rnd(6 downto 0)); --frame_rnd(11),
end;
@@ -785,24 +789,25 @@ begin
begin
log(ID_SEQUENCER, "Issuing BCR to start gating pulse generation");
wait until rising_edge(bcr);
- send_L0A("0000", "0000000"); --'1',
+ wait until rising_edge(clk);
+ --send_L0A("0000", "0000000"); --'1',
dequeue_next_frame;
check_value(next_frame.decoded, "100000000000", ERROR, "BCR frame received");
register_command_open := false;
commands_received := 0;
dequeue_next_frame(expiration_time => (bc_stop + 100) * C_CLK_PERIOD);
+
while not next_frame_timeout loop
interruption_roll := random(1,10);
if interruption_roll = 1 then
-- interrupt with L0A frame
- wait until rising_edge(bcr);
- wait_num_rising_edge(clk, 3);
send_L0A( mask => "1011", tag => "0100111"); --bcr_i => '0',
elsif interruption_roll = 2 then
-- interrupt with bypass frame
axistream_transmit(AXISTREAM_VVCT, command_channel,--@suppress
t_slv_array'(x"33", x"33"), "Interrupting with bypass frame 0x3333");
end if;
+
if next_frame.k2 then
if next_frame.decoded(4) = '1' then
log(ID_SEQUENCER_SUB, "Received register command START frame");
@@ -836,8 +841,7 @@ begin
frame_queue.set_scope(C_TB_SCOPE_DEFAULT);
start_clock(CLOCK_GENERATOR_VVCT, 1, "Start clock generator (BC clock)");--@suppress
start_clock(CLOCK_GENERATOR_VVCT, 5, "Start clock generator (AXI clock)");--@suppress
- --temp
- --disable_log_msg(ALL_MESSAGES);
+ disable_log_msg(ALL_MESSAGES);
enable_log_msg(ID_LOG_HDR);
enable_log_msg(ID_SEQUENCER);
enable_log_msg(ID_SEQUENCER_SUB);
@@ -916,6 +920,7 @@ begin
-- log(ID_SEQUENCER, "Setting BCR delay to 0");
-- set_register(t_register_name'pos(TTC_BCR_DELAY), x"0000");
+ enable_bcr <= '1';
log(ID_LOG_HDR, "Verifying that overall L0A frame delay can be adjusted");
set_register(t_register_name'pos(TTC_L0A_ENABLE), x"0001");
@@ -944,6 +949,7 @@ begin
-------- verify that fast commands work
+ enable_bcr <= '0';
log(ID_LOG_HDR, "Verifying that elink commands work (using command decoder)");
set_encoding(true);
log(ID_SEQUENCER, "Sending and checking fast commands");
@@ -1003,6 +1009,7 @@ begin
reset_abc_hcc_mask;
-------- verify that TTC L0A signals are ignored when disabled
+ enable_bcr <= '1';
log(ID_LOG_HDR, "Verifying response to TTC L0A signals");
log(ID_SEQUENCER, "Verifying that TTC L0A frames can be disabled");
set_register(t_register_name'pos(TTC_L0A_ENABLE), x"0000");
@@ -1024,19 +1031,24 @@ begin
check_value(next_frame.decoded, frame_rnd, ERROR, "Received expected L0A frame");
end loop;
+ enable_bcr <= '0';
+
log(ID_LOG_HDR, "Enabling L0A frames and verifying them (sequence)");
ttc_l0a_data := ttc_l0a.parse_file("../samples/ttc_l0a_command_inputs.txt",
"../samples/ttc_l0a_command_outputs.txt"
);
for i in 0 to ttc_l0a_data.count - 1 loop
send_L0A( ttc_l0a_data.inputs(i).mask, ttc_l0a_data.inputs(i).tag); --ttc_l0a_data.inputs(i).bcr,
- end loop;
- for i in 0 to ttc_l0a_data.count - 1 loop
+ --end loop;
+ --for i in 0 to ttc_l0a_data.count - 1 loop
dequeue_next_frame;
- check_value(next_frame.encoded, ttc_l0a_data.outputs(i), ERROR, "Received expected L0A frame");
+ --check_value(next_frame.encoded, ttc_l0a_data.outputs(i), ERROR, "Received expected L0A frame");
+ frame_rnd := frame_rnd(11) & next_frame.decoded(10 downto 0);
+ frame_sent := frame_rnd(11) & ttc_l0a_data.inputs(i).mask & ttc_l0a_data.inputs(i).tag;
+ check_value(frame_rnd, frame_sent, ERROR, "Received expected L0A frame");
end loop;
-
+ enable_bcr <= '1';
-------- verify bypass frames come through
log(ID_LOG_HDR, "Verifying that bypass frames are correctly transmitted");
set_encoding(false);
@@ -1077,7 +1089,7 @@ begin
verify_elink_command_responses(trickle_test_data_1);
-
+ enable_bcr <= '0';
-------- verify that trickle configuration memory can store multiple sequences and switch between them
log(ID_LOG_HDR, "Verifying that multiple trickle configuration samples can be stored in memory");
trickle_test_data_2 := elink_parser.parse_file("../samples/trickle_config_inputs_2.txt",
@@ -1222,6 +1234,8 @@ begin
-- low-priority frame gating
----- bypass frames respect gating signals
+ enable_bcr <= '1';
+
log(ID_LOG_HDR, "Verifying that bypass frames respect gating signal");
set_encoding(false);
gating_test_frames := 40;
@@ -1292,6 +1306,7 @@ begin
wait until rising_edge(clk);
+ --frame_queue.reset(VOID);
----- gating guard interval is respected = only complete register read/write command are sent
log(ID_LOG_HDR, "Register guard interval test: register read/write commands are not interrupted"
@@ -1323,13 +1338,14 @@ begin
set_register(t_register_name'pos(GATING_TTC_ENABLE), x"0001", timeout_clk_periods => 5000);
set_register(t_register_name'pos(TRICKLE_TRIGGER_RUN), x"0001", timeout_clk_periods => 5000);
wait_num_rising_edge(clk, 50);
- verify_register_frame_completion;
+ verify_register_frame_completion; --needs BCR
--wait_num_rising_edge(clk, guard_window_size + 10);
set_register(t_register_name'pos(GATING_TTC_ENABLE), x"0000", timeout_clk_periods => 5000);
set_register(t_register_name'pos(TRICKLE_TRIGGER_RUN), x"0000", timeout_clk_periods => 5000);
wait_num_rising_edge(clk, 30);
await_value(frame.idle, '1', 0 ns, 5000 * C_CLK_PERIOD, "Waiting for the trickle configuration to flush out"); --@suppress
frame_queue.flush(void);
+ --frame_queue.reset(VOID);
wait for 1500 ns;
wait until rising_edge(clk);
end loop;
@@ -1361,7 +1377,7 @@ begin
bcid:=bcid+1;
end if;
- if(bcid=0) then
+ if(bcid=0 and enable_bcr = '1') then
bcr <= '1';
end if;