diff --git a/simulation/FELIX_Top/felix_top_tb.vhd b/simulation/FELIX_Top/felix_top_tb.vhd index 905ab31d88531a572239200a61bea73fa732bd13..ac7ee732fd3bf50d06c223eccfe6957830da87a5 100644 --- a/simulation/FELIX_Top/felix_top_tb.vhd +++ b/simulation/FELIX_Top/felix_top_tb.vhd @@ -71,84 +71,84 @@ architecture structure of felix_top_tb is constant BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE"; constant GBT_NUM : integer := 24; -- number of GBT channels - - signal BUSY_OUT : std_logic; - signal CLK40_FPGA2LMK_N : std_logic; - signal CLK40_FPGA2LMK_P : std_logic; - signal OPTO_LOS : std_logic_vector(3 downto 0); - signal I2C_SMB : std_logic; - signal I2C_SMBUS_CFG_nEN : std_logic; - signal I2C_nRESET_PCIe : std_logic; - signal LMK_CLK : std_logic; - signal LMK_DATA : std_logic; - signal LMK_GOE : std_logic; - signal LMK_LD : std_logic; - signal LMK_LE : std_logic; - signal LMK_SYNCn : std_logic; - signal LOL_ADN : std_logic; - signal LOS_ADN : std_logic; - signal MGMT_PORT_EN : std_logic; - signal NT_PORTSEL : std_logic_vector(2 downto 0); - signal PCIE_PERSTn1 : std_logic; - signal PCIE_PERSTn2 : std_logic; - signal PEX_PERSTn : std_logic; - signal PEX_SCL : std_logic; - signal PEX_SDA : std_logic; - signal PORT_GOOD : std_logic_vector(7 downto 0); - signal Perstn1_open : std_logic; - signal Perstn2_open : std_logic; - signal SCL : std_logic; - signal SDA : std_logic; - signal SHPC_INT : std_logic; - signal SI5345_A : std_logic_vector(1 downto 0); - signal SI5345_INSEL : std_logic_vector(1 downto 0); - signal SI5345_OE : std_logic; - signal SI5345_RSTN : std_logic; - signal SI5345_SEL : std_logic; - signal SI5345_nLOL : std_logic; - signal STN0_PORTCFG : std_logic_vector(1 downto 0); - signal STN1_PORTCFG : std_logic_vector(1 downto 0); - signal SmaOut_x3 : std_logic; - signal SmaOut_x4 : std_logic; - signal SmaOut_x5 : std_logic; - signal SmaOut_x6 : std_logic; - signal TACH : std_logic; - signal TESTMODE : std_logic_vector(2 downto 0); - signal UPSTREAM_PORTSEL : std_logic_vector(2 downto 0); - signal clk_adn_160_out_n : std_logic; - signal clk_adn_160_out_p : std_logic; - signal clk40_ttc_ref_out_n : std_logic; -- Towards Si5345 CLKIN - signal clk40_ttc_ref_out_p : std_logic; -- Towards Si5345 CLKIN - signal clk_ttcfx_ref1_in_n : std_logic; - signal clk_ttcfx_ref1_in_p : std_logic; - signal clk_ttcfx_ref2_in_n : std_logic; - signal clk_ttcfx_ref2_in_p : std_logic; - signal i2cmux_rst : std_logic; - signal leds : std_logic_vector(7 downto 0); - signal flash_SEL : std_logic; - signal flash_a : std_logic_vector(24 downto 0); - signal flash_a_msb : std_logic_vector(1 downto 0); - signal flash_adv : std_logic; - signal flash_cclk : std_logic; - signal flash_ce : std_logic; - signal flash_d : std_logic_vector(15 downto 0); - signal flash_re : std_logic; - signal flash_we : std_logic; - signal si5324_resetn : std_logic; - signal pcie_txn : std_logic_vector((1*8)-1 downto 0); - signal pcie_txp : std_logic_vector((1*8)-1 downto 0); --! PCIe link lanes - signal uC_reset_N : std_logic; - - - signal pcie_rxn : std_logic_vector((1*8)-1 downto 0); - signal pcie_rxp : std_logic_vector((1*8)-1 downto 0); - signal opto_inhibit : std_logic_vector(4-1 downto 0); + --@suppress + signal BUSY_OUT : std_logic; --@suppress + signal CLK40_FPGA2LMK_N : std_logic; --@suppress + signal CLK40_FPGA2LMK_P : std_logic; --@suppress + signal OPTO_LOS : std_logic_vector(3 downto 0); --@suppress + signal I2C_SMB : std_logic; --@suppress + signal I2C_SMBUS_CFG_nEN : std_logic; --@suppress + signal I2C_nRESET_PCIe : std_logic; --@suppress + signal LMK_CLK : std_logic; --@suppress + signal LMK_DATA : std_logic; --@suppress + signal LMK_GOE : std_logic; --@suppress + signal LMK_LD : std_logic; --@suppress + signal LMK_LE : std_logic; --@suppress + signal LMK_SYNCn : std_logic; --@suppress + signal LOL_ADN : std_logic; --@suppress + signal LOS_ADN : std_logic; --@suppress + signal MGMT_PORT_EN : std_logic; --@suppress + signal NT_PORTSEL : std_logic_vector(2 downto 0); --@suppress + signal PCIE_PERSTn1 : std_logic; --@suppress + signal PCIE_PERSTn2 : std_logic; --@suppress + signal PEX_PERSTn : std_logic; --@suppress + signal PEX_SCL : std_logic; --@suppress + signal PEX_SDA : std_logic; --@suppress + signal PORT_GOOD : std_logic_vector(7 downto 0); --@suppress + signal Perstn1_open : std_logic; --@suppress + signal Perstn2_open : std_logic; --@suppress + signal SCL : std_logic; --@suppress + signal SDA : std_logic; --@suppress + signal SHPC_INT : std_logic; --@suppress + signal SI5345_A : std_logic_vector(1 downto 0); --@suppress + signal SI5345_INSEL : std_logic_vector(1 downto 0); --@suppress + signal SI5345_OE : std_logic; --@suppress + signal SI5345_RSTN : std_logic; --@suppress + signal SI5345_SEL : std_logic; --@suppress + signal SI5345_nLOL : std_logic; --@suppress + signal STN0_PORTCFG : std_logic_vector(1 downto 0); --@suppress + signal STN1_PORTCFG : std_logic_vector(1 downto 0); --@suppress + signal SmaOut_x3 : std_logic; --@suppress + signal SmaOut_x4 : std_logic; --@suppress + signal SmaOut_x5 : std_logic; --@suppress + signal SmaOut_x6 : std_logic; --@suppress + signal TACH : std_logic; --@suppress + signal TESTMODE : std_logic_vector(2 downto 0); --@suppress + signal UPSTREAM_PORTSEL : std_logic_vector(2 downto 0); --@suppress + signal clk_adn_160_out_n : std_logic; --@suppress + signal clk_adn_160_out_p : std_logic; --@suppress + signal clk40_ttc_ref_out_n : std_logic; -- Towards Si5345 CLKIN --@suppress + signal clk40_ttc_ref_out_p : std_logic; -- Towards Si5345 CLKIN --@suppress + signal clk_ttcfx_ref1_in_n : std_logic; --@suppress + signal clk_ttcfx_ref1_in_p : std_logic; --@suppress + signal clk_ttcfx_ref2_in_n : std_logic; --@suppress + signal clk_ttcfx_ref2_in_p : std_logic; --@suppress + signal i2cmux_rst : std_logic; --@suppress + signal leds : std_logic_vector(7 downto 0); --@suppress + signal flash_SEL : std_logic; --@suppress + signal flash_a : std_logic_vector(24 downto 0); --@suppress + signal flash_a_msb : std_logic_vector(1 downto 0); --@suppress + signal flash_adv : std_logic; --@suppress + signal flash_cclk : std_logic; --@suppress + signal flash_ce : std_logic; --@suppress + signal flash_d : std_logic_vector(15 downto 0); --@suppress + signal flash_re : std_logic; --@suppress + signal flash_we : std_logic; --@suppress + signal si5324_resetn : std_logic; --@suppress + signal pcie_txn : std_logic_vector((1*8)-1 downto 0); --@suppress + signal pcie_txp : std_logic_vector((1*8)-1 downto 0); --! PCIe link lanes --@suppress + signal uC_reset_N : std_logic; --@suppress + + + signal pcie_rxn : std_logic_vector((1*8)-1 downto 0); -- @suppress "signal pcie_rxn is never written" + signal pcie_rxp : std_logic_vector((1*8)-1 downto 0); -- @suppress "signal pcie_rxp is never written" + signal opto_inhibit : std_logic_vector(4-1 downto 0); -- @suppress "signal opto_inhibit is never read" signal sys_reset_n : std_logic; --! Active-low system reset from PCIe interface); - signal RX_N : std_logic_vector(4-1 downto 0); - signal RX_P : std_logic_vector(4-1 downto 0); - signal TX_N : std_logic_vector(4-1 downto 0); - signal TX_P : std_logic_vector(4-1 downto 0); + signal RX_N : std_logic_vector(24-1 downto 0); -- @suppress "signal RX_N is never written" -- @suppress "signal RX_P is never written" + signal RX_P : std_logic_vector(24-1 downto 0); -- @suppress "signal RX_P is never written" + signal TX_N : std_logic_vector(24-1 downto 0); -- @suppress "signal TX_N is never read" + signal TX_P : std_logic_vector(24-1 downto 0); -- @suppress "signal TX_P is never read" signal GTREFCLK_N_IN : std_logic_vector(5-1 downto 0); signal GTREFCLK_P_IN : std_logic_vector(5-1 downto 0); @@ -160,9 +160,9 @@ architecture structure of felix_top_tb is signal DATA_TTC_N : std_logic; signal DATA_TTC_P : std_logic; signal DATA_TTC : std_logic; - signal GTREFCLK_Si5324_N_IN : std_logic; - signal GTREFCLK_Si5324_P_IN : std_logic; - signal GTREFCLK_Si5324_IN : std_logic; + signal GTREFCLK_Si5324_N_IN : std_logic; -- @suppress "signal GTREFCLK_Si5324_N_IN is never written" + signal GTREFCLK_Si5324_P_IN : std_logic; -- @suppress "signal GTREFCLK_Si5324_P_IN is never written" + signal GTREFCLK_Si5324_IN : std_logic; -- @suppress "Unused declaration" signal sys_clk_n : std_logic_vector(1-1 downto 0); signal sys_clk_p : std_logic_vector(1-1 downto 0); --! 100MHz PCIe reference clock signal sys_clk : std_logic; @@ -187,7 +187,7 @@ architecture structure of felix_top_tb is constant GIT_COMMIT_NUMBER : integer := 1; constant COMMIT_DATETIME : std_logic_vector(39 downto 0) := (others => '0'); constant GTHREFCLK_SEL : std_logic := '0'; - constant wideMode : boolean := false; + constant wideMode : boolean := false; -- @suppress "Unused declaration" constant USE_Si5324_RefCLK : boolean := false; constant IncludeDecodingEpath2_HDLC : std_logic_vector(6 downto 0) := (others => '1'); constant IncludeDecodingEpath2_8b10b : std_logic_vector(6 downto 0) := (others => '1'); diff --git a/simulation/UVVMExample/tb/DecodingGearBox_tb.vhd b/simulation/UVVMExample/tb/DecodingGearBox_tb.vhd index 0b84225bbcfe3a857643f757499259ee3720480d..632179efb137db9cf1c2d07e571906fe0ca30a2a 100644 --- a/simulation/UVVMExample/tb/DecodingGearBox_tb.vhd +++ b/simulation/UVVMExample/tb/DecodingGearBox_tb.vhd @@ -11,8 +11,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; - library STD; - use std.env.all; +use std.env.all; library uvvm_util; context uvvm_util.uvvm_util_context; @@ -32,13 +31,13 @@ end DecodingGearBox_tb; architecture tb of DecodingGearBox_tb is -signal reset, clk40, DataOutValid, BitSlip, BitSlip_s, ElinkAligned: std_logic; +signal reset, clk40, DataOutValid, BitSlip, ElinkAligned: std_logic; signal ElinkData: std_logic_vector(31 downto 0); -signal ElinkData8b: std_logic_vector(7 downto 0); +signal ElinkData8b: std_logic_vector(7 downto 0); -- @suppress "signal ElinkData8b is never read" signal DataOut: std_logic_vector(65 downto 0); -signal DataOut10b: std_logic_vector(9 downto 0); +signal DataOut10b: std_logic_vector(9 downto 0); -- @suppress "signal DataOut10b is never read" constant dataIn_66b: std_logic_vector(65 downto 0) := "10"& x"FEDC_BA98_7654_3305"; -signal cnt: integer := 0; +--signal cnt: integer := 0; signal ElinkWidth, OutputWidth: std_logic_vector(2 downto 0); signal InputBits : integer := 32; @@ -156,7 +155,7 @@ begin end if; for i in 0 to InputBits-1 loop if ReverseInputBits = '1' then - ElinkData((InputBits-1) -i) <= ElinkData_v(i); + ElinkData((InputBits-1) -i) <= ElinkData_v(i); -- @suppress "Dead code" else ElinkData(i) <= ElinkData_v(i); end if; @@ -190,12 +189,12 @@ begin if rising_edge(clk40) then BitSlip <= '0'; if AlignmentPulse = '1' then - BitSlip <= not GearBoxAligned; + BitSlip <= not GearboxAligned; end if; if DataOut(OutputBits-1 downto 0) = dataIn_66b(OutputBits-1 downto 0) and DataOutValid = '1' then - GearBoxAligned <= '1'; + GearboxAligned <= '1'; elsif DataOutValid = '1' then - GearBoxAligned <= '0'; + GearboxAligned <= '0'; end if; end if; end process; diff --git a/simulation/UVVMExample/tb/EncodingEpath_tb.vhd b/simulation/UVVMExample/tb/EncodingEpath_tb.vhd index 52335b464d7b6fe0dd2eb4824cadd3719ec00a7d..18917f4b4c6ee9683e9fe5214eedafcb554be30d 100644 --- a/simulation/UVVMExample/tb/EncodingEpath_tb.vhd +++ b/simulation/UVVMExample/tb/EncodingEpath_tb.vhd @@ -13,7 +13,6 @@ use IEEE.numeric_std.all; use work.axi_stream_package.all; use work.centralRouter_package.all; -library STD; use std.env.all; library uvvm_util; @@ -45,9 +44,9 @@ architecture tb of EncodingEpath_tb is signal ElinkWidth_i: std_logic_vector(1 downto 0) :="00"; signal DecodingEpathWidth_i : std_logic_vector(2 downto 0); signal EpathEncoding_i: std_logic_vector(3 downto 0) := x"1"; - signal XOff_i : std_logic := '0'; + constant XOff_i : std_logic := '0'; signal s_axis_i : axis_8_type; - signal s_axis_tready_i : std_logic; + signal s_axis_tready_i : std_logic; -- @suppress "signal s_axis_tready_i is never read" signal TTCOption_i: std_logic_vector(3 downto 0) :=(others => '0'); signal TTCOption_control: std_logic_vector(3 downto 0) :=(others => '0'); signal TTCin_i : std_logic_vector(10 downto 0) :=(others => '0'); @@ -55,14 +54,14 @@ architecture tb of EncodingEpath_tb is --file OUTPUT, OUTPUT2 : text; - signal reading, finish_read, header_found: std_logic := '0'; + signal reading, finish_read: std_logic := '0'; signal ttc_wrote: std_logic := '0'; --signal max : integer := 255; signal max : integer := 33; signal combined_data : std_logic_vector(7 downto 0); signal word_length : integer:=0; - signal kflag : std_logic; + signal kflag : std_logic; -- @suppress "signal kflag is never read" signal DataOut_tmp : std_logic_vector(7 downto 0); signal data_two_words : std_logic_vector(15 downto 0); signal data_10b : std_logic_vector(9 downto 0); @@ -75,7 +74,7 @@ architecture tb of EncodingEpath_tb is signal data_HDLC : std_logic_vector(7 downto 0); signal data_HDLC_valid : std_logic; - signal debug_flag: std_logic; + --signal debug_flag: std_logic; begin gen: for i in 0 to 9 generate @@ -87,33 +86,35 @@ end generate; EncodingEpathGBT_uut: entity work.EncodingEpathGBT generic Map( - MAX_OUTPUT => 8, - INCLUDE_8b => '1', - INCLUDE_4b => '1', - INCLUDE_2b => '1', - INCLUDE_8b10b => '1', - INCLUDE_HDLC => '1', + MAX_OUTPUT => 8, + INCLUDE_8b => '1', + INCLUDE_4b => '1', + INCLUDE_2b => '1', + INCLUDE_8b10b => '1', + INCLUDE_HDLC => '1', INCLUDE_DIRECT => '1', - BLOCKSIZE => 1024, + INCLUDE_TTC => '1', + BLOCKSIZE => 1024, GENERATE_FEI4B => false, GENERATE_LCB_ENC => false, HDLC_IDLE_STATE => x"7F" ) port Map( - clk40 => clk40, - reset => reset, - EpathEnable => '1', - EpathEncoding => EpathEncoding_i, - ElinkWidth => ElinkWidth_i, - MsbFirst => '1', + clk40 => clk40, + reset => reset, + EpathEnable => '1', + EpathEncoding => EpathEncoding_i, + ElinkWidth => ElinkWidth_i, + MsbFirst => '1', ReverseOutputBits => '0', - ElinkData => ElinkData_i, - XOff => xOff_i, - s_axis => s_axis_i, + ElinkData => ElinkData_i, + Xoff => XOff_i, + epath_almost_full => open, + s_axis => s_axis_i, s_axis_tready => s_axis_tready_i, - s_axis_aclk => s_axis_aclk_i, - TTCOption => TTCOption_i, - TTCin => TTCin_i + s_axis_aclk => s_axis_aclk_i, + TTCOption => TTCOption_i, + TTCin => TTCin_i ); DecodingEpathWidth_i <= '0'&ElinkWidth_i; @@ -189,15 +190,20 @@ PORT MAP( dec_HDLC_inst: entity work.DecoderHDLC + generic map( + g_WORD_SIZE => 8, + g_DELIMITER => x"7E", + g_IDLE => x"7F" + ) PORT MAP ( - clk40 => clk40, - reset => reset, - ena => '1', - DataIn => ElinkData_i(1 downto 0), - DataOut => data_HDLC, - DataOutValid => data_HDLC_valid, - EOP => open, - TruncateHDLC => open, + clk40 => clk40, + ena => '1', + reset => reset, + DataIn => ElinkData_i(1 downto 0), + DataOut => data_HDLC, + DataOutValid => data_HDLC_valid, + EOP => open, + TruncateHDLC => open, EnableTruncation => '1' ); @@ -218,9 +224,9 @@ p_output_check: process constant C_SCOPE : string := C_TB_SCOPE_DEFAULT; variable position_i: integer:=0; variable next_sign: integer:=0; - variable header_flag: std_logic:='0'; + --variable header_flag: std_logic:='0'; variable TP : std_logic:='0'; - variable Brc_t2 : std_logic_vector(1 downto 0):= (others=>'0'); + variable Brc_t2 : std_logic_vector(1 downto 0):= (others=>'0'); -- @suppress "variable Brc_t2 is never read" variable Brc_d4 : std_logic_vector(3 downto 0):= (others=>'0'); variable ECR : std_logic:='0'; variable BCR : std_logic:='0'; @@ -296,61 +302,61 @@ p_output_check: process wait for 5 ns; end; - procedure check_timing is - begin - while position_i = 1 loop - - slice_data; - - if (data_10b_rev = COMMAp) then - next_sign := 2; - position_i := 2; - log("pos data " &to_string(data_two_words)& " "& to_string(data_10b_rev)); - elsif (data_10b_rev = COMMAn) then - next_sign := 1; - position_i := 2; - log("neg data " &to_string(data_two_words)& " "& to_string(data_10b_rev)); - end if; - - wait for 10 ns; - - end loop; - end; - - procedure wait_header is - begin - header_flag := '0'; - while header_flag = '0' loop - - slice_data; - log("In wait data " &to_string(data_two_words)& " "& to_string(data_10b_rev)); - - if (data_10b_rev = std_logic_vector(to_unsigned(0, 10))) then - log("skip one cycle"); - elsif (next_sign = 1) then - if(data_10b_rev = SOCp) then - log("header found"); - header_flag := '1'; - else - check_value(data_10b_rev, COMMAp, ERROR, "Comma pos", C_SCOPE); - end if; - next_sign := 2; - elsif (next_sign = 2) then - if(data_10b_rev = SOCn) then - log("header found"); - header_flag := '1'; - else - check_value(data_10b_rev, COMMAn, ERROR, "Comma neg", C_SCOPE); - end if; - next_sign := 1; - else - error("Unexpected sign",C_TB_SCOPE_DEFAULT); - end if; - - change_pos; - end loop; - - end; + --procedure check_timing is + --begin + -- while position_i = 1 loop + -- + -- slice_data; + -- + -- if (data_10b_rev = COMMAp) then + -- next_sign := 2; + -- position_i := 2; + -- log("pos data " &to_string(data_two_words)& " "& to_string(data_10b_rev)); + -- elsif (data_10b_rev = COMMAn) then + -- next_sign := 1; + -- position_i := 2; + -- log("neg data " &to_string(data_two_words)& " "& to_string(data_10b_rev)); + -- end if; + -- + -- wait for 10 ns; + -- + -- end loop; + --end; + + --procedure wait_header is + --begin + -- header_flag := '0'; + -- while header_flag = '0' loop + -- + -- slice_data; + -- log("In wait data " &to_string(data_two_words)& " "& to_string(data_10b_rev)); + -- + -- if (data_10b_rev = std_logic_vector(to_unsigned(0, 10))) then + -- log("skip one cycle"); + -- elsif (next_sign = 1) then + -- if(data_10b_rev = SOCp) then + -- log("header found"); + -- header_flag := '1'; + -- else + -- check_value(data_10b_rev, COMMAp, ERROR, "Comma pos", C_SCOPE); + -- end if; + -- next_sign := 2; + -- elsif (next_sign = 2) then + -- if(data_10b_rev = SOCn) then + -- log("header found"); + -- header_flag := '1'; + -- else + -- check_value(data_10b_rev, COMMAn, ERROR, "Comma neg", C_SCOPE); + -- end if; + -- next_sign := 1; + -- else + -- error("Unexpected sign",C_TB_SCOPE_DEFAULT); + -- end if; + -- + -- change_pos; + -- end loop; + -- + --end; procedure check_data_8b10b( constant expected : in std_logic_vector(7 downto 0)) is @@ -533,7 +539,7 @@ p_output_check: process ------------------------------------------------ p_combine: process(clk40,reset) - constant C_SCOPE : string := C_TB_SCOPE_DEFAULT; + --constant C_SCOPE : string := C_TB_SCOPE_DEFAULT; begin if (reset = '1') then combined_data <= (others => '0'); diff --git a/simulation/UVVMExample/tb/FULLModeToHost_tb.vhd b/simulation/UVVMExample/tb/FULLModeToHost_tb.vhd index 48c100b7a327f4025f6a5d37385e17feaf9f08ae..f2def8d5a8bca1288676fea41600af4baa21998e 100644 --- a/simulation/UVVMExample/tb/FULLModeToHost_tb.vhd +++ b/simulation/UVVMExample/tb/FULLModeToHost_tb.vhd @@ -31,7 +31,7 @@ end entity; architecture arch of FULLModeToHost_tb is function to_dstring (a : natural; d : integer range 1 to 9) return string is - variable vString : string(1 to d) := (others => ' '); + constant vString : string(1 to d) := (others => ' '); begin if(a >= 10**d) then return integer'image(a); @@ -55,30 +55,29 @@ architecture arch of FULLModeToHost_tb is constant STREAMS_TOHOST: integer := STREAMS_TOHOST_MODE(FIRMWARE_MODE); constant BLOCKSIZE : integer :=1024; constant LOCK_PERIOD : integer := 640; - constant wideMode : boolean := false; + constant CHUNK_TRAILER_32B : boolean := true; constant DATA_WIDTH : integer := 256; constant SIM_NUMBER_OF_BLOCKS : integer := 1000; constant pcie_endpoint: integer := 0; - signal GBT_UPLINK_USER_DATA : txrx120b_type(0 to (GBT_NUM-1)); - signal register_map_xoff_monitor : register_map_xoff_monitor_type; - signal register_map_gbtemu_monitor : register_map_gbtemu_monitor_type; - signal register_map_decoding_monitor : register_map_decoding_monitor_type; + signal GBT_UPLINK_USER_DATA : txrx120b_type(0 to (GBT_NUM-1)); -- @suppress "signal GBT_UPLINK_USER_DATA is never read" + signal register_map_xoff_monitor : register_map_xoff_monitor_type; -- @suppress "signal register_map_xoff_monitor is never read" + signal register_map_gbtemu_monitor : register_map_gbtemu_monitor_type; -- @suppress "signal register_map_gbtemu_monitor is never read" + signal register_map_decoding_monitor : register_map_decoding_monitor_type; -- @suppress "signal register_map_decoding_monitor is never read" signal register_map_40_control : register_map_control_type; signal register_map_control_appreg_clk : register_map_control_type; - signal emuToHost_GBTdata: std_logic_vector(119 downto 0); - signal emuToHost_GBTlinkValid : std_logic; - signal GBT_UPLINK_USER_DATA_FOSEL : txrx120b_type (0 to GBT_NUM/ENDPOINTS-1); - signal GBT_DOWNLINK_USER_DATA_ENCODING : txrx120b_type (0 to GBT_NUM/ENDPOINTS-1); + signal emuToHost_GBTdata: std_logic_vector(119 downto 0); -- @suppress "Unused declaration" + + constant GBT_UPLINK_USER_DATA_FOSEL : txrx120b_type (0 to GBT_NUM/ENDPOINTS-1) := (others => (others => '0')); + --signal GBT_DOWNLINK_USER_DATA_ENCODING : txrx120b_type (0 to GBT_NUM/ENDPOINTS-1); signal LinkAligned_FOSEL : std_logic_vector(GBT_NUM/ENDPOINTS-1 downto 0); signal toHostFifo_din : slv_array(0 to NUMBER_OF_DESCRIPTORS-2); signal toHostFifo_wr_en : std_logic_vector(NUMBER_OF_DESCRIPTORS-2 downto 0); signal toHostFifo_prog_full : std_logic_vector(NUMBER_OF_DESCRIPTORS-2 downto 0); signal toHostFifo_wr_clk : std_logic; - signal toHostFifo_rst : std_logic; - signal wr_data_count : slv12_array(0 to NUMBER_OF_DESCRIPTORS-2); + constant wr_data_count : slv12_array(0 to NUMBER_OF_DESCRIPTORS-2) := (others => (others => '0')); signal decoding_aclk : std_logic; signal decoding_axis : axis_32_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_TOHOST-1); signal decoding_axis_tready : axis_tready_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_TOHOST-1); @@ -104,37 +103,18 @@ architecture arch of FULLModeToHost_tb is signal reset : std_logic; signal aresetn : std_logic; - signal rst_hw, rst_soft_40: std_logic; - + --==================================Egroup_reader type slv16_array is array (natural range <>) of std_logic_vector(15 downto 0); signal block_data: slv16_array(0 to 511); - signal chunk_data: slv16_array(0 to 1023); - signal start_check: std_logic:='0'; - - signal Trunc : std_logic:='0'; - signal TrailerError:std_logic:='0'; - signal CRCError : std_logic:='0'; - - signal chunk_count_s: integer range 0 to 1023; - signal chunk_length_s: integer range 0 to 1023; - signal chunk_index_s: integer range 0 to 1023; - signal trailer_s, Eout: std_logic_vector(15 downto 0):=X"0000"; - signal block_count: integer range 0 to 511; - signal GBTdata : std_logic_vector (119 downto 0); - - signal EPath_HFs, Epath_AFs, EPath_REs, EPath_Busy: std_logic_vector(7 downto 0):="00000000"; - signal anyEPATH_HFs: std_logic; - signal Eout_rdy : std_logic :='0'; - constant toHostTimeoutBitn : integer := 16; - signal timeCntIn: unsigned(toHostTimeoutBitn-1 downto 0):=(others =>'0'); - - signal block_error0: std_logic:='0'; - signal chunk_error0: std_logic:='0'; - signal GbtConfig : std_logic_vector (63 downto 0) := (others =>'0'); - signal EPATH_ID: std_logic_vector(2 downto 0); - signal GTH_FM_RX_33b_out : txrx33b_type(0 to (GBT_NUM-1)); + signal start_check: std_logic:='0'; -- @suppress "signal start_check is never read" + signal Trunc : std_logic:='0'; -- @suppress "signal Trunc is never read" + signal TrailerError:std_logic:='0'; -- @suppress "signal TrailerError is never read" + signal CRCError : std_logic:='0'; -- @suppress "signal CRCError is never read" + signal block_error0: std_logic:='0'; -- @suppress "signal block_error0 is never read" + signal chunk_error0: std_logic:='0'; -- @suppress "signal chunk_error0 is never read" + signal GTH_FM_RX_33b_out : txrx33b_type(0 to (GBT_NUM-1)); signal checker_done: std_logic; signal backpressure_applied : std_logic; constant Trailer32b : boolean := true; @@ -175,9 +155,7 @@ begin end process; aresetn <= not reset; - rst_hw <= reset; - rst_soft_40 <= reset; - + register_map_40_control.FE_EMU_ENA.EMU_TOHOST <= "1"; register_map_40_control.FE_EMU_ENA.EMU_TOFRONTEND <= "1"; register_map_40_control.FE_EMU_CONFIG.WE <= (others => '0'); @@ -200,11 +178,17 @@ begin decoding0: entity work.decoding generic map( - GBT_NUM => GBT_NUM/ENDPOINTS, - FIRMWARE_MODE => FIRMWARE_MODE, + GBT_NUM => GBT_NUM/ENDPOINTS, + FIRMWARE_MODE => FIRMWARE_MODE, STREAMS_TOHOST => STREAMS_TOHOST, - BLOCKSIZE => BLOCKSIZE, - LOCK_PERIOD => LOCK_PERIOD + BLOCKSIZE => BLOCKSIZE, + LOCK_PERIOD => LOCK_PERIOD, + IncludeDecodingEpath2_HDLC => "1111111", + IncludeDecodingEpath2_8b10b => "1111111", + IncludeDecodingEpath4_8b10b => "1111111", + IncludeDecodingEpath8_8b10b => "1111111", + IncludeDecodingEpath16_8b10b => "1111111", + IncludeDecodingEpath32_8b10b => "1111111" ) Port map( RXUSRCLK => RXUSRCLK(((GBT_NUM/ENDPOINTS)*(pcie_endpoint+1))-1 downto (GBT_NUM/ENDPOINTS)*pcie_endpoint), --: in std_logic_vector(GBT_NUM-1 downto 0); @@ -237,24 +221,25 @@ decoding0: entity work.decoding CHUNK_TRAILER_32B => CHUNK_TRAILER_32B, DATA_WIDTH => DATA_WIDTH) port map( - clk40 => clk40, - clk250 => clk250, - aclk_tohost => decoding_aclk, - aresetn => aresetn, - register_map_control => register_map_40_control, - register_map_xoff_monitor => register_map_xoff_monitor, - interrupt_call => open, - s_axis => fanout_sel_axis, - s_axis_tready => fanout_sel_axis_tready, - s_axis_prog_empty => fanout_sel_axis_prog_empty, - toHostFifo_din => toHostFifo_din, - toHostFifo_wr_en => toHostFifo_wr_en, - toHostFifo_prog_full => toHostFifo_prog_full, - toHostFifo_wr_clk => toHostFifo_wr_clk, - toHostFifo_rst => toHostFifo_rst, - thFIFObusyOut => open, - TTC_ToHost_Data_in => TTC_ToHost_Data, - toHostFifo_wr_data_count => wr_data_count); + clk40 => clk40, + clk250 => clk250, + aclk_tohost => decoding_aclk, + aresetn => aresetn, + register_map_control => register_map_40_control, + register_map_xoff_monitor => register_map_xoff_monitor, + register_map_crtohost_monitor => open, + interrupt_call => open, + s_axis => fanout_sel_axis, + s_axis_tready => fanout_sel_axis_tready, + s_axis_prog_empty => fanout_sel_axis_prog_empty, + toHostFifo_din => toHostFifo_din, + toHostFifo_wr_en => toHostFifo_wr_en, + toHostFifo_prog_full => toHostFifo_prog_full, + toHostFifo_wr_clk => toHostFifo_wr_clk, + toHostFifo_rst => open, + thFIFObusyOut => open, + TTC_ToHost_Data_in => TTC_ToHost_Data, + toHostFifo_wr_data_count => wr_data_count); g_EnableFullModeEmulator: if FIRMWARE_MODE = FIRMWARE_MODE_FULL generate @@ -281,7 +266,7 @@ decoding0: entity work.decoding ) port map( aclk => decoding_aclk, - aresetn => aresetn, + --aresetn => aresetn, emu_axis => emu_axis, emu_axis_tready => emu_axis_tready, emu_axis_prog_empty => emu_axis_prog_empty, @@ -359,8 +344,8 @@ begin end process; -- sequencer checker: process - variable re_count: integer range 0 to 511; - variable reading : boolean := false; + variable re_count: integer range 0 to 511; -- @suppress "variable re_count is never read" + variable reading : boolean := false; -- @suppress "variable reading is never read" --variable block_data0_v: slv16_array(0 to 511); type ByteArray is array (natural range<>) of std_logic_vector(7 downto 0); type Chunk2DArray is array (natural range<>, natural range<>) of ByteArray(0 to 2047); @@ -381,9 +366,9 @@ checker: process --variable chunk_index: IntArray(0 to 63); variable ElinkID : integer range 0 to STREAMS_TOHOST-1; variable GBTID : integer range 0 to GBT_NUM-1; - variable BlockSequence : integer range 0 to 31; + variable BlockSequence : integer range 0 to 31; -- @suppress "variable BlockSequence is never read" - variable checking: boolean; + variable checking: boolean; -- @suppress "variable checking is never read" variable trailer: std_logic_vector(31 downto 0); variable TrailerType: std_logic_vector(2 downto 0):="000"; variable progress : integer := 100; @@ -494,7 +479,7 @@ begin if block_data(1) /= x"ABCE" then check_value(block_data(1), x"ABCE", ERROR, "Invalid block header", C_SCOPE); end if; - else + else -- @suppress "Dead code" if block_data(1) /= x"ABCD" then check_value(block_data(1), x"ABCD", ERROR, "Invalid block header", C_SCOPE); end if; @@ -510,7 +495,7 @@ begin trailer := block_data(chunk_count) & block_data(chunk_count-1); TrailerType := trailer(31 downto 29); chunk_count := chunk_count - 2; --Move to last data word - else + else -- @suppress "Dead code" trailer := x"0000"&block_data(chunk_count); TrailerType := trailer(15 downto 13); chunk_count := chunk_count - 1; --Move to last data word @@ -549,7 +534,7 @@ begin Trunc_v := trailer(28); Error_v := trailer(27); CRCError_v := trailer(26); - else + else -- @suppress "Dead code" trailer := x"0000"&block_data(chunk_count); TrailerType := trailer(15 downto 13); Trunc_v := trailer(12); @@ -581,7 +566,7 @@ begin case(TrailerType) is when "000" => NULL; when "001" => --First - if ReceivingState(GBTID,ElinkID) = true then + if ReceivingState(GBTID,ElinkID) then tb_error("ReceivingState was true while getting first trailer type", C_SCOPE); end if; ReceivingState(GBTID,ElinkID) := true; @@ -591,7 +576,7 @@ begin end if; ReceivingState(GBTID,ElinkID) := false; when "011" => --Both - if ReceivingState(GBTID,ElinkID) = true then + if ReceivingState(GBTID,ElinkID) then tb_error("ReceivingState was true while getting both trailer type", C_SCOPE); end if; ReceivingState(GBTID,ElinkID) := false; diff --git a/simulation/UVVMExample/tb/GBTLinkToHost_tb.vhd b/simulation/UVVMExample/tb/GBTLinkToHost_tb.vhd index 8765e91c2855e89e835bc231ae46fbd7b8ce82f5..7ef8a07f402963210846a05441340762035950e4 100644 --- a/simulation/UVVMExample/tb/GBTLinkToHost_tb.vhd +++ b/simulation/UVVMExample/tb/GBTLinkToHost_tb.vhd @@ -31,7 +31,7 @@ end entity; architecture arch of GBTLinkToHost_tb is function to_dstring (a : natural; d : integer range 1 to 9) return string is - variable vString : string(1 to d) := (others => ' '); + constant vString : string(1 to d) := (others => ' '); begin if(a >= 10**d) then return integer'image(a); @@ -54,7 +54,6 @@ architecture arch of GBTLinkToHost_tb is constant STREAMS_TOHOST: integer := STREAMS_TOHOST_MODE(FIRMWARE_MODE); constant BLOCKSIZE : integer :=1024; constant LOCK_PERIOD : integer := 640; - constant wideMode : boolean := false; constant CHUNK_TRAILER_32B : boolean := true; constant DATA_WIDTH : integer := 256; constant SIM_NUMBER_OF_BLOCKS : integer := 1000; @@ -62,27 +61,25 @@ architecture arch of GBTLinkToHost_tb is constant pcie_endpoint: integer := 0; signal GBT_UPLINK_USER_DATA : txrx120b_type(0 to (GBT_NUM-1)); - signal register_map_xoff_monitor : register_map_xoff_monitor_type; - signal register_map_gbtemu_monitor : register_map_gbtemu_monitor_type; - signal register_map_decoding_monitor : register_map_decoding_monitor_type; + signal register_map_xoff_monitor : register_map_xoff_monitor_type; -- @suppress "signal register_map_xoff_monitor is never read" + signal register_map_gbtemu_monitor : register_map_gbtemu_monitor_type; -- @suppress "Unused declaration" + signal register_map_decoding_monitor : register_map_decoding_monitor_type; -- @suppress "signal register_map_decoding_monitor is never read" signal register_map_40_control : register_map_control_type; signal emuToHost_GBTdata: std_logic_vector(119 downto 0); signal emuToHost_GBTlinkValid : std_logic; signal GBT_UPLINK_USER_DATA_FOSEL : txrx120b_type (0 to GBT_NUM/ENDPOINTS-1); - signal GBT_DOWNLINK_USER_DATA_ENCODING : txrx120b_type (0 to GBT_NUM/ENDPOINTS-1); + signal LinkAligned_FOSEL : std_logic_vector(GBT_NUM/ENDPOINTS-1 downto 0); signal toHostFifo_din : slv_array(0 to NUMBER_OF_DESCRIPTORS-2); signal toHostFifo_wr_en : std_logic_vector(NUMBER_OF_DESCRIPTORS-2 downto 0); signal toHostFifo_prog_full : std_logic_vector(NUMBER_OF_DESCRIPTORS-2 downto 0); signal toHostFifo_wr_clk : std_logic; - signal toHostFifo_rst : std_logic; - signal wr_data_count : slv12_array(0 to NUMBER_OF_DESCRIPTORS-2); + signal toHostFifo_rst : std_logic; -- @suppress "signal toHostFifo_rst is never read" + signal wr_data_count : slv12_array(0 to NUMBER_OF_DESCRIPTORS-2); -- @suppress "signal wr_data_count is never written" signal decoding_aclk : std_logic; signal decoding_axis : axis_32_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_TOHOST-1); signal decoding_axis_tready : axis_tready_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_TOHOST-1); signal decoding_axis_prog_empty : axis_tready_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_TOHOST-1); - signal emu_axis : axis_32_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_TOHOST-1); - signal emu_axis_tready : axis_tready_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_TOHOST-1); signal fanout_sel_axis : axis_32_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_TOHOST-1); signal fanout_sel_axis_tready : axis_tready_2d_array_type(0 to GBT_NUM/ENDPOINTS-1, 0 to STREAMS_TOHOST-1); signal LinkAligned : std_logic_vector(GBT_NUM-1 downto 0); @@ -103,30 +100,15 @@ architecture arch of GBTLinkToHost_tb is --==================================Egroup_reader type slv16_array is array (natural range <>) of std_logic_vector(15 downto 0); signal block_data: slv16_array(0 to 511); - signal chunk_data: slv16_array(0 to 1023); - signal start_check: std_logic:='0'; - - signal Trunc : std_logic:='0'; - signal TrailerError:std_logic:='0'; - signal CRCError : std_logic:='0'; - - signal chunk_count_s: integer range 0 to 1023; - signal chunk_length_s: integer range 0 to 1023; - signal chunk_index_s: integer range 0 to 1023; - signal trailer_s, Eout: std_logic_vector(15 downto 0):=X"0000"; - signal block_count: integer range 0 to 511; - signal GBTdata : std_logic_vector (119 downto 0); - - signal EPath_HFs, Epath_AFs, EPath_REs, EPath_Busy: std_logic_vector(7 downto 0):="00000000"; - signal anyEPATH_HFs: std_logic; - signal Eout_rdy : std_logic :='0'; - constant toHostTimeoutBitn : integer := 16; - signal timeCntIn: unsigned(toHostTimeoutBitn-1 downto 0):=(others =>'0'); + --signal chunk_data: slv16_array(0 to 1023); + signal start_check: std_logic:='0'; -- @suppress "signal start_check is never read" + + signal Trunc : std_logic:='0'; -- @suppress "signal Trunc is never read" + signal TrailerError:std_logic:='0'; -- @suppress "signal TrailerError is never read" + signal CRCError : std_logic:='0'; -- @suppress "signal CRCError is never read" - signal block_error0: std_logic:='0'; - signal chunk_error0: std_logic:='0'; - signal GbtConfig : std_logic_vector (63 downto 0) := (others =>'0'); - signal EPATH_ID: std_logic_vector(2 downto 0); + signal block_error0: std_logic:='0'; -- @suppress "signal block_error0 is never read" -- @suppress "signal chunk_error0 is never read" + signal chunk_error0: std_logic:='0'; -- @suppress "signal chunk_error0 is never read" signal GTH_FM_RX_33b_out : txrx33b_type(0 to (GBT_NUM-1)); signal checker_done: std_logic; @@ -138,7 +120,7 @@ architecture arch of GBTLinkToHost_tb is constant IncludeDecodingEpath8_8b10b : std_logic_vector(6 downto 0) := (others => '1'); constant IncludeDecodingEpath16_8b10b : std_logic_vector(6 downto 0) := (others => '1'); constant IncludeDecodingEpath32_8b10b : std_logic_vector(6 downto 0) := (others => '1'); - signal register_map_crtohost_monitor : register_map_crtohost_monitor_type; + signal register_map_crtohost_monitor : register_map_crtohost_monitor_type; -- @suppress "signal register_map_crtohost_monitor is never read" begin TTC_ToHost_Data <= ( @@ -402,8 +384,8 @@ begin end process; -- sequencer checker: process - variable re_count: integer range 0 to 511; - variable reading : boolean := false; + variable re_count: integer range 0 to 511; -- @suppress "variable re_count is never read" + variable reading : boolean := false; -- @suppress "variable reading is never read" --variable block_data0_v: slv16_array(0 to 511); type ByteArray is array (natural range<>) of std_logic_vector(7 downto 0); type Chunk2DArray is array (natural range<>, natural range<>) of ByteArray(0 to 2047); @@ -424,9 +406,9 @@ checker: process --variable chunk_index: IntArray(0 to 63); variable ElinkID : integer range 0 to STREAMS_TOHOST-1; variable GBTID : integer range 0 to GBT_NUM-1; - variable BlockSequence : integer range 0 to 31; + variable BlockSequence : integer range 0 to 31; -- @suppress "variable BlockSequence is never read" - variable checking: boolean; + variable checking: boolean; -- @suppress "variable checking is never read" variable trailer: std_logic_vector(31 downto 0); variable TrailerType: std_logic_vector(2 downto 0):="000"; variable progress : integer := 100; @@ -577,7 +559,7 @@ begin if block_data(1) /= x"ABCE" then check_value(block_data(1), x"ABCE", ERROR, "Invalid block header", C_SCOPE); end if; - else + else -- @suppress "Dead code" if block_data(1) /= x"ABCD" then check_value(block_data(1), x"ABCD", ERROR, "Invalid block header", C_SCOPE); end if; @@ -593,7 +575,7 @@ begin trailer := block_data(chunk_count) & block_data(chunk_count-1); TrailerType := trailer(31 downto 29); chunk_count := chunk_count - 2; --Move to last data word - else + else -- @suppress "Dead code" trailer := x"0000"&block_data(chunk_count); TrailerType := trailer(15 downto 13); chunk_count := chunk_count - 1; --Move to last data word @@ -632,7 +614,7 @@ begin Trunc_v := trailer(28); Error_v := trailer(27); CRCError_v := trailer(26); - else + else -- @suppress "Dead code" trailer := x"0000"&block_data(chunk_count); TrailerType := trailer(15 downto 13); Trunc_v := trailer(12); @@ -664,7 +646,7 @@ begin case(TrailerType) is when "000" => NULL; when "001" => --First - if ReceivingState(GBTID,ElinkID) = true then + if ReceivingState(GBTID,ElinkID) then tb_error("ReceivingState was true while getting first trailer type", C_SCOPE); end if; ReceivingState(GBTID,ElinkID) := true; @@ -674,7 +656,7 @@ begin end if; ReceivingState(GBTID,ElinkID) := false; when "011" => --Both - if ReceivingState(GBTID,ElinkID) = true then + if ReceivingState(GBTID,ElinkID) then tb_error("ReceivingState was true while getting both trailer type", C_SCOPE); end if; ReceivingState(GBTID,ElinkID) := false; diff --git a/simulation/UVVMExample/tb/amac_chip.vhd b/simulation/UVVMExample/tb/amac_chip.vhd index 3a432ee5709c55b24590efbeb7775f08b14b1c86..f9f7a458020f5281a2c9cec1b7cbcb516a331756 100644 --- a/simulation/UVVMExample/tb/amac_chip.vhd +++ b/simulation/UVVMExample/tb/amac_chip.vhd @@ -23,8 +23,8 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.axi_stream_package.all; use ieee.numeric_std.all; -use ieee.STD_LOGIC_ARITH.all; -use ieee.STD_LOGIC_UNSIGNED.all; +use ieee.STD_LOGIC_ARITH.all;-- @suppress "Deprecated package" +use ieee.STD_LOGIC_UNSIGNED.all;-- @suppress "Deprecated package" -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values @@ -47,8 +47,8 @@ end amac_chip; architecture Behavioral of amac_chip is --------------------------------- SOGLIE DA CAMBIARE IN BASE AL CLOCK -------------------------------------------------------- - constant TICKS_QUIESCENT : integer := 100; -- 512 + ~40% = 704 (1011000000) - constant TICKS_TX2RX : integer := 4; -- =50ns + --constant TICKS_QUIESCENT : integer := 100; -- 512 + ~40% = 704 (1011000000) + --constant TICKS_TX2RX : integer := 4; -- =50ns constant TICKS_DIT_MIN : integer := 6; -- (*2 for 80MHz) constant TICKS_DIT_MAX : integer := 22; -- 4+16=20 (*2) constant TICKS_DIT_MID : integer := (TICKS_DIT_MIN + TICKS_DIT_MAX)/2; --24 0 @@ -65,7 +65,7 @@ architecture Behavioral of amac_chip is type fsm_AMAC_t is (idle, readbit, readgap, idreply0, idreply1, idreplygap, seqreply0, seqreply1, seqreplygap, datareply0, datareply1, datareplygap, errorstate); --, intertransactgap); signal fsm_AMAC : fsm_AMAC_t := idle; -signal nmaxbit, nbitrd, nclock : std_logic_vector(7 downto 0) := (others => '0'); +signal nmaxbit, nbitrd, nclock : std_logic_vector(7 downto 0) := (others => '0'); -- @suppress "signal nmaxbit is never read" signal command, seqnum : std_logic_vector(2 downto 0) := (others => '0'); signal signalin_del, signalin_rising, signalin_falling: std_logic; @@ -315,7 +315,7 @@ begin end if; end if; - when errorstate => -- wait a little bit for things to settle + when errorstate => -- wait a little bit for things to settle -- @suppress "Dead state 'errorstate': state does not have outgoing transitions" fsm_AMAC <= errorstate; diff --git a/simulation/UVVMExample/tb/amac_demo_tb.vhd b/simulation/UVVMExample/tb/amac_demo_tb.vhd index 4bf93f54d3e1c6333bb7908bec70ac0459731f0d..7c07eba2ccf2947075640a8e11bbf4849d93b836 100644 --- a/simulation/UVVMExample/tb/amac_demo_tb.vhd +++ b/simulation/UVVMExample/tb/amac_demo_tb.vhd @@ -20,7 +20,7 @@ use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; - library STD; + --library STD; use std.env.all; library uvvm_util; @@ -47,7 +47,7 @@ signal amac_signal : std_logic := '0'; signal gbt_signal : std_logic_vector(1 downto 0) ; signal to_amac : std_logic := '0'; - signal test_link : std_logic := '0'; + signal test_link : std_logic := '0'; -- @suppress "signal test_link is never read" -- output signal data_axi_fromhost : axis_8_type; signal data_ready_fromhost : std_logic := '0'; @@ -64,10 +64,10 @@ constant C_CLK_PERIOD_40 : time := 25 ns; constant C_CLK_PERIOD_250 : time := 4 ns; - constant BIT1_TIME : time := 76 * C_CLK_PERIOD_40; - constant BIT0_TIME : time := 14 * C_CLK_PERIOD_40; - constant INTRAWORD_GAP_TIME : time := 43 * C_CLK_PERIOD_40; - constant ENDWORD_GAP_TIME : time := 100 * C_CLK_PERIOD_40; + --constant BIT1_TIME : time := 76 * C_CLK_PERIOD_40; + --constant BIT0_TIME : time := 14 * C_CLK_PERIOD_40; + --constant INTRAWORD_GAP_TIME : time := 43 * C_CLK_PERIOD_40; + --constant ENDWORD_GAP_TIME : time := 100 * C_CLK_PERIOD_40; begin ----------------------------------------------------------------------------- @@ -149,8 +149,7 @@ -- clk, sbi_if, alert_level, C_SCOPE); --end; - procedure set_inputs_passive( - dummy : t_void) is + procedure set_inputs_passive is begin log(ID_SEQUENCER_SUB, "All inputs set passive", C_SCOPE); end; @@ -174,7 +173,7 @@ log(ID_LOG_HDR, "Simulation of TB for Endeveour", C_SCOPE); ------------------------------------------------------------ - set_inputs_passive(VOID); + set_inputs_passive; clock_ena <= true; -- to start clock generator diff --git a/simulation/UVVMExample/tb/amacgbt_converter.vhd b/simulation/UVVMExample/tb/amacgbt_converter.vhd index a3938ac8585c5300c158c6cccf903933920649ff..81f5a5e936db020d8f6912c45d6a57fd0b31c28b 100644 --- a/simulation/UVVMExample/tb/amacgbt_converter.vhd +++ b/simulation/UVVMExample/tb/amacgbt_converter.vhd @@ -23,8 +23,8 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.axi_stream_package.all; use ieee.numeric_std.all; -use ieee.STD_LOGIC_ARITH.all; -use ieee.STD_LOGIC_UNSIGNED.all; +use ieee.STD_LOGIC_ARITH.all;-- @suppress "Deprecated package" +use ieee.STD_LOGIC_UNSIGNED.all;-- @suppress "Deprecated package" -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values @@ -77,11 +77,11 @@ signal twobitsignal : std_logic_vector(1 downto 0) := (others => '0'); signal datavalid : std_logic; signal readrq : std_logic := '0'; signal fifodataout : std_logic_vector(1 downto 0) := (others => '0'); -signal fifofull : std_logic; -signal fifoempty : std_logic; -signal fifoafull : std_logic; -signal wrrstbusy : std_logic; -signal rdrstbusy : std_logic; +signal fifofull : std_logic; -- @suppress +signal fifoempty : std_logic; -- @suppress +signal fifoafull : std_logic; -- @suppress +signal wrrstbusy : std_logic; -- @suppress +signal rdrstbusy : std_logic; -- @suppress begin diff --git a/simulation/UVVMExample/tb/crc20_datagen.vhd b/simulation/UVVMExample/tb/crc20_datagen.vhd index 3c104fab2ccc55c42c1fb132a14ba57ae69d7bb5..1722f9b3155621d7e9e5e005ac2d56b677d6f006 100644 --- a/simulation/UVVMExample/tb/crc20_datagen.vhd +++ b/simulation/UVVMExample/tb/crc20_datagen.vhd @@ -25,8 +25,8 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; -use ieee.STD_LOGIC_ARITH.all; -use ieee.STD_LOGIC_UNSIGNED.all; +use ieee.STD_LOGIC_ARITH.all;-- @suppress "Deprecated package" +use ieee.STD_LOGIC_UNSIGNED.all;-- @suppress "Deprecated package" library uvvm_util; context uvvm_util.uvvm_util_context; @@ -53,8 +53,8 @@ datagen_proc: process(clk) variable packageLength: integer range 0 to 10000; variable idleLength: integer range 0 to 10000; - variable rnd: integer range 0 to 1000; - constant C_SCOPE : string := C_TB_SCOPE_DEFAULT; + --variable rnd: integer range 0 to 1000; + --constant C_SCOPE : string := C_TB_SCOPE_DEFAULT; begin if rising_edge(clk) then diff --git a/simulation/UVVMExample/tb/crc20_tb.vhd b/simulation/UVVMExample/tb/crc20_tb.vhd index f710240c42051d0fcf3aa7a9a2d20ef3afadb3b8..e2595ceed67d28adf4f1d5714e75ab006b4196da 100644 --- a/simulation/UVVMExample/tb/crc20_tb.vhd +++ b/simulation/UVVMExample/tb/crc20_tb.vhd @@ -23,7 +23,6 @@ use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; - library STD; use std.env.all; library uvvm_util; @@ -59,18 +58,18 @@ ----------------------------------------------------------------------------- -- Instantiate DUT ----------------------------------------------------------------------------- - crc20: entity work.crc - generic map( - Nbits => 32, - CRC_Width => 20, - G_Poly => x"8359f", - G_InitVal => x"fffff" - ) + crc20: entity work.CRC + --generic map( + -- Nbits => 32, + -- CRC_Width => 20, + -- G_Poly => x"8359f", + -- G_InitVal => x"fffff" + -- ) port map( CRC => crc_result, Calc => crc_calc, Clk => clk250, - DIn => data, + Din => data, Reset => sop); datagen: entity work.crc20_datagen diff --git a/simulation/Wupper/wupper_tb.vhd b/simulation/Wupper/wupper_tb.vhd index 2ada120c5993e185ba0673cd4e0db6232733f9b0..e30e206507ea6d9ad122e825efc7ddc05f0bb75d 100644 --- a/simulation/Wupper/wupper_tb.vhd +++ b/simulation/Wupper/wupper_tb.vhd @@ -155,7 +155,6 @@ begin NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS, NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS, BUILD_DATETIME => (others => '0'), - SVN_VERSION => 0, CARD_TYPE => 128, GIT_HASH => (others => '0'), COMMIT_DATETIME => (others => '0'), diff --git a/sources/AxisUtils/Axis32Fifo.vhd b/sources/AxisUtils/Axis32Fifo.vhd index cb490532fa574d0dc797fc0b4b8e3a0c10de4a7c..21241b56433dec89a2f8867fa227ebee405646ec 100644 --- a/sources/AxisUtils/Axis32Fifo.vhd +++ b/sources/AxisUtils/Axis32Fifo.vhd @@ -58,6 +58,7 @@ fifo: xpm_fifo_axis RD_DATA_COUNT_WIDTH => 1, PROG_FULL_THRESH => 7, PROG_EMPTY_THRESH => 253, + SIM_ASSERT_CHK => 0, CDC_SYNC_STAGES => 2 ) port map ( @@ -161,10 +162,10 @@ xpm_cdc_trunc : xpm_cdc_single SRC_INPUT_REG => 1 -- DECIMAL; integer; 0=do not register input, 1=register input ) port map ( - dest_out => s_axis_tuser_3, -- 1-bit output: src_in synchronized to the destination clock domain. This output is registered. + src_clk => s_axis_aclk, -- 1-bit input: optional; required when SRC_INPUT_REG = 1 + src_in => s_axis.tuser(3), -- 1-bit input: Input signal to be synchronized to dest_clk domain. dest_clk => m_axis_aclk, -- 1-bit input: Clock signal for the destination clock domain. - src_clk => s_axis_aclk, -- 1-bit input: optional; required when SRC_INPUT_REG = 1 - src_in => s_axis.tuser(3) -- 1-bit input: Input signal to be synchronized to dest_clk domain. + dest_out => s_axis_tuser_3 -- 1-bit output: src_in synchronized to the destination clock domain. This output is registered. ); xpm_cdc_busy : xpm_cdc_single @@ -175,10 +176,10 @@ xpm_cdc_busy : xpm_cdc_single SRC_INPUT_REG => 1 -- DECIMAL; integer; 0=do not register input, 1=register input ) port map ( - dest_out => s_axis_tuser_2, -- 1-bit output: src_in synchronized to the destination clock domain. This output is registered. + src_clk => s_axis_aclk, -- 1-bit input: optional; required when SRC_INPUT_REG = 1 + src_in => s_axis.tuser(2), -- 1-bit input: Input signal to be synchronized to dest_clk domain. dest_clk => m_axis_aclk, -- 1-bit input: Clock signal for the destination clock domain. - src_clk => s_axis_aclk, -- 1-bit input: optional; required when SRC_INPUT_REG = 1 - src_in => s_axis.tuser(2) -- 1-bit input: Input signal to be synchronized to dest_clk domain. + dest_out => s_axis_tuser_2 -- 1-bit output: src_in synchronized to the destination clock domain. This output is registered. ); diff --git a/sources/AxisUtils/Axis8Fifo.vhd b/sources/AxisUtils/Axis8Fifo.vhd index fb88187f388592e6df34690a5fc2641ef1bb6815..f49a6680c17b7233dde1caec577f938e8a20a535 100644 --- a/sources/AxisUtils/Axis8Fifo.vhd +++ b/sources/AxisUtils/Axis8Fifo.vhd @@ -72,6 +72,7 @@ xpm_fifo_gen: if USE_BUILT_IN_FIFO = false generate RD_DATA_COUNT_WIDTH => 1, PROG_FULL_THRESH => DEPTH-2, PROG_EMPTY_THRESH => 5, + SIM_ASSERT_CHK => 0, CDC_SYNC_STAGES => 2 ) port map ( diff --git a/sources/CRC20/crc.vhd b/sources/CRC20/crc.vhd index b26e23d878f5a5893c23d2562ccf162f56fd7ccb..8b2ef1ed1da80c0b3b1dabd50d44fcb8e310ce40 100644 --- a/sources/CRC20/crc.vhd +++ b/sources/CRC20/crc.vhd @@ -20,17 +20,17 @@ library ieee; use ieee.std_logic_1164.all; entity CRC is - generic( - Nbits : positive := 32; - CRC_Width : positive := 20; - G_Poly: Std_Logic_Vector :=x"8359f"; - G_InitVal: std_logic_vector:=x"fffff" - ); + --generic( + --Nbits : positive := 32; + --CRC_Width : positive := 20 + --G_Poly: Std_Logic_Vector :=x"8359f"; + --G_InitVal: std_logic_vector:=x"fffff" + -- ); port( - CRC : out std_logic_vector(CRC_Width-1 downto 0); + CRC : out std_logic_vector(19 downto 0); Calc : in std_logic; Clk : in std_logic; - DIn : in std_logic_vector(Nbits-1 downto 0); + Din : in std_logic_vector(31 downto 0); Reset : in std_logic); end CRC; diff --git a/sources/CRFromHostAxis/CRFromHostAxis.vhd b/sources/CRFromHostAxis/CRFromHostAxis.vhd index a7853846d6581d445b6c69c344d5743020c64848..1d18bbc256c3a15139abbf64de6e3b51d5ebbf19 100644 --- a/sources/CRFromHostAxis/CRFromHostAxis.vhd +++ b/sources/CRFromHostAxis/CRFromHostAxis.vhd @@ -42,8 +42,8 @@ architecture rtl of CRFromHostAxis is signal fromHostFifo_wait : std_logic; signal fromHostFifo_valid : std_logic; - signal upstreamFifoPfull : std_logic_vector(0 to GBT_NUM-1); - signal upstreamFifoPfull_ored : std_logic; + --signal upstreamFifoPfull : std_logic_vector(0 to GBT_NUM-1); + --signal upstreamFifoPfull_ored : std_logic; signal firstPacket : std_logic_vector(255 downto 0); signal secondPacket : std_logic_vector(255 downto 0); @@ -216,10 +216,10 @@ begin linkFifo_rden => linkFifo_rden(GBT), linkFifo_valid => linkFifo_valid(GBT), linkFifo_empty => linkFifo_empty(GBT), - broadcastEnable => register_map_control.BROADCAST_ENABLE(GBT)(STREAMS_PER_LINK_FROMHOST-1 downto 0), fhAxis_aclk => fhAxis_aclk, fhAxis => channelFhAxis, - fhAxis_tready => channelFhAxis_tready + fhAxis_tready => channelFhAxis_tready, + broadcastEnable => register_map_control.BROADCAST_ENABLE(GBT)(STREAMS_PER_LINK_FROMHOST-1 downto 0) ); end generate; diff --git a/sources/CRFromHostAxis/CRFromHostDataManagerAxis.vhd b/sources/CRFromHostAxis/CRFromHostDataManagerAxis.vhd index 13ead1ac73cddba821e8aa29511ccfbe485ca632..8ebb809a149a381d50b5fc625c0847733fa9dcaa 100644 --- a/sources/CRFromHostAxis/CRFromHostDataManagerAxis.vhd +++ b/sources/CRFromHostAxis/CRFromHostDataManagerAxis.vhd @@ -54,7 +54,7 @@ architecture rtl of CRFromHostDataManagerAxis is if i = x then return offs; end if; - offs := offs + GROUP_CONFIG(I); + offs := offs + GROUP_CONFIG(i); end loop; return -1; -- group not found end function; @@ -94,8 +94,8 @@ architecture rtl of CRFromHostDataManagerAxis is signal groupFifo_dout : groupFifo_dout_array(0 to get_group_num(GROUP_CONFIG)-1); signal groupFifo_wren : std_logic_vector(0 to get_group_num(GROUP_CONFIG)-1); signal groupFifo_rden : std_logic_vector(0 to get_group_num(GROUP_CONFIG)-1); - signal groupFifo_valid : std_logic_vector(0 to get_group_num(GROUP_CONFIG)-1); - signal groupFifo_full : std_logic_vector(0 to get_group_num(GROUP_CONFIG)-1); + --signal groupFifo_valid : std_logic_vector(0 to get_group_num(GROUP_CONFIG)-1); + --signal groupFifo_full : std_logic_vector(0 to get_group_num(GROUP_CONFIG)-1); signal groupFifo_pfull : std_logic_vector(0 to get_group_num(GROUP_CONFIG)-1); signal groupFifo_empty : std_logic_vector(0 to get_group_num(GROUP_CONFIG)-1); signal groupFifo_pfull_ored : std_logic; @@ -152,10 +152,10 @@ groupFifos: for I in 0 to get_group_num(GROUP_CONFIG)-1 generate dout => groupFifo_dout(I), wren => groupFifo_wren(I), rden => groupFifo_rden(I), - valid => groupFifo_valid(I), - full => groupFifo_full(I), - pfull => groupFifo_pfull(I), - empty => groupFifo_empty(I) + valid => open, --groupFifo_valid(I), + full => open, --groupFifo_full(I), + empty => groupFifo_empty(I), + pfull => groupFifo_pfull(I) ); end generate; diff --git a/sources/CRFromHostAxis/CRFromHostGroupFifo.vhd b/sources/CRFromHostAxis/CRFromHostGroupFifo.vhd index 8099f04bd667f906b14a52e9de3bc7e1aa446266..c66ce5e3c81933b136a69ee8ac5a812e698f9020 100644 --- a/sources/CRFromHostAxis/CRFromHostGroupFifo.vhd +++ b/sources/CRFromHostAxis/CRFromHostGroupFifo.vhd @@ -96,48 +96,49 @@ fifo_dout(255 downto 240) when 15; -- XPM macro fifo: xpm_fifo_sync generic map ( - DOUT_RESET_VALUE => "0", - ECC_MODE => "no_ecc", FIFO_MEMORY_TYPE => "distributed", - FIFO_READ_LATENCY => 0, FIFO_WRITE_DEPTH => DEPTH, + WRITE_DATA_WIDTH => 256, + READ_MODE => "fwft", + FIFO_READ_LATENCY => 0, FULL_RESET_VALUE => 0, - PROG_EMPTY_THRESH => 10, + USE_ADV_FEATURES => "0002", + READ_DATA_WIDTH => 256, + WR_DATA_COUNT_WIDTH => 1, PROG_FULL_THRESH => PROG_FULL_THRESHOLD, RD_DATA_COUNT_WIDTH => 1, - READ_DATA_WIDTH => 256, - READ_MODE => "fwft", - USE_ADV_FEATURES => "0002", - WAKEUP_TIME => 0, - WRITE_DATA_WIDTH => 256, - WR_DATA_COUNT_WIDTH => 1 + PROG_EMPTY_THRESH => 10, + DOUT_RESET_VALUE => "0", + ECC_MODE => "no_ecc", + SIM_ASSERT_CHK => 0, + WAKEUP_TIME => 0 ) port map ( - almost_empty => open, + sleep => '0', + rst => areset, + wr_clk => clk, + wr_en => fifo_wren, + din => fifo_din, + full => fifo_full, + prog_full => fifo_pfull, + wr_data_count => open, + overflow => open, + wr_rst_busy => open, almost_full => open, - data_valid => open, - dbiterr => open, + wr_ack => open, + rd_en => fifo_rden, dout => fifo_dout, empty => fifo_empty, - full => fifo_full, - overflow => open, prog_empty => open, - prog_full => fifo_pfull, rd_data_count => open, - rd_rst_busy => open, - sbiterr => open, underflow => open, - wr_ack => open, - wr_data_count => open, - wr_rst_busy => open, - din => fifo_din, - injectdbiterr => '0', + rd_rst_busy => open, + almost_empty => open, + data_valid => open, injectsbiterr => '0', - rd_en => fifo_rden, - rst => areset, - sleep => '0', - wr_clk => clk, - wr_en => fifo_wren + injectdbiterr => '0', + sbiterr => open, + dbiterr => open ); diff --git a/sources/CRFromHostAxis/CRFromHostLinkFifo.vhd b/sources/CRFromHostAxis/CRFromHostLinkFifo.vhd index a723cef0f3c4791c64dc99547e4e45bf95a1ddf6..c61b7930b7144a80d327d6bd650992513cf53afc 100644 --- a/sources/CRFromHostAxis/CRFromHostLinkFifo.vhd +++ b/sources/CRFromHostAxis/CRFromHostLinkFifo.vhd @@ -56,48 +56,49 @@ dout <= fifo_dout; -- XPM macro fifo: xpm_fifo_sync generic map ( - DOUT_RESET_VALUE => "0", - ECC_MODE => "no_ecc", FIFO_MEMORY_TYPE => "block", - FIFO_READ_LATENCY => 1, FIFO_WRITE_DEPTH => DEPTH, + WRITE_DATA_WIDTH => 256, + READ_MODE => "std", + FIFO_READ_LATENCY => 1, FULL_RESET_VALUE => 0, - PROG_EMPTY_THRESH => 10, + USE_ADV_FEATURES => "0002", + READ_DATA_WIDTH => 256, + WR_DATA_COUNT_WIDTH => 1, PROG_FULL_THRESH => PROG_FULL_THRESHOLD, RD_DATA_COUNT_WIDTH => 1, - READ_DATA_WIDTH => 256, - READ_MODE => "std", - USE_ADV_FEATURES => "0002", - WAKEUP_TIME => 0, - WRITE_DATA_WIDTH => 256, - WR_DATA_COUNT_WIDTH => 1 + PROG_EMPTY_THRESH => 10, + DOUT_RESET_VALUE => "0", + ECC_MODE => "no_ecc", + SIM_ASSERT_CHK => 0, + WAKEUP_TIME => 0 ) port map ( - almost_empty => open, + sleep => '0', + rst => areset, + wr_clk => clk, + wr_en => fifo_wren, + din => fifo_din, + full => fifo_full, + prog_full => fifo_pfull, + wr_data_count => open, + overflow => open, + wr_rst_busy => open, almost_full => open, - data_valid => open, - dbiterr => open, + wr_ack => open, + rd_en => fifo_rden, dout => fifo_dout, empty => fifo_empty, - full => fifo_full, - overflow => open, prog_empty => open, - prog_full => fifo_pfull, rd_data_count => open, - rd_rst_busy => open, - sbiterr => open, underflow => open, - wr_ack => open, - wr_data_count => open, - wr_rst_busy => open, - din => fifo_din, - injectdbiterr => '0', + rd_rst_busy => open, + almost_empty => open, + data_valid => open, injectsbiterr => '0', - rd_en => fifo_rden, - rst => areset, - sleep => '0', - wr_clk => clk, - wr_en => fifo_wren + injectdbiterr => '0', + sbiterr => open, + dbiterr => open ); diff --git a/sources/CRFromHostAxis/CRFromHostTransferManager.vhd b/sources/CRFromHostAxis/CRFromHostTransferManager.vhd index 3ad6dec26473c838d12afdffca0c564f65650846..519735d40cfce3b987a3f5f88e7d584deba69769 100644 --- a/sources/CRFromHostAxis/CRFromHostTransferManager.vhd +++ b/sources/CRFromHostAxis/CRFromHostTransferManager.vhd @@ -24,7 +24,7 @@ entity CRFromHostTransferManager is end CRFromHostTransferManager; architecture rtl of CRFromHostTransferManager is - constant ADDR_BITS_STREAM : integer := integer(ceil(log2(real(STREAMS_PER_GROUP_FROMHOST)))); + --constant ADDR_BITS_STREAM : integer := integer(ceil(log2(real(STREAMS_PER_GROUP_FROMHOST)))); signal message_len : integer range 0 to 30; signal last_block : std_logic; signal byte_cnt : integer range 0 to 31; @@ -78,7 +78,7 @@ begin end process; -- fanout streams -stream_fanout_mux: process (stream, stream_sel, stream_out_tready) +stream_fanout_mux: process (stream, stream_sel, stream_out_tready, broadcastEnable, broadcast_acked) variable tready_anded : std_logic; begin if stream_sel = STREAMS_PER_GROUP_FROMHOST then diff --git a/sources/CRToHost/CRToHost.vhd b/sources/CRToHost/CRToHost.vhd index f0ab63f5ecdfe7529aa0d990efad1bcf6b9b1378..56505688a87a3df64182fbb32a3f4169fbf9be15 100644 --- a/sources/CRToHost/CRToHost.vhd +++ b/sources/CRToHost/CRToHost.vhd @@ -38,7 +38,7 @@ port ( ----- register_map_control : in register_map_control_type; --! configuration settings, 64 bit per EGROUP (7 EGROUPS total) register_map_xoff_monitor : out register_map_xoff_monitor_type; - register_map_crtohost_monitor : out register_map_crtohost_monitor_type; + register_map_crtohost_monitor : out register_map_crtohost_monitor_type; -- @suppress "Unused port: register_map_crtohost_monitor is not used in work.CRToHost(Behavioral)" interrupt_call : out std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4); -- decoding side s_axis : in axis_32_2d_array_type(0 to GBT_NUM-1, 0 to STREAMS_TOHOST-1); @@ -174,7 +174,8 @@ generic map( epathID => 3, generate_IC_EC_TTC_only => false, TimeoutCounterBitNum => 12, -- IG: number of timeout counter bits - DATA_WIDTH => DATA_WIDTH + DATA_WIDTH => DATA_WIDTH, + BLOCKSIZE => BLOCKSIZE ) port map( clk40 => clk40, @@ -196,9 +197,9 @@ port map( FIFOhasBlock => chFifo_hasBlock_array(GBT_NUM), FIFOre => chFifo_re_array(GBT_NUM), FIFOempty => open, - FIFOdvalid => chFifo_dvalid_array(GBT_NUM), + FIFOdvalid => chFifo_dvalid_array(GBT_NUM) ----- - xoff_in => croutfifo_full + --xoff_in => croutfifo_full ); ------------------------------------------------------------ diff --git a/sources/CRToHost/CRToHostPCIeManager.vhd b/sources/CRToHost/CRToHostPCIeManager.vhd index a177ab87013b4cd2c0aa59275af0bc4d0b68d386..d6db54184653121cb4d78825f0b6ca702eecd435 100644 --- a/sources/CRToHost/CRToHostPCIeManager.vhd +++ b/sources/CRToHost/CRToHostPCIeManager.vhd @@ -10,7 +10,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all; -- @suppress "Deprecated package" +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use work.all; use work.centralRouter_package.all; @@ -86,7 +86,17 @@ thch_rdy_array_full((GBT_NUM-1) downto 0) <= thch_rdy_array; -- GBT_NUM bit thch_rdy <= thch_rdy_array_full(to_integer(unsigned(FMCHcount(5 downto 1)))); thch_rdy_s <= thch_rdy and (not FMCHcount(0)) and (not rst_state) and PCIe_ena; -thch_rdy_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk, thch_rdy_s, thch_rdy_1clk); +thch_rdy_pulse: entity work.pulse_pdxx_pwxx +generic map( + pd=>0, + pw=>1 +) +port map( + clk => clk, + trigger => thch_rdy_s, + pulseout => thch_rdy_1clk +); + -- g_256: if DATA_WIDTH = 256 generate block_done <= '1' when (BLOCKcount = NUMBER_OF_256_PER_BLOCK) else '0'; -- 1KByte = 256 x 32 diff --git a/sources/CRToHost/CRToHostdm.vhd b/sources/CRToHost/CRToHostdm.vhd index 0448e1531671fad05526b085f360c35ef4ae4a66..5c033b3cde294024d1be1232c512b15f86b7ec37 100644 --- a/sources/CRToHost/CRToHostdm.vhd +++ b/sources/CRToHost/CRToHostdm.vhd @@ -10,7 +10,7 @@ library IEEE; use IEEE.std_logic_1164.ALL; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all; -- @suppress "Deprecated package" +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use work.all; use work.pcie_package.all; use work.centralRouter_package.all; @@ -166,46 +166,52 @@ begin chFIFO : xpm_fifo_async generic map ( - FIFO_MEMORY_TYPE => "auto", --string; "auto", "block", or "distributed"; - ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc"; - RELATED_CLOCKS => 0, --positive integer; 0 or 1 - FIFO_WRITE_DEPTH => FIFO_DEPTH, --positive integer - WRITE_DATA_WIDTH => 32, --positive integer - WR_DATA_COUNT_WIDTH => FIFO_COUNT_WIDTH, --positive integer - PROG_FULL_THRESH => FIFO_DEPTH-4, --positive integer - FULL_RESET_VALUE => 1, --positive integer; 0 or 1; - READ_MODE => "std", --string; "std" or "fwft"; - FIFO_READ_LATENCY => 1, --positive integer; - READ_DATA_WIDTH => DATA_WIDTH, --positive integer - RD_DATA_COUNT_WIDTH => 1, --positive integer - PROG_EMPTY_THRESH => (BLOCKSIZE/(DATA_WIDTH/8))-1, --!TODO: This doesn't work for 4k blocks, use rd_data_count instead - DOUT_RESET_VALUE => "0", --string - CDC_SYNC_STAGES => 2, --positive integer - WAKEUP_TIME => 0 --positive integer; 0 or 2; + FIFO_MEMORY_TYPE => "auto", --string; "auto", "block", or "distributed"; + FIFO_WRITE_DEPTH => FIFO_DEPTH, --positive integer + RELATED_CLOCKS => 0, --positive integer; 0 or 1 + WRITE_DATA_WIDTH => 32, --positive integer + READ_MODE => "std", --string; "std" or "fwft"; + FIFO_READ_LATENCY => 1, --positive integer; + FULL_RESET_VALUE => 1, --positive integer; 0 or 1; + USE_ADV_FEATURES => "0707", + READ_DATA_WIDTH => DATA_WIDTH, --positive integer + CDC_SYNC_STAGES => 2, --positive integer + WR_DATA_COUNT_WIDTH => FIFO_COUNT_WIDTH, --positive integer + PROG_FULL_THRESH => FIFO_DEPTH-4, --positive integer + RD_DATA_COUNT_WIDTH => 1, --positive integer + PROG_EMPTY_THRESH => (BLOCKSIZE/(DATA_WIDTH/8))-1, --!TODO: This doesn't work for 4k blocks, use rd_data_count instead + DOUT_RESET_VALUE => "0", --string + ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc"; + SIM_ASSERT_CHK => 0, + WAKEUP_TIME => 0 --positive integer; 0 or 2; ) port map ( - sleep => '0', - rst => fmchFifo_flush, - wr_clk => aclk, - wr_en => chFIFO_din32_valid_s, - din => chFIFO_din32_s, - full => open, - overflow => open, - wr_rst_busy => open, - rd_clk => clk250, - rd_en => fmchFifo_re, - dout => chFIFO_dout_s, - empty => empty, - underflow => open, - rd_rst_busy => open, - prog_full => chFIFO_pfull, - wr_data_count => wr_data_count, - prog_empty => chFIFO_pempty, - rd_data_count => open, - injectsbiterr => '0', - injectdbiterr => '0', - sbiterr => open, - dbiterr => open + sleep => '0', + rst => fmchFifo_flush, + wr_clk => aclk, + wr_en => chFIFO_din32_valid_s, + din => chFIFO_din32_s, + full => open, + prog_full => chFIFO_pfull, + wr_data_count => wr_data_count, + overflow => open, + wr_rst_busy => open, + almost_full => open, + wr_ack => open, + rd_clk => clk250, + rd_en => fmchFifo_re, + dout => chFIFO_dout_s, + empty => empty, + prog_empty => chFIFO_pempty, + rd_data_count => open, + underflow => open, + rd_rst_busy => open, + almost_empty => open, + data_valid => open, + injectsbiterr => '0', + injectdbiterr => '0', + sbiterr => open, + dbiterr => open ); valid_proc: process(clk250) diff --git a/sources/CRToHost/CRresetManager.vhd b/sources/CRToHost/CRresetManager.vhd index d2db6ba0c4f35f8457936288ca9fc06ebd9f8af8..7eae11f705e339398faacfe680029293a1daa1ca 100644 --- a/sources/CRToHost/CRresetManager.vhd +++ b/sources/CRToHost/CRresetManager.vhd @@ -7,10 +7,10 @@ --! Project Name: FELIX ---------------------------------------------------------------------------------- --! Use standard library -library work, ieee; +library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use work.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" + --! entity CRresetManager is @@ -46,7 +46,7 @@ begin else rstTimerCount <= rstTimerCount + 1; end if; - end if; + end if; end process; -- cr_rst_out: process(clk40,rst) diff --git a/sources/CRToHost/MUXn.vhd b/sources/CRToHost/MUXn.vhd index 2910063028a1e383a65d4d79409a98c98dee9a03..404661ed81e9bd4412febd989f2043305de78ef4 100644 --- a/sources/CRToHost/MUXn.vhd +++ b/sources/CRToHost/MUXn.vhd @@ -9,7 +9,6 @@ --! Use standard library library ieee; use ieee.std_logic_1164.ALL; -use ieee.std_logic_unsigned.ALL; use ieee.numeric_std.all; use work.centralRouter_package.all; use work.pcie_package.all; diff --git a/sources/CRToHost/ReMuxN.vhd b/sources/CRToHost/ReMuxN.vhd index 187c773c40a7dffdb98aef07ad7f5a28faf0bb7b..b6cbf9922d3cb137b32b9625f7319dca02b52a23 100644 --- a/sources/CRToHost/ReMuxN.vhd +++ b/sources/CRToHost/ReMuxN.vhd @@ -9,7 +9,6 @@ --! Use standard library library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity ReMuxN is diff --git a/sources/CRToHost/ToHostAxiStreamController.vhd b/sources/CRToHost/ToHostAxiStreamController.vhd index 588c004dabf8d0f2fb52a5ac7cc3d2a94ea2a716..7588458895257b3af61d30b0214ca28c653fc5e1 100644 --- a/sources/CRToHost/ToHostAxiStreamController.vhd +++ b/sources/CRToHost/ToHostAxiStreamController.vhd @@ -9,7 +9,7 @@ --! Use standard library library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -- @suppress "Deprecated package" +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use ieee.numeric_std.all; use work.all; use work.centralRouter_package.all; @@ -176,11 +176,13 @@ end process; --This process counts a 40MHz timeout counter, but in the 240MHz (or 250MHz) domain. timeout_cnt: process(aclk, reset) variable cnt6 : std_logic_vector(2 downto 0); + variable timeOutEna_i_v : std_logic; begin if(reset = '1') then cnt6 := (others => '0'); timeOutCnt <= (others => '0'); timeout_pulse <= '0'; + timeOutEna_i_v := '0'; elsif rising_edge(aclk) then timeout_pulse <= '0'; if (cnt6 < 5) then @@ -191,9 +193,10 @@ begin timeOutCnt <= timeOutCnt + 1; else timeOutCnt <= (others => '0'); - timeout_pulse <= '1'; + timeout_pulse <= timeOutEna_i_v; end if; end if; + timeOutEna_i_v := timeOutEna_i; end if; end process; @@ -228,7 +231,7 @@ toblock: process(aclk) variable chunkCounter : std_logic_vector (15 downto 0); --counts the length in the chunk, both for trailer generation and truncation variable create_trailer, create_zero_trailer, create_timeout_trailer : std_logic; - variable trunc , end_truncation: std_logic; + variable trunc: std_logic; variable trailerType : std_logic_vector(2 downto 0); variable first_subchunk, last_subchunk : std_logic_vector(STREAMS_TOHOST-1 downto 0); variable stream_select_v: integer range 0 to STREAMS_TOHOST; diff --git a/sources/Endeavour/EndeavourDecoder.vhd b/sources/Endeavour/EndeavourDecoder.vhd index 0fa92be6404d7f666aa3df18c60eb0320c68c935..05db3a805e00a97739024d5032ac715aef0369b4 100644 --- a/sources/Endeavour/EndeavourDecoder.vhd +++ b/sources/Endeavour/EndeavourDecoder.vhd @@ -22,8 +22,8 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.axi_stream_package.all; use ieee.numeric_std.all; -use ieee.STD_LOGIC_ARITH.all; -use ieee.STD_LOGIC_UNSIGNED.all; +use ieee.STD_LOGIC_ARITH.all;-- @suppress "Deprecated package" +use ieee.STD_LOGIC_UNSIGNED.all;-- @suppress "Deprecated package" use work.pcie_package.all; use work.centralRouter_package.all; @@ -45,23 +45,23 @@ architecture Behavioral of EndeavourDecoder is -------- the number of clock are half respect to the encoder for the lenght reduction done by the deglitcher - constant TICKS_QUIESCENT : integer := 100; + --constant TICKS_QUIESCENT : integer := 100; constant TICKS_DIT_MIN : integer := 6; -- bit0 min constant TICKS_DIT_MAX : integer := 22; -- bit0 max - constant TICKS_DIT_MID : integer := (TICKS_DIT_MIN + TICKS_DIT_MAX)/2; --bit0 + --constant TICKS_DIT_MID : integer := (TICKS_DIT_MIN + TICKS_DIT_MAX)/2; --bit0 constant TICKS_DAH_MIN : integer := 30; --bit1 min constant TICKS_DAH_MAX : integer := 124; --bit1 max - constant TICKS_DAH_MID : integer := (TICKS_DAH_MIN + TICKS_DAH_MAX)/2; --bit1 - constant TICKS_BITGAP_MIN : integer := 11; -- intraword gap min + --constant TICKS_DAH_MID : integer := (TICKS_DAH_MIN + TICKS_DAH_MAX)/2; --bit1 + --constant TICKS_BITGAP_MIN : integer := 11; -- intraword gap min constant TICKS_BITGAP_MAX : integer := 75; -- intraword gap max - constant TICKS_BITGAP_MID : integer := (TICKS_BITGAP_MIN + TICKS_BITGAP_MAX)/2; -- intraword gap + --constant TICKS_BITGAP_MID : integer := (TICKS_BITGAP_MIN + TICKS_BITGAP_MAX)/2; -- intraword gap type fsm_rd_t is (idle, waitbit, readbit, waitgap, secondword); --, intertransactgap); signal fsm_rd : fsm_rd_t := idle; - type fsm_wr_t is (idle, waitfifo, writedata); - signal fsm_wr : fsm_wr_t := idle; + --type fsm_wr_t is (idle, waitfifo, writedata); + --signal fsm_wr : fsm_wr_t := idle; signal s_axis : axis_32_type; signal s_axis_tready : std_logic; @@ -71,10 +71,10 @@ architecture Behavioral of EndeavourDecoder is signal reg_dataout : std_logic_vector(63 downto 0) := (others => '0'); - signal datavalid, readrq, fifofull, fifoempty, fifoafull: std_logic; + --signal datavalid, readrq, fifofull, fifoempty, fifoafull: std_logic; - signal datatofifo : std_logic_vector(39 downto 0) := (others => '0'); - signal fifodataout : std_logic_vector(39 downto 0) := (others => '0'); + --signal datatofifo : std_logic_vector(39 downto 0) := (others => '0'); + --signal fifodataout : std_logic_vector(39 downto 0) := (others => '0'); begin diff --git a/sources/Endeavour/EndeavourDeglitcher.vhd b/sources/Endeavour/EndeavourDeglitcher.vhd index 21ce157b3d82d1af2076c0f0a198ac11a43d8877..7fb875970a9413d2f6b7b3cefbf8e76d77088121 100644 --- a/sources/Endeavour/EndeavourDeglitcher.vhd +++ b/sources/Endeavour/EndeavourDeglitcher.vhd @@ -19,12 +19,12 @@ ---------------------------------------------------------------------------------- -library work, IEEE; +library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.axi_stream_package.all; use ieee.numeric_std.all; -use ieee.STD_LOGIC_ARITH.all; -use ieee.STD_LOGIC_UNSIGNED.all; +use ieee.STD_LOGIC_ARITH.all;-- @suppress "Deprecated package" +use ieee.STD_LOGIC_UNSIGNED.all;-- @suppress "Deprecated package" use work.pcie_package.all; use work.centralRouter_package.all; @@ -41,13 +41,13 @@ end EndeavourDeglitcher; architecture Behavioral of EndeavourDeglitcher is -constant BIGGAP : std_logic_vector(7 downto 0) := X"30"; +--constant BIGGAP : std_logic_vector(7 downto 0) := X"30"; signal datain_state : std_logic := '0'; signal onecount : std_logic_vector(3 downto 0); begin -deglitch : process(clk40, aresetn) +deglitch : process(clk40) ----- the process filters the gliches on the 2 bit line and it transfors the signal from 2 bit to 1 bit mantaing the same clock frequensy and so reducing to half the length signal ----- (indeed in the decoder all the clock lenght are half of the one in the encoder). A counter increas when on the line there is a 11 and decrease with a 00; 01 and 10 are considered neutral ----- 2 thresholds of 7 and 1 are considered to transmit respectively a 1 and a 0 diff --git a/sources/Endeavour/EndeavourEncoder.vhd b/sources/Endeavour/EndeavourEncoder.vhd index 3f6cb814323a092b3f60a0cca32a5c871d25b13f..fb077654e920d68be0f94bd6131bb9d2664aebb3 100644 --- a/sources/Endeavour/EndeavourEncoder.vhd +++ b/sources/Endeavour/EndeavourEncoder.vhd @@ -23,8 +23,8 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.axi_stream_package.all; use ieee.numeric_std.all; -use ieee.STD_LOGIC_ARITH.all; -use ieee.STD_LOGIC_UNSIGNED.all; +use ieee.STD_LOGIC_ARITH.all;-- @suppress "Deprecated package" +use ieee.STD_LOGIC_UNSIGNED.all;-- @suppress "Deprecated package" use work.pcie_package.all; use work.centralRouter_package.all; @@ -57,12 +57,11 @@ architecture Behavioral of EndeavourEncoder is type fsm_wr_t is (biggap, idle, waitword, startsend, sendbit_zero, sendbit_one, smallgap); --, intertransactgap); signal fsm_wr : fsm_wr_t := biggap; -type fsm_rd_t is (idle, readdata); -signal fsm_rd : fsm_rd_t := idle; -signal m_axis, m_axisbis, s_axis_in, m_axis_out : axis_8_type; -signal m_axis_tready, write_enable, readrq, fifofull, fifoempty, fifoafull, error_sig, error2_sig, serialout, s_axisbis_tready : std_logic; -signal datain, dataout, nmaxwords, nwordsent: std_logic_vector(7 downto 0) := (others => '0'); - +--type fsm_rd_t is (idle, readdata); +--signal fsm_rd : fsm_rd_t := idle; +signal m_axis, s_axis_in, m_axis_out : axis_8_type; +signal m_axis_tready, error_sig, error2_sig, serialout : std_logic; -- @suppress "signal error_sig is never read" -- @suppress "signal error2_sig is never read" +signal nwordsent, nmaxwords : std_logic_vector (7 downto 0); begin @@ -94,7 +93,7 @@ fifoaxi8: entity work.Axis8Fifo -- endev_encod_proc: process (clk40) variable ntranfbit : integer range -1 to 15 := 8; - variable writebit : std_logic; + --variable writebit : std_logic; variable counter : integer range 0 to 1023 := 0; begin if rising_edge(clk40) then diff --git a/sources/Endeavour/EndeavourInterface.vhd b/sources/Endeavour/EndeavourInterface.vhd index 11f517b5a423c94e859a1e283ebd368aa3641a80..97b1919dc25779321c7c08ac31223c151d62fa84 100644 --- a/sources/Endeavour/EndeavourInterface.vhd +++ b/sources/Endeavour/EndeavourInterface.vhd @@ -24,7 +24,7 @@ use IEEE.STD_LOGIC_1164.ALL; use work.axi_stream_package.all; use work.centralRouter_package.all; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all; +--use ieee.std_logic_unsigned.all; use work.pcie_package.all; use work.FELIX_gbt_package.all; @@ -88,7 +88,8 @@ begin aresetn => aresetn, s_axis => s_axis, --s_axis(i,0), s_axis_tready => s_axis_tready, --s_axis_tready(i,0), - amac_signal => toAMACsignal + amac_signal => toAMACsignal, + almost_full => open ); end Behavioral; diff --git a/sources/FanoutSelectors/axis_32_fanout_selector.vhd b/sources/FanoutSelectors/axis_32_fanout_selector.vhd index e810f3da0ea426bd5bfbe36c31c5c81ddeb04198..5838dd9d1a3befd6c4e5f7e2e3ecea11b0e42390 100644 --- a/sources/FanoutSelectors/axis_32_fanout_selector.vhd +++ b/sources/FanoutSelectors/axis_32_fanout_selector.vhd @@ -2,10 +2,9 @@ -library ieee, UNISIM, work; +library ieee, UNISIM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; use work.pcie_package.all; use work.axi_stream_package.all; @@ -16,7 +15,6 @@ entity axis_32_fanout_selector is STREAMS_TOHOST : integer := 1); port ( aclk : in std_logic; - aresetn : in std_logic; emu_axis : in axis_32_2d_array_type(0 to GBT_NUM-1, 0 to STREAMS_TOHOST-1); emu_axis_tready : out axis_tready_2d_array_type(0 to GBT_NUM-1, 0 to STREAMS_TOHOST-1); emu_axis_prog_empty : in axis_tready_2d_array_type(0 to GBT_NUM-1, 0 to STREAMS_TOHOST-1); @@ -73,7 +71,7 @@ begin end if; end process; - tvalid_fanout: process(fanout_sel_axis_tready, fanout_sel_axis_s, fosel_aclk) + tvalid_fanout: process(fanout_sel_axis_s) begin for i in 0 to GBT_NUM-1 loop for j in 0 to STREAMS_TOHOST-1 loop diff --git a/sources/FelixTop/felix_top.vhd b/sources/FelixTop/felix_top.vhd index ec3859b4113c79c839588a048af61d532e2bb763..fddcfe481834b09cf2439ce4e6cc99f3f671567f 100644 --- a/sources/FelixTop/felix_top.vhd +++ b/sources/FelixTop/felix_top.vhd @@ -243,7 +243,7 @@ architecture structure of felix_top is signal BUSY_REQUESTs : busyOut_array_type(0 to (GBT_NUM-1)); signal TTC_ToHost_Data : TTC_ToHost_data_type; - signal cdrlocked_out : std_logic; + --signal cdrlocked_out : std_logic; signal lnk_up : std_logic_vector(1 downto 0); signal dma_busy_arr : std_logic_vector(ENDPOINTS-1 downto 0); @@ -337,7 +337,7 @@ begin MMCM_OscSelect_out => MMCM_OscSelect_out, app_clk_in_n => app_clk_in_n, app_clk_in_p => app_clk_in_p, - cdrlocked_in => cdrlocked_out, + --cdrlocked_in => cdrlocked_out, clk10_xtal => clk10_xtal,--open, clk160 => clk160, clk240 => clk240, @@ -435,7 +435,6 @@ begin NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS, NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS, BUILD_DATETIME => BUILD_DATETIME, - SVN_VERSION => 0, CARD_TYPE => CARD_TYPE, GIT_HASH => GIT_HASH, COMMIT_DATETIME => COMMIT_DATETIME, @@ -759,7 +758,6 @@ begin ) port map( aclk => decoding_aclk, - aresetn => aresetn, emu_axis => emu_axis, emu_axis_tready => emu_axis_tready, emu_axis_prog_empty => emu_axis_prog_empty, @@ -806,7 +804,7 @@ begin IncludeDecodingEpath4_8b10b => IncludeDecodingEpath4_8b10b, IncludeDecodingEpath8_8b10b => IncludeDecodingEpath8_8b10b, IncludeDecodingEpath16_8b10b => IncludeDecodingEpath16_8b10b, - IncludeDecodingEpath32_8b10b => IncludeDecodingEpath32_8b10b, + --IncludeDecodingEpath32_8b10b => IncludeDecodingEpath32_8b10b, IncludeEncodingEpath2_HDLC => IncludeEncodingEpath2_HDLC, IncludeEncodingEpath2_8b10b => IncludeEncodingEpath2_8b10b, IncludeEncodingEpath4_8b10b => IncludeEncodingEpath4_8b10b, @@ -844,7 +842,7 @@ begin clk40 => clk40, --MT added leds => leds, opto_inhibit => opto_inhibit, - opto_los => OPTO_LOS, + --opto_los => OPTO_LOS, register_map_control => global_register_map_control_appreg_clk, register_map_gen_board_info => register_map_gen_board_info, register_map_hk_monitor => register_map_hk_monitor, @@ -880,7 +878,7 @@ begin DATA_TTC_N => DATA_TTC_N, LOL_ADN => LOL_ADN, LOS_ADN => LOS_ADN, - RESET_N => sys_reset_n, + --RESET_N => sys_reset_n, register_map_control => global_register_map_40_control, register_map_ttc_monitor => register_map_ttc_monitor, TTC_out => TTC_path, @@ -888,7 +886,7 @@ begin clk_ttc_40 => clk_ttc_40_s, clk40 => clk40, BUSY => open, - cdrlocked_out => cdrlocked_out, + cdrlocked_out => open, TTC_ToHost_Data_out => TTC_ToHost_Data, TTC_BUSY_mon_array => ttc_TTC_BUSY_mon_array, BUSY_IN => BUSY_OUT_s); diff --git a/sources/FullModeDataEmulator/FullModeDataEmulator.vhd b/sources/FullModeDataEmulator/FullModeDataEmulator.vhd index 2c32e06845a7f2166495af3ea704b236797c2937..c08796f21fc419bc914e9faa1f68c05903276f98 100644 --- a/sources/FullModeDataEmulator/FullModeDataEmulator.vhd +++ b/sources/FullModeDataEmulator/FullModeDataEmulator.vhd @@ -7,10 +7,10 @@ --! Project Name: FELIX ---------------------------------------------------------------------------------- --! Use standard library -library work, IEEE; +library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use work.pcie_package.all; use work.centralRouter_package.all; use work.axi_stream_package.all; @@ -73,7 +73,7 @@ begin -- reset state --------------------------------------------------------------------------------------- -- -rst_sync: process(clk240,aresetn) +rst_sync: process(clk240) begin if rising_edge (clk240) then reset_state <= aresetn; diff --git a/sources/FullModeWrapper/FELIX_FM_gbt_wrapper.vhd b/sources/FullModeWrapper/FELIX_FM_gbt_wrapper.vhd index ddf978b9cddd3e1326842a4bc241006dda5316cd..95bb82deb85329111ea1d4203029f48a2755e083 100644 --- a/sources/FullModeWrapper/FELIX_FM_gbt_wrapper.vhd +++ b/sources/FullModeWrapper/FELIX_FM_gbt_wrapper.vhd @@ -20,8 +20,8 @@ ---------------------------------------------------------------------------------- LIBRARY IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_ARITH.ALL;-- @suppress "Deprecated package" +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. @@ -112,11 +112,11 @@ architecture Behavioral of FELIX_FM_gbt_wrapper is type data20barray is array (0 to GBT_NUM-1) of std_logic_vector(19 downto 0); signal TX_DATA_20b : data20barray := (others => ("00000000000000000000")); - signal SOFT_TXRST_GT :std_logic_vector(23 downto 0); - signal SOFT_RXRST_GT :std_logic_vector(23 downto 0); + --signal SOFT_TXRST_GT :std_logic_vector(23 downto 0); + --signal SOFT_RXRST_GT :std_logic_vector(23 downto 0); signal SOFT_TXRST_ALL :std_logic_vector(5 downto 0); signal SOFT_RXRST_ALL :std_logic_vector(5 downto 0); - signal TX_OPT :std_logic_vector(95 downto 0); + --signal TX_OPT :std_logic_vector(95 downto 0); signal DATA_TXFORMAT :std_logic_vector(47 downto 0); signal DATA_TXFORMAT_i :std_logic_vector(47 downto 0); signal General_ctrl : std_logic_vector(63 downto 0); @@ -173,7 +173,11 @@ g_709a: if CARD_TYPE = 709 or CARD_TYPE = 710 generate g_712a: if CARD_TYPE /= 709 and CARD_TYPE /= 710 generate g_RXUSRCLK_BUFG: for i in 0 to GBT_NUM-1 generate - buf0: BUFG_GT port map( + buf0: BUFG_GT generic map( + SIM_DEVICE => "ULTRASCALE", + STARTUP_SYNC => "FALSE" + ) + port map( O => GT_RXUSRCLK(i), CE => '1', CEMASK => '0', @@ -193,6 +197,11 @@ g_709a: if CARD_TYPE = 709 or CARD_TYPE = 710 generate REFCLK_CXP2 <= CXP2_GTH_RefClk; g_709b: if CARD_TYPE = 709 or CARD_TYPE = 710 generate ibufds_instq2_clk0 : IBUFDS_GTE2 + generic map( + CLKCM_CFG => true, + CLKRCV_TRST => true, + CLKSWING_CFG => "11" + ) port map ( O => CXP1_GTH_RefClk, ODIV2 => open, @@ -202,6 +211,11 @@ g_709a: if CARD_TYPE = 709 or CARD_TYPE = 710 generate ); ibufds_instq8_clk0 : IBUFDS_GTE2 + generic map( + CLKCM_CFG => true, + CLKRCV_TRST => true, + CLKSWING_CFG => "11" + ) port map ( O => CXP2_GTH_RefClk, ODIV2 => open, @@ -408,8 +422,8 @@ g_709a: if CARD_TYPE = 709 or CARD_TYPE = 710 generate cpll_reset(23 downto 0) <= register_map_control.GBT_PLL_RESET.CPLL_RESET(23 downto 0); qpll_reset(5 downto 0) <= register_map_control.GBT_PLL_RESET.QPLL_RESET(53 downto 48) or rst_hw_23(5 downto 0); - SOFT_TXRST_GT(23 downto 0) <= register_map_control.GBT_SOFT_TX_RESET.RESET_GT(23 downto 0); - SOFT_RXRST_GT(23 downto 0) <= register_map_control.GBT_SOFT_RX_RESET.RESET_GT(23 downto 0); + --SOFT_TXRST_GT(23 downto 0) <= register_map_control.GBT_SOFT_TX_RESET.RESET_GT(23 downto 0); + --SOFT_RXRST_GT(23 downto 0) <= register_map_control.GBT_SOFT_RX_RESET.RESET_GT(23 downto 0); SOFT_TXRST_ALL(5 downto 0) <= register_map_control.GBT_SOFT_TX_RESET.RESET_ALL(53 downto 48) or rst_hw_23(5 downto 0); SOFT_RXRST_ALL(5 downto 0) <= register_map_control.GBT_SOFT_RX_RESET.RESET_ALL(53 downto 48) or rst_hw_23(5 downto 0) or RXRESET_AUTO; @@ -418,7 +432,7 @@ g_709a: if CARD_TYPE = 709 or CARD_TYPE = 710 generate TX_TC_DLY_VALUE(47 downto 0) <= register_map_control.GBT_TX_TC_DLY_VALUE1; TX_TC_DLY_VALUE(95 downto 48) <= register_map_control.GBT_TX_TC_DLY_VALUE2; - TX_OPT(47 downto 0) <= x"000000555555"; -- Register was removed in RM 4.0 register_map_control.GBT_TX_OPT; + --TX_OPT(47 downto 0) <= x"000000555555"; -- Register was removed in RM 4.0 register_map_control.GBT_TX_OPT; DATA_TXFORMAT(47 downto 0) <= register_map_control.GBT_DATA_TXFORMAT1(47 downto 0); --DATA_RXFORMAT(47 downto 0) <= register_map_control.GBT_DATA_RXFORMAT1(47 downto 0); @@ -606,8 +620,8 @@ g_709a: if CARD_TYPE = 709 or CARD_TYPE = 710 generate TX_RESET_I => TX_RESET_i(i), TX_FRAMECLK_I => TX_FRAME_CLK_I, TX_WORDCLK_I => GT_TX_WORD_CLK(i), - Tx_latopt_scr => TX_OPT(24+i), - TX_LATOPT_TC => TX_OPT(i), + --Tx_latopt_scr => TX_OPT(24+i), + --TX_LATOPT_TC => TX_OPT(i), TX_TC_METHOD => TX_TC_METHOD(i), TC_EDGE => TC_EDGE(i), DATA_MODE_CFG => DATA_TXFORMAT_i(2*i+1 downto 2*i), @@ -635,6 +649,10 @@ g_709a: if CARD_TYPE = 709 or CARD_TYPE = 710 generate g_712c: if CARD_TYPE /= 709 and CARD_TYPE /= 710 generate GTTXOUTCLK_BUFG: BUFG_GT + generic map( + SIM_DEVICE => "ULTRASCALE", + STARTUP_SYNC => "FALSE" + ) port map ( O => GT_TXUSRCLK(i), CE => '1', -- 1-bit input: Buffer enable @@ -658,9 +676,9 @@ g_709a: if CARD_TYPE = 709 or CARD_TYPE = 710 generate -- GTH RX using QPLL --------------------------------- GTH_inst: for i in (GBT_NUM-1)/4 downto 0 generate - signal SOFT_RESET_IN_g, SOFT_TXRST_ALL_g, SOFT_RXRST_ALL_g: std_logic; + signal SOFT_TXRST_ALL_g, SOFT_RXRST_ALL_g: std_logic; begin - SOFT_RESET_IN_g <= soft_reset(i) or rst_hw; + --SOFT_RESET_IN_g <= soft_reset(i) or rst_hw; SOFT_TXRST_ALL_g <= SOFT_TXRST_ALL(i) or rst_hw; SOFT_RXRST_ALL_g <= SOFT_RXRST_ALL(i) or rst_hw; @@ -676,89 +694,70 @@ g_709a: if CARD_TYPE = 709 or CARD_TYPE = 710 generate GTH_FM_TOP_INST: entity work.gth_fullmode_wrapper_v7 Port map ( ---------- Clocks - DRP_CLK_IN => DRP_CLK_IN, - GTH_RefClk => GTH_RefClk(4*i), - - gt3_rxoutclk_out => GT_RXOUTCLK(4*i+3), - gt2_rxoutclk_out => GT_RXOUTCLK(4*i+2), - gt1_rxoutclk_out => GT_RXOUTCLK(4*i+1), - gt0_rxoutclk_out => GT_RXOUTCLK(4*i), - - gt3_txoutclk_out => GT_TXOUTCLK(4*i+3), - gt2_txoutclk_out => GT_TXOUTCLK(4*i+2), - gt1_txoutclk_out => GT_TXOUTCLK(4*i+1), - gt0_txoutclk_out => GT_TXOUTCLK(4*i), - - gt3_rxusrclk_in => GT_RXUSRCLK(4*i+3), - gt2_rxusrclk_in => GT_RXUSRCLK(4*i+2), - gt1_rxusrclk_in => GT_RXUSRCLK(4*i+1), - gt0_rxusrclk_in => GT_RXUSRCLK(4*i), - - gt3_txusrclk_in => GT_TXUSRCLK(i), - gt2_txusrclk_in => GT_TXUSRCLK(i), - gt1_txusrclk_in => GT_TXUSRCLK(i), - gt0_txusrclk_in => GT_TXUSRCLK(i), - - gt_txresetdone_out => txresetdone(4*i+3 downto 4*i), - gt_rxresetdone_out => rxresetdone(4*i+3 downto 4*i), - - gt_txfsmresetdone_out => txfsmresetdone(4*i+3 downto 4*i), - gt_rxfsmresetdone_out => rxfsmresetdone(4*i+3 downto 4*i), - - gt_cpllfbclklost_out => cpllfbclklost(4*i+3 downto 4*i), - gt_cplllock_out => cplllock(4*i+3 downto 4*i), - gt_cpllreset_in => cpll_reset(4*i+3 downto 4*i), - gt_rxcdrlock_out => rxcdrlock(4*i+3 downto 4*i), - - gt0_rxdisperr_out => RxDisperr(16*i+3 downto 16*i), - gt0_rxnotintable_out => open, --RxNotIntable(16*i+3 downto 4*i), - gt1_rxdisperr_out => RxDisperr(16*i+7 downto 16*i+4), - gt1_rxnotintable_out => open, --RxNotIntable(16*i+7 downto 4*i+4), - gt2_rxdisperr_out => RxDisperr(16*i+11 downto 16*i+8), - gt2_rxnotintable_out => open, --RxNotIntable(16*i+11 downto 4*i+8), - gt3_rxdisperr_out => RxDisperr(16*i+15 downto 16*i+12), - gt3_rxnotintable_out => open, --RxNotIntable(16*i+15 downto 4*i+12), - - gt_rxbyteisaligned_out => RXByteisAligned(4*i+3 downto 4*i), - - gt_qplllock_out => qplllock(i), - + GTH_RefClk => GTH_RefClk(4*i), + DRP_CLK_IN => DRP_CLK_IN, + gt0_rxusrclk_in => GT_RXUSRCLK(4*i), + gt0_rxoutclk_out => GT_RXOUTCLK(4*i), + gt1_rxusrclk_in => GT_RXUSRCLK(4*i+1), + gt1_rxoutclk_out => GT_RXOUTCLK(4*i+1), + gt2_rxusrclk_in => GT_RXUSRCLK(4*i+2), + gt2_rxoutclk_out => GT_RXOUTCLK(4*i+2), + gt3_rxusrclk_in => GT_RXUSRCLK(4*i+3), + gt3_rxoutclk_out => GT_RXOUTCLK(4*i+3), + gt0_txusrclk_in => GT_TXUSRCLK(i), + gt0_txoutclk_out => GT_TXOUTCLK(4*i), + --gt1_txusrclk_in => GT_TXUSRCLK(i), + gt1_txoutclk_out => GT_TXOUTCLK(4*i+1), + --gt2_txusrclk_in => GT_TXUSRCLK(i), + gt2_txoutclk_out => GT_TXOUTCLK(4*i+2), + --gt3_txusrclk_in => GT_TXUSRCLK(i), + gt3_txoutclk_out => GT_TXOUTCLK(4*i+3), + gt_txresetdone_out => txresetdone(4*i+3 downto 4*i), + gt_rxresetdone_out => rxresetdone(4*i+3 downto 4*i), + gt_txfsmresetdone_out => txfsmresetdone(4*i+3 downto 4*i), + gt_rxfsmresetdone_out => rxfsmresetdone(4*i+3 downto 4*i), + gt_cpllfbclklost_out => cpllfbclklost(4*i+3 downto 4*i), + gt_cplllock_out => cplllock(4*i+3 downto 4*i), + gt_rxcdrlock_out => rxcdrlock(4*i+3 downto 4*i), + gt_qplllock_out => qplllock(i), + gt0_rxdisperr_out => RxDisperr(16*i+3 downto 16*i), + gt0_rxnotintable_out => open, --RxNotIntable(16*i+3 downto 4*i), + gt1_rxdisperr_out => RxDisperr(16*i+7 downto 16*i+4), + gt1_rxnotintable_out => open, --RxNotIntable(16*i+7 downto 4*i+4), + gt2_rxdisperr_out => RxDisperr(16*i+11 downto 16*i+8), + gt2_rxnotintable_out => open, --RxNotIntable(16*i+11 downto 4*i+8), + gt3_rxdisperr_out => RxDisperr(16*i+15 downto 16*i+12), + gt3_rxnotintable_out => open, --RxNotIntable(16*i+15 downto 4*i+12), + gt_rxbyteisaligned_out => RXByteisAligned(4*i+3 downto 4*i), + gt_cpllreset_in => cpll_reset(4*i+3 downto 4*i), --------------------------- ---- CTRL signals --------------------------- - gt_txuserrdy_in => txusrrdy(4*i+3 downto 4*i), - gt_rxuserrdy_in => rxusrrdy(4*i+3 downto 4*i), - - ---------------------------------------------------------------- - ----------RESET SIGNALs - ---------------------------------------------------------------- - - SOFT_RESET_IN => SOFT_RESET_IN_g, - GTTX_RESET_IN => gttx_reset(4*i+3 downto 4*i),-- or rst_hw, - GTRX_RESET_IN => gtrx_reset_i(4*i+3 downto 4*i), - CPLL_RESET_IN => cpll_reset(4*i+3 downto 4*i), - QPLL_RESET_IN => qpll_reset(i), - - SOFT_TXRST_GT => SOFT_TXRST_GT(4*i+3 downto 4*i), - SOFT_RXRST_GT => SOFT_RXRST_GT(4*i+3 downto 4*i), - SOFT_TXRST_ALL => SOFT_TXRST_ALL_g, - SOFT_RXRST_ALL => SOFT_RXRST_ALL_g, - + gt_txuserrdy_in => txusrrdy(4*i+3 downto 4*i), + gt_rxuserrdy_in => rxusrrdy(4*i+3 downto 4*i), + --SOFT_RESET_IN => SOFT_RESET_IN_g, + GTTX_RESET_IN => gttx_reset(4*i+3 downto 4*i), -- or rst_hw, + GTRX_RESET_IN => gtrx_reset_i(4*i+3 downto 4*i), + --CPLL_RESET_IN => cpll_reset(4*i+3 downto 4*i), + QPLL_RESET_IN => qpll_reset(i), + --SOFT_TXRST_GT => SOFT_TXRST_GT(4*i+3 downto 4*i), + --SOFT_RXRST_GT => SOFT_RXRST_GT(4*i+3 downto 4*i), + SOFT_TXRST_ALL => SOFT_TXRST_ALL_g, + SOFT_RXRST_ALL => SOFT_RXRST_ALL_g, ---------- DATA - RX_DATA_gt0_33b => RX_DATA_33b_s(4*i), - TX_DATA_gt0_20b => TX_DATA_20b(4*i), - RX_DATA_gt1_33b => RX_DATA_33b_s(4*i+1), - TX_DATA_gt1_20b => TX_DATA_20b(4*i+1), - RX_DATA_gt2_33b => RX_DATA_33b_s(4*i+2), - TX_DATA_gt2_20b => TX_DATA_20b(4*i+2), - RX_DATA_gt3_33b => RX_DATA_33b_s(4*i+3), - TX_DATA_gt3_20b => TX_DATA_20b(4*i+3), - + RX_DATA_gt0_33b => RX_DATA_33b_s(4*i), + TX_DATA_gt0_20b => TX_DATA_20b(4*i), + RX_DATA_gt1_33b => RX_DATA_33b_s(4*i+1), + TX_DATA_gt1_20b => TX_DATA_20b(4*i+1), + RX_DATA_gt2_33b => RX_DATA_33b_s(4*i+2), + TX_DATA_gt2_20b => TX_DATA_20b(4*i+2), + RX_DATA_gt3_33b => RX_DATA_33b_s(4*i+3), + TX_DATA_gt3_20b => TX_DATA_20b(4*i+3), --------- GTH Data pins - TXP_OUT => TX_P(4*i+3 downto 4*i), - TXN_OUT => TX_N(4*i+3 downto 4*i), - RXP_IN => RX_P(4*i+3 downto 4*i), - RXN_IN => RX_N(4*i+3 downto 4*i) + RXN_IN => RX_N(4*i+3 downto 4*i), + RXP_IN => RX_P(4*i+3 downto 4*i), + TXN_OUT => TX_N(4*i+3 downto 4*i), + TXP_OUT => TX_P(4*i+3 downto 4*i) ); end generate; @@ -767,78 +766,72 @@ g_709a: if CARD_TYPE = 709 or CARD_TYPE = 710 generate GTH_FM_TOP_INST: entity work.gth_fullmode_wrapper_ku Port map ( ---------- Clocks - DRP_CLK_IN => DRP_CLK_IN, - GTH_RefClk => GTH_RefClk(4*i), - - gt3_rxoutclk_out => GT_RXOUTCLK(4*i+3), - gt2_rxoutclk_out => GT_RXOUTCLK(4*i+2), - gt1_rxoutclk_out => GT_RXOUTCLK(4*i+1), - gt0_rxoutclk_out => GT_RXOUTCLK(4*i), - - - gt3_txoutclk_out => GT_TXOUTCLK(4*i+3), - gt2_txoutclk_out => GT_TXOUTCLK(4*i+2), - gt1_txoutclk_out => GT_TXOUTCLK(4*i+1), - gt0_txoutclk_out => GT_TXOUTCLK(4*i), - - gt3_rxusrclk_in => GT_RXUSRCLK(4*i+3), - gt2_rxusrclk_in => GT_RXUSRCLK(4*i+2), - gt1_rxusrclk_in => GT_RXUSRCLK(4*i+1), - gt0_rxusrclk_in => GT_RXUSRCLK(4*i), - - - gt3_txusrclk_in => GT_TXUSRCLK(i), - gt2_txusrclk_in => GT_TXUSRCLK(i), - gt1_txusrclk_in => GT_TXUSRCLK(i), - gt0_txusrclk_in => GT_TXUSRCLK(i), + GTH_RefClk => GTH_RefClk(4*i), + DRP_CLK_IN => DRP_CLK_IN, + + gt0_rxusrclk_in => GT_RXUSRCLK(4*i), + gt1_rxusrclk_in => GT_RXUSRCLK(4*i+1), + gt2_rxusrclk_in => GT_RXUSRCLK(4*i+2), + gt3_rxusrclk_in => GT_RXUSRCLK(4*i+3), + + gt0_rxoutclk_out => GT_RXOUTCLK(4*i), + gt1_rxoutclk_out => GT_RXOUTCLK(4*i+1), + gt2_rxoutclk_out => GT_RXOUTCLK(4*i+2), + gt3_rxoutclk_out => GT_RXOUTCLK(4*i+3), + + gt0_txusrclk_in => GT_TXUSRCLK(i), + gt1_txusrclk_in => GT_TXUSRCLK(i), + gt2_txusrclk_in => GT_TXUSRCLK(i), + gt3_txusrclk_in => GT_TXUSRCLK(i), + + gt0_txoutclk_out => GT_TXOUTCLK(4*i), + gt1_txoutclk_out => GT_TXOUTCLK(4*i+1), + gt2_txoutclk_out => GT_TXOUTCLK(4*i+2), + gt3_txoutclk_out => GT_TXOUTCLK(4*i+3), + ----------------------------------------- ---- Control signals ----------------------------------------- - reset_all_in => soft_reset(i), - cpllreset_in => cpll_reset(4*i+3 downto 4*i), - reset_tx_pll_and_datapath_in => SOFT_TXRST_ALL(i),--QPLL_RESET(i), - reset_tx_datapath_in => SOFT_TXRST_ALL(i), + reset_all_in => soft_reset(i), + cpllreset_in => cpll_reset(4*i+3 downto 4*i), + rxcommadeten_in => rxcommadeten_in(4*i+3 downto 4*i), + reset_tx_pll_and_datapath_in => SOFT_TXRST_ALL(i), --QPLL_RESET(i), + reset_tx_datapath_in => SOFT_TXRST_ALL(i), reset_rx_pll_and_datapath_in => qpll_reset(i), - reset_rx_datapath_in => SOFT_RXRST_ALL(i), - rxcommadeten_in => rxcommadeten_in(4*i+3 downto 4*i), + reset_rx_datapath_in => SOFT_RXRST_ALL(i), + ----------------------------------------- ---- STATUS signals ----------------------------------------- - gt_qplllock_out => qplllock(i), - gt_cpllfbclklost_out => cpllfbclklost(4*i+3 downto 4*i), - gt_cplllock_out => cplllock(4*i+3 downto 4*i), - - gt_txresetdone_out => txresetdone(4*i+3 downto 4*i), - gt_rxresetdone_out => rxresetdone(4*i+3 downto 4*i), - - - gt_rxcdrlock_out => rxcdrlock(4*i+3 downto 4*i), - gt_rxbyteisaligned_out => RXByteisAligned(4*i+3 downto 4*i), - - gt_txfsmresetdone_out => txfsmresetdone(4*i+3 downto 4*i), - gt_rxfsmresetdone_out => rxfsmresetdone(4*i+3 downto 4*i), - - gt0_rxdisperr_out => RxDisperr(16*i+3 downto 16*i), - gt1_rxdisperr_out => RxDisperr(16*i+7 downto 16*i+4), - gt2_rxdisperr_out => RxDisperr(16*i+11 downto 16*i+8), - gt3_rxdisperr_out => RxDisperr(16*i+15 downto 16*i+12), - - + gt_qplllock_out => qplllock(i), + gt_cplllock_out => cplllock(4*i+3 downto 4*i), + gt_cpllfbclklost_out => cpllfbclklost(4*i+3 downto 4*i), + gt_txresetdone_out => txresetdone(4*i+3 downto 4*i), + gt_rxresetdone_out => rxresetdone(4*i+3 downto 4*i), + gt_txfsmresetdone_out => txfsmresetdone(4*i+3 downto 4*i), + gt_rxfsmresetdone_out => rxfsmresetdone(4*i+3 downto 4*i), + gt_rxcdrlock_out => rxcdrlock(4*i+3 downto 4*i), + gt_rxbyteisaligned_out => RXByteisAligned(4*i+3 downto 4*i), + gt0_rxdisperr_out => RxDisperr(16*i+3 downto 16*i), + gt1_rxdisperr_out => RxDisperr(16*i+7 downto 16*i+4), + gt2_rxdisperr_out => RxDisperr(16*i+11 downto 16*i+8), + gt3_rxdisperr_out => RxDisperr(16*i+15 downto 16*i+12), + ---------- DATA - RX_DATA_gt0_33b => RX_DATA_33b_s(4*i), - TX_DATA_gt0_20b => TX_DATA_20b(4*i), - RX_DATA_gt1_33b => RX_DATA_33b_s(4*i+1), - TX_DATA_gt1_20b => TX_DATA_20b(4*i+1), - RX_DATA_gt2_33b => RX_DATA_33b_s(4*i+2), - TX_DATA_gt2_20b => TX_DATA_20b(4*i+2), - RX_DATA_gt3_33b => RX_DATA_33b_s(4*i+3), - TX_DATA_gt3_20b => TX_DATA_20b(4*i+3), - + RX_DATA_gt0_33b => RX_DATA_33b_s(4*i), + TX_DATA_gt0_20b => TX_DATA_20b(4*i), + RX_DATA_gt1_33b => RX_DATA_33b_s(4*i+1), + TX_DATA_gt1_20b => TX_DATA_20b(4*i+1), + RX_DATA_gt2_33b => RX_DATA_33b_s(4*i+2), + TX_DATA_gt2_20b => TX_DATA_20b(4*i+2), + RX_DATA_gt3_33b => RX_DATA_33b_s(4*i+3), + TX_DATA_gt3_20b => TX_DATA_20b(4*i+3), + --------- GTH Data pins - TXP_OUT => TX_P(4*i+3 downto 4*i), - TXN_OUT => TX_N(4*i+3 downto 4*i), - RXP_IN => RX_P(4*i+3 downto 4*i), - RXN_IN => RX_N(4*i+3 downto 4*i) + RXN_IN => RX_N(4*i+3 downto 4*i), + RXP_IN => RX_P(4*i+3 downto 4*i), + TXN_OUT => TX_N(4*i+3 downto 4*i), + TXP_OUT => TX_P(4*i+3 downto 4*i) ); end generate; @@ -847,78 +840,64 @@ g_709a: if CARD_TYPE = 709 or CARD_TYPE = 710 generate GTH_FM_TOP_INST: entity work.gth_fullmode_wrapper_vup Port map ( ---------- Clocks - DRP_CLK_IN => DRP_CLK_IN, - GTH_RefClk => GTH_RefClk(4*i), - - gt3_rxoutclk_out => GT_RXOUTCLK(4*i+3), - gt2_rxoutclk_out => GT_RXOUTCLK(4*i+2), - gt1_rxoutclk_out => GT_RXOUTCLK(4*i+1), - gt0_rxoutclk_out => GT_RXOUTCLK(4*i), - - - gt3_txoutclk_out => GT_TXOUTCLK(4*i+3), - gt2_txoutclk_out => GT_TXOUTCLK(4*i+2), - gt1_txoutclk_out => GT_TXOUTCLK(4*i+1), - gt0_txoutclk_out => GT_TXOUTCLK(4*i), - - gt3_rxusrclk_in => GT_RXUSRCLK(4*i+3), - gt2_rxusrclk_in => GT_RXUSRCLK(4*i+2), - gt1_rxusrclk_in => GT_RXUSRCLK(4*i+1), - gt0_rxusrclk_in => GT_RXUSRCLK(4*i), - - - gt3_txusrclk_in => GT_TXUSRCLK(i), - gt2_txusrclk_in => GT_TXUSRCLK(i), - gt1_txusrclk_in => GT_TXUSRCLK(i), - gt0_txusrclk_in => GT_TXUSRCLK(i), + GTH_RefClk => GTH_RefClk(4*i), + DRP_CLK_IN => DRP_CLK_IN, + gt0_rxusrclk_in => GT_RXUSRCLK(4*i), + gt1_rxusrclk_in => GT_RXUSRCLK(4*i+1), + gt2_rxusrclk_in => GT_RXUSRCLK(4*i+2), + gt3_rxusrclk_in => GT_RXUSRCLK(4*i+3), + gt0_rxoutclk_out => GT_RXOUTCLK(4*i), + gt1_rxoutclk_out => GT_RXOUTCLK(4*i+1), + gt2_rxoutclk_out => GT_RXOUTCLK(4*i+2), + gt3_rxoutclk_out => GT_RXOUTCLK(4*i+3), + gt0_txusrclk_in => GT_TXUSRCLK(i), + gt1_txusrclk_in => GT_TXUSRCLK(i), + gt2_txusrclk_in => GT_TXUSRCLK(i), + gt3_txusrclk_in => GT_TXUSRCLK(i), + gt0_txoutclk_out => GT_TXOUTCLK(4*i), + gt1_txoutclk_out => GT_TXOUTCLK(4*i+1), + gt2_txoutclk_out => GT_TXOUTCLK(4*i+2), + gt3_txoutclk_out => GT_TXOUTCLK(4*i+3), ----------------------------------------- ---- Control signals ----------------------------------------- - reset_all_in => soft_reset(i), - cpllreset_in => cpll_reset(4*i+3 downto 4*i), - reset_tx_pll_and_datapath_in => SOFT_TXRST_ALL(i),--QPLL_RESET(i), - reset_tx_datapath_in => SOFT_TXRST_ALL(i), + reset_all_in => soft_reset(i), + cpllreset_in => cpll_reset(4*i+3 downto 4*i), + rxcommadeten_in => rxcommadeten_in(4*i+3 downto 4*i), + reset_tx_pll_and_datapath_in => SOFT_TXRST_ALL(i), --QPLL_RESET(i), + reset_tx_datapath_in => SOFT_TXRST_ALL(i), reset_rx_pll_and_datapath_in => qpll_reset(i), - reset_rx_datapath_in => SOFT_RXRST_ALL(i), - rxcommadeten_in => rxcommadeten_in(4*i+3 downto 4*i), + reset_rx_datapath_in => SOFT_RXRST_ALL(i), ----------------------------------------- ---- STATUS signals ----------------------------------------- - gt_qplllock_out => qplllock(i), - gt_cpllfbclklost_out => cpllfbclklost(4*i+3 downto 4*i), - gt_cplllock_out => cplllock(4*i+3 downto 4*i), - - gt_txresetdone_out => txresetdone(4*i+3 downto 4*i), - gt_rxresetdone_out => rxresetdone(4*i+3 downto 4*i), - - - gt_rxcdrlock_out => rxcdrlock(4*i+3 downto 4*i), - gt_rxbyteisaligned_out => RXByteisAligned(4*i+3 downto 4*i), - - gt_txfsmresetdone_out => txfsmresetdone(4*i+3 downto 4*i), - gt_rxfsmresetdone_out => rxfsmresetdone(4*i+3 downto 4*i), - - gt0_rxdisperr_out => RxDisperr(16*i+3 downto 16*i), - gt1_rxdisperr_out => RxDisperr(16*i+7 downto 16*i+4), - gt2_rxdisperr_out => RxDisperr(16*i+11 downto 16*i+8), - gt3_rxdisperr_out => RxDisperr(16*i+15 downto 16*i+12), - - + gt_qplllock_out => qplllock(i), + gt_cplllock_out => cplllock(4*i+3 downto 4*i), + gt_cpllfbclklost_out => cpllfbclklost(4*i+3 downto 4*i), + gt_txresetdone_out => txresetdone(4*i+3 downto 4*i), + gt_rxresetdone_out => rxresetdone(4*i+3 downto 4*i), + gt_txfsmresetdone_out => txfsmresetdone(4*i+3 downto 4*i), + gt_rxfsmresetdone_out => rxfsmresetdone(4*i+3 downto 4*i), + gt_rxcdrlock_out => rxcdrlock(4*i+3 downto 4*i), + gt_rxbyteisaligned_out => RXByteisAligned(4*i+3 downto 4*i), + gt0_rxdisperr_out => RxDisperr(16*i+3 downto 16*i), + gt1_rxdisperr_out => RxDisperr(16*i+7 downto 16*i+4), + gt2_rxdisperr_out => RxDisperr(16*i+11 downto 16*i+8), + gt3_rxdisperr_out => RxDisperr(16*i+15 downto 16*i+12), ---------- DATA - RX_DATA_gt0_33b => RX_DATA_33b_s(4*i), - TX_DATA_gt0_20b => TX_DATA_20b(4*i), - RX_DATA_gt1_33b => RX_DATA_33b_s(4*i+1), - TX_DATA_gt1_20b => TX_DATA_20b(4*i+1), - RX_DATA_gt2_33b => RX_DATA_33b_s(4*i+2), - TX_DATA_gt2_20b => TX_DATA_20b(4*i+2), - RX_DATA_gt3_33b => RX_DATA_33b_s(4*i+3), - TX_DATA_gt3_20b => TX_DATA_20b(4*i+3), - + RX_DATA_gt0_33b => RX_DATA_33b_s(4*i), + TX_DATA_gt0_20b => TX_DATA_20b(4*i), + RX_DATA_gt1_33b => RX_DATA_33b_s(4*i+1), + TX_DATA_gt1_20b => TX_DATA_20b(4*i+1), + RX_DATA_gt2_33b => RX_DATA_33b_s(4*i+2), + TX_DATA_gt2_20b => TX_DATA_20b(4*i+2), + RX_DATA_gt3_33b => RX_DATA_33b_s(4*i+3), + TX_DATA_gt3_20b => TX_DATA_20b(4*i+3), --------- GTH Data pins - TXP_OUT => TX_P(4*i+3 downto 4*i), - TXN_OUT => TX_N(4*i+3 downto 4*i), - RXP_IN => RX_P(4*i+3 downto 4*i), - RXN_IN => RX_N(4*i+3 downto 4*i) + RXN_IN => RX_N(4*i+3 downto 4*i), + RXP_IN => RX_P(4*i+3 downto 4*i), + TXN_OUT => TX_N(4*i+3 downto 4*i), + TXP_OUT => TX_P(4*i+3 downto 4*i) ); end generate; diff --git a/sources/FullModeWrapper/gth_fullmode_wrapper_ku.vhd b/sources/FullModeWrapper/gth_fullmode_wrapper_ku.vhd index 36e929f0768eba667b600d07c6595bac500c08ec..70e2d57cddd58bbdf0aaffa17ed34441b7562390 100644 --- a/sources/FullModeWrapper/gth_fullmode_wrapper_ku.vhd +++ b/sources/FullModeWrapper/gth_fullmode_wrapper_ku.vhd @@ -182,171 +182,118 @@ architecture RTL of gth_fullmode_wrapper_ku is attribute CORE_GENERATION_INFO of RTL : architecture is "gtwizard_qpll_4p8g_4ch,gtwizard_v3_4,{protocol_file=Start_from_scratch}"; component gtwizard_fullmode_txcpll_rxqpll_ku -port ( - gtwiz_userclk_tx_active_in : in std_logic_vector(0 downto 0); - gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_reset_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_start_user_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_error_out : out std_logic_vector(0 downto 0); - gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); - gtwiz_reset_all_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); - gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); - gtwiz_userdata_tx_in : in std_logic_vector(79 downto 0); - gtwiz_userdata_rx_out : out std_logic_vector(127 downto 0); - gtrefclk01_in : in std_logic_vector(0 downto 0); - qpll1lock_out : out std_logic_vector(0 downto 0); - qpll1outclk_out : out std_logic_vector(0 downto 0); - qpll1outrefclk_out : out std_logic_vector(0 downto 0); - cplllockdetclk_in : in std_logic_vector(3 downto 0); - cpllreset_in : in std_logic_vector(3 downto 0); - drpclk_in : in std_logic_vector(3 downto 0); - gthrxn_in : in std_logic_vector(3 downto 0); - gthrxp_in : in std_logic_vector(3 downto 0); - gtrefclk0_in : in std_logic_vector(3 downto 0); - rx8b10ben_in : in std_logic_vector(3 downto 0); - rxcommadeten_in : in std_logic_vector(3 downto 0); - rxmcommaalignen_in : in std_logic_vector(3 downto 0); - rxpcommaalignen_in : in std_logic_vector(3 downto 0); - rxusrclk_in : in std_logic_vector(3 downto 0); - rxusrclk2_in : in std_logic_vector(3 downto 0); - txusrclk_in : in std_logic_vector(3 downto 0); - txusrclk2_in : in std_logic_vector(3 downto 0); - cpllfbclklost_out : out std_logic_vector(3 downto 0); - cplllock_out : out std_logic_vector(3 downto 0); - gthtxn_out : out std_logic_vector(3 downto 0); - gthtxp_out : out std_logic_vector(3 downto 0); - rxbyteisaligned_out : out std_logic_vector(3 downto 0); - rxbyterealign_out : out std_logic_vector(3 downto 0); - rxcdrlock_out : out std_logic_vector(3 downto 0); - rxcommadet_out : out std_logic_vector(3 downto 0); - rxctrl0_out : out std_logic_vector(63 downto 0); - rxctrl1_out : out std_logic_vector(63 downto 0); - rxctrl2_out : out std_logic_vector(31 downto 0); - rxctrl3_out : out std_logic_vector(31 downto 0); - rxoutclk_out : out std_logic_vector(3 downto 0); - rxpmaresetdone_out : out std_logic_vector(3 downto 0); - rxresetdone_out : out std_logic_vector(3 downto 0); - txoutclk_out : out std_logic_vector(3 downto 0); - txpmaresetdone_out : out std_logic_vector(3 downto 0); - txresetdone_out : out std_logic_vector(3 downto 0) -); -end component; - -component vio_gbt_chk IS -PORT ( -clk : IN STD_LOGIC; -probe_in0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in5 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in6 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in7 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in8 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in9 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in10 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_in12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_in13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_in14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_in15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_in16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_in17 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in18 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in19 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in20 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in21 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in22 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_out2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_out3 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) -); -END component; - -component ila_gbt_chk IS -PORT ( -clk : IN STD_LOGIC; -probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -probe2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -probe3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -probe4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe5 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe6 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe7 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe8 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe9 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe10 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe11 : IN STD_LOGIC_VECTOR(3 DOWNTO 0) -); -END component; - -signal GT0_QPLLLOCK_I: std_logic:='0'; -signal gt0_gttxreset_in : std_logic:='0'; -signal gt1_gttxreset_in : std_logic:='0'; -signal gt2_gttxreset_in : std_logic:='0'; -signal gt3_gttxreset_in : std_logic:='0'; -signal gt0_gtrxreset_in : std_logic:='0'; -signal gt1_gtrxreset_in : std_logic:='0'; -signal gt2_gtrxreset_in : std_logic:='0'; -signal gt3_gtrxreset_in : std_logic:='0'; - -signal gt0_qplloutclk_i:std_logic; + port( + gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_all_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR(79 downto 0); + gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR(127 downto 0); + gtrefclk01_in : in STD_LOGIC_VECTOR(0 to 0); + qpll1lock_out : out STD_LOGIC_VECTOR(0 to 0); + qpll1outclk_out : out STD_LOGIC_VECTOR(0 to 0); + qpll1outrefclk_out : out STD_LOGIC_VECTOR(0 to 0); + cplllockdetclk_in : in STD_LOGIC_VECTOR(3 downto 0); + cpllreset_in : in STD_LOGIC_VECTOR(3 downto 0); + drpclk_in : in STD_LOGIC_VECTOR(3 downto 0); + gthrxn_in : in STD_LOGIC_VECTOR(3 downto 0); + gthrxp_in : in STD_LOGIC_VECTOR(3 downto 0); + gtrefclk0_in : in STD_LOGIC_VECTOR(3 downto 0); + rx8b10ben_in : in STD_LOGIC_VECTOR(3 downto 0); + rxcommadeten_in : in STD_LOGIC_VECTOR(3 downto 0); + rxmcommaalignen_in : in STD_LOGIC_VECTOR(3 downto 0); + rxpcommaalignen_in : in STD_LOGIC_VECTOR(3 downto 0); + rxusrclk_in : in STD_LOGIC_VECTOR(3 downto 0); + rxusrclk2_in : in STD_LOGIC_VECTOR(3 downto 0); + txusrclk_in : in STD_LOGIC_VECTOR(3 downto 0); + txusrclk2_in : in STD_LOGIC_VECTOR(3 downto 0); + cpllfbclklost_out : out STD_LOGIC_VECTOR(3 downto 0); + cplllock_out : out STD_LOGIC_VECTOR(3 downto 0); + gthtxn_out : out STD_LOGIC_VECTOR(3 downto 0); + gthtxp_out : out STD_LOGIC_VECTOR(3 downto 0); + gtpowergood_out : out STD_LOGIC_VECTOR(3 downto 0); + rxbyteisaligned_out : out STD_LOGIC_VECTOR(3 downto 0); + rxbyterealign_out : out STD_LOGIC_VECTOR(3 downto 0); + rxcdrlock_out : out STD_LOGIC_VECTOR(3 downto 0); + rxcommadet_out : out STD_LOGIC_VECTOR(3 downto 0); + rxctrl0_out : out STD_LOGIC_VECTOR(63 downto 0); + rxctrl1_out : out STD_LOGIC_VECTOR(63 downto 0); + rxctrl2_out : out STD_LOGIC_VECTOR(31 downto 0); + rxctrl3_out : out STD_LOGIC_VECTOR(31 downto 0); + rxoutclk_out : out STD_LOGIC_VECTOR(3 downto 0); + rxpmaresetdone_out : out STD_LOGIC_VECTOR(3 downto 0); + rxresetdone_out : out STD_LOGIC_VECTOR(3 downto 0); + txoutclk_out : out STD_LOGIC_VECTOR(3 downto 0); + txpmaresetdone_out : out STD_LOGIC_VECTOR(3 downto 0); + txresetdone_out : out STD_LOGIC_VECTOR(3 downto 0) + ); +end component gtwizard_fullmode_txcpll_rxqpll_ku; + + +--signal GT0_QPLLLOCK_I: std_logic:='0'; +--signal gt0_gttxreset_in : std_logic:='0'; +--signal gt1_gttxreset_in : std_logic:='0'; +--signal gt2_gttxreset_in : std_logic:='0'; +--signal gt3_gttxreset_in : std_logic:='0'; +--signal gt0_gtrxreset_in : std_logic:='0'; +--signal gt1_gtrxreset_in : std_logic:='0'; +--signal gt2_gtrxreset_in : std_logic:='0'; +--signal gt3_gtrxreset_in : std_logic:='0'; + +--signal gt0_qplloutclk_i:std_logic; signal tied_to_ground_i : std_logic_vector(0 downto 0); -signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); -signal tied_to_vcc_i : std_logic_vector(0 downto 0); -signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0); +--signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); +--signal tied_to_vcc_i : std_logic_vector(0 downto 0); +--signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0); signal tied_to_vcc_vec : std_logic_vector(3 downto 0); -signal gt0_drpaddr_in, gt1_drpaddr_in, gt2_drpaddr_in, gt3_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; -signal gt0_drpdi_in, gt1_drpdi_in, gt2_drpdi_in, gt3_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; -signal gt0_drpdo_out, gt1_drpdo_out, gt2_drpdo_out, gt3_drpdo_out : std_logic_vector(15 downto 0); -signal gt0_drpen_in, gt1_drpen_in,gt2_drpen_in,gt3_drpen_in:std_logic:='0'; -signal gt0_drprdy_out, gt1_drprdy_out,gt2_drprdy_out,gt3_drprdy_out:std_logic; -signal gt0_drpwe_in, gt1_drpwe_in,gt2_drpwe_in,gt3_drpwe_in:std_logic:='0'; - -signal GT0_QPLLREFCLKLOST_I, GT0_QPLLRESET_I,GT0_QPLLOUTREFCLK_I:std_logic; - -signal SOFT_RESET_RX_IN_VIO : std_logic_vector(0 downto 0); -signal gt0_rxdata_out, gt0_rxdata_chk : std_logic_vector(31 downto 0); -signal gt1_rxdata_out,gt1_rxdata_out_r, gt1_rxdata_chk,gt1_rxdata_chk_r : std_logic_vector(31 downto 0); -signal gt2_rxdata_out,gt2_rxdata_out_r, gt2_rxdata_chk,gt2_rxdata_chk_r : std_logic_vector(31 downto 0); -signal gt3_rxdata_out, gt3_rxdata_chk,gt3_rxdata_chk_r : std_logic_vector(31 downto 0); - -signal gt0_rxcharisk_out : std_logic_vector(3 downto 0); -signal gt1_rxcharisk_out : std_logic_vector(3 downto 0); -signal gt2_rxcharisk_out : std_logic_vector(3 downto 0); -signal gt3_rxcharisk_out : std_logic_vector(3 downto 0); +--signal gt0_drpaddr_in, gt1_drpaddr_in, gt2_drpaddr_in, gt3_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; +--signal gt0_drpdi_in, gt1_drpdi_in, gt2_drpdi_in, gt3_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; +--signal gt0_drpdo_out, gt1_drpdo_out, gt2_drpdo_out, gt3_drpdo_out : std_logic_vector(15 downto 0); +--signal gt0_drpen_in, gt1_drpen_in,gt2_drpen_in,gt3_drpen_in:std_logic:='0'; +--signal gt0_drprdy_out, gt1_drprdy_out,gt2_drprdy_out,gt3_drprdy_out:std_logic; +--signal gt0_drpwe_in, gt1_drpwe_in,gt2_drpwe_in,gt3_drpwe_in:std_logic:='0'; + +--signal GT0_QPLLREFCLKLOST_I, GT0_QPLLRESET_I,GT0_QPLLOUTREFCLK_I:std_logic; + +--signal SOFT_RESET_RX_IN_VIO : std_logic_vector(0 downto 0); +--signal gt0_rxdata_out, gt0_rxdata_chk : std_logic_vector(31 downto 0); +--signal gt1_rxdata_out,gt1_rxdata_out_r, gt1_rxdata_chk,gt1_rxdata_chk_r : std_logic_vector(31 downto 0); +--signal gt2_rxdata_out,gt2_rxdata_out_r, gt2_rxdata_chk,gt2_rxdata_chk_r : std_logic_vector(31 downto 0); +--signal gt3_rxdata_out, gt3_rxdata_chk,gt3_rxdata_chk_r : std_logic_vector(31 downto 0); + +--signal gt0_rxcharisk_out : std_logic_vector(3 downto 0); +--signal gt1_rxcharisk_out : std_logic_vector(3 downto 0); +--signal gt2_rxcharisk_out : std_logic_vector(3 downto 0); +--signal gt3_rxcharisk_out : std_logic_vector(3 downto 0); signal rx_data_gt0_33b_i : std_logic_vector(32 downto 0); signal rx_data_gt1_33b_i : std_logic_vector(32 downto 0); signal rx_data_gt2_33b_i : std_logic_vector(32 downto 0); signal rx_data_gt3_33b_i : std_logic_vector(32 downto 0); -signal gt_cplllock_i : std_logic_vector(3 downto 0); -signal gt_cpllfbclklost_i : std_logic_vector(3 downto 0); +--signal gt_cplllock_i : std_logic_vector(3 downto 0); +--signal gt_cpllfbclklost_i : std_logic_vector(3 downto 0); signal rxctrl0_out : std_logic_vector(63 downto 0); signal rxctrl1_out : std_logic_vector(63 downto 0); -signal rxctrl2_out : std_logic_vector(31 downto 0); -signal rxctrl3_out : std_logic_vector(31 downto 0); -signal rxcommadet_out : std_logic_vector(3 downto 0); -signal rxcdrlock_out : std_logic_vector(3 downto 0); +--signal rxctrl2_out : std_logic_vector(31 downto 0); +--signal rxctrl3_out : std_logic_vector(31 downto 0); +--signal rxcommadet_out : std_logic_vector(3 downto 0); +--signal rxcdrlock_out : std_logic_vector(3 downto 0); signal rxbyteisaligned_out : std_logic_vector(3 downto 0); -signal rxbyterealign_out : std_logic_vector(3 downto 0); +--signal rxbyterealign_out : std_logic_vector(3 downto 0); --signal cpllreset_in : std_logic_vector(3 downto 0); signal userclk_tx_active_out : std_logic_vector(0 downto 0); @@ -361,22 +308,22 @@ signal txpmaresetdone_out : std_logic_vector(3 downto 0); signal cplllock_out : std_logic_vector(3 downto 0); signal cpllfbclklost_out : std_logic_vector(3 downto 0); -signal reset_tx_done_out : std_logic_vector(0 downto 0); -signal reset_rx_done_out : std_logic_vector(0 downto 0); +--signal reset_tx_done_out : std_logic_vector(0 downto 0); +--signal reset_rx_done_out : std_logic_vector(0 downto 0); signal reset_all : std_logic_vector(0 downto 0); -signal buffbypass_tx_reset_in : std_logic_vector(0 downto 0); +--signal buffbypass_tx_reset_in : std_logic_vector(0 downto 0); signal userdata_rx_out : std_logic_vector(127 downto 0); -signal buffbypass_tx_error : std_logic_vector(0 downto 0); -signal buffbypass_tx_done : std_logic_vector(0 downto 0); +--signal buffbypass_tx_error : std_logic_vector(0 downto 0); +--signal buffbypass_tx_done : std_logic_vector(0 downto 0); signal reset_tx_pll_and_datapath : std_logic_vector(0 downto 0); signal reset_tx_datapath : std_logic_vector(0 downto 0); signal reset_rx_pll_and_datapath : std_logic_vector(0 downto 0); signal reset_rx_datapath : std_logic_vector(0 downto 0); -signal reset_cdr_stable : std_logic_vector(0 downto 0); +--signal reset_cdr_stable : std_logic_vector(0 downto 0); signal gt_drp_clk_in : std_logic_vector(0 downto 0); signal gtrefclk01_in : std_logic_vector(0 downto 0); @@ -390,36 +337,36 @@ signal txoutclk_out : std_logic_vector(3 downto 0); signal gt_drp_clk_vec : std_logic_vector(3 downto 0); signal qpll1lock_out : std_logic_vector(0 downto 0); -signal comma_8b10b_deted0 : std_logic_vector(3 downto 0); -signal comma_8b10b_deted1 : std_logic_vector(3 downto 0); -signal comma_8b10b_deted2 : std_logic_vector(3 downto 0); -signal comma_8b10b_deted3 : std_logic_vector(3 downto 0); +--signal comma_8b10b_deted0 : std_logic_vector(3 downto 0); +--signal comma_8b10b_deted1 : std_logic_vector(3 downto 0); +--signal comma_8b10b_deted2 : std_logic_vector(3 downto 0); +--signal comma_8b10b_deted3 : std_logic_vector(3 downto 0); -signal comma_deted0 : std_logic_vector(3 downto 0); -signal comma_deted1 : std_logic_vector(3 downto 0); -signal comma_deted2 : std_logic_vector(3 downto 0); -signal comma_deted3 : std_logic_vector(3 downto 0); +--signal comma_deted0 : std_logic_vector(3 downto 0); +--signal comma_deted1 : std_logic_vector(3 downto 0); +--signal comma_deted2 : std_logic_vector(3 downto 0); +--signal comma_deted3 : std_logic_vector(3 downto 0); -signal rxdata0 : std_logic_vector(31 downto 0); -signal rxdata1 : std_logic_vector(31 downto 0); -signal rxdata2 : std_logic_vector(31 downto 0); -signal rxdata3 : std_logic_vector(31 downto 0); +--signal rxdata0 : std_logic_vector(31 downto 0); +--signal rxdata1 : std_logic_vector(31 downto 0); +--signal rxdata2 : std_logic_vector(31 downto 0); +--signal rxdata3 : std_logic_vector(31 downto 0); -signal disp_err0 : std_logic_vector(3 downto 0); -signal disp_err1 : std_logic_vector(3 downto 0); -signal disp_err2 : std_logic_vector(3 downto 0); -signal disp_err3 : std_logic_vector(3 downto 0); +--signal disp_err0 : std_logic_vector(3 downto 0); +--signal disp_err1 : std_logic_vector(3 downto 0); +--signal disp_err2 : std_logic_vector(3 downto 0); +--signal disp_err3 : std_logic_vector(3 downto 0); -signal comma_not_tab0 : std_logic_vector(3 downto 0); -signal comma_not_tab1 : std_logic_vector(3 downto 0); -signal comma_not_tab2 : std_logic_vector(3 downto 0); -signal comma_not_tab3 : std_logic_vector(3 downto 0); +--signal comma_not_tab0 : std_logic_vector(3 downto 0); +--signal comma_not_tab1 : std_logic_vector(3 downto 0); +--signal comma_not_tab2 : std_logic_vector(3 downto 0); +--signal comma_not_tab3 : std_logic_vector(3 downto 0); -signal lmk_reset_out : std_logic_vector(0 downto 0); +--signal lmk_reset_out : std_logic_vector(0 downto 0); -signal gt_reset_tx_done : std_logic_vector(3 downto 0); -signal gt_reset_rx_done : std_logic_vector(3 downto 0); +--signal gt_reset_tx_done : std_logic_vector(3 downto 0); +--signal gt_reset_rx_done : std_logic_vector(3 downto 0); signal gtwiz_userdata_tx_in : std_logic_vector(79 downto 0); --**************************** Main Body of Code ******************************* @@ -481,10 +428,10 @@ begin end process; tied_to_ground_i <= "0"; - tied_to_ground_vec_i <= x"0000000000000000"; - tied_to_vcc_i <= "1"; + --tied_to_ground_vec_i <= x"0000000000000000"; + --tied_to_vcc_i <= "1"; tied_to_vcc_vec <= x"f"; - tied_to_vcc_vec_i <= x"ff"; + --tied_to_vcc_vec_i <= x"ff"; gt_drp_clk_in(0) <= DRP_CLK_IN; gtrefclk0_in(0) <= GTH_RefClk; @@ -562,65 +509,60 @@ end generate; gtwiz_userdata_tx_in <= TX_DATA_gt3_20b & TX_DATA_gt2_20b & TX_DATA_gt1_20b & TX_DATA_gt0_20b; gth_fullmode_ultrascale_inst: gtwizard_fullmode_txcpll_rxqpll_ku port map( - gtwiz_userclk_tx_active_in => userclk_tx_active_out, - gtwiz_userclk_rx_active_in => userclk_rx_active_out, - gtwiz_buffbypass_tx_reset_in => tied_to_ground_i, --buffbypass_tx_reset_in, - gtwiz_buffbypass_tx_start_user_in => tied_to_ground_i, - gtwiz_buffbypass_tx_done_out => open, --buffbypass_tx_done, - gtwiz_buffbypass_tx_error_out => open, --buffbypass_tx_error, - gtwiz_reset_clk_freerun_in => gt_drp_clk_in, - gtwiz_reset_all_in => reset_all, - gtwiz_reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath, - gtwiz_reset_tx_datapath_in => reset_tx_datapath, - gtwiz_reset_rx_pll_and_datapath_in => reset_rx_pll_and_datapath, - gtwiz_reset_rx_datapath_in => reset_rx_datapath, - gtwiz_reset_rx_cdr_stable_out => reset_cdr_stable, - gtwiz_reset_tx_done_out => reset_tx_done_out, - gtwiz_reset_rx_done_out => reset_rx_done_out, - gtwiz_userdata_tx_in => gtwiz_userdata_tx_in, - gtwiz_userdata_rx_out => userdata_rx_out, - - gtrefclk01_in => gtrefclk01_in, - qpll1lock_out => qpll1lock_out, - qpll1outclk_out => open, - qpll1outrefclk_out => open, - - cplllockdetclk_in => gt_drp_clk_vec, --gt_drp_clk_in, - cpllreset_in => cpllreset_in, - drpclk_in => gt_drp_clk_vec, - gthrxn_in => RXN_IN, - gthrxp_in => RXP_IN, - gtrefclk0_in => gtrefclk0_in, - - rx8b10ben_in => tied_to_vcc_vec, - rxcommadeten_in => rxcommadeten_in,--tied_to_vcc_vec, - rxmcommaalignen_in => tied_to_vcc_vec, - rxpcommaalignen_in => tied_to_vcc_vec, - - rxusrclk_in => rxusrclk_in, - rxusrclk2_in => rxusrclk_in, - txusrclk_in => txusrclk_in, - txusrclk2_in => txusrclk_in, - cpllfbclklost_out => cpllfbclklost_out, - cplllock_out => cplllock_out, - gthtxn_out => TXN_OUT, - gthtxp_out => TXP_OUT, - rxbyteisaligned_out => rxbyteisaligned_out, - rxbyterealign_out => open, --rxbyterealign_out, - rxcdrlock_out => rxcdrlock_out, - rxcommadet_out => open, --rxcommadet_out, - - rxctrl0_out => rxctrl0_out, - rxctrl1_out => rxctrl1_out, - rxctrl2_out => rxctrl2_out, - rxctrl3_out => rxctrl3_out, - - rxoutclk_out => rxoutclk_out, - rxpmaresetdone_out => rxpmaresetdone_out, - rxresetdone_out => rxresetdone_out, - txoutclk_out => txoutclk_out, - txpmaresetdone_out => txpmaresetdone_out, - txresetdone_out => txresetdone_out + gtwiz_userclk_tx_active_in => userclk_tx_active_out, + gtwiz_userclk_rx_active_in => userclk_rx_active_out, + gtwiz_buffbypass_tx_reset_in => tied_to_ground_i, --buffbypass_tx_reset_in, + gtwiz_buffbypass_tx_start_user_in => tied_to_ground_i, + gtwiz_buffbypass_tx_done_out => open, --buffbypass_tx_done, + gtwiz_buffbypass_tx_error_out => open, --buffbypass_tx_error, + gtwiz_reset_clk_freerun_in => gt_drp_clk_in, + gtwiz_reset_all_in => reset_all, + gtwiz_reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath, + gtwiz_reset_tx_datapath_in => reset_tx_datapath, + gtwiz_reset_rx_pll_and_datapath_in => reset_rx_pll_and_datapath, + gtwiz_reset_rx_datapath_in => reset_rx_datapath, + gtwiz_reset_rx_cdr_stable_out => open, + gtwiz_reset_tx_done_out => open, + gtwiz_reset_rx_done_out => open, + gtwiz_userdata_tx_in => gtwiz_userdata_tx_in, + gtwiz_userdata_rx_out => userdata_rx_out, + gtrefclk01_in => gtrefclk01_in, + qpll1lock_out => qpll1lock_out, + qpll1outclk_out => open, + qpll1outrefclk_out => open, + cplllockdetclk_in => gt_drp_clk_vec, --gt_drp_clk_in, + cpllreset_in => cpllreset_in, + drpclk_in => gt_drp_clk_vec, + gthrxn_in => RXN_IN, + gthrxp_in => RXP_IN, + gtrefclk0_in => gtrefclk0_in, + rx8b10ben_in => tied_to_vcc_vec, + rxcommadeten_in => rxcommadeten_in, --tied_to_vcc_vec, + rxmcommaalignen_in => tied_to_vcc_vec, + rxpcommaalignen_in => tied_to_vcc_vec, + rxusrclk_in => rxusrclk_in, + rxusrclk2_in => rxusrclk_in, + txusrclk_in => txusrclk_in, + txusrclk2_in => txusrclk_in, + cpllfbclklost_out => cpllfbclklost_out, + cplllock_out => cplllock_out, + gthtxn_out => TXN_OUT, + gthtxp_out => TXP_OUT, + gtpowergood_out => open, + rxbyteisaligned_out => rxbyteisaligned_out, + rxbyterealign_out => open, --rxbyterealign_out, + rxcdrlock_out => open, + rxcommadet_out => open, --rxcommadet_out, + rxctrl0_out => rxctrl0_out, + rxctrl1_out => rxctrl1_out, + rxctrl2_out => open, + rxctrl3_out => open, + rxoutclk_out => rxoutclk_out, + rxpmaresetdone_out => rxpmaresetdone_out, + rxresetdone_out => rxresetdone_out, + txoutclk_out => txoutclk_out, + txpmaresetdone_out => txpmaresetdone_out, + txresetdone_out => txresetdone_out ); gt_cpllfbclklost_out <= cpllfbclklost_out; @@ -677,20 +619,20 @@ gt_qplllock_out <= qpll1lock_out(0); --comma_not_tab2 <= rxctrl3_out(3 downto 0); --comma_not_tab3 <= rxctrl3_out(3 downto 0); -comma_8b10b_deted0 <= rxctrl0_out(3 downto 0); -comma_8b10b_deted1 <= rxctrl0_out(19 downto 16); -comma_8b10b_deted2 <= rxctrl0_out(35 downto 32); -comma_8b10b_deted3 <= rxctrl0_out(51 downto 48); - -comma_deted0 <= rxctrl2_out(3 downto 0); -comma_deted1 <= rxctrl2_out(11 downto 8); -comma_deted2 <= rxctrl2_out(19 downto 16); -comma_deted3 <= rxctrl2_out(27 downto 24); - -rxdata0 <= userdata_rx_out(31 downto 0); -rxdata1 <= userdata_rx_out(31 downto 0); -rxdata2 <= userdata_rx_out(31 downto 0); -rxdata3 <= userdata_rx_out(31 downto 0); +--comma_8b10b_deted0 <= rxctrl0_out(3 downto 0); +--comma_8b10b_deted1 <= rxctrl0_out(19 downto 16); +--comma_8b10b_deted2 <= rxctrl0_out(35 downto 32); +--comma_8b10b_deted3 <= rxctrl0_out(51 downto 48); +-- +--comma_deted0 <= rxctrl2_out(3 downto 0); +--comma_deted1 <= rxctrl2_out(11 downto 8); +--comma_deted2 <= rxctrl2_out(19 downto 16); +--comma_deted3 <= rxctrl2_out(27 downto 24); +-- +--rxdata0 <= userdata_rx_out(31 downto 0); +--rxdata1 <= userdata_rx_out(31 downto 0); +--rxdata2 <= userdata_rx_out(31 downto 0); +--rxdata3 <= userdata_rx_out(31 downto 0); --ila_gbt_chk_inst: ila_gbt_chk --PORT MAP( diff --git a/sources/FullModeWrapper/gth_fullmode_wrapper_v7.vhd b/sources/FullModeWrapper/gth_fullmode_wrapper_v7.vhd index 2b1978ff6f5c48eb8b73fbae401aed1fb6f80b9a..d61a8e9d329690fbde590ad63ef07f7177b77704 100644 --- a/sources/FullModeWrapper/gth_fullmode_wrapper_v7.vhd +++ b/sources/FullModeWrapper/gth_fullmode_wrapper_v7.vhd @@ -93,11 +93,11 @@ port --- TX clock, shared by all channels gt0_txusrclk_in : in std_logic; gt0_txoutclk_out : out std_logic; - gt1_txusrclk_in : in std_logic; + --gt1_txusrclk_in : in std_logic; gt1_txoutclk_out : out std_logic; - gt2_txusrclk_in : in std_logic; + --gt2_txusrclk_in : in std_logic; gt2_txoutclk_out : out std_logic; - gt3_txusrclk_in : in std_logic; + --gt3_txusrclk_in : in std_logic; gt3_txoutclk_out : out std_logic; ----------------------------------------- @@ -138,14 +138,14 @@ port ---------------------------------------------------------------- ----------RESET SIGNALs ---------------------------------------------------------------- - SOFT_RESET_IN : in std_logic; + --SOFT_RESET_IN : in std_logic; GTTX_RESET_IN : in std_logic_vector(3 downto 0); GTRX_RESET_IN : in std_logic_vector(3 downto 0); - CPLL_RESET_IN : in std_logic_vector(3 downto 0); + --CPLL_RESET_IN : in std_logic_vector(3 downto 0); QPLL_RESET_IN : in std_logic; - SOFT_TXRST_GT : in std_logic_vector(3 downto 0); - SOFT_RXRST_GT : in std_logic_vector(3 downto 0); + --SOFT_TXRST_GT : in std_logic_vector(3 downto 0); + --SOFT_RXRST_GT : in std_logic_vector(3 downto 0); SOFT_TXRST_ALL : in std_logic; SOFT_RXRST_ALL : in std_logic; @@ -532,22 +532,22 @@ signal gt0_qplloutclk_i:std_logic; signal tied_to_ground_i : std_logic; signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); signal tied_to_vcc_i : std_logic; -signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0); +--signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0); -signal gt0_drpaddr_in, gt1_drpaddr_in, gt2_drpaddr_in, gt3_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; -signal gt0_drpdi_in, gt1_drpdi_in, gt2_drpdi_in, gt3_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; -signal gt0_drpdo_out, gt1_drpdo_out, gt2_drpdo_out, gt3_drpdo_out : std_logic_vector(15 downto 0); -signal gt0_drpen_in, gt1_drpen_in,gt2_drpen_in,gt3_drpen_in:std_logic:='0'; -signal gt0_drprdy_out, gt1_drprdy_out,gt2_drprdy_out,gt3_drprdy_out:std_logic; -signal gt0_drpwe_in, gt1_drpwe_in,gt2_drpwe_in,gt3_drpwe_in:std_logic:='0'; +--signal gt0_drpaddr_in, gt1_drpaddr_in, gt2_drpaddr_in, gt3_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; +--signal gt0_drpdi_in, gt1_drpdi_in, gt2_drpdi_in, gt3_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; +--signal gt0_drpdo_out, gt1_drpdo_out, gt2_drpdo_out, gt3_drpdo_out : std_logic_vector(15 downto 0); +--signal gt0_drpen_in, gt1_drpen_in,gt2_drpen_in,gt3_drpen_in:std_logic:='0'; +--signal gt0_drprdy_out, gt1_drprdy_out,gt2_drprdy_out,gt3_drprdy_out:std_logic; +--signal gt0_drpwe_in, gt1_drpwe_in,gt2_drpwe_in,gt3_drpwe_in:std_logic:='0'; signal GT0_QPLLREFCLKLOST_I, GT0_QPLLRESET_I,GT0_QPLLOUTREFCLK_I:std_logic; -signal SOFT_RESET_RX_IN_VIO : std_logic_vector(0 downto 0); -signal gt0_rxdata_out, gt0_rxdata_chk : std_logic_vector(31 downto 0); -signal gt1_rxdata_out,gt1_rxdata_out_r, gt1_rxdata_chk,gt1_rxdata_chk_r : std_logic_vector(31 downto 0); -signal gt2_rxdata_out,gt2_rxdata_out_r, gt2_rxdata_chk,gt2_rxdata_chk_r : std_logic_vector(31 downto 0); -signal gt3_rxdata_out, gt3_rxdata_chk,gt3_rxdata_chk_r : std_logic_vector(31 downto 0); +--signal SOFT_RESET_RX_IN_VIO : std_logic_vector(0 downto 0); +signal gt0_rxdata_out : std_logic_vector(31 downto 0); +signal gt1_rxdata_out : std_logic_vector(31 downto 0); +signal gt2_rxdata_out : std_logic_vector(31 downto 0); +signal gt3_rxdata_out : std_logic_vector(31 downto 0); signal gt0_rxcharisk_out : std_logic_vector(3 downto 0); signal gt1_rxcharisk_out : std_logic_vector(3 downto 0); @@ -597,8 +597,7 @@ begin tied_to_ground_i <= '0'; tied_to_ground_vec_i <= x"0000000000000000"; tied_to_vcc_i <= '1'; - tied_to_vcc_vec_i <= x"ff"; - + gt_cpllfbclklost_out <= gt_cpllfbclklost_i; gt_cplllock_out <= gt_cplllock_i; @@ -617,11 +616,11 @@ begin gt2_gtrxreset_in <= GTRX_RESET_IN(2) or (not GT0_QPLLLOCK_I); gt3_gtrxreset_in <= GTRX_RESET_IN(3) or (not GT0_QPLLLOCK_I); - QPLLRESET <= GT0_QPLLRESET_i or QPLL_RESET_IN; + QPLLRESET <= GT0_QPLLRESET_I or QPLL_RESET_IN; gthe2_common_0_i : GTHE2_COMMON - generic map + generic map -- @suppress "The order of the associations is different from the declaration order" ( -- Simulation attributes SIM_RESET_SPEEDUP => ("FALSE"), @@ -629,6 +628,9 @@ begin SIM_VERSION => ("2.0"), ------------------COMMON BLOCK Attributes--------------- + IS_DRPCLK_INVERTED => '0', + IS_GTGREFCLK_INVERTED => '0', + IS_QPLLLOCKDETCLK_INVERTED => '0', BIAS_CFG => (x"0000040000001050"), COMMON_CFG => (x"0000001C"), QPLL_CFG => (x"04801C7"), @@ -653,7 +655,7 @@ begin ) - port map + port map -- @suppress "The order of the associations is different from the declaration order" ( ------------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- DRPADDR => tied_to_ground_vec_i(7 downto 0), @@ -675,7 +677,7 @@ begin QPLLDMONITOR => open, ----------------------- Common Block - Clocking Ports ---------------------- QPLLOUTCLK => gt0_qplloutclk_i, - QPLLOUTREFCLK => gt0_qplloutrefclk_i, + QPLLOUTREFCLK => GT0_QPLLOUTREFCLK_I, REFCLKOUTMONITOR => open, ------------------------- Common Block - QPLL Ports ------------------------ BGRCALOVRDENB => tied_to_vcc_i, @@ -706,343 +708,219 @@ qpll_inst: gtwizard_fullmode_txcpll_rxqpll_v7 port map ( - SYSCLK_IN => DRP_CLK_IN, - - SOFT_RESET_TX_IN => SOFT_TXRST_ALL, - SOFT_RESET_RX_IN => SOFT_RXRST_ALL, - DONT_RESET_ON_DATA_ERROR_IN => '1', - GT0_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(0), - GT0_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(0), - GT0_DATA_VALID_IN => '1', - GT1_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(1), - GT1_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(1), - GT1_DATA_VALID_IN => '1', - GT2_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(2), - GT2_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(2), - GT2_DATA_VALID_IN => '1', - GT3_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(3), - GT3_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(3), - GT3_DATA_VALID_IN => '1', - - --_________________________________________________________________________ - --_________________________________________________________________________ - --GT0 (X1Y4) - --____________________________CHANNEL PORTS________________________________ - - --------------------------------- CPLL Ports ------------------------------- - gt0_cpllfbclklost_out => gt_cpllfbclklost_i(0), - gt0_cplllock_out => gt_cplllock_i(0), - gt0_cplllockdetclk_in => DRP_CLK_IN, - gt0_cpllreset_in => gt_cpllreset_in(0), - - -------------------------- Channel - Clocking Ports ------------------------ - gt0_gtrefclk0_in => tied_to_ground_i, - gt0_gtrefclk1_in => GTH_RefClk, - - ---------------------------- Channel - DRP Ports -------------------------- - gt0_drpaddr_in => (others => '0'), --gt0_drpaddr_in, - gt0_drpclk_in => DRP_CLK_IN, - gt0_drpdi_in => (others => '0'), --gt0_drpdi_in, - gt0_drpdo_out => open, --gt0_drpdo_out, - gt0_drpen_in => '0', --gt0_drpen_in, - gt0_drprdy_out => open, --gt0_drprdy_out, - gt0_drpwe_in => '0', --gt0_drpwe_in, - --------------------- RX Initialization and Reset Ports -------------------- - gt0_eyescanreset_in => '0', - gt0_rxuserrdy_in => gt_rxuserrdy_in(0), - -------------------------- RX Margin Analysis Ports ------------------------ - gt0_eyescandataerror_out => open, - gt0_eyescantrigger_in => '0', - ------------------- Receive Ports - Digital Monitor Ports ------------------ - gt0_dmonitorout_out => open, - ------------------ Receive Ports - FPGA RX Interface Ports ----------------- - gt0_rxusrclk_in => gt0_rxusrclk_in, - gt0_rxusrclk2_in => gt0_rxusrclk_in, - ------------------ Receive Ports - FPGA RX interface Ports ----------------- - gt0_rxdata_out => gt0_rxdata_out, --RX_DATA_gt0_20b, - ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- - gt0_rxdisperr_out => gt0_rxdisperr_out, - gt0_rxnotintable_out => gt0_rxnotintable_out, - ------------------------ Receive Ports - RX AFE Ports ---------------------- - gt0_gthrxn_in => RXN_IN(0), - -------------- Receive Ports - RX Byte and Word Alignment Ports ------------ - gt0_rxbyteisaligned_out => gt_rxbyteisaligned_out(0), - gt0_rxmcommaalignen_in => '0',--gt0_rxmcommaalignen_in, - gt0_rxpcommaalignen_in => '1',--gt0_rxpcommaalignen_in, - --------------------- Receive Ports - RX Equalizer Ports ------------------- - gt0_rxmonitorout_out => open, - gt0_rxmonitorsel_in => "00", - --------------- Receive Ports - RX Fabric Output Control Ports ------------- - gt0_rxoutclk_out => gt0_rxoutclk_out, - gt0_rxoutclkfabric_out => open,--gt0_rxoutclkfabric_out, - ------------- Receive Ports - RX Initialization and Reset Ports ------------ - gt0_gtrxreset_in => gt0_gtrxreset_in, - ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- - gt0_rxcharisk_out => gt0_rxcharisk_out, - ------------------------ Receive Ports -RX AFE Ports ----------------------- - gt0_gthrxp_in => RXP_IN(0), - -------------- Receive Ports -RX Initialization and Reset Ports ------------ - gt0_rxresetdone_out => gt_rxresetdone_out(0),-- gt0_rxresetdone_out, - --------------------- TX Initialization and Reset Ports -------------------- - gt0_gttxreset_in => gt0_gttxreset_in, - gt0_txuserrdy_in => gt_txuserrdy_in(0), - ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- - gt0_txusrclk_in => gt0_txusrclk_in, - gt0_txusrclk2_in => gt0_txusrclk_in, - ------------------ Transmit Ports - TX Data Path interface ----------------- - gt0_txdata_in => TX_DATA_gt0_20b, - ---------------- Transmit Ports - TX Driver and OOB signaling -------------- - gt0_gthtxn_out => TXN_OUT(0), - gt0_gthtxp_out => TXP_OUT(0), - ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- - gt0_txoutclk_out => gt0_txoutclk_out, - gt0_txoutclkfabric_out => open,--gt0_txoutclkfabric_out, - gt0_txoutclkpcs_out => open,--gt0_txoutclkpcs_out, - ------------- Transmit Ports - TX Initialization and Reset Ports ----------- - gt0_txresetdone_out => gt_txresetdone_out(0), - gt0_rxphmonitor_out => open, - gt0_rxphslipmonitor_out => open, - --GT1 (X1Y5) - --____________________________CHANNEL PORTS________________________________ - --------------------------------- CPLL Ports ------------------------------- - gt1_cpllfbclklost_out => gt_cpllfbclklost_i(1), - gt1_cplllock_out => gt_cplllock_i(1), - gt1_cplllockdetclk_in => DRP_CLK_IN, - gt1_cpllreset_in => gt_cpllreset_in(1), - - -------------------------- Channel - Clocking Ports ------------------------ - gt1_gtrefclk0_in => tied_to_ground_i, - gt1_gtrefclk1_in => GTH_RefClk, - - ---------------------------- Channel - DRP Ports -------------------------- - gt1_drpaddr_in => gt1_drpaddr_in, - gt1_drpclk_in => DRP_CLK_IN, - gt1_drpdi_in => gt1_drpdi_in, - gt1_drpdo_out => gt1_drpdo_out, - gt1_drpen_in => gt1_drpen_in, - gt1_drprdy_out => gt1_drprdy_out, - gt1_drpwe_in => gt1_drpwe_in, - --------------------- RX Initialization and Reset Ports -------------------- - gt1_eyescanreset_in => '0', - gt1_rxuserrdy_in => gt_rxuserrdy_in(1), - -------------------------- RX Margin Analysis Ports ------------------------ - gt1_eyescandataerror_out => open, - gt1_eyescantrigger_in => '0', - ------------------- Receive Ports - Digital Monitor Ports ------------------ - gt1_dmonitorout_out => open, - ------------------ Receive Ports - FPGA RX Interface Ports ----------------- - gt1_rxusrclk_in => gt1_rxusrclk_in, - gt1_rxusrclk2_in => gt1_rxusrclk_in, - ------------------ Receive Ports - FPGA RX interface Ports ----------------- - gt1_rxdata_out => gt1_rxdata_out, --RX_DATA_gt1_20b, - ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- - gt1_rxdisperr_out => gt1_rxdisperr_out, - gt1_rxnotintable_out => gt1_rxnotintable_out, - ------------------------ Receive Ports - RX AFE Ports ---------------------- - gt1_gthrxn_in => RXN_IN(1), - -------------- Receive Ports - RX Byte and Word Alignment Ports ------------ - gt1_rxbyteisaligned_out => gt_rxbyteisaligned_out(1), - gt1_rxmcommaalignen_in => '0',--gt0_rxmcommaalignen_in, - gt1_rxpcommaalignen_in => '1',--gt0_rxpcommaalignen_in, - ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- - --gt1_rxphmonitor_out => open, - --gt1_rxphslipmonitor_out => open, - --------------------- Receive Ports - RX Equalizer Ports ------------------- - gt1_rxmonitorout_out => open, - gt1_rxmonitorsel_in => "00", - --------------- Receive Ports - RX Fabric Output Control Ports ------------- - gt1_rxoutclk_out => gt1_rxoutclk_out, - gt1_rxoutclkfabric_out => open,--gt0_rxoutclkfabric_out, - ------------- Receive Ports - RX Initialization and Reset Ports ------------ - gt1_gtrxreset_in => gt1_gtrxreset_in, - ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- - gt1_rxcharisk_out => gt1_rxcharisk_out, - ------------------------ Receive Ports -RX AFE Ports ----------------------- - gt1_gthrxp_in => RXP_IN(1), - -------------- Receive Ports -RX Initialization and Reset Ports ------------ - gt1_rxresetdone_out => gt_rxresetdone_out(1), - --------------------- TX Initialization and Reset Ports -------------------- - gt1_gttxreset_in => gt1_gttxreset_in, - gt1_txuserrdy_in => gt_txuserrdy_in(1), - ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- - gt1_txusrclk_in => gt0_txusrclk_in, - gt1_txusrclk2_in => gt0_txusrclk_in, - ------------------ Transmit Ports - TX Data Path interface ----------------- - gt1_txdata_in => TX_DATA_gt1_20b, - ---------------- Transmit Ports - TX Driver and OOB signaling -------------- - gt1_gthtxn_out => TXN_OUT(1), - gt1_gthtxp_out => TXP_OUT(1), - ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- - gt1_txoutclk_out => gt1_txoutclk_out, - gt1_txoutclkfabric_out => open,--gt1_txoutclkfabric_out, - gt1_txoutclkpcs_out => open,--gt1_txoutclkpcs_out, - ------------- Transmit Ports - TX Initialization and Reset Ports ----------- - gt1_txresetdone_out => gt_txresetdone_out(1), - gt1_rxphmonitor_out => open, - gt1_rxphslipmonitor_out => open, - --GT2 (X1Y6) - --____________________________CHANNEL PORTS________________________________ - - --------------------------------- CPLL Ports ------------------------------- - gt2_cpllfbclklost_out => gt_cpllfbclklost_i(2), - gt2_cplllock_out => gt_cplllock_i(2), - gt2_cplllockdetclk_in => DRP_CLK_IN, - gt2_cpllreset_in => gt_cpllreset_in(2), - - -------------------------- Channel - Clocking Ports ------------------------ - gt2_gtrefclk0_in => tied_to_ground_i, - gt2_gtrefclk1_in => GTH_RefClk, - ---------------------------- Channel - DRP Ports -------------------------- - gt2_drpaddr_in => gt2_drpaddr_in, - gt2_drpclk_in => DRP_CLK_IN, - gt2_drpdi_in => gt2_drpdi_in, - gt2_drpdo_out => gt2_drpdo_out, - gt2_drpen_in => gt2_drpen_in, - gt2_drprdy_out => gt2_drprdy_out, - gt2_drpwe_in => gt2_drpwe_in, - --------------------- RX Initialization and Reset Ports -------------------- - gt2_eyescanreset_in => '0', - gt2_rxuserrdy_in => gt_rxuserrdy_in(2), - -------------------------- RX Margin Analysis Ports ------------------------ - gt2_eyescandataerror_out => open, - gt2_eyescantrigger_in => '0', - ------------------- Receive Ports - Digital Monitor Ports ------------------ - gt2_dmonitorout_out => open, - ------------------ Receive Ports - FPGA RX Interface Ports ----------------- - gt2_rxusrclk_in => gt2_rxusrclk_in, - gt2_rxusrclk2_in => gt2_rxusrclk_in, - ------------------ Receive Ports - FPGA RX interface Ports ----------------- - gt2_rxdata_out => gt2_rxdata_out, --RX_DATA_gt2_20b, - ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- - gt2_rxdisperr_out => gt2_rxdisperr_out, - gt2_rxnotintable_out => gt2_rxnotintable_out, - ------------------------ Receive Ports - RX AFE Ports ---------------------- - gt2_gthrxn_in => RXN_IN(2), - -------------- Receive Ports - RX Byte and Word Alignment Ports ------------ - gt2_rxbyteisaligned_out => gt_rxbyteisaligned_out(2), - gt2_rxmcommaalignen_in => '0',--gt0_rxmcommaalignen_in, - gt2_rxpcommaalignen_in => '1',--gt0_rxpcommaalignen_in, - ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- - --gt2_rxphmonitor_out => open, - --gt2_rxphslipmonitor_out => open, - --------------------- Receive Ports - RX Equalizer Ports ------------------- - gt2_rxmonitorout_out => open, - gt2_rxmonitorsel_in => "00", - --------------- Receive Ports - RX Fabric Output Control Ports ------------- - gt2_rxoutclk_out => gt2_rxoutclk_out, - gt2_rxoutclkfabric_out => open,--gt0_rxoutclkfabric_out, - ------------- Receive Ports - RX Initialization and Reset Ports ------------ - gt2_gtrxreset_in => gt2_gtrxreset_in, - ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- - gt2_rxcharisk_out => gt2_rxcharisk_out, - ------------------------ Receive Ports -RX AFE Ports ----------------------- - gt2_gthrxp_in => RXP_IN(2), - -------------- Receive Ports -RX Initialization and Reset Ports ------------ - gt2_rxresetdone_out => gt_rxresetdone_out(2), - --------------------- TX Initialization and Reset Ports -------------------- - gt2_gttxreset_in => gt2_gttxreset_in, - gt2_txuserrdy_in => gt_txuserrdy_in(2), - ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- - gt2_txusrclk_in => gt0_txusrclk_in, - gt2_txusrclk2_in => gt0_txusrclk_in, - ------------------ Transmit Ports - TX Data Path interface ----------------- - gt2_txdata_in => TX_DATA_gt2_20b, - ---------------- Transmit Ports - TX Driver and OOB signaling -------------- - gt2_gthtxn_out => TXN_OUT(2), - gt2_gthtxp_out => TXP_OUT(2), - ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- - gt2_txoutclk_out => gt2_txoutclk_out, - gt2_txoutclkfabric_out => open,--gt2_txoutclkfabric_out, - gt2_txoutclkpcs_out => open,--gt2_txoutclkpcs_out, - ------------- Transmit Ports - TX Initialization and Reset Ports ----------- - gt2_txresetdone_out => gt_txresetdone_out(2), - gt2_rxphmonitor_out => open, - gt2_rxphslipmonitor_out => open, - --GT3 (X1Y7) - --____________________________CHANNEL PORTS________________________________ - - --------------------------------- CPLL Ports ------------------------------- - gt3_cpllfbclklost_out => gt_cpllfbclklost_i(3), - gt3_cplllock_out => gt_cplllock_i(3), - gt3_cplllockdetclk_in => DRP_CLK_IN, - gt3_cpllreset_in => gt_cpllreset_in(3), - - -------------------------- Channel - Clocking Ports ------------------------ - gt3_gtrefclk0_in => tied_to_ground_i, - gt3_gtrefclk1_in => GTH_RefClk, - ---------------------------- Channel - DRP Ports -------------------------- - gt3_drpaddr_in => gt3_drpaddr_in, - gt3_drpclk_in => DRP_CLK_IN, - gt3_drpdi_in => gt3_drpdi_in, - gt3_drpdo_out => gt3_drpdo_out, - gt3_drpen_in => gt3_drpen_in, - gt3_drprdy_out => gt3_drprdy_out, - gt3_drpwe_in => gt3_drpwe_in, - --------------------- RX Initialization and Reset Ports -------------------- - gt3_eyescanreset_in => '0', - gt3_rxuserrdy_in => gt_rxuserrdy_in(3), - -------------------------- RX Margin Analysis Ports ------------------------ - gt3_eyescandataerror_out => open, - gt3_eyescantrigger_in => '0', - ------------------- Receive Ports - Digital Monitor Ports ------------------ - gt3_dmonitorout_out => open, - ------------------ Receive Ports - FPGA RX Interface Ports ----------------- - gt3_rxusrclk_in => gt3_rxusrclk_in, - gt3_rxusrclk2_in => gt3_rxusrclk_in, - ------------------ Receive Ports - FPGA RX interface Ports ----------------- - gt3_rxdata_out => gt3_rxdata_out, --RX_DATA_gt3_20b, - ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- - gt3_rxdisperr_out => gt3_rxdisperr_out, - gt3_rxnotintable_out => gt3_rxnotintable_out, - ------------------------ Receive Ports - RX AFE Ports ---------------------- - gt3_gthrxn_in => RXN_IN(3), - -------------- Receive Ports - RX Byte and Word Alignment Ports ------------ - gt3_rxbyteisaligned_out => gt_rxbyteisaligned_out(3), - gt3_rxmcommaalignen_in => '0',--gt0_rxmcommaalignen_in, - gt3_rxpcommaalignen_in => '1',--gt0_rxpcommaalignen_in, - ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- - --gt3_rxphmonitor_out => open, - --gt3_rxphslipmonitor_out => open, - --------------------- Receive Ports - RX Equalizer Ports ------------------- - gt3_rxmonitorout_out => open, - gt3_rxmonitorsel_in => "00", - --------------- Receive Ports - RX Fabric Output Control Ports ------------- - gt3_rxoutclk_out => gt3_rxoutclk_out, - gt3_rxoutclkfabric_out => open,--gt0_rxoutclkfabric_out, - ------------- Receive Ports - RX Initialization and Reset Ports ------------ - gt3_gtrxreset_in => gt3_gtrxreset_in, - ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- - gt3_rxcharisk_out => gt3_rxcharisk_out, - ------------------------ Receive Ports -RX AFE Ports ----------------------- - gt3_gthrxp_in => RXP_IN(3), - -------------- Receive Ports -RX Initialization and Reset Ports ------------ - gt3_rxresetdone_out => gt_rxresetdone_out(3), - --------------------- TX Initialization and Reset Ports -------------------- - gt3_gttxreset_in => gt3_gttxreset_in, - gt3_txuserrdy_in => gt_txuserrdy_in(3), - ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- - gt3_txusrclk_in => gt0_txusrclk_in, - gt3_txusrclk2_in => gt0_txusrclk_in, - ------------------ Transmit Ports - TX Data Path interface ----------------- - gt3_txdata_in => TX_DATA_gt3_20b, - ---------------- Transmit Ports - TX Driver and OOB signaling -------------- - gt3_gthtxn_out => TXN_OUT(3), - gt3_gthtxp_out => TXP_OUT(3), - ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- - gt3_txoutclk_out => gt3_txoutclk_out, - gt3_txoutclkfabric_out => open,--gt3_txoutclkfabric_out, - gt3_txoutclkpcs_out => open,--gt3_txoutclkpcs_out, - ------------- Transmit Ports - TX Initialization and Reset Ports ----------- - gt3_txresetdone_out => gt_txresetdone_out(3), - gt3_rxphmonitor_out => open, - gt3_rxphslipmonitor_out => open, - --____________________________COMMON PORTS________________________________ - - GT0_QPLLLOCK_IN => GT0_QPLLLOCK_I, - GT0_QPLLREFCLKLOST_IN => GT0_QPLLREFCLKLOST_I, - GT0_QPLLRESET_OUT => GT0_QPLLRESET_I, - GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_I, - GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_I + SYSCLK_IN => DRP_CLK_IN, + SOFT_RESET_TX_IN => SOFT_TXRST_ALL, + SOFT_RESET_RX_IN => SOFT_RXRST_ALL, + DONT_RESET_ON_DATA_ERROR_IN => '1', + GT0_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(0), + GT0_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(0), + GT0_DATA_VALID_IN => '1', + GT1_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(1), + GT1_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(1), + GT1_DATA_VALID_IN => '1', + GT2_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(2), + GT2_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(2), + GT2_DATA_VALID_IN => '1', + GT3_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(3), + GT3_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(3), + GT3_DATA_VALID_IN => '1', + gt0_cpllfbclklost_out => gt_cpllfbclklost_i(0), + gt0_cplllock_out => gt_cplllock_i(0), + gt0_cplllockdetclk_in => DRP_CLK_IN, + gt0_cpllreset_in => gt_cpllreset_in(0), + gt0_gtrefclk0_in => tied_to_ground_i, + gt0_gtrefclk1_in => GTH_RefClk, + gt0_drpaddr_in => (others => '0'), --gt0_drpaddr_in, + gt0_drpclk_in => DRP_CLK_IN, + gt0_drpdi_in => (others => '0'), --gt0_drpdi_in, + gt0_drpdo_out => open, --gt0_drpdo_out, + gt0_drpen_in => '0', --gt0_drpen_in, + gt0_drprdy_out => open, --gt0_drprdy_out, + gt0_drpwe_in => '0', --gt0_drpwe_in, + gt0_eyescanreset_in => '0', + gt0_rxuserrdy_in => gt_rxuserrdy_in(0), + gt0_eyescandataerror_out => open, + gt0_eyescantrigger_in => '0', + gt0_dmonitorout_out => open, + gt0_rxusrclk_in => gt0_rxusrclk_in, + gt0_rxusrclk2_in => gt0_rxusrclk_in, + gt0_rxdata_out => gt0_rxdata_out, --RX_DATA_gt0_20b, + gt0_rxdisperr_out => gt0_rxdisperr_out, + gt0_rxnotintable_out => gt0_rxnotintable_out, + gt0_gthrxn_in => RXN_IN(0), + gt0_rxphmonitor_out => open, + gt0_rxphslipmonitor_out => open, + gt0_rxbyteisaligned_out => gt_rxbyteisaligned_out(0), + gt0_rxmcommaalignen_in => '0', --gt0_rxmcommaalignen_in, + gt0_rxpcommaalignen_in => '1', --gt0_rxpcommaalignen_in, + gt0_rxmonitorout_out => open, + gt0_rxmonitorsel_in => "00", + gt0_rxoutclk_out => gt0_rxoutclk_out, + gt0_rxoutclkfabric_out => open, --gt0_rxoutclkfabric_out, + gt0_gtrxreset_in => gt0_gtrxreset_in, + gt0_rxcharisk_out => gt0_rxcharisk_out, + gt0_gthrxp_in => RXP_IN(0), + gt0_rxresetdone_out => gt_rxresetdone_out(0), -- gt0_rxresetdone_out, + gt0_gttxreset_in => gt0_gttxreset_in, + gt0_txuserrdy_in => gt_txuserrdy_in(0), + gt0_txusrclk_in => gt0_txusrclk_in, + gt0_txusrclk2_in => gt0_txusrclk_in, + gt0_txdata_in => TX_DATA_gt0_20b, + gt0_gthtxn_out => TXN_OUT(0), + gt0_gthtxp_out => TXP_OUT(0), + gt0_txoutclk_out => gt0_txoutclk_out, + gt0_txoutclkfabric_out => open, --gt0_txoutclkfabric_out, + gt0_txoutclkpcs_out => open, --gt0_txoutclkpcs_out, + gt0_txresetdone_out => gt_txresetdone_out(0), + gt1_cpllfbclklost_out => gt_cpllfbclklost_i(1), + gt1_cplllock_out => gt_cplllock_i(1), + gt1_cplllockdetclk_in => DRP_CLK_IN, + gt1_cpllreset_in => gt_cpllreset_in(1), + gt1_gtrefclk0_in => tied_to_ground_i, + gt1_gtrefclk1_in => GTH_RefClk, + gt1_drpaddr_in => (others => '0'), + gt1_drpclk_in => DRP_CLK_IN, + gt1_drpdi_in => (others => '0'), + gt1_drpdo_out => open, + gt1_drpen_in => '0', + gt1_drprdy_out => open, + gt1_drpwe_in => '0', + gt1_eyescanreset_in => '0', + gt1_rxuserrdy_in => gt_rxuserrdy_in(1), + gt1_eyescandataerror_out => open, + gt1_eyescantrigger_in => '0', + gt1_dmonitorout_out => open, + gt1_rxusrclk_in => gt1_rxusrclk_in, + gt1_rxusrclk2_in => gt1_rxusrclk_in, + gt1_rxdata_out => gt1_rxdata_out, --RX_DATA_gt1_20b, + gt1_rxdisperr_out => gt1_rxdisperr_out, + gt1_rxnotintable_out => gt1_rxnotintable_out, + gt1_gthrxn_in => RXN_IN(1), + gt1_rxphmonitor_out => open, + gt1_rxphslipmonitor_out => open, + gt1_rxbyteisaligned_out => gt_rxbyteisaligned_out(1), + gt1_rxmcommaalignen_in => '0', --gt0_rxmcommaalignen_in, + gt1_rxpcommaalignen_in => '1', --gt0_rxpcommaalignen_in, + gt1_rxmonitorout_out => open, + gt1_rxmonitorsel_in => "00", + gt1_rxoutclk_out => gt1_rxoutclk_out, + gt1_rxoutclkfabric_out => open, --gt0_rxoutclkfabric_out, + gt1_gtrxreset_in => gt1_gtrxreset_in, + gt1_rxcharisk_out => gt1_rxcharisk_out, + gt1_gthrxp_in => RXP_IN(1), + gt1_rxresetdone_out => gt_rxresetdone_out(1), + gt1_gttxreset_in => gt1_gttxreset_in, + gt1_txuserrdy_in => gt_txuserrdy_in(1), + gt1_txusrclk_in => gt0_txusrclk_in, + gt1_txusrclk2_in => gt0_txusrclk_in, + gt1_txdata_in => TX_DATA_gt1_20b, + gt1_gthtxn_out => TXN_OUT(1), + gt1_gthtxp_out => TXP_OUT(1), + gt1_txoutclk_out => gt1_txoutclk_out, + gt1_txoutclkfabric_out => open, --gt1_txoutclkfabric_out, + gt1_txoutclkpcs_out => open, --gt1_txoutclkpcs_out, + gt1_txresetdone_out => gt_txresetdone_out(1), + gt2_cpllfbclklost_out => gt_cpllfbclklost_i(2), + gt2_cplllock_out => gt_cplllock_i(2), + gt2_cplllockdetclk_in => DRP_CLK_IN, + gt2_cpllreset_in => gt_cpllreset_in(2), + gt2_gtrefclk0_in => tied_to_ground_i, + gt2_gtrefclk1_in => GTH_RefClk, + gt2_drpaddr_in => (others => '0'), + gt2_drpclk_in => DRP_CLK_IN, + gt2_drpdi_in => (others => '0'), + gt2_drpdo_out => open, + gt2_drpen_in => '0', + gt2_drprdy_out => open, + gt2_drpwe_in => '0', + gt2_eyescanreset_in => '0', + gt2_rxuserrdy_in => gt_rxuserrdy_in(2), + gt2_eyescandataerror_out => open, + gt2_eyescantrigger_in => '0', + gt2_dmonitorout_out => open, + gt2_rxusrclk_in => gt2_rxusrclk_in, + gt2_rxusrclk2_in => gt2_rxusrclk_in, + gt2_rxdata_out => gt2_rxdata_out, --RX_DATA_gt2_20b, + gt2_rxdisperr_out => gt2_rxdisperr_out, + gt2_rxnotintable_out => gt2_rxnotintable_out, + gt2_gthrxn_in => RXN_IN(2), + gt2_rxphmonitor_out => open, + gt2_rxphslipmonitor_out => open, + gt2_rxbyteisaligned_out => gt_rxbyteisaligned_out(2), + gt2_rxmcommaalignen_in => '0', --gt0_rxmcommaalignen_in, + gt2_rxpcommaalignen_in => '1', --gt0_rxpcommaalignen_in, + gt2_rxmonitorout_out => open, + gt2_rxmonitorsel_in => "00", + gt2_rxoutclk_out => gt2_rxoutclk_out, + gt2_rxoutclkfabric_out => open, --gt0_rxoutclkfabric_out, + gt2_gtrxreset_in => gt2_gtrxreset_in, + gt2_rxcharisk_out => gt2_rxcharisk_out, + gt2_gthrxp_in => RXP_IN(2), + gt2_rxresetdone_out => gt_rxresetdone_out(2), + gt2_gttxreset_in => gt2_gttxreset_in, + gt2_txuserrdy_in => gt_txuserrdy_in(2), + gt2_txusrclk_in => gt0_txusrclk_in, + gt2_txusrclk2_in => gt0_txusrclk_in, + gt2_txdata_in => TX_DATA_gt2_20b, + gt2_gthtxn_out => TXN_OUT(2), + gt2_gthtxp_out => TXP_OUT(2), + gt2_txoutclk_out => gt2_txoutclk_out, + gt2_txoutclkfabric_out => open, --gt2_txoutclkfabric_out, + gt2_txoutclkpcs_out => open, --gt2_txoutclkpcs_out, + gt2_txresetdone_out => gt_txresetdone_out(2), + gt3_cpllfbclklost_out => gt_cpllfbclklost_i(3), + gt3_cplllock_out => gt_cplllock_i(3), + gt3_cplllockdetclk_in => DRP_CLK_IN, + gt3_cpllreset_in => gt_cpllreset_in(3), + gt3_gtrefclk0_in => tied_to_ground_i, + gt3_gtrefclk1_in => GTH_RefClk, + gt3_drpaddr_in => (others => '0'), + gt3_drpclk_in => DRP_CLK_IN, + gt3_drpdi_in => (others => '0'), + gt3_drpdo_out => open, + gt3_drpen_in => '0', + gt3_drprdy_out => open, + gt3_drpwe_in => '0', + gt3_eyescanreset_in => '0', + gt3_rxuserrdy_in => gt_rxuserrdy_in(3), + gt3_eyescandataerror_out => open, + gt3_eyescantrigger_in => '0', + gt3_dmonitorout_out => open, + gt3_rxusrclk_in => gt3_rxusrclk_in, + gt3_rxusrclk2_in => gt3_rxusrclk_in, + gt3_rxdata_out => gt3_rxdata_out, --RX_DATA_gt3_20b, + gt3_rxdisperr_out => gt3_rxdisperr_out, + gt3_rxnotintable_out => gt3_rxnotintable_out, + gt3_gthrxn_in => RXN_IN(3), + gt3_rxphmonitor_out => open, + gt3_rxphslipmonitor_out => open, + gt3_rxbyteisaligned_out => gt_rxbyteisaligned_out(3), + gt3_rxmcommaalignen_in => '0', --gt0_rxmcommaalignen_in, + gt3_rxpcommaalignen_in => '1', --gt0_rxpcommaalignen_in, + gt3_rxmonitorout_out => open, + gt3_rxmonitorsel_in => "00", + gt3_rxoutclk_out => gt3_rxoutclk_out, + gt3_rxoutclkfabric_out => open, --gt0_rxoutclkfabric_out, + gt3_gtrxreset_in => gt3_gtrxreset_in, + gt3_rxcharisk_out => gt3_rxcharisk_out, + gt3_gthrxp_in => RXP_IN(3), + gt3_rxresetdone_out => gt_rxresetdone_out(3), + gt3_gttxreset_in => gt3_gttxreset_in, + gt3_txuserrdy_in => gt_txuserrdy_in(3), + gt3_txusrclk_in => gt0_txusrclk_in, + gt3_txusrclk2_in => gt0_txusrclk_in, + gt3_txdata_in => TX_DATA_gt3_20b, + gt3_gthtxn_out => TXN_OUT(3), + gt3_gthtxp_out => TXP_OUT(3), + gt3_txoutclk_out => gt3_txoutclk_out, + gt3_txoutclkfabric_out => open, --gt3_txoutclkfabric_out, + gt3_txoutclkpcs_out => open, --gt3_txoutclkpcs_out, + gt3_txresetdone_out => gt_txresetdone_out(3), + GT0_QPLLLOCK_IN => GT0_QPLLLOCK_I, + GT0_QPLLREFCLKLOST_IN => GT0_QPLLREFCLKLOST_I, + GT0_QPLLRESET_OUT => GT0_QPLLRESET_I, + GT0_QPLLOUTCLK_IN => gt0_qplloutclk_i, + GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_I ); diff --git a/sources/FullModeWrapper/gth_fullmode_wrapper_vup.vhd b/sources/FullModeWrapper/gth_fullmode_wrapper_vup.vhd index af5dba7c27a5d6c35a02bd818b5b56fb96fa3e43..3e3fc13d1e00a7adf203255662c299e298463016 100644 --- a/sources/FullModeWrapper/gth_fullmode_wrapper_vup.vhd +++ b/sources/FullModeWrapper/gth_fullmode_wrapper_vup.vhd @@ -242,114 +242,114 @@ COMPONENT gtwizard_fullmode_txcpll_rxqpll_vup ); END COMPONENT; -component vio_gbt_chk IS -PORT ( -clk : IN STD_LOGIC; -probe_in0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in5 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in6 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in7 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in8 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in9 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in10 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_in12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_in13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_in14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_in15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_in16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_in17 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in18 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in19 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in20 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in21 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_in22 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_out2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -probe_out3 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) -); -END component; - -component ila_gbt_chk IS -PORT ( -clk : IN STD_LOGIC; -probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -probe2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -probe3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -probe4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe5 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe6 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe7 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe8 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe9 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe10 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -probe11 : IN STD_LOGIC_VECTOR(3 DOWNTO 0) -); -END component; +--component vio_gbt_chk IS +--PORT ( +--clk : IN STD_LOGIC; +--probe_in0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in5 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in6 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in7 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in8 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in9 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in10 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); +--probe_in12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); +--probe_in13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); +--probe_in14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); +--probe_in15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); +--probe_in16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); +--probe_in17 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in18 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in19 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in20 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in21 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_in22 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); +--probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); +--probe_out2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe_out3 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); +--probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); +--probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); +--probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); +--probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) +--); +--END component; + +--component ila_gbt_chk IS +--PORT ( +--clk : IN STD_LOGIC; +--probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); +--probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); +--probe2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); +--probe3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); +--probe4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe5 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe6 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe7 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe8 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe9 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe10 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); +--probe11 : IN STD_LOGIC_VECTOR(3 DOWNTO 0) +--); +--END component; -signal GT0_QPLLLOCK_I: std_logic:='0'; -signal gt0_gttxreset_in : std_logic:='0'; -signal gt1_gttxreset_in : std_logic:='0'; -signal gt2_gttxreset_in : std_logic:='0'; -signal gt3_gttxreset_in : std_logic:='0'; -signal gt0_gtrxreset_in : std_logic:='0'; -signal gt1_gtrxreset_in : std_logic:='0'; -signal gt2_gtrxreset_in : std_logic:='0'; -signal gt3_gtrxreset_in : std_logic:='0'; +--signal GT0_QPLLLOCK_I: std_logic:='0'; +--signal gt0_gttxreset_in : std_logic:='0'; +--signal gt1_gttxreset_in : std_logic:='0'; +--signal gt2_gttxreset_in : std_logic:='0'; +--signal gt3_gttxreset_in : std_logic:='0'; +--signal gt0_gtrxreset_in : std_logic:='0'; +--signal gt1_gtrxreset_in : std_logic:='0'; +--signal gt2_gtrxreset_in : std_logic:='0'; +--signal gt3_gtrxreset_in : std_logic:='0'; -signal gt0_qplloutclk_i:std_logic; +--signal gt0_qplloutclk_i:std_logic; signal tied_to_ground_i : std_logic_vector(0 downto 0); -signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); -signal tied_to_vcc_i : std_logic_vector(0 downto 0); -signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0); +--signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); +--signal tied_to_vcc_i : std_logic_vector(0 downto 0); +--signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0); signal tied_to_vcc_vec : std_logic_vector(3 downto 0); -signal gt0_drpaddr_in, gt1_drpaddr_in, gt2_drpaddr_in, gt3_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; -signal gt0_drpdi_in, gt1_drpdi_in, gt2_drpdi_in, gt3_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; -signal gt0_drpdo_out, gt1_drpdo_out, gt2_drpdo_out, gt3_drpdo_out : std_logic_vector(15 downto 0); -signal gt0_drpen_in, gt1_drpen_in,gt2_drpen_in,gt3_drpen_in:std_logic:='0'; -signal gt0_drprdy_out, gt1_drprdy_out,gt2_drprdy_out,gt3_drprdy_out:std_logic; -signal gt0_drpwe_in, gt1_drpwe_in,gt2_drpwe_in,gt3_drpwe_in:std_logic:='0'; - -signal GT0_QPLLREFCLKLOST_I, GT0_QPLLRESET_I,GT0_QPLLOUTREFCLK_I:std_logic; - -signal SOFT_RESET_RX_IN_VIO : std_logic_vector(0 downto 0); -signal gt0_rxdata_out, gt0_rxdata_chk : std_logic_vector(31 downto 0); -signal gt1_rxdata_out,gt1_rxdata_out_r, gt1_rxdata_chk,gt1_rxdata_chk_r : std_logic_vector(31 downto 0); -signal gt2_rxdata_out,gt2_rxdata_out_r, gt2_rxdata_chk,gt2_rxdata_chk_r : std_logic_vector(31 downto 0); -signal gt3_rxdata_out, gt3_rxdata_chk,gt3_rxdata_chk_r : std_logic_vector(31 downto 0); - -signal gt0_rxcharisk_out : std_logic_vector(3 downto 0); -signal gt1_rxcharisk_out : std_logic_vector(3 downto 0); -signal gt2_rxcharisk_out : std_logic_vector(3 downto 0); -signal gt3_rxcharisk_out : std_logic_vector(3 downto 0); +--signal gt0_drpaddr_in, gt1_drpaddr_in, gt2_drpaddr_in, gt3_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; +--signal gt0_drpdi_in, gt1_drpdi_in, gt2_drpdi_in, gt3_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; +--signal gt0_drpdo_out, gt1_drpdo_out, gt2_drpdo_out, gt3_drpdo_out : std_logic_vector(15 downto 0); +--signal gt0_drpen_in, gt1_drpen_in,gt2_drpen_in,gt3_drpen_in:std_logic:='0'; +--signal gt0_drprdy_out, gt1_drprdy_out,gt2_drprdy_out,gt3_drprdy_out:std_logic; +--signal gt0_drpwe_in, gt1_drpwe_in,gt2_drpwe_in,gt3_drpwe_in:std_logic:='0'; + +--signal GT0_QPLLREFCLKLOST_I, GT0_QPLLRESET_I,GT0_QPLLOUTREFCLK_I:std_logic; + +--signal SOFT_RESET_RX_IN_VIO : std_logic_vector(0 downto 0); +--signal gt0_rxdata_out, gt0_rxdata_chk : std_logic_vector(31 downto 0); +--signal gt1_rxdata_out,gt1_rxdata_out_r, gt1_rxdata_chk,gt1_rxdata_chk_r : std_logic_vector(31 downto 0); +--signal gt2_rxdata_out,gt2_rxdata_out_r, gt2_rxdata_chk,gt2_rxdata_chk_r : std_logic_vector(31 downto 0); +--signal gt3_rxdata_out, gt3_rxdata_chk,gt3_rxdata_chk_r : std_logic_vector(31 downto 0); + +--signal gt0_rxcharisk_out : std_logic_vector(3 downto 0); +--signal gt1_rxcharisk_out : std_logic_vector(3 downto 0); +--signal gt2_rxcharisk_out : std_logic_vector(3 downto 0); +--signal gt3_rxcharisk_out : std_logic_vector(3 downto 0); signal rx_data_gt0_33b_i : std_logic_vector(32 downto 0); signal rx_data_gt1_33b_i : std_logic_vector(32 downto 0); signal rx_data_gt2_33b_i : std_logic_vector(32 downto 0); signal rx_data_gt3_33b_i : std_logic_vector(32 downto 0); -signal gt_cplllock_i : std_logic_vector(3 downto 0); -signal gt_cpllfbclklost_i : std_logic_vector(3 downto 0); +--signal gt_cplllock_i : std_logic_vector(3 downto 0); +--signal gt_cpllfbclklost_i : std_logic_vector(3 downto 0); signal rxctrl0_out : std_logic_vector(63 downto 0); signal rxctrl1_out : std_logic_vector(63 downto 0); -signal rxctrl2_out : std_logic_vector(31 downto 0); -signal rxctrl3_out : std_logic_vector(31 downto 0); -signal rxcommadet_out : std_logic_vector(3 downto 0); -signal rxcdrlock_out : std_logic_vector(3 downto 0); +--signal rxctrl2_out : std_logic_vector(31 downto 0); +--signal rxctrl3_out : std_logic_vector(31 downto 0); +--signal rxcommadet_out : std_logic_vector(3 downto 0); +--signal rxcdrlock_out : std_logic_vector(3 downto 0); signal rxbyteisaligned_out : std_logic_vector(3 downto 0); -signal rxbyterealign_out : std_logic_vector(3 downto 0); +--signal rxbyterealign_out : std_logic_vector(3 downto 0); --signal cpllreset_in : std_logic_vector(3 downto 0); signal userclk_tx_active_out : std_logic_vector(0 downto 0); @@ -364,22 +364,22 @@ signal txpmaresetdone_out : std_logic_vector(3 downto 0); signal cplllock_out : std_logic_vector(3 downto 0); signal cpllfbclklost_out : std_logic_vector(3 downto 0); -signal reset_tx_done_out : std_logic_vector(0 downto 0); -signal reset_rx_done_out : std_logic_vector(0 downto 0); +--signal reset_tx_done_out : std_logic_vector(0 downto 0); +--signal reset_rx_done_out : std_logic_vector(0 downto 0); signal reset_all : std_logic_vector(0 downto 0); -signal buffbypass_tx_reset_in : std_logic_vector(0 downto 0); +--signal buffbypass_tx_reset_in : std_logic_vector(0 downto 0); signal userdata_rx_out : std_logic_vector(127 downto 0); -signal buffbypass_tx_error : std_logic_vector(0 downto 0); -signal buffbypass_tx_done : std_logic_vector(0 downto 0); +--signal buffbypass_tx_error : std_logic_vector(0 downto 0); +--signal buffbypass_tx_done : std_logic_vector(0 downto 0); signal reset_tx_pll_and_datapath : std_logic_vector(0 downto 0); signal reset_tx_datapath : std_logic_vector(0 downto 0); signal reset_rx_pll_and_datapath : std_logic_vector(0 downto 0); signal reset_rx_datapath : std_logic_vector(0 downto 0); -signal reset_cdr_stable : std_logic_vector(0 downto 0); +--signal reset_cdr_stable : std_logic_vector(0 downto 0); signal gt_drp_clk_in : std_logic_vector(0 downto 0); signal gtrefclk01_in : std_logic_vector(0 downto 0); @@ -393,36 +393,36 @@ signal txoutclk_out : std_logic_vector(3 downto 0); signal gt_drp_clk_vec : std_logic_vector(3 downto 0); signal qpll1lock_out : std_logic_vector(0 downto 0); -signal comma_8b10b_deted0 : std_logic_vector(3 downto 0); -signal comma_8b10b_deted1 : std_logic_vector(3 downto 0); -signal comma_8b10b_deted2 : std_logic_vector(3 downto 0); -signal comma_8b10b_deted3 : std_logic_vector(3 downto 0); +--signal comma_8b10b_deted0 : std_logic_vector(3 downto 0); +--signal comma_8b10b_deted1 : std_logic_vector(3 downto 0); +--signal comma_8b10b_deted2 : std_logic_vector(3 downto 0); +--signal comma_8b10b_deted3 : std_logic_vector(3 downto 0); -signal comma_deted0 : std_logic_vector(3 downto 0); -signal comma_deted1 : std_logic_vector(3 downto 0); -signal comma_deted2 : std_logic_vector(3 downto 0); -signal comma_deted3 : std_logic_vector(3 downto 0); +--signal comma_deted0 : std_logic_vector(3 downto 0); +--signal comma_deted1 : std_logic_vector(3 downto 0); +--signal comma_deted2 : std_logic_vector(3 downto 0); +--signal comma_deted3 : std_logic_vector(3 downto 0); -signal rxdata0 : std_logic_vector(31 downto 0); -signal rxdata1 : std_logic_vector(31 downto 0); -signal rxdata2 : std_logic_vector(31 downto 0); -signal rxdata3 : std_logic_vector(31 downto 0); +--signal rxdata0 : std_logic_vector(31 downto 0); +--signal rxdata1 : std_logic_vector(31 downto 0); +--signal rxdata2 : std_logic_vector(31 downto 0); +--signal rxdata3 : std_logic_vector(31 downto 0); -signal disp_err0 : std_logic_vector(3 downto 0); -signal disp_err1 : std_logic_vector(3 downto 0); -signal disp_err2 : std_logic_vector(3 downto 0); -signal disp_err3 : std_logic_vector(3 downto 0); +--signal disp_err0 : std_logic_vector(3 downto 0); +--signal disp_err1 : std_logic_vector(3 downto 0); +--signal disp_err2 : std_logic_vector(3 downto 0); +--signal disp_err3 : std_logic_vector(3 downto 0); -signal comma_not_tab0 : std_logic_vector(3 downto 0); -signal comma_not_tab1 : std_logic_vector(3 downto 0); -signal comma_not_tab2 : std_logic_vector(3 downto 0); -signal comma_not_tab3 : std_logic_vector(3 downto 0); +--signal comma_not_tab0 : std_logic_vector(3 downto 0); +--signal comma_not_tab1 : std_logic_vector(3 downto 0); +--signal comma_not_tab2 : std_logic_vector(3 downto 0); +--signal comma_not_tab3 : std_logic_vector(3 downto 0); -signal lmk_reset_out : std_logic_vector(0 downto 0); +--signal lmk_reset_out : std_logic_vector(0 downto 0); -signal gt_reset_tx_done : std_logic_vector(3 downto 0); -signal gt_reset_rx_done : std_logic_vector(3 downto 0); +--signal gt_reset_tx_done : std_logic_vector(3 downto 0); +--signal gt_reset_rx_done : std_logic_vector(3 downto 0); signal gtwiz_userdata_tx_in : std_logic_vector(79 downto 0); --**************************** Main Body of Code ******************************* @@ -484,10 +484,10 @@ begin end process; tied_to_ground_i <= "0"; - tied_to_ground_vec_i <= x"0000000000000000"; - tied_to_vcc_i <= "1"; + --tied_to_ground_vec_i <= x"0000000000000000"; + --tied_to_vcc_i <= "1"; tied_to_vcc_vec <= x"f"; - tied_to_vcc_vec_i <= x"ff"; + --tied_to_vcc_vec_i <= x"ff"; gt_drp_clk_in(0) <= DRP_CLK_IN; gtrefclk0_in(0) <= GTH_RefClk; @@ -565,67 +565,62 @@ end generate; gtwiz_userdata_tx_in <= TX_DATA_gt3_20b & TX_DATA_gt2_20b & TX_DATA_gt1_20b & TX_DATA_gt0_20b; gth_fullmode_ultrascale_inst: gtwizard_fullmode_txcpll_rxqpll_vup port map( - gtwiz_userclk_tx_reset_in => "0", - gtwiz_userclk_rx_reset_in => "0", - gtwiz_userclk_tx_active_in => userclk_tx_active_out, - gtwiz_userclk_rx_active_in => userclk_rx_active_out, - gtwiz_buffbypass_tx_reset_in => tied_to_ground_i, --buffbypass_tx_reset_in, - gtwiz_buffbypass_tx_start_user_in => tied_to_ground_i, - gtwiz_buffbypass_tx_done_out => open, --buffbypass_tx_done, - gtwiz_buffbypass_tx_error_out => open, --buffbypass_tx_error, - gtwiz_reset_clk_freerun_in => gt_drp_clk_in, - gtwiz_reset_all_in => reset_all, - gtwiz_reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath, - gtwiz_reset_tx_datapath_in => reset_tx_datapath, - gtwiz_reset_rx_pll_and_datapath_in => reset_rx_pll_and_datapath, - gtwiz_reset_rx_datapath_in => reset_rx_datapath, - gtwiz_reset_rx_cdr_stable_out => reset_cdr_stable, - gtwiz_reset_tx_done_out => reset_tx_done_out, - gtwiz_reset_rx_done_out => reset_rx_done_out, - gtwiz_userdata_tx_in => gtwiz_userdata_tx_in, - gtwiz_userdata_rx_out => userdata_rx_out, - - gtrefclk01_in => gtrefclk01_in, - qpll1lock_out => qpll1lock_out, - qpll1outclk_out => open, - qpll1outrefclk_out => open, - - cplllockdetclk_in => gt_drp_clk_vec, --gt_drp_clk_in, - cpllreset_in => cpllreset_in, - drpclk_in => gt_drp_clk_vec, - gtyrxn_in => RXN_IN, - gtyrxp_in => RXP_IN, - gtrefclk0_in => gtrefclk0_in, - - rx8b10ben_in => tied_to_vcc_vec, - rxcommadeten_in => rxcommadeten_in,--tied_to_vcc_vec, - rxmcommaalignen_in => tied_to_vcc_vec, - rxpcommaalignen_in => tied_to_vcc_vec, - - rxusrclk_in => rxusrclk_in, - rxusrclk2_in => rxusrclk_in, - txusrclk_in => txusrclk_in, - txusrclk2_in => txusrclk_in, - cpllfbclklost_out => cpllfbclklost_out, - cplllock_out => cplllock_out, - gtytxn_out => TXN_OUT, - gtytxp_out => TXP_OUT, - rxbyteisaligned_out => rxbyteisaligned_out, - rxbyterealign_out => open, --rxbyterealign_out, - rxcdrlock_out => rxcdrlock_out, - rxcommadet_out => open, --rxcommadet_out, - - rxctrl0_out => rxctrl0_out, - rxctrl1_out => rxctrl1_out, - rxctrl2_out => rxctrl2_out, - rxctrl3_out => rxctrl3_out, - - rxoutclk_out => rxoutclk_out, - rxpmaresetdone_out => rxpmaresetdone_out, - rxresetdone_out => rxresetdone_out, - txoutclk_out => txoutclk_out, - txpmaresetdone_out => txpmaresetdone_out, - txresetdone_out => txresetdone_out + gtwiz_userclk_tx_reset_in => "0", + gtwiz_userclk_tx_active_in => userclk_tx_active_out, + gtwiz_userclk_rx_reset_in => "0", + gtwiz_userclk_rx_active_in => userclk_rx_active_out, + gtwiz_buffbypass_tx_reset_in => tied_to_ground_i, --buffbypass_tx_reset_in, + gtwiz_buffbypass_tx_start_user_in => tied_to_ground_i, + gtwiz_buffbypass_tx_done_out => open, --buffbypass_tx_done, + gtwiz_buffbypass_tx_error_out => open, --buffbypass_tx_error, + gtwiz_reset_clk_freerun_in => gt_drp_clk_in, + gtwiz_reset_all_in => reset_all, + gtwiz_reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath, + gtwiz_reset_tx_datapath_in => reset_tx_datapath, + gtwiz_reset_rx_pll_and_datapath_in => reset_rx_pll_and_datapath, + gtwiz_reset_rx_datapath_in => reset_rx_datapath, + gtwiz_reset_rx_cdr_stable_out => open, + gtwiz_reset_tx_done_out => open, + gtwiz_reset_rx_done_out => open, + gtwiz_userdata_tx_in => gtwiz_userdata_tx_in, + gtwiz_userdata_rx_out => userdata_rx_out, + gtrefclk01_in => gtrefclk01_in, + qpll1lock_out => qpll1lock_out, + qpll1outclk_out => open, + qpll1outrefclk_out => open, + cplllockdetclk_in => gt_drp_clk_vec, --gt_drp_clk_in, + cpllreset_in => cpllreset_in, + drpclk_in => gt_drp_clk_vec, + gtrefclk0_in => gtrefclk0_in, + gtyrxn_in => RXN_IN, + gtyrxp_in => RXP_IN, + rx8b10ben_in => tied_to_vcc_vec, + rxcommadeten_in => rxcommadeten_in, --tied_to_vcc_vec, + rxmcommaalignen_in => tied_to_vcc_vec, + rxpcommaalignen_in => tied_to_vcc_vec, + rxusrclk_in => rxusrclk_in, + rxusrclk2_in => rxusrclk_in, + txusrclk_in => txusrclk_in, + txusrclk2_in => txusrclk_in, + cpllfbclklost_out => cpllfbclklost_out, + cplllock_out => cplllock_out, + gtpowergood_out => open, + gtytxn_out => TXN_OUT, + gtytxp_out => TXP_OUT, + rxbyteisaligned_out => rxbyteisaligned_out, + rxbyterealign_out => open, --rxbyterealign_out, + rxcdrlock_out => open, + rxcommadet_out => open, --rxcommadet_out, + rxctrl0_out => rxctrl0_out, + rxctrl1_out => rxctrl1_out, + rxctrl2_out => open, + rxctrl3_out => open, + rxoutclk_out => rxoutclk_out, + rxpmaresetdone_out => rxpmaresetdone_out, + rxresetdone_out => rxresetdone_out, + txoutclk_out => txoutclk_out, + txpmaresetdone_out => txpmaresetdone_out, + txresetdone_out => txresetdone_out ); gt_cpllfbclklost_out <= cpllfbclklost_out; @@ -682,20 +677,20 @@ gt_qplllock_out <= qpll1lock_out(0); --comma_not_tab2 <= rxctrl3_out(3 downto 0); --comma_not_tab3 <= rxctrl3_out(3 downto 0); -comma_8b10b_deted0 <= rxctrl0_out(3 downto 0); -comma_8b10b_deted1 <= rxctrl0_out(19 downto 16); -comma_8b10b_deted2 <= rxctrl0_out(35 downto 32); -comma_8b10b_deted3 <= rxctrl0_out(51 downto 48); +--comma_8b10b_deted0 <= rxctrl0_out(3 downto 0); +--comma_8b10b_deted1 <= rxctrl0_out(19 downto 16); +--comma_8b10b_deted2 <= rxctrl0_out(35 downto 32); +--comma_8b10b_deted3 <= rxctrl0_out(51 downto 48); -comma_deted0 <= rxctrl2_out(3 downto 0); -comma_deted1 <= rxctrl2_out(11 downto 8); -comma_deted2 <= rxctrl2_out(19 downto 16); -comma_deted3 <= rxctrl2_out(27 downto 24); +--comma_deted0 <= rxctrl2_out(3 downto 0); +--comma_deted1 <= rxctrl2_out(11 downto 8); +--comma_deted2 <= rxctrl2_out(19 downto 16); +--comma_deted3 <= rxctrl2_out(27 downto 24); -rxdata0 <= userdata_rx_out(31 downto 0); -rxdata1 <= userdata_rx_out(31 downto 0); -rxdata2 <= userdata_rx_out(31 downto 0); -rxdata3 <= userdata_rx_out(31 downto 0); +--rxdata0 <= userdata_rx_out(31 downto 0); +--rxdata1 <= userdata_rx_out(31 downto 0); +--rxdata2 <= userdata_rx_out(31 downto 0); +--rxdata3 <= userdata_rx_out(31 downto 0); --ila_gbt_chk_inst: ila_gbt_chk --PORT MAP( diff --git a/sources/GBT/gbt_code/FELIX_GBT_RXSLIDE_FSM.vhd b/sources/GBT/gbt_code/FELIX_GBT_RXSLIDE_FSM.vhd index 1945d890137362c0086c27ef62823d7d352769f4..af2307ee11b4fab36b7cd086f49ed86b25159381 100644 --- a/sources/GBT/gbt_code/FELIX_GBT_RXSLIDE_FSM.vhd +++ b/sources/GBT/gbt_code/FELIX_GBT_RXSLIDE_FSM.vhd @@ -31,7 +31,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values @@ -45,7 +45,7 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FELIX_GBT_RXSLIDE_FSM is Port ( alignment_chk_rst : out std_logic; - ext_trig_realign : in std_logic; + --ext_trig_realign : in std_logic; FSM_RST : in std_logic; FSM_CLK : in std_logic; GBT_LOCK : in std_logic; @@ -59,15 +59,15 @@ architecture Behavioral of FELIX_GBT_RXSLIDE_FSM is signal alignwait_done_p : std_logic:='0'; signal alignwait_done : std_logic:='0'; signal RxSlide_trig : std_logic:='0'; - signal RxSlide_trig_2 : std_logic:='0'; + --signal RxSlide_trig_2 : std_logic:='0'; signal RxSlide_done : std_logic:='0'; - signal waitcnt : std_logic:='0'; + --signal waitcnt : std_logic:='0'; signal alignwaitcnt : std_logic_vector(6 downto 0):="0000000"; - signal phase : std_logic_vector(10 downto 0):="00000000000"; + --signal phase : std_logic_vector(10 downto 0):="00000000000"; signal step : std_logic_vector(1 downto 0):="00"; - signal phase_data : std_logic_vector(9 downto 0):="0000000000"; - signal rstcnt : std_logic_vector(9 downto 0):="0000000000"; - signal cnt : integer:=0; + --signal phase_data : std_logic_vector(9 downto 0):="0000000000"; + --signal rstcnt : std_logic_vector(9 downto 0):="0000000000"; + --signal cnt : integer:=0; type fsmtype is (IDLE,ALIGN_DONE); signal RA_STATE : fsmtype; signal slide_vec : std_logic_vector(19 downto 0):=x"00000"; @@ -101,7 +101,7 @@ begin end if; RxSlide <= RxSlide_trig;-- or RxSlide_trig_2 ; - RxSlide_trig_2 <= slide_vec(9); + --RxSlide_trig_2 <= slide_vec(9); RxSlide_done <= slide_vec(19); end if; end process; @@ -129,7 +129,7 @@ begin --GBT_IS_LOCKED <= GBT_LOCK; if GBT_LOCK = '1' then RA_STATE <= ALIGN_DONE; - cnt <= 0; + --cnt <= 0; step <= "10"; else step <= "11"; @@ -161,7 +161,7 @@ begin RA_STATE <= ALIGN_DONE; end if; - when others => + when others => -- @suppress "Case statement contains all choices explicitly. You can safely remove the redundant 'others'" RA_STATE <= IDLE; step <= "10"; end case; diff --git a/sources/GBT/gbt_code/FELIX_GBT_RX_AUTO_RST.vhd b/sources/GBT/gbt_code/FELIX_GBT_RX_AUTO_RST.vhd index cae083c39e0e290b802a537a1f127d91d00172a9..befde932e77aaf39af2babb6d8bc0b85bdc0b0e0 100644 --- a/sources/GBT/gbt_code/FELIX_GBT_RX_AUTO_RST.vhd +++ b/sources/GBT/gbt_code/FELIX_GBT_RX_AUTO_RST.vhd @@ -31,7 +31,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values @@ -59,21 +59,21 @@ architecture Behavioral of FELIX_GBT_RX_AUTO_RST is signal AUTO_GBT_RXRST_p : std_logic:='0'; - signal GTHRXRESET_DONE_2r : std_logic:='0'; - signal GTHRXRESET_DONE_r : std_logic:='0'; + --signal GTHRXRESET_DONE_2r : std_logic:='0'; + --signal GTHRXRESET_DONE_r : std_logic:='0'; signal ext_trig_realign_p : std_logic:='0'; - signal ext_trig_realign_p_r : std_logic:='0'; + --signal ext_trig_realign_p_r : std_logic:='0'; signal long_counter16_2r : std_logic:='0'; signal long_counter16_r : std_logic:='0'; - signal AUTO_GBT_RXRST_p_r : std_logic:='0'; - signal AUTO_GTH_RXRST_p_r : std_logic:='0'; + --signal AUTO_GBT_RXRST_p_r : std_logic:='0'; + --signal AUTO_GTH_RXRST_p_r : std_logic:='0'; signal AUTO_GTH_RXRST_p : std_logic:='0'; signal alignment_chk_rst_p : std_logic:='0'; - signal alignment_chk_rst_p_r : std_logic:='0'; + --signal alignment_chk_rst_p_r : std_logic:='0'; signal wpulse : std_logic:='0'; - signal long_counter : std_logic_vector(26 downto 0):="000" & x"000000"; + --signal long_counter : std_logic_vector(26 downto 0):="000" & x"000000"; - signal AUTO_GBT_RXRST_p_vec : std_logic_vector(99 downto 0):=x"0000000000000000000000000"; + --signal AUTO_GBT_RXRST_p_vec : std_logic_vector(99 downto 0):=x"0000000000000000000000000"; type fsmtype is (IDLE, GTHRST,GBTRST,ALIGNRST); signal statusA : fsmtype:=IDLE; @@ -86,16 +86,16 @@ begin begin if FSM_CLK'event and FSM_CLK='1' then - AUTO_GTH_RXRST_p_r <= AUTO_GTH_RXRST_p; + --AUTO_GTH_RXRST_p_r <= AUTO_GTH_RXRST_p; AUTO_GTH_RXRST <= AUTO_GTH_RXRST_p;-- and (not AUTO_GTH_RXRST_p_r); - ext_trig_realign_p_r <= ext_trig_realign_p; + --ext_trig_realign_p_r <= ext_trig_realign_p; ext_trig_realign <= ext_trig_realign_p;-- and (not ext_trig_realign_p_r); - AUTO_GBT_RXRST_p_r <= AUTO_GBT_RXRST_p; + --AUTO_GBT_RXRST_p_r <= AUTO_GBT_RXRST_p; AUTO_GBT_RXRST <= AUTO_GBT_RXRST_p;-- and (not AUTO_GBT_RXRST_p_r); - alignment_chk_rst_p_r <= alignment_chk_rst_p; + --alignment_chk_rst_p_r <= alignment_chk_rst_p; alignment_chk_rst <= alignment_chk_rst_p;-- and (not alignment_chk_rst_p_r); long_counter16_2r <= long_counter16_r; @@ -148,7 +148,7 @@ begin AUTO_GTH_RXRST_p <= '0'; AUTO_GBT_RXRST_p <= '0'; ext_trig_realign_p <= '0'; - when others => + when others => -- @suppress "Case statement contains all choices explicitly. You can safely remove the redundant 'others'" statusA <= IDLE; end case; end if; diff --git a/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd b/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd index beb14886a3d7939bdc3a55f53845ec0dd113ff85..ee59fc72c5a2c777e6e0b322841dcb568ca14966 100644 --- a/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd +++ b/sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd @@ -1,4 +1,4 @@ ---!----------------------------------------------------------------------------- +--!----------------------------FA------------------------------------------------ --! -- --! BNL - Brookhaven National Lboratory -- --! Physics Department -- @@ -29,8 +29,8 @@ LIBRARY IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_ARITH.ALL;-- @suppress "Deprecated package" +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. @@ -39,1179 +39,1160 @@ use UNISIM.VComponents.all; use work.FELIX_gbt_package.all; use work.FELIX_package.all; use work.pcie_package.all; +use ieee.numeric_std.all; entity FELIX_gbt_wrapper_KCU is - Generic ( - STABLE_CLOCK_PERIOD : integer := 24; --period of the drp_clock - GBT_NUM : integer := 24; - GTHREFCLK_SEL : std_logic := '1'; --GREFCLK : std_logic := '1'; - --MGTREFCLK : std_logic := '0'; - CARD_TYPE : integer := 712; - PLL_SEL : std_logic := '0' -- CPLL : '0' - -- QPLL : '1' - --QUAD_NUM : integer := 6 + Generic ( + --STABLE_CLOCK_PERIOD : integer := 24; --period of the drp_clock + GBT_NUM : integer := 24; + GTHREFCLK_SEL : std_logic := '1'; --GREFCLK : std_logic := '1'; + --MGTREFCLK : std_logic := '0'; + CARD_TYPE : integer := 712; + PLL_SEL : std_logic := '0' -- CPLL : '0' + -- QPLL : '1' + --QUAD_NUM : integer := 6 + ); + Port ( + ------------------- + ---- For debug + ------------------- + -- For Debugging + RX_FLAG_O : out std_logic_vector(GBT_NUM-1 downto 0); + TX_FLAG_O : out std_logic_vector(GBT_NUM-1 downto 0); + REFCLK_CXP1 : out std_logic; + REFCLK_CXP2 : out std_logic; + + rst_hw : in std_logic; + + register_map_control : in register_map_control_type; + register_map_link_monitor : out register_map_link_monitor_type; + + -- GTH REFCLK, DRPCLK, GREFCLK + --DRP_CLK_IN : in std_logic; + Q2_CLK0_GTREFCLK_PAD_N_IN : in std_logic; + Q2_CLK0_GTREFCLK_PAD_P_IN : in std_logic; + Q8_CLK0_GTREFCLK_PAD_N_IN : in std_logic; + Q8_CLK0_GTREFCLK_PAD_P_IN : in std_logic; + Q4_CLK0_GTREFCLK_PAD_N_IN : in std_logic; + Q4_CLK0_GTREFCLK_PAD_P_IN : in std_logic; + Q5_CLK0_GTREFCLK_PAD_N_IN : in std_logic; + Q5_CLK0_GTREFCLK_PAD_P_IN : in std_logic; + Q6_CLK0_GTREFCLK_PAD_N_IN : in std_logic; + Q6_CLK0_GTREFCLK_PAD_P_IN : in std_logic; + --GREFCLK_IN : in std_logic; + + clk40_in : in std_logic; + --clk240_in : in std_logic; + -- for CentralRouter + TX_120b_in : in txrx120b_type(0 to GBT_NUM-1); + RX_120b_out : out txrx120b_type(0 to GBT_NUM-1); + FRAME_LOCKED_O : out std_logic_vector(GBT_NUM-1 downto 0); + -- TX_ISDATA_I : in std_logic_vector(GBT_NUM-1 downto 0); + -- RX_ISDATA_O : out std_logic_vector(GBT_NUM-1 downto 0); + -- RX_FRAME_CLK_O : out std_logic_vector(GBT_NUM-1 downto 0); + TX_FRAME_CLK_I : in std_logic_vector(GBT_NUM-1 downto 0); + + -- FIFO_RD_CLK : in std_logic_vector(GBT_NUM-1 downto 0); + -- FIFO_RD_EN : in std_logic_vector(GBT_NUM-1 downto 0); + -- FIFO_FULL : out std_logic_vector(GBT_NUM-1 downto 0); + -- FIFO_EMPTY : out std_logic_vector(GBT_NUM-1 downto 0); + + + -- GTH Data pins + TX_P : out std_logic_vector(GBT_NUM-1 downto 0); + TX_N : out std_logic_vector(GBT_NUM-1 downto 0); + RX_P : in std_logic_vector(GBT_NUM-1 downto 0); + RX_N : in std_logic_vector(GBT_NUM-1 downto 0); + RXUSRCLK_OUT : out std_logic_vector(GBT_NUM-1 downto 0) ); - Port ( -------------------- ----- For debug -------------------- - -- For Debugging - RX_FLAG_O : out std_logic_vector(GBT_NUM-1 downto 0); - TX_FLAG_O : out std_logic_vector(GBT_NUM-1 downto 0); - REFCLK_CXP1 : out std_logic; - REFCLK_CXP2 : out std_logic; - - rst_hw : in std_logic; - - register_map_control : in register_map_control_type; - register_map_link_monitor : out register_map_link_monitor_type; - - -- GTH REFCLK, DRPCLK, GREFCLK - DRP_CLK_IN : in std_logic; - Q2_CLK0_GTREFCLK_PAD_N_IN : in std_logic; - Q2_CLK0_GTREFCLK_PAD_P_IN : in std_logic; - Q8_CLK0_GTREFCLK_PAD_N_IN : in std_logic; - Q8_CLK0_GTREFCLK_PAD_P_IN : in std_logic; - Q4_CLK0_GTREFCLK_PAD_N_IN : in std_logic; - Q4_CLK0_GTREFCLK_PAD_P_IN : in std_logic; - Q5_CLK0_GTREFCLK_PAD_N_IN : in std_logic; - Q5_CLK0_GTREFCLK_PAD_P_IN : in std_logic; - Q6_CLK0_GTREFCLK_PAD_N_IN : in std_logic; - Q6_CLK0_GTREFCLK_PAD_P_IN : in std_logic; - GREFCLK_IN : in std_logic; - - clk40_in : in std_logic; - clk240_in : in std_logic; - -- for CentralRouter - TX_120b_in : in txrx120b_type(0 to GBT_NUM-1); - RX_120b_out : out txrx120b_type(0 to GBT_NUM-1); - FRAME_LOCKED_O : out std_logic_vector(GBT_NUM-1 downto 0); - -- TX_ISDATA_I : in std_logic_vector(GBT_NUM-1 downto 0); - -- RX_ISDATA_O : out std_logic_vector(GBT_NUM-1 downto 0); - -- RX_FRAME_CLK_O : out std_logic_vector(GBT_NUM-1 downto 0); - TX_FRAME_CLK_I : in std_logic_vector(GBT_NUM-1 downto 0); - - -- FIFO_RD_CLK : in std_logic_vector(GBT_NUM-1 downto 0); - -- FIFO_RD_EN : in std_logic_vector(GBT_NUM-1 downto 0); - -- FIFO_FULL : out std_logic_vector(GBT_NUM-1 downto 0); - -- FIFO_EMPTY : out std_logic_vector(GBT_NUM-1 downto 0); - - - -- GTH Data pins - TX_P : out std_logic_vector(GBT_NUM-1 downto 0); - TX_N : out std_logic_vector(GBT_NUM-1 downto 0); - RX_P : in std_logic_vector(GBT_NUM-1 downto 0); - RX_N : in std_logic_vector(GBT_NUM-1 downto 0); - RXUSRCLK_OUT : out std_logic_vector(GBT_NUM-1 downto 0) -); end FELIX_gbt_wrapper_KCU; architecture Behavioral of FELIX_gbt_wrapper_KCU is - component fifo_GBT2CR IS - PORT ( - wr_clk : IN STD_LOGIC; - wr_rst : IN STD_LOGIC; - rd_clk : IN STD_LOGIC; - rd_rst : IN STD_LOGIC; - din : IN STD_LOGIC_VECTOR(119 DOWNTO 0); - wr_en : IN STD_LOGIC; - rd_en : IN STD_LOGIC; - dout : OUT STD_LOGIC_VECTOR(119 DOWNTO 0); - full : OUT STD_LOGIC; - empty : OUT STD_LOGIC; - prog_empty : OUT STD_LOGIC - ); - END component; - - -- constant QUAD_NUM : integer := GBT_NUM / 4; - - signal rxslide_manual : STD_LOGIC_VECTOR(47 downto 0); - signal RxSlide_c : STD_LOGIC_VECTOR(47 downto 0); - signal RxSlide_i : std_logic_vector(47 downto 0); - signal rxslide_sel : std_logic_vector(47 downto 0); - signal txusrrdy : std_logic_vector(47 downto 0); - signal rxusrrdy : std_logic_vector(47 downto 0); - signal gttx_reset : std_logic_vector(47 downto 0); - - signal gtrx_reset : std_logic_vector(47 downto 0); - signal soft_reset : std_logic_vector(47 downto 0); - signal cpll_reset : std_logic_vector(47 downto 0); - signal qpll_reset : std_logic_vector(11 downto 0); - signal txresetdone : std_logic_vector(47 downto 0); - - signal clk_sampled : std_logic_vector(47 downto 0); - - signal rxresetdone : std_logic_vector(47 downto 0); - signal txfsmresetdone : std_logic_vector(47 downto 0); - signal rxfsmresetdone : std_logic_vector(47 downto 0); - signal cpllfbclklost : std_logic_vector(47 downto 0); - signal cplllock : std_logic_vector(47 downto 0); - signal rxcdrlock,RxCdrLock_int : std_logic_vector(47 downto 0); - signal qplllock : std_logic_vector(11 downto 0); - signal cdr_cnt : std_logic_vector(19 downto 0); - - signal tx_is_data : std_logic_vector(47 downto 0); - signal TX_RESET : std_logic_vector(47 downto 0); - signal TX_RESET_i : std_logic_vector(47 downto 0); - - signal RX_RESET : std_logic_vector(47 downto 0); - signal RX_RESET_i : std_logic_vector(47 downto 0); - signal GT_TXUSRCLK : std_logic_vector(47 downto 0); - signal GT_RXUSRCLK : std_logic_vector(47 downto 0); - signal RX_FLAG_Oi : std_logic_vector(47 downto 0); - signal gbt_data_format: std_logic_vector(47 downto 0); - - SIGNAL RX_ALIGN_SW : STD_logic; - signal RX_ALIGN_TB_SW : STD_logic; - - signal rx_pll_locked : std_logic_vector(47 downto 0); - signal outsel_i : std_logic_vector(47 downto 0); - signal outsel_ii : std_logic_vector(47 downto 0); - signal outsel_o : std_logic_vector(47 downto 0); - signal RX_120b_out_i : txrx120b_type(0 to (GBT_NUM-1)); - signal RX_120b_out_ii : txrx120b_type(0 to (GBT_NUM-1)); - - signal rx_is_header : std_logic_vector(47 downto 0); - signal alignment_done : std_logic_vector(47 downto 0); - signal rx_is_data : std_logic_vector(47 downto 0); - signal RX_HEADER_FOUND: std_logic_vector(47 downto 0); - - signal RxSlide : std_logic_vector(47 downto 0); - - signal GT_TX_WORD_CLK : std_logic_vector(47 downto 0); - signal TX_TC_METHOD : std_logic_vector(47 downto 0); - signal TC_EDGE : std_logic_vector(47 downto 0); - - type data20barray is array (0 to 47) of std_logic_vector(19 downto 0); - signal TX_DATA_20b : data20barray := (others => ("00000000000000000000")); - signal RX_DATA_20b : data20barray := (others => ("00000000000000000000")); - - signal GT_RX_WORD_CLK : std_logic_vector(47 downto 0); - signal alignment_chk_rst_c : std_logic_vector(47 downto 0); - signal alignment_chk_rst_c1 : std_logic_vector(47 downto 0); - signal alignment_chk_rst : std_logic_vector(47 downto 0); - signal alignment_chk_rst_f : std_logic_vector(47 downto 0); - - signal rstframeclk : std_logic; - signal alignment_chk_rst_i : std_logic; - signal rstframeclk1 : std_logic; - - signal DESMUX_USE_SW : std_logic; - - signal rstframeclk_3r : std_logic; - signal rstframeclk_r : std_logic; - signal rstframeclk_2r : std_logic; - signal rstframeclk1_3r : std_logic; - signal rstframeclk1_r : std_logic; - signal rstframeclk1_2r : std_logic; - signal cxp1_tx_pll_rst : std_logic; - signal cxp2_tx_pll_rst : std_logic; - signal SOFT_TXRST_GT : std_logic_vector(47 downto 0); - signal TopBot : std_logic_vector(47 downto 0); - signal TopBot_C : std_logic_vector(47 downto 0); - signal TopBot_i : std_logic_vector(47 downto 0); - signal SOFT_RXRST_GT : std_logic_vector(47 downto 0); - signal SOFT_TXRST_ALL : std_logic_vector(11 downto 0); - signal SOFT_RXRST_ALL : std_logic_vector(11 downto 0); - signal TX_OPT : std_logic_vector(95 downto 0); - signal RX_OPT : std_logic_vector(95 downto 0); - SIGNAL DATA_TXFORMAT : std_logic_vector(95 downto 0); - signal DATA_TXFORMAT_i : std_logic_vector(95 downto 0); - SIGNAL DATA_RXFORMAT : std_logic_vector(95 downto 0); - signal DATA_RXFORMAT_i : std_logic_vector(95 downto 0); - - SIGNAL OddEven : std_logic_vector(47 downto 0); - signal OddEven_i : std_logic_vector(47 downto 0); - signal OddEven_c : std_logic_vector(47 downto 0); - signal ext_trig_realign : std_logic_vector(47 downto 0); - - - signal General_ctrl : std_logic_vector(63 downto 0); - - - - signal GBT_RXSLIDE : std_logic_vector(47 downto 0); - signal GBT_TXUSRRDY : std_logic_vector(47 downto 0); - signal GBT_RXUSRRDY : std_logic_vector(47 downto 0); - signal GBT_GTTX_RESET : std_logic_vector(47 downto 0); - signal GBT_GTRX_RESET : std_logic_vector(47 downto 0); - signal GBT_PLL_RESET : std_logic_vector(47 downto 0); - signal GBT_SOFT_TX_RESET : std_logic_vector(47 downto 0); - signal GBT_SOFT_RX_RESET : std_logic_vector(47 downto 0); - signal GBT_ODDEVEN : std_logic_vector(47 downto 0); - signal GBT_TOPBOT : std_logic_vector(47 downto 0); - signal GBT_TX_TC_DLY_VALUE1 : std_logic_vector(47 downto 0); - signal GBT_TX_TC_DLY_VALUE2 : std_logic_vector(47 downto 0); - signal GBT_TX_TC_DLY_VALUE3 : std_logic_vector(47 downto 0); - signal GBT_TX_TC_DLY_VALUE4 : std_logic_vector(47 downto 0); - signal GBT_TX_OPT : std_logic_vector(47 downto 0); - signal GBT_RX_OPT : std_logic_vector(47 downto 0); - signal GBT_DATA_TXFORMAT : std_logic_vector(95 downto 0); - signal GBT_DATA_RXFORMAT : std_logic_vector(95 downto 0); - signal GBT_TX_RESET : std_logic_vector(47 downto 0); - signal GBT_RX_RESET : std_logic_vector(47 downto 0); - signal GBT_TX_TC_METHOD : std_logic_vector(47 downto 0); - signal GBT_TC_EDGE : std_logic_vector(47 downto 0); - signal GBT_OUTMUX_SEL : std_logic_vector(47 downto 0); - - SIGNAL GBT_TXRESET_DONE : std_logic_vector(47 downto 0); - SIGNAL GBT_RXRESET_DONE : std_logic_vector(47 downto 0); - signal TXPMARESETDONE : std_logic_vector(47 downto 0); - signal RXPMARESETDONE : std_logic_vector(47 downto 0); - signal alignment_done_f : std_logic_vector(47 downto 0); - signal soft_reset_f : std_logic_vector(47 downto 0); - signal fifo_empty : std_logic_vector(47 downto 0); - signal userclk_rx_reset_in : std_logic_vector(47 downto 0); - signal userclk_tx_reset_in : std_logic_vector(47 downto 0); - signal TXPMARESETDONE_out : std_logic_vector(47 downto 0); - signal RXPMARESETDONE_out : std_logic_vector(47 downto 0); - - SIGNAL GBT_TXFSMRESET_DONE : std_logic_vector(47 downto 0); - SIGNAL GBT_RXFSMRESET_DONE : std_logic_vector(47 downto 0); - SIGNAL GBT_CPLL_FBCLK_LOST : std_logic_vector(47 downto 0); - SIGNAL GBT_PLL_LOCK : std_logic_vector(47 downto 0); - SIGNAL GBT_RXCDR_LOCK : std_logic_vector(47 downto 0); - SIGNAL GBT_CLK_SAMPLED : std_logic_vector(47 downto 0); - SIGNAL GBT_RX_IS_HEADER : std_logic_vector(47 downto 0); - SIGNAL GBT_RX_IS_DATA : std_logic_vector(47 downto 0); - SIGNAL GBT_RX_HEADER_FOUND : std_logic_vector(47 downto 0); - SIGNAL GBT_ALIGNMENT_DONE : std_logic_vector(47 downto 0); - SIGNAL GBT_OUT_MUX_STATUS : std_logic_vector(47 downto 0); - SIGNAL GBT_ERROR : std_logic_vector(47 downto 0); - SIGNAL GBT_GBT_TOPBOT_C : std_logic_vector(47 downto 0); - signal rxcdrlock_a : std_logic_vector(47 downto 0); - - SIGNAL LOGIC_RST : std_logic_vector(63 downto 0); - SIGNAL Channel_disable : std_logic_vector(63 downto 0); - SIGNAL Mode_ctrl : std_logic_vector(47 downto 0); - SIGNAL TX_TC_DLY_VALUE : std_logic_vector(191 downto 0); - signal data_sel : std_logic_vector(191 downto 0); - - signal GTH_RefClk : std_logic_vector(47 downto 0); - signal gbt_sel : std_logic_vector(47 downto 0); - signal lock_lg : std_logic_vector(47 downto 0); - signal pulse_cnt : std_logic_vector(29 downto 0); - signal pulse_lg : std_logic; - - signal CXP1_GTH_RefClk : std_logic; - signal CXP2_GTH_RefClk : std_logic; - signal CXP4_GTH_RefClk : std_logic; - signal CXP3_GTH_RefClk : std_logic; - signal CXP5_GTH_RefClk : std_logic; - signal des_rxusrclk_cxp1 : std_logic; - signal des_rxusrclk_cxp2 : std_logic; - - signal alignment_done_chk_cnt : std_logic_vector(12 downto 0); - signal alignment_done_a : std_logic_vector(47 downto 0); - signal fifo_rst : std_logic_vector(47 downto 0); - signal fifo_rden : std_logic_vector(47 downto 0); - signal clksampled : std_logic_vector(47 downto 0); - signal des_rxusrclk : std_logic_vector(47 downto 0); - signal error_orig : std_logic_vector(47 downto 0); - signal error_f : std_logic_vector(47 downto 0); - signal FSM_RST : std_logic_vector(47 downto 0); - signal auto_gth_rxrst : std_logic_vector(47 downto 0); - signal auto_gbt_rxrst : std_logic_vector(47 downto 0); - signal gbt_rx_reset_i : std_logic_vector(47 downto 0); - signal gtrx_reset_i : std_logic_vector(47 downto 0); - - signal TX_LINERATE : std_logic_vector(47 downto 0); - signal RX_LINERATE : std_logic_vector(47 downto 0); - signal GT_RXOUTCLK : std_logic_vector(47 downto 0); - signal GT_TXOUTCLK : std_logic_vector(47 downto 0); - - signal BITSLIP_MANUAL_r : std_logic_vector(47 downto 0); - signal BITSLIP_MANUAL_2r : std_logic_vector(47 downto 0); - signal BITSLIP_MANUAL_3r : std_logic_vector(47 downto 0); - type txrx80b_12ch_type is array (11 downto 0) of std_logic_vector(79 downto 0); - signal RX_DATA_80b : txrx80b_12ch_type; - signal TX_DATA_80b : txrx80b_12ch_type; - - signal gttx_reset_merge : std_logic_vector(11 downto 0); - signal gtrx_reset_merge : std_logic_vector(11 downto 0); - signal rxcdrlock_quad : std_logic_vector(11 downto 0); - signal rxresetdone_quad : std_logic_vector(11 downto 0); - signal txresetdone_quad : std_logic_vector(11 downto 0); - signal rxcdrlock_out : std_logic_vector(47 downto 0); - signal RxResetDone_f : std_logic_vector(47 downto 0); - - signal RX_N_i : std_logic_vector(47 downto 0):=x"000000000000"; - signal RX_P_i : std_logic_vector(47 downto 0):=x"000000000000"; - signal TX_N_i : std_logic_vector(47 downto 0):=x"000000000000"; - signal TX_P_i : std_logic_vector(47 downto 0):=x"000000000000"; - - signal drpclk_in : std_logic_vector(0 downto 0); - -begin - - FRAME_LOCKED_O <= alignment_done_f(GBT_NUM-1 downto 0); - - -- GTHREFCLK_1 : if GTHREFCLK_SEL = '0' generate - -- IBUFDS_GTE2 - REFCLK_CXP1 <= CXP1_GTH_RefClk; - REFCLK_CXP2 <= CXP2_GTH_RefClk; - ---bank 126, 127, 128 use clk from bank 127 - ibufds_instq2_clk0 : IBUFDS_GTE3 - port map - ( - O => CXP1_GTH_RefClk, - ODIV2 => open, - CEB => '0', - I => Q2_CLK0_GTREFCLK_PAD_P_IN, - IB => Q2_CLK0_GTREFCLK_PAD_N_IN - ); - ---bank 131, 132, 133 use clk from bank 132 - ibufds_instq8_clk0 : IBUFDS_GTE3 - port map - ( - O => CXP2_GTH_RefClk, - ODIV2 => open, - CEB => '0', - I => Q8_CLK0_GTREFCLK_PAD_P_IN, - IB => Q8_CLK0_GTREFCLK_PAD_N_IN - ); - ---bank 231, 232, 233,use clk from bank 232 - ibufds_instq4_clk0 : IBUFDS_GTE3 - port map - ( - O => CXP3_GTH_RefClk, - ODIV2 => open, - CEB => '0', - I => Q4_CLK0_GTREFCLK_PAD_P_IN, - IB => Q4_CLK0_GTREFCLK_PAD_N_IN - ); - ---bank 228 use clk from bank 228 - ibufds_instq5_clk0 : IBUFDS_GTE3 - port map - ( - O => CXP4_GTH_RefClk, - ODIV2 => open, - CEB => '0', - I => Q5_CLK0_GTREFCLK_PAD_P_IN, - IB => Q5_CLK0_GTREFCLK_PAD_N_IN - ); - ---bank 224, 225 use clk from bank 225 -CXP5: if (CARD_TYPE = 712) generate - ibufds_instq6_clk0 : IBUFDS_GTE3 - port map - ( - O => CXP5_GTH_RefClk, - ODIV2 => open, - CEB => '0', - I => Q6_CLK0_GTREFCLK_PAD_P_IN, - IB => Q6_CLK0_GTREFCLK_PAD_N_IN - ); -end generate CXP5; - ---SLR0 banks: 126, 127, 128, 224, 225, 228 ---SLR1 banks: 131, 132, 133, 231, 232, 233 -g_refclk_8ch: if (GBT_NUM <= 8) generate - GTH_RefClk( 0) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - GTH_RefClk( 1) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - GTH_RefClk( 2) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - GTH_RefClk( 3) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - - GTH_RefClk( 4) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - GTH_RefClk( 5) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - GTH_RefClk( 6) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - GTH_RefClk( 7) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - end generate g_refclk_8ch; - -g_refclk_16ch: if ((8 < GBT_NUM) and (GBT_NUM <= 16)) generate - GTH_RefClk( 0) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - GTH_RefClk( 1) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - GTH_RefClk( 2) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - GTH_RefClk( 3) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - GTH_RefClk( 4) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) - GTH_RefClk( 5) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) - GTH_RefClk( 6) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) - GTH_RefClk( 7) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) - - GTH_RefClk( 8) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - GTH_RefClk( 9) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - GTH_RefClk(10) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - GTH_RefClk(11) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - GTH_RefClk(12) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) - GTH_RefClk(13) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) - GTH_RefClk(14) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) - GTH_RefClk(15) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) -end generate g_refclk_16ch; - -g_refclk_24ch: if ((16 < GBT_NUM) and (GBT_NUM <= 24)) generate - GTH_RefClk( 0) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - GTH_RefClk( 1) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - GTH_RefClk( 2) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - GTH_RefClk( 3) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - GTH_RefClk( 4) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) - GTH_RefClk( 5) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) - GTH_RefClk( 6) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) - GTH_RefClk( 7) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) - GTH_RefClk( 8) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) - GTH_RefClk( 9) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) - GTH_RefClk(10) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) - GTH_RefClk(11) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) - - GTH_RefClk(12) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - GTH_RefClk(13) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - GTH_RefClk(14) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - GTH_RefClk(15) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - GTH_RefClk(16) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) - GTH_RefClk(17) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) - GTH_RefClk(18) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) - GTH_RefClk(19) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) - GTH_RefClk(20) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) - GTH_RefClk(21) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) - GTH_RefClk(22) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) - GTH_RefClk(23) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) -end generate g_refclk_24ch; - -g_refclk_48ch: if ((24 < GBT_NUM) and (GBT_NUM <= 48)) generate - GTH_RefClk( 0) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - GTH_RefClk( 1) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - GTH_RefClk( 2) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - GTH_RefClk( 3) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) - GTH_RefClk( 4) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) - GTH_RefClk( 5) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) - GTH_RefClk( 6) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) - GTH_RefClk( 7) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) - GTH_RefClk( 8) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) - GTH_RefClk( 9) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) - GTH_RefClk(10) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) - GTH_RefClk(11) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) - GTH_RefClk(12) <= CXP4_GTH_RefClk;--bank 228 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(13) <= CXP4_GTH_RefClk;--bank 228 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(14) <= CXP4_GTH_RefClk;--bank 228 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(15) <= CXP4_GTH_RefClk;--bank 228 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(16) <= CXP5_GTH_RefClk;--bank 224 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(17) <= CXP5_GTH_RefClk;--bank 224 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(18) <= CXP5_GTH_RefClk;--bank 224 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(19) <= CXP5_GTH_RefClk;--bank 224 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(20) <= CXP5_GTH_RefClk;--bank 225 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(21) <= CXP5_GTH_RefClk;--bank 225 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(22) <= CXP5_GTH_RefClk;--bank 225 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(23) <= CXP5_GTH_RefClk;--bank 225 (up to 48 channels) - BNL712 ONLY - - GTH_RefClk(24) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - GTH_RefClk(25) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - GTH_RefClk(26) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - GTH_RefClk(27) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) - GTH_RefClk(28) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) - GTH_RefClk(29) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) - GTH_RefClk(30) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) - GTH_RefClk(31) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) - GTH_RefClk(32) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) - GTH_RefClk(33) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) - GTH_RefClk(34) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) - GTH_RefClk(35) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) - GTH_RefClk(36) <= CXP3_GTH_RefClk;--bank 231 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(37) <= CXP3_GTH_RefClk;--bank 231 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(38) <= CXP3_GTH_RefClk;--bank 231 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(39) <= CXP3_GTH_RefClk;--bank 231 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(40) <= CXP3_GTH_RefClk;--bank 232 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(41) <= CXP3_GTH_RefClk;--bank 232 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(42) <= CXP3_GTH_RefClk;--bank 232 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(43) <= CXP3_GTH_RefClk;--bank 232 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(44) <= CXP3_GTH_RefClk;--bank 233 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(45) <= CXP3_GTH_RefClk;--bank 233 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(46) <= CXP3_GTH_RefClk;--bank 233 (up to 48 channels) - BNL712 ONLY - GTH_RefClk(47) <= CXP3_GTH_RefClk;--bank 233 (up to 48 channels) - BNL712 ONLY -end generate g_refclk_48ch; - ---IG GTH_RefClk(0) <= CXP1_GTH_RefClk; ---IG GTH_RefClk(1) <= CXP1_GTH_RefClk; ---IG GTH_RefClk(2) <= CXP1_GTH_RefClk; ---IG GTH_RefClk(3) <= CXP1_GTH_RefClk; ---IG GTH_RefClk(4) <= CXP1_GTH_RefClk; ---IG GTH_RefClk(5) <= CXP1_GTH_RefClk; ---IG GTH_RefClk(6) <= CXP1_GTH_RefClk; ---IG GTH_RefClk(7) <= CXP1_GTH_RefClk; ---IG ---IG -- For 16 channels (and below) put 8 channels in SRL0, channel 8..15 in SRL1. ---IG g_refclk0: if GBT_NUM <= 16 generate ---IG GTH_RefClk(8) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(9) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(10) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(11) <= CXP2_GTH_RefClk; ---IG end generate; ---IG ---IG -- For 24 channels put 12 channels in SRL0, channel 12..23 in SRL1. ---IG g_refclk1: if GBT_NUM > 16 generate ---IG GTH_RefClk(8) <= CXP1_GTH_RefClk; ---IG GTH_RefClk(9) <= CXP1_GTH_RefClk; ---IG GTH_RefClk(10) <= CXP1_GTH_RefClk; ---IG GTH_RefClk(11) <= CXP1_GTH_RefClk; ---IG end generate; ---IG ---IG refclkgen_v2p0 : if CARD_TYPE=712 generate ---IG g_refclk11: if GBT_NUM <25 generate ---IG --IBUFDS_GTE2 ---IG ---IG GTH_RefClk(12) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(13) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(14) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(15) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(16) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(17) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(18) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(19) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(20) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(21) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(22) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(23) <= CXP2_GTH_RefClk; ---IG end generate; ---IG g_refclk12: if GBT_NUM >24 generate ---IG GTH_RefClk(24) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(25) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(26) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(27) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(28) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(29) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(30) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(31) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(32) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(33) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(34) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(35) <= CXP2_GTH_RefClk; ---IG ---IG GTH_RefClk(36) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(37) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(38) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(39) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(40) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(41) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(42) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(43) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(44) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(45) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(46) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(47) <= CXP3_GTH_RefClk; ---IG ---IG GTH_RefClk(12) <= CXP4_GTH_RefClk; ---IG GTH_RefClk(13) <= CXP4_GTH_RefClk; ---IG GTH_RefClk(14) <= CXP4_GTH_RefClk; ---IG GTH_RefClk(15) <= CXP4_GTH_RefClk; ---IG ---IG GTH_RefClk(16) <= CXP5_GTH_RefClk; ---IG GTH_RefClk(17) <= CXP5_GTH_RefClk; ---IG GTH_RefClk(18) <= CXP5_GTH_RefClk; ---IG GTH_RefClk(19) <= CXP5_GTH_RefClk; ---IG GTH_RefClk(20) <= CXP5_GTH_RefClk; ---IG GTH_RefClk(21) <= CXP5_GTH_RefClk; ---IG GTH_RefClk(22) <= CXP5_GTH_RefClk; ---IG GTH_RefClk(23) <= CXP5_GTH_RefClk; ---IG ---IG--bank 224, 225 use clk from bank 225 ---IG ibufds_instq6_clk0 : IBUFDS_GTE3 ---IG port map ---IG ( ---IG O => CXP5_GTH_RefClk, ---IG ODIV2 => open, ---IG CEB => '0', ---IG I => Q6_CLK0_GTREFCLK_PAD_P_IN, ---IG IB => Q6_CLK0_GTREFCLK_PAD_N_IN ---IG ); ---IG ---IG end generate; ---IG ---IG end generate; ---IG ---IGrefclkgen_v1p5 : if CARD_TYPE=711 generate ---IG ---IG ---IG GTH_RefClk(12) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(13) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(14) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(15) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(16) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(17) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(18) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(19) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(20) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(21) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(22) <= CXP2_GTH_RefClk; ---IG GTH_RefClk(23) <= CXP2_GTH_RefClk; ---IG ---IG ---IG GTH_RefClk(24) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(25) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(26) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(27) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(28) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(29) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(30) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(31) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(32) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(33) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(34) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(35) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(40) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(41) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(42) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(43) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(44) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(45) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(46) <= CXP3_GTH_RefClk; ---IG GTH_RefClk(47) <= CXP3_GTH_RefClk; ---IG ---IG ---IG GTH_RefClk(36) <= CXP4_GTH_RefClk; ---IG GTH_RefClk(37) <= CXP4_GTH_RefClk; ---IG GTH_RefClk(38) <= CXP4_GTH_RefClk; ---IG GTH_RefClk(39) <= CXP4_GTH_RefClk; ---IG ---IG end generate; - - Channel_disable(47 downto 0) <= register_map_control.GBT_CHANNEL_DISABLE; - General_ctrl <= register_map_control.GBT_GENERAL_CTRL; - - RxSlide_Manual(47 downto 0) <= register_map_control.GBT_RXSLIDE_MANUAL(47 downto 0); - RxSlide_Sel(47 downto 0) <= register_map_control.GBT_RXSLIDE_SELECT(47 downto 0); - TXUSRRDY(47 downto 0) <= register_map_control.GBT_TXUSRRDY(47 downto 0); - RXUSRRDY(47 downto 0) <= register_map_control.GBT_RXUSRRDY(47 downto 0); - GTTX_RESET(47 downto 0) <= register_map_control.GBT_GTTX_RESET(47 downto 0); - GTRX_RESET(47 downto 0) <= register_map_control.GBT_GTRX_RESET(47 downto 0); - SOFT_RESET(47 downto 0) <= register_map_control.GBT_SOFT_RESET(47 downto 0); - CPLL_RESET(47 downto 0) <= register_map_control.GBT_PLL_RESET.CPLL_RESET(47 downto 0); - QPLL_RESET(11 downto 0) <= register_map_control.GBT_PLL_RESET.QPLL_RESET(59 downto 48); - - SOFT_TXRST_GT(47 downto 0) <= register_map_control.GBT_SOFT_TX_RESET.RESET_GT; -- Default: 0b000 - SOFT_RXRST_GT(47 downto 0) <= register_map_control.GBT_SOFT_RX_RESET.RESET_GT; -- Default: 0b000 - SOFT_TXRST_ALL(11 downto 0) <= register_map_control.GBT_SOFT_TX_RESET.RESET_ALL(59 downto 48); - SOFT_RXRST_ALL(11 downto 0) <= register_map_control.GBT_SOFT_RX_RESET.RESET_ALL(59 downto 48); - - OddEven(47 downto 0) <= register_map_control.GBT_ODD_EVEN(47 downto 0); - TopBot(47 downto 0) <= register_map_control.GBT_TOPBOT(47 downto 0); - - TX_TC_DLY_VALUE(47 downto 0) <= register_map_control.GBT_TX_TC_DLY_VALUE1; - TX_TC_DLY_VALUE(95 downto 48) <=register_map_control.GBT_TX_TC_DLY_VALUE2; - TX_TC_DLY_VALUE(143 downto 96) <= register_map_control.GBT_TX_TC_DLY_VALUE3; - TX_TC_DLY_VALUE(191 downto 144) <= register_map_control.GBT_TX_TC_DLY_VALUE4; - - - -- TX_OPT(47 downto 0) <= GBT_TX_OPT(47 DOWNTO 0); -- - -- RX_OPT(47 downto 0) <= GBT_RX_OPT(47 DOWNTO 0); -- - - - -- GBT_TX_OPT(47 downto 0) <= x"000000555555"; -- ! TODO:Register was removed in RM4.0 register_map_control.GBT_TX_OPT; - -- GBT_RX_OPT(47 downto 0) <= x"000000555555"; -- ! TODO:Register was removed in RM4.0 register_map_control.GBT_RX_OPT; - DATA_TXFORMAT(47 downto 0) <= register_map_control.GBT_DATA_TXFORMAT1(47 downto 0); - DATA_RXFORMAT(47 downto 0) <= register_map_control.GBT_DATA_RXFORMAT1(47 downto 0); - DATA_TXFORMAT(95 downto 48) <= register_map_control.GBT_DATA_TXFORMAT2(47 downto 0); - DATA_RXFORMAT(95 downto 48) <= register_map_control.GBT_DATA_RXFORMAT2(47 downto 0); - - TX_RESET(47 downto 0) <= register_map_control.GBT_TX_RESET(47 downto 0); - RX_RESET(47 downto 0) <= register_map_control.GBT_RX_RESET(47 downto 0); - TX_TC_METHOD(47 downto 0) <= register_map_control.GBT_TX_TC_METHOD(47 downto 0); - TC_EDGE(47 downto 0) <= register_map_control.GBT_TC_EDGE(47 downto 0); - outsel_i(47 downto 0) <= register_map_control.GBT_OUTMUX_SEL(47 downto 0); - - register_map_link_monitor.GBT_VERSION.DATE <= GBT_VERSION(63 downto 48); - register_map_link_monitor.GBT_VERSION.GBT_VERSION(35 downto 32) <= GBT_VERSION(23 downto 20); - register_map_link_monitor.GBT_VERSION.GTH_IP_VERSION(19 downto 16) <= GBT_VERSION(19 downto 16); - register_map_link_monitor.GBT_VERSION.RESERVED <= GBT_VERSION(15 downto 3); - register_map_link_monitor.GBT_VERSION.GTHREFCLK_SEL <= (others => GTHREFCLK_SEL); - register_map_link_monitor.GBT_VERSION.RX_CLK_SEL <= GBT_VERSION(1 downto 1); - register_map_link_monitor.GBT_VERSION.PLL_SEL <= GBT_VERSION(0 downto 0); - - -- - - register_map_link_monitor.GBT_TXRESET_DONE(47 downto 0) <= TxResetDone(47 downto 0); - register_map_link_monitor.GBT_RXRESET_DONE(47 downto 0) <= RxResetDone(47 downto 0); - register_map_link_monitor.GBT_TXFSMRESET_DONE(47 downto 0) <= txpmaresetdone(47 downto 0); - register_map_link_monitor.GBT_RXFSMRESET_DONE(47 downto 0) <= rxpmaresetdone(47 downto 0); - register_map_link_monitor.GBT_CPLL_FBCLK_LOST(47 downto 0) <= CpllFbClkLost (47 downto 0); - register_map_link_monitor.GBT_PLL_LOCK.CPLL_LOCK(47 downto 0) <= CpllLock(47 downto 0); - register_map_link_monitor.GBT_PLL_LOCK.QPLL_LOCK(59 downto 48) <= QpllLock(11 downto 0); - register_map_link_monitor.GBT_RXCDR_LOCK(47 downto 0) <= RxCdrLock(47 downto 0); - register_map_link_monitor.GBT_CLK_SAMPLED(47 downto 0) <= clk_sampled(47 downto 0); - - register_map_link_monitor.GBT_RX_IS_HEADER(47 downto 0) <= RX_IS_HEADER(47 downto 0); - register_map_link_monitor.GBT_RX_IS_DATA(47 downto 0) <= RX_IS_DATA(47 downto 0); - register_map_link_monitor.GBT_RX_HEADER_FOUND(47 downto 0) <= RX_HEADER_FOUND(47 downto 0); - - register_map_link_monitor.GBT_ALIGNMENT_DONE(47 downto 0) <= alignment_done_f(47 downto 0); - - - -- aligndone_gen : for i in 23 downto 0 generate - -- alignment_done_f(i) <= RxCdrLock(i) and alignment_done(i); - -- end generate; - - register_map_link_monitor.GBT_OUT_MUX_STATUS(47 downto 0) <= outsel_o(47 downto 0); - register_map_link_monitor.GBT_ERROR(47 downto 0) <= error_f(47 downto 0); - - error_gen : for i in 47 downto 0 generate - error_f(i) <= error_orig(i) and alignment_done_f(i); - end generate; - - register_map_link_monitor.GBT_GBT_TOPBOT_C(47 downto 0) <= TopBot_c(47 downto 0); - - ----------------------------------------- ------- REGISTERS MAPPING ----------------------------------------- - alignment_chk_rst_i <= General_ctrl(0); - - - DESMUX_USE_SW <= register_map_control.GBT_MODE_CTRL.DESMUX_USE_SW(0); - RX_ALIGN_SW <= register_map_control.GBT_MODE_CTRL.RX_ALIGN_SW(1); - RX_ALIGN_TB_SW <= register_map_control.GBT_MODE_CTRL.RX_ALIGN_TB_SW(2); - - - - - - - ------- - - datamod_gen1 : if DYNAMIC_DATA_MODE_EN='1' generate - DATA_TXFORMAT_i <= DATA_TXFORMAT; - DATA_RXFORMAT_i <= DATA_RXFORMAT; - end generate; - - datamod_gen2 : if DYNAMIC_DATA_MODE_EN='0' generate - DATA_TXFORMAT_i <= GBT_DATA_TXFORMAT_PACKAGE; - DATA_RXFORMAT_i <= GBT_DATA_RXFORMAT_PACKAGE; - end generate; - - process(clk40_in) - begin - if clk40_in'event and clk40_in='1' then - pulse_lg <= pulse_cnt(20); - if pulse_cnt(20)='1' then - pulse_cnt <=(others=>'0'); - else - pulse_cnt <= pulse_cnt+'1'; - end if; - end if; - end process; - - process(clk40_in) - begin - if clk40_in'event and clk40_in='1' then - alignment_done_chk_cnt <= alignment_done_chk_cnt + '1'; - end if; - end process; - - rxalign_auto : for i in GBT_NUM-1 downto 0 generate - --- process(clk40_in) --- begin --- if clk40_in'event and clk40_in='1' then --- if pulse_lg = '1' then --- gbt_sel(i) <= lock_lg(i); --- end if; --- if pulse_lg = '1' then --- lock_lg(i) <='1'; --- elsif alignment_done_f(i)='0' then --- lock_lg(i) <='0'; --- end if; --- end if; --- end process; - - process(clk40_in) - begin - if clk40_in'event and clk40_in='1' then - if alignment_done_chk_cnt="0000000000000" then - alignment_done_a(i) <= RxCdrLock(i) and alignment_done(i); - else - alignment_done_a(i) <= RxCdrLock(i) and alignment_done(i) and alignment_done_a(i); - end if; - if alignment_done_chk_cnt="0000000000000" then - alignment_done_f(i) <= RxCdrLock(i) and alignment_done_a(i); - end if; - end if; - end process; - - - RX_120b_out(i) <= RX_120b_out_ii(i) when alignment_done_f(i)='1' - else (others =>'0'); - - auto_rxrst : entity work.FELIX_GBT_RX_AUTO_RST - port map - ( - FSM_CLK => clk40_in, - pulse_lg => pulse_lg, - GTHRXRESET_DONE => RxResetDone(i),-- and RxFsmResetDone(i), - alignment_chk_rst => alignment_chk_rst_c1(i), - GBT_LOCK => alignment_done_f(i),--alignment_done(i), - AUTO_GTH_RXRST => auto_gth_rxrst(i), - ext_trig_realign => ext_trig_realign(i), - AUTO_GBT_RXRST => auto_gbt_rxrst(i) + component fifo_GBT2CR IS + PORT ( + wr_clk : IN STD_LOGIC; + wr_rst : IN STD_LOGIC; + rd_clk : IN STD_LOGIC; + rd_rst : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(119 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(119 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC; + prog_empty : OUT STD_LOGIC ); + END component; + + -- constant QUAD_NUM : integer := GBT_NUM / 4; + + --signal rxslide_manual : STD_LOGIC_VECTOR(47 downto 0); + signal RxSlide_c : STD_LOGIC_VECTOR(47 downto 0); + signal RxSlide_i : std_logic_vector(47 downto 0); + --signal rxslide_sel : std_logic_vector(47 downto 0); + --signal txusrrdy : std_logic_vector(47 downto 0); + --signal rxusrrdy : std_logic_vector(47 downto 0); + signal gttx_reset : std_logic_vector(47 downto 0); + + signal gtrx_reset : std_logic_vector(47 downto 0); + signal soft_reset : std_logic_vector(47 downto 0); + signal cpll_reset : std_logic_vector(47 downto 0); + signal qpll_reset : std_logic_vector(11 downto 0); + signal txresetdone : std_logic_vector(47 downto 0); + + --signal clk_sampled : std_logic_vector(47 downto 0); + + signal rxresetdone : std_logic_vector(47 downto 0); + --signal txfsmresetdone : std_logic_vector(47 downto 0); + --signal rxfsmresetdone : std_logic_vector(47 downto 0); + signal cpllfbclklost : std_logic_vector(47 downto 0); + signal cplllock : std_logic_vector(47 downto 0); + signal rxcdrlock,RxCdrLock_int : std_logic_vector(47 downto 0); + signal qplllock : std_logic_vector(11 downto 0); + signal cdr_cnt : std_logic_vector(19 downto 0); + + --signal tx_is_data : std_logic_vector(47 downto 0); + signal TX_RESET : std_logic_vector(47 downto 0); + signal TX_RESET_i : std_logic_vector(47 downto 0); + + signal RX_RESET : std_logic_vector(47 downto 0); + signal RX_RESET_i : std_logic_vector(47 downto 0); + signal GT_TXUSRCLK : std_logic_vector(47 downto 0); + signal GT_RXUSRCLK : std_logic_vector(47 downto 0); + signal RX_FLAG_Oi : std_logic_vector(47 downto 0); + --signal gbt_data_format: std_logic_vector(47 downto 0); + + --SIGNAL RX_ALIGN_SW : STD_logic; + --signal RX_ALIGN_TB_SW : STD_logic; + + --signal rx_pll_locked : std_logic_vector(47 downto 0); + signal outsel_i : std_logic_vector(47 downto 0); + signal outsel_ii : std_logic_vector(47 downto 0); + signal outsel_o : std_logic_vector(47 downto 0); + signal RX_120b_out_i : txrx120b_type(0 to (GBT_NUM-1)); + signal RX_120b_out_ii : txrx120b_type(0 to (GBT_NUM-1)); + + signal rx_is_header : std_logic_vector(47 downto 0); + signal alignment_done : std_logic_vector(47 downto 0); + --signal rx_is_data : std_logic_vector(47 downto 0); + signal RX_HEADER_FOUND: std_logic_vector(47 downto 0); + + signal RxSlide : std_logic_vector(47 downto 0); + + signal GT_TX_WORD_CLK : std_logic_vector(47 downto 0); + signal TX_TC_METHOD : std_logic_vector(47 downto 0); + signal TC_EDGE : std_logic_vector(47 downto 0); + + type data20barray is array (0 to 47) of std_logic_vector(19 downto 0); + signal TX_DATA_20b : data20barray := (others => ("00000000000000000000")); + signal RX_DATA_20b : data20barray := (others => ("00000000000000000000")); + + signal GT_RX_WORD_CLK : std_logic_vector(47 downto 0); + signal alignment_chk_rst_c : std_logic_vector(47 downto 0); + signal alignment_chk_rst_c1 : std_logic_vector(47 downto 0); + signal alignment_chk_rst : std_logic_vector(47 downto 0); + signal alignment_chk_rst_f : std_logic_vector(47 downto 0); + + --signal rstframeclk : std_logic; + signal alignment_chk_rst_i : std_logic; + --signal rstframeclk1 : std_logic; + + signal DESMUX_USE_SW : std_logic; + + --signal rstframeclk_3r : std_logic; + --signal rstframeclk_r : std_logic; + --signal rstframeclk_2r : std_logic; + --signal rstframeclk1_3r : std_logic; + --signal rstframeclk1_r : std_logic; + --signal rstframeclk1_2r : std_logic; + --signal cxp1_tx_pll_rst : std_logic; + --signal cxp2_tx_pll_rst : std_logic; + --signal SOFT_TXRST_GT : std_logic_vector(47 downto 0); + --signal TopBot : std_logic_vector(47 downto 0); + --signal TopBot_C : std_logic_vector(47 downto 0); + --signal TopBot_i : std_logic_vector(47 downto 0); + --signal SOFT_RXRST_GT : std_logic_vector(47 downto 0); + --signal SOFT_TXRST_ALL : std_logic_vector(11 downto 0); + --signal SOFT_RXRST_ALL : std_logic_vector(11 downto 0); + --signal TX_OPT : std_logic_vector(95 downto 0); + --signal RX_OPT : std_logic_vector(95 downto 0); + SIGNAL DATA_TXFORMAT : std_logic_vector(95 downto 0); + signal DATA_TXFORMAT_i : std_logic_vector(95 downto 0); + SIGNAL DATA_RXFORMAT : std_logic_vector(95 downto 0); + signal DATA_RXFORMAT_i : std_logic_vector(95 downto 0); + + --SIGNAL OddEven : std_logic_vector(47 downto 0); + --signal OddEven_i : std_logic_vector(47 downto 0); + --signal OddEven_c : std_logic_vector(47 downto 0); + --signal ext_trig_realign : std_logic_vector(47 downto 0); + + + signal General_ctrl : std_logic_vector(63 downto 0); + + + + --signal GBT_RXSLIDE : std_logic_vector(47 downto 0); + --signal GBT_TXUSRRDY : std_logic_vector(47 downto 0); + --signal GBT_RXUSRRDY : std_logic_vector(47 downto 0); + --signal GBT_GTTX_RESET : std_logic_vector(47 downto 0); + --signal GBT_GTRX_RESET : std_logic_vector(47 downto 0); + --signal GBT_PLL_RESET : std_logic_vector(47 downto 0); + --signal GBT_SOFT_TX_RESET : std_logic_vector(47 downto 0); + --signal GBT_SOFT_RX_RESET : std_logic_vector(47 downto 0); + --signal GBT_ODDEVEN : std_logic_vector(47 downto 0); + --signal GBT_TOPBOT : std_logic_vector(47 downto 0); + --signal GBT_TX_TC_DLY_VALUE1 : std_logic_vector(47 downto 0); + --signal GBT_TX_TC_DLY_VALUE2 : std_logic_vector(47 downto 0); + --signal GBT_TX_TC_DLY_VALUE3 : std_logic_vector(47 downto 0); + --signal GBT_TX_TC_DLY_VALUE4 : std_logic_vector(47 downto 0); + --signal GBT_TX_OPT : std_logic_vector(47 downto 0); + --signal GBT_RX_OPT : std_logic_vector(47 downto 0); + --signal GBT_DATA_TXFORMAT : std_logic_vector(95 downto 0); + --signal GBT_DATA_RXFORMAT : std_logic_vector(95 downto 0); + --signal GBT_TX_RESET : std_logic_vector(47 downto 0); + --signal GBT_RX_RESET : std_logic_vector(47 downto 0); + --signal GBT_TX_TC_METHOD : std_logic_vector(47 downto 0); + --signal GBT_TC_EDGE : std_logic_vector(47 downto 0); + --signal GBT_OUTMUX_SEL : std_logic_vector(47 downto 0); + + --SIGNAL GBT_TXRESET_DONE : std_logic_vector(47 downto 0); + --SIGNAL GBT_RXRESET_DONE : std_logic_vector(47 downto 0); + signal TXPMARESETDONE : std_logic_vector(47 downto 0); + signal RXPMARESETDONE : std_logic_vector(47 downto 0); + signal alignment_done_f : std_logic_vector(47 downto 0); + signal soft_reset_f : std_logic_vector(47 downto 0); + signal fifo_empty : std_logic_vector(47 downto 0); + signal userclk_rx_reset_in : std_logic_vector(47 downto 0); + signal userclk_tx_reset_in : std_logic_vector(47 downto 0); + --signal TXPMARESETDONE_out : std_logic_vector(47 downto 0); + --signal RXPMARESETDONE_out : std_logic_vector(47 downto 0); + + --SIGNAL GBT_TXFSMRESET_DONE : std_logic_vector(47 downto 0); + --SIGNAL GBT_RXFSMRESET_DONE : std_logic_vector(47 downto 0); + --SIGNAL GBT_CPLL_FBCLK_LOST : std_logic_vector(47 downto 0); + --SIGNAL GBT_PLL_LOCK : std_logic_vector(47 downto 0); + --SIGNAL GBT_RXCDR_LOCK : std_logic_vector(47 downto 0); + --SIGNAL GBT_CLK_SAMPLED : std_logic_vector(47 downto 0); + --SIGNAL GBT_RX_IS_HEADER : std_logic_vector(47 downto 0); + --SIGNAL GBT_RX_IS_DATA : std_logic_vector(47 downto 0); + --SIGNAL GBT_RX_HEADER_FOUND : std_logic_vector(47 downto 0); + --SIGNAL GBT_ALIGNMENT_DONE : std_logic_vector(47 downto 0); + --SIGNAL GBT_OUT_MUX_STATUS : std_logic_vector(47 downto 0); + --SIGNAL GBT_ERROR : std_logic_vector(47 downto 0); + --SIGNAL GBT_GBT_TOPBOT_C : std_logic_vector(47 downto 0); + signal rxcdrlock_a : std_logic_vector(47 downto 0); + + --SIGNAL LOGIC_RST : std_logic_vector(63 downto 0); + SIGNAL Channel_disable : std_logic_vector(63 downto 0); + --SIGNAL Mode_ctrl : std_logic_vector(47 downto 0); + SIGNAL TX_TC_DLY_VALUE : std_logic_vector(191 downto 0); + --signal data_sel : std_logic_vector(191 downto 0); + + signal GTH_RefClk : std_logic_vector(47 downto 0); + --signal gbt_sel : std_logic_vector(47 downto 0); + --signal lock_lg : std_logic_vector(47 downto 0); + signal pulse_cnt : std_logic_vector(29 downto 0); + signal pulse_lg : std_logic; + + signal CXP1_GTH_RefClk : std_logic; + signal CXP2_GTH_RefClk : std_logic; + signal CXP4_GTH_RefClk : std_logic; + signal CXP3_GTH_RefClk : std_logic; + signal CXP5_GTH_RefClk : std_logic; + --signal des_rxusrclk_cxp1 : std_logic; + --signal des_rxusrclk_cxp2 : std_logic; + + signal alignment_done_chk_cnt : std_logic_vector(12 downto 0); + signal alignment_done_a : std_logic_vector(47 downto 0); + signal fifo_rst : std_logic_vector(47 downto 0); + signal fifo_rden : std_logic_vector(47 downto 0); + --signal clksampled : std_logic_vector(47 downto 0); + --signal des_rxusrclk : std_logic_vector(47 downto 0); + signal error_orig : std_logic_vector(47 downto 0); + signal error_f : std_logic_vector(47 downto 0); + signal FSM_RST : std_logic_vector(47 downto 0); + signal auto_gth_rxrst : std_logic_vector(47 downto 0); + signal auto_gbt_rxrst : std_logic_vector(47 downto 0); + --signal gbt_rx_reset_i : std_logic_vector(47 downto 0); + signal gtrx_reset_i : std_logic_vector(47 downto 0); + + --signal TX_LINERATE : std_logic_vector(47 downto 0); + --signal RX_LINERATE : std_logic_vector(47 downto 0); + signal GT_RXOUTCLK : std_logic_vector(47 downto 0); + signal GT_TXOUTCLK : std_logic_vector(47 downto 0); + + signal BITSLIP_MANUAL_r : std_logic_vector(47 downto 0); + signal BITSLIP_MANUAL_2r : std_logic_vector(47 downto 0); + --signal BITSLIP_MANUAL_3r : std_logic_vector(47 downto 0); + type txrx80b_12ch_type is array (11 downto 0) of std_logic_vector(79 downto 0); + signal RX_DATA_80b : txrx80b_12ch_type; + signal TX_DATA_80b : txrx80b_12ch_type; + + signal gttx_reset_merge : std_logic_vector(11 downto 0); + signal gtrx_reset_merge : std_logic_vector(11 downto 0); + --signal rxcdrlock_quad : std_logic_vector(11 downto 0); + --signal rxresetdone_quad : std_logic_vector(11 downto 0); + --signal txresetdone_quad : std_logic_vector(11 downto 0); + signal rxcdrlock_out : std_logic_vector(47 downto 0); + --signal RxResetDone_f : std_logic_vector(47 downto 0); + + signal RX_N_i : std_logic_vector(47 downto 0):=x"000000000000"; + signal RX_P_i : std_logic_vector(47 downto 0):=x"000000000000"; + signal TX_N_i : std_logic_vector(47 downto 0):=x"000000000000"; + signal TX_P_i : std_logic_vector(47 downto 0):=x"000000000000"; + + signal drpclk_in : std_logic_vector(0 downto 0); - rafsm : entity work.FELIX_GBT_RXSLIDE_FSM - port map - ( - ext_trig_realign => ext_trig_realign(i), - FSM_RST => FSM_RST(i), - FSM_CLK => clk40_in, - GBT_LOCK => alignment_done(i), - RxSlide => RxSlide_c(i), - alignment_chk_rst => alignment_chk_rst_c(i) - ); - - FSM_RST(i) <= RX_RESET(i);-- or RX_ALIGN_SW; - -- GTRX_RESET_i(i) <= --GTRX_RESET(i) when RX_ALIGN_SW='1' else - -- (GTRX_RESET(i) or auto_gth_rxrst(i)); - RX_RESET_i(i) <= --RX_RESET(i) when RX_ALIGN_SW='1' else - (RX_RESET(i) or auto_gbt_rxrst(i)); - alignment_chk_rst(i) <= --alignment_chk_rst_i when RX_ALIGN_SW='1' else - (alignment_chk_rst_i or alignment_chk_rst_c(i) or alignment_chk_rst_c1(i)); - RxSlide_i(i) <= RxSlide_c(i) and RxCdrLock(i); - TX_RESET_i(i) <= TX_RESET(i) or (not TxResetDone(i));-- or (not TxFsmResetDone(i)); - end generate; - - outsel_ii <= outsel_o when DESMUX_USE_SW = '0' else - outsel_i; - --- OddEven_i <= OddEven_c when RX_ALIGN_SW ='0' else --- OddEven; - --- TopBot_i <= TopBot_c when RX_ALIGN_SW='0' else --and RX_ALIGN_TB_SW='0' else --- TopBot; - - --RxSlide_i <= RxSlide_c;-- when RX_ALIGN_SW='0' else - -- RxSlide_Manual; - - RX_FLAG_O <= RX_FLAG_Oi(GBT_NUM-1 downto 0); +begin - gbtRxTx : for i in GBT_NUM-1 downto 0 generate - process(GT_RX_WORD_CLK(i)) - begin - if GT_RX_WORD_CLK(i)'event and GT_RX_WORD_CLK(i)='1' then - BITSLIP_MANUAL_r(i) <= RxSlide_i(i); - BITSLIP_MANUAL_2r(i) <= BITSLIP_MANUAL_r(i); - BITSLIP_MANUAL_3r(i) <= BITSLIP_MANUAL_2r(i); - RxSlide(i) <= BITSLIP_MANUAL_r(i) and (not BITSLIP_MANUAL_2r(i)); - end if; - end process; + FRAME_LOCKED_O <= alignment_done_f(GBT_NUM-1 downto 0); + -- GTHREFCLK_1 : if GTHREFCLK_SEL = '0' generate + -- IBUFDS_GTE2 + REFCLK_CXP1 <= CXP1_GTH_RefClk; + REFCLK_CXP2 <= CXP2_GTH_RefClk; - alignment_chk_rst_f(i) <= alignment_chk_rst(i);-- or (not RxCdrLock(i)); - gbtTxRx_inst: entity work.gbtTxRx_FELIX - generic map - ( - channel => i + --bank 126, 127, 128 use clk from bank 127 + ibufds_instq2_clk0 : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" ) - port map - ( - error_o => error_orig(i), - RX_FLAG => RX_FLAG_Oi(i),--RX_FLAG_O(i), - TX_FLAG => TX_FLAG_O(i), - - Tx_DATA_FORMAT => DATA_TXFORMAT_i(2*i+1 downto 2*i), - Rx_DATA_FORMAT => DATA_RXFORMAT_i(2*i+1 downto 2*i), - - Tx_latopt_tc => '1',--TX_OPT(i), - Tx_latopt_scr => '1',--TX_OPT(24+i), - RX_LATOPT_DES => '1',--RX_OPT(i), - - TX_TC_METHOD => TX_TC_METHOD(i), - TC_EDGE => TC_EDGE(i), - TX_TC_DLY_VALUE => TX_TC_DLY_VALUE(4*i+2 downto 4*i), - - alignment_chk_rst => alignment_chk_rst_f(i), - alignment_done_O => alignment_done(i), - L40M => clk40_in, - outsel_i => outsel_ii(i), - outsel_o => outsel_o(i), - - --BITSLIP_MANUAL => RxSlide_i(i), - --BITSLIP_SEL => RxSlide_Sel(i), - --GT_RXSLIDE => RxSlide(i), - OddEven => '0',--OddEven_i(i), - TopBot => '0',--TopBot_i(i), - data_sel => data_sel(4*i+3 downto 4*i), - - TX_RESET_I => TX_RESET_i(i), - TX_FRAMECLK_I => TX_FRAME_CLK_I(i), - TX_WORDCLK_I => GT_TX_WORD_CLK(i), - --TX_ISDATA_SEL_I => TX_IS_DATA(i), - TX_DATA_120b_I => TX_120b_in(i), - TX_DATA_20b_O => TX_DATA_20b(i), - - RX_RESET_I => RX_RESET_i(i), - RX_FRAME_CLK_O => open,--RX_FRAME_CLK_O(i), - RX_WORD_IS_HEADER_O => RX_IS_HEADER(i), - RX_HEADER_FOUND => RX_HEADER_FOUND(i), - RX_ISDATA_FLAG_O => RX_IS_DATA(i), - RX_DATA_20b_I => RX_DATA_20b(i), - RX_DATA_120b_O => RX_120b_out_i(i), - des_rxusrclk => GT_RX_WORD_CLK(i), - RX_WORDCLK_I => GT_RX_WORD_CLK(i) - + port map( + O => CXP1_GTH_RefClk, + ODIV2 => open, + CEB => '0', + I => Q2_CLK0_GTREFCLK_PAD_P_IN, + IB => Q2_CLK0_GTREFCLK_PAD_N_IN ); - fifo_rst(i) <= rst_hw or (not alignment_done_f(i)) or RX_RESET_i(i) or General_ctrl(4); - fifo_rden(i) <= not fifo_empty(i); - - fifo_inst: fifo_GBT2CR - PORT MAP( - rd_rst => fifo_rst(i),--rst_hw, - wr_rst => fifo_rst(i),--rst_hw, - wr_clk => GT_RX_WORD_CLK(i), - rd_clk => clk40_in,--FIFO_RD_CLK(i), - din => RX_120b_out_i(i), - wr_en => RX_FLAG_Oi(i), - rd_en => fifo_rden(i),--not fifo_empty(i),--'1',--FIFO_RD_EN(i), - dout => RX_120b_out_ii(i), - full => open, - empty => open, - prog_empty => fifo_empty(i)--FIFO_EMPTY(i) - ); - - end generate; - - - - - -------------------------------- ------- GTH TOP WRAPPER -------------------------------- - - clk_generate : for i in GBT_NUM-1 downto 0 generate - - GTTXOUTCLK_BUFG: bufg_gt - port map( - i => GT_TXOUTCLK(i), - div => "000", - clr => '0',--userclk_tx_reset_in,--'0', - cemask => '0', - clrmask => '0', - ce => '1', - o => GT_TXUSRCLK(i) + --bank 131, 132, 133 use clk from bank 132 + ibufds_instq8_clk0 : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) + port map( + O => CXP2_GTH_RefClk, + ODIV2 => open, + CEB => '0', + I => Q8_CLK0_GTREFCLK_PAD_P_IN, + IB => Q8_CLK0_GTREFCLK_PAD_N_IN ); - GT_TX_WORD_CLK(i) <= GT_TXUSRCLK(i); - - GTRXOUTCLK_BUFG: bufg_gt - port map( - i => GT_RXOUTCLK(i), - div => "000", - clr => '0',--userclk_tx_reset_in,--'0', - cemask => '0', - clrmask => '0', - ce => '1', - o => GT_RXUSRCLK(i) + --bank 231, 232, 233,use clk from bank 232 + ibufds_instq4_clk0 : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) + port map( + O => CXP3_GTH_RefClk, + ODIV2 => open, + CEB => '0', + I => Q4_CLK0_GTREFCLK_PAD_P_IN, + IB => Q4_CLK0_GTREFCLK_PAD_N_IN ); - -- GT_RXUSRCLK(i) <= clk240_in; - - GT_RX_WORD_CLK(i) <= GT_RXUSRCLK(i); - RXUSRCLK_OUT(i) <= GT_RXUSRCLK(i); - end generate; - - - drpclk_in(0) <= clk40_in; - - QPLL_GEN: if PLL_SEL = QPLL generate - - port_trans : for i in GBT_NUM-1 downto 0 generate - RX_N_i(i) <= RX_N(i); - RX_P_i(i) <= RX_P(i); - TX_N(i) <= TX_N_i(i); - TX_P(i) <= TX_P_i(i); - - end generate; - - GTH_inst : for i in (GBT_NUM-1)/4 downto 0 generate - - RX_DATA_20b(4*i+0) <= RX_DATA_80b(i)(19 downto 0); - RX_DATA_20b(4*i+1) <= RX_DATA_80b(i)(39 downto 20); - RX_DATA_20b(4*i+2) <= RX_DATA_80b(i)(59 downto 40); - RX_DATA_20b(4*i+3) <= RX_DATA_80b(i)(79 downto 60); - - TX_DATA_80b(i) <= TX_DATA_20b(4*i+3) & TX_DATA_20b(4*i+2) & TX_DATA_20b(4*i+1) & TX_DATA_20b(4*i+0); - - GTH_TOP_INST: entity work.GTH_QPLL_Wrapper - Port map( - gthrxn_in => RX_N_i(4*i+3 downto 4*i), - gthrxp_in => RX_P_i(4*i+3 downto 4*i), - gthtxn_out => TX_N_i(4*i+3 downto 4*i), - gthtxp_out => TX_P_i(4*i+3 downto 4*i), - - drpclk_in => drpclk_in,--(others=>clk40_in), - gtrefclk0_in => GTH_RefClk(4*i downto 4*i), - gt_rxusrclk_in => GT_RX_WORD_CLK(4*i+3 downto 4*i), - gt_rxoutclk_out => GT_RXOUTCLK(4*i+3 downto 4*i), - gt_txusrclk_in => GT_TX_WORD_CLK(4*i+3 downto 4*i), - gt_txoutclk_out => GT_TXOUTCLK(4*i+3 downto 4*i), - - userdata_tx_in => TX_DATA_80b(i), - userdata_rx_out => RX_DATA_80b(i), - rxpolarity_in => register_map_control.GBT_RXPOLARITY(4*i+3 downto 4*i), - txpolarity_in => register_map_control.GBT_TXPOLARITY(4*i+3 downto 4*i), - - - -- for loopback: default, both signal need to be all '0' - -- read kcu gth manual for the details. NOTE: the TXBUFFER is disabled, so some type of loopbhack may be - -- not supported. - -- for loopback rxcdrhold needs to be set, a register needs to be added, check KCU GTH manual for details - -- not tested yet - loopback_in => register_map_control.GTH_LOOPBACK_CONTROL, - rxcdrhold_in => '0', - - userclk_rx_reset_in => userclk_rx_reset_in(i downto i),--(others=>(not rxpmaresetdone_out(i))),--locked, - userclk_tx_reset_in => userclk_tx_reset_in(i downto i),--(others=>(not txpmaresetdone_out(i))),--,--locked, - - -- reset_clk_freerun_in : in std_logic_vector(0 downto 0); - reset_all_in => SOFT_RESET_f(i downto i), - reset_tx_pll_and_datapath_in => QPLL_RESET(i downto i), - reset_tx_datapath_in => GTTX_RESET_MERGE(i downto i), - reset_rx_pll_and_datapath_in => QPLL_RESET(i downto i), - reset_rx_datapath_in => GTRX_RESET_MERGE(i downto i), - - qpll0lock_out => open, - qpll1lock_out => QpllLock(i downto i), - qpll1fbclklost_out => open,-- - qpll0fbclklost_out => open, - rxslide_in => RxSlide(4*i+3 downto 4*i), - - rxresetdone_out => rxresetdone(4*i+3 downto 4*i), - txresetdone_out => txresetdone(4*i+3 downto 4*i), - rxpmaresetdone_out => rxpmaresetdone(4*i+3 downto 4*i), - txpmaresetdone_out => txpmaresetdone(4*i+3 downto 4*i), - reset_tx_done_out => txresetdone_quad(i downto i), - reset_rx_done_out => rxresetdone_quad(i downto i), - reset_rx_cdr_stable_out => RxCdrLock_quad(i downto i), - rxcdrlock_out => rxcdrlock_out(4*i+3 downto 4*i) + --bank 228 use clk from bank 228 + ibufds_instq5_clk0 : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) + port map( + O => CXP4_GTH_RefClk, + ODIV2 => open, + CEB => '0', + I => Q5_CLK0_GTREFCLK_PAD_P_IN, + IB => Q5_CLK0_GTREFCLK_PAD_N_IN ); + --bank 224, 225 use clk from bank 225 + CXP5: if (CARD_TYPE = 712) generate + ibufds_instq6_clk0 : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) + port map( + O => CXP5_GTH_RefClk, + ODIV2 => open, + CEB => '0', + I => Q6_CLK0_GTREFCLK_PAD_P_IN, + IB => Q6_CLK0_GTREFCLK_PAD_N_IN + ); + end generate CXP5; + + --SLR0 banks: 126, 127, 128, 224, 225, 228 + --SLR1 banks: 131, 132, 133, 231, 232, 233 + g_refclk_8ch: if (GBT_NUM <= 8) generate + GTH_RefClk( 0) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + GTH_RefClk( 1) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + GTH_RefClk( 2) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + GTH_RefClk( 3) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + + GTH_RefClk( 4) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + GTH_RefClk( 5) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + GTH_RefClk( 6) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + GTH_RefClk( 7) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + end generate g_refclk_8ch; + + g_refclk_16ch: if ((8 < GBT_NUM) and (GBT_NUM <= 16)) generate + GTH_RefClk( 0) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + GTH_RefClk( 1) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + GTH_RefClk( 2) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + GTH_RefClk( 3) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + GTH_RefClk( 4) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) + GTH_RefClk( 5) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) + GTH_RefClk( 6) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) + GTH_RefClk( 7) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) + + GTH_RefClk( 8) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + GTH_RefClk( 9) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + GTH_RefClk(10) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + GTH_RefClk(11) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + GTH_RefClk(12) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) + GTH_RefClk(13) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) + GTH_RefClk(14) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) + GTH_RefClk(15) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) + end generate g_refclk_16ch; + + g_refclk_24ch: if ((16 < GBT_NUM) and (GBT_NUM <= 24)) generate + GTH_RefClk( 0) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + GTH_RefClk( 1) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + GTH_RefClk( 2) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + GTH_RefClk( 3) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + GTH_RefClk( 4) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) + GTH_RefClk( 5) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) + GTH_RefClk( 6) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) + GTH_RefClk( 7) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) + GTH_RefClk( 8) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) + GTH_RefClk( 9) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) + GTH_RefClk(10) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) + GTH_RefClk(11) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) + + GTH_RefClk(12) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + GTH_RefClk(13) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + GTH_RefClk(14) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + GTH_RefClk(15) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + GTH_RefClk(16) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) + GTH_RefClk(17) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) + GTH_RefClk(18) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) + GTH_RefClk(19) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) + GTH_RefClk(20) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) + GTH_RefClk(21) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) + GTH_RefClk(22) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) + GTH_RefClk(23) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) + end generate g_refclk_24ch; + + g_refclk_48ch: if ((24 < GBT_NUM) and (GBT_NUM <= 48)) generate + GTH_RefClk( 0) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + GTH_RefClk( 1) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + GTH_RefClk( 2) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + GTH_RefClk( 3) <= CXP1_GTH_RefClk;--bank 128 (up to 8 channels) + GTH_RefClk( 4) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) + GTH_RefClk( 5) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) + GTH_RefClk( 6) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) + GTH_RefClk( 7) <= CXP1_GTH_RefClk;--bank 127 (up to 16 channels) + GTH_RefClk( 8) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) + GTH_RefClk( 9) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) + GTH_RefClk(10) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) + GTH_RefClk(11) <= CXP1_GTH_RefClk;--bank 126 (up to 24 channels) + GTH_RefClk(12) <= CXP4_GTH_RefClk;--bank 228 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(13) <= CXP4_GTH_RefClk;--bank 228 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(14) <= CXP4_GTH_RefClk;--bank 228 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(15) <= CXP4_GTH_RefClk;--bank 228 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(16) <= CXP5_GTH_RefClk;--bank 224 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(17) <= CXP5_GTH_RefClk;--bank 224 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(18) <= CXP5_GTH_RefClk;--bank 224 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(19) <= CXP5_GTH_RefClk;--bank 224 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(20) <= CXP5_GTH_RefClk;--bank 225 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(21) <= CXP5_GTH_RefClk;--bank 225 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(22) <= CXP5_GTH_RefClk;--bank 225 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(23) <= CXP5_GTH_RefClk;--bank 225 (up to 48 channels) - BNL712 ONLY + + GTH_RefClk(24) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + GTH_RefClk(25) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + GTH_RefClk(26) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + GTH_RefClk(27) <= CXP2_GTH_RefClk;--bank 133 (up to 8 channels) + GTH_RefClk(28) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) + GTH_RefClk(29) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) + GTH_RefClk(30) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) + GTH_RefClk(31) <= CXP2_GTH_RefClk;--bank 132 (up to 16 channels) + GTH_RefClk(32) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) + GTH_RefClk(33) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) + GTH_RefClk(34) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) + GTH_RefClk(35) <= CXP2_GTH_RefClk;--bank 131 (up to 24 channels) + GTH_RefClk(36) <= CXP3_GTH_RefClk;--bank 231 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(37) <= CXP3_GTH_RefClk;--bank 231 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(38) <= CXP3_GTH_RefClk;--bank 231 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(39) <= CXP3_GTH_RefClk;--bank 231 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(40) <= CXP3_GTH_RefClk;--bank 232 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(41) <= CXP3_GTH_RefClk;--bank 232 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(42) <= CXP3_GTH_RefClk;--bank 232 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(43) <= CXP3_GTH_RefClk;--bank 232 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(44) <= CXP3_GTH_RefClk;--bank 233 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(45) <= CXP3_GTH_RefClk;--bank 233 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(46) <= CXP3_GTH_RefClk;--bank 233 (up to 48 channels) - BNL712 ONLY + GTH_RefClk(47) <= CXP3_GTH_RefClk;--bank 233 (up to 48 channels) - BNL712 ONLY + end generate g_refclk_48ch; + + --IG GTH_RefClk(0) <= CXP1_GTH_RefClk; + --IG GTH_RefClk(1) <= CXP1_GTH_RefClk; + --IG GTH_RefClk(2) <= CXP1_GTH_RefClk; + --IG GTH_RefClk(3) <= CXP1_GTH_RefClk; + --IG GTH_RefClk(4) <= CXP1_GTH_RefClk; + --IG GTH_RefClk(5) <= CXP1_GTH_RefClk; + --IG GTH_RefClk(6) <= CXP1_GTH_RefClk; + --IG GTH_RefClk(7) <= CXP1_GTH_RefClk; + --IG + --IG -- For 16 channels (and below) put 8 channels in SRL0, channel 8..15 in SRL1. + --IG g_refclk0: if GBT_NUM <= 16 generate + --IG GTH_RefClk(8) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(9) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(10) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(11) <= CXP2_GTH_RefClk; + --IG end generate; + --IG + --IG -- For 24 channels put 12 channels in SRL0, channel 12..23 in SRL1. + --IG g_refclk1: if GBT_NUM > 16 generate + --IG GTH_RefClk(8) <= CXP1_GTH_RefClk; + --IG GTH_RefClk(9) <= CXP1_GTH_RefClk; + --IG GTH_RefClk(10) <= CXP1_GTH_RefClk; + --IG GTH_RefClk(11) <= CXP1_GTH_RefClk; + --IG end generate; + --IG + --IG refclkgen_v2p0 : if CARD_TYPE=712 generate + --IG g_refclk11: if GBT_NUM <25 generate + --IG --IBUFDS_GTE2 + --IG + --IG GTH_RefClk(12) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(13) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(14) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(15) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(16) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(17) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(18) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(19) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(20) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(21) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(22) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(23) <= CXP2_GTH_RefClk; + --IG end generate; + --IG g_refclk12: if GBT_NUM >24 generate + --IG GTH_RefClk(24) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(25) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(26) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(27) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(28) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(29) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(30) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(31) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(32) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(33) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(34) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(35) <= CXP2_GTH_RefClk; + --IG + --IG GTH_RefClk(36) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(37) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(38) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(39) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(40) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(41) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(42) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(43) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(44) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(45) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(46) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(47) <= CXP3_GTH_RefClk; + --IG + --IG GTH_RefClk(12) <= CXP4_GTH_RefClk; + --IG GTH_RefClk(13) <= CXP4_GTH_RefClk; + --IG GTH_RefClk(14) <= CXP4_GTH_RefClk; + --IG GTH_RefClk(15) <= CXP4_GTH_RefClk; + --IG + --IG GTH_RefClk(16) <= CXP5_GTH_RefClk; + --IG GTH_RefClk(17) <= CXP5_GTH_RefClk; + --IG GTH_RefClk(18) <= CXP5_GTH_RefClk; + --IG GTH_RefClk(19) <= CXP5_GTH_RefClk; + --IG GTH_RefClk(20) <= CXP5_GTH_RefClk; + --IG GTH_RefClk(21) <= CXP5_GTH_RefClk; + --IG GTH_RefClk(22) <= CXP5_GTH_RefClk; + --IG GTH_RefClk(23) <= CXP5_GTH_RefClk; + --IG + --IG--bank 224, 225 use clk from bank 225 + --IG ibufds_instq6_clk0 : IBUFDS_GTE3 + --IG port map + --IG ( + --IG O => CXP5_GTH_RefClk, + --IG ODIV2 => open, + --IG CEB => '0', + --IG I => Q6_CLK0_GTREFCLK_PAD_P_IN, + --IG IB => Q6_CLK0_GTREFCLK_PAD_N_IN + --IG ); + --IG + --IG end generate; + --IG + --IG end generate; + --IG + --IGrefclkgen_v1p5 : if CARD_TYPE=711 generate + --IG + --IG + --IG GTH_RefClk(12) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(13) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(14) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(15) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(16) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(17) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(18) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(19) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(20) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(21) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(22) <= CXP2_GTH_RefClk; + --IG GTH_RefClk(23) <= CXP2_GTH_RefClk; + --IG + --IG + --IG GTH_RefClk(24) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(25) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(26) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(27) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(28) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(29) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(30) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(31) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(32) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(33) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(34) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(35) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(40) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(41) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(42) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(43) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(44) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(45) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(46) <= CXP3_GTH_RefClk; + --IG GTH_RefClk(47) <= CXP3_GTH_RefClk; + --IG + --IG + --IG GTH_RefClk(36) <= CXP4_GTH_RefClk; + --IG GTH_RefClk(37) <= CXP4_GTH_RefClk; + --IG GTH_RefClk(38) <= CXP4_GTH_RefClk; + --IG GTH_RefClk(39) <= CXP4_GTH_RefClk; + --IG + --IG end generate; + + Channel_disable(47 downto 0) <= register_map_control.GBT_CHANNEL_DISABLE; + General_ctrl <= register_map_control.GBT_GENERAL_CTRL; + + --rxslide_manual(47 downto 0) <= register_map_control.GBT_RXSLIDE_MANUAL(47 downto 0); + --rxslide_sel(47 downto 0) <= register_map_control.GBT_RXSLIDE_SELECT(47 downto 0); + --txusrrdy(47 downto 0) <= register_map_control.GBT_TXUSRRDY(47 downto 0); + --rxusrrdy(47 downto 0) <= register_map_control.GBT_RXUSRRDY(47 downto 0); + gttx_reset(47 downto 0) <= register_map_control.GBT_GTTX_RESET(47 downto 0); + gtrx_reset(47 downto 0) <= register_map_control.GBT_GTRX_RESET(47 downto 0); + soft_reset(47 downto 0) <= register_map_control.GBT_SOFT_RESET(47 downto 0); + cpll_reset(47 downto 0) <= register_map_control.GBT_PLL_RESET.CPLL_RESET(47 downto 0); + qpll_reset(11 downto 0) <= register_map_control.GBT_PLL_RESET.QPLL_RESET(59 downto 48); + + --SOFT_TXRST_GT(47 downto 0) <= register_map_control.GBT_SOFT_TX_RESET.RESET_GT; -- Default: 0b000 + --SOFT_RXRST_GT(47 downto 0) <= register_map_control.GBT_SOFT_RX_RESET.RESET_GT; -- Default: 0b000 + --SOFT_TXRST_ALL(11 downto 0) <= register_map_control.GBT_SOFT_TX_RESET.RESET_ALL(59 downto 48); + --SOFT_RXRST_ALL(11 downto 0) <= register_map_control.GBT_SOFT_RX_RESET.RESET_ALL(59 downto 48); + + --OddEven(47 downto 0) <= register_map_control.GBT_ODD_EVEN(47 downto 0); + --TopBot(47 downto 0) <= register_map_control.GBT_TOPBOT(47 downto 0); + + TX_TC_DLY_VALUE(47 downto 0) <= register_map_control.GBT_TX_TC_DLY_VALUE1; + TX_TC_DLY_VALUE(95 downto 48) <=register_map_control.GBT_TX_TC_DLY_VALUE2; + TX_TC_DLY_VALUE(143 downto 96) <= register_map_control.GBT_TX_TC_DLY_VALUE3; + TX_TC_DLY_VALUE(191 downto 144) <= register_map_control.GBT_TX_TC_DLY_VALUE4; + + + -- TX_OPT(47 downto 0) <= GBT_TX_OPT(47 DOWNTO 0); -- + -- RX_OPT(47 downto 0) <= GBT_RX_OPT(47 DOWNTO 0); -- + + + -- GBT_TX_OPT(47 downto 0) <= x"000000555555"; -- ! TODO:Register was removed in RM4.0 register_map_control.GBT_TX_OPT; + -- GBT_RX_OPT(47 downto 0) <= x"000000555555"; -- ! TODO:Register was removed in RM4.0 register_map_control.GBT_RX_OPT; + DATA_TXFORMAT(47 downto 0) <= register_map_control.GBT_DATA_TXFORMAT1(47 downto 0); + DATA_RXFORMAT(47 downto 0) <= register_map_control.GBT_DATA_RXFORMAT1(47 downto 0); + DATA_TXFORMAT(95 downto 48) <= register_map_control.GBT_DATA_TXFORMAT2(47 downto 0); + DATA_RXFORMAT(95 downto 48) <= register_map_control.GBT_DATA_RXFORMAT2(47 downto 0); + + TX_RESET(47 downto 0) <= register_map_control.GBT_TX_RESET(47 downto 0); + RX_RESET(47 downto 0) <= register_map_control.GBT_RX_RESET(47 downto 0); + TX_TC_METHOD(47 downto 0) <= register_map_control.GBT_TX_TC_METHOD(47 downto 0); + TC_EDGE(47 downto 0) <= register_map_control.GBT_TC_EDGE(47 downto 0); + outsel_i(47 downto 0) <= register_map_control.GBT_OUTMUX_SEL(47 downto 0); + + register_map_link_monitor.GBT_VERSION.DATE <= GBT_VERSION(63 downto 48); + register_map_link_monitor.GBT_VERSION.GBT_VERSION(35 downto 32) <= GBT_VERSION(23 downto 20); + register_map_link_monitor.GBT_VERSION.GTH_IP_VERSION(19 downto 16) <= GBT_VERSION(19 downto 16); + register_map_link_monitor.GBT_VERSION.RESERVED <= GBT_VERSION(15 downto 3); + register_map_link_monitor.GBT_VERSION.GTHREFCLK_SEL <= (others => GTHREFCLK_SEL); + register_map_link_monitor.GBT_VERSION.RX_CLK_SEL <= GBT_VERSION(1 downto 1); + register_map_link_monitor.GBT_VERSION.PLL_SEL <= GBT_VERSION(0 downto 0); + + -- + + register_map_link_monitor.GBT_TXRESET_DONE(47 downto 0) <= txresetdone(47 downto 0); + register_map_link_monitor.GBT_RXRESET_DONE(47 downto 0) <= rxresetdone(47 downto 0); + register_map_link_monitor.GBT_TXFSMRESET_DONE(47 downto 0) <= TXPMARESETDONE(47 downto 0); + register_map_link_monitor.GBT_RXFSMRESET_DONE(47 downto 0) <= RXPMARESETDONE(47 downto 0); + register_map_link_monitor.GBT_CPLL_FBCLK_LOST(47 downto 0) <= cpllfbclklost (47 downto 0); + register_map_link_monitor.GBT_PLL_LOCK.CPLL_LOCK(47 downto 0) <= cplllock(47 downto 0); + register_map_link_monitor.GBT_PLL_LOCK.QPLL_LOCK(59 downto 48) <= qplllock(11 downto 0); + register_map_link_monitor.GBT_RXCDR_LOCK(47 downto 0) <= rxcdrlock(47 downto 0); + register_map_link_monitor.GBT_CLK_SAMPLED(47 downto 0) <= (others => '0'); --never written clk_sampled(47 downto 0); + + register_map_link_monitor.GBT_RX_IS_HEADER(47 downto 0) <= rx_is_header(47 downto 0); + register_map_link_monitor.GBT_RX_IS_DATA(47 downto 0) <= (others => '0'); --rx_is_data(47 downto 0); + register_map_link_monitor.GBT_RX_HEADER_FOUND(47 downto 0) <= RX_HEADER_FOUND(47 downto 0); + + register_map_link_monitor.GBT_ALIGNMENT_DONE(47 downto 0) <= alignment_done_f(47 downto 0); + + + -- aligndone_gen : for i in 23 downto 0 generate + -- alignment_done_f(i) <= RxCdrLock(i) and alignment_done(i); + -- end generate; + + register_map_link_monitor.GBT_OUT_MUX_STATUS(47 downto 0) <= outsel_o(47 downto 0); + register_map_link_monitor.GBT_ERROR(47 downto 0) <= error_f(47 downto 0); - process(clk40_in) - begin - if clk40_in'event and clk40_in='1' then - if cdr_cnt ="00000000000000000000" then - RxCdrLock_a(4*i) <= rxcdrlock_out(4*i); - RxCdrLock_a(4*i+1) <= rxcdrlock_out(4*i+1); - RxCdrLock_a(4*i+2) <= rxcdrlock_out(4*i+2); - RxCdrLock_a(4*i+3) <= rxcdrlock_out(4*i+3); - else - RxCdrLock_a(4*i) <= RxCdrLock_a(4*i) and rxcdrlock_out(4*i); - RxCdrLock_a(4*i+1) <= RxCdrLock_a(4*i+1) and rxcdrlock_out(4*i+1); - RxCdrLock_a(4*i+2) <= RxCdrLock_a(4*i+2) and rxcdrlock_out(4*i+2); - RxCdrLock_a(4*i+3) <= RxCdrLock_a(4*i+3) and rxcdrlock_out(4*i+3); - end if; - if cdr_cnt="00000000000000000000" then - RxCdrLock_int(4*i) <=RxCdrLock_a(4*i); - RxCdrLock_int(4*i+1) <=RxCdrLock_a(4*i+1); - RxCdrLock_int(4*i+2) <=RxCdrLock_a(4*i+2); - RxCdrLock_int(4*i+3) <=RxCdrLock_a(4*i+3); - end if; - end if; - end process; - RxCdrLock(4*i) <= (not Channel_disable(4*i)) and RxCdrLock_int(4*i); - RxCdrLock(4*i+1) <= (not Channel_disable(4*i+1)) and RxCdrLock_int(4*i+1); - RxCdrLock(4*i+2) <= (not Channel_disable(4*i+2)) and RxCdrLock_int(4*i+2); - RxCdrLock(4*i+3) <= (not Channel_disable(4*i+3)) and RxCdrLock_int(4*i+3); - - SOFT_RESET_f(i) <= SOFT_RESET(i) or QPLL_RESET(i);--or rst_hw;-- or GTRX_RESET(i); - - userclk_rx_reset_in(i) <=not (rxpmaresetdone(4*i+0) or rxpmaresetdone(4*i+1) or rxpmaresetdone(4*i+2) or rxpmaresetdone(4*i+3)); - userclk_tx_reset_in(i) <=not (txpmaresetdone(4*i+0) or txpmaresetdone(4*i+1) or txpmaresetdone(4*i+2) or txpmaresetdone(4*i+3)); - - GTTX_RESET_MERGE(i) <= GTTX_RESET(4*i) or GTTX_RESET(4*i+1) or GTTX_RESET(4*i+2) or GTTX_RESET(4*i+3); - GTRX_RESET_MERGE(i) <= (GTRX_RESET(4*i) or (auto_gth_rxrst(4*i) and RxCdrLock(4*i))) - or (GTRX_RESET(4*i+1) or (auto_gth_rxrst(4*i+1) and RxCdrLock(4*i+1))) - or (GTRX_RESET(4*i+2) or (auto_gth_rxrst(4*i+2) and RxCdrLock(4*i+2))) - or (GTRX_RESET(4*i+3) or (auto_gth_rxrst(4*i+3) and RxCdrLock(4*i+3))) ; - --GTRX_RESET_MERGE(i) <= GTRX_RESET(4*i) or GTRX_RESET(4*i+1) or GTRX_RESET(4*i+2) or GTRX_RESET(4*i+3); - - -- CpllLock(i) <= '1'; - - end generate; - end generate; - + error_gen : for i in 47 downto 0 generate + error_f(i) <= error_orig(i) and alignment_done_f(i); + end generate; - process(clk40_in) - begin - if clk40_in'event and clk40_in='1' then - cdr_cnt <=cdr_cnt+'1'; - end if; - end process; + register_map_link_monitor.GBT_GBT_TOPBOT_C(47 downto 0) <= (others => '0');--TopBot_C(47 downto 0); - CPLL_GEN: if PLL_SEL = CPLL generate - GTH_inst : for i in GBT_NUM-1 downto 0 generate + ---------------------------------------- + ------ REGISTERS MAPPING + ---------------------------------------- + alignment_chk_rst_i <= General_ctrl(0); - GTH_TOP_INST: entity work.GTH_CPLL_Wrapper - Port map( - gthrxn_in => RX_N(i downto i), - gthrxp_in => RX_P(i downto i), - gthtxn_out => TX_N(i downto i), - gthtxp_out => TX_P(i downto i), - drpclk_in => drpclk_in,--(others=>clk40_in), - gtrefclk0_in => GTH_RefClk(i downto i), - gt0_rxusrclk_in => GT_RX_WORD_CLK(i downto i), - gt0_rxoutclk_out => GT_RXOUTCLK(i downto i), - gt0_txusrclk_in => GT_TX_WORD_CLK(i downto i), - gt0_txoutclk_out => GT_TXOUTCLK(i downto i), + DESMUX_USE_SW <= register_map_control.GBT_MODE_CTRL.DESMUX_USE_SW(0); + --RX_ALIGN_SW <= register_map_control.GBT_MODE_CTRL.RX_ALIGN_SW(1); + --RX_ALIGN_TB_SW <= register_map_control.GBT_MODE_CTRL.RX_ALIGN_TB_SW(2); - userdata_tx_in => TX_DATA_20b(i), - userdata_rx_out => RX_DATA_20b(i), - rxpolarity_in => register_map_control.GBT_RXPOLARITY(i downto i), - txpolarity_in => register_map_control.GBT_TXPOLARITY(i downto i), - -- for loopback: default, both signal need to be all '0' - -- read kcu gth manual for the details. NOTE: the TXBUFFER is disabled, so some type of loopbhack may be - -- not supported. - -- for loopback rxcdrhold needs to be set, a register needs to be added, check KCU GTH manual for details - -- not tested yet - loopback_in => register_map_control.GTH_LOOPBACK_CONTROL, - rxcdrhold_in => '0', - userclk_rx_reset_in => userclk_rx_reset_in(i downto i),--(others=>(not rxpmaresetdone_out(i))),--locked, - userclk_tx_reset_in => userclk_tx_reset_in(i downto i),--(others=>(not txpmaresetdone_out(i))),--,--locked, - -- reset_clk_freerun_in : in std_logic_vector(0 downto 0); - reset_all_in => SOFT_RESET_f(i downto i), - reset_tx_pll_and_datapath_in => CPLL_RESET(i downto i), - reset_tx_datapath_in => GTTX_RESET(i downto i), - reset_rx_pll_and_datapath_in => CPLL_RESET(i downto i), - reset_rx_datapath_in => GTRX_RESET_i(i downto i),-- and RxCdrLock(i downto i), + ------- - cpllfbclklost_out => cpllfbclklost(i downto i), - cplllock_out => cplllock(i downto i), + datamod_gen1 : if DYNAMIC_DATA_MODE_EN='1' generate + DATA_TXFORMAT_i <= DATA_TXFORMAT; + DATA_RXFORMAT_i <= DATA_RXFORMAT; + end generate; + datamod_gen2 : if DYNAMIC_DATA_MODE_EN='0' generate + DATA_TXFORMAT_i <= GBT_DATA_TXFORMAT_PACKAGE; + DATA_RXFORMAT_i <= GBT_DATA_RXFORMAT_PACKAGE; + end generate; - rxslide_in => RxSlide(i downto i), - - - - rxpmaresetdone_out => rxpmaresetdone(i downto i), - txpmaresetdone_out => txpmaresetdone(i downto i), - - reset_tx_done_out => txresetdone(i downto i), - reset_rx_done_out => rxresetdone(i downto i), - reset_rx_cdr_stable_out => RxCdrLock_int(i downto i) + process(clk40_in) + begin + if clk40_in'event and clk40_in='1' then + pulse_lg <= pulse_cnt(20); + if pulse_cnt(20)='1' then + pulse_cnt <=(others=>'0'); + else + pulse_cnt <= pulse_cnt+'1'; + end if; + end if; + end process; - ); + process(clk40_in) + begin + if clk40_in'event and clk40_in='1' then + alignment_done_chk_cnt <= alignment_done_chk_cnt + '1'; + end if; + end process; + rxalign_auto : for i in GBT_NUM-1 downto 0 generate + + -- process(clk40_in) + -- begin + -- if clk40_in'event and clk40_in='1' then + -- if pulse_lg = '1' then + -- gbt_sel(i) <= lock_lg(i); + -- end if; + -- if pulse_lg = '1' then + -- lock_lg(i) <='1'; + -- elsif alignment_done_f(i)='0' then + -- lock_lg(i) <='0'; + -- end if; + -- end if; + -- end process; + + process(clk40_in) + begin + if clk40_in'event and clk40_in='1' then + if alignment_done_chk_cnt="0000000000000" then + alignment_done_a(i) <= rxcdrlock(i) and alignment_done(i); + else + alignment_done_a(i) <= rxcdrlock(i) and alignment_done(i) and alignment_done_a(i); + end if; + if alignment_done_chk_cnt="0000000000000" then + alignment_done_f(i) <= rxcdrlock(i) and alignment_done_a(i); + end if; + end if; + end process; + + + RX_120b_out(i) <= RX_120b_out_ii(i) when alignment_done_f(i)='1' + else (others =>'0'); + + auto_rxrst : entity work.FELIX_GBT_RX_AUTO_RST + port map( + ext_trig_realign => open, --ext_trig_realign(i), + FSM_CLK => clk40_in, + GBT_LOCK => alignment_done_f(i), --alignment_done(i), + pulse_lg => pulse_lg, + GTHRXRESET_DONE => rxresetdone(i), -- and RxFsmResetDone(i), + AUTO_GTH_RXRST => auto_gth_rxrst(i), + alignment_chk_rst => alignment_chk_rst_c1(i), + AUTO_GBT_RXRST => auto_gbt_rxrst(i) + ); + + rafsm : entity work.FELIX_GBT_RXSLIDE_FSM + port map( + alignment_chk_rst => alignment_chk_rst_c(i), + --ext_trig_realign => ext_trig_realign(i), + FSM_RST => FSM_RST(i), + FSM_CLK => clk40_in, + GBT_LOCK => alignment_done(i), + RxSlide => RxSlide_c(i) + ); + + FSM_RST(i) <= RX_RESET(i);-- or RX_ALIGN_SW; + -- GTRX_RESET_i(i) <= --GTRX_RESET(i) when RX_ALIGN_SW='1' else + -- (GTRX_RESET(i) or auto_gth_rxrst(i)); + RX_RESET_i(i) <= --RX_RESET(i) when RX_ALIGN_SW='1' else + (RX_RESET(i) or auto_gbt_rxrst(i)); + alignment_chk_rst(i) <= --alignment_chk_rst_i when RX_ALIGN_SW='1' else + (alignment_chk_rst_i or alignment_chk_rst_c(i) or alignment_chk_rst_c1(i)); + RxSlide_i(i) <= RxSlide_c(i) and rxcdrlock(i); + TX_RESET_i(i) <= TX_RESET(i) or (not txresetdone(i));-- or (not TxFsmResetDone(i)); + end generate; + + outsel_ii <= outsel_o when DESMUX_USE_SW = '0' else outsel_i; + + -- OddEven_i <= OddEven_c when RX_ALIGN_SW ='0' else + -- OddEven; + + -- TopBot_i <= TopBot_c when RX_ALIGN_SW='0' else --and RX_ALIGN_TB_SW='0' else + -- TopBot; + + --RxSlide_i <= RxSlide_c;-- when RX_ALIGN_SW='0' else + -- RxSlide_Manual; + + RX_FLAG_O <= RX_FLAG_Oi(GBT_NUM-1 downto 0); + + gbtRxTx : for i in GBT_NUM-1 downto 0 generate + process(GT_RX_WORD_CLK(i)) + begin + if GT_RX_WORD_CLK(i)'event and GT_RX_WORD_CLK(i)='1' then + BITSLIP_MANUAL_r(i) <= RxSlide_i(i); + BITSLIP_MANUAL_2r(i) <= BITSLIP_MANUAL_r(i); + --BITSLIP_MANUAL_3r(i) <= BITSLIP_MANUAL_2r(i); + RxSlide(i) <= BITSLIP_MANUAL_r(i) and (not BITSLIP_MANUAL_2r(i)); + end if; + end process; + + + alignment_chk_rst_f(i) <= alignment_chk_rst(i);-- or (not RxCdrLock(i)); + gbtTxRx_inst: entity work.gbtTxRx_FELIX + generic map( + channel => i + ) + port map( + alignment_chk_rst => alignment_chk_rst_f(i), + alignment_done_O => alignment_done(i), + outsel_i => outsel_ii(i), + outsel_o => outsel_o(i), + error_o => error_orig(i), + TX_TC_DLY_VALUE => TX_TC_DLY_VALUE(4*i+2 downto 4*i), + TX_TC_METHOD => TX_TC_METHOD(i), + TC_EDGE => TC_EDGE(i), + RX_FLAG => RX_FLAG_Oi(i), --RX_FLAG_O(i), + TX_FLAG => TX_FLAG_O(i), + --Tx_latopt_scr => '1', --TX_OPT(24+i), + --Tx_latopt_tc => '1', --TX_OPT(i), + RX_LATOPT_DES => '1', --RX_OPT(i), + Tx_DATA_FORMAT => DATA_TXFORMAT_i(2*i+1 downto 2*i), + Rx_Data_Format => DATA_RXFORMAT_i(2*i+1 downto 2*i), + RX_RESET_I => RX_RESET_i(i), + RX_FRAME_CLK_O => open, --RX_FRAME_CLK_O(i), + RX_HEADER_FOUND => RX_HEADER_FOUND(i), + RX_WORD_IS_HEADER_O => rx_is_header(i), + RX_WORDCLK_I => GT_RX_WORD_CLK(i), + L40M => clk40_in, + --RX_ISDATA_FLAG_O => rx_is_data(i), + RX_DATA_20b_I => RX_DATA_20b(i), + RX_DATA_120b_O => RX_120b_out_i(i), + TX_RESET_I => TX_RESET_i(i), + TX_FRAMECLK_I => TX_FRAME_CLK_I(i), + des_rxusrclk => GT_RX_WORD_CLK(i), + TX_WORDCLK_I => GT_TX_WORD_CLK(i), + --TX_ISDATA_SEL_I => TX_IS_DATA(i), + TX_DATA_120b_I => TX_120b_in(i), + TX_DATA_20b_O => TX_DATA_20b(i) + ); + + fifo_rst(i) <= rst_hw or (not alignment_done_f(i)) or RX_RESET_i(i) or General_ctrl(4); + fifo_rden(i) <= not fifo_empty(i); + + fifo_inst: fifo_GBT2CR + PORT MAP( + wr_clk => GT_RX_WORD_CLK(i), + wr_rst => fifo_rst(i), --rst_hw, + rd_clk => clk40_in, --FIFO_RD_CLK(i), + rd_rst => fifo_rst(i), --rst_hw, + din => RX_120b_out_i(i), + wr_en => RX_FLAG_Oi(i), + rd_en => fifo_rden(i), --not fifo_empty(i),--'1',--FIFO_RD_EN(i), + dout => RX_120b_out_ii(i), + full => open, + empty => open, + prog_empty => fifo_empty(i) --FIFO_EMPTY(i) + ); + + end generate; + + + + + + ------------------------------- + ------ GTH TOP WRAPPER + ------------------------------- + + clk_generate : for i in GBT_NUM-1 downto 0 generate + + GTTXOUTCLK_BUFG: bufg_gt + generic map( + SIM_DEVICE => "ULTRASCALE", + STARTUP_SYNC => "FALSE" + ) + port map( + o => GT_TXUSRCLK(i), + ce => '1', + cemask => '0', + clr => '0', --userclk_tx_reset_in,--'0', + clrmask => '0', + div => "000", + i => GT_TXOUTCLK(i) + ); + + GT_TX_WORD_CLK(i) <= GT_TXUSRCLK(i); + + GTRXOUTCLK_BUFG: bufg_gt + generic map( + SIM_DEVICE => "ULTRASCALE", + STARTUP_SYNC => "FALSE" + ) + port map( + o => GT_RXUSRCLK(i), + ce => '1', + cemask => '0', + clr => '0', --userclk_tx_reset_in,--'0', + clrmask => '0', + div => "000", + i => GT_RXOUTCLK(i) + ); + + -- GT_RXUSRCLK(i) <= clk240_in; + + GT_RX_WORD_CLK(i) <= GT_RXUSRCLK(i); + RXUSRCLK_OUT(i) <= GT_RXUSRCLK(i); + end generate; + + + drpclk_in(0) <= clk40_in; + + QPLL_GEN: if PLL_SEL = QPLL generate + + port_trans : for i in GBT_NUM-1 downto 0 generate + RX_N_i(i) <= RX_N(i); + RX_P_i(i) <= RX_P(i); + TX_N(i) <= TX_N_i(i); + TX_P(i) <= TX_P_i(i); + + end generate; + + GTH_inst : for i in (GBT_NUM-1)/4 downto 0 generate + + RX_DATA_20b(4*i+0) <= RX_DATA_80b(i)(19 downto 0); + RX_DATA_20b(4*i+1) <= RX_DATA_80b(i)(39 downto 20); + RX_DATA_20b(4*i+2) <= RX_DATA_80b(i)(59 downto 40); + RX_DATA_20b(4*i+3) <= RX_DATA_80b(i)(79 downto 60); + + TX_DATA_80b(i) <= TX_DATA_20b(4*i+3) & TX_DATA_20b(4*i+2) & TX_DATA_20b(4*i+1) & TX_DATA_20b(4*i+0); + + GTH_TOP_INST: entity work.GTH_QPLL_Wrapper + Port map( + gt_rxusrclk_in => GT_RX_WORD_CLK(4*i+3 downto 4*i), + gt_txusrclk_in => GT_TX_WORD_CLK(4*i+3 downto 4*i), + gt_rxoutclk_out => GT_RXOUTCLK(4*i+3 downto 4*i), + gt_txoutclk_out => GT_TXOUTCLK(4*i+3 downto 4*i), + gthrxn_in => RX_N_i(4*i+3 downto 4*i), + gthrxp_in => RX_P_i(4*i+3 downto 4*i), + gthtxn_out => TX_N_i(4*i+3 downto 4*i), + gthtxp_out => TX_P_i(4*i+3 downto 4*i), + drpclk_in => drpclk_in, --(others=>clk40_in), + gtrefclk0_in => GTH_RefClk(4*i downto 4*i), + rxpolarity_in => register_map_control.GBT_RXPOLARITY(4*i+3 downto 4*i), + txpolarity_in => register_map_control.GBT_TXPOLARITY(4*i+3 downto 4*i), + loopback_in => register_map_control.GTH_LOOPBACK_CONTROL, + rxcdrhold_in => '0', + userdata_tx_in => TX_DATA_80b(i), + userdata_rx_out => RX_DATA_80b(i), + userclk_rx_reset_in => userclk_rx_reset_in(i downto i), --(others=>(not rxpmaresetdone_out(i))),--locked, + userclk_tx_reset_in => userclk_tx_reset_in(i downto i), --(others=>(not txpmaresetdone_out(i))),--,--locked, + reset_all_in => soft_reset_f(i downto i), + reset_tx_pll_and_datapath_in => qpll_reset(i downto i), + reset_tx_datapath_in => gttx_reset_merge(i downto i), + reset_rx_pll_and_datapath_in => qpll_reset(i downto i), + reset_rx_datapath_in => gtrx_reset_merge(i downto i), + qpll1lock_out => qplllock(i downto i), + qpll1fbclklost_out => open, -- + qpll0lock_out => open, + qpll0fbclklost_out => open, + rxslide_in => RxSlide(4*i+3 downto 4*i), + txresetdone_out => txresetdone(4*i+3 downto 4*i), + txpmaresetdone_out => TXPMARESETDONE(4*i+3 downto 4*i), + rxresetdone_out => rxresetdone(4*i+3 downto 4*i), + rxpmaresetdone_out => RXPMARESETDONE(4*i+3 downto 4*i), + reset_tx_done_out => open, --txresetdone_quad(i downto i), + reset_rx_done_out => open, --rxresetdone_quad(i downto i), + reset_rx_cdr_stable_out => open, --rxcdrlock_quad(i downto i), + rxcdrlock_out => rxcdrlock_out(4*i+3 downto 4*i) + ); + + + process(clk40_in) + begin + if clk40_in'event and clk40_in='1' then + if cdr_cnt ="00000000000000000000" then + rxcdrlock_a(4*i) <= rxcdrlock_out(4*i); + rxcdrlock_a(4*i+1) <= rxcdrlock_out(4*i+1); + rxcdrlock_a(4*i+2) <= rxcdrlock_out(4*i+2); + rxcdrlock_a(4*i+3) <= rxcdrlock_out(4*i+3); + else + rxcdrlock_a(4*i) <= rxcdrlock_a(4*i) and rxcdrlock_out(4*i); + rxcdrlock_a(4*i+1) <= rxcdrlock_a(4*i+1) and rxcdrlock_out(4*i+1); + rxcdrlock_a(4*i+2) <= rxcdrlock_a(4*i+2) and rxcdrlock_out(4*i+2); + rxcdrlock_a(4*i+3) <= rxcdrlock_a(4*i+3) and rxcdrlock_out(4*i+3); + end if; + if cdr_cnt="00000000000000000000" then + RxCdrLock_int(4*i) <=rxcdrlock_a(4*i); + RxCdrLock_int(4*i+1) <=rxcdrlock_a(4*i+1); + RxCdrLock_int(4*i+2) <=rxcdrlock_a(4*i+2); + RxCdrLock_int(4*i+3) <=rxcdrlock_a(4*i+3); + end if; + end if; + end process; + rxcdrlock(4*i) <= (not Channel_disable(4*i)) and RxCdrLock_int(4*i); + rxcdrlock(4*i+1) <= (not Channel_disable(4*i+1)) and RxCdrLock_int(4*i+1); + rxcdrlock(4*i+2) <= (not Channel_disable(4*i+2)) and RxCdrLock_int(4*i+2); + rxcdrlock(4*i+3) <= (not Channel_disable(4*i+3)) and RxCdrLock_int(4*i+3); + + soft_reset_f(i) <= soft_reset(i) or qpll_reset(i);--or rst_hw;-- or GTRX_RESET(i); + + userclk_rx_reset_in(i) <=not (RXPMARESETDONE(4*i+0) or RXPMARESETDONE(4*i+1) or RXPMARESETDONE(4*i+2) or RXPMARESETDONE(4*i+3)); + userclk_tx_reset_in(i) <=not (TXPMARESETDONE(4*i+0) or TXPMARESETDONE(4*i+1) or TXPMARESETDONE(4*i+2) or TXPMARESETDONE(4*i+3)); + + gttx_reset_merge(i) <= gttx_reset(4*i) or gttx_reset(4*i+1) or gttx_reset(4*i+2) or gttx_reset(4*i+3); + gtrx_reset_merge(i) <= (gtrx_reset(4*i) or (auto_gth_rxrst(4*i) and rxcdrlock(4*i))) + or (gtrx_reset(4*i+1) or (auto_gth_rxrst(4*i+1) and rxcdrlock(4*i+1))) + or (gtrx_reset(4*i+2) or (auto_gth_rxrst(4*i+2) and rxcdrlock(4*i+2))) + or (gtrx_reset(4*i+3) or (auto_gth_rxrst(4*i+3) and rxcdrlock(4*i+3))) ; + --GTRX_RESET_MERGE(i) <= GTRX_RESET(4*i) or GTRX_RESET(4*i+1) or GTRX_RESET(4*i+2) or GTRX_RESET(4*i+3); + + -- CpllLock(i) <= '1'; + + end generate; + end generate; - RxCdrLock(i) <= (not Channel_disable(i)) and RxCdrLock_int(i); - GTRX_RESET_i(i) <= --GTRX_RESET(i) when RX_ALIGN_SW='1' else - GTRX_RESET(i) or (auto_gth_rxrst(i) and RxCdrLock(i)); - SOFT_RESET_f(i) <= SOFT_RESET(i/4) or CPLL_RESET(i);--or rst_hw; -- or GTRX_RESET(i); + process(clk40_in) + begin + if clk40_in'event and clk40_in='1' then + cdr_cnt <=cdr_cnt+'1'; + end if; + end process; - userclk_rx_reset_in(i) <=not rxpmaresetdone(i); - userclk_tx_reset_in(i) <=not txpmaresetdone(i); - --RxResetDone_f(i) <= RxResetDone(i); - end generate; - end generate; + CPLL_GEN: if PLL_SEL = CPLL generate + GTH_inst : for i in GBT_NUM-1 downto 0 generate + + GTH_TOP_INST: entity work.GTH_CPLL_Wrapper + Port map( + cpllfbclklost_out => cpllfbclklost(i downto i), + cplllock_out => cplllock(i downto i), + gt0_rxusrclk_in => GT_RX_WORD_CLK(i downto i), + gt0_txusrclk_in => GT_TX_WORD_CLK(i downto i), + gt0_rxoutclk_out => GT_RXOUTCLK(i downto i), + gt0_txoutclk_out => GT_TXOUTCLK(i downto i), + gthrxn_in => RX_N(i downto i), + gthrxp_in => RX_P(i downto i), + gthtxn_out => TX_N(i downto i), + gthtxp_out => TX_P(i downto i), + drpclk_in => drpclk_in, --(others=>clk40_in), + gtrefclk0_in => GTH_RefClk(i downto i), + rxpolarity_in => register_map_control.GBT_RXPOLARITY(i downto i), + txpolarity_in => register_map_control.GBT_TXPOLARITY(i downto i), + -- for loopback: default, both signal need to be all '0' + -- read kcu gth manual for the details. NOTE: the TXBUFFER is disabled, so some type of loopbhack may be + -- not supported. + -- for loopback rxcdrhold needs to be set, a register needs to be added, check KCU GTH manual for details + -- not tested yet + loopback_in => register_map_control.GTH_LOOPBACK_CONTROL, + rxcdrhold_in => '0', + userdata_tx_in => TX_DATA_20b(i), + userdata_rx_out => RX_DATA_20b(i), + userclk_rx_reset_in => userclk_rx_reset_in(i downto i), --(others=>(not rxpmaresetdone_out(i))),--locked, + userclk_tx_reset_in => userclk_tx_reset_in(i downto i), --(others=>(not txpmaresetdone_out(i))),--,--locked, + reset_all_in => soft_reset_f(i downto i), + reset_tx_pll_and_datapath_in => cpll_reset(i downto i), + reset_tx_datapath_in => gttx_reset(i downto i), + reset_rx_pll_and_datapath_in => cpll_reset(i downto i), + reset_rx_datapath_in => gtrx_reset_i(i downto i), -- and RxCdrLock(i downto i), + rxslide_in => RxSlide(i downto i), + rxpmaresetdone_out => RXPMARESETDONE(i downto i), + txpmaresetdone_out => TXPMARESETDONE(i downto i), + reset_tx_done_out => txresetdone(i downto i), + reset_rx_done_out => rxresetdone(i downto i), + reset_rx_cdr_stable_out => RxCdrLock_int(i downto i) + + ); + + + rxcdrlock(i) <= (not Channel_disable(i)) and RxCdrLock_int(i); + gtrx_reset_i(i) <= --GTRX_RESET(i) when RX_ALIGN_SW='1' else + gtrx_reset(i) or (auto_gth_rxrst(i) and rxcdrlock(i)); + + soft_reset_f(i) <= soft_reset(i/4) or cpll_reset(i);--or rst_hw; -- or GTRX_RESET(i); + + userclk_rx_reset_in(i) <=not RXPMARESETDONE(i); + userclk_tx_reset_in(i) <=not TXPMARESETDONE(i); + --RxResetDone_f(i) <= RxResetDone(i); + + end generate; + end generate; end Behavioral; diff --git a/sources/GBT/gbt_code/FELIX_gbt_wrapper_V7.vhd b/sources/GBT/gbt_code/FELIX_gbt_wrapper_V7.vhd index 8fe0b54d56fd7f8d239225ac3c0f6aaa2b786d8c..7816cc887bbaab597d62dae8cfb5fea36424778e 100644 --- a/sources/GBT/gbt_code/FELIX_gbt_wrapper_V7.vhd +++ b/sources/GBT/gbt_code/FELIX_gbt_wrapper_V7.vhd @@ -29,8 +29,8 @@ LIBRARY IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_ARITH.ALL;-- @suppress "Deprecated package" +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. @@ -43,7 +43,7 @@ use work.pcie_package.all; entity FELIX_gbt_wrapper is Generic ( CARD_TYPE : integer := 709; - STABLE_CLOCK_PERIOD : integer := 24; --period of the drp_clock + --STABLE_CLOCK_PERIOD : integer := 24; --period of the drp_clock GBT_NUM : integer := 24; OPTO_TRX : integer := 4; -- number of optical transceivers GTHREFCLK_SEL : std_logic; --GREFCLK : std_logic := '1'; @@ -81,7 +81,7 @@ entity FELIX_gbt_wrapper is GREFCLK_IN : in std_logic; clk40_in : in std_logic; - clk240_in : in std_logic; + --clk240_in : in std_logic; -- for CentralRouter TX_120b_in : in txrx120b_type(0 to (GBT_NUM-1)); RX_120b_out : out txrx120b_type(0 to (GBT_NUM-1)); @@ -108,7 +108,7 @@ entity FELIX_gbt_wrapper is end FELIX_gbt_wrapper; architecture Behavioral of FELIX_gbt_wrapper is - component fifo_GBT2CR IS + component fifo_GBT2CR IS -- @suppress "Component declaration is not equal to its matching entity" PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; @@ -125,22 +125,22 @@ architecture Behavioral of FELIX_gbt_wrapper is END component; -- constant QUAD_NUM : integer := GBT_NUM / 4; - signal rxslide_manual : std_logic_vector(23 downto 0); + --signal rxslide_manual : std_logic_vector(23 downto 0); signal RxSlide_c : std_logic_vector(23 downto 0); signal RxSlide_i : std_logic_vector(23 downto 0); - signal rxslide_sel : std_logic_vector(23 downto 0); - signal txusrrdy : std_logic_vector(23 downto 0); - signal rxusrrdy : std_logic_vector(23 downto 0); + --signal rxslide_sel : std_logic_vector(23 downto 0); + --signal txusrrdy : std_logic_vector(23 downto 0); + --signal rxusrrdy : std_logic_vector(23 downto 0); signal gttx_reset : std_logic_vector(23 downto 0); signal gtrx_reset : std_logic_vector(23 downto 0); - signal soft_reset : std_logic_vector(23 downto 0); + --signal soft_reset : std_logic_vector(23 downto 0); signal cpll_reset : std_logic_vector(23 downto 0); signal qpll_reset : std_logic_vector(11 downto 0); signal GT_TXUSRCLK : std_logic_vector(11 downto 0); signal txresetdone : std_logic_vector(23 downto 0); - signal clk_sampled : std_logic_vector(23 downto 0); + --signal clk_sampled : std_logic_vector(23 downto 0); signal rxresetdone : std_logic_vector(23 downto 0); signal txfsmresetdone : std_logic_vector(23 downto 0); @@ -151,32 +151,32 @@ architecture Behavioral of FELIX_gbt_wrapper is signal RxCdrLock_f : std_logic_vector(23 downto 0); signal qplllock : std_logic_vector(5 downto 0); - signal tx_is_data : std_logic_vector(23 downto 0); + --signal tx_is_data : std_logic_vector(23 downto 0); signal TX_RESET : std_logic_vector(23 downto 0); signal TX_RESET_i : std_logic_vector(23 downto 0); signal RX_RESET : std_logic_vector(23 downto 0); signal RX_RESET_i : std_logic_vector(23 downto 0); - signal gbt_data_format : std_logic_vector(47 downto 0); + --signal gbt_data_format : std_logic_vector(47 downto 0); - SIGNAL CXP1_TX_PLL_LOCKEd : STD_LOGIC; - signal CXP2_TX_PLL_LOCKED : STD_LOGIC; - signal cpu_rst : STD_LOGIC; - signal RX_ALIGN_SW : STD_LOGIC; - signal RX_ALIGN_TB_SW : STD_logic; + --SIGNAL CXP1_TX_PLL_LOCKEd : STD_LOGIC; + --signal CXP2_TX_PLL_LOCKED : STD_LOGIC; + --signal cpu_rst : STD_LOGIC; + --signal RX_ALIGN_SW : STD_LOGIC; + --signal RX_ALIGN_TB_SW : STD_logic; - signal rx_pll_locked : std_logic_vector(23 downto 0); + --signal rx_pll_locked : std_logic_vector(23 downto 0); signal outsel_i : std_logic_vector(23 downto 0); signal outsel_ii : std_logic_vector(23 downto 0); signal outsel_o : std_logic_vector(23 downto 0); signal rx_is_header : std_logic_vector(23 downto 0); signal alignment_done : std_logic_vector(23 downto 0); - signal rx_is_data : std_logic_vector(23 downto 0); + --signal rx_is_data : std_logic_vector(23 downto 0); signal RX_HEADER_FOUND : std_logic_vector(23 downto 0); - signal cxp1_rx_bitslip_nbr : std_logic_vector(71 downto 0); - signal cxp2_rx_bitslip_nbr : std_logic_vector(71 downto 0); + --signal cxp1_rx_bitslip_nbr : std_logic_vector(71 downto 0); + --signal cxp2_rx_bitslip_nbr : std_logic_vector(71 downto 0); signal RxSlide : std_logic_vector(23 downto 0); @@ -193,46 +193,46 @@ architecture Behavioral of FELIX_gbt_wrapper is signal alignment_chk_rst_c1 : std_logic_vector(23 downto 0); signal alignment_chk_rst : std_logic_vector(23 downto 0); - signal rstframeclk : STD_LOGIC; + --signal rstframeclk : STD_LOGIC; signal alignment_chk_rst_i : STD_LOGIC; - signal rstframeclk1 : STD_LOGIC; - signal rx_frame_phase_ok_cxp1 : STD_LOGIC; - signal rx_frame_phase_ok_cxp2 : std_logic; - - signal CXP2_GTH_REF_CLK_BUF : std_logic; - signal CXP1_GTH_REF_CLK : std_logic; - signal CXP2_GTH_REF_CLK : std_logic; - signal CXP1_GTH_REF_CLK_BUF : std_logic; + --signal rstframeclk1 : STD_LOGIC; + --signal rx_frame_phase_ok_cxp1 : STD_LOGIC; + --signal rx_frame_phase_ok_cxp2 : std_logic; + + --signal CXP2_GTH_REF_CLK_BUF : std_logic; + --signal CXP1_GTH_REF_CLK : std_logic; + --signal CXP2_GTH_REF_CLK : std_logic; + --signal CXP1_GTH_REF_CLK_BUF : std_logic; signal DESMUX_USE_SW : std_logic; - signal counterbig : std_logic_vector(26 downto 0); - signal counterbig1 : std_logic_vector(26 downto 0); - - signal rstframeclk_3r : std_logic; - signal rstframeclk_r : std_logic; - signal rstframeclk_2r : std_logic; - signal rstframeclk1_3r : std_logic; - signal rstframeclk1_r : std_logic; - signal rstframeclk1_2r : std_logic; - signal cxp1_tx_pll_rst : std_logic; - signal cxp2_tx_pll_rst : std_logic; + --signal counterbig : std_logic_vector(26 downto 0); + --signal counterbig1 : std_logic_vector(26 downto 0); + + --signal rstframeclk_3r : std_logic; + --signal rstframeclk_r : std_logic; + --signal rstframeclk_2r : std_logic; + --signal rstframeclk1_3r : std_logic; + --signal rstframeclk1_r : std_logic; + --signal rstframeclk1_2r : std_logic; + --signal cxp1_tx_pll_rst : std_logic; + --signal cxp2_tx_pll_rst : std_logic; signal SOFT_TXRST_GT : std_logic_vector(23 downto 0); - signal TopBot : std_logic_vector(23 downto 0); - signal TopBot_C : std_logic_vector(23 downto 0); - signal TopBot_i : std_logic_vector(23 downto 0); + --signal TopBot : std_logic_vector(23 downto 0); + --signal TopBot_C : std_logic_vector(23 downto 0); + --signal TopBot_i : std_logic_vector(23 downto 0); signal SOFT_RXRST_GT : std_logic_vector(23 downto 0); signal SOFT_TXRST_ALL : std_logic_vector(11 downto 0); signal SOFT_RXRST_ALL : std_logic_vector(11 downto 0); - signal TX_OPT : std_logic_vector(95 downto 0); - signal RX_OPT : std_logic_vector(95 downto 0); + --signal TX_OPT : std_logic_vector(95 downto 0); + --signal RX_OPT : std_logic_vector(95 downto 0); SIGNAL DATA_TXFORMAT : std_logic_vector(95 downto 0); signal DATA_TXFORMAT_i : std_logic_vector(95 downto 0); SIGNAL DATA_RXFORMAT : std_logic_vector(95 downto 0); signal DATA_RXFORMAT_i : std_logic_vector(95 downto 0); - SIGNAL OddEven : std_logic_vector(23 downto 0); - signal OddEven_i : std_logic_vector(23 downto 0); - signal OddEven_c : std_logic_vector(23 downto 0); - signal ext_trig_realign : std_logic_vector(23 downto 0); + --SIGNAL OddEven : std_logic_vector(23 downto 0); + --signal OddEven_i : std_logic_vector(23 downto 0); + --signal OddEven_c : std_logic_vector(23 downto 0); + --signal ext_trig_realign : std_logic_vector(23 downto 0); @@ -240,100 +240,100 @@ architecture Behavioral of FELIX_gbt_wrapper is signal fifo_empty : std_logic_vector(63 downto 0); - signal GBT_RXSLIDE : std_logic_vector(63 downto 0); - signal GBT_TXUSRRDY : std_logic_vector(63 downto 0); - signal GBT_RXUSRRDY : std_logic_vector(63 downto 0); - signal GBT_GTTX_RESET : std_logic_vector(63 downto 0); - signal GBT_GTRX_RESET : std_logic_vector(63 downto 0); - signal GBT_PLL_RESET : std_logic_vector(63 downto 0); - signal GBT_SOFT_TX_RESET : std_logic_vector(63 downto 0); - signal GBT_SOFT_RX_RESET : std_logic_vector(63 downto 0); - signal GBT_ODDEVEN : std_logic_vector(63 downto 0); - signal GBT_TOPBOT : std_logic_vector(63 downto 0); + --signal GBT_RXSLIDE : std_logic_vector(63 downto 0); + --signal GBT_TXUSRRDY : std_logic_vector(63 downto 0); + --signal GBT_RXUSRRDY : std_logic_vector(63 downto 0); + --signal GBT_GTTX_RESET : std_logic_vector(63 downto 0); + --signal GBT_GTRX_RESET : std_logic_vector(63 downto 0); + --signal GBT_PLL_RESET : std_logic_vector(63 downto 0); + --signal GBT_SOFT_TX_RESET : std_logic_vector(63 downto 0); + --signal GBT_SOFT_RX_RESET : std_logic_vector(63 downto 0); + --signal GBT_ODDEVEN : std_logic_vector(63 downto 0); + --signal GBT_TOPBOT : std_logic_vector(63 downto 0); --signal GBT_TX_TC_DLY_VALUE1 : std_logic_vector(63 downto 0); -- signal GBT_TX_TC_DLY_VALUE2 : std_logic_vector(63 downto 0); - signal GBT_TX_OPT : std_logic_vector(63 downto 0); - signal GBT_RX_OPT : std_logic_vector(63 downto 0); - signal GBT_DATA_TXFORMAT : std_logic_vector(63 downto 0); - signal GBT_DATA_RXFORMAT : std_logic_vector(63 downto 0); - signal GBT_TX_RESET : std_logic_vector(63 downto 0); - signal GBT_RX_RESET : std_logic_vector(63 downto 0); - signal GBT_TX_TC_METHOD : std_logic_vector(63 downto 0); - signal GBT_TC_EDGE : std_logic_vector(63 downto 0); - signal GBT_OUTMUX_SEL : std_logic_vector(63 downto 0); - - SIGNAL GBT_TXRESET_DONE : std_logic_vector(63 downto 0); - SIGNAL GBT_RXRESET_DONE : std_logic_vector(63 downto 0); - signal TXPMARESETDONE : std_logic_vector(63 downto 0); - signal RXPMARESETDONE : std_logic_vector(63 downto 0); + --signal GBT_TX_OPT : std_logic_vector(63 downto 0); + --signal GBT_RX_OPT : std_logic_vector(63 downto 0); + --signal GBT_DATA_TXFORMAT : std_logic_vector(63 downto 0); + --signal GBT_DATA_RXFORMAT : std_logic_vector(63 downto 0); + --signal GBT_TX_RESET : std_logic_vector(63 downto 0); + --signal GBT_RX_RESET : std_logic_vector(63 downto 0); + --signal GBT_TX_TC_METHOD : std_logic_vector(63 downto 0); + --signal GBT_TC_EDGE : std_logic_vector(63 downto 0); + --signal GBT_OUTMUX_SEL : std_logic_vector(63 downto 0); + + --SIGNAL GBT_TXRESET_DONE : std_logic_vector(63 downto 0); + --SIGNAL GBT_RXRESET_DONE : std_logic_vector(63 downto 0); + --signal TXPMARESETDONE : std_logic_vector(63 downto 0); + --signal RXPMARESETDONE : std_logic_vector(63 downto 0); signal alignment_done_f : std_logic_vector(63 downto 0); - signal soft_reset_f : std_logic_vector(63 downto 0); - signal userclk_rx_reset_in : std_logic_vector(63 downto 0); - signal userclk_tx_reset_in : std_logic_vector(63 downto 0); - signal TXPMARESETDONE_out : std_logic_vector(63 downto 0); - signal RXPMARESETDONE_out : std_logic_vector(63 downto 0); + --signal soft_reset_f : std_logic_vector(63 downto 0); + --signal userclk_rx_reset_in : std_logic_vector(63 downto 0); + --signal userclk_tx_reset_in : std_logic_vector(63 downto 0); + --signal TXPMARESETDONE_out : std_logic_vector(63 downto 0); + --signal RXPMARESETDONE_out : std_logic_vector(63 downto 0); signal GT_RXUSRCLK : std_logic; - SIGNAL GBT_TXFSMRESET_DONE : std_logic_vector(63 downto 0); - SIGNAL GBT_RXFSMRESET_DONE : std_logic_vector(63 downto 0); - SIGNAL GBT_CPLL_FBCLK_LOST : std_logic_vector(63 downto 0); - SIGNAL GBT_PLL_LOCK : std_logic_vector(63 downto 0); - SIGNAL GBT_RXCDR_LOCK : std_logic_vector(63 downto 0); - SIGNAL GBT_CLK_SAMPLED : std_logic_vector(63 downto 0); - SIGNAL GBT_RX_IS_HEADER : std_logic_vector(63 downto 0); - SIGNAL GBT_RX_IS_DATA : std_logic_vector(63 downto 0); - SIGNAL GBT_RX_HEADER_FOUND : std_logic_vector(63 downto 0); - SIGNAL GBT_ALIGNMENT_DONE : std_logic_vector(63 downto 0); - SIGNAL GBT_OUT_MUX_STATUS : std_logic_vector(63 downto 0); - SIGNAL GBT_ERROR : std_logic_vector(63 downto 0); - SIGNAL GBT_GBT_TOPBOT_C : std_logic_vector(63 downto 0); + --SIGNAL GBT_TXFSMRESET_DONE : std_logic_vector(63 downto 0); + --SIGNAL GBT_RXFSMRESET_DONE : std_logic_vector(63 downto 0); + --SIGNAL GBT_CPLL_FBCLK_LOST : std_logic_vector(63 downto 0); + --SIGNAL GBT_PLL_LOCK : std_logic_vector(63 downto 0); + --SIGNAL GBT_RXCDR_LOCK : std_logic_vector(63 downto 0); + --SIGNAL GBT_CLK_SAMPLED : std_logic_vector(63 downto 0); + --SIGNAL GBT_RX_IS_HEADER : std_logic_vector(63 downto 0); + --SIGNAL GBT_RX_IS_DATA : std_logic_vector(63 downto 0); + --SIGNAL GBT_RX_HEADER_FOUND : std_logic_vector(63 downto 0); + --SIGNAL GBT_ALIGNMENT_DONE : std_logic_vector(63 downto 0); + --SIGNAL GBT_OUT_MUX_STATUS : std_logic_vector(63 downto 0); + --SIGNAL GBT_ERROR : std_logic_vector(63 downto 0); + --SIGNAL GBT_GBT_TOPBOT_C : std_logic_vector(63 downto 0); - type txrx4b_24ch_type is array (23 downto 0) of std_logic_vector(3 downto 0); + --type txrx4b_24ch_type is array (23 downto 0) of std_logic_vector(3 downto 0); signal RX_120b_out_i : txrx120b_type(0 to (GBT_NUM-1)); signal RX_120b_out_ii : txrx120b_type(0 to (GBT_NUM-1)); - signal RxWordCnt_out : txrx4b_24ch_type; + --signal RxWordCnt_out : txrx4b_24ch_type; - SIGNAL LOGIC_RST : std_logic_vector(63 downto 0); - signal Mode_ctrl : std_logic_vector(63 downto 0); + --SIGNAL LOGIC_RST : std_logic_vector(63 downto 0); + --signal Mode_ctrl : std_logic_vector(63 downto 0); SIGNAL TX_TC_DLY_VALUE : std_logic_vector(191 downto 0); - signal data_sel : std_logic_vector(95 downto 0); + --signal data_sel : std_logic_vector(95 downto 0); signal GTH_RefClk : std_logic_vector(23 downto 0); signal RX_FLAG_Oi : std_logic_vector(23 downto 0); - signal lock_lg : std_logic_vector(23 downto 0); + --signal lock_lg : std_logic_vector(23 downto 0); signal pulse_cnt : std_logic_vector(29 downto 0); signal pulse_lg : std_logic; signal CXP1_GTH_RefClk : std_logic; signal CXP2_GTH_RefClk : std_logic; - signal des_rxusrclk_cxp1 : std_logic; - signal des_rxusrclk_cxp2 : std_logic; + --signal des_rxusrclk_cxp1 : std_logic; + --signal des_rxusrclk_cxp2 : std_logic; - signal clksampled : std_logic_vector(23 downto 0); - signal des_rxusrclk : std_logic_vector(23 downto 0); + --signal clksampled : std_logic_vector(23 downto 0); + --signal des_rxusrclk : std_logic_vector(23 downto 0); signal error_orig : std_logic_vector(23 downto 0); signal FSM_RST : std_logic_vector(23 downto 0); signal auto_gth_rxrst : std_logic_vector(23 downto 0); signal auto_gbt_rxrst : std_logic_vector(23 downto 0); - signal gbt_rx_reset_i : std_logic_vector(23 downto 0); + --signal gbt_rx_reset_i : std_logic_vector(23 downto 0); signal gtrx_reset_i : std_logic_vector(23 downto 0); - signal gbt_sel : std_logic_vector(23 downto 0); + --signal gbt_sel : std_logic_vector(23 downto 0); - signal TX_LINERATE : std_logic_vector(23 downto 0); - signal RX_LINERATE : std_logic_vector(23 downto 0); + --signal TX_LINERATE : std_logic_vector(23 downto 0); + --signal RX_LINERATE : std_logic_vector(23 downto 0); signal GT_RXOUTCLK : std_logic_vector(23 downto 0); signal GT_TXOUTCLK : std_logic_vector(23 downto 0); signal BITSLIP_MANUAL_r : std_logic_vector(23 downto 0); signal BITSLIP_MANUAL_2r : std_logic_vector(23 downto 0); signal error_f : std_logic_vector(23 downto 0); - signal BITSLIP_MANUAL_3r : std_logic_vector(23 downto 0); + --signal BITSLIP_MANUAL_3r : std_logic_vector(23 downto 0); signal alignment_done_chk_cnt : std_logic_vector(12 downto 0); signal alignment_done_a : std_logic_vector(47 downto 0); @@ -353,6 +353,11 @@ begin REFCLK_CXP2 <= CXP2_GTH_RefClk; ibufds_instq2_clk0 : IBUFDS_GTE2 + generic map( + CLKCM_CFG => true, + CLKRCV_TRST => true, + CLKSWING_CFG => "11" + ) port map ( O => CXP1_GTH_RefClk, @@ -375,6 +380,11 @@ begin GTH_RefClk(11) <= CXP1_GTH_RefClk; --IBUFDS_GTE2 ibufds_instq8_clk0 : IBUFDS_GTE2 + generic map( + CLKCM_CFG => true, + CLKRCV_TRST => true, + CLKSWING_CFG => "11" + ) port map ( O => CXP2_GTH_RefClk, @@ -429,29 +439,29 @@ begin -- -- - LOGIC_RST(47 downto 0) <= register_map_control.GBT_CHANNEL_DISABLE; + --LOGIC_RST(47 downto 0) <= register_map_control.GBT_CHANNEL_DISABLE; General_ctrl <= register_map_control.GBT_GENERAL_CTRL; - RxSlide_Manual(23 downto 0) <= register_map_control.GBT_RXSLIDE_MANUAL(23 downto 0); - RxSlide_Sel(23 downto 0) <= register_map_control.GBT_RXSLIDE_SELECT(23 downto 0); - TxUsrRdy(23 downto 0) <= register_map_control.GBT_TXUSRRDY(23 downto 0); - RxUsrRdy(23 downto 0) <= register_map_control.GBT_RXUSRRDY(23 downto 0); - GTTX_RESET(23 downto 0) <= register_map_control.GBT_GTTX_RESET(23 downto 0); - GTRX_RESET(23 downto 0) <= register_map_control.GBT_GTRX_RESET(23 downto 0); + --rxslide_manual(23 downto 0) <= register_map_control.GBT_RXSLIDE_MANUAL(23 downto 0); + --rxslide_sel(23 downto 0) <= register_map_control.GBT_RXSLIDE_SELECT(23 downto 0); + --txusrrdy(23 downto 0) <= register_map_control.GBT_TXUSRRDY(23 downto 0); + --rxusrrdy(23 downto 0) <= register_map_control.GBT_RXUSRRDY(23 downto 0); + gttx_reset(23 downto 0) <= register_map_control.GBT_GTTX_RESET(23 downto 0); + gtrx_reset(23 downto 0) <= register_map_control.GBT_GTRX_RESET(23 downto 0); - SOFT_RESET(23 downto 0) <= register_map_control.GBT_SOFT_RESET(23 downto 0); - CPLL_RESET(23 downto 0) <= register_map_control.GBT_PLL_RESET.CPLL_RESET(23 downto 0); - QPLL_RESET(11 downto 0) <= register_map_control.GBT_PLL_RESET.QPLL_RESET(59 downto 48); + --soft_reset(23 downto 0) <= register_map_control.GBT_SOFT_RESET(23 downto 0); + cpll_reset(23 downto 0) <= register_map_control.GBT_PLL_RESET.CPLL_RESET(23 downto 0); + qpll_reset(11 downto 0) <= register_map_control.GBT_PLL_RESET.QPLL_RESET(59 downto 48); SOFT_TXRST_GT(23 downto 0) <= register_map_control.GBT_SOFT_TX_RESET.RESET_GT(23 downto 0); -- Default: 0b000 SOFT_RXRST_GT(23 downto 0) <= register_map_control.GBT_SOFT_RX_RESET.RESET_GT(23 downto 0); -- Default: 0b000 SOFT_TXRST_ALL(11 downto 0) <= register_map_control.GBT_SOFT_TX_RESET.RESET_ALL(59 downto 48); SOFT_RXRST_ALL(11 downto 0) <= register_map_control.GBT_SOFT_RX_RESET.RESET_ALL(59 downto 48); - OddEven(23 downto 0) <= register_map_control.GBT_ODD_EVEN(23 downto 0); - TopBot(23 downto 0) <= register_map_control.GBT_TOPBOT(23 downto 0); + --OddEven(23 downto 0) <= register_map_control.GBT_ODD_EVEN(23 downto 0); + --TopBot(23 downto 0) <= register_map_control.GBT_TOPBOT(23 downto 0); TX_TC_DLY_VALUE(47 downto 0) <= register_map_control.GBT_TX_TC_DLY_VALUE1; TX_TC_DLY_VALUE(95 downto 48) <=register_map_control.GBT_TX_TC_DLY_VALUE2; @@ -485,18 +495,18 @@ begin -- -- - register_map_link_monitor.GBT_TXRESET_DONE(23 downto 0) <= TxResetDone(23 downto 0); - register_map_link_monitor.GBT_RXRESET_DONE(23 downto 0) <= RxResetDone(23 downto 0); - register_map_link_monitor.GBT_TXFSMRESET_DONE(23 downto 0) <= txpmaresetdone(23 downto 0); - register_map_link_monitor.GBT_RXFSMRESET_DONE(23 downto 0) <= rxpmaresetdone(23 downto 0); - register_map_link_monitor.GBT_CPLL_FBCLK_LOST(23 downto 0) <= CpllFbClkLost (23 downto 0); - register_map_link_monitor.GBT_PLL_LOCK.CPLL_LOCK(23 downto 0) <= CpllLock(23 downto 0); - register_map_link_monitor.GBT_PLL_LOCK.QPLL_LOCK(53 downto 48) <= QpllLock(5 downto 0); - register_map_link_monitor.GBT_RXCDR_LOCK(23 downto 0) <= RxCdrLock(23 downto 0); - register_map_link_monitor.GBT_CLK_SAMPLED(23 downto 0) <= clk_sampled(23 downto 0); - - register_map_link_monitor.GBT_RX_IS_HEADER(23 downto 0) <= RX_IS_HEADER(23 downto 0); - register_map_link_monitor.GBT_RX_IS_DATA(23 downto 0) <= RX_IS_DATA(23 downto 0); + register_map_link_monitor.GBT_TXRESET_DONE(23 downto 0) <= txresetdone(23 downto 0); + register_map_link_monitor.GBT_RXRESET_DONE(23 downto 0) <= rxresetdone(23 downto 0); + register_map_link_monitor.GBT_TXFSMRESET_DONE(23 downto 0) <= (others => '0'); --TXPMARESETDONE(23 downto 0); + register_map_link_monitor.GBT_RXFSMRESET_DONE(23 downto 0) <= (others => '0'); --RXPMARESETDONE(23 downto 0); + register_map_link_monitor.GBT_CPLL_FBCLK_LOST(23 downto 0) <= cpllfbclklost (23 downto 0); + register_map_link_monitor.GBT_PLL_LOCK.CPLL_LOCK(23 downto 0) <= cplllock(23 downto 0); + register_map_link_monitor.GBT_PLL_LOCK.QPLL_LOCK(53 downto 48) <= qplllock(5 downto 0); + register_map_link_monitor.GBT_RXCDR_LOCK(23 downto 0) <= rxcdrlock(23 downto 0); + register_map_link_monitor.GBT_CLK_SAMPLED(23 downto 0) <= (others => '0'); --clk_sampled(23 downto 0); + + register_map_link_monitor.GBT_RX_IS_HEADER(23 downto 0) <= rx_is_header(23 downto 0); + register_map_link_monitor.GBT_RX_IS_DATA(23 downto 0) <= (others => '0'); --rx_is_data(23 downto 0); register_map_link_monitor.GBT_RX_HEADER_FOUND(23 downto 0) <= RX_HEADER_FOUND(23 downto 0); register_map_link_monitor.GBT_ALIGNMENT_DONE(23 downto 0) <= alignment_done_f(23 downto 0); @@ -513,7 +523,7 @@ begin error_f(i) <= error_orig(i) and alignment_done_f(i); end generate; - register_map_link_monitor.GBT_GBT_TOPBOT_C(23 downto 0) <= TopBot_c(23 downto 0); + register_map_link_monitor.GBT_GBT_TOPBOT_C(23 downto 0) <= (others => '0'); --TopBot_C(23 downto 0); ---------------------------------------- @@ -523,8 +533,8 @@ begin DESMUX_USE_SW <= register_map_control.GBT_MODE_CTRL.DESMUX_USE_SW(0); --Mode_ctrl(0); - RX_ALIGN_SW <= register_map_control.GBT_MODE_CTRL.RX_ALIGN_SW(1); --Mode_ctrl(1); - RX_ALIGN_TB_SW <= register_map_control.GBT_MODE_CTRL.RX_ALIGN_TB_SW(2); --Mode_ctrl(2); + --RX_ALIGN_SW <= register_map_control.GBT_MODE_CTRL.RX_ALIGN_SW(1); --Mode_ctrl(1); + --RX_ALIGN_TB_SW <= register_map_control.GBT_MODE_CTRL.RX_ALIGN_TB_SW(2); --Mode_ctrl(2); @@ -593,17 +603,17 @@ begin end process; RXCDRGEN: if CARD_TYPE = 709 generate - RxCdrLock_f(0) <= RxCdrLock(0) and (not opto_los(0)) when register_map_control.GTH_LOOPBACK_CONTROL="000" - else RxCdrLock(0); - RxCdrLock_f(1) <= RxCdrLock(1) and (not opto_los(1)) when register_map_control.GTH_LOOPBACK_CONTROL="000" - else RxCdrLock(1); - RxCdrLock_f(2) <= RxCdrLock(2) and (not opto_los(2)) when register_map_control.GTH_LOOPBACK_CONTROL="000" - else RxCdrLock(2); - RxCdrLock_f(3) <= RxCdrLock(3) and (not opto_los(3)) when register_map_control.GTH_LOOPBACK_CONTROL="000" - else RxCdrLock(3); + RxCdrLock_f(0) <= rxcdrlock(0) and (not opto_los(0)) when register_map_control.GTH_LOOPBACK_CONTROL="000" + else rxcdrlock(0); + RxCdrLock_f(1) <= rxcdrlock(1) and (not opto_los(1)) when register_map_control.GTH_LOOPBACK_CONTROL="000" + else rxcdrlock(1); + RxCdrLock_f(2) <= rxcdrlock(2) and (not opto_los(2)) when register_map_control.GTH_LOOPBACK_CONTROL="000" + else rxcdrlock(2); + RxCdrLock_f(3) <= rxcdrlock(3) and (not opto_los(3)) when register_map_control.GTH_LOOPBACK_CONTROL="000" + else rxcdrlock(3); end generate; RXCDRGEN1: if CARD_TYPE = 710 generate - RxCdrLock_f <= RxCdrLock; + RxCdrLock_f <= rxcdrlock; end generate; RX_120b_out(i) <= RX_120b_out_ii(i) when alignment_done_f(i)='1' else @@ -612,39 +622,36 @@ begin auto_rxrst : entity work.FELIX_GBT_RX_AUTO_RST port map ( - FSM_CLK => clk40_in, - pulse_lg => pulse_lg, - GTHRXRESET_DONE => RxResetDone(i) and RxFsmResetDone(i), - alignment_chk_rst => alignment_chk_rst_c1(i), - GBT_LOCK => alignment_done_f(i),--alignment_done(i), - AUTO_GTH_RXRST => auto_gth_rxrst(i), - ext_trig_realign => ext_trig_realign(i), - AUTO_GBT_RXRST => auto_gbt_rxrst(i) + ext_trig_realign => open, --ext_trig_realign(i), + FSM_CLK => clk40_in, + GBT_LOCK => alignment_done_f(i), --alignment_done(i), + pulse_lg => pulse_lg, + GTHRXRESET_DONE => rxresetdone(i) and rxfsmresetdone(i), + AUTO_GTH_RXRST => auto_gth_rxrst(i), + alignment_chk_rst => alignment_chk_rst_c1(i), + AUTO_GBT_RXRST => auto_gbt_rxrst(i) ); rafsm : entity work.FELIX_GBT_RXSLIDE_FSM port map ( - ext_trig_realign => ext_trig_realign(i), - - FSM_RST => FSM_RST(i), - FSM_CLK => clk40_in, - - GBT_LOCK => alignment_done(i), - RxSlide => RxSlide_c(i), - - alignment_chk_rst => alignment_chk_rst_c(i) + alignment_chk_rst => alignment_chk_rst_c(i), + --ext_trig_realign => ext_trig_realign(i), + FSM_RST => FSM_RST(i), + FSM_CLK => clk40_in, + GBT_LOCK => alignment_done(i), + RxSlide => RxSlide_c(i) ); FSM_RST(i) <= RX_RESET(i);-- or RX_ALIGN_SW; - GTRX_RESET_i(i) <= --GTRX_RESET(i) when RX_ALIGN_SW='1' else - (GTRX_RESET(i) or auto_gth_rxrst(i)); + gtrx_reset_i(i) <= --GTRX_RESET(i) when RX_ALIGN_SW='1' else + (gtrx_reset(i) or auto_gth_rxrst(i)); RX_RESET_i(i) <= --RX_RESET(i) when RX_ALIGN_SW='1' else (RX_RESET(i) or auto_gbt_rxrst(i)); alignment_chk_rst(i) <= --alignment_chk_rst_i when RX_ALIGN_SW='1' else (alignment_chk_rst_i or alignment_chk_rst_c(i) or alignment_chk_rst_c1(i)); - TX_RESET_i(i) <= TX_RESET(i) or (not TxResetDone(i)) or (not TxFsmResetDone(i));-- for V7 + TX_RESET_i(i) <= TX_RESET(i) or (not txresetdone(i)) or (not txfsmresetdone(i));-- for V7 RxSlide_i(i) <= RxCdrLock_f(i) and RxSlide_c(i); end generate; @@ -672,7 +679,7 @@ gbtRxTx : for i in GBT_NUM-1 downto 0 generate if GT_RX_WORD_CLK(i)'event and GT_RX_WORD_CLK(i)='1' then BITSLIP_MANUAL_r(i) <= RxSlide_i(i); BITSLIP_MANUAL_2r(i) <= BITSLIP_MANUAL_r(i); - BITSLIP_MANUAL_3r(i) <= BITSLIP_MANUAL_2r(i); + --BITSLIP_MANUAL_3r(i) <= BITSLIP_MANUAL_2r(i); RxSlide(i) <= BITSLIP_MANUAL_r(i) and (not BITSLIP_MANUAL_2r(i)); end if; end process; @@ -685,50 +692,43 @@ gbtRxTx : for i in GBT_NUM-1 downto 0 generate port map ( - error_o => error_orig(i), - RX_FLAG => RX_FLAG_Oi(i), - TX_FLAG => TX_FLAG_O(i), - - Tx_DATA_FORMAT => DATA_TXFORMAT_i(2*i+1 downto 2*i), - Rx_DATA_FORMAT => DATA_RXFORMAT_i(2*i+1 downto 2*i), - - Tx_latopt_tc => '1',--TX_OPT(i), - Tx_latopt_scr => '1',--TX_OPT(24+i), - RX_LATOPT_DES => '1',--RX_OPT(i), - - TX_TC_METHOD => TX_TC_METHOD(i), - TC_EDGE => TC_EDGE(i), - TX_TC_DLY_VALUE => TX_TC_DLY_VALUE(4*i+2 downto 4*i), - - alignment_chk_rst => alignment_chk_rst(i), - alignment_done_O => alignment_done(i), - L40M => clk40_in, - outsel_i => outsel_ii(i), - outsel_o => outsel_o(i), - - --BITSLIP_MANUAL => RxSlide_i(i), - --BITSLIP_SEL => RxSlide_Sel(i), - --GT_RXSLIDE => RxSlide(i), - OddEven => '0',--OddEven_i(i), - TopBot => '0',--TopBot_i(i), - data_sel => data_sel(4*i+3 downto 4*i), - - TX_RESET_I => TX_RESET_i(i), - TX_FRAMECLK_I => TX_FRAME_CLK_I(i), - TX_WORDCLK_I => GT_TX_WORD_CLK(i), - -- TX_ISDATA_SEL_I => TX_IS_DATA(i), - TX_DATA_120b_I => TX_120b_in(i), - TX_DATA_20b_O => TX_DATA_20b(i), - - RX_RESET_I => RX_RESET_i(i), - RX_FRAME_CLK_O => open,--RX_FRAME_CLK_O(i), - RX_WORD_IS_HEADER_O => RX_IS_HEADER(i), - RX_HEADER_FOUND => RX_HEADER_FOUND(i), - RX_ISDATA_FLAG_O => RX_IS_DATA(i), - RX_DATA_20b_I => RX_DATA_20b(i), - RX_DATA_120b_O => RX_120b_out_i(i), - des_rxusrclk => GT_RX_WORD_CLK(i), - RX_WORDCLK_I => GT_RX_WORD_CLK(i) + alignment_chk_rst => alignment_chk_rst(i), + alignment_done_O => alignment_done(i), + outsel_i => outsel_ii(i), + outsel_o => outsel_o(i), + error_o => error_orig(i), + TX_TC_DLY_VALUE => TX_TC_DLY_VALUE(4*i+2 downto 4*i), + TX_TC_METHOD => TX_TC_METHOD(i), + TC_EDGE => TC_EDGE(i), + --BITSLIP_MANUAL => RxSlide_i(i), + --BITSLIP_SEL => RxSlide_Sel(i), + --GT_RXSLIDE => RxSlide(i), + --OddEven => '0', --OddEven_i(i), + --TopBot => '0', --TopBot_i(i), + --data_sel => "0000", -- FS: never written. data_sel(4*i+3 downto 4*i), + RX_FLAG => RX_FLAG_Oi(i), + TX_FLAG => TX_FLAG_O(i), + --Tx_latopt_scr => '1', --TX_OPT(24+i), + --Tx_latopt_tc => '1', --TX_OPT(i), + RX_LATOPT_DES => '1', --RX_OPT(i), + Tx_DATA_FORMAT => DATA_TXFORMAT_i(2*i+1 downto 2*i), + Rx_Data_Format => DATA_RXFORMAT_i(2*i+1 downto 2*i), + RX_RESET_I => RX_RESET_i(i), + RX_FRAME_CLK_O => open, --RX_FRAME_CLK_O(i), + RX_HEADER_FOUND => RX_HEADER_FOUND(i), + RX_WORD_IS_HEADER_O => rx_is_header(i), + RX_WORDCLK_I => GT_RX_WORD_CLK(i), + --RX_ISDATA_FLAG_O => rx_is_data(i), + L40M => clk40_in, + RX_DATA_20b_I => RX_DATA_20b(i), + RX_DATA_120b_O => RX_120b_out_i(i), + TX_RESET_I => TX_RESET_i(i), + TX_FRAMECLK_I => TX_FRAME_CLK_I(i), + des_rxusrclk => GT_RX_WORD_CLK(i), + TX_WORDCLK_I => GT_TX_WORD_CLK(i), + -- TX_ISDATA_SEL_I => TX_IS_DATA(i), + TX_DATA_120b_I => TX_120b_in(i), + TX_DATA_20b_O => TX_DATA_20b(i) ); @@ -755,8 +755,8 @@ clk_generate : for i in (GBT_NUM-1)/4 downto 0 generate GTTXOUTCLK_BUFG: BUFG port map ( - I => GT_TXOUTCLK(4*i), - O => GT_TXUSRCLK(i) + O => GT_TXUSRCLK(i), + I => GT_TXOUTCLK(4*i) ); GT_TX_WORD_CLK(4*i+0) <= GT_TXUSRCLK(i); @@ -772,8 +772,8 @@ end generate; RXCLK_GEN: if CARD_TYPE = 710 or CARD_TYPE = 709 generate GTRXOUTCLK_BUFG: BUFG port map( - I => GT_RXOUTCLK(0), - O => GT_RXUSRCLK + O => GT_RXUSRCLK, + I => GT_RXOUTCLK(0) ); end generate; @@ -787,18 +787,18 @@ RXCLK_GEN_709: if CARD_TYPE = 709 generate GT_RX_WORD_CLK(0) <= GT_RXUSRCLK; GTRXOUTCLK2_BUFG: BUFG port map( - I => GT_RXOUTCLK(1), - O => GT_RX_WORD_CLK(1) + O => GT_RX_WORD_CLK(1), + I => GT_RXOUTCLK(1) ); GTRXOUTCLK3_BUFG: BUFG port map( - I => GT_RXOUTCLK(2), - O => GT_RX_WORD_CLK(2) + O => GT_RX_WORD_CLK(2), + I => GT_RXOUTCLK(2) ); GTRXOUTCLK4_BUFG: BUFG port map( - I => GT_RXOUTCLK(3), - O => GT_RX_WORD_CLK(3) + O => GT_RX_WORD_CLK(3), + I => GT_RXOUTCLK(3) ); end generate; @@ -814,79 +814,39 @@ CPLL_GEN: if PLL_SEL = CPLL generate GTH_TOP_INST:entity work.GTH_CPLL_Wrapper_V7 port map ( - GTH_RefClk => GTH_RefClk(i),--local_rx_240m_in,--gtrefclk0_in, - DRP_CLK_IN => DRP_CLK_IN, - - - + GTH_RefClk => GTH_RefClk(i), --local_rx_240m_in,--gtrefclk0_in, + DRP_CLK_IN => DRP_CLK_IN, + gt0_loopback_in => register_map_control.GTH_LOOPBACK_CONTROL, + gt0_rxcdrhold_in => '0', --- RX clock, for each channel - gt0_rxusrclk_in => GT_RX_WORD_CLK(i),--(i) - gt0_rxoutclk_out => GT_RXOUTCLK(i), - gt0_txusrclk_in => GT_TX_WORD_CLK(i), - gt0_txoutclk_out => GT_TXOUTCLK(i), - - - ----------------------------------------- - ---- STATUS signals - ----------------------------------------- - - gt0_txresetdone_out => TxResetDone(i),--: out std_logic_vector(3 downto 0); - gt0_rxresetdone_out => RxResetDone(i),--: out std_logic_vector(3 downto 0); - - gt0_tx_fsm_reset_done_out => TxFsmResetDone(i),--: out std_logic_vector(3 downto 0); - gt0_rx_fsm_reset_done_out => RxFsmResetDone(i),--: out std_logic_vector(3 downto 0); - - gt0_cpllfbclklost_out => CpllFbClkLost(i),-- : out std_logic_vector(3 downto 0); - gt0_cplllock_out => CpllLock(i),-- : out std_logic_vector(3 downto 0); - - gt0_rxcdrlock_out => RxCdrLock(i),-- : out std_logic_vector(3 downto 0); - -- gt0_qplllock_out => open,-- : out std_logic; - --------------------------- - ---- CTRL signals - --------------------------- - gt0_rxslide_in => RxSlide(i), - gt0_txuserrdy_in => '1', - gt0_rxuserrdy_in => '1', - gt_rxpolarity_in => register_map_control.GBT_RXPOLARITY(i), - gt_txpolarity_in => register_map_control.GBT_TXPOLARITY(i), - -- for loopback: default, both signal need to be all '0' - -- read UG476 for the details. NOTE: the TXBUFFER is disabled, so some type of loopbhack may be - --not supported. - -- for loopback rxcdrhold needs to be set, a register needs to be added, check GTH manual for details - -- not tested yet - gt0_loopback_in => register_map_control.GTH_LOOPBACK_CONTROL, - gt0_rxcdrhold_in => '0', - ---------------------------------------------------------------- - ----------RESET SIGNALs - ---------------------------------------------------------------- - - SOFT_RESET_IN => SOFT_RESET(i/4) or rst_hw or SOFT_TXRST_GT(i), - GTTX_RESET_IN => GTTX_RESET(i), - GTRX_RESET_IN => GTRX_RESET(i), - gt0_cpllreset_in => CPLL_RESET(i), - --QPLL_RESET_IN : in std_logic; - - SOFT_TXRST_GT => SOFT_TXRST_GT(i) or rst_hw, - SOFT_RXRST_GT => SOFT_RXRST_GT(i) or rst_hw,-- or GTRX_RESET(i), - --SOFT_TXRST_ALL : in std_logic; - --SOFT_RXRST_ALL : in std_logic; - - ----------------------------------------------------------- - ----------- Data and TX/RX Ports - ----------------------------------------------------------- - - gt0_txdata_in => TX_DATA_20b(i), - gt0_rxdata_out => RX_DATA_20b(i), - - - gt0_gthrxn_in => RX_N(i), - gt0_gthrxp_in => RX_P(i), - gt0_gthtxn_out => TX_N(i), - gt0_gthtxp_out => TX_P(i) - - - - + gt0_rxusrclk_in => GT_RX_WORD_CLK(i), --(i) + gt0_rxoutclk_out => GT_RXOUTCLK(i), + gt0_txusrclk_in => GT_TX_WORD_CLK(i), + gt0_txoutclk_out => GT_TXOUTCLK(i), + gt0_txresetdone_out => txresetdone(i), --: out std_logic_vector(3 downto 0); + gt0_rxresetdone_out => rxresetdone(i), --: out std_logic_vector(3 downto 0); + gt0_tx_fsm_reset_done_out => txfsmresetdone(i), --: out std_logic_vector(3 downto 0); + gt0_rx_fsm_reset_done_out => rxfsmresetdone(i), --: out std_logic_vector(3 downto 0); + gt0_cpllfbclklost_out => cpllfbclklost(i), -- : out std_logic_vector(3 downto 0); + gt0_cplllock_out => cplllock(i), -- : out std_logic_vector(3 downto 0); + gt0_rxcdrlock_out => rxcdrlock(i), -- : out std_logic_vector(3 downto 0); + gt0_rxslide_in => RxSlide(i), + gt_txpolarity_in => register_map_control.GBT_TXPOLARITY(i), + gt_rxpolarity_in => register_map_control.GBT_RXPOLARITY(i), + gt0_txuserrdy_in => '1', + gt0_rxuserrdy_in => '1', + --SOFT_RESET_IN => soft_reset(i/4) or rst_hw or SOFT_TXRST_GT(i), + GTTX_RESET_IN => gttx_reset(i), + GTRX_RESET_IN => gtrx_reset(i), + gt0_cpllreset_in => cpll_reset(i), + SOFT_TXRST_GT => SOFT_TXRST_GT(i) or rst_hw, + SOFT_RXRST_GT => SOFT_RXRST_GT(i) or rst_hw, -- or GTRX_RESET(i), + gt0_txdata_in => TX_DATA_20b(i), + gt0_rxdata_out => RX_DATA_20b(i), + gt0_gthrxn_in => RX_N(i), + gt0_gthrxp_in => RX_P(i), + gt0_gthtxn_out => TX_N(i), + gt0_gthtxp_out => TX_P(i) ); --QpllLock(i) <='1'; @@ -910,103 +870,66 @@ QPLL_GEN: if PLL_SEL = QPLL generate GTH_TOP_INST: entity work.GTH_QPLL_Wrapper_V7 Port map ( - ---------- Registers in & out - - gt_txresetdone_out => TxResetDone(4*i+3 downto 4*i), - gt_rxresetdone_out => RxResetDone(4*i+3 downto 4*i), - - gt_txfsmresetdone_out => TxFsmResetDone(4*i+3 downto 4*i), - gt_rxfsmresetdone_out => RxFsmResetDone(4*i+3 downto 4*i), - - gt_cpllfbclklost_out => CpllFbClkLost(4*i+3 downto 4*i), - gt_cplllock_out => CpllLock(4*i+3 downto 4*i), - - gt_rxcdrlock_out => RxCdrLock(4*i+3 downto 4*i), - gt_qplllock_out => QpllLock(i), ---------------------------- ----- CTRL signals ---------------------------- - gt_rxslide_in => RxSlide(4*i+3 downto 4*i), - gt_txuserrdy_in => "1111",--TxUsrRdy(4*i+3 downto 4*i), - gt_rxuserrdy_in => "1111",--RxUsrRdy(4*i+3 downto 4*i), - gt_rxpolarity_in => register_map_control.GBT_RXPOLARITY(4*i+3 downto 4*i), - gt_txpolarity_in => register_map_control.GBT_TXPOLARITY(4*i+3 downto 4*i), - - -- for loopback: default, both signal need to be all '0' - -- read UG476 for the details. NOTE: the TXBUFFER is disabled, so some type of loopbhack may be - --not supported. - -- for loopback rxcdrhold needs to be set, a register needs to be added, check GTH manual for details - -- not tested yet - gt0_loopback_in => register_map_control.GTH_LOOPBACK_CONTROL, - gt0_rxcdrhold_in => '0', - gt1_loopback_in => register_map_control.GTH_LOOPBACK_CONTROL, - gt1_rxcdrhold_in => '0', - gt2_loopback_in => register_map_control.GTH_LOOPBACK_CONTROL, - gt2_rxcdrhold_in => '0', - gt3_loopback_in => register_map_control.GTH_LOOPBACK_CONTROL, - gt3_rxcdrhold_in => '0', - - ----------------------------------------------------------------- -----------RESET SIGNALs ----------------------------------------------------------------- - - SOFT_RESET_IN => SOFT_RESET(i) or rst_hw, - GTTX_RESET_IN => GTTX_RESET(4*i+3 downto 4*i),-- or rst_hw, - GTRX_RESET_IN => GTRX_RESET_i(4*i+3 downto 4*i), - CPLL_RESET_IN => CPLL_RESET(4*i+3 downto 4*i), - QPLL_RESET_IN => QPLL_RESET(i), - - SOFT_TXRST_GT => SOFT_TXRST_GT(4*i+3 downto 4*i), - SOFT_RXRST_GT => SOFT_RXRST_GT(4*i+3 downto 4*i), - SOFT_TXRST_ALL => SOFT_TXRST_ALL(i) or rst_hw, - SOFT_RXRST_ALL => SOFT_RXRST_ALL(i) or rst_hw, - ----------- Clocks - DRP_CLK_IN => DRP_CLK_IN, - - GTH_RefClk => GTH_RefClk(4*i), - - gt3_rxoutclk_out => GT_RXOUTCLK(4*i+3), - gt2_rxoutclk_out => GT_RXOUTCLK(4*i+2), - gt1_rxoutclk_out => GT_RXOUTCLK(4*i+1), - gt0_rxoutclk_out => GT_RXOUTCLK(4*i), - - - gt3_txoutclk_out => GT_TXOUTCLK(4*i+3), - gt2_txoutclk_out => GT_TXOUTCLK(4*i+2), - gt1_txoutclk_out => GT_TXOUTCLK(4*i+1), - gt0_txoutclk_out => GT_TXOUTCLK(4*i), - - gt3_rxusrclk_in => GT_RX_WORD_CLK(4*i+3), - gt2_rxusrclk_in => GT_RX_WORD_CLK(4*i+2), - gt1_rxusrclk_in => GT_RX_WORD_CLK(4*i+1), - gt0_rxusrclk_in => GT_RX_WORD_CLK(4*i), - - - gt3_txusrclk_in => GT_TXUSRCLK(i),--GT_TX_WORD_CLK(4*i+3), - gt2_txusrclk_in => GT_TXUSRCLK(i),--GT_TX_WORD_CLK(4*i+2), - gt1_txusrclk_in => GT_TXUSRCLK(i),--GT_TX_WORD_CLK(4*i+1), - gt0_txusrclk_in => GT_TXUSRCLK(i),--GT_TX_WORD_CLK(4*i), - - ----------- DATA - RX_DATA_gt0_20b => RX_DATA_20b(4*i), - TX_DATA_gt0_20b => TX_DATA_20b(4*i), - RX_DATA_gt1_20b => RX_DATA_20b(4*i+1), - TX_DATA_gt1_20b => TX_DATA_20b(4*i+1), - RX_DATA_gt2_20b => RX_DATA_20b(4*i+2), - TX_DATA_gt2_20b => TX_DATA_20b(4*i+2), - RX_DATA_gt3_20b => RX_DATA_20b(4*i+3), - TX_DATA_gt3_20b => TX_DATA_20b(4*i+3), - ---------- GTH Data pins - TXP_OUT => TX_P_i(4*i+3 downto 4*i), - TXN_OUT => TX_N_i(4*i+3 downto 4*i), - RXP_IN => RX_P_i(4*i+3 downto 4*i), - RXN_IN => RX_N_i(4*i+3 downto 4*i) - + GTH_RefClk => GTH_RefClk(4*i), + DRP_CLK_IN => DRP_CLK_IN, + gt0_rxusrclk_in => GT_RX_WORD_CLK(4*i), + gt0_rxoutclk_out => GT_RXOUTCLK(4*i), + gt1_rxusrclk_in => GT_RX_WORD_CLK(4*i+1), + gt1_rxoutclk_out => GT_RXOUTCLK(4*i+1), + gt2_rxusrclk_in => GT_RX_WORD_CLK(4*i+2), + gt2_rxoutclk_out => GT_RXOUTCLK(4*i+2), + gt3_rxusrclk_in => GT_RX_WORD_CLK(4*i+3), + gt3_rxoutclk_out => GT_RXOUTCLK(4*i+3), + gt0_txusrclk_in => GT_TXUSRCLK(i), --GT_TX_WORD_CLK(4*i), + gt0_txoutclk_out => GT_TXOUTCLK(4*i), + --gt1_txusrclk_in => GT_TXUSRCLK(i), --GT_TX_WORD_CLK(4*i+1), + gt1_txoutclk_out => GT_TXOUTCLK(4*i+1), + --gt2_txusrclk_in => GT_TXUSRCLK(i), --GT_TX_WORD_CLK(4*i+2), + gt2_txoutclk_out => GT_TXOUTCLK(4*i+2), + --gt3_txusrclk_in => GT_TXUSRCLK(i), --GT_TX_WORD_CLK(4*i+3), + gt3_txoutclk_out => GT_TXOUTCLK(4*i+3), + gt_txresetdone_out => txresetdone(4*i+3 downto 4*i), + gt_rxresetdone_out => rxresetdone(4*i+3 downto 4*i), + gt_txfsmresetdone_out => txfsmresetdone(4*i+3 downto 4*i), + gt_rxfsmresetdone_out => rxfsmresetdone(4*i+3 downto 4*i), + gt_cpllfbclklost_out => cpllfbclklost(4*i+3 downto 4*i), + gt_cplllock_out => cplllock(4*i+3 downto 4*i), + gt_rxcdrlock_out => rxcdrlock(4*i+3 downto 4*i), + gt_qplllock_out => qplllock(i), + gt_rxslide_in => RxSlide(4*i+3 downto 4*i), + gt_txpolarity_in => register_map_control.GBT_TXPOLARITY(4*i+3 downto 4*i), + gt_rxpolarity_in => register_map_control.GBT_RXPOLARITY(4*i+3 downto 4*i), + gt_txuserrdy_in => "1111", --TxUsrRdy(4*i+3 downto 4*i), + gt_rxuserrdy_in => "1111", --RxUsrRdy(4*i+3 downto 4*i), + gt0_loopback_in => register_map_control.GTH_LOOPBACK_CONTROL, + gt0_rxcdrhold_in => '0', + gt1_loopback_in => register_map_control.GTH_LOOPBACK_CONTROL, + gt1_rxcdrhold_in => '0', + gt2_loopback_in => register_map_control.GTH_LOOPBACK_CONTROL, + gt2_rxcdrhold_in => '0', + gt3_loopback_in => register_map_control.GTH_LOOPBACK_CONTROL, + gt3_rxcdrhold_in => '0', + --SOFT_RESET_IN => soft_reset(i) or rst_hw, + GTTX_RESET_IN => gttx_reset(4*i+3 downto 4*i), -- or rst_hw, + GTRX_RESET_IN => gtrx_reset_i(4*i+3 downto 4*i), + --CPLL_RESET_IN => cpll_reset(4*i+3 downto 4*i), + QPLL_RESET_IN => qpll_reset(i), + --SOFT_TXRST_GT => SOFT_TXRST_GT(4*i+3 downto 4*i), + --SOFT_RXRST_GT => SOFT_RXRST_GT(4*i+3 downto 4*i), + SOFT_TXRST_ALL => SOFT_TXRST_ALL(i) or rst_hw, + SOFT_RXRST_ALL => SOFT_RXRST_ALL(i) or rst_hw, + RX_DATA_gt0_20b => RX_DATA_20b(4*i), + TX_DATA_gt0_20b => TX_DATA_20b(4*i), + RX_DATA_gt1_20b => RX_DATA_20b(4*i+1), + TX_DATA_gt1_20b => TX_DATA_20b(4*i+1), + RX_DATA_gt2_20b => RX_DATA_20b(4*i+2), + TX_DATA_gt2_20b => TX_DATA_20b(4*i+2), + RX_DATA_gt3_20b => RX_DATA_20b(4*i+3), + TX_DATA_gt3_20b => TX_DATA_20b(4*i+3), + RXN_IN => RX_N_i(4*i+3 downto 4*i), + RXP_IN => RX_P_i(4*i+3 downto 4*i), + TXN_OUT => TX_N_i(4*i+3 downto 4*i), + TXP_OUT => TX_P_i(4*i+3 downto 4*i) ); diff --git a/sources/GBT/gbt_code/gbtRx_FELIX.vhd b/sources/GBT/gbt_code/gbtRx_FELIX.vhd index 498b962d1e203b808a30e630b9d23186de1aa1d4..f3338f975abddce276010e5c50e949d211e39cc6 100644 --- a/sources/GBT/gbt_code/gbtRx_FELIX.vhd +++ b/sources/GBT/gbt_code/gbtRx_FELIX.vhd @@ -30,7 +30,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" use work.FELIX_gbt_package.all; -- Uncomment the following library declaration if using @@ -50,17 +50,17 @@ entity gbtRx_FELIX is error_o : out std_logic; -- RxWordCnt_out : out std_logic_vector(2 downto 0); RX_RESET_I : in std_logic; - data_sel : in std_logic_vector(3 downto 0); + --data_sel : in std_logic_vector(3 downto 0); RX_LATOPT_DES : in std_logic; RX_WORDCLK_I : in std_logic; des_rxusrclk : in std_logic; -- L40M : in std_logic; - OddEven, TopBot : in std_logic; + --OddEven, TopBot : in std_logic; HeaderFlag : out std_logic; --For 40MHz generation header_found : out std_logic; Rx_Data_Format : in std_logic_vector(1 downto 0); - RX_ISDATA_FLAG_O : out std_logic; + --RX_ISDATA_FLAG_O : out std_logic; RX_DATA_20b_I : in std_logic_vector(19 downto 0); @@ -75,15 +75,15 @@ end gbtRx_FELIX; architecture Behavioral of gbtRx_FELIX is - signal Rx_40M_FrameClk, Rx_240M_WordClk,data_valid_i : std_logic; - signal RxIsData : std_logic; + signal Rx_40M_FrameClk, Rx_240M_WordClk : std_logic; + --signal RxIsData : std_logic; signal RxCommon84b : std_logic_vector(83 downto 0); signal RxExtraWidebus32b : std_logic_vector(31 downto 0); signal Descrambler_enable, Descrambler_enable_r ,error_i ,error_buf, Descrambler_enable_3r,Descrambler_enable_2r : std_logic; signal RxFrame120b : std_logic_vector(119 downto 0); - signal RX_HEADER_r, RX_HEADER: std_logic_vector(3 downto 0); - signal cnta:std_logic_vector(2 downto 0); - signal HeaderLocked_5r, HeaderLocked_4r, HeaderLocked_3r, HeaderLocked_2r, HeaderLocked_r, HeaderLocked,Rx_40M_FrameClk_A:std_logic; + signal RX_HEADER: std_logic_vector(3 downto 0); + --signal cnta:std_logic_vector(2 downto 0); + signal HeaderLocked:std_logic; begin @@ -97,14 +97,14 @@ begin FelixRxGearbox: entity work.gbt_rx_gearbox_FELIX port map ( - OddEven => OddEven, - TopBot => TopBot, + --OddEven => OddEven, + --TopBot => TopBot, HeaderFlag => HeaderFlag, HeaderLocked => HeaderLocked, Descrambler_enable => Descrambler_enable, Rx_40M_FrameClk_O => Rx_40M_FrameClk, Rx_240M_WordClk_I => Rx_240M_WordClk, - RX_ISDATA_FLAG_O => RxIsData, + RX_ISDATA_FLAG_O => open, RX_LATOPT_DES => RX_LATOPT_DES, Rx_Data_Format => Rx_Data_Format, ---- Data in & out @@ -118,17 +118,17 @@ begin Decoder: entity work.gbt_rx_decoder_FELIX port map ( + --------------------------------------- + RX_FRAME_I => RxFrame120b, + DATA_MODE_CFG => Rx_Data_Format, --RX_ISDATA_FLAG_O => RxIsData, --RX_HEADER_LOCKED_FLAG => HeaderLocked, - RX_HEADER => RX_HEADER, - Rx_240M_WordClk_I => Rx_240M_WordClk, - error_o => error_i, - --------------------------------------- - RX_FRAME_I => RxFrame120b, - DATA_MODE_CFG => Rx_Data_Format, + RX_HEADER => RX_HEADER, + error_o => error_i, + Rx_240M_WordClk_I => Rx_240M_WordClk, --------------------------------------- - RX_COMMON_FRAME_O => RxCommon84b, - RX_EXTRA_FRAME_WIDEBUS_O => RxExtraWidebus32b + RX_COMMON_FRAME_O => RxCommon84b, + RX_EXTRA_FRAME_WIDEBUS_O => RxExtraWidebus32b ); -- data_valid <= data_valid_i; @@ -137,16 +137,16 @@ begin begin if des_rxusrclk'event and des_rxusrclk='1' then -- if Rx_240M_WordClk'event and Rx_240M_WordClk='1' then - RX_HEADER_r <= RX_HEADER; + --RX_HEADER_r <= RX_HEADER; Descrambler_enable_r <= Descrambler_enable; Descrambler_enable_2r <= Descrambler_enable_r; Descrambler_enable_3r <= Descrambler_enable_2r; -- Descrambler_enable_2r <= Descrambler_enable_r; - HeaderLocked_5r <= HeaderLocked_4r; - HeaderLocked_4r <= HeaderLocked_3r; - HeaderLocked_3r <= HeaderLocked_2r; - HeaderLocked_2r <= HeaderLocked_r; - HeaderLocked_r <= HeaderLocked; + --HeaderLocked_5r <= HeaderLocked_4r; + --HeaderLocked_4r <= HeaderLocked_3r; + --HeaderLocked_3r <= HeaderLocked_2r; + --HeaderLocked_2r <= HeaderLocked_r; + --HeaderLocked_r <= HeaderLocked; header_found <= HeaderLocked; if Descrambler_enable = '1' then @@ -165,22 +165,17 @@ begin FelixDescrambler: entity work.gbt_rx_descrambler_FELIX port map ( - - RX_HEADER_O => RX_HEADER_O, - RX_HEADER_I => RX_HEADER, - - RX_RESET_I => RX_RESET_I, - RX_FRAMECLK_I => Rx_40M_FrameClk, - RX_WORDCLK_I => des_rxusrclk,--Rx_240M_WordClk, - Descrambler_enable => Descrambler_enable, - DATA_MODE_CFG => Rx_Data_Format, - --------------------------------------- - --------------------------------------- - RX_COMMON_FRAME_I => RxCommon84b, - RX_DATA_O => RX_DATA_84b_O , - --------------------------------------- - RX_EXTRA_FRAME_WIDEBUS_I => RxExtraWidebus32b, - RX_EXTRA_DATA_WIDEBUS_O => RX_EXTRA_DATA_WIDEBUS_O + RX_RESET_I => RX_RESET_I, + descrambler_enable => Descrambler_enable, + DATA_MODE_CFG => Rx_Data_Format, + RX_WORDCLK_I => des_rxusrclk, --Rx_240M_WordClk, + --RX_FRAMECLK_I => Rx_40M_FrameClk, + RX_HEADER_I => RX_HEADER, + RX_HEADER_O => RX_HEADER_O, + RX_COMMON_FRAME_I => RxCommon84b, + RX_DATA_O => RX_DATA_84b_O, + RX_EXTRA_FRAME_WIDEBUS_I => RxExtraWidebus32b, + RX_EXTRA_DATA_WIDEBUS_O => RX_EXTRA_DATA_WIDEBUS_O ); end Behavioral; diff --git a/sources/GBT/gbt_code/gbtTxRx_FELIX.vhd b/sources/GBT/gbt_code/gbtTxRx_FELIX.vhd index bb6ea226fba6aa8ba1989af80f373c1f5f9e0969..a8a9e87ed0111ffc534b17a85745e0647ba0adb6 100644 --- a/sources/GBT/gbt_code/gbtTxRx_FELIX.vhd +++ b/sources/GBT/gbt_code/gbtTxRx_FELIX.vhd @@ -60,13 +60,13 @@ entity gbtTxRx_FELIX is --BITSLIP_MANUAL : in std_logic; --BITSLIP_SEL : in std_logic; --backup for auto bitslip --GT_RXSLIDE : out std_logic; - OddEven : in std_logic; - TopBot : in std_logic; - data_sel : in std_logic_vector(3 downto 0); + --OddEven : in std_logic; + --TopBot : in std_logic; + --data_sel : in std_logic_vector(3 downto 0); RX_FLAG : out std_logic; TX_FLAG : out std_logic; - Tx_latopt_scr : in std_logic; - Tx_latopt_tc : in std_logic; + --Tx_latopt_scr : in std_logic; + --Tx_latopt_tc : in std_logic; RX_LATOPT_DES : in std_logic; Tx_DATA_FORMAT : IN STD_LOGIC_VECTOR(1 DOWNTO 0); Rx_Data_Format : IN STD_LOGIC_VECTOR(1 DOWNTO 0); @@ -76,7 +76,7 @@ entity gbtTxRx_FELIX is RX_HEADER_FOUND : out std_logic; RX_WORD_IS_HEADER_O : out std_logic; RX_WORDCLK_I : in std_logic; - RX_ISDATA_FLAG_O : out std_logic; + --RX_ISDATA_FLAG_O : out std_logic; L40M : in std_logic; RX_DATA_20b_I : in std_logic_vector(19 downto 0); @@ -130,7 +130,7 @@ begin --- outsel_o <= outsel_gen; - process(RX_RESET_I, L40M) + process(L40M) begin if L40M'event and L40M='1' then if RX_RESET_I = '1' then @@ -144,7 +144,7 @@ begin desmux_en : if RX_DESCR_MUX_EN = '1' generate - process(RX_RESET_I, L40M) + process(L40M) begin if L40M'event and L40M = '0' then RX_DATA_120b_O_r <= RX_DATA_120b_Oi; @@ -161,26 +161,24 @@ begin gbtRx_inst: entity work.gbtRx_FELIX Port Map( - RX_FLAG => RX_FLAG, - error_o => error_orig, - RX_RESET_I => RX_RESET_I, - RX_FRAME_CLK_O => RX_FRAME_CLK, - RX_WORDCLK_I => RX_WORDCLK_I, - des_rxusrclk => des_rxusrclk, - -- L40M => L40M, - OddEven => OddEven, - TopBot => TopBot, - data_sel => data_sel, - HeaderFlag => HeaderFlag, - header_found => header_found, - Rx_Data_Format => Rx_Data_Format, - RX_ISDATA_FLAG_O => RX_ISDATA_FLAG_O, - RX_LATOPT_DES => RX_LATOPT_DES, - - RX_DATA_20b_I => RX_DATA_20b_I, - RX_HEADER_O => RX_DATA_120b_Oi(119 downto 116), - RX_DATA_84b_O => RX_DATA_120b_Oi(115 downto 32), - RX_EXTRA_DATA_WIDEBUS_O => RX_DATA_120b_Oi(31 downto 0) + RX_FRAME_CLK_O => RX_FRAME_CLK, + RX_FLAG => RX_FLAG, + error_o => error_orig, + RX_RESET_I => RX_RESET_I, + --RX_ISDATA_FLAG_O => RX_ISDATA_FLAG_O, + RX_LATOPT_DES => RX_LATOPT_DES, + RX_WORDCLK_I => RX_WORDCLK_I, + des_rxusrclk => des_rxusrclk, + --OddEven => OddEven, + --TopBot => TopBot, + --data_sel => data_sel, + HeaderFlag => HeaderFlag, + header_found => header_found, + Rx_Data_Format => Rx_Data_Format, + RX_DATA_20b_I => RX_DATA_20b_I, + RX_HEADER_O => RX_DATA_120b_Oi(119 downto 116), + RX_DATA_84b_O => RX_DATA_120b_Oi(115 downto 32), + RX_EXTRA_DATA_WIDEBUS_O => RX_DATA_120b_Oi(31 downto 0) ); RX_HEADER_FOUND <= header_found; @@ -245,22 +243,21 @@ begin Port map ( - TX_FLAG => TX_FLAG, - TX_RESET_I => TX_RESET_I, - TX_FRAMECLK_I => TX_FRAMECLK_I, - TX_WORDCLK_I => TX_WORDCLK_I, - TX_TC_METHOD => TX_TC_METHOD, - TC_EDGE => TC_EDGE, - Tx_latopt_scr => Tx_latopt_scr, - TX_LATOPT_TC => TX_LATOPT_TC, - DATA_MODE_CFG => Tx_DATA_FORMAT, - - TX_TC_DLY_VALUE => TX_TC_DLY_VALUE, + TX_FLAG => TX_FLAG, + TX_RESET_I => TX_RESET_I, + TX_FRAMECLK_I => TX_FRAMECLK_I, + TX_WORDCLK_I => TX_WORDCLK_I, + --Tx_latopt_scr => Tx_latopt_scr, + --TX_LATOPT_TC => Tx_latopt_tc, + TX_TC_METHOD => TX_TC_METHOD, + TC_EDGE => TC_EDGE, + DATA_MODE_CFG => Tx_DATA_FORMAT, + TX_TC_DLY_VALUE => TX_TC_DLY_VALUE, --TX_ISDATA_SEL_I => TX_ISDATA_SEL_I, - TX_HEADER_I => TX_DATA_120b_I(119 downto 116), - TX_DATA_84b_I => TX_DATA_120b_I(115 downto 32), - TX_EXTRA_DATA_WIDEBUS_I => TX_DATA_120b_I(31 downto 0), - TX_DATA_20b_O => TX_DATA_20b_O + TX_HEADER_I => TX_DATA_120b_I(119 downto 116), + TX_DATA_84b_I => TX_DATA_120b_I(115 downto 32), + TX_EXTRA_DATA_WIDEBUS_I => TX_DATA_120b_I(31 downto 0), + TX_DATA_20b_O => TX_DATA_20b_O ); diff --git a/sources/GBT/gbt_code/gbtTx_FELIX.vhd b/sources/GBT/gbt_code/gbtTx_FELIX.vhd index 40bb2836c8354ef22c4083e4aadad1e4ff54c80b..dce23d485d3f519dc0da763ec0b99d68437e7fec 100644 --- a/sources/GBT/gbt_code/gbtTx_FELIX.vhd +++ b/sources/GBT/gbt_code/gbtTx_FELIX.vhd @@ -47,11 +47,11 @@ entity gbtTx_FELIX is Port ( TX_FLAG : out std_logic; - TX_RESET_I : in std_logic; + TX_RESET_I : in std_logic; TX_FRAMECLK_I : in std_logic; - TX_WORDCLK_I : in std_logic; - Tx_latopt_scr : in std_logic; - TX_LATOPT_TC : in std_logic; + TX_WORDCLK_I : in std_logic; + --Tx_latopt_scr : in std_logic; + --TX_LATOPT_TC : in std_logic; TX_TC_METHOD : in std_logic; TC_EDGE : in std_logic; DATA_MODE_CFG : in std_logic_vector(1 downto 0); @@ -60,10 +60,10 @@ entity gbtTx_FELIX is TX_HEADER_I : in std_logic_vector(3 downto 0); --TX_ISDATA_SEL_I : in std_logic; - TX_DATA_84b_I : in std_logic_vector(83 downto 0); + TX_DATA_84b_I : in std_logic_vector(83 downto 0); TX_EXTRA_DATA_WIDEBUS_I : in std_logic_vector(31 downto 0); - TX_DATA_20b_O : out std_logic_vector(19 downto 0) + TX_DATA_20b_O : out std_logic_vector(19 downto 0) ); end gbtTx_FELIX; @@ -72,7 +72,7 @@ architecture Behavioral of gbtTx_FELIX is signal Scrambler_Enable : std_logic; signal Tx_Align_Signal : std_logic; - signal Tx_latopt_tc_i : std_logic; + --signal Tx_latopt_tc_i : std_logic; signal TX_HEADER : std_logic_vector(3 downto 0); signal TxExtraWidebus32b : std_logic_vector(31 downto 0); signal TxCommon84b : std_logic_vector(83 downto 0); @@ -82,37 +82,30 @@ begin TX_FLAG <= Scrambler_Enable; -- Scrambler, clock changed, ctrl signal added. - Tx_latopt_tc_i <= '1' when TX_DLY_SW_CTRL='1' else - Tx_latopt_tc; + --Tx_latopt_tc_i <= '1' when TX_DLY_SW_CTRL='1' else + -- TX_LATOPT_TC; FelixScrambler: entity work.gbt_tx_scrambler_FELIX - generic map - ( - channel => channel - ) + --generic map + --( + -- channel => channel + -- ) port map ( --CTRL - TX_TC_METHOD => TX_TC_METHOD, - TC_EDGE => TC_EDGE, - Scrambler_Enable => Scrambler_Enable, - Tx_Align_Signal => Tx_Align_Signal, - Tx_latopt_tc => Tx_latopt_tc_i,-- Tx_latopt_tc, - - TX_RESET_I => TX_RESET_I, - TX_WORDCLK_I => TX_WORDCLK_I, - TX_FRAMECLK_I => TX_FRAMECLK_I, - - TX_TC_DLY_VALUE => TX_TC_DLY_VALUE, - --------------------------------------- - --TX_ISDATA_SEL_I => TX_ISDATA_SEL_I, - TX_HEADER_I => TX_HEADER_I, - - TX_HEADER_O => TX_HEADER, - --------------------------------------- - TX_DATA_I => TX_DATA_84b_I, - TX_COMMON_FRAME_O => TxCommon84b, - --------------------------------------- - TX_EXTRA_DATA_WIDEBUS_I => TX_EXTRA_DATA_WIDEBUS_I, - TX_EXTRA_FRAME_WIDEBUS_O => TxExtraWidebus32b + TX_TC_METHOD => TX_TC_METHOD, + Scrambler_Enable => Scrambler_Enable, + Tx_Align_Signal => Tx_Align_Signal, + --TX_LATOPT_TC => Tx_latopt_tc_i, -- Tx_latopt_tc, + TC_EDGE => TC_EDGE, + TX_TC_DLY_VALUE => TX_TC_DLY_VALUE, + TX_WORDCLK_I => TX_WORDCLK_I, + TX_RESET_I => TX_RESET_I, + TX_FRAMECLK_I => TX_FRAMECLK_I, + TX_HEADER_I => TX_HEADER_I, + TX_HEADER_O => TX_HEADER, + TX_DATA_I => TX_DATA_84b_I, + TX_COMMON_FRAME_O => TxCommon84b, + TX_EXTRA_DATA_WIDEBUS_I => TX_EXTRA_DATA_WIDEBUS_I, + TX_EXTRA_FRAME_WIDEBUS_O => TxExtraWidebus32b ); @@ -120,14 +113,11 @@ begin -- Encoder encoder: entity work.gbt_tx_encoder_FELIX port map ( - - TX_HEADER_I => TX_HEADER, - DATA_MODE_CFG => DATA_MODE_CFG, - --------------------------------------- - TX_COMMON_FRAME_I => TxCommon84b, - TX_EXTRA_FRAME_WIDEBUS_I => TxExtraWidebus32b, - --------------------------------------- - TX_FRAME_O => TxFrame120b + DATA_MODE_CFG => DATA_MODE_CFG, + TX_HEADER_I => TX_HEADER, + TX_COMMON_FRAME_I => TxCommon84b, + TX_EXTRA_FRAME_WIDEBUS_I => TxExtraWidebus32b, + TX_FRAME_O => TxFrame120b ); ---- TxGearBox, control signal added, @@ -140,16 +130,14 @@ begin channel => channel ) port map ( - Scrambler_Enable_o => Scrambler_Enable, - Tx_Align_Signal => Tx_Align_Signal, - TX_LATOPT_SCR => '1',--TX_LATOPT_SCR, - - TX_RESET_I => TX_RESET_I, - TX_FRAMECLK_I => TX_FRAMECLK_I, - TX_WORDCLK_I => TX_WORDCLK_I, - --------------------------------------- - TX_FRAME_I => TxFrame120b, - TX_WORD_OO => TX_DATA_20b_o + Scrambler_Enable_o => Scrambler_Enable, + Tx_Align_Signal => Tx_Align_Signal, + TX_LATOPT_SCR => '1', --TX_LATOPT_SCR, + --TX_RESET_I => TX_RESET_I, + TX_WORDCLK_I => TX_WORDCLK_I, + --TX_FRAMECLK_I => TX_FRAMECLK_I, + TX_FRAME_I => TxFrame120b, + TX_WORD_OO => TX_DATA_20b_O ); end Behavioral; diff --git a/sources/GBT/gbt_code/gbt_rx_decoder_gbtframe_rs2errcor.vhd b/sources/GBT/gbt_code/gbt_rx_decoder_gbtframe_rs2errcor.vhd index a2a6c2f0d16b8734b9e400976d37aa096dd25a55..c538eadd30f4285182f24fc0d95b38a1d6c18b6e 100644 --- a/sources/GBT/gbt_code/gbt_rx_decoder_gbtframe_rs2errcor.vhd +++ b/sources/GBT/gbt_code/gbt_rx_decoder_gbtframe_rs2errcor.vhd @@ -66,7 +66,7 @@ use work.FELIX_gbt_package.all; entity gbt_rx_decoder_gbtframe_rs2errcor is port ( - Rx_240M_WordClk_I : in std_logic; + --Rx_240M_WordClk_I : in std_logic; --========-- -- Inputs -- --========-- diff --git a/sources/GBT/gbt_code/gbt_rx_decoder_gbtframe_rsdec.vhd b/sources/GBT/gbt_code/gbt_rx_decoder_gbtframe_rsdec.vhd index 048fe7626f0524bb3ac00d6f6fd80e16ab4f9063..8725918f46a29cbe01df12fb23026a7502eefe32 100644 --- a/sources/GBT/gbt_code/gbt_rx_decoder_gbtframe_rsdec.vhd +++ b/sources/GBT/gbt_code/gbt_rx_decoder_gbtframe_rsdec.vhd @@ -154,7 +154,7 @@ begin --========#### Architecture Body ####========-- rsTwoErrorsCorrect: entity work.gbt_rx_decoder_gbtframe_rs2errcor port map( - Rx_240M_WordClk_I =>'0', + --Rx_240M_WordClk_I =>'0', S1_I => s1_from_syndromes, S2_I => s2_from_syndromes, XX0_I => xx0_from_chienSearch, diff --git a/sources/GBT/gbt_code/gbt_rx_decoder_gbtframe_rsdec_sync.vhd b/sources/GBT/gbt_code/gbt_rx_decoder_gbtframe_rsdec_sync.vhd index ca538f669e6dde4d88ca23bdd53493c4463889b9..1618b8dc5770702154412f2a8456d067e0aa97aa 100644 --- a/sources/GBT/gbt_code/gbt_rx_decoder_gbtframe_rsdec_sync.vhd +++ b/sources/GBT/gbt_code/gbt_rx_decoder_gbtframe_rsdec_sync.vhd @@ -103,8 +103,8 @@ architecture structural of gbt_rx_decoder_gbtframe_rsdec_sync is signal error1loc_from_errorLocPolynomial ,error1loc_from_errorLocPolynomial_buf : std_logic_vector( 3 downto 0); signal error2loc_from_errorLocPolynomial ,error2loc_from_errorLocPolynomial_buf : std_logic_vector( 3 downto 0); - signal xx0_from_chienSearch ,xx0_from_chienSearch_buf : std_logic_vector( 3 downto 0); - signal xx1_from_chienSearch ,xx1_from_chienSearch_buf : std_logic_vector( 3 downto 0); + signal xx0_from_chienSearch_buf : std_logic_vector( 3 downto 0); + signal xx1_from_chienSearch_buf : std_logic_vector( 3 downto 0); signal corCoeffs_from_rsTwoErrorsCorrect ,corCoeffs_from_rsTwoErrorsCorrect_buf : std_logic_vector(59 downto 0); @@ -170,15 +170,15 @@ begin --========#### Architecture Body ####========-- ERROR_2_LOC_I => error2loc_from_errorLocPolynomial, DET_IS_ZERO_I => detIsZero_from_lambdaDeterminant, XX0_O => xx0_from_chienSearch_buf, - XX1_O => xx1_from_chienSearch_Buf + XX1_O => xx1_from_chienSearch_buf ); process(Rx_240M_WordClk_I) begin if Rx_240M_WordClk_I'event and Rx_240M_WordClk_I='1' then - xx0_from_chienSearch <= xx0_from_chienSearch_buf; - xx1_from_chienSearch <= xx1_from_chienSearch_Buf; + --xx0_from_chienSearch <= xx0_from_chienSearch_buf; + --xx1_from_chienSearch <= xx1_from_chienSearch_buf; error1loc_from_errorLocPolynomial <= error1loc_from_errorLocPolynomial_buf; error2loc_from_errorLocPolynomial <= error2loc_from_errorLocPolynomial_buf; @@ -189,7 +189,7 @@ begin --========#### Architecture Body ####========-- corCoeffs_from_rsTwoErrorsCorrect <= corCoeffs_from_rsTwoErrorsCorrect_buf; rsTwoErrorsCorrect: entity work.gbt_rx_decoder_gbtframe_rs2errcor port map( - Rx_240M_WordClk_I => Rx_240M_WordClk_I, + --Rx_240M_WordClk_I => Rx_240M_WordClk_I, S1_I => s1_from_syndromes_r, S2_I => s2_from_syndromes_r, XX0_I => xx0_from_chienSearch_buf, diff --git a/sources/GBT/gbt_code/gbt_rx_descrambler_FELIX.vhd b/sources/GBT/gbt_code/gbt_rx_descrambler_FELIX.vhd index 7f9e30ac760534f788b5d0930092d42fb6e233b3..8a46d839c6e82b7ef43f3852bcad30bf887f988e 100644 --- a/sources/GBT/gbt_code/gbt_rx_descrambler_FELIX.vhd +++ b/sources/GBT/gbt_code/gbt_rx_descrambler_FELIX.vhd @@ -81,7 +81,7 @@ entity gbt_rx_descrambler_FELIX is -- Clock: --------- RX_WORDCLK_I : IN STD_LOGIC; - RX_FRAMECLK_I : in std_logic; + --RX_FRAMECLK_I : in std_logic; --==============-- @@ -136,11 +136,11 @@ begin --========#### Architecture Body ####========-- gbtRxDescrambler21bit: entity work.gbt_rx_descrambler_21bit port map( - RX_RESET_I => RX_RESET_I, - RX_FRAMECLK_I => RX_WORDCLK_I, - Descrambler_enable => Descrambler_enable, - RX_COMMON_FRAME_I => RX_COMMON_FRAME_I(((21*i)+20) downto (21*i)), - RX_DATA_O => RX_DATA_O(((21*i)+20) downto (21*i)) + Descrambler_enable => descrambler_enable, + RX_RESET_I => RX_RESET_I, + RX_FRAMECLK_I => RX_WORDCLK_I, + RX_COMMON_FRAME_I => RX_COMMON_FRAME_I(((21*i)+20) downto (21*i)), + RX_DATA_O => RX_DATA_O(((21*i)+20) downto (21*i)) ); end generate; @@ -154,11 +154,11 @@ begin --========#### Architecture Body ####========-- -- Comment: [31:16] & [15:0] gbtRxDescrambler16bit: entity work.gbt_rx_descrambler_16bit port map( - RX_RESET_I => RX_RESET_I, - RX_FRAMECLK_I => RX_WORDCLK_I, - Descrambler_enable => Descrambler_enable, - RX_EXTRA_FRAME_WIDEBUS_I => RX_EXTRA_FRAME_WIDEBUS_I(((16*i)+15) downto (16*i)), - RX_EXTRA_DATA_WIDEBUS_O => RX_EXTRA_DATA_WIDEBUS_O_DES(((16*i)+15) downto (16*i)) + Descrambler_enable => descrambler_enable, + RX_RESET_I => RX_RESET_I, + RX_FRAMECLK_I => RX_WORDCLK_I, + RX_EXTRA_FRAME_WIDEBUS_I => RX_EXTRA_FRAME_WIDEBUS_I(((16*i)+15) downto (16*i)), + RX_EXTRA_DATA_WIDEBUS_O => RX_EXTRA_DATA_WIDEBUS_O_DES(((16*i)+15) downto (16*i)) ); end generate; diff --git a/sources/GBT/gbt_code/gbt_rx_gearbox_FELIX_wi_rxbuffer.vhd b/sources/GBT/gbt_code/gbt_rx_gearbox_FELIX_wi_rxbuffer.vhd index b7b4d512f7ba9b0e4149b5a9c6335ac023216ced..9219dd35a8267ac79a9d7c4d06ce39cb0f5ebf10 100644 --- a/sources/GBT/gbt_code/gbt_rx_gearbox_FELIX_wi_rxbuffer.vhd +++ b/sources/GBT/gbt_code/gbt_rx_gearbox_FELIX_wi_rxbuffer.vhd @@ -30,7 +30,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. @@ -42,8 +42,8 @@ use work.FELIX_gbt_package.all; entity gbt_rx_gearbox_FELIX is port ( ---- Ctrl & Status - OddEven : in std_logic; - TopBot : in std_logic; + --OddEven : in std_logic; + --TopBot : in std_logic; HeaderFlag : out std_logic; HeaderLocked : out std_logic; Descrambler_enable : out std_logic; @@ -64,8 +64,8 @@ architecture Behavioral of gbt_rx_gearbox_FELIX is signal reg_inv : std_logic_vector(119 downto 0); signal shiftreg : std_logic_vector(119 downto 0); - signal reg_inv_wb : std_logic_vector(119 downto 0); - signal reg_inv_gf : std_logic_vector(119 downto 0); + --signal reg_inv_wb : std_logic_vector(119 downto 0); + --signal reg_inv_gf : std_logic_vector(119 downto 0); signal RxWordCnt : std_logic_vector(2 downto 0); signal Rx_40M_FrameClk : std_logic; signal Data_Header : std_logic; @@ -74,17 +74,17 @@ architecture Behavioral of gbt_rx_gearbox_FELIX is signal Rx_40M_FrameClk_gf : std_logic; signal Rx_40M_FrameClk_gf1 : std_logic; signal Rx_40M_FrameClk_wb : std_logic; - signal Descrambler_enable1 : std_logic; + --signal Descrambler_enable1 : std_logic; signal Descrambler_enable_gf1 : std_logic; signal errcnt : std_logic_vector(1 downto 0) := "00"; - signal data_sel : std_logic_vector(1 downto 0) := "00"; - signal Descrambler_enable_wb1 : std_logic; - signal Rx_40M_FrameClk_wb1 : std_logic; - signal Descrambler_enable_gf_r: std_logic; - signal Rx_40M_FrameClk_gf_r : std_logic; + --signal data_sel : std_logic_vector(1 downto 0) := "00"; + --signal Descrambler_enable_wb1 : std_logic; + --signal Rx_40M_FrameClk_wb1 : std_logic; + --signal Descrambler_enable_gf_r: std_logic; + --signal Rx_40M_FrameClk_gf_r : std_logic; signal Rx_Word_I : std_logic_vector(19 downto 0); - signal Rx_Word_In_buf : std_logic_vector(19 downto 0); - signal Rx_Word_In_buf2 : std_logic_vector(19 downto 0); + --signal Rx_Word_In_buf : std_logic_vector(19 downto 0); + --signal Rx_Word_In_buf2 : std_logic_vector(19 downto 0); begin @@ -112,7 +112,7 @@ begin when "011" => Descrambler_enable_gf <= '0'; if RX_LATOPT_DESCRAMBLER = '1' and DYNAMIC_LATENCY_OPT = '0' then - Rx_40M_FrameClk_gf <= '1'; + Rx_40M_FrameClk_gf <= '1'; -- @suppress "Dead code" elsif RX_LATOPT_DES = '1' and DYNAMIC_LATENCY_OPT = '1' then Rx_40M_FrameClk_gf <= '1'; else @@ -133,7 +133,7 @@ begin -- reg_inv <= Rx_Word_I & shiftreg(119 downto 20); Descrambler_enable_gf <= '0'; if RX_LATOPT_DESCRAMBLER = '1' and DYNAMIC_LATENCY_OPT = '0' then - Rx_40M_FrameClk_gf <= '0'; + Rx_40M_FrameClk_gf <= '0'; -- @suppress "Dead code" elsif RX_LATOPT_DES = '1' and DYNAMIC_LATENCY_OPT = '1' then Rx_40M_FrameClk_gf <= '0'; else @@ -145,7 +145,7 @@ begin end if; end process; - data_sel <= topbot & OddEven; + --data_sel <= TopBot & OddEven; process(Rx_240M_WordClk_I) begin @@ -175,7 +175,7 @@ begin when "001" => Descrambler_enable_wb <= '0'; if RX_LATOPT_DESCRAMBLER = '1' and DYNAMIC_LATENCY_OPT = '0' then - Rx_40M_FrameClk_wb <= '1'; + Rx_40M_FrameClk_wb <= '1'; -- @suppress "Dead code" elsif RX_LATOPT_DES = '1' and DYNAMIC_LATENCY_OPT = '1' then Rx_40M_FrameClk_wb <= '1'; else @@ -199,7 +199,7 @@ begin when "100" => Descrambler_enable_wb <= '0'; if RX_LATOPT_DESCRAMBLER = '1' and DYNAMIC_LATENCY_OPT = '0' then - Rx_40M_FrameClk_wb <= '0'; + Rx_40M_FrameClk_wb <= '0'; -- @suppress "Dead code" elsif RX_LATOPT_DES = '1' and DYNAMIC_LATENCY_OPT = '1' then Rx_40M_FrameClk_wb <= '0'; else @@ -254,8 +254,8 @@ end generate; process(Rx_240M_WordClk_I) begin if Rx_240M_WordClk_I'event and Rx_240M_WordClk_I = '1' then - Descrambler_enable_wb1 <= Descrambler_enable_wb; - Rx_40M_FrameClk_wb1 <= Rx_40M_FrameClk_wb; + --Descrambler_enable_wb1 <= Descrambler_enable_wb; + --Rx_40M_FrameClk_wb1 <= Rx_40M_FrameClk_wb; Descrambler_enable_gf1 <= Descrambler_enable_gf; Rx_40M_FrameClk_gf1 <= Rx_40M_FrameClk_gf; diff --git a/sources/GBT/gbt_code/gbt_tx_gearbox_FELIX.vhd b/sources/GBT/gbt_code/gbt_tx_gearbox_FELIX.vhd index cce09d1742ecd00186ba33343df2e5d70243dbb9..80c97ebaaca473ecada51d7219ac2d885883a2e0 100644 --- a/sources/GBT/gbt_code/gbt_tx_gearbox_FELIX.vhd +++ b/sources/GBT/gbt_code/gbt_tx_gearbox_FELIX.vhd @@ -64,7 +64,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" -- Custom libraries and packages: use work.FELIX_gbt_package.all; @@ -92,13 +92,13 @@ channel : integer := 0 -- Reset: --------- - TX_RESET_I : in std_logic; + --TX_RESET_I : in std_logic; -- Clocks: ---------- TX_WORDCLK_I : in std_logic; - TX_FRAMECLK_I : in std_logic; + --TX_FRAMECLK_I : in std_logic; --==============-- -- Frame & Word -- @@ -120,7 +120,7 @@ architecture behavioral of gbt_tx_gearbox_FELIX is signal txFrame_from_frameInverter : std_logic_vector (119 downto 0); signal tx_buffer : std_logic_vector (119 downto 0); - signal gearboxSyncReset : std_logic; + --signal gearboxSyncReset : std_logic; signal address : std_logic_vector(2 downto 0); signal TX_WORD_O_r : std_logic_vector(19 downto 0); signal TX_WORD_O : std_logic_vector(19 downto 0); diff --git a/sources/GBT/gbt_code/gbt_tx_scrambler_16bit.vhd b/sources/GBT/gbt_code/gbt_tx_scrambler_16bit.vhd index e26d38ed4791ae057a8b165437ace44fb2b456ef..2d7e499b17e5953e0a8e3d3391f6bf3bb9b0c8f6 100644 --- a/sources/GBT/gbt_code/gbt_tx_scrambler_16bit.vhd +++ b/sources/GBT/gbt_code/gbt_tx_scrambler_16bit.vhd @@ -113,7 +113,7 @@ begin --========#### Architecture Body ####========-- --==================================== User Logic =====================================-- - scrambler16bit: process(TX_RESET_I, TX_FRAMECLK_I) + scrambler16bit: process(TX_FRAMECLK_I) begin if rising_edge(TX_FRAMECLK_I) then diff --git a/sources/GBT/gbt_code/gbt_tx_scrambler_21bit.vhd b/sources/GBT/gbt_code/gbt_tx_scrambler_21bit.vhd index f9abdb1df97f51186bcbf333545f19c3a6921162..1c6e6c26a3710fab67d304413f638c19cee95a79 100644 --- a/sources/GBT/gbt_code/gbt_tx_scrambler_21bit.vhd +++ b/sources/GBT/gbt_code/gbt_tx_scrambler_21bit.vhd @@ -121,7 +121,7 @@ begin --========#### Architecture Body ####========-- --==================================== User Logic =====================================-- - scrambler21bit: process(TX_RESET_I, TX_FRAMECLK_I) + scrambler21bit: process(TX_FRAMECLK_I) begin if rising_edge(TX_FRAMECLK_I) then if TX_RESET_I = '1' then diff --git a/sources/GBT/gbt_code/gbt_tx_scrambler_FELIX.vhd b/sources/GBT/gbt_code/gbt_tx_scrambler_FELIX.vhd index 339ace707b647e9e18731297455aacd3335aec6f..c51a2ba5ea80c401e500c034f1f7e7bf654191a1 100644 --- a/sources/GBT/gbt_code/gbt_tx_scrambler_FELIX.vhd +++ b/sources/GBT/gbt_code/gbt_tx_scrambler_FELIX.vhd @@ -13,7 +13,7 @@ library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" library UNISIM; use UNISIM.VComponents.all; @@ -21,18 +21,18 @@ use UNISIM.VComponents.all; use work.FELIX_gbt_package.all; entity gbt_tx_scrambler_FELIX is - generic + --generic - ( - channel : integer := 0 - ); + --( + -- channel : integer := 0 + -- ); port ( TX_TC_METHOD : in std_logic; Scrambler_Enable : in std_logic; Tx_Align_Signal : out std_logic; - TX_LATOPT_TC : in std_logic; + --TX_LATOPT_TC : in std_logic; TC_EDGE : in std_logic; TX_TC_DLY_VALUE : in std_logic_vector(2 downto 0); @@ -69,26 +69,21 @@ begin ---- Dec. 2014 timedomaincrossing_C :entity work.gbt_tx_timedomaincrossing_FELIX - generic map - ( - channel => channel - ) + --generic map + --( + -- channel => channel + -- ) port map ( - - TC_EDGE => TC_EDGE, - Tx_Align_Signal => Tx_Align_Signal, - TX_LATOPT_TC => TX_LATOPT_TC, - TX_TC_METHOD => TX_TC_METHOD, - - TX_TC_DLY_VALUE => TX_TC_DLY_VALUE, - - TX_WORDCLK_I => TX_WORDCLK_I, - TX_RESET_I => TX_RESET_I, - TX_FRAMECLK_I => TX_FRAMECLK_I - - - ); + Tx_Align_Signal => Tx_Align_Signal, + TX_TC_METHOD => TX_TC_METHOD, + --TX_LATOPT_TC => TX_LATOPT_TC, + TC_EDGE => TC_EDGE, + TX_TC_DLY_VALUE => TX_TC_DLY_VALUE, + TX_WORDCLK_I => TX_WORDCLK_I, + TX_RESET_I => TX_RESET_I, + TX_FRAMECLK_I => TX_FRAMECLK_I + ); @@ -110,16 +105,15 @@ begin -- Comment: [83:63] & [62:42] & [41:21] & [20:0] gbtTxScrambler21bit: entity work.gbt_tx_scrambler_21bit port map( - TX_RESET_I => TX_RESET_I, - Scrambler_Enable => Scrambler_Enable, - RESET_PATTERN_I => SCRAMBLER_21BIT_RESET_PATTERNS(i), + Scrambler_Enable => Scrambler_Enable, + TX_RESET_I => TX_RESET_I, + RESET_PATTERN_I => SCRAMBLER_21BIT_RESET_PATTERNS(i), --------------------------------- - TX_FRAMECLK_I => TX_WORDCLK_I, + TX_FRAMECLK_I => TX_WORDCLK_I, --------------------------------- - TX_DATA_I => TX_DATA_I(((21*i)+20) downto (21*i)), - TX_COMMON_FRAME_O => TX_COMMON_FRAME_O(((21*i)+20) downto (21*i)) - ); - + TX_DATA_I => TX_DATA_I(((21*i)+20) downto (21*i)), + TX_COMMON_FRAME_O => TX_COMMON_FRAME_O(((21*i)+20) downto (21*i)) + ); end generate; end generate; @@ -133,15 +127,15 @@ begin ---- Comment: [31:16] & [15:0] gbtTxScrambler16bit: entity work.gbt_tx_scrambler_16bit port map( - TX_RESET_I => TX_RESET_I, - Scrambler_Enable => Scrambler_Enable, --'1', - RESET_PATTERN_I => SCRAMBLER_16BIT_RESET_PATTERNS(i), + Scrambler_Enable => Scrambler_Enable, --'1', + TX_RESET_I => TX_RESET_I, + RESET_PATTERN_I => SCRAMBLER_16BIT_RESET_PATTERNS(i), --------------------------------- - TX_FRAMECLK_I => TX_WORDCLK_I, + TX_FRAMECLK_I => TX_WORDCLK_I, --------------------------------- - TX_EXTRA_DATA_WIDEBUS_I => TX_EXTRA_DATA_WIDEBUS_I(((16*i)+15) downto (16*i)), - TX_EXTRA_FRAME_WIDEBUS_O => TX_EXTRA_FRAME_WIDEBUS_O(((16*i)+15) downto (16*i)) - ); + TX_EXTRA_DATA_WIDEBUS_I => TX_EXTRA_DATA_WIDEBUS_I(((16*i)+15) downto (16*i)), + TX_EXTRA_FRAME_WIDEBUS_O => TX_EXTRA_FRAME_WIDEBUS_O(((16*i)+15) downto (16*i)) + ); end generate; end generate; diff --git a/sources/GBT/gbt_code/gbt_tx_timedomaincrossing_FELIX.vhd b/sources/GBT/gbt_code/gbt_tx_timedomaincrossing_FELIX.vhd index d0f901d3b2d2324610c0cdd92ecdce2ecd93af75..759f11015b4bc909e561a0717f8d87b3489c395b 100644 --- a/sources/GBT/gbt_code/gbt_tx_timedomaincrossing_FELIX.vhd +++ b/sources/GBT/gbt_code/gbt_tx_timedomaincrossing_FELIX.vhd @@ -30,7 +30,7 @@ library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" library UNISIM; use UNISIM.VComponents.all; @@ -38,15 +38,15 @@ use UNISIM.VComponents.all; use work.FELIX_gbt_package.all; entity gbt_tx_timedomaincrossing_FELIX is - generic - ( - channel : integer := 0 - ); +-- generic +-- ( +-- channel : integer := 0 +-- ); port ( Tx_Align_Signal : out std_logic; TX_TC_METHOD : in std_logic; - TX_LATOPT_TC : in std_logic; + --TX_LATOPT_TC : in std_logic; TC_EDGE : in std_logic; @@ -65,7 +65,7 @@ end gbt_tx_timedomaincrossing_FELIX; architecture Behavior of gbt_tx_timedomaincrossing_FELIX is - signal fsm_rst : std_logic := '0'; + --signal fsm_rst : std_logic := '0'; signal TX_FRAMECLK_I_4r : std_logic; signal TX_FRAMECLK_I_5r : std_logic; signal TX_FRAMECLK_I_2r : std_logic; @@ -77,7 +77,7 @@ architecture Behavior of gbt_tx_timedomaincrossing_FELIX is signal TX_RESET_r : std_logic; signal TX_RESET_2r : std_logic; signal pulse_rising : std_logic; - signal pulse_rising_r : std_logic; + --signal pulse_rising_r : std_logic; signal pulse_falling_r : std_logic; signal pulse_falling : std_logic; @@ -112,7 +112,7 @@ begin end if; pulse_rising <= TX_FRAMECLK_I_r and (not TX_FRAMECLK_I_2r); pulse_falling <= TX_FRAMECLK_I_4r and (not TX_FRAMECLK_I_5r); - pulse_rising_r <= pulse_rising; + --pulse_rising_r <= pulse_rising; pulse_falling_r <= pulse_falling; if (TX_TC_METHOD='1' or TX_RESET_FLAG='1') then if TC_EDGE='0' then @@ -140,37 +140,37 @@ begin case cnt is when "000" => cnt <= "001"; - fsm_rst <= '0'; + --fsm_rst <= '0'; Tx_Align_Signal <= '0'; -- tx_frameclk_i_shifted <='1'; when "001" => cnt <= "010"; - fsm_rst <= '0'; + --fsm_rst <= '0'; Tx_Align_Signal <= '0'; -- tx_frameclk_i_shifted <='1'; when "010" => cnt <= "011"; - fsm_rst <= '0'; + --fsm_rst <= '0'; Tx_Align_Signal <= '1'; -- tx_frameclk_i_shifted <='0'; when "011" => cnt <= "100"; - fsm_rst <= '0'; + --fsm_rst <= '0'; Tx_Align_Signal <= '0'; -- tx_frameclk_i_shifted <='0'; when "100" => cnt <= "101"; - fsm_rst <= '0'; + --fsm_rst <= '0'; Tx_Align_Signal <= '0'; -- tx_frameclk_i_shifted <='0'; when "101" => cnt <="000"; - fsm_rst <= '0'; + --fsm_rst <= '0'; Tx_Align_Signal <= '0'; -- tx_frameclk_i_shifted <= '1'; when others => cnt <= "101"; - fsm_rst <= '1'; + --fsm_rst <= '1'; Tx_Align_Signal <= '0'; end case; end if; diff --git a/sources/GBT/gth_code/cpll4p8g1ch_KCU/GTH_CPLL_Wrapper.vhd b/sources/GBT/gth_code/cpll4p8g1ch_KCU/GTH_CPLL_Wrapper.vhd index e7172fbf36cab66fc75e92a7d08d316496af60de..8c789cac6bd58968f31cb3ac68e238c197cc27e9 100644 --- a/sources/GBT/gth_code/cpll4p8g1ch_KCU/GTH_CPLL_Wrapper.vhd +++ b/sources/GBT/gth_code/cpll4p8g1ch_KCU/GTH_CPLL_Wrapper.vhd @@ -97,61 +97,67 @@ end GTH_CPLL_Wrapper; architecture Behavioral of GTH_CPLL_Wrapper is - component KCU_NORXBUF_PCS_CPLL_1CH is - port( - gtwiz_userclk_tx_active_in : in std_logic_vector(0 downto 0); - gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_reset_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_start_user_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_error_out : out std_logic_vector(0 downto 0); - gtwiz_buffbypass_rx_reset_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_rx_start_user_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_rx_done_out : out std_logic_vector(0 downto 0); - gtwiz_buffbypass_rx_error_out : out std_logic_vector(0 downto 0); - gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); - gtwiz_reset_all_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_pll_and_datapath_in: in std_logic_vector(0 downto 0); - gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_pll_and_datapath_in: in std_logic_vector(0 downto 0); - gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); - cplllockdetclk_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); - gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); - gtwiz_userdata_tx_in : in std_logic_vector(19 downto 0); - gtwiz_userdata_rx_out : out std_logic_vector(19 downto 0); - cpllreset_in : in std_logic_vector(0 downto 0); - drpclk_in : in std_logic_vector(0 downto 0); - gtgrefclk_in : in std_logic_vector(0 downto 0); - gthrxn_in : in std_logic_vector(0 downto 0); - loopback_in : in std_logic_vector(2 downto 0); - rxcdrhold_in : in std_logic_vector(0 downto 0); - gthrxp_in : in std_logic_vector(0 downto 0); - gtrefclk0_in : in std_logic_vector(0 downto 0); - rxcdrreset_in : in std_logic_vector(0 downto 0); - rxcommadeten_in : in std_logic_vector(0 downto 0); - rxslide_in : in std_logic_vector(0 downto 0); - rxusrclk_in : in std_logic_vector(0 downto 0); - rxusrclk2_in : in std_logic_vector(0 downto 0); - rxpolarity_in : in std_logic_vector(0 downto 0); - txpolarity_in : in std_logic_vector(0 downto 0); - txusrclk_in : in std_logic_vector(0 downto 0); - txusrclk2_in : in std_logic_vector(0 downto 0); - cpllfbclklost_out : out std_logic_vector(0 downto 0); - cplllock_out : out std_logic_vector(0 downto 0); - gthtxn_out : out std_logic_vector(0 downto 0); - gthtxp_out : out std_logic_vector(0 downto 0); - rxcdrlock_out : out std_logic_vector(0 downto 0); - rxdata_out : out std_logic_vector(127 downto 0); - rxoutclk_out : out std_logic_vector(0 downto 0); - rxpmaresetdone_out : out std_logic_vector(0 downto 0); - rxresetdone_out : out std_logic_vector(0 downto 0); - txoutclk_out : out std_logic_vector(0 downto 0); - txpmaresetdone_out : out std_logic_vector(0 downto 0); - txresetdone_out : out std_logic_vector(0 downto 0) + component KCU_NORXBUF_PCS_CPLL_1CH + port( + gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_rx_reset_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_rx_start_user_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_rx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_rx_error_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_all_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR(19 downto 0); + gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR(19 downto 0); + cplllockdetclk_in : in STD_LOGIC_VECTOR(0 to 0); + cpllreset_in : in STD_LOGIC_VECTOR(0 to 0); + drpclk_in : in STD_LOGIC_VECTOR(0 to 0); + gtgrefclk_in : in STD_LOGIC_VECTOR(0 to 0); + gthrxn_in : in STD_LOGIC_VECTOR(0 to 0); + gthrxp_in : in STD_LOGIC_VECTOR(0 to 0); + gtrefclk0_in : in STD_LOGIC_VECTOR(0 to 0); + loopback_in : in STD_LOGIC_VECTOR(2 downto 0); + rxcdrhold_in : in STD_LOGIC_VECTOR(0 to 0); + rxcdrreset_in : in STD_LOGIC_VECTOR(0 to 0); + rxcommadeten_in : in STD_LOGIC_VECTOR(0 to 0); + rxmcommaalignen_in : in STD_LOGIC_VECTOR(0 to 0); + rxpcommaalignen_in : in STD_LOGIC_VECTOR(0 to 0); + rxpolarity_in : in STD_LOGIC_VECTOR(0 to 0); + rxslide_in : in STD_LOGIC_VECTOR(0 to 0); + rxusrclk_in : in STD_LOGIC_VECTOR(0 to 0); + rxusrclk2_in : in STD_LOGIC_VECTOR(0 to 0); + txpolarity_in : in STD_LOGIC_VECTOR(0 to 0); + txusrclk_in : in STD_LOGIC_VECTOR(0 to 0); + txusrclk2_in : in STD_LOGIC_VECTOR(0 to 0); + cpllfbclklost_out : out STD_LOGIC_VECTOR(0 to 0); + cplllock_out : out STD_LOGIC_VECTOR(0 to 0); + gthtxn_out : out STD_LOGIC_VECTOR(0 to 0); + gthtxp_out : out STD_LOGIC_VECTOR(0 to 0); + gtpowergood_out : out STD_LOGIC_VECTOR(0 to 0); + rxbyteisaligned_out : out STD_LOGIC_VECTOR(0 to 0); + rxbyterealign_out : out STD_LOGIC_VECTOR(0 to 0); + rxcdrlock_out : out STD_LOGIC_VECTOR(0 to 0); + rxcommadet_out : out STD_LOGIC_VECTOR(0 to 0); + rxdata_out : out STD_LOGIC_VECTOR(127 downto 0); + rxoutclk_out : out STD_LOGIC_VECTOR(0 to 0); + rxpmaresetdone_out : out STD_LOGIC_VECTOR(0 to 0); + rxresetdone_out : out STD_LOGIC_VECTOR(0 to 0); + txoutclk_out : out STD_LOGIC_VECTOR(0 to 0); + txpmaresetdone_out : out STD_LOGIC_VECTOR(0 to 0); + txresetdone_out : out STD_LOGIC_VECTOR(0 to 0) ); - end component; + end component KCU_NORXBUF_PCS_CPLL_1CH; COMPONENT KCU_RXBUF_PMA_CPLL_1CH PORT ( @@ -279,6 +285,12 @@ begin NORXBUF_GEN: if KCU_LOWER_LATENCY = '1' generate gtwizard_ultrascale_single_channel_cpll_inst: KCU_NORXBUF_PCS_CPLL_1CH port map( + gtpowergood_out => open, + rxbyteisaligned_out => open, + rxbyterealign_out => open, + rxcommadet_out => open, + rxmcommaalignen_in => "0", + rxpcommaalignen_in => "0", cpllreset_in => gndvec, gtgrefclk_in => gndvec, rxcdrreset_in => gndvec,-- diff --git a/sources/GBT/gth_code/cpll4p8g1ch_V7/GTH_CPLL_Wrapper_V7.vhd b/sources/GBT/gth_code/cpll4p8g1ch_V7/GTH_CPLL_Wrapper_V7.vhd index 27541575cf0b5a689a82f1329cfa06c40240e333..78597402628dd9aa752258f77b60c1ee89f98015 100644 --- a/sources/GBT/gth_code/cpll4p8g1ch_V7/GTH_CPLL_Wrapper_V7.vhd +++ b/sources/GBT/gth_code/cpll4p8g1ch_V7/GTH_CPLL_Wrapper_V7.vhd @@ -79,7 +79,7 @@ port ----------RESET SIGNALs ---------------------------------------------------------------- - SOFT_RESET_IN : in std_logic; + --SOFT_RESET_IN : in std_logic; GTTX_RESET_IN : in std_logic; GTRX_RESET_IN : in std_logic; gt0_cpllreset_in : in std_logic; @@ -122,111 +122,80 @@ architecture RTL of GTH_CPLL_Wrapper_V7 is component gtwizard_CPLL_4p8g_V7 - -port -( - SYSCLK_IN : in std_logic; - SOFT_RESET_TX_IN : in std_logic; - SOFT_RESET_RX_IN : in std_logic; - DONT_RESET_ON_DATA_ERROR_IN : in std_logic; - GT0_TX_FSM_RESET_DONE_OUT : out std_logic; - GT0_RX_FSM_RESET_DONE_OUT : out std_logic; - GT0_DATA_VALID_IN : in std_logic; - - --_________________________________________________________________________ - --GT0 (X1Y4) - --____________________________CHANNEL PORTS________________________________ - --------------------------------- CPLL Ports ------------------------------- - gt0_cpllfbclklost_out : out std_logic; - gt0_cplllock_out : out std_logic; - gt0_cplllockdetclk_in : in std_logic; - gt0_cpllreset_in : in std_logic; - -------------------------- Channel - Clocking Ports ------------------------ - gt0_gtrefclk0_in : in std_logic; - gt0_gtrefclk1_in : in std_logic; - ---------------------------- Channel - DRP Ports -------------------------- - gt0_drpaddr_in : in std_logic_vector(8 downto 0); - gt0_drpclk_in : in std_logic; - gt0_drpdi_in : in std_logic_vector(15 downto 0); - gt0_drpdo_out : out std_logic_vector(15 downto 0); - gt0_drpen_in : in std_logic; - gt0_drprdy_out : out std_logic; - gt0_drpwe_in : in std_logic; - --------------------- RX Initialization and Reset Ports -------------------- - gt0_eyescanreset_in : in std_logic; - gt0_rxuserrdy_in : in std_logic; - -------------------------- RX Margin Analysis Ports ------------------------ - gt0_eyescandataerror_out : out std_logic; - gt0_eyescantrigger_in : in std_logic; - --------------- Receive Ports - Comma Detection and Alignment -------------- - gt0_rxslide_in ,gt0_txpolarity_in,gt0_rxpolarity_in : in std_logic; - ------------------- Receive Ports - Digital Monitor Ports ------------------ - gt0_dmonitorout_out : out std_logic_vector(14 downto 0); - ------------------ Receive Ports - FPGA RX Interface Ports ----------------- - gt0_rxusrclk_in : in std_logic; - gt0_rxusrclk2_in : in std_logic; - ------------------ Receive Ports - FPGA RX interface Ports ----------------- - gt0_rxdata_out : out std_logic_vector(19 downto 0); - ------------------------ Receive Ports - RX AFE Ports ---------------------- - gt0_gthrxn_in : in std_logic; - --------------------- Receive Ports - RX Equalizer Ports ------------------- - gt0_rxmonitorout_out : out std_logic_vector(6 downto 0); - gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0); - --------------- Receive Ports - RX Fabric Output Control Ports ------------- - gt0_rxoutclk_out : out std_logic; - gt0_rxoutclkfabric_out : out std_logic; - ------------- Receive Ports - RX Initialization and Reset Ports ------------ - gt0_gtrxreset_in : in std_logic; - ------------------------ Receive Ports -RX AFE Ports ----------------------- - gt0_gthrxp_in : in std_logic; - -------------- Receive Ports -RX Initialization and Reset Ports ------------ - gt0_rxresetdone_out : out std_logic; - --------------------- TX Initialization and Reset Ports -------------------- - gt0_gttxreset_in : in std_logic; - gt0_txuserrdy_in : in std_logic; - ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- - gt0_txusrclk_in : in std_logic; - gt0_txusrclk2_in : in std_logic; - ------------------ Transmit Ports - TX Data Path interface ----------------- - gt0_txdata_in : in std_logic_vector(19 downto 0); - ---------------- Transmit Ports - TX Driver and OOB signaling -------------- - gt0_gthtxn_out : out std_logic; - gt0_gthtxp_out : out std_logic; - ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- - gt0_txoutclk_out : out std_logic; - gt0_txoutclkfabric_out : out std_logic; - gt0_txoutclkpcs_out : out std_logic; - ------------- Transmit Ports - TX Initialization and Reset Ports ----------- - gt0_txresetdone_out : out std_logic; - - gt0_loopback_in : in std_logic_vector(2 downto 0); - gt0_rxcdrhold_in : in std_logic; - --____________________________COMMON PORTS________________________________ - GT0_QPLLOUTCLK_IN : in std_logic; - GT0_QPLLOUTREFCLK_IN : in std_logic - -); - -end component; + port( + SYSCLK_IN : in STD_LOGIC; + SOFT_RESET_TX_IN : in STD_LOGIC; + SOFT_RESET_RX_IN : in STD_LOGIC; + DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC; + GT0_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; + GT0_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; + GT0_DATA_VALID_IN : in STD_LOGIC; + gt0_cpllfbclklost_out : out STD_LOGIC; + gt0_cplllock_out : out STD_LOGIC; + gt0_cplllockdetclk_in : in STD_LOGIC; + gt0_cpllreset_in : in STD_LOGIC; + gt0_gtrefclk0_in : in STD_LOGIC; + gt0_gtrefclk1_in : in STD_LOGIC; + gt0_drpaddr_in : in STD_LOGIC_VECTOR(8 downto 0); + gt0_drpclk_in : in STD_LOGIC; + gt0_drpdi_in : in STD_LOGIC_VECTOR(15 downto 0); + gt0_drpdo_out : out STD_LOGIC_VECTOR(15 downto 0); + gt0_drpen_in : in STD_LOGIC; + gt0_drprdy_out : out STD_LOGIC; + gt0_drpwe_in : in STD_LOGIC; + gt0_loopback_in : in STD_LOGIC_VECTOR(2 downto 0); + gt0_eyescanreset_in : in STD_LOGIC; + gt0_rxuserrdy_in : in STD_LOGIC; + gt0_eyescandataerror_out : out STD_LOGIC; + gt0_eyescantrigger_in : in STD_LOGIC; + gt0_rxcdrhold_in : in STD_LOGIC; + gt0_rxslide_in : in STD_LOGIC; + gt0_dmonitorout_out : out STD_LOGIC_VECTOR(14 downto 0); + gt0_rxusrclk_in : in STD_LOGIC; + gt0_rxusrclk2_in : in STD_LOGIC; + gt0_rxdata_out : out STD_LOGIC_VECTOR(19 downto 0); + gt0_gthrxn_in : in STD_LOGIC; + gt0_rxmonitorout_out : out STD_LOGIC_VECTOR(6 downto 0); + gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR(1 downto 0); + gt0_rxoutclk_out : out STD_LOGIC; + gt0_rxoutclkfabric_out : out STD_LOGIC; + gt0_gtrxreset_in : in STD_LOGIC; + gt0_rxpolarity_in : in STD_LOGIC; + gt0_gthrxp_in : in STD_LOGIC; + gt0_rxresetdone_out : out STD_LOGIC; + gt0_gttxreset_in : in STD_LOGIC; + gt0_txuserrdy_in : in STD_LOGIC; + gt0_txusrclk_in : in STD_LOGIC; + gt0_txusrclk2_in : in STD_LOGIC; + gt0_txdata_in : in STD_LOGIC_VECTOR(19 downto 0); + gt0_gthtxn_out : out STD_LOGIC; + gt0_gthtxp_out : out STD_LOGIC; + gt0_txoutclk_out : out STD_LOGIC; + gt0_txoutclkfabric_out : out STD_LOGIC; + gt0_txoutclkpcs_out : out STD_LOGIC; + gt0_txresetdone_out : out STD_LOGIC; + gt0_txpolarity_in : in STD_LOGIC; + GT0_QPLLOUTCLK_IN : in STD_LOGIC; + GT0_QPLLOUTREFCLK_IN : in STD_LOGIC + ); +end component gtwizard_CPLL_4p8g_V7; signal tied_to_ground_i : std_logic; signal gt0_cplllock_i : std_logic; -signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); -signal tied_to_vcc_i : std_logic; -signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0); +--signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); +--signal tied_to_vcc_i : std_logic; +--signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0); -signal gt0_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; -signal gt0_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; -signal gt0_drpdo_out : std_logic_vector(15 downto 0); -signal gt0_drpen_in : std_logic:='0'; -signal gt0_drprdy_out : std_logic; -signal gt0_drpwe_in : std_logic:='0'; +constant gt0_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; +constant gt0_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; +constant gt0_drpen_in : std_logic:='0'; +constant gt0_drpwe_in : std_logic:='0'; -signal GT0_QPLLREFCLKLOST_I : std_logic; -signal GT0_QPLLRESET_I : std_logic; -signal GT0_QPLLOUTREFCLK_I : std_logic; +--signal GT0_QPLLREFCLKLOST_I : std_logic; +--signal GT0_QPLLRESET_I : std_logic; +--signal GT0_QPLLOUTREFCLK_I : std_logic; signal gt0_gttxreset_in : std_logic; signal gt0_gtrxreset_in : std_logic; @@ -235,11 +204,7 @@ signal gt0_gtrxreset_in : std_logic; begin tied_to_ground_i <= '0'; - tied_to_ground_vec_i <= x"0000000000000000"; - tied_to_vcc_i <= '1'; - tied_to_vcc_vec_i <= x"ff"; - - + gt0_cplllock_out <= gt0_cplllock_i; @@ -251,91 +216,78 @@ begin gtwizard_CPLL_4p8g_V7_init_i : gtwizard_CPLL_4p8g_V7 port map ( - sysclk_in => DRP_CLK_IN,--sysclk_in_i, - soft_reset_tx_in => SOFT_TXRST_GT,--SOFT_RESET_TX_IN, - soft_reset_rx_in => SOFT_RXRST_GT,--SOFT_RESET_RX_IN, - dont_reset_on_data_error_in => '1',--DONT_RESET_ON_DATA_ERROR_IN, - gt0_tx_fsm_reset_done_out => gt0_tx_fsm_reset_done_out, - gt0_rx_fsm_reset_done_out => gt0_rx_fsm_reset_done_out, - gt0_data_valid_in => '1',--gt0_data_valid_in, - - --_____________________________________________________________________ - --_____________________________________________________________________ - --GT0 (X1Y4) - - gt0_txpolarity_in => gt_txpolarity_in, - gt0_rxpolarity_in => gt_rxpolarity_in, - - - --------------------------------- CPLL Ports ------------------------------- - gt0_cpllfbclklost_out => gt0_cpllfbclklost_out, - gt0_cplllock_out => gt0_cplllock_i, - gt0_cplllockdetclk_in => DRP_CLK_IN,--sysclk_in_i, - gt0_cpllreset_in => gt0_cpllreset_in, + SYSCLK_IN => DRP_CLK_IN, --sysclk_in_i, + SOFT_RESET_TX_IN => SOFT_TXRST_GT, --SOFT_RESET_TX_IN, + SOFT_RESET_RX_IN => SOFT_RXRST_GT, --SOFT_RESET_RX_IN, + DONT_RESET_ON_DATA_ERROR_IN => '1', --DONT_RESET_ON_DATA_ERROR_IN, + GT0_TX_FSM_RESET_DONE_OUT => gt0_tx_fsm_reset_done_out, + GT0_RX_FSM_RESET_DONE_OUT => gt0_rx_fsm_reset_done_out, + GT0_DATA_VALID_IN => '1', --gt0_data_valid_in, + gt0_cpllfbclklost_out => gt0_cpllfbclklost_out, + gt0_cplllock_out => gt0_cplllock_i, + gt0_cplllockdetclk_in => DRP_CLK_IN, --sysclk_in_i, + gt0_cpllreset_in => gt0_cpllreset_in, -------------------------- Channel - Clocking Ports ------------------------ - gt0_gtrefclk0_in => tied_to_ground_i, - gt0_gtrefclk1_in => GTH_RefClk, - ---------------------------- Channel - DRP Ports -------------------------- - - - gt0_drpaddr_in => gt0_drpaddr_in, - gt0_drpclk_in => DRP_CLK_IN, - gt0_drpdi_in => gt0_drpdi_in, - gt0_drpdo_out => gt0_drpdo_out, - gt0_drpen_in => gt0_drpen_in, - gt0_drprdy_out => gt0_drprdy_out, - gt0_drpwe_in => gt0_drpwe_in, + gt0_gtrefclk0_in => tied_to_ground_i, + gt0_gtrefclk1_in => GTH_RefClk, + gt0_drpaddr_in => gt0_drpaddr_in, + gt0_drpclk_in => DRP_CLK_IN, + gt0_drpdi_in => gt0_drpdi_in, + gt0_drpdo_out => open, + gt0_drpen_in => gt0_drpen_in, + gt0_drprdy_out => open, + gt0_drpwe_in => gt0_drpwe_in, + gt0_loopback_in => gt0_loopback_in, --------------------- RX Initialization and Reset Ports -------------------- - gt0_eyescanreset_in => '0', - gt0_rxuserrdy_in => gt0_rxuserrdy_in, + gt0_eyescanreset_in => '0', + gt0_rxuserrdy_in => gt0_rxuserrdy_in, -------------------------- RX Margin Analysis Ports ------------------------ - gt0_eyescandataerror_out => open, - gt0_eyescantrigger_in => '0', + gt0_eyescandataerror_out => open, + gt0_eyescantrigger_in => '0', + gt0_rxcdrhold_in => gt0_rxcdrhold_in, --------------- Receive Ports - Comma Detection and Alignment -------------- - gt0_rxslide_in => gt0_rxslide_in, + gt0_rxslide_in => gt0_rxslide_in, ------------------- Receive Ports - Digital Monitor Ports ------------------ - gt0_dmonitorout_out => open, - + gt0_dmonitorout_out => open, ------------------ Receive Ports - FPGA RX Interface Ports ----------------- - gt0_rxusrclk_in => gt0_rxusrclk_in, - gt0_rxusrclk2_in => gt0_rxusrclk_in, + gt0_rxusrclk_in => gt0_rxusrclk_in, + gt0_rxusrclk2_in => gt0_rxusrclk_in, ------------------ Receive Ports - FPGA RX interface Ports ----------------- - gt0_rxdata_out => gt0_rxdata_out, + gt0_rxdata_out => gt0_rxdata_out, ------------------------ Receive Ports - RX AFE Ports ---------------------- - gt0_gthrxn_in => gt0_gthrxn_in, + gt0_gthrxn_in => gt0_gthrxn_in, --------------------- Receive Ports - RX Equalizer Ports ------------------- - gt0_rxmonitorout_out => open, - gt0_rxmonitorsel_in => "00", ------------- - gt0_rxoutclk_out => gt0_rxoutclk_out, - gt0_rxoutclkfabric_out => open,--gt0_rxoutclkfabric_out, + gt0_rxmonitorout_out => open, + gt0_rxmonitorsel_in => "00", ------------- + gt0_rxoutclk_out => gt0_rxoutclk_out, + gt0_rxoutclkfabric_out => open, --gt0_rxoutclkfabric_out, ------------- Receive Ports - RX Initialization and Reset Ports ------------ - gt0_gtrxreset_in => gt0_gtrxreset_in, + gt0_gtrxreset_in => gt0_gtrxreset_in, + gt0_rxpolarity_in => gt_rxpolarity_in, ------------------------ Receive Ports -RX AFE Ports ----------------------- - gt0_gthrxp_in => gt0_gthrxp_in, + gt0_gthrxp_in => gt0_gthrxp_in, -------------- Receive Ports -RX Initialization and Reset Ports ------------ - gt0_rxresetdone_out => gt0_rxresetdone_out, + gt0_rxresetdone_out => gt0_rxresetdone_out, --------------------- TX Initialization and Reset Ports -------------------- - gt0_gttxreset_in => gt0_gttxreset_in, - gt0_txuserrdy_in => gt0_txuserrdy_in, + gt0_gttxreset_in => gt0_gttxreset_in, + gt0_txuserrdy_in => gt0_txuserrdy_in, ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- - gt0_txusrclk_in => gt0_txusrclk_in, - gt0_txusrclk2_in => gt0_txusrclk_in, + gt0_txusrclk_in => gt0_txusrclk_in, + gt0_txusrclk2_in => gt0_txusrclk_in, ------------------ Transmit Ports - TX Data Path interface ----------------- - gt0_txdata_in => gt0_txdata_in, + gt0_txdata_in => gt0_txdata_in, ---------------- Transmit Ports - TX Driver and OOB signaling -------------- - gt0_gthtxn_out => gt0_gthtxn_out, - gt0_gthtxp_out => gt0_gthtxp_out, + gt0_gthtxn_out => gt0_gthtxn_out, + gt0_gthtxp_out => gt0_gthtxp_out, ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- - gt0_txoutclk_out => gt0_txoutclk_out, - gt0_txoutclkfabric_out => open,-- gt0_txoutclkfabric_out, - gt0_txoutclkpcs_out => open,--gt0_txoutclkpcs_out, + gt0_txoutclk_out => gt0_txoutclk_out, + gt0_txoutclkfabric_out => open, -- gt0_txoutclkfabric_out, + gt0_txoutclkpcs_out => open, --gt0_txoutclkpcs_out, ------------- Transmit Ports - TX Initialization and Reset Ports ----------- - gt0_txresetdone_out => gt0_txresetdone_out, - - gt0_loopback_in => gt0_loopback_in, - gt0_rxcdrhold_in => gt0_rxcdrhold_in, - gt0_qplloutclk_in => '0',--gt0_qplloutclk_in, - gt0_qplloutrefclk_in => '0'--gt0_qplloutrefclk_in + gt0_txresetdone_out => gt0_txresetdone_out, + gt0_txpolarity_in => gt_txpolarity_in, + GT0_QPLLOUTCLK_IN => '0', --gt0_qplloutclk_in, + GT0_QPLLOUTREFCLK_IN => '0' --gt0_qplloutrefclk_in ); diff --git a/sources/GBT/gth_code/qpll4p8g4ch_KCU/GTH_QPLL_Wrapper.vhd b/sources/GBT/gth_code/qpll4p8g4ch_KCU/GTH_QPLL_Wrapper.vhd index dc1a033ea479ae7cb2ee588b0cae8e343ec5c55e..32ac6a05100d4bd826db6fa39624419f1102ef51 100644 --- a/sources/GBT/gth_code/qpll4p8g4ch_KCU/GTH_QPLL_Wrapper.vhd +++ b/sources/GBT/gth_code/qpll4p8g4ch_KCU/GTH_QPLL_Wrapper.vhd @@ -96,54 +96,55 @@ end GTH_QPLL_Wrapper; architecture Behavioral of GTH_QPLL_Wrapper is - component KCU_RXBUF_PMA_QPLL_4CH is - port( - gtwiz_userclk_tx_active_in : in std_logic_vector(0 downto 0); - gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_reset_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_start_user_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_error_out : out std_logic_vector(0 downto 0); - gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); - gtwiz_reset_all_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); - gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); - gtwiz_userdata_tx_in : in std_logic_vector(79 downto 0); - gtwiz_userdata_rx_out : out std_logic_vector(79 downto 0); - gtrefclk01_in : in std_logic_vector(0 downto 0); - qpll1outclk_out : out std_logic_vector(0 downto 0); - qpll1outrefclk_out : out std_logic_vector(0 downto 0); - loopback_in : in std_logic_vector(11 downto 0); - gthrxn_in : in std_logic_vector(3 downto 0); - gthrxp_in : in std_logic_vector(3 downto 0); - rxcdrhold_in : in std_logic_vector(3 downto 0); - rxpolarity_in : in std_logic_vector(3 downto 0); - rxusrclk_in : in std_logic_vector(3 downto 0); - rxusrclk2_in : in std_logic_vector(3 downto 0); - txpolarity_in : in std_logic_vector(3 downto 0); - txusrclk_in : in std_logic_vector(3 downto 0); - qpll1lock_out : out std_logic_vector(0 downto 0); - qpll1fbclklost_out : out std_logic_vector(0 downto 0); - qpll0fbclklost_out : out std_logic_vector(0 downto 0); - qpll0lock_out : out std_logic_vector(0 downto 0); - txusrclk2_in : in std_logic_vector(3 downto 0); - gthtxn_out : out std_logic_vector(3 downto 0); - gthtxp_out : out std_logic_vector(3 downto 0); - rxslide_in : in std_logic_vector(3 downto 0); - rxcdrlock_out : out std_logic_vector(3 downto 0); - rxoutclk_out : out std_logic_vector(3 downto 0); - rxpmaresetdone_out : out std_logic_vector(3 downto 0); - txoutclk_out : out std_logic_vector(3 downto 0); - txresetdone_out : out std_logic_vector(3 downto 0); - rxresetdone_out : out std_logic_vector(3 downto 0); - txpmaresetdone_out : out std_logic_vector(3 downto 0) + component KCU_RXBUF_PMA_QPLL_4CH + port( + gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_all_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR(79 downto 0); + gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR(79 downto 0); + gtrefclk01_in : in STD_LOGIC_VECTOR(0 to 0); + qpll0fbclklost_out : out STD_LOGIC_VECTOR(0 to 0); + qpll0lock_out : out STD_LOGIC_VECTOR(0 to 0); + qpll1fbclklost_out : out STD_LOGIC_VECTOR(0 to 0); + qpll1lock_out : out STD_LOGIC_VECTOR(0 to 0); + qpll1outclk_out : out STD_LOGIC_VECTOR(0 to 0); + qpll1outrefclk_out : out STD_LOGIC_VECTOR(0 to 0); + gthrxn_in : in STD_LOGIC_VECTOR(3 downto 0); + gthrxp_in : in STD_LOGIC_VECTOR(3 downto 0); + loopback_in : in STD_LOGIC_VECTOR(11 downto 0); + rxcdrhold_in : in STD_LOGIC_VECTOR(3 downto 0); + rxpolarity_in : in STD_LOGIC_VECTOR(3 downto 0); + rxslide_in : in STD_LOGIC_VECTOR(3 downto 0); + rxusrclk_in : in STD_LOGIC_VECTOR(3 downto 0); + rxusrclk2_in : in STD_LOGIC_VECTOR(3 downto 0); + txpolarity_in : in STD_LOGIC_VECTOR(3 downto 0); + txusrclk_in : in STD_LOGIC_VECTOR(3 downto 0); + txusrclk2_in : in STD_LOGIC_VECTOR(3 downto 0); + gthtxn_out : out STD_LOGIC_VECTOR(3 downto 0); + gthtxp_out : out STD_LOGIC_VECTOR(3 downto 0); + gtpowergood_out : out STD_LOGIC_VECTOR(3 downto 0); + rxcdrlock_out : out STD_LOGIC_VECTOR(3 downto 0); + rxoutclk_out : out STD_LOGIC_VECTOR(3 downto 0); + rxpmaresetdone_out : out STD_LOGIC_VECTOR(3 downto 0); + rxresetdone_out : out STD_LOGIC_VECTOR(3 downto 0); + txoutclk_out : out STD_LOGIC_VECTOR(3 downto 0); + txpmaresetdone_out : out STD_LOGIC_VECTOR(3 downto 0); + txresetdone_out : out STD_LOGIC_VECTOR(3 downto 0) ); - end component; + end component KCU_RXBUF_PMA_QPLL_4CH; signal rxusrclk : std_logic_vector(3 downto 0); @@ -158,16 +159,12 @@ architecture Behavioral of GTH_QPLL_Wrapper is signal userclk_rx_active_out_p: std_logic_vector(0 downto 0); signal userclk_tx_active_out_p: std_logic_vector(0 downto 0); signal txusrclk : std_logic; - signal vccvec : std_logic_vector(0 downto 0); - signal gndvec : std_logic_vector(0 downto 0); signal loopback_in_s : std_logic_vector(11 downto 0); signal rxcdrhold_in_s : std_logic_vector(3 downto 0); begin - vccvec(0) <= '1'; - gndvec(0) <= '0'; -- RxUsrClk rxusrclk <= gt_rxusrclk_in; rxusrclk_int <= rxusrclk; @@ -224,54 +221,51 @@ begin gtwizard_ultrascale_four_channel_qpll_inst: KCU_RXBUF_PMA_QPLL_4CH port map( - gtwiz_userclk_tx_active_in => userclk_tx_active_out, - gtwiz_userclk_rx_active_in => userclk_rx_active_out, - gtwiz_buffbypass_tx_reset_in => gndvec, - gtwiz_buffbypass_tx_start_user_in => gndvec, - gtwiz_buffbypass_tx_done_out => open, - gtwiz_buffbypass_tx_error_out => open, - - gtwiz_reset_clk_freerun_in => drpclk_in, - gtwiz_reset_all_in => reset_all_in, - - gtwiz_reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath_in, - gtwiz_reset_tx_datapath_in => reset_tx_datapath_in, - gtwiz_reset_rx_pll_and_datapath_in => reset_rx_pll_and_datapath_in, - gtwiz_reset_rx_datapath_in => reset_rx_datapath_in, - - gtwiz_reset_rx_cdr_stable_out => reset_rx_cdr_stable_out, - gtwiz_reset_tx_done_out => reset_tx_done_out, - gtwiz_reset_rx_done_out => reset_rx_done_out, - - qpll1lock_out => qpll1lock_out, - qpll0lock_out => qpll0lock_out, - qpll1fbclklost_out => qpll1fbclklost_out, - qpll0fbclklost_out => qpll0fbclklost_out, - gtwiz_userdata_tx_in => userdata_tx_in, - gtwiz_userdata_rx_out => userdata_rx_out, - gtrefclk01_in => gtrefclk0_in, - loopback_in => loopback_in_s, - qpll1outclk_out => open, - qpll1outrefclk_out => open, - gthrxn_in => gthrxn_in, - gthrxp_in => gthrxp_in, - rxcdrhold_in => rxcdrhold_in_s, - rxpolarity_in => rxpolarity_in, - rxusrclk_in => rxusrclk_int, - rxusrclk2_in => rxusrclk2_int, - txpolarity_in => txpolarity_in, - txusrclk_in => txusrclk_int, - txusrclk2_in => txusrclk2_int, - gthtxn_out => gthtxn_out, - gthtxp_out => gthtxp_out, - rxcdrlock_out => rxcdrlock_out, - rxoutclk_out => rxoutclk_int, - rxpmaresetdone_out => rxpmaresetdone_out, - rxslide_in => rxslide_in, - txoutclk_out => txoutclk_int, - txpmaresetdone_out => txpmaresetdone_out, - txresetdone_out => txresetdone_out, - rxresetdone_out => rxresetdone_out + gtwiz_userclk_tx_active_in => userclk_tx_active_out, + gtwiz_userclk_rx_active_in => userclk_rx_active_out, + gtwiz_buffbypass_tx_reset_in => "0", + gtwiz_buffbypass_tx_start_user_in => "0", + gtwiz_buffbypass_tx_done_out => open, + gtwiz_buffbypass_tx_error_out => open, + gtwiz_reset_clk_freerun_in => drpclk_in, + gtwiz_reset_all_in => reset_all_in, + gtwiz_reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath_in, + gtwiz_reset_tx_datapath_in => reset_tx_datapath_in, + gtwiz_reset_rx_pll_and_datapath_in => reset_rx_pll_and_datapath_in, + gtwiz_reset_rx_datapath_in => reset_rx_datapath_in, + gtwiz_reset_rx_cdr_stable_out => reset_rx_cdr_stable_out, + gtwiz_reset_tx_done_out => reset_tx_done_out, + gtwiz_reset_rx_done_out => reset_rx_done_out, + gtwiz_userdata_tx_in => userdata_tx_in, + gtwiz_userdata_rx_out => userdata_rx_out, + gtrefclk01_in => gtrefclk0_in, + qpll0fbclklost_out => qpll0fbclklost_out, + qpll0lock_out => qpll0lock_out, + qpll1fbclklost_out => qpll1fbclklost_out, + qpll1lock_out => qpll1lock_out, + qpll1outclk_out => open, + qpll1outrefclk_out => open, + gthrxn_in => gthrxn_in, + gthrxp_in => gthrxp_in, + loopback_in => loopback_in_s, + rxcdrhold_in => rxcdrhold_in_s, + rxpolarity_in => rxpolarity_in, + rxslide_in => rxslide_in, + rxusrclk_in => rxusrclk_int, + rxusrclk2_in => rxusrclk2_int, + txpolarity_in => txpolarity_in, + txusrclk_in => txusrclk_int, + txusrclk2_in => txusrclk2_int, + gthtxn_out => gthtxn_out, + gthtxp_out => gthtxp_out, + gtpowergood_out => open, + rxcdrlock_out => rxcdrlock_out, + rxoutclk_out => rxoutclk_int, + rxpmaresetdone_out => rxpmaresetdone_out, + rxresetdone_out => rxresetdone_out, + txoutclk_out => txoutclk_int, + txpmaresetdone_out => txpmaresetdone_out, + txresetdone_out => txresetdone_out ); --end generate; diff --git a/sources/GBT/gth_code/qpll4p8g4ch_V7/GTH_QPLL_Wrapper_V7.vhd b/sources/GBT/gth_code/qpll4p8g4ch_V7/GTH_QPLL_Wrapper_V7.vhd index d9ca339b19dc9e48554e7a777cdca822707a785b..c7d523af7015fc003026a2f97e4d02056ac6d55c 100644 --- a/sources/GBT/gth_code/qpll4p8g4ch_V7/GTH_QPLL_Wrapper_V7.vhd +++ b/sources/GBT/gth_code/qpll4p8g4ch_V7/GTH_QPLL_Wrapper_V7.vhd @@ -60,13 +60,13 @@ entity GTH_QPLL_Wrapper_V7 is gt0_txusrclk_in : in std_logic; gt0_txoutclk_out : out std_logic; - gt1_txusrclk_in : in std_logic; + --gt1_txusrclk_in : in std_logic; gt1_txoutclk_out : out std_logic; - gt2_txusrclk_in : in std_logic; + --gt2_txusrclk_in : in std_logic; gt2_txoutclk_out : out std_logic; - gt3_txusrclk_in : in std_logic; + --gt3_txusrclk_in : in std_logic; gt3_txoutclk_out : out std_logic; ----------------------------------------- ---- STATUS signals @@ -104,14 +104,14 @@ entity GTH_QPLL_Wrapper_V7 is ----------RESET SIGNALs ---------------------------------------------------------------- - SOFT_RESET_IN : in std_logic; + --SOFT_RESET_IN : in std_logic; GTTX_RESET_IN : in std_logic_vector(3 downto 0); GTRX_RESET_IN : in std_logic_vector(3 downto 0); - CPLL_RESET_IN : in std_logic_vector(3 downto 0); + --CPLL_RESET_IN : in std_logic_vector(3 downto 0); QPLL_RESET_IN : in std_logic; - SOFT_TXRST_GT : in std_logic_vector(3 downto 0); - SOFT_RXRST_GT : in std_logic_vector(3 downto 0); + --SOFT_TXRST_GT : in std_logic_vector(3 downto 0); + --SOFT_RXRST_GT : in std_logic_vector(3 downto 0); SOFT_TXRST_ALL : in std_logic; SOFT_RXRST_ALL : in std_logic; @@ -150,286 +150,190 @@ architecture RTL of GTH_QPLL_Wrapper_V7 is component gtwizard_QPLL_4p8g_V7 - -port -( - SYSCLK_IN : in std_logic; - SOFT_RESET_TX_IN : in std_logic; - SOFT_RESET_RX_IN : in std_logic; - DONT_RESET_ON_DATA_ERROR_IN : in std_logic; - GT0_DRP_BUSY_OUT : out std_logic; - GT0_TX_FSM_RESET_DONE_OUT : out std_logic; - GT0_RX_FSM_RESET_DONE_OUT : out std_logic; - GT0_DATA_VALID_IN : in std_logic; - GT1_DRP_BUSY_OUT : out std_logic; - GT1_TX_FSM_RESET_DONE_OUT : out std_logic; - GT1_RX_FSM_RESET_DONE_OUT : out std_logic; - GT1_DATA_VALID_IN : in std_logic; - GT2_DRP_BUSY_OUT : out std_logic; - GT2_TX_FSM_RESET_DONE_OUT : out std_logic; - GT2_RX_FSM_RESET_DONE_OUT : out std_logic; - GT2_DATA_VALID_IN : in std_logic; - GT3_DRP_BUSY_OUT : out std_logic; - GT3_TX_FSM_RESET_DONE_OUT : out std_logic; - GT3_RX_FSM_RESET_DONE_OUT : out std_logic; - GT3_DATA_VALID_IN : in std_logic; - - --_________________________________________________________________________ - --GT0 (X1Y4) - --____________________________CHANNEL PORTS________________________________ - ---------------------------- Channel - DRP Ports -------------------------- - gt0_drpaddr_in : in std_logic_vector(8 downto 0); - gt0_drpclk_in : in std_logic; - gt0_drpdi_in : in std_logic_vector(15 downto 0); - gt0_drpdo_out : out std_logic_vector(15 downto 0); - gt0_drpen_in : in std_logic; - gt0_drprdy_out : out std_logic; - gt0_drpwe_in : in std_logic; - --------------------- RX Initialization and Reset Ports -------------------- - gt0_eyescanreset_in : in std_logic; - gt0_rxuserrdy_in : in std_logic; - -------------------------- RX Margin Analysis Ports ------------------------ - gt0_eyescandataerror_out : out std_logic; - gt0_eyescantrigger_in : in std_logic; - --------------- Receive Ports - Comma Detection and Alignment -------------- - gt0_rxslide_in : in std_logic; - ------------------- Receive Ports - Digital Monitor Ports ------------------ - gt0_dmonitorout_out : out std_logic_vector(14 downto 0); - ------------------ Receive Ports - FPGA RX Interface Ports ----------------- - gt0_rxusrclk_in : in std_logic; - gt0_rxusrclk2_in : in std_logic; - ------------------ Receive Ports - FPGA RX interface Ports ----------------- - gt0_rxdata_out : out std_logic_vector(19 downto 0); - ------------------------ Receive Ports - RX AFE Ports ---------------------- - gt0_gthrxn_in : in std_logic; - --------------------- Receive Ports - RX Equalizer Ports ------------------- - gt0_rxmonitorout_out : out std_logic_vector(6 downto 0); - gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0); - --------------- Receive Ports - RX Fabric Output Control Ports ------------- - gt0_rxoutclk_out : out std_logic; - gt0_rxoutclkfabric_out : out std_logic; - ------------- Receive Ports - RX Initialization and Reset Ports ------------ - gt0_gtrxreset_in : in std_logic; - ------------------------ Receive Ports -RX AFE Ports ----------------------- - gt0_gthrxp_in : in std_logic; - -------------- Receive Ports -RX Initialization and Reset Ports ------------ - gt0_rxresetdone_out : out std_logic; - --------------------- TX Initialization and Reset Ports -------------------- - gt0_gttxreset_in : in std_logic; - gt0_txuserrdy_in : in std_logic; - ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- - gt0_txusrclk_in : in std_logic; - gt0_txusrclk2_in : in std_logic; - ------------------ Transmit Ports - TX Data Path interface ----------------- - gt0_txdata_in : in std_logic_vector(19 downto 0); - ---------------- Transmit Ports - TX Driver and OOB signaling -------------- - gt0_gthtxn_out : out std_logic; - gt0_gthtxp_out : out std_logic; - ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- - gt0_txoutclk_out : out std_logic; - gt0_txoutclkfabric_out : out std_logic; - gt0_txoutclkpcs_out : out std_logic; - ------------- Transmit Ports - TX Initialization and Reset Ports ----------- - gt0_txresetdone_out : out std_logic; - - --GT1 (X1Y5) - --____________________________CHANNEL PORTS________________________________ - ---------------------------- Channel - DRP Ports -------------------------- - gt1_drpaddr_in : in std_logic_vector(8 downto 0); - gt1_drpclk_in : in std_logic; - gt1_drpdi_in : in std_logic_vector(15 downto 0); - gt1_drpdo_out : out std_logic_vector(15 downto 0); - gt1_drpen_in : in std_logic; - gt1_drprdy_out : out std_logic; - gt1_drpwe_in : in std_logic; - --------------------- RX Initialization and Reset Ports -------------------- - gt1_eyescanreset_in : in std_logic; - gt1_rxuserrdy_in : in std_logic; - -------------------------- RX Margin Analysis Ports ------------------------ - gt1_eyescandataerror_out : out std_logic; - gt1_eyescantrigger_in : in std_logic; - --------------- Receive Ports - Comma Detection and Alignment -------------- - gt1_rxslide_in : in std_logic; - ------------------- Receive Ports - Digital Monitor Ports ------------------ - gt1_dmonitorout_out : out std_logic_vector(14 downto 0); - ------------------ Receive Ports - FPGA RX Interface Ports ----------------- - gt1_rxusrclk_in : in std_logic; - gt1_rxusrclk2_in : in std_logic; - ------------------ Receive Ports - FPGA RX interface Ports ----------------- - gt1_rxdata_out : out std_logic_vector(19 downto 0); - ------------------------ Receive Ports - RX AFE Ports ---------------------- - gt1_gthrxn_in : in std_logic; - --------------------- Receive Ports - RX Equalizer Ports ------------------- - gt1_rxmonitorout_out : out std_logic_vector(6 downto 0); - gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0); - --------------- Receive Ports - RX Fabric Output Control Ports ------------- - gt1_rxoutclk_out : out std_logic; - gt1_rxoutclkfabric_out : out std_logic; - ------------- Receive Ports - RX Initialization and Reset Ports ------------ - gt1_gtrxreset_in : in std_logic; - ------------------------ Receive Ports -RX AFE Ports ----------------------- - gt1_gthrxp_in : in std_logic; - -------------- Receive Ports -RX Initialization and Reset Ports ------------ - gt1_rxresetdone_out : out std_logic; - --------------------- TX Initialization and Reset Ports -------------------- - gt1_gttxreset_in : in std_logic; - gt1_txuserrdy_in : in std_logic; - ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- - gt1_txusrclk_in : in std_logic; - gt1_txusrclk2_in : in std_logic; - ------------------ Transmit Ports - TX Data Path interface ----------------- - gt1_txdata_in : in std_logic_vector(19 downto 0); - ---------------- Transmit Ports - TX Driver and OOB signaling -------------- - gt1_gthtxn_out : out std_logic; - gt1_gthtxp_out : out std_logic; - ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- - gt1_txoutclk_out : out std_logic; - gt1_txoutclkfabric_out : out std_logic; - gt1_txoutclkpcs_out : out std_logic; - ------------- Transmit Ports - TX Initialization and Reset Ports ----------- - gt1_txresetdone_out : out std_logic; - - --GT2 (X1Y6) - --____________________________CHANNEL PORTS________________________________ - ---------------------------- Channel - DRP Ports -------------------------- - gt2_drpaddr_in : in std_logic_vector(8 downto 0); - gt2_drpclk_in : in std_logic; - gt2_drpdi_in : in std_logic_vector(15 downto 0); - gt2_drpdo_out : out std_logic_vector(15 downto 0); - gt2_drpen_in : in std_logic; - gt2_drprdy_out : out std_logic; - gt2_drpwe_in : in std_logic; - --------------------- RX Initialization and Reset Ports -------------------- - gt2_eyescanreset_in : in std_logic; - gt2_rxuserrdy_in : in std_logic; - -------------------------- RX Margin Analysis Ports ------------------------ - gt2_eyescandataerror_out : out std_logic; - gt2_eyescantrigger_in : in std_logic; - --------------- Receive Ports - Comma Detection and Alignment -------------- - gt2_rxslide_in : in std_logic; - ------------------- Receive Ports - Digital Monitor Ports ------------------ - gt2_dmonitorout_out : out std_logic_vector(14 downto 0); - ------------------ Receive Ports - FPGA RX Interface Ports ----------------- - gt2_rxusrclk_in : in std_logic; - gt2_rxusrclk2_in : in std_logic; - ------------------ Receive Ports - FPGA RX interface Ports ----------------- - gt2_rxdata_out : out std_logic_vector(19 downto 0); - ------------------------ Receive Ports - RX AFE Ports ---------------------- - gt2_gthrxn_in : in std_logic; - --------------------- Receive Ports - RX Equalizer Ports ------------------- - gt2_rxmonitorout_out : out std_logic_vector(6 downto 0); - gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0); - --------------- Receive Ports - RX Fabric Output Control Ports ------------- - gt2_rxoutclk_out : out std_logic; - gt2_rxoutclkfabric_out : out std_logic; - ------------- Receive Ports - RX Initialization and Reset Ports ------------ - gt2_gtrxreset_in : in std_logic; - ------------------------ Receive Ports -RX AFE Ports ----------------------- - gt2_gthrxp_in : in std_logic; - -------------- Receive Ports -RX Initialization and Reset Ports ------------ - gt2_rxresetdone_out : out std_logic; - --------------------- TX Initialization and Reset Ports -------------------- - gt2_gttxreset_in : in std_logic; - gt2_txuserrdy_in : in std_logic; - ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- - gt2_txusrclk_in : in std_logic; - gt2_txusrclk2_in : in std_logic; - ------------------ Transmit Ports - TX Data Path interface ----------------- - gt2_txdata_in : in std_logic_vector(19 downto 0); - ---------------- Transmit Ports - TX Driver and OOB signaling -------------- - gt2_gthtxn_out : out std_logic; - gt2_gthtxp_out : out std_logic; - ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- - gt2_txoutclk_out : out std_logic; - gt2_txoutclkfabric_out : out std_logic; - gt2_txoutclkpcs_out : out std_logic; - ------------- Transmit Ports - TX Initialization and Reset Ports ----------- - gt2_txresetdone_out : out std_logic; - - --GT3 (X1Y7) - --____________________________CHANNEL PORTS________________________________ - ---------------------------- Channel - DRP Ports -------------------------- - gt3_drpaddr_in : in std_logic_vector(8 downto 0); - gt3_drpclk_in : in std_logic; - gt3_drpdi_in : in std_logic_vector(15 downto 0); - gt3_drpdo_out : out std_logic_vector(15 downto 0); - gt3_drpen_in : in std_logic; - gt3_drprdy_out : out std_logic; - gt3_drpwe_in : in std_logic; - --------------------- RX Initialization and Reset Ports -------------------- - gt3_eyescanreset_in : in std_logic; - gt3_rxuserrdy_in : in std_logic; - -------------------------- RX Margin Analysis Ports ------------------------ - gt3_eyescandataerror_out : out std_logic; - gt3_eyescantrigger_in : in std_logic; - --------------- Receive Ports - Comma Detection and Alignment -------------- - gt3_rxslide_in : in std_logic; - ------------------- Receive Ports - Digital Monitor Ports ------------------ - gt3_dmonitorout_out : out std_logic_vector(14 downto 0); - ------------------ Receive Ports - FPGA RX Interface Ports ----------------- - gt3_rxusrclk_in : in std_logic; - gt3_rxusrclk2_in : in std_logic; - ------------------ Receive Ports - FPGA RX interface Ports ----------------- - gt3_rxdata_out : out std_logic_vector(19 downto 0); - ------------------------ Receive Ports - RX AFE Ports ---------------------- - gt3_gthrxn_in : in std_logic; - --------------------- Receive Ports - RX Equalizer Ports ------------------- - gt3_rxmonitorout_out : out std_logic_vector(6 downto 0); - gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0); - --------------- Receive Ports - RX Fabric Output Control Ports ------------- - gt3_rxoutclk_out : out std_logic; - gt3_rxoutclkfabric_out : out std_logic; - ------------- Receive Ports - RX Initialization and Reset Ports ------------ - gt3_gtrxreset_in : in std_logic; - ------------------------ Receive Ports -RX AFE Ports ----------------------- - gt3_gthrxp_in : in std_logic; - -------------- Receive Ports -RX Initialization and Reset Ports ------------ - gt3_rxresetdone_out : out std_logic; - --------------------- TX Initialization and Reset Ports -------------------- - gt3_gttxreset_in : in std_logic; - gt3_txuserrdy_in : in std_logic; - ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- - gt3_txusrclk_in : in std_logic; - gt3_txusrclk2_in : in std_logic; - ------------------ Transmit Ports - TX Data Path interface ----------------- - gt3_txdata_in : in std_logic_vector(19 downto 0); - ---------------- Transmit Ports - TX Driver and OOB signaling -------------- - gt3_gthtxn_out : out std_logic; - gt3_gthtxp_out : out std_logic; - ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- - gt3_txoutclk_out : out std_logic; - gt3_txoutclkfabric_out : out std_logic; - gt3_txoutclkpcs_out : out std_logic; - ------------- Transmit Ports - TX Initialization and Reset Ports ----------- - gt3_txresetdone_out : out std_logic; - gt3_txpolarity_in : in std_logic; - gt2_txpolarity_in : in std_logic; - gt1_txpolarity_in : in std_logic; - gt0_txpolarity_in : in std_logic; - gt3_rxpolarity_in : in std_logic; - gt2_rxpolarity_in : in std_logic; - gt1_rxpolarity_in : in std_logic; - gt0_rxpolarity_in : in std_logic; - - gt0_loopback_in : in std_logic_vector(2 downto 0); - gt0_rxcdrhold_in : in std_logic; - gt1_loopback_in : in std_logic_vector(2 downto 0); - gt1_rxcdrhold_in : in std_logic; - gt2_loopback_in : in std_logic_vector(2 downto 0); - gt2_rxcdrhold_in : in std_logic; - gt3_loopback_in : in std_logic_vector(2 downto 0); - gt3_rxcdrhold_in : in std_logic; - - --____________________________COMMON PORTS________________________________ - GT0_QPLLLOCK_IN : in std_logic; - GT0_QPLLREFCLKLOST_IN : in std_logic; - GT0_QPLLRESET_OUT : out std_logic; - GT0_QPLLOUTCLK_IN : in std_logic; - GT0_QPLLOUTREFCLK_IN : in std_logic - -); - -end component; + port( + SYSCLK_IN : in STD_LOGIC; + SOFT_RESET_TX_IN : in STD_LOGIC; + SOFT_RESET_RX_IN : in STD_LOGIC; + DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC; + GT0_DRP_BUSY_OUT : out STD_LOGIC; + GT0_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; + GT0_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; + GT0_DATA_VALID_IN : in STD_LOGIC; + GT1_DRP_BUSY_OUT : out STD_LOGIC; + GT1_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; + GT1_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; + GT1_DATA_VALID_IN : in STD_LOGIC; + GT2_DRP_BUSY_OUT : out STD_LOGIC; + GT2_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; + GT2_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; + GT2_DATA_VALID_IN : in STD_LOGIC; + GT3_DRP_BUSY_OUT : out STD_LOGIC; + GT3_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; + GT3_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; + GT3_DATA_VALID_IN : in STD_LOGIC; + gt0_drpaddr_in : in STD_LOGIC_VECTOR(8 downto 0); + gt0_drpclk_in : in STD_LOGIC; + gt0_drpdi_in : in STD_LOGIC_VECTOR(15 downto 0); + gt0_drpdo_out : out STD_LOGIC_VECTOR(15 downto 0); + gt0_drpen_in : in STD_LOGIC; + gt0_drprdy_out : out STD_LOGIC; + gt0_drpwe_in : in STD_LOGIC; + gt0_loopback_in : in STD_LOGIC_VECTOR(2 downto 0); + gt0_eyescanreset_in : in STD_LOGIC; + gt0_rxuserrdy_in : in STD_LOGIC; + gt0_eyescandataerror_out : out STD_LOGIC; + gt0_eyescantrigger_in : in STD_LOGIC; + gt0_rxcdrhold_in : in STD_LOGIC; + gt0_rxslide_in : in STD_LOGIC; + gt0_dmonitorout_out : out STD_LOGIC_VECTOR(14 downto 0); + gt0_rxusrclk_in : in STD_LOGIC; + gt0_rxusrclk2_in : in STD_LOGIC; + gt0_rxdata_out : out STD_LOGIC_VECTOR(19 downto 0); + gt0_gthrxn_in : in STD_LOGIC; + gt0_rxmonitorout_out : out STD_LOGIC_VECTOR(6 downto 0); + gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR(1 downto 0); + gt0_rxoutclk_out : out STD_LOGIC; + gt0_rxoutclkfabric_out : out STD_LOGIC; + gt0_gtrxreset_in : in STD_LOGIC; + gt0_rxpolarity_in : in STD_LOGIC; + gt0_gthrxp_in : in STD_LOGIC; + gt0_rxresetdone_out : out STD_LOGIC; + gt0_gttxreset_in : in STD_LOGIC; + gt0_txuserrdy_in : in STD_LOGIC; + gt0_txusrclk_in : in STD_LOGIC; + gt0_txusrclk2_in : in STD_LOGIC; + gt0_txdata_in : in STD_LOGIC_VECTOR(19 downto 0); + gt0_gthtxn_out : out STD_LOGIC; + gt0_gthtxp_out : out STD_LOGIC; + gt0_txoutclk_out : out STD_LOGIC; + gt0_txoutclkfabric_out : out STD_LOGIC; + gt0_txoutclkpcs_out : out STD_LOGIC; + gt0_txresetdone_out : out STD_LOGIC; + gt0_txpolarity_in : in STD_LOGIC; + gt1_drpaddr_in : in STD_LOGIC_VECTOR(8 downto 0); + gt1_drpclk_in : in STD_LOGIC; + gt1_drpdi_in : in STD_LOGIC_VECTOR(15 downto 0); + gt1_drpdo_out : out STD_LOGIC_VECTOR(15 downto 0); + gt1_drpen_in : in STD_LOGIC; + gt1_drprdy_out : out STD_LOGIC; + gt1_drpwe_in : in STD_LOGIC; + gt1_loopback_in : in STD_LOGIC_VECTOR(2 downto 0); + gt1_eyescanreset_in : in STD_LOGIC; + gt1_rxuserrdy_in : in STD_LOGIC; + gt1_eyescandataerror_out : out STD_LOGIC; + gt1_eyescantrigger_in : in STD_LOGIC; + gt1_rxcdrhold_in : in STD_LOGIC; + gt1_rxslide_in : in STD_LOGIC; + gt1_dmonitorout_out : out STD_LOGIC_VECTOR(14 downto 0); + gt1_rxusrclk_in : in STD_LOGIC; + gt1_rxusrclk2_in : in STD_LOGIC; + gt1_rxdata_out : out STD_LOGIC_VECTOR(19 downto 0); + gt1_gthrxn_in : in STD_LOGIC; + gt1_rxmonitorout_out : out STD_LOGIC_VECTOR(6 downto 0); + gt1_rxmonitorsel_in : in STD_LOGIC_VECTOR(1 downto 0); + gt1_rxoutclk_out : out STD_LOGIC; + gt1_rxoutclkfabric_out : out STD_LOGIC; + gt1_gtrxreset_in : in STD_LOGIC; + gt1_rxpolarity_in : in STD_LOGIC; + gt1_gthrxp_in : in STD_LOGIC; + gt1_rxresetdone_out : out STD_LOGIC; + gt1_gttxreset_in : in STD_LOGIC; + gt1_txuserrdy_in : in STD_LOGIC; + gt1_txusrclk_in : in STD_LOGIC; + gt1_txusrclk2_in : in STD_LOGIC; + gt1_txdata_in : in STD_LOGIC_VECTOR(19 downto 0); + gt1_gthtxn_out : out STD_LOGIC; + gt1_gthtxp_out : out STD_LOGIC; + gt1_txoutclk_out : out STD_LOGIC; + gt1_txoutclkfabric_out : out STD_LOGIC; + gt1_txoutclkpcs_out : out STD_LOGIC; + gt1_txresetdone_out : out STD_LOGIC; + gt1_txpolarity_in : in STD_LOGIC; + gt2_drpaddr_in : in STD_LOGIC_VECTOR(8 downto 0); + gt2_drpclk_in : in STD_LOGIC; + gt2_drpdi_in : in STD_LOGIC_VECTOR(15 downto 0); + gt2_drpdo_out : out STD_LOGIC_VECTOR(15 downto 0); + gt2_drpen_in : in STD_LOGIC; + gt2_drprdy_out : out STD_LOGIC; + gt2_drpwe_in : in STD_LOGIC; + gt2_loopback_in : in STD_LOGIC_VECTOR(2 downto 0); + gt2_eyescanreset_in : in STD_LOGIC; + gt2_rxuserrdy_in : in STD_LOGIC; + gt2_eyescandataerror_out : out STD_LOGIC; + gt2_eyescantrigger_in : in STD_LOGIC; + gt2_rxcdrhold_in : in STD_LOGIC; + gt2_rxslide_in : in STD_LOGIC; + gt2_dmonitorout_out : out STD_LOGIC_VECTOR(14 downto 0); + gt2_rxusrclk_in : in STD_LOGIC; + gt2_rxusrclk2_in : in STD_LOGIC; + gt2_rxdata_out : out STD_LOGIC_VECTOR(19 downto 0); + gt2_gthrxn_in : in STD_LOGIC; + gt2_rxmonitorout_out : out STD_LOGIC_VECTOR(6 downto 0); + gt2_rxmonitorsel_in : in STD_LOGIC_VECTOR(1 downto 0); + gt2_rxoutclk_out : out STD_LOGIC; + gt2_rxoutclkfabric_out : out STD_LOGIC; + gt2_gtrxreset_in : in STD_LOGIC; + gt2_rxpolarity_in : in STD_LOGIC; + gt2_gthrxp_in : in STD_LOGIC; + gt2_rxresetdone_out : out STD_LOGIC; + gt2_gttxreset_in : in STD_LOGIC; + gt2_txuserrdy_in : in STD_LOGIC; + gt2_txusrclk_in : in STD_LOGIC; + gt2_txusrclk2_in : in STD_LOGIC; + gt2_txdata_in : in STD_LOGIC_VECTOR(19 downto 0); + gt2_gthtxn_out : out STD_LOGIC; + gt2_gthtxp_out : out STD_LOGIC; + gt2_txoutclk_out : out STD_LOGIC; + gt2_txoutclkfabric_out : out STD_LOGIC; + gt2_txoutclkpcs_out : out STD_LOGIC; + gt2_txresetdone_out : out STD_LOGIC; + gt2_txpolarity_in : in STD_LOGIC; + gt3_drpaddr_in : in STD_LOGIC_VECTOR(8 downto 0); + gt3_drpclk_in : in STD_LOGIC; + gt3_drpdi_in : in STD_LOGIC_VECTOR(15 downto 0); + gt3_drpdo_out : out STD_LOGIC_VECTOR(15 downto 0); + gt3_drpen_in : in STD_LOGIC; + gt3_drprdy_out : out STD_LOGIC; + gt3_drpwe_in : in STD_LOGIC; + gt3_loopback_in : in STD_LOGIC_VECTOR(2 downto 0); + gt3_eyescanreset_in : in STD_LOGIC; + gt3_rxuserrdy_in : in STD_LOGIC; + gt3_eyescandataerror_out : out STD_LOGIC; + gt3_eyescantrigger_in : in STD_LOGIC; + gt3_rxcdrhold_in : in STD_LOGIC; + gt3_rxslide_in : in STD_LOGIC; + gt3_dmonitorout_out : out STD_LOGIC_VECTOR(14 downto 0); + gt3_rxusrclk_in : in STD_LOGIC; + gt3_rxusrclk2_in : in STD_LOGIC; + gt3_rxdata_out : out STD_LOGIC_VECTOR(19 downto 0); + gt3_gthrxn_in : in STD_LOGIC; + gt3_rxmonitorout_out : out STD_LOGIC_VECTOR(6 downto 0); + gt3_rxmonitorsel_in : in STD_LOGIC_VECTOR(1 downto 0); + gt3_rxoutclk_out : out STD_LOGIC; + gt3_rxoutclkfabric_out : out STD_LOGIC; + gt3_gtrxreset_in : in STD_LOGIC; + gt3_rxpolarity_in : in STD_LOGIC; + gt3_gthrxp_in : in STD_LOGIC; + gt3_rxresetdone_out : out STD_LOGIC; + gt3_gttxreset_in : in STD_LOGIC; + gt3_txuserrdy_in : in STD_LOGIC; + gt3_txusrclk_in : in STD_LOGIC; + gt3_txusrclk2_in : in STD_LOGIC; + gt3_txdata_in : in STD_LOGIC_VECTOR(19 downto 0); + gt3_gthtxn_out : out STD_LOGIC; + gt3_gthtxp_out : out STD_LOGIC; + gt3_txoutclk_out : out STD_LOGIC; + gt3_txoutclkfabric_out : out STD_LOGIC; + gt3_txoutclkpcs_out : out STD_LOGIC; + gt3_txresetdone_out : out STD_LOGIC; + gt3_txpolarity_in : in STD_LOGIC; + GT0_QPLLLOCK_IN : in STD_LOGIC; + GT0_QPLLREFCLKLOST_IN : in STD_LOGIC; + GT0_QPLLRESET_OUT : out STD_LOGIC; + GT0_QPLLOUTCLK_IN : in STD_LOGIC; + GT0_QPLLOUTREFCLK_IN : in STD_LOGIC + ); +end component gtwizard_QPLL_4p8g_V7; @@ -448,32 +352,32 @@ signal gt0_qplloutclk_i :std_logic; signal tied_to_ground_i : std_logic; signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); signal tied_to_vcc_i : std_logic; -signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0); +--signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0); -signal gt0_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; -signal gt1_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; -signal gt2_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; -signal gt3_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; -signal gt0_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; -signal gt1_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; -signal gt2_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; -signal gt3_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; -signal gt0_drpdo_out : std_logic_vector(15 downto 0); -signal gt1_drpdo_out : std_logic_vector(15 downto 0); -signal gt2_drpdo_out : std_logic_vector(15 downto 0); -signal gt3_drpdo_out : std_logic_vector(15 downto 0); -signal gt0_drpen_in : std_logic:='0'; -signal gt1_drpen_in : std_logic:='0'; -signal gt2_drpen_in : std_logic:='0'; -signal gt3_drpen_in : std_logic:='0'; -signal gt0_drprdy_out : std_logic; -signal gt1_drprdy_out : std_logic; -signal gt2_drprdy_out : std_logic; -signal gt3_drprdy_out : std_logic; -signal gt0_drpwe_in : std_logic:='0'; -signal gt1_drpwe_in : std_logic:='0'; -signal gt2_drpwe_in : std_logic:='0'; -signal gt3_drpwe_in : std_logic:='0'; +--signal gt0_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; +--signal gt1_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; +--signal gt2_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; +--signal gt3_drpaddr_in : std_logic_vector(8 downto 0):="000000000"; +--signal gt0_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; +--signal gt1_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; +--signal gt2_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; +--signal gt3_drpdi_in : std_logic_vector(15 downto 0):=x"0000"; +--signal gt0_drpdo_out : std_logic_vector(15 downto 0); +--signal gt1_drpdo_out : std_logic_vector(15 downto 0); +--signal gt2_drpdo_out : std_logic_vector(15 downto 0); +--signal gt3_drpdo_out : std_logic_vector(15 downto 0); +--signal gt0_drpen_in : std_logic:='0'; +--signal gt1_drpen_in : std_logic:='0'; +--signal gt2_drpen_in : std_logic:='0'; +--signal gt3_drpen_in : std_logic:='0'; +--signal gt0_drprdy_out : std_logic; +--signal gt1_drprdy_out : std_logic; +--signal gt2_drprdy_out : std_logic; +--signal gt3_drprdy_out : std_logic; +--signal gt0_drpwe_in : std_logic:='0'; +--signal gt1_drpwe_in : std_logic:='0'; +--signal gt2_drpwe_in : std_logic:='0'; +--signal gt3_drpwe_in : std_logic:='0'; signal GT0_QPLLREFCLKLOST_I : std_logic; @@ -487,8 +391,6 @@ begin tied_to_ground_i <= '0'; tied_to_ground_vec_i <= x"0000000000000000"; tied_to_vcc_i <= '1'; - tied_to_vcc_vec_i <= x"ff"; - gt_cpllfbclklost_out <= "0000"; gt_cplllock_out <= "1111"; @@ -513,82 +415,82 @@ begin gthe2_common_0_i : GTHE2_COMMON generic map ( + BIAS_CFG => (x"0000040000001050"), + COMMON_CFG => (x"0000001C"), -- Simulation attributes - SIM_RESET_SPEEDUP => ("FALSE"), - SIM_QPLLREFCLK_SEL => ("001"), - SIM_VERSION => ("2.0"), - - - ------------------COMMON BLOCK Attributes--------------- - BIAS_CFG => (x"0000040000001050"), - COMMON_CFG => (x"0000001C"), - QPLL_CFG => (x"04801C7"), - QPLL_CLKOUT_CFG => ("1111"), - QPLL_COARSE_FREQ_OVRD => ("010000"), - QPLL_COARSE_FREQ_OVRD_EN => ('0'), - QPLL_CP => ("0000011111"), - QPLL_CP_MONITOR_EN => ('0'), - QPLL_DMONITOR_SEL => ('0'), - QPLL_FBDIV => ("0010000000"),--(QPLL_FBDIV_IN), - QPLL_FBDIV_MONITOR_EN => ('0'), - QPLL_FBDIV_RATIO => ('1'),--(QPLL_FBDIV_RATIO), - QPLL_INIT_CFG => (x"000006"), - QPLL_LOCK_CFG => (x"05E8"), - QPLL_LPF => ("1111"), - QPLL_REFCLK_DIV => (1), - RSVD_ATTR0 => (x"0000"), - RSVD_ATTR1 => (x"0000"), - QPLL_RP_COMP => ('0'), - QPLL_VTRL_RESET => ("00"), - RCAL_CFG => ("00") + IS_DRPCLK_INVERTED => '0', + IS_GTGREFCLK_INVERTED => '0', + IS_QPLLLOCKDETCLK_INVERTED => '0', + QPLL_CFG => (x"04801C7"), + QPLL_CLKOUT_CFG => ("1111"), + QPLL_COARSE_FREQ_OVRD => ("010000"), + QPLL_COARSE_FREQ_OVRD_EN => ('0'), + QPLL_CP => ("0000011111"), + QPLL_CP_MONITOR_EN => ('0'), + QPLL_DMONITOR_SEL => ('0'), + QPLL_FBDIV => ("0010000000"), --(QPLL_FBDIV_IN), + QPLL_FBDIV_MONITOR_EN => ('0'), + QPLL_FBDIV_RATIO => ('1'), --(QPLL_FBDIV_RATIO), + QPLL_INIT_CFG => (x"000006"), + QPLL_LOCK_CFG => (x"05E8"), + QPLL_LPF => ("1111"), + QPLL_REFCLK_DIV => (1), + QPLL_RP_COMP => ('0'), + QPLL_VTRL_RESET => ("00"), + RCAL_CFG => ("00"), + RSVD_ATTR0 => (x"0000"), + RSVD_ATTR1 => (x"0000"), + SIM_QPLLREFCLK_SEL => ("001"), + SIM_RESET_SPEEDUP => ("FALSE"), + SIM_VERSION => ("2.0") ) port map ( - ------------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- - DRPADDR => tied_to_ground_vec_i(7 downto 0), - DRPCLK => tied_to_ground_i, - DRPDI => tied_to_ground_vec_i(15 downto 0), - DRPDO => open, - DRPEN => tied_to_ground_i, - DRPRDY => open, - DRPWE => tied_to_ground_i, - ---------------------- Common Block - Ref Clock Ports --------------------- - GTGREFCLK => tied_to_ground_i, - GTNORTHREFCLK0 => tied_to_ground_i, - GTNORTHREFCLK1 => tied_to_ground_i, - GTREFCLK0 => GTH_RefClk, - GTREFCLK1 => tied_to_ground_i, - GTSOUTHREFCLK0 => tied_to_ground_i, - GTSOUTHREFCLK1 => tied_to_ground_i, + DRPDO => open, + DRPRDY => open, + PMARSVDOUT => open, ------------------------- Common Block - QPLL Ports ----------------------- - QPLLDMONITOR => open, + QPLLDMONITOR => open, + QPLLFBCLKLOST => open, + QPLLLOCK => GT0_QPLLLOCK_I, ----------------------- Common Block - Clocking Ports ---------------------- - QPLLOUTCLK => gt0_qplloutclk_i, - QPLLOUTREFCLK => gt0_qplloutrefclk_i, - REFCLKOUTMONITOR => open, - ------------------------- Common Block - QPLL Ports ------------------------ - BGRCALOVRDENB => tied_to_vcc_i, - PMARSVDOUT => open, - QPLLFBCLKLOST => open, - QPLLLOCK => GT0_QPLLLOCK_I, - QPLLLOCKDETCLK => DRP_CLK_IN, - QPLLLOCKEN => tied_to_vcc_i, - QPLLOUTRESET => tied_to_ground_i, - QPLLPD => tied_to_ground_i, - QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_I, - QPLLREFCLKSEL => "001", - QPLLRESET => GT0_QPLLRESET_i or QPLL_RESET_IN, - QPLLRSVD1 => "0000000000000000", - QPLLRSVD2 => "11111", + QPLLOUTCLK => gt0_qplloutclk_i, + QPLLOUTREFCLK => GT0_QPLLOUTREFCLK_I, + QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_I, + REFCLKOUTMONITOR => open, --------------------------------- QPLL Ports ------------------------------- - BGBYPASSB => tied_to_vcc_i, - BGMONITORENB => tied_to_vcc_i, - BGPDB => tied_to_vcc_i, - BGRCALOVRD => "00000", - PMARSVD => "00000000", - RCALENB => tied_to_vcc_i + BGBYPASSB => tied_to_vcc_i, + BGMONITORENB => tied_to_vcc_i, + BGPDB => tied_to_vcc_i, + BGRCALOVRD => "00000", + ------------------------- Common Block - QPLL Ports ------------------------ + BGRCALOVRDENB => tied_to_vcc_i, + ------------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- + DRPADDR => tied_to_ground_vec_i(7 downto 0), + DRPCLK => tied_to_ground_i, + DRPDI => tied_to_ground_vec_i(15 downto 0), + DRPEN => tied_to_ground_i, + DRPWE => tied_to_ground_i, + ---------------------- Common Block - Ref Clock Ports --------------------- + GTGREFCLK => tied_to_ground_i, + GTNORTHREFCLK0 => tied_to_ground_i, + GTNORTHREFCLK1 => tied_to_ground_i, + GTREFCLK0 => GTH_RefClk, + GTREFCLK1 => tied_to_ground_i, + GTSOUTHREFCLK0 => tied_to_ground_i, + GTSOUTHREFCLK1 => tied_to_ground_i, + PMARSVD => "00000000", + QPLLLOCKDETCLK => DRP_CLK_IN, + QPLLLOCKEN => tied_to_vcc_i, + QPLLOUTRESET => tied_to_ground_i, + QPLLPD => tied_to_ground_i, + QPLLREFCLKSEL => "001", + QPLLRESET => GT0_QPLLRESET_I or QPLL_RESET_IN, + QPLLRSVD1 => "0000000000000000", + QPLLRSVD2 => "11111", + RCALENB => tied_to_vcc_i ); @@ -599,295 +501,245 @@ qpll_inst: gtwizard_QPLL_4p8g_V7 port map ( - SYSCLK_IN => DRP_CLK_IN, - - SOFT_RESET_TX_IN => SOFT_TXRST_ALL, - SOFT_RESET_RX_IN => SOFT_RXRST_ALL, - - DONT_RESET_ON_DATA_ERROR_IN => '1', - - GT0_DRP_BUSY_OUT => open, - GT0_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(0), - GT0_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(0), - GT0_DATA_VALID_IN => '1', - GT1_DRP_BUSY_OUT => open, - GT1_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(1), - GT1_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(1), - GT1_DATA_VALID_IN => '1', - GT2_DRP_BUSY_OUT => open, - GT2_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(2), - GT2_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(2), - GT2_DATA_VALID_IN => '1', - GT3_DRP_BUSY_OUT => open, - GT3_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(3), - GT3_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(3), - GT3_DATA_VALID_IN => '1', - - - --_________________________________________________________________________ - --_________________________________________________________________________ - --GT0 (X1Y4) - --____________________________CHANNEL PORTS________________________________ - ---------------------------- Channel - DRP Ports -------------------------- - gt0_drpaddr_in => gt0_drpaddr_in, - gt0_drpclk_in => DRP_CLK_IN, - gt0_drpdi_in => gt0_drpdi_in, - gt0_drpdo_out => gt0_drpdo_out, - gt0_drpen_in => gt0_drpen_in, - gt0_drprdy_out => gt0_drprdy_out, - gt0_drpwe_in => gt0_drpwe_in, - --------------------- RX Initialization and Reset Ports -------------------- - gt0_eyescanreset_in => '0', - gt0_rxuserrdy_in => gt_rxuserrdy_in(0), - -------------------------- RX Margin Analysis Ports ------------------------ - gt0_eyescandataerror_out => open, - gt0_eyescantrigger_in => '0', - --------------- Receive Ports - Comma Detection and Alignment -------------- - gt0_rxslide_in => gt_rxslide_in(0), - ------------------- Receive Ports - Digital Monitor Ports ------------------ - gt0_dmonitorout_out => open, - ------------------ Receive Ports - FPGA RX Interface Ports ----------------- - gt0_rxusrclk_in => gt0_rxusrclk_in, - gt0_rxusrclk2_in => gt0_rxusrclk_in, - ------------------ Receive Ports - FPGA RX interface Ports ----------------- - gt0_rxdata_out => RX_DATA_gt0_20b, - ------------------------ Receive Ports - RX AFE Ports ---------------------- - gt0_gthrxn_in => RXN_IN(0), - ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- - -- gt0_rxphmonitor_out => open, - --gt0_rxphslipmonitor_out => open, - --------------------- Receive Ports - RX Equalizer Ports ------------------- - gt0_rxmonitorout_out => open, - gt0_rxmonitorsel_in => "00", - --------------- Receive Ports - RX Fabric Output Control Ports ------------- - gt0_rxoutclk_out => gt0_rxoutclk_out, - ------------- Receive Ports - RX Initialization and Reset Ports ------------ - gt0_gtrxreset_in => gt0_gtrxreset_in, - ------------------------ Receive Ports -RX AFE Ports ----------------------- - gt0_gthrxp_in => RXP_IN(0), - -------------- Receive Ports -RX Initialization and Reset Ports ------------ - gt0_rxresetdone_out => gt_rxresetdone_out(0),-- gt0_rxresetdone_out, - --------------------- TX Initialization and Reset Ports -------------------- - gt0_gttxreset_in => gt0_gttxreset_in, - gt0_txuserrdy_in => gt_txuserrdy_in(0), - ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- - gt0_txusrclk_in => gt0_txusrclk_in, - gt0_txusrclk2_in => gt0_txusrclk_in, - ------------------ Transmit Ports - TX Data Path interface ----------------- - gt0_txdata_in => TX_DATA_gt0_20b, - ---------------- Transmit Ports - TX Driver and OOB signaling -------------- - gt0_gthtxn_out => TXN_OUT(0), - gt0_gthtxp_out => TXP_OUT(0), - ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- - gt0_txoutclk_out => gt0_txoutclk_out, - gt0_txoutclkfabric_out => open,--gt0_txoutclkfabric_out, - gt0_txoutclkpcs_out => open,--gt0_txoutclkpcs_out, - ------------- Transmit Ports - TX Initialization and Reset Ports ----------- - gt0_txresetdone_out => gt_txresetdone_out(0), - - --GT1 (X1Y5) - --____________________________CHANNEL PORTS________________________________ - ---------------------------- Channel - DRP Ports -------------------------- - gt1_drpaddr_in => gt1_drpaddr_in, - gt1_drpclk_in => DRP_CLK_IN, - gt1_drpdi_in => gt1_drpdi_in, - gt1_drpdo_out => gt1_drpdo_out, - gt1_drpen_in => gt1_drpen_in, - gt1_drprdy_out => gt1_drprdy_out, - gt1_drpwe_in => gt1_drpwe_in, - --------------------- RX Initialization and Reset Ports -------------------- - gt1_eyescanreset_in => '0', - gt1_rxuserrdy_in => gt_rxuserrdy_in(1), - -------------------------- RX Margin Analysis Ports ------------------------ - gt1_eyescandataerror_out => open, - gt1_eyescantrigger_in => '0', - --------------- Receive Ports - Comma Detection and Alignment -------------- - gt1_rxslide_in => gt_rxslide_in(1), - ------------------- Receive Ports - Digital Monitor Ports ------------------ - gt1_dmonitorout_out => open, - ------------------ Receive Ports - FPGA RX Interface Ports ----------------- - gt1_rxusrclk_in => gt1_rxusrclk_in, - gt1_rxusrclk2_in => gt1_rxusrclk_in, - ------------------ Receive Ports - FPGA RX interface Ports ----------------- - gt1_rxdata_out => RX_DATA_gt1_20b, - ------------------------ Receive Ports - RX AFE Ports ---------------------- - gt1_gthrxn_in => RXN_IN(1), - ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + SYSCLK_IN => DRP_CLK_IN, + SOFT_RESET_TX_IN => SOFT_TXRST_ALL, + SOFT_RESET_RX_IN => SOFT_RXRST_ALL, + DONT_RESET_ON_DATA_ERROR_IN => '1', + GT0_DRP_BUSY_OUT => open, + GT0_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(0), + GT0_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(0), + GT0_DATA_VALID_IN => '1', + GT1_DRP_BUSY_OUT => open, + GT1_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(1), + GT1_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(1), + GT1_DATA_VALID_IN => '1', + GT2_DRP_BUSY_OUT => open, + GT2_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(2), + GT2_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(2), + GT2_DATA_VALID_IN => '1', + GT3_DRP_BUSY_OUT => open, + GT3_TX_FSM_RESET_DONE_OUT => gt_txfsmresetdone_out(3), + GT3_RX_FSM_RESET_DONE_OUT => gt_rxfsmresetdone_out(3), + GT3_DATA_VALID_IN => '1', + gt0_drpaddr_in => (others => '0'), + gt0_drpclk_in => DRP_CLK_IN, + gt0_drpdi_in => (others => '0'), + gt0_drpdo_out => open, + gt0_drpen_in => '0', + gt0_drprdy_out => open, + gt0_drpwe_in => '0', + gt0_loopback_in => gt0_loopback_in, + gt0_eyescanreset_in => '0', + gt0_rxuserrdy_in => gt_rxuserrdy_in(0), + gt0_eyescandataerror_out => open, + gt0_eyescantrigger_in => '0', + gt0_rxcdrhold_in => gt0_rxcdrhold_in, + gt0_rxslide_in => gt_rxslide_in(0), + gt0_dmonitorout_out => open, + gt0_rxusrclk_in => gt0_rxusrclk_in, + gt0_rxusrclk2_in => gt0_rxusrclk_in, + gt0_rxdata_out => RX_DATA_gt0_20b, + gt0_gthrxn_in => RXN_IN(0), + gt0_rxmonitorout_out => open, + gt0_rxmonitorsel_in => "00", + gt0_rxoutclk_out => gt0_rxoutclk_out, + gt0_rxoutclkfabric_out => open, + gt0_gtrxreset_in => gt0_gtrxreset_in, + gt0_rxpolarity_in => gt_rxpolarity_in(0), + gt0_gthrxp_in => RXP_IN(0), + gt0_rxresetdone_out => gt_rxresetdone_out(0), -- gt0_rxresetdone_out, + gt0_gttxreset_in => gt0_gttxreset_in, + gt0_txuserrdy_in => gt_txuserrdy_in(0), + gt0_txusrclk_in => gt0_txusrclk_in, + gt0_txusrclk2_in => gt0_txusrclk_in, + gt0_txdata_in => TX_DATA_gt0_20b, + gt0_gthtxn_out => TXN_OUT(0), + gt0_gthtxp_out => TXP_OUT(0), + gt0_txoutclk_out => gt0_txoutclk_out, + gt0_txoutclkfabric_out => open, --gt0_txoutclkfabric_out, + gt0_txoutclkpcs_out => open, --gt0_txoutclkpcs_out, + gt0_txresetdone_out => gt_txresetdone_out(0), + gt0_txpolarity_in => gt_txpolarity_in(0), + gt1_drpaddr_in => (others => '0'), + gt1_drpclk_in => DRP_CLK_IN, + gt1_drpdi_in => (others => '0'), + gt1_drpdo_out => open, + gt1_drpen_in => '0', + gt1_drprdy_out => open, + gt1_drpwe_in => '0', + gt1_loopback_in => gt1_loopback_in, + gt1_eyescanreset_in => '0', + gt1_rxuserrdy_in => gt_rxuserrdy_in(1), + gt1_eyescandataerror_out => open, + gt1_eyescantrigger_in => '0', + gt1_rxcdrhold_in => gt1_rxcdrhold_in, + gt1_rxslide_in => gt_rxslide_in(1), + gt1_dmonitorout_out => open, + gt1_rxusrclk_in => gt1_rxusrclk_in, + gt1_rxusrclk2_in => gt1_rxusrclk_in, + gt1_rxdata_out => RX_DATA_gt1_20b, + gt1_gthrxn_in => RXN_IN(1), --gt1_rxphmonitor_out => open, --gt1_rxphslipmonitor_out => open, --------------------- Receive Ports - RX Equalizer Ports ------------------- - gt1_rxmonitorout_out => open, - gt1_rxmonitorsel_in => "00", + gt1_rxmonitorout_out => open, + gt1_rxmonitorsel_in => "00", --------------- Receive Ports - RX Fabric Output Control Ports ------------- - gt1_rxoutclk_out => gt1_rxoutclk_out, + gt1_rxoutclk_out => gt1_rxoutclk_out, + gt1_rxoutclkfabric_out => open, ------------- Receive Ports - RX Initialization and Reset Ports ------------ - gt1_gtrxreset_in => gt1_gtrxreset_in, + gt1_gtrxreset_in => gt1_gtrxreset_in, + gt1_rxpolarity_in => gt_rxpolarity_in(1), ------------------------ Receive Ports -RX AFE Ports ----------------------- - gt1_gthrxp_in => RXP_IN(1), + gt1_gthrxp_in => RXP_IN(1), -------------- Receive Ports -RX Initialization and Reset Ports ------------ - gt1_rxresetdone_out => gt_rxresetdone_out(1), + gt1_rxresetdone_out => gt_rxresetdone_out(1), --------------------- TX Initialization and Reset Ports -------------------- - gt1_gttxreset_in => gt1_gttxreset_in, - gt1_txuserrdy_in => gt_txuserrdy_in(1), + gt1_gttxreset_in => gt1_gttxreset_in, + gt1_txuserrdy_in => gt_txuserrdy_in(1), ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- - gt1_txusrclk_in => gt0_txusrclk_in, - gt1_txusrclk2_in => gt0_txusrclk_in, + gt1_txusrclk_in => gt0_txusrclk_in, + gt1_txusrclk2_in => gt0_txusrclk_in, ------------------ Transmit Ports - TX Data Path interface ----------------- - gt1_txdata_in => TX_DATA_gt1_20b, + gt1_txdata_in => TX_DATA_gt1_20b, ---------------- Transmit Ports - TX Driver and OOB signaling -------------- - gt1_gthtxn_out => TXN_OUT(1), - gt1_gthtxp_out => TXP_OUT(1), + gt1_gthtxn_out => TXN_OUT(1), + gt1_gthtxp_out => TXP_OUT(1), ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- - gt1_txoutclk_out => gt1_txoutclk_out, - gt1_txoutclkfabric_out => open,--gt1_txoutclkfabric_out, - gt1_txoutclkpcs_out => open,--gt1_txoutclkpcs_out, + gt1_txoutclk_out => gt1_txoutclk_out, + gt1_txoutclkfabric_out => open, --gt1_txoutclkfabric_out, + gt1_txoutclkpcs_out => open, --gt1_txoutclkpcs_out, ------------- Transmit Ports - TX Initialization and Reset Ports ----------- - gt1_txresetdone_out => gt_txresetdone_out(1), - - --GT2 (X1Y6) - --____________________________CHANNEL PORTS________________________________ - ---------------------------- Channel - DRP Ports -------------------------- - gt2_drpaddr_in => gt2_drpaddr_in, - gt2_drpclk_in => DRP_CLK_IN, - gt2_drpdi_in => gt2_drpdi_in, - gt2_drpdo_out => gt2_drpdo_out, - gt2_drpen_in => gt2_drpen_in, - gt2_drprdy_out => gt2_drprdy_out, - gt2_drpwe_in => gt2_drpwe_in, + gt1_txresetdone_out => gt_txresetdone_out(1), + gt1_txpolarity_in => gt_txpolarity_in(1), + gt2_drpaddr_in => (others => '0'), + gt2_drpclk_in => DRP_CLK_IN, + gt2_drpdi_in => (others => '0'), + gt2_drpdo_out => open, + gt2_drpen_in => '0', + gt2_drprdy_out => open, + gt2_drpwe_in => '0', + gt2_loopback_in => gt2_loopback_in, --------------------- RX Initialization and Reset Ports -------------------- - gt2_eyescanreset_in => '0', - gt2_rxuserrdy_in => gt_rxuserrdy_in(2), + gt2_eyescanreset_in => '0', + gt2_rxuserrdy_in => gt_rxuserrdy_in(2), -------------------------- RX Margin Analysis Ports ------------------------ - gt2_eyescandataerror_out => open, - gt2_eyescantrigger_in => '0', + gt2_eyescandataerror_out => open, + gt2_eyescantrigger_in => '0', + gt2_rxcdrhold_in => gt2_rxcdrhold_in, --------------- Receive Ports - Comma Detection and Alignment -------------- - gt2_rxslide_in => gt_rxslide_in(2), + gt2_rxslide_in => gt_rxslide_in(2), ------------------- Receive Ports - Digital Monitor Ports ------------------ - gt2_dmonitorout_out => open, + gt2_dmonitorout_out => open, ------------------ Receive Ports - FPGA RX Interface Ports ----------------- - gt2_rxusrclk_in => gt2_rxusrclk_in, - gt2_rxusrclk2_in => gt2_rxusrclk_in, + gt2_rxusrclk_in => gt2_rxusrclk_in, + gt2_rxusrclk2_in => gt2_rxusrclk_in, ------------------ Receive Ports - FPGA RX interface Ports ----------------- - gt2_rxdata_out => RX_DATA_gt2_20b, + gt2_rxdata_out => RX_DATA_gt2_20b, ------------------------ Receive Ports - RX AFE Ports ---------------------- - gt2_gthrxn_in => RXN_IN(2), + gt2_gthrxn_in => RXN_IN(2), ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- --gt2_rxphmonitor_out => open, --gt2_rxphslipmonitor_out => open, --------------------- Receive Ports - RX Equalizer Ports ------------------- - gt2_rxmonitorout_out => open, - gt2_rxmonitorsel_in => "00", + gt2_rxmonitorout_out => open, + gt2_rxmonitorsel_in => "00", --------------- Receive Ports - RX Fabric Output Control Ports ------------- - gt2_rxoutclk_out => gt2_rxoutclk_out, + gt2_rxoutclk_out => gt2_rxoutclk_out, + gt2_rxoutclkfabric_out => open, ------------- Receive Ports - RX Initialization and Reset Ports ------------ - gt2_gtrxreset_in => gt2_gtrxreset_in, + gt2_gtrxreset_in => gt2_gtrxreset_in, + gt2_rxpolarity_in => gt_rxpolarity_in(2), ------------------------ Receive Ports -RX AFE Ports ----------------------- - gt2_gthrxp_in => RXP_IN(2), + gt2_gthrxp_in => RXP_IN(2), -------------- Receive Ports -RX Initialization and Reset Ports ------------ - gt2_rxresetdone_out => gt_rxresetdone_out(2), + gt2_rxresetdone_out => gt_rxresetdone_out(2), --------------------- TX Initialization and Reset Ports -------------------- - gt2_gttxreset_in => gt2_gttxreset_in, - gt2_txuserrdy_in => gt_txuserrdy_in(2), + gt2_gttxreset_in => gt2_gttxreset_in, + gt2_txuserrdy_in => gt_txuserrdy_in(2), ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- - gt2_txusrclk_in => gt0_txusrclk_in, - gt2_txusrclk2_in => gt0_txusrclk_in, + gt2_txusrclk_in => gt0_txusrclk_in, + gt2_txusrclk2_in => gt0_txusrclk_in, ------------------ Transmit Ports - TX Data Path interface ----------------- - gt2_txdata_in => TX_DATA_gt2_20b, + gt2_txdata_in => TX_DATA_gt2_20b, ---------------- Transmit Ports - TX Driver and OOB signaling -------------- - gt2_gthtxn_out => TXN_OUT(2), - gt2_gthtxp_out => TXP_OUT(2), + gt2_gthtxn_out => TXN_OUT(2), + gt2_gthtxp_out => TXP_OUT(2), ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- - gt2_txoutclk_out => gt2_txoutclk_out, - gt2_txoutclkfabric_out => open,--gt2_txoutclkfabric_out, - gt2_txoutclkpcs_out => open,--gt2_txoutclkpcs_out, + gt2_txoutclk_out => gt2_txoutclk_out, + gt2_txoutclkfabric_out => open, --gt2_txoutclkfabric_out, + gt2_txoutclkpcs_out => open, --gt2_txoutclkpcs_out, ------------- Transmit Ports - TX Initialization and Reset Ports ----------- - gt2_txresetdone_out => gt_txresetdone_out(2), - + gt2_txresetdone_out => gt_txresetdone_out(2), + gt2_txpolarity_in => gt_txpolarity_in(2), --GT3 (X1Y7) --____________________________CHANNEL PORTS________________________________ ---------------------------- Channel - DRP Ports -------------------------- - gt3_drpaddr_in => gt3_drpaddr_in, - gt3_drpclk_in => DRP_CLK_IN, - gt3_drpdi_in => gt3_drpdi_in, - gt3_drpdo_out => gt3_drpdo_out, - gt3_drpen_in => gt3_drpen_in, - gt3_drprdy_out => gt3_drprdy_out, - gt3_drpwe_in => gt3_drpwe_in, + gt3_drpaddr_in => (others => '0'), + gt3_drpclk_in => DRP_CLK_IN, + gt3_drpdi_in => (others => '0'), + gt3_drpdo_out => open, + gt3_drpen_in => '0', + gt3_drprdy_out => open, + gt3_drpwe_in => '0', + gt3_loopback_in => gt3_loopback_in, --------------------- RX Initialization and Reset Ports -------------------- - gt3_eyescanreset_in => '0', - gt3_rxuserrdy_in => gt_rxuserrdy_in(3), + gt3_eyescanreset_in => '0', + gt3_rxuserrdy_in => gt_rxuserrdy_in(3), -------------------------- RX Margin Analysis Ports ------------------------ - gt3_eyescandataerror_out => open, - gt3_eyescantrigger_in => '0', + gt3_eyescandataerror_out => open, + gt3_eyescantrigger_in => '0', + gt3_rxcdrhold_in => gt3_rxcdrhold_in, --------------- Receive Ports - Comma Detection and Alignment -------------- - gt3_rxslide_in => gt_rxslide_in(3), + gt3_rxslide_in => gt_rxslide_in(3), ------------------- Receive Ports - Digital Monitor Ports ------------------ - gt3_dmonitorout_out => open, + gt3_dmonitorout_out => open, ------------------ Receive Ports - FPGA RX Interface Ports ----------------- - gt3_rxusrclk_in => gt3_rxusrclk_in, - gt3_rxusrclk2_in => gt3_rxusrclk_in, + gt3_rxusrclk_in => gt3_rxusrclk_in, + gt3_rxusrclk2_in => gt3_rxusrclk_in, ------------------ Receive Ports - FPGA RX interface Ports ----------------- - gt3_rxdata_out => RX_DATA_gt3_20b, + gt3_rxdata_out => RX_DATA_gt3_20b, ------------------------ Receive Ports - RX AFE Ports ---------------------- - gt3_gthrxn_in => RXN_IN(3), + gt3_gthrxn_in => RXN_IN(3), ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- --gt3_rxphmonitor_out => open, --gt3_rxphslipmonitor_out => open, --------------------- Receive Ports - RX Equalizer Ports ------------------- - gt3_rxmonitorout_out => open, - gt3_rxmonitorsel_in => "00", + gt3_rxmonitorout_out => open, + gt3_rxmonitorsel_in => "00", --------------- Receive Ports - RX Fabric Output Control Ports ------------- - gt3_rxoutclk_out => gt3_rxoutclk_out, + gt3_rxoutclk_out => gt3_rxoutclk_out, + gt3_rxoutclkfabric_out => open, ------------- Receive Ports - RX Initialization and Reset Ports ------------ - gt3_gtrxreset_in => gt3_gtrxreset_in, + gt3_gtrxreset_in => gt3_gtrxreset_in, + gt3_rxpolarity_in => gt_rxpolarity_in(3), ------------------------ Receive Ports -RX AFE Ports ----------------------- - gt3_gthrxp_in => RXP_IN(3), + gt3_gthrxp_in => RXP_IN(3), -------------- Receive Ports -RX Initialization and Reset Ports ------------ - gt3_rxresetdone_out => gt_rxresetdone_out(3), + gt3_rxresetdone_out => gt_rxresetdone_out(3), --------------------- TX Initialization and Reset Ports -------------------- - gt3_gttxreset_in => gt3_gttxreset_in, - gt3_txuserrdy_in => gt_txuserrdy_in(3), + gt3_gttxreset_in => gt3_gttxreset_in, + gt3_txuserrdy_in => gt_txuserrdy_in(3), ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- - gt3_txusrclk_in => gt0_txusrclk_in, - gt3_txusrclk2_in => gt0_txusrclk_in, + gt3_txusrclk_in => gt0_txusrclk_in, + gt3_txusrclk2_in => gt0_txusrclk_in, ------------------ Transmit Ports - TX Data Path interface ----------------- - gt3_txdata_in => TX_DATA_gt3_20b, + gt3_txdata_in => TX_DATA_gt3_20b, ---------------- Transmit Ports - TX Driver and OOB signaling -------------- - gt3_gthtxn_out => TXN_OUT(3), - gt3_gthtxp_out => TXP_OUT(3), + gt3_gthtxn_out => TXN_OUT(3), + gt3_gthtxp_out => TXP_OUT(3), ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- - gt3_txoutclk_out => gt3_txoutclk_out, - gt3_txoutclkfabric_out => open,--gt3_txoutclkfabric_out, - gt3_txoutclkpcs_out => open,--gt3_txoutclkpcs_out, + gt3_txoutclk_out => gt3_txoutclk_out, + gt3_txoutclkfabric_out => open, --gt3_txoutclkfabric_out, + gt3_txoutclkpcs_out => open, --gt3_txoutclkpcs_out, ------------- Transmit Ports - TX Initialization and Reset Ports ----------- - gt3_txresetdone_out => gt_txresetdone_out(3), - - gt3_txpolarity_in => gt_txpolarity_in(3), - gt2_txpolarity_in => gt_txpolarity_in(2), - gt1_txpolarity_in => gt_txpolarity_in(1), - gt0_txpolarity_in => gt_txpolarity_in(0), - gt3_rxpolarity_in => gt_rxpolarity_in(3), - gt2_rxpolarity_in => gt_rxpolarity_in(2), - gt1_rxpolarity_in => gt_rxpolarity_in(1), - gt0_rxpolarity_in => gt_rxpolarity_in(0), - gt0_loopback_in => gt0_loopback_in, - gt0_rxcdrhold_in => gt0_rxcdrhold_in, - gt1_loopback_in => gt1_loopback_in, - gt1_rxcdrhold_in => gt1_rxcdrhold_in, - gt2_loopback_in => gt2_loopback_in, - gt2_rxcdrhold_in => gt2_rxcdrhold_in, - gt3_loopback_in => gt3_loopback_in, - gt3_rxcdrhold_in => gt3_rxcdrhold_in, - - - - --____________________________COMMON PORTS________________________________ - - GT0_QPLLLOCK_IN => GT0_QPLLLOCK_I, - GT0_QPLLREFCLKLOST_IN => GT0_QPLLREFCLKLOST_I, - GT0_QPLLRESET_OUT => GT0_QPLLRESET_I, - GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_I, - GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_I + gt3_txresetdone_out => gt_txresetdone_out(3), + gt3_txpolarity_in => gt_txpolarity_in(3), + GT0_QPLLLOCK_IN => GT0_QPLLLOCK_I, + GT0_QPLLREFCLKLOST_IN => GT0_QPLLREFCLKLOST_I, + GT0_QPLLRESET_OUT => GT0_QPLLRESET_I, + GT0_QPLLOUTCLK_IN => gt0_qplloutclk_i, + GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_I ); diff --git a/sources/GBTlinksDataEmulator/GBTdataEmulator.vhd b/sources/GBTlinksDataEmulator/GBTdataEmulator.vhd index ddff09afa497638798f8c3a092fb651cb3225448..9e31e4acf2f00458b2b9cbf9234c24e8d5eea7c6 100644 --- a/sources/GBTlinksDataEmulator/GBTdataEmulator.vhd +++ b/sources/GBTlinksDataEmulator/GBTdataEmulator.vhd @@ -7,10 +7,10 @@ --! Project Name: FELIX ---------------------------------------------------------------------------------- --! Use standard library -library work, IEEE; +library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use work.pcie_package.all; use work.centralRouter_package.all; @@ -142,7 +142,13 @@ begin -- -- global reset -rst_fall_pulse: entity work.pulse_fall_pw01(behavioral) port map(clk40, rst_soft, rst_fall); + +rst_fall_pulse: entity work.pulse_fall_pw01 port map( + clk => clk40, + trigger => rst_soft, + pulseout => rst_fall +); + -- RESET_latch: process(clk40, rst_hw) begin diff --git a/sources/LinkWrapper/link_wrapper.vhd b/sources/LinkWrapper/link_wrapper.vhd index 0f97b351f1221460894a595612041161756dd67f..e1d10a9c7cca3a88eac349cd4a953087cef2c659 100644 --- a/sources/LinkWrapper/link_wrapper.vhd +++ b/sources/LinkWrapper/link_wrapper.vhd @@ -51,71 +51,40 @@ architecture rtl of link_wrapper is component FELIX_gbt_wrapper - Generic ( - CARD_TYPE : integer := 709; - STABLE_CLOCK_PERIOD : integer := 24; --period of the drp_clock - GBT_NUM : integer := 24; - OPTO_TRX : integer := 4; -- number of optical transceivers - GTHREFCLK_SEL : std_logic; --GREFCLK : std_logic := '1'; - --MGTREFCLK : std_logic := '0'; - PLL_SEL : std_logic -- CPLL : '0' - -- QPLL : '1' - -- QUAD_NUM : integer := 6 - ); - Port ( - ------------------- - ---- For debug - ------------------- - RX_FLAG_O : out std_logic_vector(GBT_NUM-1 downto 0); - TX_FLAG_O : out std_logic_vector(GBT_NUM-1 downto 0); - REFCLK_CXP1 : out std_logic; - REFCLK_CXP2 : out std_logic; - ----------------------- - ---- Used ports - ---------------------- - rst_hw : in std_logic; - opto_los : in std_logic_vector(OPTO_TRX-1 downto 0); - -- for VC709, use LOS from SFP - -- for HTG710, use all '0', or use software to read - -- optical module register, then set it. - - register_map_control : in register_map_control_type; - register_map_link_monitor : out register_map_link_monitor_type; - - -- GTH REFCLK, DRPCLK, GREFCLK - DRP_CLK_IN : in std_logic; - Q2_CLK0_GTREFCLK_PAD_N_IN : in std_logic; - Q2_CLK0_GTREFCLK_PAD_P_IN : in std_logic; - Q8_CLK0_GTREFCLK_PAD_N_IN : in std_logic; - Q8_CLK0_GTREFCLK_PAD_P_IN : in std_logic; - GREFCLK_IN : in std_logic; - - clk40_in : in std_logic; - clk240_in : in std_logic; - -- for CentralRouter - TX_120b_in : in txrx120b_type(0 to (GBT_NUM-1)); - RX_120b_out : out txrx120b_type(0 to (GBT_NUM-1)); - FRAME_LOCKED_O : out std_logic_vector(GBT_NUM-1 downto 0); - -- TX_ISDATA_I : in std_logic_vector(GBT_NUM-1 downto 0); - -- RX_ISDATA_O : out std_logic_vector(GBT_NUM-1 downto 0); - -- RX_FRAME_CLK_O : out std_logic_vector(GBT_NUM-1 downto 0); - TX_FRAME_CLK_I : in std_logic_vector(GBT_NUM-1 downto 0); - - --FIFO_RD_CLK : in std_logic_vector(GBT_NUM-1 downto 0); - --FIFO_RD_EN : in std_logic_vector(GBT_NUM-1 downto 0); - --FIFO_FULL : out std_logic_vector(GBT_NUM-1 downto 0); - --FIFO_EMPTY : out std_logic_vector(GBT_NUM-1 downto 0); - - - -- GTH Data pins - TX_P : out std_logic_vector(GBT_NUM-1 downto 0); - TX_N : out std_logic_vector(GBT_NUM-1 downto 0); - RX_P : in std_logic_vector(GBT_NUM-1 downto 0); - RX_N : in std_logic_vector(GBT_NUM-1 downto 0); - RXUSRCLK_OUT : out std_logic_vector(GBT_NUM-1 downto 0) - - ); - end component FELIX_gbt_wrapper; + generic( + CARD_TYPE : integer; + GBT_NUM : integer; + OPTO_TRX : integer; + GTHREFCLK_SEL : std_logic; + PLL_SEL : std_logic + ); + port( + RX_FLAG_O : out std_logic_vector(GBT_NUM - 1 downto 0); + TX_FLAG_O : out std_logic_vector(GBT_NUM - 1 downto 0); + REFCLK_CXP1 : out std_logic; + REFCLK_CXP2 : out std_logic; + rst_hw : in std_logic; + opto_los : in std_logic_vector(OPTO_TRX - 1 downto 0); + register_map_control : in register_map_control_type; + register_map_link_monitor : out register_map_link_monitor_type; + DRP_CLK_IN : in std_logic; + Q2_CLK0_GTREFCLK_PAD_N_IN : in std_logic; + Q2_CLK0_GTREFCLK_PAD_P_IN : in std_logic; + Q8_CLK0_GTREFCLK_PAD_N_IN : in std_logic; + Q8_CLK0_GTREFCLK_PAD_P_IN : in std_logic; + GREFCLK_IN : in std_logic; + clk40_in : in std_logic; + TX_120b_in : in txrx120b_type(0 to (GBT_NUM - 1)); + RX_120b_out : out txrx120b_type(0 to (GBT_NUM - 1)); + FRAME_LOCKED_O : out std_logic_vector(GBT_NUM - 1 downto 0); + TX_FRAME_CLK_I : in std_logic_vector(GBT_NUM - 1 downto 0); + TX_P : out std_logic_vector(GBT_NUM - 1 downto 0); + TX_N : out std_logic_vector(GBT_NUM - 1 downto 0); + RX_P : in std_logic_vector(GBT_NUM - 1 downto 0); + RX_N : in std_logic_vector(GBT_NUM - 1 downto 0); + RXUSRCLK_OUT : out std_logic_vector(GBT_NUM - 1 downto 0) + ); + end component FELIX_gbt_wrapper; begin @@ -134,7 +103,7 @@ begin u2: FELIX_gbt_wrapper generic map( CARD_TYPE => CARD_TYPE, - STABLE_CLOCK_PERIOD => 24, + --STABLE_CLOCK_PERIOD => 24, GBT_NUM => GBT_NUM, OPTO_TRX => OPTO_TRX, GTHREFCLK_SEL => GTHREFCLK_SEL, @@ -155,7 +124,7 @@ begin Q8_CLK0_GTREFCLK_PAD_P_IN => GTREFCLK_P_in(1), GREFCLK_IN => clk240, clk40_in => clk40, - clk240_in => clk240, + --clk240_in => clk240, TX_120b_in => GBT_DOWNLINK_USER_DATA, RX_120b_out => GBT_UPLINK_USER_DATA, FRAME_LOCKED_O => LinkAligned, @@ -170,7 +139,7 @@ begin g_712: if CARD_TYPE = 711 or CARD_TYPE = 712 generate u2: entity work.FELIX_gbt_wrapper_KCU generic map( - STABLE_CLOCK_PERIOD => 24, + --STABLE_CLOCK_PERIOD => 24, GBT_NUM => GBT_NUM, GTHREFCLK_SEL => GTHREFCLK_SEL, CARD_TYPE => CARD_TYPE, @@ -183,7 +152,7 @@ begin rst_hw => rst_hw, register_map_control => register_map_control, register_map_link_monitor => register_map_link_monitor, - DRP_CLK_IN => clk40_xtal, + --DRP_CLK_IN => clk40_xtal, Q2_CLK0_GTREFCLK_PAD_N_IN => GTREFCLK_N_in(0), Q2_CLK0_GTREFCLK_PAD_P_IN => GTREFCLK_P_in(0), Q8_CLK0_GTREFCLK_PAD_N_IN => GTREFCLK_N_in(1), @@ -194,9 +163,9 @@ begin Q5_CLK0_GTREFCLK_PAD_P_IN => GTREFCLK_P_in(3), Q6_CLK0_GTREFCLK_PAD_N_IN => GTREFCLK_N_in(4), Q6_CLK0_GTREFCLK_PAD_P_IN => GTREFCLK_P_in(4), - GREFCLK_IN => clk240, + --GREFCLK_IN => clk240, clk40_in => clk40, - clk240_in => clk240, + --clk240_in => clk240, TX_120b_in => GBT_DOWNLINK_USER_DATA, RX_120b_out => GBT_UPLINK_USER_DATA, FRAME_LOCKED_O => LinkAligned, @@ -214,30 +183,23 @@ begin FIRMWARE_MODE = FIRMWARE_MODE_STRIP generate u2: entity work.FELIX_LpGBT_Wrapper Generic map( - STABLE_CLOCK_PERIOD => 24, GBT_NUM => GBT_NUM, - PRBS_TEST_EN => 0, - GTHREFCLK_SEL => GTHREFCLK_SEL, - CARD_TYPE => CARD_TYPE, + --CARD_TYPE => CARD_TYPE, FE_EMU_EN => 0, CLK_CHIP_SEL => 1, - PLL_SEL => PLL_SEL, GTREFCLKS => GTREFCLKS ) Port map( rst_hw => rst_hw, - rxrecclk40m_out => open, register_map_control => register_map_control, register_map_link_monitor => register_map_link_monitor, CLK40_IN => clk40, -- GREFCLK_IN => clk240, --MT commented unused - RX320_CH0 => open, GTREFCLK_P_s => GTREFCLK_P_in, GTREFCLK_N_s => GTREFCLK_N_in, LMK_P => LMK_P, LMK_N => LMK_N, - RX_LINK_LCK => open, FELIX_DOWNLINK_USER_DATA => lpGBT_DOWNLINK_USER_DATA, FELIX_DOWNLINK_IC_DATA => lpGBT_DOWNLINK_IC_DATA, FELIX_DOWNLINK_EC_DATA => lpGBT_DOWNLINK_EC_DATA, diff --git a/sources/LpGBT/LpGBT_FELIX/BIT_ERROR_CALC.vhd b/sources/LpGBT/LpGBT_FELIX/BIT_ERROR_CALC.vhd index 399f54059b341e7355938a8958b1fb09f7f9b21b..364d1ad90ad9fb4f7653ede8a3719116ea3b0267 100644 --- a/sources/LpGBT/LpGBT_FELIX/BIT_ERROR_CALC.vhd +++ b/sources/LpGBT/LpGBT_FELIX/BIT_ERROR_CALC.vhd @@ -30,7 +30,7 @@ library ieee, UNISIM; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all; -- @suppress "Deprecated package" use ieee.std_logic_1164.all; entity BIT_ERROR_CALC is diff --git a/sources/LpGBT/LpGBT_FELIX/FELIX_LpGBT_Wrapper.vhd b/sources/LpGBT/LpGBT_FELIX/FELIX_LpGBT_Wrapper.vhd index 4d11e5261dc8bd9a019f4bc71d835033128c9852..4d9986fa585624b9ebabbf0e3ec5829537e5a0ed 100644 --- a/sources/LpGBT/LpGBT_FELIX/FELIX_LpGBT_Wrapper.vhd +++ b/sources/LpGBT/LpGBT_FELIX/FELIX_LpGBT_Wrapper.vhd @@ -29,8 +29,8 @@ LIBRARY IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_ARITH.ALL;-- @suppress "Deprecated package" +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" library UNISIM; use UNISIM.VComponents.all; @@ -40,19 +40,19 @@ use work.pcie_package.all; entity FELIX_LpGBT_Wrapper is Generic ( - STABLE_CLOCK_PERIOD : integer := 24; + --STABLE_CLOCK_PERIOD : integer := 24; -- period of the drp_clock GBT_NUM : integer := 24; - PRBS_TEST_EN : integer := 1; - GTHREFCLK_SEL : std_logic := '0'; + --PRBS_TEST_EN : integer := 1; + --GTHREFCLK_SEL : std_logic := '0'; -- GREFCLK : std_logic := '1'; -- MGTREFCLK : std_logic := '0'; - CARD_TYPE : integer := 712; + --CARD_TYPE : integer := 712; FE_EMU_EN : integer := 0; CLK_CHIP_SEL : integer := 1; --tested only with =1 -- SI5345 : integer := 0; -- LMK03200 : integer := 1; - PLL_SEL : std_logic := '0'; + --PLL_SEL : std_logic := '0'; -- CPLL : '0' -- QPLL : '1' GTREFCLKS : integer := 5 @@ -60,20 +60,20 @@ entity FELIX_LpGBT_Wrapper is ); Port ( rst_hw : in std_logic; - rxrecclk40m_out : out std_logic; + --rxrecclk40m_out : out std_logic; register_map_control : in register_map_control_type; register_map_link_monitor : out register_map_link_monitor_type; CLK40_IN : in std_logic; -- GREFCLK_IN : in std_logic; --MT not used - RX320_CH0 : out std_logic; + --RX320_CH0 : out std_logic; GTREFCLK_P_s : in std_logic_vector(GTREFCLKS-1 downto 0); GTREFCLK_N_s : in std_logic_vector(GTREFCLKS-1 downto 0); LMK_P : in std_logic_vector(7 downto 0); LMK_N : in std_logic_vector(7 downto 0); - RX_LINK_LCK : out std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); + --RX_LINK_LCK : out std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); FELIX_DOWNLINK_USER_DATA : in txrx32b_type(0 to GBT_NUM-1); FELIX_DOWNLINK_IC_DATA : in txrx2b_type(0 to GBT_NUM-1); @@ -96,15 +96,15 @@ end FELIX_LpGBT_Wrapper; architecture Behavioral of FELIX_LpGBT_Wrapper is -signal FE_SIDE_RX40MCLK : std_logic; -signal FELIX_SIDE_RX40MCLK : std_logic; -signal PRBS_ERR_CLR : std_logic; +--signal FE_SIDE_RX40MCLK : std_logic; +--signal FELIX_SIDE_RX40MCLK : std_logic; +--signal PRBS_ERR_CLR : std_logic; signal GTH_REFCLK_OUT : std_logic_vector(GBT_NUM-1 downto 0); -signal GTH_EMU_REFCLK_OUT : std_logic_vector(GBT_NUM-1 downto 0); +--signal GTH_EMU_REFCLK_OUT : std_logic_vector(GBT_NUM-1 downto 0); signal CTRL_TXPOLARITY : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); -signal CTRL_RXPOLARITY : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); +--signal CTRL_RXPOLARITY : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); signal CTRL_GBTTXRST : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); signal CTRL_GBTRXRST : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); --signal CTRL_DATARATE : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); @@ -117,11 +117,11 @@ signal MON_TXPMARSTDONE : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 down signal MON_RXCDR_LCK : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); signal MON_CPLL_LCK : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); signal MON_ALIGNMENT_DONE : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); -signal MON_LPGBT_ERRFLG : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); +--signal MON_LPGBT_ERRFLG : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); -signal MON_RXRSTDONE_QUAD : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0); -signal MON_TXRSTDONE_QUAD : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0); -signal MON_RXCDR_LCK_QUAD : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0); +--signal MON_RXRSTDONE_QUAD : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0); +--signal MON_TXRSTDONE_QUAD : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0); +--signal MON_RXCDR_LCK_QUAD : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0); signal MON_QPLL_LCK : std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0); @@ -135,12 +135,12 @@ signal CTRL_GBT_General_ctrl : std_logic_vector(63 downto 0); signal PRBS_ERR_CNT : std_logic_vector(63 downto 0); -signal FE_DOWNLINK_USER_DATA : txrx32b_type(0 to GBT_NUM-1); -signal FE_DOWNLINK_IC_DATA : txrx2b_type(0 to GBT_NUM-1); -signal FE_DOWNLINK_EC_DATA : txrx2b_type(0 to GBT_NUM-1); -signal FE_UPLINK_USER_DATA : txrx224b_type(0 to GBT_NUM-1); -signal FE_UPLINK_EC_DATA : txrx2b_type(0 to GBT_NUM-1); -signal FE_UPLINK_IC_DATA : txrx2b_type(0 to GBT_NUM-1); +--signal FE_DOWNLINK_USER_DATA : txrx32b_type(0 to GBT_NUM-1); +--signal FE_DOWNLINK_IC_DATA : txrx2b_type(0 to GBT_NUM-1); +--signal FE_DOWNLINK_EC_DATA : txrx2b_type(0 to GBT_NUM-1); +--signal FE_UPLINK_USER_DATA : txrx224b_type(0 to GBT_NUM-1); +--signal FE_UPLINK_EC_DATA : txrx2b_type(0 to GBT_NUM-1); +--signal FE_UPLINK_IC_DATA : txrx2b_type(0 to GBT_NUM-1); --MT commented --signal FELIX_DOWNLINK_USER_DATA_s : txrx32b_type(0 to GBT_NUM-1); @@ -152,7 +152,7 @@ signal FE_UPLINK_IC_DATA : txrx2b_type(0 to GBT_NUM-1); --signal FELIX_UPLINK_IC_DATA_s : txrx2b_type(0 to GBT_NUM-1); -- -signal PRBS_CH_SEL : std_logic_vector(7 downto 0); +--signal PRBS_CH_SEL : std_logic_vector(7 downto 0); begin @@ -177,10 +177,10 @@ begin Reference_Clk_Gen : entity work.RefClk_Gen Generic Map( GBT_NUM => GBT_NUM, - GTHREFCLK_SEL => '0', + --GTHREFCLK_SEL => '0', -- GREFCLK : std_logic := '1'; -- MGTREFCLK : std_logic := '0'; - CARD_TYPE => CARD_TYPE, + --CARD_TYPE => CARD_TYPE, FE_EMU_EN => FE_EMU_EN, CLK_CHIP_SEL => CLK_CHIP_SEL -- SI5345 : integer := 0; @@ -218,7 +218,7 @@ begin LMK7_N => LMK_N(7), GTH_REFCLK_OUT => GTH_REFCLK_OUT, - GTH_EMU_REFCLK_OUT => GTH_EMU_REFCLK_OUT + GTH_EMU_REFCLK_OUT => open --GTH_EMU_REFCLK_OUT ); @@ -236,7 +236,7 @@ begin CTRL_TX_DATAPATH_RESET => CTRL_TX_DATAPATH_RESET, CTRL_RX_DATAPATH_RESET => CTRL_RX_DATAPATH_RESET, CTRL_TXPOLARITY => CTRL_TXPOLARITY, - CTRL_RXPOLARITY => CTRL_RXPOLARITY, + CTRL_RXPOLARITY => open, --CTRL_RXPOLARITY, CTRL_GBTTXRST => CTRL_GBTTXRST, CTRL_GBTRXRST => CTRL_GBTRXRST, CTRL_CHANNEL_DISABLE => CTRL_CHANNEL_DISABLE, @@ -246,29 +246,31 @@ begin + CTRL_PRBS_ERR_CLR => open, -- PRBS_ERR_CLR, + CTRL_ERROR_CNT_SEL => open, -- PRBS_CH_SEL, MON_RXRSTDONE => MON_RXRSTDONE, MON_TXRSTDONE => MON_TXRSTDONE, - MON_RXRSTDONE_QUAD => MON_RXRSTDONE_QUAD, - MON_TXRSTDONE_QUAD => MON_TXRSTDONE_QUAD, + --MON_RXRSTDONE_QUAD => MON_RXRSTDONE_QUAD, + --MON_TXRSTDONE_QUAD => MON_TXRSTDONE_QUAD, MON_RXPMARSTDONE => MON_RXPMARSTDONE, MON_TXPMARSTDONE => MON_TXPMARSTDONE, MON_RXCDR_LCK => MON_RXCDR_LCK, - MON_RXCDR_LCK_QUAD => MON_RXCDR_LCK_QUAD, + --MON_RXCDR_LCK_QUAD => MON_RXCDR_LCK_QUAD, MON_QPLL_LCK => MON_QPLL_LCK, MON_CPLL_LCK => MON_CPLL_LCK, MON_ALIGNMENT_DONE => MON_ALIGNMENT_DONE, - MON_LPGBT_ERRFLG => MON_LPGBT_ERRFLG, + --MON_LPGBT_ERRFLG => MON_LPGBT_ERRFLG, MON_PRBS_ERRCNT => PRBS_ERR_CNT, - CTRL_PRBS_ERR_CLR => PRBS_ERR_CLR, - CTRL_ERROR_CNT_SEL => PRBS_CH_SEL, register_map_control => register_map_control, register_map_link_monitor => register_map_link_monitor ); + + PRBS_ERR_CNT <= (others => '0'); --MT commented: FE will live in FELIG --PRBS_TEST: if PRBS_TEST_EN = 1 generate @@ -322,18 +324,6 @@ begin ) Port map( - clk40_in => clk40_in, - rst_hw => rst_hw, - FELIX_SIDE_RX40MCLK => FELIX_SIDE_RX40MCLK, - - GTHREFCLK => GTH_REFCLK_OUT, - - - RX_P => RX_P(GBT_NUM-1 downto 0), - RX_N => RX_N(GBT_NUM-1 downto 0), - TX_P => TX_P(GBT_NUM-1 downto 0), - TX_N => TX_N(GBT_NUM-1 downto 0), - FELIX_DOWNLINK_USER_DATA => FELIX_DOWNLINK_USER_DATA, --MT _s, FELIX_DOWNLINK_EC_DATA => FELIX_DOWNLINK_EC_DATA, --_s, FELIX_DOWNLINK_IC_DATA => FELIX_DOWNLINK_IC_DATA, --_s, @@ -342,6 +332,17 @@ begin FELIX_UPLINK_EC_DATA => FELIX_UPLINK_EC_DATA, --_s, FELIX_UPLINK_IC_DATA => FELIX_UPLINK_IC_DATA, --_s, + clk40_in => CLK40_IN, + rst_hw => rst_hw, + FELIX_SIDE_RX40MCLK => open, --FELIX_SIDE_RX40MCLK, + + RX_P => RX_P(GBT_NUM-1 downto 0), + RX_N => RX_N(GBT_NUM-1 downto 0), + TX_P => TX_P(GBT_NUM-1 downto 0), + TX_N => TX_N(GBT_NUM-1 downto 0), + + GTHREFCLK => GTH_REFCLK_OUT, + CTRL_SOFT_RESET => CTRL_SOFT_RESET(GBT_NUM/4-1 downto 0), CTRL_TXPLL_DATAPATH_RESET => CTRL_TXPLL_DATAPATH_RESET(GBT_NUM/4-1 downto 0), CTRL_RXPLL_DATAPATH_RESET => CTRL_RXPLL_DATAPATH_RESET(GBT_NUM/4-1 downto 0), @@ -360,17 +361,17 @@ begin MON_RXRSTDONE => MON_RXRSTDONE(GBT_NUM-1 downto 0), MON_TXRSTDONE => MON_TXRSTDONE(GBT_NUM-1 downto 0), - MON_RXRSTDONE_QUAD => MON_RXRSTDONE_QUAD(GBT_NUM/4-1 downto 0), - MON_TXRSTDONE_QUAD => MON_TXRSTDONE_QUAD(GBT_NUM/4-1 downto 0), + MON_RXRSTDONE_QUAD => open, --MON_RXRSTDONE_QUAD(GBT_NUM/4-1 downto 0), + MON_TXRSTDONE_QUAD => open, --MON_TXRSTDONE_QUAD(GBT_NUM/4-1 downto 0), MON_RXPMARSTDONE => MON_RXPMARSTDONE(GBT_NUM-1 downto 0), MON_TXPMARSTDONE => MON_TXPMARSTDONE(GBT_NUM-1 downto 0), MON_RXCDR_LCK => MON_RXCDR_LCK(GBT_NUM-1 downto 0), - MON_RXCDR_LCK_QUAD => MON_RXCDR_LCK_QUAD(GBT_NUM/4-1 downto 0), + MON_RXCDR_LCK_QUAD => open, --open, --MON_RXCDR_LCK_QUAD(GBT_NUM/4-1 downto 0), MON_QPLL_LCK => MON_QPLL_LCK(GBT_NUM/4-1 downto 0), MON_CPLL_LCK => MON_CPLL_LCK(GBT_NUM-1 downto 0), MON_ALIGNMENT_DONE => MON_ALIGNMENT_DONE(GBT_NUM-1 downto 0), - MON_LPGBT_ERRFLG => MON_LPGBT_ERRFLG(GBT_NUM-1 downto 0) + MON_LPGBT_ERRFLG => open --MON_LPGBT_ERRFLG(GBT_NUM-1 downto 0) ); --MT commented: FE will live in FELIG diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE.vhd index 11ba0b332d17c9d5c7717e610f58792446998621..8e9c86a94aaed862f6d2fae4b18663571348a9db 100644 --- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE.vhd +++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE.vhd @@ -32,8 +32,8 @@ LIBRARY IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_ARITH.ALL;-- @suppress "Deprecated package" +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" @@ -47,20 +47,20 @@ entity FLX_LpGBT_BE is downlinkEcData_i : in std_logic_vector(1 downto 0); downlinkIcData_i : in std_logic_vector(1 downto 0); TXCLK40 : in std_logic; - RXCLK40 : in std_logic; + --RXCLK40 : in std_logic; TXCLK320 : in std_logic; RXCLK320m : in std_logic; uplinkSelectFEC_i : in std_logic; data_rdy : out std_logic; Tx_scrambler_bypass : in std_logic; Tx_Interleaver_bypass : in std_logic; - phase_sel : in std_logic_vector(2 downto 0); + --phase_sel : in std_logic_vector(2 downto 0); Tx_FEC_bypass : in std_logic; TxData_Out : out std_logic_vector(15 downto 0); rxdatain : in std_logic_vector(31 downto 0); GBT_TX_RST : in std_logic; GBT_RX_RST : in std_logic; - rst_patternsearch : in std_logic; + --rst_patternsearch : in std_logic; -- uplinkSelectDataRate_i : in std_logic; --MT now hard coded to 1024Gbps uplinkBypassInterleaver_i : in std_logic; uplinkBypassFECEncoder_i : in std_logic; @@ -74,7 +74,7 @@ entity FLX_LpGBT_BE is sta_headeLocked_o : out std_logic; sta_headerFlag_o : out std_logic; ctr_clkSlip_o : out std_logic; - sta_rxGbRdy_o : out std_logic; + --sta_rxGbRdy_o : out std_logic; uplinkReady_o : out std_logic; uplinkUserData_o : out std_logic_vector(229 downto 0); @@ -93,55 +93,55 @@ signal cnt : std_logic_vector(2 downto 0); signal TxData_Interleaved : std_logic_vector(63 downto 0); signal TxData_Interleaved_inv : std_logic_vector(63 downto 0); signal TxData_Interleaved_latched : std_logic_vector(63 downto 0); -signal ctr_clkSlip_5g12_s : std_logic; -signal ctr_clkSlip_10g24_s : std_logic; -signal sta_headeLocked_10g24_s : std_logic; -signal sta_headeLocked_5g12_s : std_logic; -signal sta_headerFlag_5g12_s : std_logic; -signal sta_headerFlag_10g24_s : std_logic; -signal clk_dataFlag_rxgearbox_5g12_s : std_logic; -signal rst_rxgearbox_10g24_s : std_logic; -signal rst_rxgearbox_5g12_s : std_logic; -signal clk_dataFlag_rxgearbox_10g24_s : std_logic; -signal uplinkFrame_from_rxgb_s : std_logic_vector(255 downto 0); -signal uplinkFrame_from_5g12_rxgb_s : std_logic_vector(255 downto 0); -signal uplinkFrame_from_10g24_rxgb_s : std_logic_vector(255 downto 0); -signal dat_upLinkWord_fromMgt_s256_1024 : std_logic_vector(255 downto 0); -signal dat_upLinkWord_fromGb_s1024_buf : std_logic_vector(255 downto 0); -signal sta_rxGbRdy_5g12_s : std_logic; -signal sta_rxGbRdy_10g24_s : std_logic; -signal clk_dataFlag_rxgearbox_s : std_logic; -signal uplinkUserData_s : std_logic_vector(229 downto 0); -signal uplinkEcData_s : std_logic_vector(1 downto 0); -signal uplinkIcData_s : std_logic_vector(1 downto 0); -signal uplinkReady_s : std_logic; +--signal ctr_clkSlip_5g12_s : std_logic; +--signal ctr_clkSlip_10g24_s : std_logic; +--signal sta_headeLocked_10g24_s : std_logic; +--signal sta_headeLocked_5g12_s : std_logic; +--signal sta_headerFlag_5g12_s : std_logic; +--signal sta_headerFlag_10g24_s : std_logic; +--signal clk_dataFlag_rxgearbox_5g12_s : std_logic; +--signal rst_rxgearbox_10g24_s : std_logic; +--signal rst_rxgearbox_5g12_s : std_logic; +--signal clk_dataFlag_rxgearbox_10g24_s : std_logic; +--signal uplinkFrame_from_rxgb_s : std_logic_vector(255 downto 0); +--signal uplinkFrame_from_5g12_rxgb_s : std_logic_vector(255 downto 0); +--signal uplinkFrame_from_10g24_rxgb_s : std_logic_vector(255 downto 0); +--signal dat_upLinkWord_fromMgt_s256_1024 : std_logic_vector(255 downto 0); +--signal dat_upLinkWord_fromGb_s1024_buf : std_logic_vector(255 downto 0); +--signal sta_rxGbRdy_5g12_s : std_logic; +--signal sta_rxGbRdy_10g24_s : std_logic; +--signal clk_dataFlag_rxgearbox_s : std_logic; +--signal uplinkUserData_s : std_logic_vector(229 downto 0); +--signal uplinkEcData_s : std_logic_vector(1 downto 0); +--signal uplinkIcData_s : std_logic_vector(1 downto 0); +--signal uplinkReady_s : std_logic; signal TXCLK40_r : std_logic; signal data_rdy_or : std_logic; signal data_rdy_o : std_logic; signal downLinkData_s : std_logic_vector(35 downto 0); -signal TxData_Out_i : std_logic_vector(31 downto 0); +--signal TxData_Out_i : std_logic_vector(31 downto 0); signal dat_upLinkWord_fromMgt_s32_1024 : std_logic_vector(31 downto 0); -signal dat_upLinkWord_fromMgt_s128_512 : std_logic_vector(127 downto 0); -signal dat_upLinkWord_fromGb_s512_buf : std_logic_vector(127 downto 0); -signal count_rx : std_logic_vector(2 downto 0); -signal count_rx2 : std_logic_vector(2 downto 0); +--signal dat_upLinkWord_fromMgt_s128_512 : std_logic_vector(127 downto 0); +--signal dat_upLinkWord_fromGb_s512_buf : std_logic_vector(127 downto 0); +--signal count_rx : std_logic_vector(2 downto 0); +--signal count_rx2 : std_logic_vector(2 downto 0); signal TxData_Out_8 : std_logic_vector(7 downto 0); -signal dat_upLinkWord_fromMgt_s16_512 : std_logic_vector(15 downto 0); -signal sta_headerFlag_5g12_s_vec : std_logic_vector(9 downto 0); -signal sta_headerFlag_10g24_s_vec : std_logic_vector(9 downto 0); -signal sta_headerFlag_s512 : std_logic; -signal RXCLK40_r : std_logic; -signal sel : std_logic; -signal sel2 : std_logic; -signal sta_headerFlag_s512_r1 : std_logic; -signal sta_headerFlag_s1024 : std_logic; -signal sta_headerFlag_s512_r2 : std_logic; -signal sta_headerFlag_s512_r3 : std_logic; -signal sta_headerFlag_s512_r4 : std_logic; -signal sta_headerFlag_s1024_r4 : std_logic; -signal sta_headerFlag_s1024_r3 : std_logic; -signal sta_headerFlag_s1024_r2 : std_logic; -signal sta_headerFlag_s1024_r1 : std_logic; +--signal dat_upLinkWord_fromMgt_s16_512 : std_logic_vector(15 downto 0); +--signal sta_headerFlag_5g12_s_vec : std_logic_vector(9 downto 0); +--signal sta_headerFlag_10g24_s_vec : std_logic_vector(9 downto 0); +--signal sta_headerFlag_s512 : std_logic; +--signal RXCLK40_r : std_logic; +--signal sel : std_logic; +--signal sel2 : std_logic; +--signal sta_headerFlag_s512_r1 : std_logic; +--signal sta_headerFlag_s1024 : std_logic; +--signal sta_headerFlag_s512_r2 : std_logic; +--signal sta_headerFlag_s512_r3 : std_logic; +--signal sta_headerFlag_s512_r4 : std_logic; +--signal sta_headerFlag_s1024_r4 : std_logic; +--signal sta_headerFlag_s1024_r3 : std_logic; +--signal sta_headerFlag_s1024_r2 : std_logic; +--signal sta_headerFlag_s1024_r1 : std_logic; signal uplinkUserData_fec12_s : std_logic_vector(229 downto 0); signal uplinkEcData_fec12_s : std_logic_vector(1 downto 0); @@ -169,6 +169,9 @@ begin TxData_Out_8(0) & TxData_Out_8(0); lpgbtfpga_scrambler_inst: entity work.lpgbtfpga_scrambler + generic map( + INIT_SEED => x"1fba847af" + ) port map ( clk_i => TXCLK40, @@ -252,9 +255,9 @@ begin dat_upLinkWord_fromMgt_s32_1024 <= rxdatain(31 downto 0); - process(RxClk320m) + process(RXCLK320m) begin - if RxClk320m'event and RxClk320m='1' then + if RXCLK320m'event and RXCLK320m='1' then data_rdy_or <= data_rdy_o; data_rdy <= data_rdy_or; end if; @@ -280,7 +283,7 @@ begin ) port map ( - uplinkClk_i => RxClk320m, + uplinkClk_i => RXCLK320m, uplinkClkOutEn_o => open, uplinkRst_n_i => not(GBT_RX_RST), @@ -330,7 +333,7 @@ begin ) port map ( - uplinkClk_i => RxClk320m, + uplinkClk_i => RXCLK320m, uplinkClkOutEn_o => data_rdy_o, uplinkRst_n_i => not(GBT_RX_RST), diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE_Wrapper.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE_Wrapper.vhd index e8860de6cbcde433c0b3b4d4b63bf68d743bc50f..d894ed20f685fed50f399dc7bd323394357569a9 100644 --- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE_Wrapper.vhd +++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE_Wrapper.vhd @@ -29,8 +29,8 @@ LIBRARY IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_ARITH.ALL;-- @suppress "Deprecated package" +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" library UNISIM; use UNISIM.VComponents.all; @@ -144,7 +144,7 @@ signal GT_RX_WORD_CLK : std_logic_vector(GBT_NUM-1 downto 0); signal rxresetdone : std_logic_vector(GBT_NUM-1 downto 0); signal data_rdy : std_logic_vector(GBT_NUM-1 downto 0); signal RxSlide : std_logic_vector(GBT_NUM-1 downto 0); -signal UplinkRdy : std_logic_vector(GBT_NUM-1 downto 0); +--signal UplinkRdy : std_logic_vector(GBT_NUM-1 downto 0); signal fifo_rst : std_logic_vector(GBT_NUM-1 downto 0); signal fifo_empty : std_logic_vector(GBT_NUM-1 downto 0); signal fifo_rden : std_logic_vector(GBT_NUM-1 downto 0); @@ -245,42 +245,34 @@ gbtRxTx : for i in 0 to GBT_NUM-1 generate lpgbt_inst: entity work.FLX_LpGBT_BE Port map ( - downlinkUserData_i => downlinkUserData_i(i), - downlinkEcData_i => downlinkEcData_i(i), - downlinkIcData_i => downlinkIcData_i(i), - TXCLK40 => clk40_in, - RXCLK40 => rxrecclk40m, - TXCLK320 => GT_TX_WORD_CLK(i), - rxclk320m => GT_RX_WORD_CLK(i), - Tx_scrambler_bypass =>'0', - Tx_Interleaver_bypass => '0', - Tx_FEC_bypass => '0', - TxData_Out => TX_DATA_16b(i), - rxdatain => RX_DATA_32b(i), - GBT_TX_RST => TX_RESET_i(i), - gbt_rx_rst => RX_RESET_i(i), - rst_patternsearch => not rxresetdone(i), --- uplinkSelectDataRate_i => CTRL_DATARATE(i), - uplinkSelectFEC_i => CTRL_FECMODE(i), - uplinkBypassInterleaver_i => GBT_General_ctrl(35), - uplinkBypassFECEncoder_i => GBT_General_ctrl(36), - uplinkBypassScrambler_i => GBT_General_ctrl(37), - phase_sel => "100", - data_rdy => data_rdy(i), - --- sta_headeLocked_s => alignment_done_f(i), --- sta_headerFlag_s => open, --- ctr_clkSlip_s => RxSlide(i), --- sta_rxGbRdy_s => open, - - sta_headeLocked_o => alignment_done_f(i), - sta_headerFlag_o => open, - ctr_clkSlip_o => RxSlide(i), - sta_rxGbRdy_o => open, - uplinkReady_o => UplinkRdy(i), - uplinkUserData_o => uplinkData_i(i)(229 downto 0), - uplinkEcData_o => uplinkData_i(i)(231 downto 230), - uplinkIcData_o => uplinkData_i(i)(233 downto 232) + downlinkUserData_i => downlinkUserData_i(i), + downlinkEcData_i => downlinkEcData_i(i), + downlinkIcData_i => downlinkIcData_i(i), + TXCLK40 => clk40_in, + --RXCLK40 => rxrecclk40m, + TXCLK320 => GT_TX_WORD_CLK(i), + RXCLK320m => GT_RX_WORD_CLK(i), + uplinkSelectFEC_i => CTRL_FECMODE(i), + --phase_sel => "100", + data_rdy => data_rdy(i), + Tx_scrambler_bypass => '0', + Tx_Interleaver_bypass => '0', + Tx_FEC_bypass => '0', + TxData_Out => TX_DATA_16b(i), + rxdatain => RX_DATA_32b(i), + GBT_TX_RST => TX_RESET_i(i), + GBT_RX_RST => RX_RESET_i(i), + uplinkBypassInterleaver_i => GBT_General_ctrl(35), + uplinkBypassFECEncoder_i => GBT_General_ctrl(36), + uplinkBypassScrambler_i => GBT_General_ctrl(37), + sta_headeLocked_o => alignment_done_f(i), + sta_headerFlag_o => open, + ctr_clkSlip_o => RxSlide(i), + --sta_rxGbRdy_o => open, + uplinkReady_o => open, --UplinkRdy(i), + uplinkUserData_o => uplinkData_i(i)(229 downto 0), + uplinkEcData_o => uplinkData_i(i)(231 downto 230), + uplinkIcData_o => uplinkData_i(i)(233 downto 232) ); @@ -332,28 +324,28 @@ rxclkgen_inst: rxclkgen ); clk_generate : for i in 0 to GBT_NUM-1 generate - GTTXOUTCLK_BUFG: bufg_gt + GTTXOUTCLK_BUFG: bufg_gt -- @suppress "Generic map uses default values. Missing optional actuals: SIM_DEVICE, STARTUP_SYNC" port map( - i => GT_TXOUTCLK(i), - div => "000", - clr => '0', - cemask => '0', + o => GT_TXUSRCLK(i), + ce => '1', + cemask => '0', + clr => '0', clrmask => '0', - ce => '1', - o => GT_TXUSRCLK(i) + div => "000", + i => GT_TXOUTCLK(i) ); GT_TX_WORD_CLK(i) <= GT_TXUSRCLK(i); - GTRXOUTCLK_BUFG: bufg_gt + GTRXOUTCLK_BUFG: bufg_gt -- @suppress "Generic map uses default values. Missing optional actuals: SIM_DEVICE, STARTUP_SYNC" port map( - i => GT_RXOUTCLK(i), - div => "000", - clr => '0', - cemask => '0', + o => GT_RXUSRCLK(i), + ce => '1', + cemask => '0', + clr => '0', clrmask => '0', - ce => '1', - o => GT_RXUSRCLK(i) + div => "000", + i => GT_RXOUTCLK(i) ); GT_RX_WORD_CLK(i) <= GT_RXUSRCLK(i); @@ -378,55 +370,47 @@ GTH_inst : for i in 0 to (GBT_NUM-1)/4 generate GTH_TOP_INST: entity work.FLX_LpGBT_GTH_BE Port map ( - gthrxn_in => RX_N_i(4*i+3 downto 4*i), - gthrxp_in => RX_P_i(4*i+3 downto 4*i), - gthtxn_out => TX_N_i(4*i+3 downto 4*i), - gthtxp_out => TX_P_i(4*i+3 downto 4*i), - - drpclk_in => drpclk_vec(i downto i), - gtrefclk0_in => GTHREFCLK(4*i downto 4*i), - gt_rxusrclk_in => GT_RX_WORD_CLK(4*i+3 downto 4*i), - gt_rxoutclk_out => GT_RXOUTCLK(4*i+3 downto 4*i), - gt_txusrclk_in => GT_TX_WORD_CLK(4*i+3 downto 4*i), - gt_txoutclk_out => GT_TXOUTCLK(4*i+3 downto 4*i), - - userdata_tx_in => TX_DATA_64b(i), - userdata_rx_out => RX_DATA_128b(i), - rxpolarity_in => CTRL_RXPOLARITY(4*i+3 downto 4*i), - txpolarity_in => CTRL_TXPOLARITY(4*i+3 downto 4*i), - - loopback_in => "000", - rxcdrhold_in => '0', - - userclk_rx_reset_in => userclk_rx_reset_in(i downto i),--(others=>(not rxpmaresetdone_out(i))),--locked, - userclk_tx_reset_in => userclk_tx_reset_in(i downto i),--(others=>(not txpmaresetdone_out(i))),--,--locked, - - - reset_all_in => CTRL_SOFT_RESET(i downto i), - reset_tx_pll_and_datapath_in => CTRL_TXPLL_DATAPATH_RESET(i downto i), - reset_tx_datapath_in => CTRL_TX_DATAPATH_RESET(i downto i), - reset_rx_pll_and_datapath_in => CTRL_RXPLL_DATAPATH_RESET(i downto i), - reset_rx_datapath_in => RX_DATAPATH_RESET_FINL(i downto i),--CTRL_RX_DATAPATH_RESET(i downto i),-- may need to add auto reset in the future? - - qpll0lock_out => open, - qpll1lock_out => MON_QPLL_LCK(i downto i), - qpll1fbclklost_out => open,-- - qpll0fbclklost_out => open, - rxslide_in => RxSlide(4*i+3 downto 4*i), - cplllock_out => MON_CPLL_LCK(4*i+3 downto 4*i), - - rxresetdone_out => rxresetdone(4*i+3 downto 4*i), - txresetdone_out => txresetdone(4*i+3 downto 4*i), - rxpmaresetdone_out => rxpmaresetdone(4*i+3 downto 4*i), - txpmaresetdone_out => txpmaresetdone(4*i+3 downto 4*i), - reset_tx_done_out => txresetdone_quad(i downto i), - reset_rx_done_out => rxresetdone_quad(i downto i), - reset_rx_cdr_stable_out => RxCdrLock_quad(i downto i), - rxcdrlock_out => rxcdrlock_out(4*i+3 downto 4*i) + gt_rxusrclk_in => GT_RX_WORD_CLK(4*i+3 downto 4*i), + gt_txusrclk_in => GT_TX_WORD_CLK(4*i+3 downto 4*i), + gt_rxoutclk_out => GT_RXOUTCLK(4*i+3 downto 4*i), + gt_txoutclk_out => GT_TXOUTCLK(4*i+3 downto 4*i), + gthrxn_in => RX_N_i(4*i+3 downto 4*i), + gthrxp_in => RX_P_i(4*i+3 downto 4*i), + gthtxn_out => TX_N_i(4*i+3 downto 4*i), + gthtxp_out => TX_P_i(4*i+3 downto 4*i), + drpclk_in => drpclk_vec(i downto i), + gtrefclk0_in => GTHREFCLK(4*i downto 4*i), + rxpolarity_in => CTRL_RXPOLARITY(4*i+3 downto 4*i), + txpolarity_in => CTRL_TXPOLARITY(4*i+3 downto 4*i), + loopback_in => "000", + rxcdrhold_in => '0', + userdata_tx_in => TX_DATA_64b(i), + userdata_rx_out => RX_DATA_128b(i), + userclk_rx_reset_in => userclk_rx_reset_in(i downto i), --(others=>(not rxpmaresetdone_out(i))),--locked, + userclk_tx_reset_in => userclk_tx_reset_in(i downto i), --(others=>(not txpmaresetdone_out(i))),--,--locked, + reset_all_in => CTRL_SOFT_RESET(i downto i), + reset_tx_pll_and_datapath_in => CTRL_TXPLL_DATAPATH_RESET(i downto i), + reset_tx_datapath_in => CTRL_TX_DATAPATH_RESET(i downto i), + reset_rx_pll_and_datapath_in => CTRL_RXPLL_DATAPATH_RESET(i downto i), + reset_rx_datapath_in => RX_DATAPATH_RESET_FINL(i downto i), --CTRL_RX_DATAPATH_RESET(i downto i),-- may need to add auto reset in the future? + qpll1lock_out => MON_QPLL_LCK(i downto i), + qpll1fbclklost_out => open, -- + qpll0lock_out => open, + qpll0fbclklost_out => open, + rxslide_in => RxSlide(4*i+3 downto 4*i), + txresetdone_out => TxResetDone(4*i+3 downto 4*i), + txpmaresetdone_out => txpmaresetdone(4*i+3 downto 4*i), + rxresetdone_out => rxresetdone(4*i+3 downto 4*i), + rxpmaresetdone_out => rxpmaresetdone(4*i+3 downto 4*i), + reset_tx_done_out => txresetdone_quad(i downto i), + reset_rx_done_out => rxresetdone_quad(i downto i), + reset_rx_cdr_stable_out => RxCdrLock_quad(i downto i), + rxcdrlock_out => rxcdrlock_out(4*i+3 downto 4*i), + cplllock_out => MON_CPLL_LCK(4*i+3 downto 4*i) ); MON_RXRSTDONE(4*i+3 downto 4*i) <= rxresetdone(4*i+3 downto 4*i); - MON_TXRSTDONE(4*i+3 downto 4*i) <= txresetdone(4*i+3 downto 4*i); + MON_TXRSTDONE(4*i+3 downto 4*i) <= TxResetDone(4*i+3 downto 4*i); MON_RXRSTDONE_QUAD(i downto i) <= rxresetdone_quad(i downto i); MON_TXRSTDONE_QUAD(i downto i) <= txresetdone_quad(i downto i); MON_RXPMARSTDONE(4*i+3 downto 4*i) <= rxpmaresetdone(4*i+3 downto 4*i); diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE.vhd index 41ed36e3795de1b29be759ac055fa7af32bfd458..64d6ead111240aa6087d9682f8374122de760323 100644 --- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE.vhd +++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE.vhd @@ -30,8 +30,8 @@ LIBRARY IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_ARITH.ALL;-- @suppress "Deprecated package" +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" -- Uncomment the following library declaration if using @@ -51,18 +51,18 @@ entity FLX_LpGBT_FE is clk_mgtRxUsrclk_s : in std_logic; clk_mgtTxUsrclk_s : in std_logic; rst_uplink_i : in std_logic; - uplinkClkEn_i : in std_logic; + --uplinkClkEn_i : in std_logic; ctr_clkSlip_s : out std_logic; aligned : out std_logic; - uplinkRdy_o : out std_logic; - downlinkRdy_o : out std_logic; + --uplinkRdy_o : out std_logic; + --downlinkRdy_o : out std_logic; sta_headerFlag_o : out std_logic; sta_headerFlag_shift : out std_logic; - sta_rxgbxRdy_o : out std_logic; + --sta_rxgbxRdy_o : out std_logic; clk_dataFlag_rxGb_s_o : out std_logic; dat_upLinkWord_fromGb_s : out std_logic_vector(31 downto 0); dat_downLinkWord_fromMgt_s16 : in std_logic_vector(15 downto 0); - sta_mgtTxRdy_s : in std_logic; + --sta_mgtTxRdy_s : in std_logic; rst_dnlink_i : in std_logic; sta_mgtRxRdy_s : in std_logic; @@ -91,8 +91,8 @@ end FLX_LpGBT_FE; architecture Behavioral of FLX_LpGBT_FE is - signal clk_mgtTxUsrclkToEmul_s : std_logic; - signal clk_mgtRxUsrclkToEmul_s : std_logic; + --signal clk_mgtTxUsrclkToEmul_s : std_logic; + --signal clk_mgtRxUsrclkToEmul_s : std_logic; signal rst_pattsearch_s : std_logic; @@ -101,41 +101,41 @@ architecture Behavioral of FLX_LpGBT_FE is signal sta_headerFlag_s_r1 : std_logic; signal sta_headerFlag_s_r2 : std_logic; - signal sta_rxgbxRdy_s : std_logic; + --signal sta_rxgbxRdy_s : std_logic; signal sta_headerFlag_s_r3 : std_logic; signal sta_headerFlag_s_r4 : std_logic; - signal rstn_datapath_s : std_logic; - signal rst_datapath_s : std_logic; + --signal rstn_datapath_s : std_logic; + --signal rst_datapath_s : std_logic; signal dat_downLinkWord_fromGb_s : std_logic_vector(63 downto 0); - signal dat_downLinkWord_fromGbInv_s : std_logic_vector(63 downto 0); + --signal dat_downLinkWord_fromGbInv_s : std_logic_vector(63 downto 0); signal dat_downLinkWord_toPattSrch_s : std_logic_vector(15 downto 0); - signal downlinkRdy_s0 : std_logic; - signal downlinkRdy_s1 : std_logic; + --signal downlinkRdy_s0 : std_logic; + --signal downlinkRdy_s1 : std_logic; - signal uplinkClkEn_sh_s : std_logic; - signal uplinkClkEn_shgb_s : std_logic; - signal sta_txGbRdy_s : std_logic; + --signal uplinkClkEn_sh_s : std_logic; + --signal uplinkClkEn_shgb_s : std_logic; + --signal sta_txGbRdy_s : std_logic; signal dat_upLinkWord_fromLpGBT_s : std_logic_vector(255 downto 0); - signal dat_upLinkWord_fromLpGBT_pipeline_s : std_logic_vector(255 downto 0); - signal dat_upLinkWord_toGb_s : std_logic_vector(255 downto 0); + --signal dat_upLinkWord_fromLpGBT_pipeline_s : std_logic_vector(255 downto 0); + --signal dat_upLinkWord_toGb_s : std_logic_vector(255 downto 0); signal dat_upLinkWord_toGb_pipeline_s : std_logic_vector(255 downto 0); signal dat_upLinkWord_toGb_pipeline_s_r : std_logic_vector(255 downto 0); signal dat_upLinkWord_toGb_pipeline_s_inv : std_logic_vector(255 downto 0); - signal rst_uplinkGb_s : std_logic; + --signal rst_uplinkGb_s : std_logic; signal RXCLK40_r : std_logic; - signal rst_uplinkGb_synch_s : std_logic; - signal rst_uplinkMgt_s : std_logic; + --signal rst_uplinkGb_synch_s : std_logic; + --signal rst_uplinkMgt_s : std_logic; signal sel : std_logic; - signal rst_uplinkInitDone_s : std_logic; - signal rst_downlinkInitDone_s : std_logic; + --signal rst_uplinkInitDone_s : std_logic; + --signal rst_downlinkInitDone_s : std_logic; - signal RX_CLKEn_s : std_logic; - signal RX_CLK40_s : std_logic; + --signal RX_CLKEn_s : std_logic; + --signal RX_CLK40_s : std_logic; signal TXCLK40_r : std_logic; signal downLinkDataIc_s : std_logic_vector(1 downto 0); @@ -143,7 +143,7 @@ architecture Behavioral of FLX_LpGBT_FE is signal downLinkDataGroup1_s : std_logic_vector(15 downto 0); signal downLinkDataGroup0_s : std_logic_vector(15 downto 0); - signal clk_dataFlag_rxGb_s : std_logic; + constant clk_dataFlag_rxGb_s : std_logic := '0'; signal txcnt : std_logic_vector(2 downto 0); signal count_rx : std_logic_vector(2 downto 0); signal upLinkData0_s : std_logic_vector(31 downto 0); @@ -154,13 +154,13 @@ architecture Behavioral of FLX_LpGBT_FE is signal upLinkData5_s : std_logic_vector(31 downto 0); signal dat_downLinkWord_fromMgt_s : std_logic_vector(31 downto 0); signal upLinkData6_s : std_logic_vector(31 downto 0); - signal upLinkDataIC_s : std_logic_vector(1 downto 0); - signal upLinkDataEC_s : std_logic_vector(1 downto 0); + --signal upLinkDataIC_s : std_logic_vector(1 downto 0); + --signal upLinkDataEC_s : std_logic_vector(1 downto 0); signal dat_downLinkWord_fromMgt_s64 : std_logic_vector(63 downto 0); signal dat_downLinkWord_fromGb_s_buf : std_logic_vector(63 downto 0); signal dat_downLinkWord_fromMgt_s8 : std_logic_vector(7 downto 0); - COMPONENT LpGBT_Model_dataPath + COMPONENT LpGBT_Model_dataPath --@suppress PORT ( -- Clock upClki : in std_logic; @@ -210,7 +210,7 @@ architecture Behavioral of FLX_LpGBT_FE is signal sta_headerFlag_s_vec: std_logic_vector(9 downto 0); signal sta_headerFlag_s0: std_logic; - COMPONENT mgt_framealigner + COMPONENT mgt_framealigner--@suppress generic ( c_wordRatio : integer; c_headerPattern : std_logic_vector; @@ -271,21 +271,21 @@ begin aligned <= sta_headeLocked_s; sta_headerFlag_o <= sta_headerFlag_s0; sta_headerFlag_shift <= sta_headerFlag_s; - sta_rxgbxRdy_o <= sta_rxgbxRdy_s; + --sta_rxgbxRdy_o <= sta_rxgbxRdy_s; clk_dataFlag_rxGb_s_o <= clk_dataFlag_rxGb_s; downLinkData(15 downto 0) <= downLinkDataGroup0_s; downLinkData(31 downto 16) <= downLinkDataGroup1_s; - downLinkDataEc <= downLinkDataEc_s; - downLinkDataIc <= downLinkDataIc_s; + downLinkDataEC <= downLinkDataEc_s; + downLinkDataIC <= downLinkDataIc_s; rst_pattsearch_s <= not(sta_mgtRxRdy_s); - rst_datapath_s <= not(sta_headeLocked_s); + --rst_datapath_s <= not(sta_headeLocked_s); - rst_uplinkGb_s <= rst_uplink_i or not(sta_mgtTxRdy_s);-- or not(sta_headeLocked_s); + --rst_uplinkGb_s <= rst_uplink_i or not(sta_mgtTxRdy_s);-- or not(sta_headeLocked_s); - uplinkRdy_o <= sta_txGbRdy_s; + --uplinkRdy_o <= sta_txGbRdy_s; -- Pattern aligner @@ -298,6 +298,7 @@ begin c_allowedFalseHeader => 32, c_allowedFalseHeaderOverN => 40, c_requiredTrueHeader => 30, + c_resetOnEven => 0, c_bitslip_mindly => 40 ) port map ( @@ -444,8 +445,8 @@ begin upLinkData4_s <= upLinkData(159 downto 128); upLinkData5_s <= upLinkData(191 downto 160); upLinkData6_s <= upLinkData(223 downto 192); - upLinkDataIC_s <= upLinkDataIC; - upLinkDataEC_s <= upLinkDataEC; + --upLinkDataIC_s <= upLinkDataIC; + --upLinkDataEC_s <= upLinkDataEC; -- LpGBT Model LpGBT_Model_dataPath_inst: LpGBT_Model_dataPath diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE_Wrapper.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE_Wrapper.vhd index 7271e79a93a8438ac3cdf7c07ed5079191202ef0..06b489f8998d87885ad3c1a9ac9a2b7982636bee 100644 --- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE_Wrapper.vhd +++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_FE_Wrapper.vhd @@ -29,8 +29,8 @@ LIBRARY IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_ARITH.ALL;-- @suppress "Deprecated package" +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" library UNISIM; use UNISIM.VComponents.all; @@ -143,9 +143,9 @@ signal TxResetDone : std_logic_vector(GBT_NUM-1 downto 0); signal GT_TX_WORD_CLK : std_logic_vector(GBT_NUM-1 downto 0); signal GT_RX_WORD_CLK : std_logic_vector(GBT_NUM-1 downto 0); signal rxresetdone : std_logic_vector(GBT_NUM-1 downto 0); -signal data_rdy : std_logic_vector(GBT_NUM-1 downto 0); +--signal data_rdy : std_logic_vector(GBT_NUM-1 downto 0); signal RxSlide : std_logic_vector(GBT_NUM-1 downto 0); -signal UplinkRdy : std_logic_vector(GBT_NUM-1 downto 0); +--signal UplinkRdy : std_logic_vector(GBT_NUM-1 downto 0); signal fifo_rst : std_logic_vector(GBT_NUM-1 downto 0); signal fifo_empty : std_logic_vector(GBT_NUM-1 downto 0); signal fifo_rden : std_logic_vector(GBT_NUM-1 downto 0); @@ -174,8 +174,8 @@ signal RX_DATAPATH_RESET_FINL : std_logic_vector(GBT_NUM/4-1 downto 0); signal GBT_General_ctrl : std_logic_vector(63 downto 0); -type txrx80b_12ch_type is array (GBT_NUM/4-1 downto 0) of std_logic_vector(79 downto 0); -signal RX_DATA_80b : txrx80b_12ch_type; +--type txrx80b_12ch_type is array (GBT_NUM/4-1 downto 0) of std_logic_vector(79 downto 0); +--signal RX_DATA_80b : txrx80b_12ch_type; type data16barray is array (0 to GBT_NUM-1) of std_logic_vector(15 downto 0); type data32barray is array (0 to GBT_NUM-1) of std_logic_vector(31 downto 0); type data128barray is array (0 to GBT_NUM/4-1) of std_logic_vector(127 downto 0); @@ -243,44 +243,41 @@ gbtRxTx : for i in 0 to GBT_NUM-1 generate Port map ( - TXCLK40 => clk40_in, - RXCLK40 => rxrecclk40m, - phase_sel => "100", - downLinkBypassDeinterleaver => '0', - downLinkBypassFECDecoder => '0', - downLinkBypassDescsrambler => '0', - - enableFECErrCounter => '0', - - upLinkScramblerBypass => GBT_General_ctrl(32), - - upLinkFecBypass => GBT_General_ctrl(33), - upLinkInterleaverBypass => GBT_General_ctrl(34), - fecMode => CTRL_FECMODE(i), - txDataRate => CTRL_DATARATE(i), - rst_uplink_i => TX_RESET_i(i), - rst_dnlink_i => (not rxclk_locked) or RX_RESET_i(i), - uplinkClkEn_i => '1', - clk_mgtRxUsrclk_s => GT_RX_WORD_CLK(i), - clk_mgtTxUsrclk_s => GT_TX_WORD_CLK(i), - sta_headerFlag_o => open,--sta_headerFlag_o(i), - sta_headerFlag_shift => open,--sta_headerFlag_shift(i), - sta_rxgbxRdy_o => open,--sta_rxgbxRdy_o(i), - ctr_clkSlip_s => RxSlide(i), - aligned => alignment_done_f(i), - downlinkRdy_o => open,--downlinkrdy(i), - uplinkRdy_o => open, - dat_upLinkWord_fromGb_s => TX_DATA_32b(i), + TXCLK40 => clk40_in, + RXCLK40 => rxrecclk40m, + --uplinkClkEn_i => '1', + clk_mgtRxUsrclk_s => GT_RX_WORD_CLK(i), + clk_mgtTxUsrclk_s => GT_TX_WORD_CLK(i), + rst_uplink_i => TX_RESET_i(i), + --sta_rxgbxRdy_o => open,--sta_rxgbxRdy_o(i), + ctr_clkSlip_s => RxSlide(i), + aligned => alignment_done_f(i), + sta_headerFlag_o => open, --sta_headerFlag_o(i), + sta_headerFlag_shift => open, --sta_headerFlag_shift(i), + clk_dataFlag_rxGb_s_o => open, --clk_dataFlag_rxGb_s_o(i), + --downlinkRdy_o => open,--downlinkrdy(i), + --uplinkRdy_o => open, + dat_upLinkWord_fromGb_s => TX_DATA_32b(i), dat_downLinkWord_fromMgt_s16 => RX_DATA_16b(i), - sta_mgtTxRdy_s => txresetdone(i), - sta_mgtRxRdy_s => rxresetdone(i), - clk_dataFlag_rxGb_s_o => open,--clk_dataFlag_rxGb_s_o(i), - upLinkData => FE_UPLINK_USER_DATA(i), - upLinkDataIC => FE_UPLINK_IC_DATA(i), - upLinkDataEC => FE_UPLINK_EC_DATA(i), - downLinkData => downLinkData_i(i)(31 downto 0), - downLinkDataIC => downLinkData_i(i)(33 downto 32), - downLinkDataEC => downLinkData_i(i)(35 downto 34) + rst_dnlink_i => (not rxclk_locked) or RX_RESET_i(i), + --sta_mgtTxRdy_s => txresetdone(i), + sta_mgtRxRdy_s => rxresetdone(i), + downLinkBypassDeinterleaver => '0', + downLinkBypassFECDecoder => '0', + downLinkBypassDescsrambler => '0', + enableFECErrCounter => '0', + upLinkScramblerBypass => GBT_General_ctrl(32), + upLinkFecBypass => GBT_General_ctrl(33), + upLinkInterleaverBypass => GBT_General_ctrl(34), + fecMode => CTRL_FECMODE(i), + txDataRate => CTRL_DATARATE(i), + phase_sel => "100", + upLinkData => FE_UPLINK_USER_DATA(i), + upLinkDataIC => FE_UPLINK_IC_DATA(i), + upLinkDataEC => FE_UPLINK_EC_DATA(i), + downLinkData => downLinkData_i(i)(31 downto 0), + downLinkDataIC => downLinkData_i(i)(33 downto 32), + downLinkDataEC => downLinkData_i(i)(35 downto 34) ); @@ -324,28 +321,28 @@ rxclkgen_inst: rxclkgen clk_generate : for i in 0 to GBT_NUM-1 generate - GTTXOUTCLK_BUFG: bufg_gt + GTTXOUTCLK_BUFG: bufg_gt -- @suppress "Generic map uses default values. Missing optional actuals: SIM_DEVICE, STARTUP_SYNC" port map( - i => GT_TXOUTCLK(i), - div => "000", - clr => '0',--userclk_tx_reset_in,--'0', - cemask => '0', + o => GT_TXUSRCLK(i), + ce => '1', + cemask => '0', + clr => '0', --userclk_tx_reset_in,--'0', clrmask => '0', - ce => '1', - o => GT_TXUSRCLK(i) + div => "000", + i => GT_TXOUTCLK(i) ); GT_TX_WORD_CLK(i) <= GT_TXUSRCLK(i); - GTRXOUTCLK_BUFG: bufg_gt + GTRXOUTCLK_BUFG: bufg_gt -- @suppress "Generic map uses default values. Missing optional actuals: SIM_DEVICE, STARTUP_SYNC" port map( - i => GT_RXOUTCLK(i), - div => "000", - clr => '0',--userclk_tx_reset_in,--'0', - cemask => '0', + o => GT_RXUSRCLK(i), + ce => '1', + cemask => '0', + clr => '0', --userclk_tx_reset_in,--'0', clrmask => '0', - ce => '1', - o => GT_RXUSRCLK(i) + div => "000", + i => GT_RXOUTCLK(i) ); GT_RX_WORD_CLK(i) <= GT_RXUSRCLK(i); @@ -373,55 +370,48 @@ GTH_inst : for i in 0 to (GBT_NUM/4)-1 generate GTH_TOP_INST: entity work.FLX_LpGBT_GTH_FE Port map ( - gthrxn_in => RX_N_i(4*i+3 downto 4*i), - gthrxp_in => RX_P_i(4*i+3 downto 4*i), - gthtxn_out => TX_N_i(4*i+3 downto 4*i), - gthtxp_out => TX_P_i(4*i+3 downto 4*i), - - drpclk_in => drpclk_vec(i downto i), - gtrefclk0_in => GTHREFCLK(4*i downto 4*i), - gt_rxusrclk_in => GT_RX_WORD_CLK(4*i+3 downto 4*i), - gt_rxoutclk_out => GT_RXOUTCLK(4*i+3 downto 4*i), - gt_txusrclk_in => GT_TX_WORD_CLK(4*i+3 downto 4*i), - gt_txoutclk_out => GT_TXOUTCLK(4*i+3 downto 4*i), - - userdata_tx_in => TX_DATA_128b(i), - userdata_rx_out => RX_DATA_64b(i), - rxpolarity_in => CTRL_RXPOLARITY(4*i+3 downto 4*i), - txpolarity_in => CTRL_TXPOLARITY(4*i+3 downto 4*i), - - loopback_in => "000", - rxcdrhold_in => '0', - - userclk_rx_reset_in => userclk_rx_reset_in(i downto i),--(others=>(not rxpmaresetdone_out(i))),--locked, - userclk_tx_reset_in => userclk_tx_reset_in(i downto i),--(others=>(not txpmaresetdone_out(i))),--,--locked, - - reset_all_in => CTRL_SOFT_RESET(i downto i), - reset_tx_pll_and_datapath_in => CTRL_TXPLL_DATAPATH_RESET(i downto i), - reset_tx_datapath_in => CTRL_TX_DATAPATH_RESET(i downto i), - reset_rx_pll_and_datapath_in => CTRL_RXPLL_DATAPATH_RESET(i downto i), - reset_rx_datapath_in => RX_DATAPATH_RESET_FINL(i downto i), - - qpll0lock_out => open, - qpll1lock_out => MON_QPLL_LCK(i downto i), - qpll1fbclklost_out => open,-- - qpll0fbclklost_out => open, - rxslide_in => RxSlide(4*i+3 downto 4*i), - - cplllock_out => MON_CPLL_LCK(4*i+3 downto 4*i), - rxresetdone_out => rxresetdone(4*i+3 downto 4*i), - txresetdone_out => txresetdone(4*i+3 downto 4*i), - rxpmaresetdone_out => rxpmaresetdone(4*i+3 downto 4*i), - txpmaresetdone_out => txpmaresetdone(4*i+3 downto 4*i), - reset_tx_done_out => txresetdone_quad(i downto i), - reset_rx_done_out => rxresetdone_quad(i downto i), - reset_rx_cdr_stable_out => RxCdrLock_quad(i downto i), - rxcdrlock_out => rxcdrlock_out(4*i+3 downto 4*i) + gt_rxusrclk_in => GT_RX_WORD_CLK(4*i+3 downto 4*i), + gt_txusrclk_in => GT_TX_WORD_CLK(4*i+3 downto 4*i), + gt_rxoutclk_out => GT_RXOUTCLK(4*i+3 downto 4*i), + gt_txoutclk_out => GT_TXOUTCLK(4*i+3 downto 4*i), + gthrxn_in => RX_N_i(4*i+3 downto 4*i), + gthrxp_in => RX_P_i(4*i+3 downto 4*i), + gthtxn_out => TX_N_i(4*i+3 downto 4*i), + gthtxp_out => TX_P_i(4*i+3 downto 4*i), + drpclk_in => drpclk_vec(i downto i), + gtrefclk0_in => GTHREFCLK(4*i downto 4*i), + rxpolarity_in => CTRL_RXPOLARITY(4*i+3 downto 4*i), + txpolarity_in => CTRL_TXPOLARITY(4*i+3 downto 4*i), + loopback_in => "000", + rxcdrhold_in => '0', + userdata_tx_in => TX_DATA_128b(i), + userdata_rx_out => RX_DATA_64b(i), + userclk_rx_reset_in => userclk_rx_reset_in(i downto i), --(others=>(not rxpmaresetdone_out(i))),--locked, + userclk_tx_reset_in => userclk_tx_reset_in(i downto i), --(others=>(not txpmaresetdone_out(i))),--,--locked, + reset_all_in => CTRL_SOFT_RESET(i downto i), + reset_tx_pll_and_datapath_in => CTRL_TXPLL_DATAPATH_RESET(i downto i), + reset_tx_datapath_in => CTRL_TX_DATAPATH_RESET(i downto i), + reset_rx_pll_and_datapath_in => CTRL_RXPLL_DATAPATH_RESET(i downto i), + reset_rx_datapath_in => RX_DATAPATH_RESET_FINL(i downto i), + qpll1lock_out => MON_QPLL_LCK(i downto i), + qpll1fbclklost_out => open, -- + qpll0lock_out => open, + qpll0fbclklost_out => open, + rxslide_in => RxSlide(4*i+3 downto 4*i), + txresetdone_out => TxResetDone(4*i+3 downto 4*i), + txpmaresetdone_out => txpmaresetdone(4*i+3 downto 4*i), + rxresetdone_out => rxresetdone(4*i+3 downto 4*i), + rxpmaresetdone_out => rxpmaresetdone(4*i+3 downto 4*i), + cplllock_out => MON_CPLL_LCK(4*i+3 downto 4*i), + reset_tx_done_out => txresetdone_quad(i downto i), + reset_rx_done_out => rxresetdone_quad(i downto i), + reset_rx_cdr_stable_out => RxCdrLock_quad(i downto i), + rxcdrlock_out => rxcdrlock_out(4*i+3 downto 4*i) ); MON_RXRSTDONE(4*i+3 downto 4*i) <= rxresetdone(4*i+3 downto 4*i); - MON_TXRSTDONE(4*i+3 downto 4*i) <= txresetdone(4*i+3 downto 4*i); + MON_TXRSTDONE(4*i+3 downto 4*i) <= TxResetDone(4*i+3 downto 4*i); MON_RXRSTDONE_QUAD(i downto i) <= rxresetdone_quad(i downto i); MON_TXRSTDONE_QUAD(i downto i) <= txresetdone_quad(i downto i); MON_RXPMARSTDONE(4*i+3 downto 4*i) <= rxpmaresetdone(4*i+3 downto 4*i); @@ -481,4 +471,4 @@ end process; -end Behavioral; \ No newline at end of file +end Behavioral; diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_BE.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_BE.vhd index 394fbab597642c81d1215dc99641afa1ce4126af..ebdda80eaf2ded0eff0de1117f942fb78029e6d9 100644 --- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_BE.vhd +++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_BE.vhd @@ -93,60 +93,58 @@ end FLX_LpGBT_GTH_BE; architecture Behavioral of FLX_LpGBT_GTH_BE is - component KCU_RXBUF_PMA_QPLL_4CH_LPGBT is - - port( - gtrefclk0_in: in std_logic_vector(3 downto 0); - drpclk_in: in std_logic_vector(3 downto 0); - gtpowergood_out: out std_logic_vector(3 downto 0); - --txprgdivresetdone_out: out std_logic_vector(3 downto 0); - cplllock_out : out std_logic_vector(3 downto 0); - gtwiz_userclk_tx_active_in : in std_logic_vector(0 downto 0); - gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_reset_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_start_user_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_error_out : out std_logic_vector(0 downto 0); - gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); - gtwiz_reset_all_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); - gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); - gtwiz_userdata_tx_in : in std_logic_vector(63 downto 0); - gtwiz_userdata_rx_out : out std_logic_vector(127 downto 0); - gtrefclk01_in : in std_logic_vector(0 downto 0); - qpll1outclk_out : out std_logic_vector(0 downto 0); - qpll1outrefclk_out : out std_logic_vector(0 downto 0); - loopback_in : in std_logic_vector(11 downto 0); - gthrxn_in : in std_logic_vector(3 downto 0); - gthrxp_in : in std_logic_vector(3 downto 0); - rxcdrhold_in : in std_logic_vector(3 downto 0); - rxpolarity_in : in std_logic_vector(3 downto 0); - rxusrclk_in : in std_logic_vector(3 downto 0); - rxusrclk2_in : in std_logic_vector(3 downto 0); - txpolarity_in : in std_logic_vector(3 downto 0); - txusrclk_in : in std_logic_vector(3 downto 0); - qpll1lock_out : out std_logic_vector(0 downto 0); - qpll1fbclklost_out : out std_logic_vector(0 downto 0); - qpll0fbclklost_out : out std_logic_vector(0 downto 0); - qpll0lock_out : out std_logic_vector(0 downto 0); - txusrclk2_in : in std_logic_vector(3 downto 0); - gthtxn_out : out std_logic_vector(3 downto 0); - gthtxp_out : out std_logic_vector(3 downto 0); - rxslide_in : in std_logic_vector(3 downto 0); - rxcdrlock_out : out std_logic_vector(3 downto 0); - rxoutclk_out : out std_logic_vector(3 downto 0); - rxpmaresetdone_out : out std_logic_vector(3 downto 0); - txoutclk_out : out std_logic_vector(3 downto 0); - txresetdone_out : out std_logic_vector(3 downto 0); - rxresetdone_out : out std_logic_vector(3 downto 0); - txpmaresetdone_out : out std_logic_vector(3 downto 0) + component KCU_RXBUF_PMA_QPLL_4CH_LPGBT + port( + gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_all_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR(63 downto 0); + gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR(127 downto 0); + gtrefclk01_in : in STD_LOGIC_VECTOR(0 to 0); + qpll0fbclklost_out : out STD_LOGIC_VECTOR(0 to 0); + qpll0lock_out : out STD_LOGIC_VECTOR(0 to 0); + qpll1fbclklost_out : out STD_LOGIC_VECTOR(0 to 0); + qpll1lock_out : out STD_LOGIC_VECTOR(0 to 0); + qpll1outclk_out : out STD_LOGIC_VECTOR(0 to 0); + qpll1outrefclk_out : out STD_LOGIC_VECTOR(0 to 0); + drpclk_in : in STD_LOGIC_VECTOR(3 downto 0); + gthrxn_in : in STD_LOGIC_VECTOR(3 downto 0); + gthrxp_in : in STD_LOGIC_VECTOR(3 downto 0); + gtrefclk0_in : in STD_LOGIC_VECTOR(3 downto 0); + loopback_in : in STD_LOGIC_VECTOR(11 downto 0); + rxcdrhold_in : in STD_LOGIC_VECTOR(3 downto 0); + rxpolarity_in : in STD_LOGIC_VECTOR(3 downto 0); + rxslide_in : in STD_LOGIC_VECTOR(3 downto 0); + rxusrclk_in : in STD_LOGIC_VECTOR(3 downto 0); + rxusrclk2_in : in STD_LOGIC_VECTOR(3 downto 0); + txpolarity_in : in STD_LOGIC_VECTOR(3 downto 0); + txusrclk_in : in STD_LOGIC_VECTOR(3 downto 0); + txusrclk2_in : in STD_LOGIC_VECTOR(3 downto 0); + cplllock_out : out STD_LOGIC_VECTOR(3 downto 0); + gthtxn_out : out STD_LOGIC_VECTOR(3 downto 0); + gthtxp_out : out STD_LOGIC_VECTOR(3 downto 0); + gtpowergood_out : out STD_LOGIC_VECTOR(3 downto 0); + rxcdrlock_out : out STD_LOGIC_VECTOR(3 downto 0); + rxoutclk_out : out STD_LOGIC_VECTOR(3 downto 0); + rxpmaresetdone_out : out STD_LOGIC_VECTOR(3 downto 0); + rxresetdone_out : out STD_LOGIC_VECTOR(3 downto 0); + txoutclk_out : out STD_LOGIC_VECTOR(3 downto 0); + txpmaresetdone_out : out STD_LOGIC_VECTOR(3 downto 0); + txresetdone_out : out STD_LOGIC_VECTOR(3 downto 0) ); - end component; + end component KCU_RXBUF_PMA_QPLL_4CH_LPGBT; signal rxusrclk : std_logic_vector(3 downto 0); @@ -161,12 +159,10 @@ architecture Behavioral of FLX_LpGBT_GTH_BE is signal userclk_rx_active_out_p: std_logic_vector(0 downto 0); signal userclk_tx_active_out_p: std_logic_vector(0 downto 0); signal txusrclk : std_logic; - signal vccvec : std_logic_vector(0 downto 0); signal gndvec : std_logic_vector(0 downto 0); begin - vccvec(0) <= '1'; gndvec(0) <= '0'; -- RxUsrClk rxusrclk <= gt_rxusrclk_in; @@ -221,58 +217,54 @@ begin gtwizard_ultrascale_four_channel_qpll_inst: KCU_RXBUF_PMA_QPLL_4CH_LPGBT port map( - gtwiz_userclk_tx_active_in => userclk_tx_active_out, - gtwiz_userclk_rx_active_in => userclk_rx_active_out, - gtwiz_buffbypass_tx_reset_in => gndvec, - gtwiz_buffbypass_tx_start_user_in => gndvec, - gtwiz_buffbypass_tx_done_out => open, - gtwiz_buffbypass_tx_error_out => open, - - gtwiz_reset_clk_freerun_in => drpclk_in, - gtwiz_reset_all_in => reset_all_in, - - gtwiz_reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath_in, - gtwiz_reset_tx_datapath_in => reset_tx_datapath_in, - gtwiz_reset_rx_pll_and_datapath_in => reset_rx_pll_and_datapath_in, - gtwiz_reset_rx_datapath_in => reset_rx_datapath_in, - - gtwiz_reset_rx_cdr_stable_out => reset_rx_cdr_stable_out, - gtwiz_reset_tx_done_out => reset_tx_done_out, - gtwiz_reset_rx_done_out => reset_rx_done_out, - gtrefclk0_in=> gtrefclk0_in(0) & gtrefclk0_in(0) & gtrefclk0_in(0) & gtrefclk0_in(0), - drpclk_in=>drpclk_in(0) & drpclk_in(0) & drpclk_in(0) & drpclk_in(0), - gtpowergood_out=> open, - cplllock_out => cplllock_out, - -- txprgdivresetdone_out=> open, - qpll1lock_out => qpll1lock_out, - qpll0lock_out => qpll0lock_out, - qpll1fbclklost_out => qpll1fbclklost_out, - qpll0fbclklost_out => qpll0fbclklost_out, - gtwiz_userdata_tx_in => userdata_tx_in, - gtwiz_userdata_rx_out => userdata_rx_out, - gtrefclk01_in => gtrefclk0_in, - loopback_in => loopback_in & loopback_in & loopback_in & loopback_in, - qpll1outclk_out => open, - qpll1outrefclk_out => open, - gthrxn_in => gthrxn_in, - gthrxp_in => gthrxp_in, - rxcdrhold_in => (others=>rxcdrhold_in), - rxpolarity_in => rxpolarity_in, - rxusrclk_in => rxusrclk_int, - rxusrclk2_in => rxusrclk2_int, - txpolarity_in => txpolarity_in, - txusrclk_in => txusrclk_int, - txusrclk2_in => txusrclk2_int, - gthtxn_out => gthtxn_out, - gthtxp_out => gthtxp_out, - rxcdrlock_out => rxcdrlock_out, - rxoutclk_out => rxoutclk_int, - rxpmaresetdone_out => rxpmaresetdone_out, - rxslide_in => rxslide_in, - txoutclk_out => txoutclk_int, - txpmaresetdone_out => txpmaresetdone_out, - txresetdone_out => txresetdone_out, - rxresetdone_out => rxresetdone_out + gtwiz_userclk_tx_active_in => userclk_tx_active_out, + gtwiz_userclk_rx_active_in => userclk_rx_active_out, + gtwiz_buffbypass_tx_reset_in => gndvec, + gtwiz_buffbypass_tx_start_user_in => gndvec, + gtwiz_buffbypass_tx_done_out => open, + gtwiz_buffbypass_tx_error_out => open, + gtwiz_reset_clk_freerun_in => drpclk_in, + gtwiz_reset_all_in => reset_all_in, + gtwiz_reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath_in, + gtwiz_reset_tx_datapath_in => reset_tx_datapath_in, + gtwiz_reset_rx_pll_and_datapath_in => reset_rx_pll_and_datapath_in, + gtwiz_reset_rx_datapath_in => reset_rx_datapath_in, + gtwiz_reset_rx_cdr_stable_out => reset_rx_cdr_stable_out, + gtwiz_reset_tx_done_out => reset_tx_done_out, + gtwiz_reset_rx_done_out => reset_rx_done_out, + gtwiz_userdata_tx_in => userdata_tx_in, + gtwiz_userdata_rx_out => userdata_rx_out, + gtrefclk01_in => gtrefclk0_in, + qpll0fbclklost_out => qpll0fbclklost_out, + qpll0lock_out => qpll0lock_out, + qpll1fbclklost_out => qpll1fbclklost_out, + qpll1lock_out => qpll1lock_out, + qpll1outclk_out => open, + qpll1outrefclk_out => open, + drpclk_in => drpclk_in(0) & drpclk_in(0) & drpclk_in(0) & drpclk_in(0), + gthrxn_in => gthrxn_in, + gthrxp_in => gthrxp_in, + gtrefclk0_in => gtrefclk0_in(0) & gtrefclk0_in(0) & gtrefclk0_in(0) & gtrefclk0_in(0), + loopback_in => loopback_in & loopback_in & loopback_in & loopback_in, + rxcdrhold_in => (others=>rxcdrhold_in), + rxpolarity_in => rxpolarity_in, + rxslide_in => rxslide_in, + rxusrclk_in => rxusrclk_int, + rxusrclk2_in => rxusrclk2_int, + txpolarity_in => txpolarity_in, + txusrclk_in => txusrclk_int, + txusrclk2_in => txusrclk2_int, + cplllock_out => cplllock_out, + gthtxn_out => gthtxn_out, + gthtxp_out => gthtxp_out, + gtpowergood_out => open, + rxcdrlock_out => rxcdrlock_out, + rxoutclk_out => rxoutclk_int, + rxpmaresetdone_out => rxpmaresetdone_out, + rxresetdone_out => rxresetdone_out, + txoutclk_out => txoutclk_int, + txpmaresetdone_out => txpmaresetdone_out, + txresetdone_out => txresetdone_out ); --end generate; diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_FE.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_FE.vhd index 2fe0d6808af71c65a946388edbcd3a75456f4970..b872d2ee2f62661644b0bafdbd418236ff49eb48 100644 --- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_FE.vhd +++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_GTH_FE.vhd @@ -94,62 +94,58 @@ end FLX_LpGBT_GTH_FE; architecture Behavioral of FLX_LpGBT_GTH_FE is -component KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT is - port - ( - - gtrefclk0_in: in std_logic_vector(3 downto 0); - gtpowergood_out : out std_logic_vector(3 downto 0); - --txprgdivresetdone_out : out std_logic_vector(3 downto 0); - drpclk_in: in std_logic_vector(3 downto 0); - cplllock_out : out std_logic_vector(3 downto 0); - - gtwiz_userclk_tx_active_in : in std_logic_vector(0 downto 0); - gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_reset_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_start_user_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_error_out : out std_logic_vector(0 downto 0); - gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); - gtwiz_reset_all_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); - gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); - gtwiz_userdata_tx_in : in std_logic_vector(127 downto 0); - gtwiz_userdata_rx_out : out std_logic_vector(63 downto 0); - gtrefclk01_in : in std_logic_vector(0 downto 0); - qpll1outclk_out : out std_logic_vector(0 downto 0); - qpll1outrefclk_out : out std_logic_vector(0 downto 0); - loopback_in : in std_logic_vector(11 downto 0); - gthrxn_in : in std_logic_vector(3 downto 0); - gthrxp_in : in std_logic_vector(3 downto 0); - rxcdrhold_in : in std_logic_vector(3 downto 0); - rxpolarity_in : in std_logic_vector(3 downto 0); - rxusrclk_in : in std_logic_vector(3 downto 0); - rxusrclk2_in : in std_logic_vector(3 downto 0); - txpolarity_in : in std_logic_vector(3 downto 0); - txusrclk_in : in std_logic_vector(3 downto 0); - qpll1lock_out : out std_logic_vector(0 downto 0); - qpll1fbclklost_out : out std_logic_vector(0 downto 0); - qpll0fbclklost_out : out std_logic_vector(0 downto 0); - qpll0lock_out : out std_logic_vector(0 downto 0); - txusrclk2_in : in std_logic_vector(3 downto 0); - gthtxn_out : out std_logic_vector(3 downto 0); - gthtxp_out : out std_logic_vector(3 downto 0); - rxslide_in : in std_logic_vector(3 downto 0); - rxcdrlock_out : out std_logic_vector(3 downto 0); - rxoutclk_out : out std_logic_vector(3 downto 0); - rxpmaresetdone_out : out std_logic_vector(3 downto 0); - txoutclk_out : out std_logic_vector(3 downto 0); - txresetdone_out : out std_logic_vector(3 downto 0); - rxresetdone_out : out std_logic_vector(3 downto 0); - txpmaresetdone_out : out std_logic_vector(3 downto 0) - ); - end component; +component KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT + port( + gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_all_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR(0 to 0); + gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR(127 downto 0); + gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR(63 downto 0); + gtrefclk01_in : in STD_LOGIC_VECTOR(0 to 0); + qpll0fbclklost_out : out STD_LOGIC_VECTOR(0 to 0); + qpll0lock_out : out STD_LOGIC_VECTOR(0 to 0); + qpll1fbclklost_out : out STD_LOGIC_VECTOR(0 to 0); + qpll1lock_out : out STD_LOGIC_VECTOR(0 to 0); + qpll1outclk_out : out STD_LOGIC_VECTOR(0 to 0); + qpll1outrefclk_out : out STD_LOGIC_VECTOR(0 to 0); + drpclk_in : in STD_LOGIC_VECTOR(3 downto 0); + gthrxn_in : in STD_LOGIC_VECTOR(3 downto 0); + gthrxp_in : in STD_LOGIC_VECTOR(3 downto 0); + gtrefclk0_in : in STD_LOGIC_VECTOR(3 downto 0); + loopback_in : in STD_LOGIC_VECTOR(11 downto 0); + rxcdrhold_in : in STD_LOGIC_VECTOR(3 downto 0); + rxpolarity_in : in STD_LOGIC_VECTOR(3 downto 0); + rxslide_in : in STD_LOGIC_VECTOR(3 downto 0); + rxusrclk_in : in STD_LOGIC_VECTOR(3 downto 0); + rxusrclk2_in : in STD_LOGIC_VECTOR(3 downto 0); + txpolarity_in : in STD_LOGIC_VECTOR(3 downto 0); + txusrclk_in : in STD_LOGIC_VECTOR(3 downto 0); + txusrclk2_in : in STD_LOGIC_VECTOR(3 downto 0); + cplllock_out : out STD_LOGIC_VECTOR(3 downto 0); + gthtxn_out : out STD_LOGIC_VECTOR(3 downto 0); + gthtxp_out : out STD_LOGIC_VECTOR(3 downto 0); + gtpowergood_out : out STD_LOGIC_VECTOR(3 downto 0); + rxcdrlock_out : out STD_LOGIC_VECTOR(3 downto 0); + rxoutclk_out : out STD_LOGIC_VECTOR(3 downto 0); + rxpmaresetdone_out : out STD_LOGIC_VECTOR(3 downto 0); + rxresetdone_out : out STD_LOGIC_VECTOR(3 downto 0); + txoutclk_out : out STD_LOGIC_VECTOR(3 downto 0); + txpmaresetdone_out : out STD_LOGIC_VECTOR(3 downto 0); + txresetdone_out : out STD_LOGIC_VECTOR(3 downto 0) + ); +end component KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT; signal rxusrclk : std_logic_vector(3 downto 0); @@ -164,12 +160,10 @@ component KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT is signal userclk_rx_active_out_p: std_logic_vector(0 downto 0); signal userclk_tx_active_out_p: std_logic_vector(0 downto 0); signal txusrclk : std_logic; - signal vccvec : std_logic_vector(0 downto 0); signal gndvec : std_logic_vector(0 downto 0); begin - vccvec(0) <= '1'; gndvec(0) <= '0'; -- RxUsrClk rxusrclk <= gt_rxusrclk_in; @@ -224,61 +218,54 @@ begin gtwizard_ultrascale_four_channel_qpll_inst: KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT port map( + gtwiz_userclk_tx_active_in => userclk_tx_active_out, + gtwiz_userclk_rx_active_in => userclk_rx_active_out, + gtwiz_buffbypass_tx_reset_in => gndvec, + gtwiz_buffbypass_tx_start_user_in => gndvec, + gtwiz_buffbypass_tx_done_out => open, + gtwiz_buffbypass_tx_error_out => open, + gtwiz_reset_clk_freerun_in => drpclk_in, + gtwiz_reset_all_in => reset_all_in, + gtwiz_reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath_in, + gtwiz_reset_tx_datapath_in => reset_tx_datapath_in, + gtwiz_reset_rx_pll_and_datapath_in => reset_rx_pll_and_datapath_in, + gtwiz_reset_rx_datapath_in => reset_rx_datapath_in, + gtwiz_reset_rx_cdr_stable_out => reset_rx_cdr_stable_out, + gtwiz_reset_tx_done_out => reset_tx_done_out, + gtwiz_reset_rx_done_out => reset_rx_done_out, + gtwiz_userdata_tx_in => userdata_tx_in, + gtwiz_userdata_rx_out => userdata_rx_out, + gtrefclk01_in => gtrefclk0_in, + qpll0fbclklost_out => qpll0fbclklost_out, + qpll0lock_out => qpll0lock_out, + qpll1fbclklost_out => qpll1fbclklost_out, + qpll1lock_out => qpll1lock_out, + qpll1outclk_out => open, + qpll1outrefclk_out => open, drpclk_in => (others=>drpclk_in(0)), - - - gtrefclk0_in=> gtrefclk0_in(0) & gtrefclk0_in(0) & gtrefclk0_in(0) & gtrefclk0_in(0), - gtpowergood_out => open, - -- txprgdivresetdone_out => open, - - gtwiz_userclk_tx_active_in => userclk_tx_active_out, - gtwiz_userclk_rx_active_in => userclk_rx_active_out, - gtwiz_buffbypass_tx_reset_in => gndvec, - gtwiz_buffbypass_tx_start_user_in => gndvec, - gtwiz_buffbypass_tx_done_out => open, - gtwiz_buffbypass_tx_error_out => open, - - gtwiz_reset_clk_freerun_in => drpclk_in, - gtwiz_reset_all_in => reset_all_in, - - gtwiz_reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath_in, - gtwiz_reset_tx_datapath_in => reset_tx_datapath_in, - gtwiz_reset_rx_pll_and_datapath_in => reset_rx_pll_and_datapath_in, - gtwiz_reset_rx_datapath_in => reset_rx_datapath_in, - - gtwiz_reset_rx_cdr_stable_out => reset_rx_cdr_stable_out, - gtwiz_reset_tx_done_out => reset_tx_done_out, - gtwiz_reset_rx_done_out => reset_rx_done_out, - cplllock_out => cplllock_out , - qpll1lock_out => qpll1lock_out, - qpll0lock_out => qpll0lock_out, - qpll1fbclklost_out => qpll1fbclklost_out, - qpll0fbclklost_out => qpll0fbclklost_out, - gtwiz_userdata_tx_in => userdata_tx_in, - gtwiz_userdata_rx_out => userdata_rx_out, - gtrefclk01_in => gtrefclk0_in, - loopback_in => loopback_in & loopback_in & loopback_in & loopback_in, - qpll1outclk_out => open, - qpll1outrefclk_out => open, - gthrxn_in => gthrxn_in, - gthrxp_in => gthrxp_in, - rxcdrhold_in => (others=>rxcdrhold_in), - rxpolarity_in => rxpolarity_in, - rxusrclk_in => rxusrclk_int, - rxusrclk2_in => rxusrclk2_int, - txpolarity_in => txpolarity_in, - txusrclk_in => txusrclk_int, - txusrclk2_in => txusrclk2_int, - gthtxn_out => gthtxn_out, - gthtxp_out => gthtxp_out, - rxcdrlock_out => rxcdrlock_out, - rxoutclk_out => rxoutclk_int, - rxpmaresetdone_out => rxpmaresetdone_out, - rxslide_in => rxslide_in, - txoutclk_out => txoutclk_int, - txpmaresetdone_out => txpmaresetdone_out, - txresetdone_out => txresetdone_out, - rxresetdone_out => rxresetdone_out + gthrxn_in => gthrxn_in, + gthrxp_in => gthrxp_in, + gtrefclk0_in => gtrefclk0_in(0) & gtrefclk0_in(0) & gtrefclk0_in(0) & gtrefclk0_in(0), + loopback_in => loopback_in & loopback_in & loopback_in & loopback_in, + rxcdrhold_in => (others=>rxcdrhold_in), + rxpolarity_in => rxpolarity_in, + rxslide_in => rxslide_in, + rxusrclk_in => rxusrclk_int, + rxusrclk2_in => rxusrclk2_int, + txpolarity_in => txpolarity_in, + txusrclk_in => txusrclk_int, + txusrclk2_in => txusrclk2_int, + cplllock_out => cplllock_out, + gthtxn_out => gthtxn_out, + gthtxp_out => gthtxp_out, + gtpowergood_out => open, + rxcdrlock_out => rxcdrlock_out, + rxoutclk_out => rxoutclk_int, + rxpmaresetdone_out => rxpmaresetdone_out, + rxresetdone_out => rxresetdone_out, + txoutclk_out => txoutclk_int, + txpmaresetdone_out => txpmaresetdone_out, + txresetdone_out => txresetdone_out ); --end generate; diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_PRBS.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_PRBS.vhd index 1059beb6fa7e77514c573932b39ad81d78d72bcf..7ece16cfe527391aadd1113584d0741a3e2ad1c6 100644 --- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_PRBS.vhd +++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_PRBS.vhd @@ -29,8 +29,8 @@ LIBRARY IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_ARITH.ALL;-- @suppress "Deprecated package" +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" library UNISIM; use UNISIM.VComponents.all; @@ -56,12 +56,12 @@ entity FLX_LpGBT_PRBS is FELIX_DOWNLINK_EC_DATA : out txrx2b_type(0 to GBT_NUM-1); FELIX_DOWNLINK_IC_DATA : out txrx2b_type(0 to GBT_NUM-1); FE_DOWNLINK_USER_DATA : in txrx32b_type(0 to GBT_NUM-1); - FE_DOWNLINK_EC_DATA : in txrx2b_type(0 to GBT_NUM-1); - FE_DOWNLINK_IC_DATA : in txrx2b_type(0 to GBT_NUM-1); + --FE_DOWNLINK_EC_DATA : in txrx2b_type(0 to GBT_NUM-1); + --FE_DOWNLINK_IC_DATA : in txrx2b_type(0 to GBT_NUM-1); FELIX_UPLINK_USER_DATA : in txrx230b_type(0 to GBT_NUM-1); - FELIX_UPLINK_EC_DATA : in txrx2b_type(0 to GBT_NUM-1); - FELIX_UPLINK_IC_DATA : in txrx2b_type(0 to GBT_NUM-1); + --FELIX_UPLINK_EC_DATA : in txrx2b_type(0 to GBT_NUM-1); + --FELIX_UPLINK_IC_DATA : in txrx2b_type(0 to GBT_NUM-1); FE_UPLINK_USER_DATA : out txrx224b_type(0 to GBT_NUM-1); FE_UPLINK_EC_DATA : out txrx2b_type(0 to GBT_NUM-1); FE_UPLINK_IC_DATA : out txrx2b_type(0 to GBT_NUM-1) @@ -127,7 +127,7 @@ begin dataA => x"55559999", dataB => PRBS_RX32_OUT(i*7+j), error_counter => error_cnt(i*7+j), - error_clr => error_clear, + error_clr => ERROR_CLEAR, clk => FELIX_SIDE_RX40MCLK, charflag => '0' ); @@ -183,7 +183,7 @@ begin dataA => x"55559999", dataB => PRBS_FERX32_OUT(i), error_counter => error_cnt_fe(i), - error_clr => error_clear, + error_clr => ERROR_CLEAR, clk => FE_SIDE_RX40MCLK, charflag => '0' ); diff --git a/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Chk.vhd b/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Chk.vhd index 010e294ee4e98ddb99ae9242f8df6b17df237a0c..97b62b3b065dfff9f325674c6a1a1c1b54db5f37 100644 --- a/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Chk.vhd +++ b/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Chk.vhd @@ -111,7 +111,7 @@ begin elsif (DATA_VALID_IN = '1') then poly <= PRBS_DATA_IN(31 downto 1); else - poly <= POLY; + poly <= poly; end if; DATA_VALID_IN_r <= DATA_VALID_IN; end if; diff --git a/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Gen.vhd b/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Gen.vhd index 38a1cee13a44b16af8fff10efbb1f91455c2fe5d..2c3670bc6d3a9d1f877eab676a86ed0743ebfa77 100644 --- a/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Gen.vhd +++ b/sources/LpGBT/LpGBT_FELIX/PRBS31_32BIT_Gen.vhd @@ -64,38 +64,38 @@ process( CLK ) if (RESET = '1') then poly <= "000" & x"0000000"; elsif DATA_VALID_IN='1' then - poly31 <= poly(3) xor poly(0) xor datain(0); - poly(0) <= poly(4) xor poly(1) xor datain(1); - poly(1) <= poly(5) xor poly(2) xor datain(2); - poly(2) <= poly(6) xor poly(3) xor datain(3); - poly(3) <= poly(7) xor poly(4) xor datain(4); - poly(4) <= poly(8) xor poly(5) xor datain(5); - poly(5) <= poly(9) xor poly(6) xor datain(6); - poly(6) <= poly(10) xor poly(7) xor datain(7); - poly(7) <= poly(11) xor poly(8) xor datain(8); - poly(8) <= poly(12) xor poly(9) xor datain(9); - poly(9) <= poly(13) xor poly(10) xor datain(10); - poly(10) <= poly(14) xor poly(11) xor datain(11); - poly(11) <= poly(15) xor poly(12) xor datain(12); - poly(12) <= poly(16) xor poly(13) xor datain(13); - poly(13) <= poly(17) xor poly(14) xor datain(14); - poly(14) <= poly(18) xor poly(15) xor datain(15); - poly(15) <= poly(19) xor poly(16) xor datain(16); - poly(16) <= poly(20) xor poly(17) xor datain(17); - poly(17) <= poly(21) xor poly(18) xor datain(18); - poly(18) <= poly(22) xor poly(19) xor datain(19); - poly(19) <= poly(23) xor poly(20) xor datain(20); - poly(20) <= poly(24) xor poly(21) xor datain(21); - poly(21) <= poly(25) xor poly(22) xor datain(22); - poly(22) <= poly(26) xor poly(23) xor datain(23); - poly(23) <= poly(27) xor poly(24) xor datain(24); - poly(24) <= poly(28) xor poly(25) xor datain(25); - poly(25) <= poly(29) xor poly(26) xor datain(26); - poly(26) <= poly(30) xor poly(27) xor datain(27); - poly(27) <= poly(3) xor poly(0) xor datain(0) xor poly(28) xor datain(28); - poly(28) <= poly(4) xor poly(1) xor datain(1) xor poly(29) xor datain(29); - poly(29) <= poly(5) xor poly(2) xor datain(2) xor poly(30) xor datain(30); - poly(30) <= poly(6) xor poly(3) xor datain(3) xor poly(3) xor poly(0) xor datain(0) xor datain(31); + poly31 <= poly(3) xor poly(0) xor DATAIN(0); + poly(0) <= poly(4) xor poly(1) xor DATAIN(1); + poly(1) <= poly(5) xor poly(2) xor DATAIN(2); + poly(2) <= poly(6) xor poly(3) xor DATAIN(3); + poly(3) <= poly(7) xor poly(4) xor DATAIN(4); + poly(4) <= poly(8) xor poly(5) xor DATAIN(5); + poly(5) <= poly(9) xor poly(6) xor DATAIN(6); + poly(6) <= poly(10) xor poly(7) xor DATAIN(7); + poly(7) <= poly(11) xor poly(8) xor DATAIN(8); + poly(8) <= poly(12) xor poly(9) xor DATAIN(9); + poly(9) <= poly(13) xor poly(10) xor DATAIN(10); + poly(10) <= poly(14) xor poly(11) xor DATAIN(11); + poly(11) <= poly(15) xor poly(12) xor DATAIN(12); + poly(12) <= poly(16) xor poly(13) xor DATAIN(13); + poly(13) <= poly(17) xor poly(14) xor DATAIN(14); + poly(14) <= poly(18) xor poly(15) xor DATAIN(15); + poly(15) <= poly(19) xor poly(16) xor DATAIN(16); + poly(16) <= poly(20) xor poly(17) xor DATAIN(17); + poly(17) <= poly(21) xor poly(18) xor DATAIN(18); + poly(18) <= poly(22) xor poly(19) xor DATAIN(19); + poly(19) <= poly(23) xor poly(20) xor DATAIN(20); + poly(20) <= poly(24) xor poly(21) xor DATAIN(21); + poly(21) <= poly(25) xor poly(22) xor DATAIN(22); + poly(22) <= poly(26) xor poly(23) xor DATAIN(23); + poly(23) <= poly(27) xor poly(24) xor DATAIN(24); + poly(24) <= poly(28) xor poly(25) xor DATAIN(25); + poly(25) <= poly(29) xor poly(26) xor DATAIN(26); + poly(26) <= poly(30) xor poly(27) xor DATAIN(27); + poly(27) <= poly(3) xor poly(0) xor DATAIN(0) xor poly(28) xor DATAIN(28); + poly(28) <= poly(4) xor poly(1) xor DATAIN(1) xor poly(29) xor DATAIN(29); + poly(29) <= poly(5) xor poly(2) xor DATAIN(2) xor poly(30) xor DATAIN(30); + poly(30) <= poly(6) xor poly(3) xor DATAIN(3) xor poly(3) xor poly(0) xor DATAIN(0) xor DATAIN(31); else poly <= poly; end if; diff --git a/sources/LpGBT/LpGBT_FELIX/RefClk_Gen.vhd b/sources/LpGBT/LpGBT_FELIX/RefClk_Gen.vhd index f12a0bd6fb45c4c44ea13d1d6834190dc64f82e1..09fb5bba1f4a31360309aac5fe302d1fc05d630a 100644 --- a/sources/LpGBT/LpGBT_FELIX/RefClk_Gen.vhd +++ b/sources/LpGBT/LpGBT_FELIX/RefClk_Gen.vhd @@ -29,8 +29,8 @@ LIBRARY IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_ARITH.ALL;-- @suppress "Deprecated package" +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" library UNISIM; use UNISIM.VComponents.all; @@ -40,10 +40,10 @@ use work.pcie_package.all; entity RefClk_Gen is Generic ( GBT_NUM : integer := 24; - GTHREFCLK_SEL : std_logic := '0'; + --GTHREFCLK_SEL : std_logic := '0'; -- GREFCLK : std_logic := '1'; -- MGTREFCLK : std_logic := '0'; - CARD_TYPE : integer := 712; + --CARD_TYPE : integer := 712; FE_EMU_EN : integer := 1; CLK_CHIP_SEL : integer := 1 -- SI5345 : integer := 0; @@ -108,6 +108,11 @@ signal GTH_RefClk : std_logic_vector(47 downto 0); begin lmk0_gen : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) port map ( O => LMK0_REFCLK, @@ -118,6 +123,11 @@ begin ); lmk1_gen : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) port map ( O => LMK1_REFCLK, @@ -128,6 +138,11 @@ begin ); lmk2_gen : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) port map ( O => LMK2_REFCLK, @@ -138,6 +153,11 @@ begin ); lmk3_gen : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) port map ( O => LMK3_REFCLK, @@ -148,6 +168,11 @@ begin ); lmk4_gen : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) port map ( O => LMK4_REFCLK, @@ -158,6 +183,11 @@ begin ); lmk5_gen : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) port map ( O => LMK5_REFCLK, @@ -168,6 +198,11 @@ begin ); lmk6_gen : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) port map ( O => LMK6_REFCLK, @@ -178,6 +213,11 @@ begin ); lmk7_gen : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) port map ( O => LMK7_REFCLK, @@ -189,6 +229,11 @@ begin si0_gen : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) port map ( O => SI0_REFCLK, @@ -199,6 +244,11 @@ begin ); si2_gen : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) port map ( O => SI2_REFCLK, @@ -209,6 +259,11 @@ begin ); si4_gen : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) port map ( O => SI4_REFCLK, @@ -219,6 +274,11 @@ begin ); si5_gen : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) port map ( O => SI5_REFCLK, @@ -229,6 +289,11 @@ begin ); si8_gen : IBUFDS_GTE3 + generic map( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) port map ( O => SI8_REFCLK, diff --git a/sources/LpGBT/LpGBT_FELIX/Regs_RW.vhd b/sources/LpGBT/LpGBT_FELIX/Regs_RW.vhd index 4ce25f07bd989fc75a4e85e370268f5871cc8b49..266a80b560bfdafedec97671db51a891b5bffe43 100644 --- a/sources/LpGBT/LpGBT_FELIX/Regs_RW.vhd +++ b/sources/LpGBT/LpGBT_FELIX/Regs_RW.vhd @@ -29,8 +29,8 @@ LIBRARY IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_ARITH.ALL;-- @suppress "Deprecated package" +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" library UNISIM; use UNISIM.VComponents.all; @@ -65,17 +65,17 @@ entity Regs_RW is MON_RXRSTDONE : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); MON_TXRSTDONE : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); - MON_RXRSTDONE_QUAD : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0); - MON_TXRSTDONE_QUAD : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0); + --MON_RXRSTDONE_QUAD : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0); + --MON_TXRSTDONE_QUAD : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0); MON_RXPMARSTDONE : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); MON_TXPMARSTDONE : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); MON_RXCDR_LCK : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); - MON_RXCDR_LCK_QUAD : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0); + --MON_RXCDR_LCK_QUAD : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0); MON_QPLL_LCK : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)/4-1 downto 0); MON_CPLL_LCK : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); MON_ALIGNMENT_DONE : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); - MON_LPGBT_ERRFLG : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); + --MON_LPGBT_ERRFLG : in std_logic_vector(GBT_NUM*(FE_EMU_EN+1)-1 downto 0); MON_PRBS_ERRCNT : in std_logic_vector(63 downto 0); diff --git a/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd b/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd index f6b2c0dfa92925c9fd07df47c4a47c67a40dab24..56d1d5923a59e2b064187a42b17277652abd5695 100644 --- a/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd +++ b/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd @@ -164,31 +164,26 @@ ARCHITECTURE behavioral OF lpgbtfpga_uplink IS END COMPONENT; --! Uplink decoder component - COMPONENT lpgbtfpga_decoder - GENERIC( - DATARATE : integer RANGE 0 to 2; - FEC : integer RANGE 0 to 2 - ); - PORT ( - uplinkClk_i : in std_logic; - uplinkClkInEn_i : in std_logic; - uplinkClkOutEn_i : in std_logic; - -- Data - fec5_data_i : in std_logic_vector(233 downto 0); - fec5_fec_i : in std_logic_vector(19 downto 0); - fec12_data_i : in std_logic_vector(205 downto 0); - fec12_fec_i : in std_logic_vector(47 downto 0); - - fec5_data_o : out std_logic_vector(233 downto 0); - fec12_data_o : out std_logic_vector(205 downto 0); - - fec5_correction_pattern_o : out std_logic_vector(233 downto 0); - fec12_correction_pattern_o : out std_logic_vector(205 downto 0); - - -- Control - bypass : in std_logic - ); - END COMPONENT; + component lpgbtfpga_decoder + generic( + DATARATE : integer RANGE 0 TO 2; + FEC : integer RANGE 0 TO 2 + ); + port( + uplinkClk_i : in std_logic; + uplinkClkInEn_i : in std_logic; + uplinkClkOutEn_i : in std_logic; + fec5_data_i : in std_logic_vector(233 downto 0); + fec5_fec_i : in std_logic_vector(19 downto 0); + fec12_data_i : in std_logic_vector(205 downto 0); + fec12_fec_i : in std_logic_vector(47 downto 0); + fec5_data_o : out std_logic_vector(233 downto 0); + fec12_data_o : out std_logic_vector(205 downto 0); + fec5_correction_pattern_o : out std_logic_vector(233 downto 0); + fec12_correction_pattern_o : out std_logic_vector(205 downto 0); + bypass : in std_logic + ); + end component lpgbtfpga_decoder; --! Uplink datapath COMPONENT lpgbtfpga_descrambler GENERIC( diff --git a/sources/TTCdataEmulator/TTC_Emulator.vhd b/sources/TTCdataEmulator/TTC_Emulator.vhd index 194004d231dfc15c6b476f2439f91e6db6faa16e..1bb4541917b85cb9fe524174a52b054d6f793b80 100644 --- a/sources/TTCdataEmulator/TTC_Emulator.vhd +++ b/sources/TTCdataEmulator/TTC_Emulator.vhd @@ -10,9 +10,8 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" -library work; use work.pcie_package.all; use work.FELIX_package.all; @@ -32,7 +31,7 @@ architecture Behavioral of TTC_Emulator is signal input_ecr_period : unsigned(31 downto 0); signal input_bcr_period : unsigned(31 downto 0); signal input_long_Bch : std_logic_vector(31 downto 0); -- default ... - signal input_broadcast : std_logic_vector(5 downto 0); -- default ... + --signal input_broadcast : std_logic_vector(5 downto 0); -- default ... signal set_default : std_logic; signal single_l1a_long : std_logic := '0'; @@ -58,7 +57,7 @@ architecture Behavioral of TTC_Emulator is signal Bch_long_one_bit : std_logic := '1'; signal Bch_long_valid_i : std_logic := '0'; signal Bch_long_valid : std_logic := '0'; - signal Bch_long_end : std_logic := '0'; + --signal Bch_long_end : std_logic := '0'; signal Bch_long_user : std_logic_vector(41 downto 0) := (others => '1'); signal l1_accept : std_logic := '0'; @@ -71,12 +70,12 @@ architecture Behavioral of TTC_Emulator is signal Data_LongB : std_logic_vector(7 downto 0); signal Hamming : std_logic_vector(6 downto 0); - signal Bch_broad : std_logic_vector(5 downto 0) := (others => '1'); + --signal Bch_broad : std_logic_vector(5 downto 0) := (others => '1'); begin -- if both ttc selector and ttc enable are high, than the enable will be active - en <= to_sl(register_map_control.ttc_emu.sel) and to_sl(register_map_control.ttc_emu.ena); + en <= to_sl(register_map_control.TTC_EMU.SEL) and to_sl(register_map_control.TTC_EMU.ENA); -- temporary here, I am not yet sure I want to keep it.. process(Clock) @@ -84,7 +83,7 @@ begin if rising_edge(Clock) then if Reset = '1' then input_long_Bch <= (others => '1'); - input_broadcast <= (others => '0'); + --input_broadcast <= (others => '0'); set_default <= '0'; single_l1a_long <= '0'; single_ecr_long <= '0'; @@ -99,7 +98,7 @@ begin input_bcr_period <= unsigned(register_map_control.TTC_EMU_BCR_PERIOD); input_long_Bch <= (register_map_control.TTC_EMU_LONG_CHANNEL_DATA); - input_broadcast <= (register_map_control.TTC_EMU_CONTROL.BROADCAST); + --input_broadcast <= (register_map_control.TTC_EMU_CONTROL.BROADCAST); set_default <= to_sl(register_map_control.TTC_EMU_RESET); @@ -291,20 +290,21 @@ begin -- Assignation of values for Bchannel Bch_long_user <= "01" & TTCrx_address & External & '1' & SubAddress & Data_LongB & Hamming & '1'; - valid_creation: entity work.pulse_extender + valid_creation: entity work.PULSE_EXTENDER generic map ( - pulse_length => 42 -- number of counts + PULSE_LENGTH => 42 -- number of counts ) port map ( - clk => Clock, -- clock - rst => Reset, -- sync reset - sig_in => l1_accept, -- input signal - sig_out => Bch_long_valid_i -- output signal + CLK => Clock, -- clock + RST => Reset, -- sync reset + SIG_IN => l1_accept, -- input signal + SIG_OUT => Bch_long_valid_i -- output signal ); delay_bch: entity work.delay_chain generic map ( - d_depth => 10 -- number of clock cycles it shell be delayed + d_depth => 10, -- number of clock cycles it shell be delayed + d_width => 1 ) port map ( clk => Clock, -- clock diff --git a/sources/TTCdataEmulator/pulse_extender.vhd b/sources/TTCdataEmulator/pulse_extender.vhd index 365e98825f14f6bf21576296215ffc3c1caa549c..b8f4edc1a46f329db39ffe5a5f92fc04ac8675f2 100644 --- a/sources/TTCdataEmulator/pulse_extender.vhd +++ b/sources/TTCdataEmulator/pulse_extender.vhd @@ -27,7 +27,6 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -library work; use work.FELIX_package.all; entity PULSE_EXTENDER is diff --git a/sources/centralRouter/MUX8_Nbit.vhd b/sources/centralRouter/MUX8_Nbit.vhd index be9f697dbac1122b35d67af43c670d8fda9e6d5c..f2f214da354ef199abe569839d009783a6911dad 100644 --- a/sources/centralRouter/MUX8_Nbit.vhd +++ b/sources/centralRouter/MUX8_Nbit.vhd @@ -7,10 +7,9 @@ --! Project Name: FELIX ---------------------------------------------------------------------------------- --! Use standard library -library IEEE,work; +library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use work.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" library unisim; use unisim.vcomponents.all; diff --git a/sources/centralRouter/TTCtoHost_channel.vhd b/sources/centralRouter/TTCtoHost_channel.vhd index 0d279c98fc69e181c3f344c1f4c5d7fe033e52f7..612960e95ed0d3ca7151e5bac2dc4b62402f1376 100644 --- a/sources/centralRouter/TTCtoHost_channel.vhd +++ b/sources/centralRouter/TTCtoHost_channel.vhd @@ -7,10 +7,10 @@ --! Project Name: FELIX ---------------------------------------------------------------------------------- --! Use standard library -library work, ieee, XPM; +library ieee, XPM; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use work.all; use work.pcie_package.all; use work.centralRouter_package.all; @@ -47,9 +47,9 @@ port ( FIFOhasBlock : out std_logic; FIFOre : in std_logic; FIFOempty : out std_logic; - FIFOdvalid : out std_logic; + FIFOdvalid : out std_logic ----- - xoff_in : in std_logic + --xoff_in : in std_logic ); end TTCtoHost_channel; @@ -64,7 +64,7 @@ signal block_header : std_logic_vector(31 downto 0); signal TTCpacket_payload_in,TTCpacket_payload : std_logic_vector(159 downto 0); signal block_count, seq_count : std_logic_vector(4 downto 0) := (others=>'0'); ---- -signal fifo_full,fifo_pempty,fifo_almost_full : std_logic; +signal fifo_pempty,fifo_almost_full : std_logic; signal data_rdy,fifo_we : std_logic := '0'; signal fifo_din : std_logic_vector(255 downto 0) := (others=>'0'); signal fifo_din_pre : std_logic_vector(255 downto 0) := (others=>'0'); --IG: preparing the fifo din value @@ -205,7 +205,7 @@ begin -- counting times between data_rdy signals. -- the timeout counter runs until it is resetting, then it hold the value zero (counting down) until the next data_rdy signal -- data_rdy signal reload the counter with the define maximum value - if (timeoutSearch = '1') then + if (TimeoutSearch = '1') then if (data_rdy = '1') then TimeoutCounting <= TTC_ToHost_TO_max; InsertTO_Bytes <= '0'; @@ -328,7 +328,7 @@ block_header <= "1010101111001101" & seq_count & (std_logic_vector(to_unsigned(G -- TTCchFIFO : xpm_fifo_async - generic map ( + generic map ( -- @suppress "Generic map uses default values. Missing optional actuals: USE_ADV_FEATURES, SIM_ASSERT_CHK" FIFO_MEMORY_TYPE => "auto", --string; "auto", "block", or "distributed"; ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc"; RELATED_CLOCKS => 0, --positive integer; 0 or 1 @@ -347,28 +347,32 @@ block_header <= "1010101111001101" & seq_count & (std_logic_vector(to_unsigned(G WAKEUP_TIME => 0 --positive integer; 0 or 2; ) port map ( - sleep => '0', - rst => FifoFlush, - wr_clk => clk40, - wr_en => fifo_we, - din => fifo_din, - full => fifo_full, - overflow => open, - wr_rst_busy => open, - rd_clk => clk240, - rd_en => FIFOre, - dout => FIFOdout_s, - empty => FIFOempty_s, - underflow => open, - rd_rst_busy => open, - prog_full => fifo_almost_full, - wr_data_count => open, - prog_empty => fifo_pempty, - rd_data_count => open, - injectsbiterr => '0', - injectdbiterr => '0', - sbiterr => open, - dbiterr => open + sleep => '0', + rst => FifoFlush, + wr_clk => clk40, + wr_en => fifo_we, + din => fifo_din, + full => open, + prog_full => fifo_almost_full, + wr_data_count => open, + overflow => open, + wr_rst_busy => open, + almost_full => open, + wr_ack => open, + rd_clk => clk240, + rd_en => FIFOre, + dout => FIFOdout_s, + empty => FIFOempty_s, + prog_empty => fifo_pempty, + rd_data_count => open, + underflow => open, + rd_rst_busy => open, + almost_empty => open, + data_valid => open, + injectsbiterr => '0', + injectdbiterr => '0', + sbiterr => open, + dbiterr => open ); FIFOempty <= FIFOempty_s; @@ -398,7 +402,7 @@ end generate generate_all; -- -ICandEC_only: if generate_IC_EC_TTC_only = true generate +ICandEC_only: if generate_IC_EC_TTC_only generate -- FIFOdout <= (others =>'0'); FIFOhasBlock <= '0'; diff --git a/sources/centralRouter/centralRouter.vhd b/sources/centralRouter/centralRouter.vhd index 9ef976299de899ec2e6e6af729731714ab83efa9..f85dcc649f401b08709d2d1078cabcbe20342352 100644 --- a/sources/centralRouter/centralRouter.vhd +++ b/sources/centralRouter/centralRouter.vhd @@ -10,7 +10,7 @@ library IEEE, UNISIM; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all; -- @suppress "Deprecated package" +use ieee.std_logic_unsigned.all; use UNISIM.VCOMPONENTS.all; use work.all; use work.pcie_package.all; diff --git a/sources/decoding/ByteToAxiStream.vhd b/sources/decoding/ByteToAxiStream.vhd index bd99ec5bd02225dda347330bd30f88a4fa66d56d..16214de07322c5f9de2ccfccfaccba891de79d78 100644 --- a/sources/decoding/ByteToAxiStream.vhd +++ b/sources/decoding/ByteToAxiStream.vhd @@ -193,10 +193,10 @@ xpm_cdc_enable : xpm_cdc_single SRC_INPUT_REG => 1 -- DECIMAL; integer; 0=do not register input, 1=register input ) port map ( - dest_out => EnableIn_aclk, - dest_clk => m_axis_aclk, src_clk => clk40, - src_in => EnableIn + src_in => EnableIn, + dest_clk => m_axis_aclk, + dest_out => EnableIn_aclk ); m_axis.tdata <= m_axis_s.tdata; diff --git a/sources/decoding/Decoder8b10b.vhd b/sources/decoding/Decoder8b10b.vhd index e380ea415313933460dd86e4b83d2d4d7bad4dfc..ec053b42d0ee2b133c94d1bae0f01dbd15ba9400 100644 --- a/sources/decoding/Decoder8b10b.vhd +++ b/sources/decoding/Decoder8b10b.vhd @@ -60,7 +60,7 @@ GBT_mode: if (GENERATE_FEI4B = false and GENERATE_LCB_ENC = false) generate Char_EOB <= '1' when (decoder_out = Kchar_eob and CharIsK = '1' and DataInValid_p1 = '1') else '0'; end generate GBT_mode; -FEI4B: if (GENERATE_FEI4B = true) generate +FEI4B: if (GENERATE_FEI4B) generate ISK_comma <= '1' when (DataIn = FEI4B_COMMAp or DataIn = FEI4B_COMMAn) else '0'; Char_comma <= '1' when (decoder_out = FEI4B_Kchar_comma and CharIsK = '1' and DataInValid_p1 = '1') else '0'; Char_SOC <= '1' when (decoder_out = FEI4B_Kchar_sop and CharIsK = '1' and DataInValid_p1 = '1') else '0'; @@ -70,7 +70,7 @@ FEI4B: if (GENERATE_FEI4B = true) generate end generate FEI4B; -- DG: block below still configured for FEI4, only names were changed -LCB: if (GENERATE_LCB_ENC = true) generate +LCB: if (GENERATE_LCB_ENC) generate ISK_comma <= '1' when (DataIn = LCB_COMMAp or DataIn = LCB_COMMAn) else '0'; Char_comma <= '1' when (decoder_out = LCB_Kchar_comma and CharIsK = '1' and DataInValid_p1 = '1') else '0'; Char_SOC <= '1' when (decoder_out = LCB_Kchar_sop and CharIsK = '1' and DataInValid_p1 = '1') else '0'; diff --git a/sources/decoding/DecodingEgroupGBT.vhd b/sources/decoding/DecodingEgroupGBT.vhd index 3a94cfc59511d18909874280b52c913c23be1243..b00125bc91ed78738bfed7454e963f8ddf80dc9f 100644 --- a/sources/decoding/DecodingEgroupGBT.vhd +++ b/sources/decoding/DecodingEgroupGBT.vhd @@ -15,8 +15,8 @@ entity DecodingEgroupGBT is INCLUDE_8b10b : std_logic := '1'; INCLUDE_HDLC : std_logic := '1'; INCLUDE_DIRECT : std_logic := '1'; - BLOCKSIZE : integer := 1024; - LOCK_PERIOD : integer := 20480 --Maximum chunk size of 2048 bytes on slowest E-link supported. + BLOCKSIZE : integer := 1024 + --LOCK_PERIOD : integer := 20480 --Maximum chunk size of 2048 bytes on slowest E-link supported. ); port ( clk40 : in std_logic; --BC clock for DataIn diff --git a/sources/decoding/DecodingEpathGBT.vhd b/sources/decoding/DecodingEpathGBT.vhd index 9a5a3342dc4cd4501a84ebecc7fbd5fe4bd5b566..52b1a55ab79dd0b4037f9a359d319142a939df0c 100644 --- a/sources/decoding/DecodingEpathGBT.vhd +++ b/sources/decoding/DecodingEpathGBT.vhd @@ -155,10 +155,15 @@ g_includeHDLC: if INCLUDE_HDLC = '1' generate DecoderHDLCAligned <= '1'; DecoderHDLCFramingError <= '0'; decoderHDLC0: entity work.DecoderHDLC + generic map( + g_WORD_SIZE => 8, + g_DELIMITER => x"7E", + g_IDLE => x"7F" + ) port map( clk40 => clk40, - reset => reset, ena => EpathEnable, + reset => reset, DataIn => ElinkData(1 downto 0), DataOut => DecoderHDLCDataOut, DataOutValid => DecoderHDLCDataOutValid, diff --git a/sources/decoding/FullToAxis.vhd b/sources/decoding/FullToAxis.vhd index f1bde63894f7297b8c69b24c0989735cad049f99..3158ed27066afd2f252a42ede4e202b8a7ee313e 100644 --- a/sources/decoding/FullToAxis.vhd +++ b/sources/decoding/FullToAxis.vhd @@ -1,7 +1,7 @@ -library work, IEEE; +library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all; +--use ieee.std_logic_unsigned.all; use work.pcie_package.all; use work.axi_stream_package.all; use work.centralRouter_package.all; @@ -52,10 +52,10 @@ begin SRC_INPUT_REG => 0 ) port map ( - dest_out => LinkAligned_240, - dest_clk => clk240, src_clk => '0', - src_in => LinkAligned + src_in => LinkAligned, + dest_clk => clk240, + dest_out => LinkAligned_240 ); xpm_cdc_PathEnable : xpm_cdc_single @@ -66,10 +66,10 @@ begin SRC_INPUT_REG => 0 ) port map ( - dest_out => PathEnable_240, - dest_clk => clk240, src_clk => '0', - src_in => path_ena + src_in => path_ena, + dest_clk => clk240, + dest_out => PathEnable_240 ); @@ -189,17 +189,17 @@ crc_block: block begin -- CRC module takes 2 clock cycles to calculate CRC crc20_0: entity work.CRC - generic map( - Nbits => 32, - CRC_Width => 20, - G_Poly => x"8359f", - G_InitVal => x"fffff" - ) + --generic map( + -- Nbits => 32, + -- CRC_Width => 20, + -- G_Poly => x"8359f", + -- G_InitVal => x"fffff" + -- ) port map( CRC => crc_out, --in sync with din_r Calc => crc_calc, Clk => clk240, - DIn => s_axis.tdata, + Din => s_axis.tdata, Reset => crc_start); crc_calc <= not FMdin(32); @@ -296,7 +296,8 @@ fifo0: entity work.Axis32Fifo CLOCKING_MODE => "independent_clock", RELATED_CLOCKS => 0, FIFO_MEMORY_TYPE => "auto", - PACKET_FIFO => "false" + PACKET_FIFO => "false", + USE_BUILT_IN_FIFO => false ) port map ( -- axi stream slave diff --git a/sources/decoding/decoding.vhd b/sources/decoding/decoding.vhd index db2a930b204c1d04490c2f65708f1766955709ca..4209cf27a670cd66f7675c2330c4572b0800277c 100644 --- a/sources/decoding/decoding.vhd +++ b/sources/decoding/decoding.vhd @@ -220,8 +220,8 @@ begin INCLUDE_8b10b => IncludeDecodingEpath2_8b10b(egroup) or IncludeDecodingEpath4_8b10b(egroup) or IncludeDecodingEpath8_8b10b(egroup), INCLUDE_HDLC => IncludeDecodingEpath2_HDLC(egroup), INCLUDE_DIRECT => '1', - BLOCKSIZE => BLOCKSIZE, - LOCK_PERIOD => LOCK_PERIOD + BLOCKSIZE => BLOCKSIZE + --LOCK_PERIOD => LOCK_PERIOD ) port map( clk40 => clk40, @@ -255,8 +255,8 @@ begin ) port map( clk40 => clk40, - AlignmentPulseDeAlign => AlignmentPulseDeAlign, - AlignmentPulseAlign => AlignmentPulseAlign + AlignmentPulseAlign => AlignmentPulseAlign, + AlignmentPulseDeAlign => AlignmentPulseDeAlign ); end generate; diff --git a/sources/encoding/EncoderHDLC.vhd b/sources/encoding/EncoderHDLC.vhd index db6ed0cc0d37fdcf58e1feaf103ade016f375d58..c0873401b34ef4893ad9906ff4c43ea3f031507e 100644 --- a/sources/encoding/EncoderHDLC.vhd +++ b/sources/encoding/EncoderHDLC.vhd @@ -9,7 +9,7 @@ --! Use standard library library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use ieee.std_logic_unsigned.all; -- @suppress "Deprecated package" +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" library XPM; use XPM.VCOMPONENTS.all; @@ -19,25 +19,25 @@ use work.all; --! HDLC data mode EPROC_OUT2 module entity EncoderHDLC is -generic ( - HDLC_IDLE_STATE : std_logic_vector(7 downto 0) := (others=>'1') --IG: determine the HDLC line idle state. for EC: 0x7F, for IC: 0xFF -); -port ( - clk40 : in std_logic; --BC clock for DataIn - EnableIn : in std_logic; - - DataIn : in std_logic_vector(7 downto 0); --8b Data from AxiStreamtoByte - DataInValid : in std_logic; -- Data validated by AxiStreamtoByte - EOP_in : in std_logic; --End of Packet from AxiStreamtoByte - - -- readyIn : in std_logic; --gearbox not ready - - readyOut : out std_logic; --m_axis_tready toward AxiStreamToByte --falfonsi=getDataTirg - DataOut : out std_logic_vector(1 downto 0); --falfonsi: towards ??? - -- DataOutValid : out std_logic; --falfonsi: towards ??? - - rst : in std_logic -); + generic ( + HDLC_IDLE_STATE : std_logic_vector(7 downto 0) := (others=>'1') --IG: determine the HDLC line idle state. for EC: 0x7F, for IC: 0xFF + ); + port ( + clk40 : in std_logic; --BC clock for DataIn + EnableIn : in std_logic; + + DataIn : in std_logic_vector(7 downto 0); --8b Data from AxiStreamtoByte + DataInValid : in std_logic; -- Data validated by AxiStreamtoByte + EOP_in : in std_logic; --End of Packet from AxiStreamtoByte + + -- readyIn : in std_logic; --gearbox not ready + + readyOut : out std_logic; --m_axis_tready toward AxiStreamToByte --falfonsi=getDataTirg + DataOut : out std_logic_vector(1 downto 0); --falfonsi: towards ??? + -- DataOutValid : out std_logic; --falfonsi: towards ??? + + rst : in std_logic + ); end EncoderHDLC; --######################################### @@ -50,224 +50,226 @@ end EncoderHDLC; architecture Behavioral of EncoderHDLC is - signal readyout_i, readyout_ii : std_logic:= '0'; - signal vetoReadyOut_i : std_logic:= '0'; - signal bit_cnt,bit_cnt_r : std_logic_vector (1 downto 0) := (others=>'1'); - signal two_bit_out,EdataOUT_s : std_logic_vector (1 downto 0) := (others=>'1'); - signal bit_cnt_ena,ce,ce_i,re_r,oe : std_logic := '0'; - signal isflag_i : std_logic := '1'; - signal rst_fall,restart, re, isflag : std_logic; - signal dataByte : std_logic_vector (8 downto 0) := (others=>'1'); - signal bit_out_sr : std_logic_vector (5 downto 0); + signal readyout_i, readyout_ii : std_logic:= '0'; + signal vetoReadyOut_i : std_logic:= '0'; + signal bit_cnt : std_logic_vector (1 downto 0) := (others=>'1'); + signal two_bit_out,EdataOUT_s : std_logic_vector (1 downto 0) := (others=>'1'); + signal bit_cnt_ena,ce,ce_i : std_logic := '0'; + signal isflag_i : std_logic := '1'; + signal rst_fall,restart, re, isflag : std_logic; + signal dataByte : std_logic_vector (8 downto 0) := (others=>'1'); + signal bit_out_sr : std_logic_vector (5 downto 0); - signal send_out_trig : std_logic := '0'; - signal fifo_empty: std_logic := '0'; + --signal send_out_trig : std_logic := '0'; + --signal fifo_empty: std_logic := '0'; - signal DataInValid_i : std_logic := '0'; - signal DataIn_i : std_logic_vector(7 downto 0); + signal DataInValid_i : std_logic := '0'; + signal DataIn_i : std_logic_vector(7 downto 0); - signal shift : std_logic := '0'; - signal shift_i : std_logic := '0'; - signal running : std_logic := '0'; - signal sendSOP, sendEOP : std_logic := '0'; + signal shift : std_logic := '0'; + signal shift_i : std_logic := '0'; + signal running : std_logic := '0'; + signal sendEOP : std_logic := '0'; begin -pipeline : process(clk40) -begin - if(clk40'event and clk40='1')then - DataInValid_i <= DataInValid; - DataIn_i <= DataIn; - readyout_ii <= readyout_i; - readyOut <= readyout_ii and not vetoReadyOut_i and not (dataInValid and not running ); - end if; -end process; -------------------------------------------------------------------------------------------- --- restarting data requests after reset fall -------------------------------------------------------------------------------------------- -rst_fall_pulse: entity work.pulse_fall_pw01 port map(clk => clk40,trigger => rst,pulseout => rst_fall); -restart_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>10,pw=>1) port map(clk => clk40, trigger => rst_fall,pulseout => restart); - --- -process(clk40) -begin - if clk40'event and clk40 = '1' then - if rst = '1' then - ce <= '0'; - elsif restart = '1' then - ce <= '1'; + pipeline : process(clk40) + begin + if(clk40'event and clk40='1')then + DataInValid_i <= DataInValid; + DataIn_i <= DataIn; + readyout_ii <= readyout_i; + readyOut <= readyout_ii and not vetoReadyOut_i and not (DataInValid and not running ); end if; - ce_i <= ce; - end if; -end process; --- ---ce_1st_clk_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk40,ce,ce_1st_clk); --- - -------------------------------------------------------------------------------------------- --- input latching @ bitCLKx4 -------------------------------------------------------------------------------------------- -process(clk40) -begin - if clk40'event and clk40 = '1' then - if (rst = '1') then - running <= '0'; - vetoReadyOut_i <= '0'; - dataByte <= '1' & HDLC_IDLE_STATE; - sendEOP <= '0'; - else - if(EnableIn = '1')then - if (readyout_i = '1') then - vetoReadyOut_i <= '0'; - if (DataInValid_i = '1') and (running = '0') then --send SOP - vetoReadyOut_i <= '1'; - dataByte <= '1' & HDLC_flag; - running <= '1'; - elsif (sendEOP = '1') then --send EOP - dataByte <= '1' & HDLC_flag; - running <= '0'; - sendEOP <= '0'; - vetoReadyOut_i <= '1'; - elsif (DataInValid_i = '1') and (EOP_in = '1') and (running = '1') then --last word before EOP - sendEOP <= '1'; - dataByte <= '0' & DataIn_i(7 downto 0); - elsif (DataInValid_i = '1') and (running = '1') then --normal word - dataByte <= '0' & DataIn_i(7 downto 0); - else --fifo empty or dataInValid = '0' - dataByte <= '1' & HDLC_IDLE_STATE; - end if; + end process; + ------------------------------------------------------------------------------------------- + -- restarting data requests after reset fall + ------------------------------------------------------------------------------------------- + rst_fall_pulse: entity work.pulse_fall_pw01 port map(clk => clk40,trigger => rst,pulseout => rst_fall); + restart_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>10,pw=>1) port map(clk => clk40, trigger => rst_fall,pulseout => restart); + + -- + process(clk40) + begin + if clk40'event and clk40 = '1' then + if rst = '1' then + ce <= '0'; + elsif restart = '1' then + ce <= '1'; + end if; + ce_i <= ce; end if; - end if; - end if; - end if; - -end process; --- - - - -------------------------------------------------------------------------------------------- --- bit counter: counting 8 bit to serialize the out while pausing for zero-bit stuffing -------------------------------------------------------------------------------------------- ---bit_stuffing_case <= '1' when (bit_out_sr_clk0 = "11111" and isflag_i = '0') else '0'; ---bit_cnt_ena <= ce and (not bit_stuffing_case); -re <= '1' when (bit_cnt = "11" and bit_cnt_ena = '1') else '0'; -getDataTrig_pulse_readyout: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk=>clk40,trigger=>re,pulseout=>readyout_i); - ---getDataTrig_pulse_DataOutValid: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk=>clk40,trigger=>re,pulseout=>DataOutValid); --- -process(clk40) -begin - if clk40'event and clk40 = '1' then - if ce = '1' then - if bit_cnt_ena = '1' then - bit_cnt <= bit_cnt + 1; + end process; + -- + --ce_1st_clk_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk40,ce,ce_1st_clk); + -- + + ------------------------------------------------------------------------------------------- + -- input latching @ bitCLKx4 + ------------------------------------------------------------------------------------------- + process(clk40) + begin + if clk40'event and clk40 = '1' then + if (rst = '1') then + running <= '0'; + vetoReadyOut_i <= '0'; + dataByte <= '1' & HDLC_IDLE_STATE; + sendEOP <= '0'; + else + if(EnableIn = '1')then + if (readyout_i = '1') then + vetoReadyOut_i <= '0'; + if (DataInValid_i = '1') and (running = '0') then --send SOP + vetoReadyOut_i <= '1'; + dataByte <= '1' & HDLC_flag; + running <= '1'; + elsif (sendEOP = '1') then --send EOP + dataByte <= '1' & HDLC_flag; + running <= '0'; + sendEOP <= '0'; + vetoReadyOut_i <= '1'; + elsif (DataInValid_i = '1') and (EOP_in = '1') and (running = '1') then --last word before EOP + sendEOP <= '1'; + dataByte <= '0' & DataIn_i(7 downto 0); + elsif (DataInValid_i = '1') and (running = '1') then --normal word + dataByte <= '0' & DataIn_i(7 downto 0); + else --fifo empty or dataInValid = '0' + dataByte <= '1' & HDLC_IDLE_STATE; + end if; + end if; + end if; end if; - else - bit_cnt <= (others=>'1'); end if; - end if; -end process; --- - -------------------------------------------------------------------------------------------- --- comma selector -------------------------------------------------------------------------------------------- -process(clk40) -begin - if clk40'event and clk40 = '1' then - re_r <= re; - end if; -end process; --- -isflag <= dataByte(8); --'1' when (byte_out = HDLC_flag) else '0'; + end process; + -- + ------------------------------------------------------------------------------------------- + -- bit counter: counting 8 bit to serialize the out while pausing for zero-bit stuffing + ------------------------------------------------------------------------------------------- + --bit_stuffing_case <= '1' when (bit_out_sr_clk0 = "11111" and isflag_i = '0') else '0'; + --bit_cnt_ena <= ce and (not bit_stuffing_case); + re <= '1' when (bit_cnt = "11" and bit_cnt_ena = '1') else '0'; + getDataTrig_pulse_readyout: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk=>clk40,trigger=>re,pulseout=>readyout_i); -------------------------------------------------------------------------------------------- --- bit selector -------------------------------------------------------------------------------------------- --- -process(clk40) -begin - if clk40'event and clk40 = '1' then - bit_cnt_r <= bit_cnt; - end if; -end process; --- -process(bit_cnt,dataByte, bit_cnt_ena) -begin - if bit_cnt_ena = '1' then - case (bit_cnt) is - when "00" => two_bit_out <= dataByte(1 downto 0); - when "01" => two_bit_out <= dataByte(3 downto 2); - when "10" => two_bit_out <= dataByte(5 downto 4); - when "11" => two_bit_out <= dataByte(7 downto 6); - when others => - end case; - end if; -end process; --- -process(clk40) -begin - if clk40'event and clk40 = '1' then - oe <= bit_cnt_ena; - end if; -end process; --- --- -process(clk40) -begin - if clk40'event and clk40 = '1' then - if rst = '1' then - bit_out_sr <= (others=>'1'); - EdataOUT_s <= "11"; + --getDataTrig_pulse_DataOutValid: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk=>clk40,trigger=>re,pulseout=>DataOutValid); + -- + process(clk40) + begin + if clk40'event and clk40 = '1' then + if ce = '1' then + if bit_cnt_ena = '1' then + bit_cnt <= bit_cnt + 1; + end if; + else + bit_cnt <= (others=>'1'); + end if; + end if; + end process; + -- + + + ------------------------------------------------------------------------------------------- + -- comma selector + ------------------------------------------------------------------------------------------- + --process(clk40) + --begin + -- if clk40'event and clk40 = '1' then + -- re_r <= re; + -- end if; + --end process; + -- + isflag <= dataByte(8); --'1' when (byte_out = HDLC_flag) else '0'; + + + + + ------------------------------------------------------------------------------------------- + -- bit selector + ------------------------------------------------------------------------------------------- + -- + --process(clk40) + --begin + -- if clk40'event and clk40 = '1' then + -- bit_cnt_r <= bit_cnt; + -- end if; + --end process; + -- + process(bit_cnt,dataByte, bit_cnt_ena) + begin + if bit_cnt_ena = '1' then + case (bit_cnt) is + when "00" => two_bit_out <= dataByte(1 downto 0); + when "01" => two_bit_out <= dataByte(3 downto 2); + when "10" => two_bit_out <= dataByte(5 downto 4); + when "11" => two_bit_out <= dataByte(7 downto 6); + when others => two_bit_out <= "00"; --default to avoid creating a latch + end case; else - bit_cnt_ena <= ce; - shift_i <= shift; - isflag_i <= isflag; - if shift = '0' then - EdataOUT_s <= (bit_out_sr(4) or (not ce_i)) & (bit_out_sr(5) or (not ce_i)); - if(bit_out_sr(5 downto 2) = x"F") and (two_bit_out(0) = '1') and (isflag = '0') then --5 consecutive 1, adding '0' - bit_out_sr <= two_bit_out(1) & '0' & two_bit_out(0) & bit_out_sr(5 downto 3); - shift <= '1'; - elsif(bit_out_sr(5 downto 3) = "111") and (two_bit_out = "11") and (isflag = '0') then --5 consecutive 1, adding '0' - bit_out_sr <= '0' & two_bit_out(1) & two_bit_out(0) & bit_out_sr(5 downto 3); - shift <= '1'; + two_bit_out <= "00"; --default to avoid creating a latch + end if; + end process; + -- + --process(clk40) + --begin + -- if clk40'event and clk40 = '1' then + -- oe <= bit_cnt_ena; + -- end if; + --end process; + -- + -- + process(clk40) + begin + if clk40'event and clk40 = '1' then + if rst = '1' then + bit_out_sr <= (others=>'1'); + EdataOUT_s <= "11"; else - bit_out_sr <= two_bit_out & bit_out_sr(5 downto 2); - end if; - else --shift = '1' - EdataOUT_s <= (bit_out_sr(3) or (not ce_i)) & (bit_out_sr(4) or (not ce_i)); - if(bit_out_sr(4 downto 0) = "11111") and (isflag_i = '0') and (shift_i = '1') then --5 consecutive 1, adding '0' - bit_cnt_ena <= '0'; - bit_out_sr <= bit_out_sr(5) & '0' & bit_out_sr(4 downto 1); - shift <= '0'; - elsif(bit_out_sr(5 downto 1) = "11111") and (isflag_i = '0') then --5 consecutive 1, adding '0' - bit_cnt_ena <= '0'; - bit_out_sr <= '0' & bit_out_sr(5 downto 1); - shift <= '0'; - else - bit_out_sr <= two_bit_out & bit_out_sr(5 downto 2); - end if; - end if; + bit_cnt_ena <= ce; + shift_i <= shift; + isflag_i <= isflag; + if shift = '0' then + EdataOUT_s <= (bit_out_sr(4) or (not ce_i)) & (bit_out_sr(5) or (not ce_i)); + if(bit_out_sr(5 downto 2) = x"F") and (two_bit_out(0) = '1') and (isflag = '0') then --5 consecutive 1, adding '0' + bit_out_sr <= two_bit_out(1) & '0' & two_bit_out(0) & bit_out_sr(5 downto 3); + shift <= '1'; + elsif(bit_out_sr(5 downto 3) = "111") and (two_bit_out = "11") and (isflag = '0') then --5 consecutive 1, adding '0' + bit_out_sr <= '0' & two_bit_out(1) & two_bit_out(0) & bit_out_sr(5 downto 3); + shift <= '1'; + else + bit_out_sr <= two_bit_out & bit_out_sr(5 downto 2); + end if; + else --shift = '1' + EdataOUT_s <= (bit_out_sr(3) or (not ce_i)) & (bit_out_sr(4) or (not ce_i)); + if(bit_out_sr(4 downto 0) = "11111") and (isflag_i = '0') and (shift_i = '1') then --5 consecutive 1, adding '0' + bit_cnt_ena <= '0'; + bit_out_sr <= bit_out_sr(5) & '0' & bit_out_sr(4 downto 1); + shift <= '0'; + elsif(bit_out_sr(5 downto 1) = "11111") and (isflag_i = '0') then --5 consecutive 1, adding '0' + bit_cnt_ena <= '0'; + bit_out_sr <= '0' & bit_out_sr(5 downto 1); + shift <= '0'; + else + bit_out_sr <= two_bit_out & bit_out_sr(5 downto 2); + end if; + end if; + end if; end if; - end if; -end process; --- + end process; + -- -------------------------------------------------------------------------------------------- --- sending out 2 bits @ bitCLK -------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- sending out 2 bits @ bitCLK + ------------------------------------------------------------------------------------------- --- + -- -DataOut <= EdataOUT_s; --- + DataOut <= EdataOUT_s; + -- end Behavioral; diff --git a/sources/encoding/EncodingGearBox.vhd b/sources/encoding/EncodingGearBox.vhd index c52d4ed667b7ecba74ad39ba1aeba0056719c204..c5a38a410eb8920c28201226db3788cb6dc0ebc7 100644 --- a/sources/encoding/EncodingGearBox.vhd +++ b/sources/encoding/EncodingGearBox.vhd @@ -142,9 +142,9 @@ begin end if; if((ReverseOutputBits xor MsbFirst) = '0') then - ElinkData(wOut -1 downto 0) <= reverse_any_vector(shift(cnt_s - 1 downto cnt_s-Wout)); + ELinkData(wOut -1 downto 0) <= reverse_any_vector(shift(cnt_s - 1 downto cnt_s-wOut)); else - ElinkData(wOut -1 downto 0) <= shift(cnt_s - 1 downto cnt_s-wOut); + ELinkData(wOut -1 downto 0) <= shift(cnt_s - 1 downto cnt_s-wOut); end if; end if; diff --git a/sources/encoding/ExtendedTestPulse.vhd b/sources/encoding/ExtendedTestPulse.vhd index e7f6accfa9c8aa30fb78778d9425745e282e08bc..e515521475d739229e05b775f1bb97bb5d8e62a3 100644 --- a/sources/encoding/ExtendedTestPulse.vhd +++ b/sources/encoding/ExtendedTestPulse.vhd @@ -8,7 +8,7 @@ ---------------------------------------------------------------------------------- --! Use standard library -library work, IEEE, UNISIM; +library IEEE, UNISIM; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; diff --git a/sources/encoding/enc_8b10.vhd b/sources/encoding/enc_8b10.vhd index f605068b042be65983812c54fcb7e205c399883c..54f37d9b792482a76fcd316ff5af7b3c38f98d6d 100644 --- a/sources/encoding/enc_8b10.vhd +++ b/sources/encoding/enc_8b10.vhd @@ -45,7 +45,7 @@ architecture behavioral of enc_8b10b is signal pd1s4 : std_logic; -- (!fi & !gi) | (ki & ((fi & !gi) | (!fi & gi))) ; signal ndos4 : std_logic; -- (!fi & !gi) ; signal pdos4 : std_logic; -- fi & gi & hi ; - signal illegalk : std_logic; -- ki & + --signal illegalk : std_logic; -- ki & signal compls6 : std_logic; -- (pd1s6 & !dispin) | (nd1s6 & dispin) ; signal disp6 : std_logic; -- dispin ^ (ndos6 | pdos6) ; signal compls4 : std_logic; -- (pd1s4 & !disp6) | (nd1s4 & disp6) ; @@ -160,9 +160,9 @@ begin -- K27 is 11011 -- K29 is 11101 -- K30 is 11110 - so K23/27/29/30 are ei and l31 - illegalk <= KI and - (ai or bi or not ci or not di or not ei) and -- not K28.0->7 - (not fi or not gi or not hi or not ei or not l31) ; -- not K23/27/29/30.7 + --illegalk <= KI and + --(ai or bi or not ci or not di or not ei) and -- not K28.0->7 + --(not fi or not gi or not hi or not ei or not l31) ; -- not K23/27/29/30.7 -- now determine whether to do the complementing -- complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set diff --git a/sources/encoding/encoding.vhd b/sources/encoding/encoding.vhd index 3d9c3efe13367932056f9d1e81dba0c583a2f1b5..b1800e116608dbaffdc9e9162ffeeff996e09abd 100644 --- a/sources/encoding/encoding.vhd +++ b/sources/encoding/encoding.vhd @@ -24,7 +24,7 @@ use IEEE.STD_LOGIC_1164.ALL; use work.axi_stream_package.all; use work.centralRouter_package.all; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all; -- @suppress "Deprecated package" +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use work.pcie_package.all; use work.FELIX_gbt_package.all; use work.FELIX_package.all; @@ -53,7 +53,7 @@ entity encoding is register_map_control : in register_map_control_type; register_map_encoding_monitor : out register_map_encoding_monitor_type; GBT_DOWNLINK_USER_DATA : out txrx120b_type(0 to GBT_NUM-1); --GBT data output - lpGBT_DOWNLINK_USER_DATA : out txrx32b_type(0 to GBT_NUM-1); --TODO: Connect to E-groups, e.g. Strips LCB encoder + lpGBT_DOWNLINK_USER_DATA : out txrx32b_type(0 to GBT_NUM-1); --TODO: Connect to E-groups, e.g. Strips LCB encoder -- @suppress "Unused port: lpGBT_DOWNLINK_USER_DATA is not used in work.encoding(Behavioral)" lpGBT_DOWNLINK_IC_DATA : out txrx2b_type(0 to GBT_NUM-1); lpGBT_DOWNLINK_EC_DATA : out txrx2b_type(0 to GBT_NUM-1); TTCin : in std_logic_vector(9 downto 0) @@ -288,6 +288,10 @@ begin --IG ttcFanDly : for J in 0 to 9 generate ttcFanDly : for J in 0 to 10 generate --IG: add another bit to support the extended Test Pulse TTC_DELAY_SRL : SRL16E + generic map( + INIT => x"0000", + IS_CLK_INVERTED => '0' + ) port map ( Q => TTCin_array(I)(J), --delayed copy of TTCin A0 => TTC_DELAY_array(I)(0), --input from control register diff --git a/sources/flash/flash_ipcore_bnl.vhd b/sources/flash/flash_ipcore_bnl.vhd index 99cb536dbef5d4e90b2ab403625aa907e43fc693..8bddbfcf15ca36b8b743b8221ca26d22891a1bf9 100644 --- a/sources/flash/flash_ipcore_bnl.vhd +++ b/sources/flash/flash_ipcore_bnl.vhd @@ -31,8 +31,8 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_ARITH.ALL;-- @suppress "Deprecated package" +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. @@ -46,7 +46,7 @@ entity flash_ipcore_bnl is Port ( clk_i : in std_logic; rst_i : in std_logic; - init_i : in std_logic; + --init_i : in std_logic; readstatus_i : in std_logic; clearstatus_i : in std_logic; eraseblock_i : in std_logic; @@ -71,7 +71,7 @@ entity flash_ipcore_bnl is flash_ce_n_o : out std_logic; flash_clk_o : out std_logic; flash_re_n_o : out std_logic; - flash_rst_n_o : out std_logic; + --flash_rst_n_o : out std_logic; --flash_wait_i : in std_logic; flash_we_n_o : out std_logic; flash_wp_n_o : out std_logic @@ -91,7 +91,7 @@ signal ipcore_op_done : std_logic:='0'; signal WRITE_A : std_logic_vector(15 downto 0); signal WRITE_B : std_logic_vector(15 downto 0); signal flash_data_out : std_logic_vector(15 downto 0); -signal flash_data_rd_o_i : std_logic_vector(15 downto 0); +--signal flash_data_rd_o_i : std_logic_vector(15 downto 0); signal cmd_type : std_logic_vector(1 downto 0):="00"; signal counter : std_logic_vector(2 downto 0):="000"; @@ -226,7 +226,7 @@ begin ipcore_op_done <= '0'; ipcore_busy <= '0'; bus_status <= IDLE; - when others => + when others => -- @suppress "Case statement contains all choices explicitly. You can safely remove the redundant 'others'" bus_status <= IDLE; end case; end if; diff --git a/sources/flash/flash_wrapper.vhd b/sources/flash/flash_wrapper.vhd index cc7e88cb2a2a42a1c5705f51ef2b87a3372190d7..b7dd5c4fba454734922f6a9b9ffdb4b1040d7d8f 100644 --- a/sources/flash/flash_wrapper.vhd +++ b/sources/flash/flash_wrapper.vhd @@ -30,13 +30,13 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_ARITH.ALL;-- @suppress "Deprecated package" +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" library UNISIM; use UNISIM.VComponents.all; -library WORK; +--library WORK; use work.pcie_package.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values @@ -82,8 +82,8 @@ architecture Behavioral of flash_wrapper is signal flash_a_i : std_logic_vector(26 downto 0); - signal do_rst_i : std_logic; - signal do_init_i : std_logic; + --signal do_rst_i : std_logic; + --signal do_init_i : std_logic; signal do_readstatus_i : std_logic; signal do_clearstatus_i : std_logic; signal do_eraseblock_i : std_logic; @@ -130,13 +130,13 @@ architecture Behavioral of flash_wrapper is signal do_readstatus_i_2r : std_logic; signal do_readstatus_i_rising : std_logic; - signal do_init_i_r : std_logic; - signal do_init_i_2r : std_logic; - signal do_init_i_rising : std_logic; + --signal do_init_i_r : std_logic; + --signal do_init_i_2r : std_logic; + --signal do_init_i_rising : std_logic; - signal do_rst_i_r : std_logic; - signal do_rst_i_2r : std_logic; - signal do_rst_i_rising : std_logic; + --signal do_rst_i_r : std_logic; + --signal do_rst_i_2r : std_logic; + --signal do_rst_i_rising : std_logic; signal do_special_rdstatus_i_r : std_logic; signal do_special_rdstatus_i : std_logic; @@ -156,7 +156,7 @@ architecture Behavioral of flash_wrapper is begin flash_a <= flash_a_i(24 downto 0); - flash_SEL <= flash_SEL_i; + flash_SEL <= flash_sel_i; flash_a_msb <= flash_par_wr when flash_par_sel_i = '1' else "ZZ"; flash_par_rd <= flash_a_msb when flash_par_sel_i = '0' else flash_par_wr; @@ -172,8 +172,8 @@ begin do_cfiquery_i <= '0'; do_readdeviceident_i <= to_sl(register_map_control.CONFIG_FLASH_WR.DO_READDEVICEID); - do_init_i <= to_sl(register_map_control.CONFIG_FLASH_WR.DO_INIT); - do_rst_i <= to_sl(register_map_control.CONFIG_FLASH_WR.DO_RESET); + --do_init_i <= to_sl(register_map_control.CONFIG_FLASH_WR.DO_INIT); + --do_rst_i <= to_sl(register_map_control.CONFIG_FLASH_WR.DO_RESET); flash_wr_data <= register_map_control.CONFIG_FLASH_WR.WRITE_DATA; flash_adr <= register_map_control.CONFIG_FLASH_WR.ADDRESS; @@ -224,13 +224,13 @@ begin do_readstatus_i_2r <= do_readstatus_i_r; do_readstatus_i_rising <= do_readstatus_i_r and (not do_readstatus_i_2r); - do_init_i_r <= do_init_i; - do_init_i_2r <= do_init_i_r; - do_init_i_rising <= do_init_i_r and (not do_init_i_2r); + --do_init_i_r <= do_init_i; + --do_init_i_2r <= do_init_i_r; + --do_init_i_rising <= do_init_i_r and (not do_init_i_2r); - do_rst_i_r <= do_rst_i; - do_rst_i_2r <= do_rst_i_r; - do_rst_i_rising <= do_rst_i_r and (not do_rst_i_2r); + --do_rst_i_r <= do_rst_i; + --do_rst_i_2r <= do_rst_i_r; + --do_rst_i_rising <= do_rst_i_r and (not do_rst_i_2r); do_special_rdstatus_i_r <= do_special_rdstatus_i; do_special_rdstatus_i_2r <= do_special_rdstatus_i_r; @@ -249,38 +249,35 @@ cfi: entity work.flash_ipcore_bnl ADDR_WIDTH => 27 ) port map( - clk_i => clk, - rst_i => rst, - - init_i => do_init_i_rising, - readstatus_i => do_readstatus_i_rising, - clearstatus_i => do_clearstatus_i_rising, - eraseblock_i => do_eraseblock_i_rising, - unlockblock_i => do_unlockblock_i_rising, - write_word_i => do_write_i_rising, - read_i => do_read_i_rising, - readdevid_i => do_readdeviceident_i_rising, - cfiquery_i => do_cfiquery_i_rising, - special_write_i => do_special_write_i_rising, - special_rdstatus_i => do_special_rdstatus_i_rising, - - flash_data_rd_o => flash_rd_data, - flash_data_wr_i => flash_wr_data, - flash_d_debug => open, - flash_addr_cmd_i => flash_adr, - ipcore_op_done_o => flash_req_done_o, - ipcore_busy_o => flash_busy_o, - - flash_dq_io => flash_d, - flash_addr_o => flash_a_i, - flash_adv_n_o => flash_adv, - flash_ce_n_o => flash_ce, - flash_clk_o => flash_cclk, - flash_re_n_o => flash_re, - flash_rst_n_o => open, + clk_i => clk, + rst_i => rst, + --init_i => do_init_i_rising, + readstatus_i => do_readstatus_i_rising, + clearstatus_i => do_clearstatus_i_rising, + eraseblock_i => do_eraseblock_i_rising, + unlockblock_i => do_unlockblock_i_rising, + write_word_i => do_write_i_rising, + special_write_i => do_special_write_i_rising, + read_i => do_read_i_rising, + readdevid_i => do_readdeviceident_i_rising, + cfiquery_i => do_cfiquery_i_rising, + special_rdstatus_i => do_special_rdstatus_i_rising, + flash_data_rd_o => flash_rd_data, + flash_data_wr_i => flash_wr_data, + flash_d_debug => open, + flash_addr_cmd_i => flash_adr, + ipcore_op_done_o => flash_req_done_o, + ipcore_busy_o => flash_busy_o, + flash_dq_io => flash_d, + flash_addr_o => flash_a_i, + flash_adv_n_o => flash_adv, + flash_ce_n_o => flash_ce, + flash_clk_o => flash_cclk, + flash_re_n_o => flash_re, + --flash_rst_n_o => open, --flash_wait_i => '0', - flash_we_n_o => flash_we, - flash_wp_n_o => open + flash_we_n_o => flash_we, + flash_wp_n_o => open ); diff --git a/sources/housekeeping/GenericConstantsToRegs.vhd b/sources/housekeeping/GenericConstantsToRegs.vhd index ead77e4bbf1b60d3513bcd23417f911b13e1a9a9..04397f536a548065f1cebb6915c79e82ab8ad048 100644 --- a/sources/housekeeping/GenericConstantsToRegs.vhd +++ b/sources/housekeeping/GenericConstantsToRegs.vhd @@ -2,10 +2,10 @@ -library ieee, UNISIM, work; +library ieee, UNISIM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use ieee.std_logic_1164.all; use work.pcie_package.all; use work.centralRouter_package.all; @@ -14,21 +14,17 @@ entity GenericConstantsToRegs is generic( GBT_NUM : integer := 24; ENDPOINTS : integer := 1; --Number of PCIe endpoints on the card. - GBT_MAPPING : integer := 0; -- GBT mapping: 0 NORMAL CXP1 -> GBT1-12 | 1 ALTERNATE CXP1 -> GBT 1-4,9-12,17-20 OPTO_TRX : integer := 2; - DEBUG_MODE : boolean := false; generateTTCemu : boolean := false; AUTOMATIC_CLOCK_SWITCH : boolean := false; FIRMWARE_MODE : integer := 0; USE_Si5324_RefCLK : boolean := false; - includeDirectMode : boolean := true; GENERATE_XOFF : boolean := true; -- FromHost Xoff transmission enabled on Full mode busy IncludeDecodingEpath2_HDLC : std_logic_vector(6 downto 0) := "1111111"; IncludeDecodingEpath2_8b10b : std_logic_vector(6 downto 0) := "1111111"; IncludeDecodingEpath4_8b10b : std_logic_vector(6 downto 0) := "1111111"; IncludeDecodingEpath8_8b10b : std_logic_vector(6 downto 0) := "1111111"; IncludeDecodingEpath16_8b10b : std_logic_vector(6 downto 0) := "0000000"; --lpGBT only - IncludeDecodingEpath32_8b10b : std_logic_vector(6 downto 0) := "0000000"; --lpGBT only IncludeEncodingEpath2_HDLC : std_logic_vector(4 downto 0) := "00000"; IncludeEncodingEpath2_8b10b : std_logic_vector(4 downto 0) := "00000"; IncludeEncodingEpath4_8b10b : std_logic_vector(4 downto 0) := "00000"; diff --git a/sources/housekeeping/clock_and_reset.vhd b/sources/housekeeping/clock_and_reset.vhd index 485770a0ffc2a0579639ceb9da969bbd731c063e..6ee140c7930945225047a6158a17fede423f9eef 100644 --- a/sources/housekeeping/clock_and_reset.vhd +++ b/sources/housekeeping/clock_and_reset.vhd @@ -52,7 +52,7 @@ library ieee, UNISIM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use ieee.std_logic_1164.all; use work.pcie_package.all; @@ -66,7 +66,7 @@ entity clock_and_reset is MMCM_OscSelect_out : out std_logic; app_clk_in_n : in std_logic; app_clk_in_p : in std_logic; - cdrlocked_in : in std_logic; + --cdrlocked_in : in std_logic; clk10_xtal : out std_logic; clk160 : out std_logic; clk240 : out std_logic; @@ -99,80 +99,64 @@ architecture rtl of clock_and_reset is component clk_wiz_40_0 -port - (-- Clock in ports - clk_40_in : in std_logic; - clk_in2 : in std_logic; - clk_in_sel : in std_logic; - -- Clock out ports - clk40 : out std_logic; - clk80 : out std_logic; - clk160 : out std_logic; - clk320 : out std_logic; - clk240 : out std_logic; - clk250 : out std_logic; - -- Status and control signals - reset : in std_logic; - locked : out std_logic - ); -end component; + port( + clk_in2 : in STD_LOGIC; + clk_in_sel : in STD_LOGIC; + clk40 : out STD_LOGIC; + clk80 : out STD_LOGIC; + clk160 : out STD_LOGIC; + clk320 : out STD_LOGIC; + clk240 : out STD_LOGIC; + clk250 : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_40_in : in STD_LOGIC + ); +end component clk_wiz_40_0; component clk_wiz_250 -port - (-- Clock in ports - clk_in40_1 : in std_logic; - clk_in40_2 : in std_logic; - clk_in_sel : in std_logic; - -- Clock out ports - clk250 : out std_logic; - -- Status and control signals - reset : in std_logic; - locked : out std_logic - ); -end component; + port( + clk_in40_2 : in STD_LOGIC; + clk_in_sel : in STD_LOGIC; + clk250 : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in40_1 : in STD_LOGIC + ); +end component clk_wiz_250; component clk_wiz_100_0 -port - (-- Clock in ports - clk_in1_p : in std_logic; - clk_in1_n : in std_logic; - - -- Clock out ports - clk40 : out std_logic; - clk10 : out std_logic; - -- Status and control signals - reset : in std_logic; - locked : out std_logic - ); -end component; + port( + clk40 : out STD_LOGIC; + clk10 : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); +end component clk_wiz_100_0; component clk_wiz_200_0 -port - (-- Clock in ports - clk_in1_p : in std_logic; - clk_in1_n : in std_logic; - -- Clock out ports - clk40 : out std_logic; - clk10 : out std_logic; - -- Status and control signals - reset : in std_logic; - locked : out std_logic - ); -end component; + port( + clk40 : out STD_LOGIC; + clk10 : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); +end component clk_wiz_200_0; component clk_wiz_156_0 -port - (-- Clock in ports - clk_in1_p : in std_logic; - clk_in1_n : in std_logic; - -- Clock out ports - clk40 : out std_logic; - clk10 : out std_logic; - -- Status and control signals - reset : in std_logic; - locked : out std_logic - ); -end component; + port( + clk40 : out STD_LOGIC; + clk10 : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); +end component clk_wiz_156_0; signal reset_in : std_logic; @@ -184,16 +168,16 @@ end component; signal clk160_out_s : std_logic; signal clk_ttcfx_ref_s : std_logic; - signal ttc_locked : std_logic; - signal ttcCounter : std_logic_vector(7 downto 0); - signal ttcCounterXtal : std_logic_vector(7 downto 0); - signal ttcCounterXtalP1 : std_logic_vector(7 downto 0); - signal xtalCounter : std_logic_vector(7 downto 0); + --signal ttc_locked : std_logic; + --signal ttcCounter : std_logic_vector(7 downto 0); + --signal ttcCounterXtal : std_logic_vector(7 downto 0); + --signal ttcCounterXtalP1 : std_logic_vector(7 downto 0); + --signal xtalCounter : std_logic_vector(7 downto 0); signal OscSelect : std_logic; constant TTC_SRC : std_logic := '1'; constant XTAL_SRC : std_logic := '0'; - signal unused_app_clk : std_logic; + signal unused_app_clk : std_logic; -- @suppress "signal unused_app_clk is never read" attribute dont_touch : string; attribute dont_touch of unused_app_clk : signal is "true"; @@ -204,49 +188,45 @@ begin -- Main MMCM clk0 : clk_wiz_40_0 port map ( - -- Clock in ports - clk_40_in => clk_ttc_40, - clk_in2 => clk_xtal_40_s, - clk_in_sel=> OscSelect, - -- Clock out ports - clk40 => clk40_s, - clk80 => clk80, + clk_in2 => clk_xtal_40_s, + clk_in_sel => OscSelect, + clk40 => clk40_s, + clk80 => clk80, clk160 => clk160_s, clk320 => clk320, - clk240 => clk240, + clk240 => clk240, clk250 => open, - -- Status and control signals reset => reset_in, - locked => locked_s + locked => locked_s, + -- Clock in ports + clk_40_in => clk_ttc_40 ); clk250_0 : clk_wiz_250 port map ( - -- Clock in ports - clk_in40_1 => clk_ttc_40, clk_in40_2 => clk_xtal_40_s, clk_in_sel => OscSelect, - -- Clock out ports clk250 => clk250, - -- Status and control signals reset => reset_in, - locked => open + locked => open, + -- Clock in ports + clk_in40_1 => clk_ttc_40 ); -- FLX-709 Si570 @ 156.25MHz g_156M: if(APP_CLK_FREQ = 156) generate clk0 : clk_wiz_156_0 port map ( - -- Clock in ports - clk_in1_p => app_clk_in_p, - clk_in1_n => app_clk_in_n, -- Clock out ports - clk40 => clk_xtal_40_s, - clk10 => clk10_xtal, + clk40 => clk_xtal_40_s, + clk10 => clk10_xtal, -- Status and control signals reset => '0', - locked => open + locked => open, + -- Clock in ports + clk_in1_p => app_clk_in_p, + clk_in1_n => app_clk_in_n ); end generate; @@ -254,15 +234,15 @@ begin g_200M: if(APP_CLK_FREQ = 200) generate clk0 : clk_wiz_200_0 port map ( - -- Clock in ports - clk_in1_p => app_clk_in_p, - clk_in1_n => app_clk_in_n, -- Clock out ports - clk40 => clk_xtal_40_s, - clk10 => clk10_xtal, + clk40 => clk_xtal_40_s, + clk10 => clk10_xtal, -- Status and control signals reset => '0', - locked => open + locked => open, + -- Clock in ports + clk_in1_p => app_clk_in_p, + clk_in1_n => app_clk_in_n ); end generate; @@ -270,15 +250,15 @@ begin g_100M: if(APP_CLK_FREQ = 100) generate clk0 : clk_wiz_100_0 port map ( - -- Clock in ports - clk_in1_p => app_clk_in_p, - clk_in1_n => app_clk_in_n, -- Clock out ports - clk40 => clk_xtal_40_s, - clk10 => clk10_xtal, + clk40 => clk_xtal_40_s, + clk10 => clk10_xtal, -- Status and control signals reset => '0', - locked => open + locked => open, + -- Clock in ports + clk_in1_p => app_clk_in_p, + clk_in1_n => app_clk_in_n ); end generate; @@ -286,16 +266,16 @@ begin g1b: if(USE_BACKUP_CLK = false and AUTOMATIC_CLOCK_SWITCH = false) generate signal unused_app_clk_temp: std_logic; begin - buf0: IBUFDS + buf0: IBUFDS -- @suppress "Generic map uses default values. Missing optional actuals: CAPACITANCE, DIFF_TERM, DQS_BIAS, IBUF_DELAY_VALUE, IBUF_LOW_PWR, IFD_DELAY_VALUE, IOSTANDARD" port map ( + O => unused_app_clk_temp, I => app_clk_in_p, - Ib => app_clk_in_n, - O => unused_app_clk_temp + Ib => app_clk_in_n ); bufg0: BUFG port map ( - I => unused_app_clk_temp, - O => unused_app_clk + O => unused_app_clk, + I => unused_app_clk_temp ); end generate; @@ -314,28 +294,28 @@ begin signal clk_ttcfx_mon2_temp: std_logic; begin - buf1: IBUFDS + buf1: IBUFDS -- @suppress "Generic map uses default values. Missing optional actuals: CAPACITANCE, DIFF_TERM, DQS_BIAS, IBUF_DELAY_VALUE, IBUF_LOW_PWR, IFD_DELAY_VALUE, IOSTANDARD" port map ( + O => clk_ttcfx_mon1_temp, I => clk_ttcfx_ref1_in_p, - Ib => clk_ttcfx_ref1_in_n, - O => clk_ttcfx_mon1_temp + Ib => clk_ttcfx_ref1_in_n ); bufg1: BUFG port map ( - I => clk_ttcfx_mon1_temp, - O => clk_ttcfx_mon1 + O => clk_ttcfx_mon1, + I => clk_ttcfx_mon1_temp ); - buf2: IBUFDS + buf2: IBUFDS -- @suppress "Generic map uses default values. Missing optional actuals: CAPACITANCE, DIFF_TERM, DQS_BIAS, IBUF_DELAY_VALUE, IBUF_LOW_PWR, IFD_DELAY_VALUE, IOSTANDARD" port map ( + O => clk_ttcfx_mon2_temp, I => clk_ttcfx_ref2_in_p, - Ib => clk_ttcfx_ref2_in_n, - O => clk_ttcfx_mon2_temp + Ib => clk_ttcfx_ref2_in_n ); bufg2: BUFG port map ( - I => clk_ttcfx_mon2_temp, - O => clk_ttcfx_mon2 + O => clk_ttcfx_mon2, + I => clk_ttcfx_mon2_temp ); end block; @@ -352,7 +332,7 @@ begin -- input to the Si5345 from Main MMCM 40 MHz OBUFDS_ttcfx_ref_out : OBUFDS - generic map + generic map -- @suppress "Generic map uses default values. Missing optional actuals: CAPACITANCE, SLEW" ( IOSTANDARD => "DEFAULT") port map ( O => clk_ttcfx_ref_out_p, @@ -362,7 +342,7 @@ begin -- extra input to the Si5345 OBUFDS_ttcfx_ref2_out : OBUFDS - generic map + generic map -- @suppress "Generic map uses default values. Missing optional actuals: CAPACITANCE, SLEW" ( IOSTANDARD => "DEFAULT") port map ( O => clk_ttcfx_ref2_out_p, @@ -375,14 +355,14 @@ begin g2c: if(USE_BACKUP_CLK = false) generate OscSelect <= TTC_SRC; end generate; - g2d: if(USE_BACKUP_CLK = true) generate + g2d: if(USE_BACKUP_CLK) generate OscSelect <= XTAL_SRC; end generate; end generate; -- autoclock switch turned into manual select - g2b: if (AUTOMATIC_CLOCK_SWITCH = true) generate - ttc_locked <= cdrlocked_in; + g2b: if (AUTOMATIC_CLOCK_SWITCH) generate + --ttc_locked <= cdrlocked_in; OscSelect <= XTAL_SRC when register_map_control.MMCM_MAIN.LCLK_SEL = "1" else TTC_SRC; --ttc_locked; end generate; @@ -390,26 +370,25 @@ begin reset_out <= not locked_s; -- 160 Mhz to the Si5324 (FLX-709 only) - g_160_out_bufgmux0: if(AUTOMATIC_CLOCK_SWITCH = true) generate + g_160_out_bufgmux0: if(AUTOMATIC_CLOCK_SWITCH) generate signal CE1, CE0: std_logic; begin CE1 <= OscSelect; CE0 <= not OscSelect; - bufgmux_160_0: BUFGCTRL + bufgmux_160_0: BUFGCTRL -- @suppress "Generic map uses default values. Missing optional actuals: CE_TYPE_CE0, CE_TYPE_CE1, INIT_OUT, IS_CE0_INVERTED, IS_CE1_INVERTED, IS_I0_INVERTED, IS_I1_INVERTED, IS_IGNORE0_INVERTED, IS_IGNORE1_INVERTED, IS_S0_INVERTED, IS_S1_INVERTED, PRESELECT_I0, PRESELECT_I1, SIM_DEVICE, STARTUP_SYNC" port map ( + O => clk160_out_s, -- insert clock output + CE0 => CE0, + CE1 => CE1, + I0 => clk160_s, -- insert clock input used when select (S) is Low + I1 => clk_adn_160, -- insert clock input used when select (S) is High IGNORE0 => '0', IGNORE1 => '0', S0 => '1', - S1 => '1', - I0 => clk160_s, -- insert clock input used when select (S) is Low - I1 => clk_adn_160, -- insert clock input used when select (S) is High - CE0 => CE0, - CE1 => CE1, - O => clk160_out_s -- insert clock output - ); + S1 => '1' ); end generate; - g_160_out_xtal: if(USE_BACKUP_CLK = true and AUTOMATIC_CLOCK_SWITCH = false) generate + g_160_out_xtal: if(USE_BACKUP_CLK and AUTOMATIC_CLOCK_SWITCH = false) generate clk160_out_s <= clk160_s; end generate; @@ -420,12 +399,13 @@ begin --OBUFDS to route the 160 MHz clock into the Si5324 jitter cleaner (VC709) to create the GBT Reference clock OBUF160: OBUFDS generic map ( + CAPACITANCE => "DONT_CARE", IOSTANDARD => "LVDS", SLEW => "FAST") port map( - I => clk160_out_s, O => clk_adn_160_out_p, - OB => clk_adn_160_out_n); + OB => clk_adn_160_out_n, + I => clk160_out_s); end architecture rtl ; -- of clock_and_reset diff --git a/sources/housekeeping/gc_multichannel_frequency_meter.vhd b/sources/housekeeping/gc_multichannel_frequency_meter.vhd index b1a7875b4fab96e64074fa9e5dac956c7b02e647..757622dab55c3dd63b4292159384eca36fbe95f2 100644 --- a/sources/housekeeping/gc_multichannel_frequency_meter.vhd +++ b/sources/housekeeping/gc_multichannel_frequency_meter.vhd @@ -68,7 +68,7 @@ architecture arch of gc_multichannel_frequency_meter is begin - gen_internal_timebase : if(g_WITH_INTERNAL_TIMEBASE = true) generate + gen_internal_timebase : if(g_WITH_INTERNAL_TIMEBASE) generate p_gate_counter : process(clk_sys_i) begin diff --git a/sources/housekeeping/gc_pulse_synchronizer.vhd b/sources/housekeeping/gc_pulse_synchronizer.vhd index ff015e576803aefa635dd8061013bdde3ef34219..1df5f212424f33c27d3f6374d052f98a2c98197d 100644 --- a/sources/housekeeping/gc_pulse_synchronizer.vhd +++ b/sources/housekeeping/gc_pulse_synchronizer.vhd @@ -53,12 +53,13 @@ begin -- rtl -- using the same reset on both domains cmp_gc_pulse_sync : entity work.gc_pulse_synchronizer2 port map ( - clk_in_i => clk_in_i, - rst_in_n_i => rst_n_i, - clk_out_i => clk_out_i, + clk_in_i => clk_in_i, + rst_in_n_i => rst_n_i, + clk_out_i => clk_out_i, rst_out_n_i => rst_n_i, - d_ready_o => d_ready_o, - d_p_i => d_p_i, - q_p_o => q_p_o); + d_ready_o => d_ready_o, + d_ack_p_o => open, + d_p_i => d_p_i, + q_p_o => q_p_o); end rtl; diff --git a/sources/housekeeping/gc_pulse_synchronizer2.vhd b/sources/housekeeping/gc_pulse_synchronizer2.vhd index 67c99542a4785a86feb74641fe3a06e6ff54dfd6..ae5c7365043ae76c0e0f4980cbc80f039d88d775 100644 --- a/sources/housekeeping/gc_pulse_synchronizer2.vhd +++ b/sources/housekeeping/gc_pulse_synchronizer2.vhd @@ -63,6 +63,9 @@ architecture rtl of gc_pulse_synchronizer2 is begin -- rtl cmp_in2out_sync : entity work.gc_sync_ffs + generic map( + g_sync_edge => "positive" + ) port map ( clk_i => clk_out_i, rst_n_i => rst_out_n_i, @@ -72,6 +75,9 @@ begin -- rtl ppulse_o => q_p_o); cmp_out2in_sync : entity work.gc_sync_ffs + generic map( + g_sync_edge => "positive" + ) port map ( clk_i => clk_in_i, rst_n_i => rst_in_n_i, diff --git a/sources/housekeeping/housekeeping_module.vhd b/sources/housekeeping/housekeeping_module.vhd index d4d522cd34237db5971fcb3f31b0e7cd1edd5b52..32204acf24e0163141d3fd3acbcccd776ae45cd5 100644 --- a/sources/housekeeping/housekeeping_module.vhd +++ b/sources/housekeeping/housekeeping_module.vhd @@ -3,7 +3,7 @@ library ieee, UNISIM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use ieee.std_logic_1164.all; use work.pcie_package.all; use work.I2C.all; @@ -24,7 +24,6 @@ entity housekeeping_module is IncludeDecodingEpath4_8b10b : std_logic_vector(6 downto 0) := "1111111"; IncludeDecodingEpath8_8b10b : std_logic_vector(6 downto 0) := "1111111"; IncludeDecodingEpath16_8b10b : std_logic_vector(6 downto 0) := "0000000"; --lpGBT only - IncludeDecodingEpath32_8b10b : std_logic_vector(6 downto 0) := "0000000"; --lpGBT only IncludeEncodingEpath2_HDLC : std_logic_vector(4 downto 0) := "00000"; IncludeEncodingEpath2_8b10b : std_logic_vector(4 downto 0) := "00000"; IncludeEncodingEpath4_8b10b : std_logic_vector(4 downto 0) := "00000"; @@ -61,7 +60,7 @@ entity housekeeping_module is clk40 : in std_logic; --MT added leds : out std_logic_vector(7 downto 0); opto_inhibit : out std_logic_vector(OPTO_TRX-1 downto 0); - opto_los : in std_logic_vector(OPTO_TRX-1 downto 0); + --opto_los : in std_logic_vector(OPTO_TRX-1 downto 0); register_map_control : in register_map_control_type; register_map_gen_board_info : out register_map_gen_board_info_type; register_map_hk_monitor : out register_map_hk_monitor_type; @@ -98,7 +97,7 @@ architecture structure of housekeeping_module is signal nReset : std_logic; signal clk : std_logic; signal cmd_ack : std_logic; - signal ack_out : std_logic; + --signal ack_out : std_logic; signal Dout : std_logic_vector(7 downto 0); signal Din : std_logic_vector(7 downto 0); signal ack_in : std_logic; @@ -138,7 +137,7 @@ begin ack_in => ack_in, Din => Din, cmd_ack => cmd_ack, - ack_out => ack_out, + ack_out => open, --ack_out, Dout => Dout, SCL => SCL, SDA => SDA); @@ -151,7 +150,7 @@ begin I2C_WR => register_map_hk_monitor.I2C_WR, RST => RST, ack_in => ack_in, - ack_out => ack_out, + --ack_out => ack_out, appreg_clk => appreg_clk, clk => clk, cmd_ack => cmd_ack, @@ -166,26 +165,25 @@ begin const0: entity work.GenericConstantsToRegs generic map( - GBT_NUM => GBT_NUM, - OPTO_TRX => OPTO_TRX, - ENDPOINTS => ENDPOINTS, - generateTTCemu => generateTTCemu, - AUTOMATIC_CLOCK_SWITCH => AUTOMATIC_CLOCK_SWITCH, - FIRMWARE_MODE => FIRMWARE_MODE, - USE_Si5324_RefCLK => USE_Si5324_RefCLK, + GBT_NUM => GBT_NUM, + ENDPOINTS => ENDPOINTS, + OPTO_TRX => OPTO_TRX, + generateTTCemu => generateTTCemu, + AUTOMATIC_CLOCK_SWITCH => AUTOMATIC_CLOCK_SWITCH, + FIRMWARE_MODE => FIRMWARE_MODE, + USE_Si5324_RefCLK => USE_Si5324_RefCLK, --CREnableFromHost => CREnableFromHost, --includeDirectMode => includeDirectMode, - GENERATE_XOFF => GENERATE_XOFF, - IncludeDecodingEpath2_HDLC => IncludeDecodingEpath2_HDLC, - IncludeDecodingEpath2_8b10b => IncludeDecodingEpath2_8b10b, - IncludeDecodingEpath4_8b10b => IncludeDecodingEpath4_8b10b, - IncludeDecodingEpath8_8b10b => IncludeDecodingEpath8_8b10b, - IncludeDecodingEpath16_8b10b => IncludeDecodingEpath16_8b10b, - IncludeDecodingEpath32_8b10b => IncludeDecodingEpath32_8b10b, - IncludeEncodingEpath2_HDLC => IncludeEncodingEpath2_HDLC , - IncludeEncodingEpath2_8b10b => IncludeEncodingEpath2_8b10b, - IncludeEncodingEpath4_8b10b => IncludeEncodingEpath4_8b10b, - IncludeEncodingEpath8_8b10b => IncludeEncodingEpath8_8b10b, + GENERATE_XOFF => GENERATE_XOFF, + IncludeDecodingEpath2_HDLC => IncludeDecodingEpath2_HDLC, + IncludeDecodingEpath2_8b10b => IncludeDecodingEpath2_8b10b, + IncludeDecodingEpath4_8b10b => IncludeDecodingEpath4_8b10b, + IncludeDecodingEpath8_8b10b => IncludeDecodingEpath8_8b10b, + IncludeDecodingEpath16_8b10b => IncludeDecodingEpath16_8b10b, + IncludeEncodingEpath2_HDLC => IncludeEncodingEpath2_HDLC, + IncludeEncodingEpath2_8b10b => IncludeEncodingEpath2_8b10b, + IncludeEncodingEpath4_8b10b => IncludeEncodingEpath4_8b10b, + IncludeEncodingEpath8_8b10b => IncludeEncodingEpath8_8b10b, BLOCKSIZE => BLOCKSIZE, CHUNK_TRAILER_32B => CHUNK_TRAILER_32B, SUPER_CHUNK_FACTOR => SUPER_CHUNK_FACTOR) @@ -285,7 +283,7 @@ begin clk40 => clk40_xtal, lnk_up0 => lnk_up(0), lnk_up1 => lnk_up(1), - reset_pcie => open, + --reset_pcie => open, sys_reset_n => sys_reset_n); end generate; diff --git a/sources/housekeeping/i2c_interface.vhd b/sources/housekeeping/i2c_interface.vhd index 2adc42ff3c1d2394368f0a6fcfaaaa8b9c06edab..f3f120bc6b45d1cbdd0a0a9418fa642f4ccd5d52 100644 --- a/sources/housekeeping/i2c_interface.vhd +++ b/sources/housekeeping/i2c_interface.vhd @@ -2,10 +2,10 @@ -library ieee, UNISIM, work; +library ieee, UNISIM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use ieee.std_logic_1164.all; use work.pcie_package.all; @@ -17,7 +17,7 @@ entity i2c_interface is I2C_WR : out bitfield_i2c_wr_r_type; RST : in std_logic; ack_in : out std_logic; - ack_out : in std_logic; + --ack_out : in std_logic; appreg_clk : in std_logic; clk : out std_logic; cmd_ack : in std_logic; @@ -154,7 +154,7 @@ fifo_wr : I2C_WRFifo RnW <= RnW; - twoBytes <= twoBytes; + twobytes <= twobytes; write <= '0'; read <= '0'; @@ -184,12 +184,12 @@ fifo_wr : I2C_WRFifo start_s <= '1'; stop_s <= '0'; RnW <= wrfifo_dout(0); - twoBytes <= wrfifo_dout(24); + twobytes <= wrfifo_dout(24); i2c_wr_state <= ADDRACK; when ADDRACK => if(cmd_ack = '1') then - if(twoBytes = '1') then + if(twobytes = '1') then if(RnW = '1') then --Write one byte, then repeated start, address and read i2c_wr_state <= WRITE1B; --first write one byte, then read else --Write two bytes, then stop @@ -281,7 +281,7 @@ fifo_wr : I2C_WRFifo else i2c_wr_state <= READDATAACK; end if; - when others => + when others => -- @suppress "Case statement contains all choices explicitly. You can safely remove the redundant 'others'" i2c_wr_state <= IDLE; end case; diff --git a/sources/i2c_master/I2C_Master_PEX.vhd b/sources/i2c_master/I2C_Master_PEX.vhd index 8008b0477876d986d7acd331b9b5b5913bf18a56..62e83befbfe6958056597da6af3422a8d0060219 100644 --- a/sources/i2c_master/I2C_Master_PEX.vhd +++ b/sources/i2c_master/I2C_Master_PEX.vhd @@ -2,8 +2,8 @@ LIBRARY ieee; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_ARITH.ALL;-- @suppress "Deprecated package" +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" ENTITY i2c_master_pex IS PORT( @@ -42,7 +42,7 @@ ARCHITECTURE logic OF i2c_master_pex IS SIGNAL adr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL data_tx : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); + --SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; signal sda_o : STD_LOGIC:='0'; @@ -54,7 +54,7 @@ ARCHITECTURE logic OF i2c_master_pex IS signal start_cnt : std_logic:='0'; signal stop_cnt : std_logic:='0'; signal sda_sel : std_logic:='0'; - signal busy : std_logic:='0'; + --signal busy : std_logic:='0'; signal command_cnt : std_logic_vector(1 downto 0):="00"; signal ack_cnt : std_logic_vector(1 downto 0):="00"; signal rd_cnt : std_logic_vector(1 downto 0):="00"; @@ -90,7 +90,7 @@ BEGIN ack_error <= '0'; iread <= 0; iwrite <= 0; - busy <= '0'; + --busy <= '0'; state_display <= "00000"; wr_number <= "0000"; rd_number <="0000"; @@ -104,7 +104,7 @@ BEGIN i2c_process_finished <= '0'; state <= start; state_display <= "00001"; - busy <= '1'; + --busy <= '1'; adr_rw <= addr & '0';--(not wr_mod); --if special='1' then -- adr_rw <= addr & '1'; @@ -292,12 +292,12 @@ BEGIN ack_cnt <= "00"; if addr_cnt =3 then if wr_mod = '0' then - state <= restartP2; + state <= restartp2; elsif no_data = '1' then -- elsif wr_number_in = "0000" then state <= stop; - WR_number <= "0000"; + wr_number <= "0000"; else state <= data_write_buf; wr_data_update <= '1'; @@ -550,7 +550,7 @@ BEGIN stop_cnt <= '0'; if wr_number = "0000" then state <= stop; - WR_number <= "0000"; + wr_number <= "0000"; else wr_number <= wr_number - '1'; state <= data_write_buf; @@ -574,7 +574,7 @@ BEGIN sda_o <= '0'; stop_cnt <= '0'; state <= stop1; - busy <= '0'; + --busy <= '0'; end if; when stop1 => @@ -593,11 +593,11 @@ BEGIN sda_o <= '1'; state <= ready; - when others => + when others => -- @suppress "Case statement contains all choices explicitly. You can safely remove the redundant 'others'" state_display <= "10010"; i2c_process_finished <= '1'; state <= ready; - busy <='0'; + --busy <='0'; end case; end if; end process; diff --git a/sources/i2c_master/i2c.vhd b/sources/i2c_master/i2c.vhd index 685897432d0aeedcad87f03b7539aa0a65bf7a36..9c5078942a05073529f1c6db21408c85c71d0298 100644 --- a/sources/i2c_master/i2c.vhd +++ b/sources/i2c_master/i2c.vhd @@ -12,7 +12,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.std_logic_arith.all;-- @suppress "Deprecated package" package I2C is component simple_i2c is @@ -46,7 +46,7 @@ end package I2C; library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.std_logic_arith.all;-- @suppress "Deprecated package" entity simple_i2c is port ( @@ -104,7 +104,7 @@ architecture structural of simple_i2c is -- signals for i2c_core signal core_cmd : std_logic_vector(2 downto 0); - signal core_ack, core_busy, core_txd, core_rxd : std_logic; + signal core_ack, core_rxd, core_txd : std_logic; -- signals for shift register signal sr : std_logic_vector(7 downto 0); -- 8bit shift register @@ -114,8 +114,18 @@ architecture structural of simple_i2c is signal go, host_ack : std_logic; begin -- hookup i2c core - u1: i2c_core port map (clk, nReset, clk_cnt, core_cmd, core_ack, core_busy, core_txd, core_rxd, SCL, SDA); - + u1: i2c_core port map( + clk => clk, + nReset => nReset, + clk_cnt => clk_cnt, + cmd => core_cmd, + cmd_ack => core_ack, + busy => open, + Din => core_txd, + Dout => core_rxd, + SCL => SCL, + SDA => SDA + ); -- generate host-command-acknowledge cmd_ack <= host_ack; @@ -133,7 +143,7 @@ begin begin if (clk'event and clk = '1') then if (ld = '1') then - sr <= din; + sr <= Din; elsif (shift = '1') then sr <= (sr(6 downto 0) & core_rxd); end if; @@ -256,7 +266,7 @@ begin icore_cmd := CMD_NOP; end if; - when others => -- illegal states + when others => -- illegal states -- @suppress "Case statement contains all choices explicitly. You can safely remove the redundant 'others'" nxt_state := st_idle; icore_cmd := CMD_NOP; end case; @@ -334,7 +344,7 @@ end architecture structural; library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.std_logic_arith.all;-- @suppress "Deprecated package" entity i2c_core is port ( @@ -356,7 +366,7 @@ entity i2c_core is end entity i2c_core; architecture structural of i2c_core is - constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; + --constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; constant CMD_START : std_logic_vector(2 downto 0) := "010"; constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; constant CMD_READ : std_logic_vector(2 downto 0) := "100"; @@ -393,7 +403,7 @@ begin end process gen_clken; -- generate statemachine - nxt_state_decoder : process (clk, nReset, state, cmd, SDA, txd, Din) + nxt_state_decoder : process (clk, nReset, state, cmd, txd, Din) variable nxt_state : cmds; variable icmd_ack, ibusy, store_sda : std_logic; variable itxd : std_logic; diff --git a/sources/ip_cores/VU37P/gtwizard_fullmode_txcpll_rxqpll_v7_stub.vhdl b/sources/ip_cores/VU37P/gtwizard_fullmode_txcpll_rxqpll_v7_stub.vhdl index f778215be5c31d2df63cee2ba5eff186c412fd6f..14d9d6dc3a27556726915bccbd08d34cf0b5916b 100644 --- a/sources/ip_cores/VU37P/gtwizard_fullmode_txcpll_rxqpll_v7_stub.vhdl +++ b/sources/ip_cores/VU37P/gtwizard_fullmode_txcpll_rxqpll_v7_stub.vhdl @@ -14,219 +14,219 @@ use IEEE.STD_LOGIC_1164.ALL; entity gtwizard_fullmode_txcpll_rxqpll_v7 is Port ( - SYSCLK_IN : in STD_LOGIC; - SOFT_RESET_TX_IN : in STD_LOGIC; - SOFT_RESET_RX_IN : in STD_LOGIC; - DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC; - GT0_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; - GT0_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; - GT0_DATA_VALID_IN : in STD_LOGIC; - GT1_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; - GT1_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; - GT1_DATA_VALID_IN : in STD_LOGIC; - GT2_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; - GT2_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; - GT2_DATA_VALID_IN : in STD_LOGIC; - GT3_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; - GT3_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; - GT3_DATA_VALID_IN : in STD_LOGIC; - gt0_cpllfbclklost_out : out STD_LOGIC; - gt0_cplllock_out : out STD_LOGIC; - gt0_cplllockdetclk_in : in STD_LOGIC; - gt0_cpllreset_in : in STD_LOGIC; - gt0_gtrefclk0_in : in STD_LOGIC; - gt0_gtrefclk1_in : in STD_LOGIC; - gt0_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); - gt0_drpclk_in : in STD_LOGIC; - gt0_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); - gt0_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); - gt0_drpen_in : in STD_LOGIC; - gt0_drprdy_out : out STD_LOGIC; - gt0_drpwe_in : in STD_LOGIC; - gt0_eyescanreset_in : in STD_LOGIC; - gt0_rxuserrdy_in : in STD_LOGIC; - gt0_eyescandataerror_out : out STD_LOGIC; - gt0_eyescantrigger_in : in STD_LOGIC; - gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 ); - gt0_rxusrclk_in : in STD_LOGIC; - gt0_rxusrclk2_in : in STD_LOGIC; - gt0_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); - gt0_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); - gt0_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); - gt0_gthrxn_in : in STD_LOGIC; - gt0_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); - gt0_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); - gt0_rxbyteisaligned_out : out STD_LOGIC; - gt0_rxmcommaalignen_in : in STD_LOGIC; - gt0_rxpcommaalignen_in : in STD_LOGIC; - gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 ); - gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); - gt0_rxoutclk_out : out STD_LOGIC; - gt0_rxoutclkfabric_out : out STD_LOGIC; - gt0_gtrxreset_in : in STD_LOGIC; - gt0_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); - gt0_gthrxp_in : in STD_LOGIC; - gt0_rxresetdone_out : out STD_LOGIC; - gt0_gttxreset_in : in STD_LOGIC; - gt0_txuserrdy_in : in STD_LOGIC; - gt0_txusrclk_in : in STD_LOGIC; - gt0_txusrclk2_in : in STD_LOGIC; - gt0_txdata_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); - gt0_gthtxn_out : out STD_LOGIC; - gt0_gthtxp_out : out STD_LOGIC; - gt0_txoutclk_out : out STD_LOGIC; - gt0_txoutclkfabric_out : out STD_LOGIC; - gt0_txoutclkpcs_out : out STD_LOGIC; - gt0_txresetdone_out : out STD_LOGIC; - gt1_cpllfbclklost_out : out STD_LOGIC; - gt1_cplllock_out : out STD_LOGIC; - gt1_cplllockdetclk_in : in STD_LOGIC; - gt1_cpllreset_in : in STD_LOGIC; - gt1_gtrefclk0_in : in STD_LOGIC; - gt1_gtrefclk1_in : in STD_LOGIC; - gt1_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); - gt1_drpclk_in : in STD_LOGIC; - gt1_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); - gt1_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); - gt1_drpen_in : in STD_LOGIC; - gt1_drprdy_out : out STD_LOGIC; - gt1_drpwe_in : in STD_LOGIC; - gt1_eyescanreset_in : in STD_LOGIC; - gt1_rxuserrdy_in : in STD_LOGIC; - gt1_eyescandataerror_out : out STD_LOGIC; - gt1_eyescantrigger_in : in STD_LOGIC; - gt1_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 ); - gt1_rxusrclk_in : in STD_LOGIC; - gt1_rxusrclk2_in : in STD_LOGIC; - gt1_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); - gt1_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); - gt1_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); - gt1_gthrxn_in : in STD_LOGIC; - gt1_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); - gt1_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); - gt1_rxbyteisaligned_out : out STD_LOGIC; - gt1_rxmcommaalignen_in : in STD_LOGIC; - gt1_rxpcommaalignen_in : in STD_LOGIC; - gt1_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 ); - gt1_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); - gt1_rxoutclk_out : out STD_LOGIC; - gt1_rxoutclkfabric_out : out STD_LOGIC; - gt1_gtrxreset_in : in STD_LOGIC; - gt1_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); - gt1_gthrxp_in : in STD_LOGIC; - gt1_rxresetdone_out : out STD_LOGIC; - gt1_gttxreset_in : in STD_LOGIC; - gt1_txuserrdy_in : in STD_LOGIC; - gt1_txusrclk_in : in STD_LOGIC; - gt1_txusrclk2_in : in STD_LOGIC; - gt1_txdata_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); - gt1_gthtxn_out : out STD_LOGIC; - gt1_gthtxp_out : out STD_LOGIC; - gt1_txoutclk_out : out STD_LOGIC; - gt1_txoutclkfabric_out : out STD_LOGIC; - gt1_txoutclkpcs_out : out STD_LOGIC; - gt1_txresetdone_out : out STD_LOGIC; - gt2_cpllfbclklost_out : out STD_LOGIC; - gt2_cplllock_out : out STD_LOGIC; - gt2_cplllockdetclk_in : in STD_LOGIC; - gt2_cpllreset_in : in STD_LOGIC; - gt2_gtrefclk0_in : in STD_LOGIC; - gt2_gtrefclk1_in : in STD_LOGIC; - gt2_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); - gt2_drpclk_in : in STD_LOGIC; - gt2_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); - gt2_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); - gt2_drpen_in : in STD_LOGIC; - gt2_drprdy_out : out STD_LOGIC; - gt2_drpwe_in : in STD_LOGIC; - gt2_eyescanreset_in : in STD_LOGIC; - gt2_rxuserrdy_in : in STD_LOGIC; - gt2_eyescandataerror_out : out STD_LOGIC; - gt2_eyescantrigger_in : in STD_LOGIC; - gt2_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 ); - gt2_rxusrclk_in : in STD_LOGIC; - gt2_rxusrclk2_in : in STD_LOGIC; - gt2_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); - gt2_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); - gt2_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); - gt2_gthrxn_in : in STD_LOGIC; - gt2_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); - gt2_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); - gt2_rxbyteisaligned_out : out STD_LOGIC; - gt2_rxmcommaalignen_in : in STD_LOGIC; - gt2_rxpcommaalignen_in : in STD_LOGIC; - gt2_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 ); - gt2_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); - gt2_rxoutclk_out : out STD_LOGIC; - gt2_rxoutclkfabric_out : out STD_LOGIC; - gt2_gtrxreset_in : in STD_LOGIC; - gt2_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); - gt2_gthrxp_in : in STD_LOGIC; - gt2_rxresetdone_out : out STD_LOGIC; - gt2_gttxreset_in : in STD_LOGIC; - gt2_txuserrdy_in : in STD_LOGIC; - gt2_txusrclk_in : in STD_LOGIC; - gt2_txusrclk2_in : in STD_LOGIC; - gt2_txdata_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); - gt2_gthtxn_out : out STD_LOGIC; - gt2_gthtxp_out : out STD_LOGIC; - gt2_txoutclk_out : out STD_LOGIC; - gt2_txoutclkfabric_out : out STD_LOGIC; - gt2_txoutclkpcs_out : out STD_LOGIC; - gt2_txresetdone_out : out STD_LOGIC; - gt3_cpllfbclklost_out : out STD_LOGIC; - gt3_cplllock_out : out STD_LOGIC; - gt3_cplllockdetclk_in : in STD_LOGIC; - gt3_cpllreset_in : in STD_LOGIC; - gt3_gtrefclk0_in : in STD_LOGIC; - gt3_gtrefclk1_in : in STD_LOGIC; - gt3_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); - gt3_drpclk_in : in STD_LOGIC; - gt3_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); - gt3_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); - gt3_drpen_in : in STD_LOGIC; - gt3_drprdy_out : out STD_LOGIC; - gt3_drpwe_in : in STD_LOGIC; - gt3_eyescanreset_in : in STD_LOGIC; - gt3_rxuserrdy_in : in STD_LOGIC; - gt3_eyescandataerror_out : out STD_LOGIC; - gt3_eyescantrigger_in : in STD_LOGIC; - gt3_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 ); - gt3_rxusrclk_in : in STD_LOGIC; - gt3_rxusrclk2_in : in STD_LOGIC; - gt3_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); - gt3_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); - gt3_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); - gt3_gthrxn_in : in STD_LOGIC; - gt3_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); - gt3_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); - gt3_rxbyteisaligned_out : out STD_LOGIC; - gt3_rxmcommaalignen_in : in STD_LOGIC; - gt3_rxpcommaalignen_in : in STD_LOGIC; - gt3_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 ); - gt3_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); - gt3_rxoutclk_out : out STD_LOGIC; - gt3_rxoutclkfabric_out : out STD_LOGIC; - gt3_gtrxreset_in : in STD_LOGIC; - gt3_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); - gt3_gthrxp_in : in STD_LOGIC; - gt3_rxresetdone_out : out STD_LOGIC; - gt3_gttxreset_in : in STD_LOGIC; - gt3_txuserrdy_in : in STD_LOGIC; - gt3_txusrclk_in : in STD_LOGIC; - gt3_txusrclk2_in : in STD_LOGIC; - gt3_txdata_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); - gt3_gthtxn_out : out STD_LOGIC; - gt3_gthtxp_out : out STD_LOGIC; - gt3_txoutclk_out : out STD_LOGIC; - gt3_txoutclkfabric_out : out STD_LOGIC; - gt3_txoutclkpcs_out : out STD_LOGIC; - gt3_txresetdone_out : out STD_LOGIC; - GT0_QPLLLOCK_IN : in STD_LOGIC; - GT0_QPLLREFCLKLOST_IN : in STD_LOGIC; - GT0_QPLLRESET_OUT : out STD_LOGIC; - GT0_QPLLOUTCLK_IN : in STD_LOGIC; - GT0_QPLLOUTREFCLK_IN : in STD_LOGIC + SYSCLK_IN : in STD_LOGIC; --@suppress + SOFT_RESET_TX_IN : in STD_LOGIC; --@suppress + SOFT_RESET_RX_IN : in STD_LOGIC; --@suppress + DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC; --@suppress + GT0_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT0_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT0_DATA_VALID_IN : in STD_LOGIC; --@suppress + GT1_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT1_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT1_DATA_VALID_IN : in STD_LOGIC; --@suppress + GT2_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT2_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT2_DATA_VALID_IN : in STD_LOGIC; --@suppress + GT3_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT3_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT3_DATA_VALID_IN : in STD_LOGIC; --@suppress + gt0_cpllfbclklost_out : out STD_LOGIC; --@suppress + gt0_cplllock_out : out STD_LOGIC; --@suppress + gt0_cplllockdetclk_in : in STD_LOGIC; --@suppress + gt0_cpllreset_in : in STD_LOGIC; --@suppress + gt0_gtrefclk0_in : in STD_LOGIC; --@suppress + gt0_gtrefclk1_in : in STD_LOGIC; --@suppress + gt0_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); --@suppress + gt0_drpclk_in : in STD_LOGIC; --@suppress + gt0_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt0_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt0_drpen_in : in STD_LOGIC; --@suppress + gt0_drprdy_out : out STD_LOGIC; --@suppress + gt0_drpwe_in : in STD_LOGIC; --@suppress + gt0_eyescanreset_in : in STD_LOGIC; --@suppress + gt0_rxuserrdy_in : in STD_LOGIC; --@suppress + gt0_eyescandataerror_out : out STD_LOGIC; --@suppress + gt0_eyescantrigger_in : in STD_LOGIC; --@suppress + gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 ); --@suppress + gt0_rxusrclk_in : in STD_LOGIC; --@suppress + gt0_rxusrclk2_in : in STD_LOGIC; --@suppress + gt0_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + gt0_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gt0_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gt0_gthrxn_in : in STD_LOGIC; --@suppress + gt0_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); --@suppress + gt0_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); --@suppress + gt0_rxbyteisaligned_out : out STD_LOGIC; --@suppress + gt0_rxmcommaalignen_in : in STD_LOGIC; --@suppress + gt0_rxpcommaalignen_in : in STD_LOGIC; --@suppress + gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 ); --@suppress + gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + gt0_rxoutclk_out : out STD_LOGIC; --@suppress + gt0_rxoutclkfabric_out : out STD_LOGIC; --@suppress + gt0_gtrxreset_in : in STD_LOGIC; --@suppress + gt0_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gt0_gthrxp_in : in STD_LOGIC; --@suppress + gt0_rxresetdone_out : out STD_LOGIC; --@suppress + gt0_gttxreset_in : in STD_LOGIC; --@suppress + gt0_txuserrdy_in : in STD_LOGIC; --@suppress + gt0_txusrclk_in : in STD_LOGIC; --@suppress + gt0_txusrclk2_in : in STD_LOGIC; --@suppress + gt0_txdata_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + gt0_gthtxn_out : out STD_LOGIC; --@suppress + gt0_gthtxp_out : out STD_LOGIC; --@suppress + gt0_txoutclk_out : out STD_LOGIC; --@suppress + gt0_txoutclkfabric_out : out STD_LOGIC; --@suppress + gt0_txoutclkpcs_out : out STD_LOGIC; --@suppress + gt0_txresetdone_out : out STD_LOGIC; --@suppress + gt1_cpllfbclklost_out : out STD_LOGIC; --@suppress + gt1_cplllock_out : out STD_LOGIC; --@suppress + gt1_cplllockdetclk_in : in STD_LOGIC; --@suppress + gt1_cpllreset_in : in STD_LOGIC; --@suppress + gt1_gtrefclk0_in : in STD_LOGIC; --@suppress + gt1_gtrefclk1_in : in STD_LOGIC; --@suppress + gt1_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); --@suppress + gt1_drpclk_in : in STD_LOGIC; --@suppress + gt1_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt1_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt1_drpen_in : in STD_LOGIC; --@suppress + gt1_drprdy_out : out STD_LOGIC; --@suppress + gt1_drpwe_in : in STD_LOGIC; --@suppress + gt1_eyescanreset_in : in STD_LOGIC; --@suppress + gt1_rxuserrdy_in : in STD_LOGIC; --@suppress + gt1_eyescandataerror_out : out STD_LOGIC; --@suppress + gt1_eyescantrigger_in : in STD_LOGIC; --@suppress + gt1_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 ); --@suppress + gt1_rxusrclk_in : in STD_LOGIC; --@suppress + gt1_rxusrclk2_in : in STD_LOGIC; --@suppress + gt1_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + gt1_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gt1_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gt1_gthrxn_in : in STD_LOGIC; --@suppress + gt1_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); --@suppress + gt1_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); --@suppress + gt1_rxbyteisaligned_out : out STD_LOGIC; --@suppress + gt1_rxmcommaalignen_in : in STD_LOGIC; --@suppress + gt1_rxpcommaalignen_in : in STD_LOGIC; --@suppress + gt1_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 ); --@suppress + gt1_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + gt1_rxoutclk_out : out STD_LOGIC; --@suppress + gt1_rxoutclkfabric_out : out STD_LOGIC; --@suppress + gt1_gtrxreset_in : in STD_LOGIC; --@suppress + gt1_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gt1_gthrxp_in : in STD_LOGIC; --@suppress + gt1_rxresetdone_out : out STD_LOGIC; --@suppress + gt1_gttxreset_in : in STD_LOGIC; --@suppress + gt1_txuserrdy_in : in STD_LOGIC; --@suppress + gt1_txusrclk_in : in STD_LOGIC; --@suppress + gt1_txusrclk2_in : in STD_LOGIC; --@suppress + gt1_txdata_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + gt1_gthtxn_out : out STD_LOGIC; --@suppress + gt1_gthtxp_out : out STD_LOGIC; --@suppress + gt1_txoutclk_out : out STD_LOGIC; --@suppress + gt1_txoutclkfabric_out : out STD_LOGIC; --@suppress + gt1_txoutclkpcs_out : out STD_LOGIC; --@suppress + gt1_txresetdone_out : out STD_LOGIC; --@suppress + gt2_cpllfbclklost_out : out STD_LOGIC; --@suppress + gt2_cplllock_out : out STD_LOGIC; --@suppress + gt2_cplllockdetclk_in : in STD_LOGIC; --@suppress + gt2_cpllreset_in : in STD_LOGIC; --@suppress + gt2_gtrefclk0_in : in STD_LOGIC; --@suppress + gt2_gtrefclk1_in : in STD_LOGIC; --@suppress + gt2_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); --@suppress + gt2_drpclk_in : in STD_LOGIC; --@suppress + gt2_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt2_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt2_drpen_in : in STD_LOGIC; --@suppress + gt2_drprdy_out : out STD_LOGIC; --@suppress + gt2_drpwe_in : in STD_LOGIC; --@suppress + gt2_eyescanreset_in : in STD_LOGIC; --@suppress + gt2_rxuserrdy_in : in STD_LOGIC; --@suppress + gt2_eyescandataerror_out : out STD_LOGIC; --@suppress + gt2_eyescantrigger_in : in STD_LOGIC; --@suppress + gt2_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 ); --@suppress + gt2_rxusrclk_in : in STD_LOGIC; --@suppress + gt2_rxusrclk2_in : in STD_LOGIC; --@suppress + gt2_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + gt2_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gt2_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gt2_gthrxn_in : in STD_LOGIC; --@suppress + gt2_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); --@suppress + gt2_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); --@suppress + gt2_rxbyteisaligned_out : out STD_LOGIC; --@suppress + gt2_rxmcommaalignen_in : in STD_LOGIC; --@suppress + gt2_rxpcommaalignen_in : in STD_LOGIC; --@suppress + gt2_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 ); --@suppress + gt2_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + gt2_rxoutclk_out : out STD_LOGIC; --@suppress + gt2_rxoutclkfabric_out : out STD_LOGIC; --@suppress + gt2_gtrxreset_in : in STD_LOGIC; --@suppress + gt2_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gt2_gthrxp_in : in STD_LOGIC; --@suppress + gt2_rxresetdone_out : out STD_LOGIC; --@suppress + gt2_gttxreset_in : in STD_LOGIC; --@suppress + gt2_txuserrdy_in : in STD_LOGIC; --@suppress + gt2_txusrclk_in : in STD_LOGIC; --@suppress + gt2_txusrclk2_in : in STD_LOGIC; --@suppress + gt2_txdata_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + gt2_gthtxn_out : out STD_LOGIC; --@suppress + gt2_gthtxp_out : out STD_LOGIC; --@suppress + gt2_txoutclk_out : out STD_LOGIC; --@suppress + gt2_txoutclkfabric_out : out STD_LOGIC; --@suppress + gt2_txoutclkpcs_out : out STD_LOGIC; --@suppress + gt2_txresetdone_out : out STD_LOGIC; --@suppress + gt3_cpllfbclklost_out : out STD_LOGIC; --@suppress + gt3_cplllock_out : out STD_LOGIC; --@suppress + gt3_cplllockdetclk_in : in STD_LOGIC; --@suppress + gt3_cpllreset_in : in STD_LOGIC; --@suppress + gt3_gtrefclk0_in : in STD_LOGIC; --@suppress + gt3_gtrefclk1_in : in STD_LOGIC; --@suppress + gt3_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); --@suppress + gt3_drpclk_in : in STD_LOGIC; --@suppress + gt3_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt3_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt3_drpen_in : in STD_LOGIC; --@suppress + gt3_drprdy_out : out STD_LOGIC; --@suppress + gt3_drpwe_in : in STD_LOGIC; --@suppress + gt3_eyescanreset_in : in STD_LOGIC; --@suppress + gt3_rxuserrdy_in : in STD_LOGIC; --@suppress + gt3_eyescandataerror_out : out STD_LOGIC; --@suppress + gt3_eyescantrigger_in : in STD_LOGIC; --@suppress + gt3_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 ); --@suppress + gt3_rxusrclk_in : in STD_LOGIC; --@suppress + gt3_rxusrclk2_in : in STD_LOGIC; --@suppress + gt3_rxdata_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + gt3_rxdisperr_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gt3_rxnotintable_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gt3_gthrxn_in : in STD_LOGIC; --@suppress + gt3_rxphmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); --@suppress + gt3_rxphslipmonitor_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); --@suppress + gt3_rxbyteisaligned_out : out STD_LOGIC; --@suppress + gt3_rxmcommaalignen_in : in STD_LOGIC; --@suppress + gt3_rxpcommaalignen_in : in STD_LOGIC; --@suppress + gt3_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 ); --@suppress + gt3_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + gt3_rxoutclk_out : out STD_LOGIC; --@suppress + gt3_rxoutclkfabric_out : out STD_LOGIC; --@suppress + gt3_gtrxreset_in : in STD_LOGIC; --@suppress + gt3_rxcharisk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gt3_gthrxp_in : in STD_LOGIC; --@suppress + gt3_rxresetdone_out : out STD_LOGIC; --@suppress + gt3_gttxreset_in : in STD_LOGIC; --@suppress + gt3_txuserrdy_in : in STD_LOGIC; --@suppress + gt3_txusrclk_in : in STD_LOGIC; --@suppress + gt3_txusrclk2_in : in STD_LOGIC; --@suppress + gt3_txdata_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + gt3_gthtxn_out : out STD_LOGIC; --@suppress + gt3_gthtxp_out : out STD_LOGIC; --@suppress + gt3_txoutclk_out : out STD_LOGIC; --@suppress + gt3_txoutclkfabric_out : out STD_LOGIC; --@suppress + gt3_txoutclkpcs_out : out STD_LOGIC; --@suppress + gt3_txresetdone_out : out STD_LOGIC; --@suppress + GT0_QPLLLOCK_IN : in STD_LOGIC; --@suppress + GT0_QPLLREFCLKLOST_IN : in STD_LOGIC; --@suppress + GT0_QPLLRESET_OUT : out STD_LOGIC; --@suppress + GT0_QPLLOUTCLK_IN : in STD_LOGIC; --@suppress + GT0_QPLLOUTREFCLK_IN : in STD_LOGIC --@suppress ); end gtwizard_fullmode_txcpll_rxqpll_v7; diff --git a/sources/ip_cores/kintexUltrascale/pcie_x8_gen3_3_0_stub.vhdl b/sources/ip_cores/kintexUltrascale/pcie_x8_gen3_3_0_stub.vhdl index 915cfaa9ae9c00e6ba94cdcdd9aa086457bc15de..56e75f8324a6f654bc0c4a517d154e62cf4588af 100644 --- a/sources/ip_cores/kintexUltrascale/pcie_x8_gen3_3_0_stub.vhdl +++ b/sources/ip_cores/kintexUltrascale/pcie_x8_gen3_3_0_stub.vhdl @@ -14,151 +14,151 @@ use IEEE.STD_LOGIC_1164.ALL; entity pcie_x8_gen3_3_0 is Port ( - pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); - pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); - pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); - pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); - pipe_pclk_in : in STD_LOGIC; - pipe_rxusrclk_in : in STD_LOGIC; - pipe_rxoutclk_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); - pipe_dclk_in : in STD_LOGIC; - pipe_userclk1_in : in STD_LOGIC; - pipe_userclk2_in : in STD_LOGIC; - pipe_oobclk_in : in STD_LOGIC; - pipe_mmcm_lock_in : in STD_LOGIC; - pipe_txoutclk_out : out STD_LOGIC; - pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); - pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); - pipe_gen3_out : out STD_LOGIC; - pipe_mmcm_rst_n : in STD_LOGIC; - user_clk : out STD_LOGIC; - user_reset : out STD_LOGIC; - user_lnk_up : out STD_LOGIC; - user_app_rdy : out STD_LOGIC; - s_axis_rq_tlast : in STD_LOGIC; - s_axis_rq_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); - s_axis_rq_tuser : in STD_LOGIC_VECTOR ( 59 downto 0 ); - s_axis_rq_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axis_rq_tready : out STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axis_rq_tvalid : in STD_LOGIC; - m_axis_rc_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 ); - m_axis_rc_tuser : out STD_LOGIC_VECTOR ( 74 downto 0 ); - m_axis_rc_tlast : out STD_LOGIC; - m_axis_rc_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 ); - m_axis_rc_tvalid : out STD_LOGIC; - m_axis_rc_tready : in STD_LOGIC; - m_axis_cq_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 ); - m_axis_cq_tuser : out STD_LOGIC_VECTOR ( 84 downto 0 ); - m_axis_cq_tlast : out STD_LOGIC; - m_axis_cq_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 ); - m_axis_cq_tvalid : out STD_LOGIC; - m_axis_cq_tready : in STD_LOGIC; - s_axis_cc_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); - s_axis_cc_tuser : in STD_LOGIC_VECTOR ( 32 downto 0 ); - s_axis_cc_tlast : in STD_LOGIC; - s_axis_cc_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 ); - s_axis_cc_tvalid : in STD_LOGIC; - s_axis_cc_tready : out STD_LOGIC_VECTOR ( 3 downto 0 ); - pcie_rq_seq_num : out STD_LOGIC_VECTOR ( 3 downto 0 ); - pcie_rq_seq_num_vld : out STD_LOGIC; - pcie_rq_tag : out STD_LOGIC_VECTOR ( 5 downto 0 ); - pcie_rq_tag_vld : out STD_LOGIC; - pcie_tfc_nph_av : out STD_LOGIC_VECTOR ( 1 downto 0 ); - pcie_tfc_npd_av : out STD_LOGIC_VECTOR ( 1 downto 0 ); - pcie_cq_np_req : in STD_LOGIC; - pcie_cq_np_req_count : out STD_LOGIC_VECTOR ( 5 downto 0 ); - cfg_phy_link_down : out STD_LOGIC; - cfg_phy_link_status : out STD_LOGIC_VECTOR ( 1 downto 0 ); - cfg_negotiated_width : out STD_LOGIC_VECTOR ( 3 downto 0 ); - cfg_current_speed : out STD_LOGIC_VECTOR ( 2 downto 0 ); - cfg_max_payload : out STD_LOGIC_VECTOR ( 2 downto 0 ); - cfg_max_read_req : out STD_LOGIC_VECTOR ( 2 downto 0 ); - cfg_function_status : out STD_LOGIC_VECTOR ( 7 downto 0 ); - cfg_function_power_state : out STD_LOGIC_VECTOR ( 5 downto 0 ); - cfg_vf_status : out STD_LOGIC_VECTOR ( 11 downto 0 ); - cfg_vf_power_state : out STD_LOGIC_VECTOR ( 17 downto 0 ); - cfg_link_power_state : out STD_LOGIC_VECTOR ( 1 downto 0 ); - cfg_mgmt_addr : in STD_LOGIC_VECTOR ( 18 downto 0 ); - cfg_mgmt_write : in STD_LOGIC; - cfg_mgmt_write_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); - cfg_mgmt_byte_enable : in STD_LOGIC_VECTOR ( 3 downto 0 ); - cfg_mgmt_read : in STD_LOGIC; - cfg_mgmt_read_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); - cfg_mgmt_read_write_done : out STD_LOGIC; - cfg_mgmt_type1_cfg_reg_access : in STD_LOGIC; - cfg_err_cor_out : out STD_LOGIC; - cfg_err_nonfatal_out : out STD_LOGIC; - cfg_err_fatal_out : out STD_LOGIC; - cfg_ltr_enable : out STD_LOGIC; - cfg_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 ); - cfg_rcb_status : out STD_LOGIC_VECTOR ( 1 downto 0 ); - cfg_dpa_substate_change : out STD_LOGIC_VECTOR ( 1 downto 0 ); - cfg_obff_enable : out STD_LOGIC_VECTOR ( 1 downto 0 ); - cfg_pl_status_change : out STD_LOGIC; - cfg_tph_requester_enable : out STD_LOGIC_VECTOR ( 1 downto 0 ); - cfg_tph_st_mode : out STD_LOGIC_VECTOR ( 5 downto 0 ); - cfg_vf_tph_requester_enable : out STD_LOGIC_VECTOR ( 5 downto 0 ); - cfg_vf_tph_st_mode : out STD_LOGIC_VECTOR ( 17 downto 0 ); - cfg_msg_received : out STD_LOGIC; - cfg_msg_received_data : out STD_LOGIC_VECTOR ( 7 downto 0 ); - cfg_msg_received_type : out STD_LOGIC_VECTOR ( 4 downto 0 ); - cfg_msg_transmit : in STD_LOGIC; - cfg_msg_transmit_type : in STD_LOGIC_VECTOR ( 2 downto 0 ); - cfg_msg_transmit_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); - cfg_msg_transmit_done : out STD_LOGIC; - cfg_fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 ); - cfg_fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 ); - cfg_fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 ); - cfg_fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 ); - cfg_fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 ); - cfg_fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 ); - cfg_fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 ); - cfg_per_func_status_control : in STD_LOGIC_VECTOR ( 2 downto 0 ); - cfg_per_func_status_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); - cfg_per_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); - cfg_per_function_output_request : in STD_LOGIC; - cfg_per_function_update_done : out STD_LOGIC; - cfg_subsys_vend_id : in STD_LOGIC_VECTOR ( 15 downto 0 ); - cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); - cfg_power_state_change_ack : in STD_LOGIC; - cfg_power_state_change_interrupt : out STD_LOGIC; - cfg_err_cor_in : in STD_LOGIC; - cfg_err_uncor_in : in STD_LOGIC; - cfg_flr_in_process : out STD_LOGIC_VECTOR ( 1 downto 0 ); - cfg_flr_done : in STD_LOGIC_VECTOR ( 1 downto 0 ); - cfg_vf_flr_in_process : out STD_LOGIC_VECTOR ( 5 downto 0 ); - cfg_vf_flr_done : in STD_LOGIC_VECTOR ( 5 downto 0 ); - cfg_link_training_enable : in STD_LOGIC; - cfg_ext_read_received : out STD_LOGIC; - cfg_ext_write_received : out STD_LOGIC; - cfg_ext_register_number : out STD_LOGIC_VECTOR ( 9 downto 0 ); - cfg_ext_function_number : out STD_LOGIC_VECTOR ( 7 downto 0 ); - cfg_ext_write_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); - cfg_ext_write_byte_enable : out STD_LOGIC_VECTOR ( 3 downto 0 ); - cfg_ext_read_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); - cfg_ext_read_data_valid : in STD_LOGIC; - cfg_interrupt_int : in STD_LOGIC_VECTOR ( 3 downto 0 ); - cfg_interrupt_pending : in STD_LOGIC_VECTOR ( 1 downto 0 ); - cfg_interrupt_sent : out STD_LOGIC; - cfg_interrupt_msix_enable : out STD_LOGIC_VECTOR ( 1 downto 0 ); - cfg_interrupt_msix_mask : out STD_LOGIC_VECTOR ( 1 downto 0 ); - cfg_interrupt_msix_vf_enable : out STD_LOGIC_VECTOR ( 5 downto 0 ); - cfg_interrupt_msix_vf_mask : out STD_LOGIC_VECTOR ( 5 downto 0 ); - cfg_interrupt_msix_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); - cfg_interrupt_msix_address : in STD_LOGIC_VECTOR ( 63 downto 0 ); - cfg_interrupt_msix_int : in STD_LOGIC; - cfg_interrupt_msix_sent : out STD_LOGIC; - cfg_interrupt_msix_fail : out STD_LOGIC; - cfg_hot_reset_out : out STD_LOGIC; - cfg_config_space_enable : in STD_LOGIC; - cfg_req_pm_transition_l23_ready : in STD_LOGIC; - cfg_hot_reset_in : in STD_LOGIC; - cfg_ds_port_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); - cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); - cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); - cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); - sys_clk : in STD_LOGIC; - sys_reset : in STD_LOGIC + pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + pipe_pclk_in : in STD_LOGIC; --@suppress + pipe_rxusrclk_in : in STD_LOGIC; --@suppress + pipe_rxoutclk_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + pipe_dclk_in : in STD_LOGIC; --@suppress + pipe_userclk1_in : in STD_LOGIC; --@suppress + pipe_userclk2_in : in STD_LOGIC; --@suppress + pipe_oobclk_in : in STD_LOGIC; --@suppress + pipe_mmcm_lock_in : in STD_LOGIC; --@suppress + pipe_txoutclk_out : out STD_LOGIC; --@suppress + pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + pipe_gen3_out : out STD_LOGIC; --@suppress + pipe_mmcm_rst_n : in STD_LOGIC; --@suppress + user_clk : out STD_LOGIC; --@suppress + user_reset : out STD_LOGIC; --@suppress + user_lnk_up : out STD_LOGIC; --@suppress + user_app_rdy : out STD_LOGIC; --@suppress + s_axis_rq_tlast : in STD_LOGIC; --@suppress + s_axis_rq_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); --@suppress + s_axis_rq_tuser : in STD_LOGIC_VECTOR ( 59 downto 0 ); --@suppress + s_axis_rq_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + s_axis_rq_tready : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + s_axis_rq_tvalid : in STD_LOGIC; --@suppress + m_axis_rc_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 ); --@suppress + m_axis_rc_tuser : out STD_LOGIC_VECTOR ( 74 downto 0 ); --@suppress + m_axis_rc_tlast : out STD_LOGIC; --@suppress + m_axis_rc_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + m_axis_rc_tvalid : out STD_LOGIC; --@suppress + m_axis_rc_tready : in STD_LOGIC; --@suppress + m_axis_cq_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 ); --@suppress + m_axis_cq_tuser : out STD_LOGIC_VECTOR ( 84 downto 0 ); --@suppress + m_axis_cq_tlast : out STD_LOGIC; --@suppress + m_axis_cq_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + m_axis_cq_tvalid : out STD_LOGIC; --@suppress + m_axis_cq_tready : in STD_LOGIC; --@suppress + s_axis_cc_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); --@suppress + s_axis_cc_tuser : in STD_LOGIC_VECTOR ( 32 downto 0 ); --@suppress + s_axis_cc_tlast : in STD_LOGIC; --@suppress + s_axis_cc_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + s_axis_cc_tvalid : in STD_LOGIC; --@suppress + s_axis_cc_tready : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + pcie_rq_seq_num : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + pcie_rq_seq_num_vld : out STD_LOGIC; --@suppress + pcie_rq_tag : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + pcie_rq_tag_vld : out STD_LOGIC; --@suppress + pcie_tfc_nph_av : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + pcie_tfc_npd_av : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + pcie_cq_np_req : in STD_LOGIC; --@suppress + pcie_cq_np_req_count : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + cfg_phy_link_down : out STD_LOGIC; --@suppress + cfg_phy_link_status : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_negotiated_width : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_current_speed : out STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_max_payload : out STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_max_read_req : out STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_function_status : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_function_power_state : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + cfg_vf_status : out STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + cfg_vf_power_state : out STD_LOGIC_VECTOR ( 17 downto 0 ); --@suppress + cfg_link_power_state : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_mgmt_addr : in STD_LOGIC_VECTOR ( 18 downto 0 ); --@suppress + cfg_mgmt_write : in STD_LOGIC; --@suppress + cfg_mgmt_write_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + cfg_mgmt_byte_enable : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_mgmt_read : in STD_LOGIC; --@suppress + cfg_mgmt_read_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + cfg_mgmt_read_write_done : out STD_LOGIC; --@suppress + cfg_mgmt_type1_cfg_reg_access : in STD_LOGIC; --@suppress + cfg_err_cor_out : out STD_LOGIC; --@suppress + cfg_err_nonfatal_out : out STD_LOGIC; --@suppress + cfg_err_fatal_out : out STD_LOGIC; --@suppress + cfg_ltr_enable : out STD_LOGIC; --@suppress + cfg_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + cfg_rcb_status : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_dpa_substate_change : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_obff_enable : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_pl_status_change : out STD_LOGIC; --@suppress + cfg_tph_requester_enable : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_tph_st_mode : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + cfg_vf_tph_requester_enable : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + cfg_vf_tph_st_mode : out STD_LOGIC_VECTOR ( 17 downto 0 ); --@suppress + cfg_msg_received : out STD_LOGIC; --@suppress + cfg_msg_received_data : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_msg_received_type : out STD_LOGIC_VECTOR ( 4 downto 0 ); --@suppress + cfg_msg_transmit : in STD_LOGIC; --@suppress + cfg_msg_transmit_type : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_msg_transmit_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + cfg_msg_transmit_done : out STD_LOGIC; --@suppress + cfg_fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + cfg_fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + cfg_fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + cfg_fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_per_func_status_control : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_per_func_status_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + cfg_per_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_per_function_output_request : in STD_LOGIC; --@suppress + cfg_per_function_update_done : out STD_LOGIC; --@suppress + cfg_subsys_vend_id : in STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); --@suppress + cfg_power_state_change_ack : in STD_LOGIC; --@suppress + cfg_power_state_change_interrupt : out STD_LOGIC; --@suppress + cfg_err_cor_in : in STD_LOGIC; --@suppress + cfg_err_uncor_in : in STD_LOGIC; --@suppress + cfg_flr_in_process : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_flr_done : in STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_vf_flr_in_process : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + cfg_vf_flr_done : in STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + cfg_link_training_enable : in STD_LOGIC; --@suppress + cfg_ext_read_received : out STD_LOGIC; --@suppress + cfg_ext_write_received : out STD_LOGIC; --@suppress + cfg_ext_register_number : out STD_LOGIC_VECTOR ( 9 downto 0 ); --@suppress + cfg_ext_function_number : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_ext_write_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + cfg_ext_write_byte_enable : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_ext_read_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + cfg_ext_read_data_valid : in STD_LOGIC; --@suppress + cfg_interrupt_int : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_interrupt_pending : in STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_interrupt_sent : out STD_LOGIC; --@suppress + cfg_interrupt_msix_enable : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_interrupt_msix_mask : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_interrupt_msix_vf_enable : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + cfg_interrupt_msix_vf_mask : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + cfg_interrupt_msix_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + cfg_interrupt_msix_address : in STD_LOGIC_VECTOR ( 63 downto 0 ); --@suppress + cfg_interrupt_msix_int : in STD_LOGIC; --@suppress + cfg_interrupt_msix_sent : out STD_LOGIC; --@suppress + cfg_interrupt_msix_fail : out STD_LOGIC; --@suppress + cfg_hot_reset_out : out STD_LOGIC; --@suppress + cfg_config_space_enable : in STD_LOGIC; --@suppress + cfg_req_pm_transition_l23_ready : in STD_LOGIC; --@suppress + cfg_hot_reset_in : in STD_LOGIC; --@suppress + cfg_ds_port_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); --@suppress + cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + sys_clk : in STD_LOGIC; --@suppress + sys_reset : in STD_LOGIC --@suppress ); end pcie_x8_gen3_3_0; diff --git a/sources/ip_cores/kintexUltrascale/xadc_wiz_0_stub.vhdl b/sources/ip_cores/kintexUltrascale/xadc_wiz_0_stub.vhdl index 52de367a010744f5d7d302d7822372762336da9a..00ff9f3cee8a692fa5da8439801ff3ecb94439c0 100644 --- a/sources/ip_cores/kintexUltrascale/xadc_wiz_0_stub.vhdl +++ b/sources/ip_cores/kintexUltrascale/xadc_wiz_0_stub.vhdl @@ -14,21 +14,21 @@ use IEEE.STD_LOGIC_1164.ALL; entity xadc_wiz_0 is Port ( - daddr_in : in STD_LOGIC_VECTOR ( 6 downto 0 ); - den_in : in STD_LOGIC; - di_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); - dwe_in : in STD_LOGIC; - do_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); - drdy_out : out STD_LOGIC; - dclk_in : in STD_LOGIC; - reset_in : in STD_LOGIC; - busy_out : out STD_LOGIC; - channel_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); - eoc_out : out STD_LOGIC; - eos_out : out STD_LOGIC; - alarm_out : out STD_LOGIC; - vp_in : in STD_LOGIC; - vn_in : in STD_LOGIC + daddr_in : in STD_LOGIC_VECTOR ( 6 downto 0 ); -- @suppress "Unused port: daddr_in is not used in work.xadc_wiz_0(stub)" + den_in : in STD_LOGIC; -- @suppress "Unused port: den_in is not used in work.xadc_wiz_0(stub)" + di_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: di_in is not used in work.xadc_wiz_0(stub)" + dwe_in : in STD_LOGIC; -- @suppress "Unused port: dwe_in is not used in work.xadc_wiz_0(stub)" + do_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: do_out is not used in work.xadc_wiz_0(stub)" + drdy_out : out STD_LOGIC; -- @suppress "Unused port: drdy_out is not used in work.xadc_wiz_0(stub)" + dclk_in : in STD_LOGIC; -- @suppress "Unused port: dclk_in is not used in work.xadc_wiz_0(stub)" + reset_in : in STD_LOGIC; -- @suppress "Unused port: reset_in is not used in work.xadc_wiz_0(stub)" + busy_out : out STD_LOGIC; -- @suppress "Unused port: busy_out is not used in work.xadc_wiz_0(stub)" + channel_out : out STD_LOGIC_VECTOR ( 4 downto 0 ); -- @suppress "Unused port: channel_out is not used in work.xadc_wiz_0(stub)" + eoc_out : out STD_LOGIC; -- @suppress "Unused port: eoc_out is not used in work.xadc_wiz_0(stub)" + eos_out : out STD_LOGIC; -- @suppress "Unused port: eos_out is not used in work.xadc_wiz_0(stub)" + alarm_out : out STD_LOGIC; -- @suppress "Unused port: alarm_out is not used in work.xadc_wiz_0(stub)" + vp_in : in STD_LOGIC; -- @suppress "Unused port: vp_in is not used in work.xadc_wiz_0(stub)" + vn_in : in STD_LOGIC -- @suppress "Unused port: vn_in is not used in work.xadc_wiz_0(stub)" ); end xadc_wiz_0; diff --git a/sources/ip_cores/stub/BUFGMUX_stub.vhdl b/sources/ip_cores/stub/BUFGMUX_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..c5e0ade2db1b217c65b7da27c7ca1570c9dc1348 --- /dev/null +++ b/sources/ip_cores/stub/BUFGMUX_stub.vhdl @@ -0,0 +1,16 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity BUFGMUX is + generic ( + CLK_SEL_TYPE : string := "SYNC");--@suppress + port ( --@suppress + O : out std_ulogic := '0'; --@suppress + I0 : in std_ulogic := '0'; --@suppress + I1 : in std_ulogic := '0'; --@suppress + S : in std_ulogic := '0'); --@suppress +end BUFGMUX; + +architecture stub of BUFGMUX is +begin +end; diff --git a/sources/ip_cores/stub/I2C_RDFifo_stub.vhdl b/sources/ip_cores/stub/I2C_RDFifo_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..a4c210728a64eb165383ebafa0d8426714242d80 --- /dev/null +++ b/sources/ip_cores/stub/I2C_RDFifo_stub.vhdl @@ -0,0 +1,38 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 15:33:46 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/I2C_RDFifo/I2C_RDFifo_stub.vhdl +-- Design : I2C_RDFifo +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity I2C_RDFifo is + Port ( + rst : in STD_LOGIC;--@suppress + wr_clk : in STD_LOGIC;--@suppress + rd_clk : in STD_LOGIC;--@suppress + din : in STD_LOGIC_VECTOR ( 7 downto 0 );--@suppress + wr_en : in STD_LOGIC;--@suppress + rd_en : in STD_LOGIC;--@suppress + dout : out STD_LOGIC_VECTOR ( 7 downto 0 );--@suppress + full : out STD_LOGIC;--@suppress + empty : out STD_LOGIC--@suppress + ); + +end I2C_RDFifo; + +architecture stub of I2C_RDFifo is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[7:0],wr_en,rd_en,dout[7:0],full,empty"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/I2C_WRFifo_stub.vhdl b/sources/ip_cores/stub/I2C_WRFifo_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..767eff4eea07f44359a7e8d1f81ff724cd93cbca --- /dev/null +++ b/sources/ip_cores/stub/I2C_WRFifo_stub.vhdl @@ -0,0 +1,38 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 15:33:56 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/I2C_WRFifo/I2C_WRFifo_stub.vhdl +-- Design : I2C_WRFifo +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity I2C_WRFifo is + Port ( + rst : in STD_LOGIC;--@suppress + wr_clk : in STD_LOGIC;--@suppress + rd_clk : in STD_LOGIC;--@suppress + din : in STD_LOGIC_VECTOR ( 24 downto 0 );--@suppress + wr_en : in STD_LOGIC;--@suppress + rd_en : in STD_LOGIC;--@suppress + dout : out STD_LOGIC_VECTOR ( 24 downto 0 );--@suppress + full : out STD_LOGIC;--@suppress + empty : out STD_LOGIC--@suppress + ); + +end I2C_WRFifo; + +architecture stub of I2C_WRFifo is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[24:0],wr_en,rd_en,dout[24:0],full,empty"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/KCU_NORXBUF_PCS_CPLL_1CH_stub.vhdl b/sources/ip_cores/stub/KCU_NORXBUF_PCS_CPLL_1CH_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..dd3c157b9a90335a2f3fe2b03e0d699c9d3322e7 --- /dev/null +++ b/sources/ip_cores/stub/KCU_NORXBUF_PCS_CPLL_1CH_stub.vhdl @@ -0,0 +1,86 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:41:43 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/KCU_NORXBUF_PCS_CPLL_1CH/KCU_NORXBUF_PCS_CPLL_1CH_stub.vhdl +-- Design : KCU_NORXBUF_PCS_CPLL_1CH +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity KCU_NORXBUF_PCS_CPLL_1CH is + Port ( + gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_buffbypass_rx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_buffbypass_rx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_buffbypass_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_buffbypass_rx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 19 downto 0 );--@suppress + gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 19 downto 0 );--@suppress + cplllockdetclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + cpllreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtgrefclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gthrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gthrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + loopback_in : in STD_LOGIC_VECTOR ( 2 downto 0 );--@suppress + rxcdrhold_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + rxcdrreset_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + rxcommadeten_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + rxmcommaalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + rxpcommaalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + rxpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + rxslide_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + txpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + txusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + cpllfbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + cplllock_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gthtxn_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gthtxp_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtpowergood_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + rxbyteisaligned_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + rxbyterealign_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + rxcdrlock_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + rxcommadet_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + rxdata_out : out STD_LOGIC_VECTOR ( 127 downto 0 );--@suppress + rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + rxresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + txoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + txpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + txresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 )--@suppress + ); + +end KCU_NORXBUF_PCS_CPLL_1CH; + +architecture stub of KCU_NORXBUF_PCS_CPLL_1CH is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "gtwiz_userclk_tx_active_in[0:0],gtwiz_userclk_rx_active_in[0:0],gtwiz_buffbypass_tx_reset_in[0:0],gtwiz_buffbypass_tx_start_user_in[0:0],gtwiz_buffbypass_tx_done_out[0:0],gtwiz_buffbypass_tx_error_out[0:0],gtwiz_buffbypass_rx_reset_in[0:0],gtwiz_buffbypass_rx_start_user_in[0:0],gtwiz_buffbypass_rx_done_out[0:0],gtwiz_buffbypass_rx_error_out[0:0],gtwiz_reset_clk_freerun_in[0:0],gtwiz_reset_all_in[0:0],gtwiz_reset_tx_pll_and_datapath_in[0:0],gtwiz_reset_tx_datapath_in[0:0],gtwiz_reset_rx_pll_and_datapath_in[0:0],gtwiz_reset_rx_datapath_in[0:0],gtwiz_reset_rx_cdr_stable_out[0:0],gtwiz_reset_tx_done_out[0:0],gtwiz_reset_rx_done_out[0:0],gtwiz_userdata_tx_in[19:0],gtwiz_userdata_rx_out[19:0],cplllockdetclk_in[0:0],cpllreset_in[0:0],drpclk_in[0:0],gtgrefclk_in[0:0],gthrxn_in[0:0],gthrxp_in[0:0],gtrefclk0_in[0:0],loopback_in[2:0],rxcdrhold_in[0:0],rxcdrreset_in[0:0],rxcommadeten_in[0:0],rxmcommaalignen_in[0:0],rxpcommaalignen_in[0:0],rxpolarity_in[0:0],rxslide_in[0:0],rxusrclk_in[0:0],rxusrclk2_in[0:0],txpolarity_in[0:0],txusrclk_in[0:0],txusrclk2_in[0:0],cpllfbclklost_out[0:0],cplllock_out[0:0],gthtxn_out[0:0],gthtxp_out[0:0],gtpowergood_out[0:0],rxbyteisaligned_out[0:0],rxbyterealign_out[0:0],rxcdrlock_out[0:0],rxcommadet_out[0:0],rxdata_out[127:0],rxoutclk_out[0:0],rxpmaresetdone_out[0:0],rxresetdone_out[0:0],txoutclk_out[0:0],txpmaresetdone_out[0:0],txresetdone_out[0:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "KCU_NORXBUF_PCS_CPLL_1CH_gtwizard_top,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/KCU_RXBUF_PMA_CPLL_1CH_stub.vhdl b/sources/ip_cores/stub/KCU_RXBUF_PMA_CPLL_1CH_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..c1f21cae296e60b3bc78dace15b54a2ba2c5ace6 --- /dev/null +++ b/sources/ip_cores/stub/KCU_RXBUF_PMA_CPLL_1CH_stub.vhdl @@ -0,0 +1,82 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:41:45 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/KCU_RXBUF_PMA_CPLL_1CH/KCU_RXBUF_PMA_CPLL_1CH_stub.vhdl +-- Design : KCU_RXBUF_PMA_CPLL_1CH +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity KCU_RXBUF_PMA_CPLL_1CH is + Port ( + gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + cplllockdetclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + cpllreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + drpclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtgrefclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gthrxn_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gthrxp_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtrefclk0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + loopback_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + rxcdrhold_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + rxcdrreset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + rxcommadeten_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + rxmcommaalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + rxpcommaalignen_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + rxpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + rxslide_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + rxusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + rxusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + txpolarity_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + txusrclk_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + txusrclk2_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + cpllfbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + cplllock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gthtxn_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gthtxp_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtpowergood_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + rxbyteisaligned_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + rxbyterealign_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + rxcdrlock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + rxcommadet_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + rxdata_out : out STD_LOGIC_VECTOR ( 127 downto 0 ); --@suppress + rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + rxresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + txoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + txpmaresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + txresetdone_out : out STD_LOGIC_VECTOR ( 0 to 0 ) --@suppress + ); + +end KCU_RXBUF_PMA_CPLL_1CH; + +architecture stub of KCU_RXBUF_PMA_CPLL_1CH is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "gtwiz_userclk_tx_active_in[0:0],gtwiz_userclk_rx_active_in[0:0],gtwiz_buffbypass_tx_reset_in[0:0],gtwiz_buffbypass_tx_start_user_in[0:0],gtwiz_buffbypass_tx_done_out[0:0],gtwiz_buffbypass_tx_error_out[0:0],gtwiz_reset_clk_freerun_in[0:0],gtwiz_reset_all_in[0:0],gtwiz_reset_tx_pll_and_datapath_in[0:0],gtwiz_reset_tx_datapath_in[0:0],gtwiz_reset_rx_pll_and_datapath_in[0:0],gtwiz_reset_rx_datapath_in[0:0],gtwiz_reset_rx_cdr_stable_out[0:0],gtwiz_reset_tx_done_out[0:0],gtwiz_reset_rx_done_out[0:0],gtwiz_userdata_tx_in[19:0],gtwiz_userdata_rx_out[19:0],cplllockdetclk_in[0:0],cpllreset_in[0:0],drpclk_in[0:0],gtgrefclk_in[0:0],gthrxn_in[0:0],gthrxp_in[0:0],gtrefclk0_in[0:0],loopback_in[2:0],rxcdrhold_in[0:0],rxcdrreset_in[0:0],rxcommadeten_in[0:0],rxmcommaalignen_in[0:0],rxpcommaalignen_in[0:0],rxpolarity_in[0:0],rxslide_in[0:0],rxusrclk_in[0:0],rxusrclk2_in[0:0],txpolarity_in[0:0],txusrclk_in[0:0],txusrclk2_in[0:0],cpllfbclklost_out[0:0],cplllock_out[0:0],gthtxn_out[0:0],gthtxp_out[0:0],gtpowergood_out[0:0],rxbyteisaligned_out[0:0],rxbyterealign_out[0:0],rxcdrlock_out[0:0],rxcommadet_out[0:0],rxdata_out[127:0],rxoutclk_out[0:0],rxpmaresetdone_out[0:0],rxresetdone_out[0:0],txoutclk_out[0:0],txpmaresetdone_out[0:0],txresetdone_out[0:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "KCU_RXBUF_PMA_CPLL_1CH_gtwizard_top,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/KCU_RXBUF_PMA_QPLL_4CH_LPGBT_stub.vhdl b/sources/ip_cores/stub/KCU_RXBUF_PMA_QPLL_4CH_LPGBT_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..d3956bfbee8a7d42232ce0f4c1d06811b07ec37d --- /dev/null +++ b/sources/ip_cores/stub/KCU_RXBUF_PMA_QPLL_4CH_LPGBT_stub.vhdl @@ -0,0 +1,77 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 15:29:51 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/KCU_RXBUF_PMA_QPLL_4CH_LPGBT/KCU_RXBUF_PMA_QPLL_4CH_LPGBT_stub.vhdl +-- Design : KCU_RXBUF_PMA_QPLL_4CH_LPGBT +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity KCU_RXBUF_PMA_QPLL_4CH_LPGBT is + Port ( + gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 63 downto 0 ); --@suppress + gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 127 downto 0 ); --@suppress + gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + drpclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gthrxn_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gthrxp_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gtrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + loopback_in : in STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + rxcdrhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxslide_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cplllock_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gthtxn_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gthtxp_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gtpowergood_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxcdrlock_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 ) --@suppress + ); + +end KCU_RXBUF_PMA_QPLL_4CH_LPGBT; + +architecture stub of KCU_RXBUF_PMA_QPLL_4CH_LPGBT is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "gtwiz_userclk_tx_active_in[0:0],gtwiz_userclk_rx_active_in[0:0],gtwiz_buffbypass_tx_reset_in[0:0],gtwiz_buffbypass_tx_start_user_in[0:0],gtwiz_buffbypass_tx_done_out[0:0],gtwiz_buffbypass_tx_error_out[0:0],gtwiz_reset_clk_freerun_in[0:0],gtwiz_reset_all_in[0:0],gtwiz_reset_tx_pll_and_datapath_in[0:0],gtwiz_reset_tx_datapath_in[0:0],gtwiz_reset_rx_pll_and_datapath_in[0:0],gtwiz_reset_rx_datapath_in[0:0],gtwiz_reset_rx_cdr_stable_out[0:0],gtwiz_reset_tx_done_out[0:0],gtwiz_reset_rx_done_out[0:0],gtwiz_userdata_tx_in[63:0],gtwiz_userdata_rx_out[127:0],gtrefclk01_in[0:0],qpll0fbclklost_out[0:0],qpll0lock_out[0:0],qpll1fbclklost_out[0:0],qpll1lock_out[0:0],qpll1outclk_out[0:0],qpll1outrefclk_out[0:0],drpclk_in[3:0],gthrxn_in[3:0],gthrxp_in[3:0],gtrefclk0_in[3:0],loopback_in[11:0],rxcdrhold_in[3:0],rxpolarity_in[3:0],rxslide_in[3:0],rxusrclk_in[3:0],rxusrclk2_in[3:0],txpolarity_in[3:0],txusrclk_in[3:0],txusrclk2_in[3:0],cplllock_out[3:0],gthtxn_out[3:0],gthtxp_out[3:0],gtpowergood_out[3:0],rxcdrlock_out[3:0],rxoutclk_out[3:0],rxpmaresetdone_out[3:0],rxresetdone_out[3:0],txoutclk_out[3:0],txpmaresetdone_out[3:0],txresetdone_out[3:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "KCU_RXBUF_PMA_QPLL_4CH_LPGBT_gtwizard_top,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/KCU_RXBUF_PMA_QPLL_4CH_stub.vhdl b/sources/ip_cores/stub/KCU_RXBUF_PMA_QPLL_4CH_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..d19fb272583fcba8db99dacd29d5071565a7878d --- /dev/null +++ b/sources/ip_cores/stub/KCU_RXBUF_PMA_QPLL_4CH_stub.vhdl @@ -0,0 +1,74 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:41:52 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/KCU_RXBUF_PMA_QPLL_4CH/KCU_RXBUF_PMA_QPLL_4CH_stub.vhdl +-- Design : KCU_RXBUF_PMA_QPLL_4CH +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity KCU_RXBUF_PMA_QPLL_4CH is + Port ( + gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 79 downto 0 ); --@suppress + gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 79 downto 0 ); --@suppress + gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gthrxn_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gthrxp_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + loopback_in : in STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + rxcdrhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxslide_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gthtxn_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gthtxp_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gtpowergood_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxcdrlock_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 ) --@suppress + ); + +end KCU_RXBUF_PMA_QPLL_4CH; + +architecture stub of KCU_RXBUF_PMA_QPLL_4CH is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "gtwiz_userclk_tx_active_in[0:0],gtwiz_userclk_rx_active_in[0:0],gtwiz_buffbypass_tx_reset_in[0:0],gtwiz_buffbypass_tx_start_user_in[0:0],gtwiz_buffbypass_tx_done_out[0:0],gtwiz_buffbypass_tx_error_out[0:0],gtwiz_reset_clk_freerun_in[0:0],gtwiz_reset_all_in[0:0],gtwiz_reset_tx_pll_and_datapath_in[0:0],gtwiz_reset_tx_datapath_in[0:0],gtwiz_reset_rx_pll_and_datapath_in[0:0],gtwiz_reset_rx_datapath_in[0:0],gtwiz_reset_rx_cdr_stable_out[0:0],gtwiz_reset_tx_done_out[0:0],gtwiz_reset_rx_done_out[0:0],gtwiz_userdata_tx_in[79:0],gtwiz_userdata_rx_out[79:0],gtrefclk01_in[0:0],qpll0fbclklost_out[0:0],qpll0lock_out[0:0],qpll1fbclklost_out[0:0],qpll1lock_out[0:0],qpll1outclk_out[0:0],qpll1outrefclk_out[0:0],gthrxn_in[3:0],gthrxp_in[3:0],loopback_in[11:0],rxcdrhold_in[3:0],rxpolarity_in[3:0],rxslide_in[3:0],rxusrclk_in[3:0],rxusrclk2_in[3:0],txpolarity_in[3:0],txusrclk_in[3:0],txusrclk2_in[3:0],gthtxn_out[3:0],gthtxp_out[3:0],gtpowergood_out[3:0],rxcdrlock_out[3:0],rxoutclk_out[3:0],rxpmaresetdone_out[3:0],rxresetdone_out[3:0],txoutclk_out[3:0],txpmaresetdone_out[3:0],txresetdone_out[3:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "KCU_RXBUF_PMA_QPLL_4CH_gtwizard_top,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT_stub.vhdl b/sources/ip_cores/stub/KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..d8bce893ab7172a6335fa0671bcd68c29ac4e01c --- /dev/null +++ b/sources/ip_cores/stub/KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT_stub.vhdl @@ -0,0 +1,77 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 15:30:21 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT/KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT_stub.vhdl +-- Design : KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT is + Port ( + gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 127 downto 0 ); --@suppress + gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 63 downto 0 ); --@suppress + gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll0fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll1fbclklost_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 ); --@suppress + drpclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gthrxn_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gthrxp_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gtrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + loopback_in : in STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + rxcdrhold_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxslide_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txpolarity_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cplllock_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gthtxn_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gthtxp_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + gtpowergood_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxcdrlock_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + rxresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + txresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 ) --@suppress + ); + +end KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT; + +architecture stub of KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "gtwiz_userclk_tx_active_in[0:0],gtwiz_userclk_rx_active_in[0:0],gtwiz_buffbypass_tx_reset_in[0:0],gtwiz_buffbypass_tx_start_user_in[0:0],gtwiz_buffbypass_tx_done_out[0:0],gtwiz_buffbypass_tx_error_out[0:0],gtwiz_reset_clk_freerun_in[0:0],gtwiz_reset_all_in[0:0],gtwiz_reset_tx_pll_and_datapath_in[0:0],gtwiz_reset_tx_datapath_in[0:0],gtwiz_reset_rx_pll_and_datapath_in[0:0],gtwiz_reset_rx_datapath_in[0:0],gtwiz_reset_rx_cdr_stable_out[0:0],gtwiz_reset_tx_done_out[0:0],gtwiz_reset_rx_done_out[0:0],gtwiz_userdata_tx_in[127:0],gtwiz_userdata_rx_out[63:0],gtrefclk01_in[0:0],qpll0fbclklost_out[0:0],qpll0lock_out[0:0],qpll1fbclklost_out[0:0],qpll1lock_out[0:0],qpll1outclk_out[0:0],qpll1outrefclk_out[0:0],drpclk_in[3:0],gthrxn_in[3:0],gthrxp_in[3:0],gtrefclk0_in[3:0],loopback_in[11:0],rxcdrhold_in[3:0],rxpolarity_in[3:0],rxslide_in[3:0],rxusrclk_in[3:0],rxusrclk2_in[3:0],txpolarity_in[3:0],txusrclk_in[3:0],txusrclk2_in[3:0],cplllock_out[3:0],gthtxn_out[3:0],gthtxp_out[3:0],gtpowergood_out[3:0],rxcdrlock_out[3:0],rxoutclk_out[3:0],rxpmaresetdone_out[3:0],rxresetdone_out[3:0],txoutclk_out[3:0],txpmaresetdone_out[3:0],txresetdone_out[3:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "KCU_RXBUF_PMA_QPLL_FE4CH_LPGBT_gtwizard_top,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/TTCtoHostData_fwft_stub.vhdl b/sources/ip_cores/stub/TTCtoHostData_fwft_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..3c6c55d96e780d38f3dd93cd4003d2b858a69784 --- /dev/null +++ b/sources/ip_cores/stub/TTCtoHostData_fwft_stub.vhdl @@ -0,0 +1,38 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 15:35:43 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/TTCtoHostData_fwft/TTCtoHostData_fwft_stub.vhdl +-- Design : TTCtoHostData_fwft +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity TTCtoHostData_fwft is + Port ( + clk : in STD_LOGIC; --@suppress + srst : in STD_LOGIC; --@suppress + din : in STD_LOGIC_VECTOR ( 144 downto 0 ); --@suppress + wr_en : in STD_LOGIC; --@suppress + rd_en : in STD_LOGIC; --@suppress + dout : out STD_LOGIC_VECTOR ( 144 downto 0 ); --@suppress + full : out STD_LOGIC; --@suppress + empty : out STD_LOGIC; --@suppress + data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ) --@suppress + ); + +end TTCtoHostData_fwft; + +architecture stub of TTCtoHostData_fwft is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,srst,din[144:0],wr_en,rd_en,dout[144:0],full,empty,data_count[10:0],wr_rst_busy,rd_rst_busy"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/TTCtoHostData_reclock_stub.vhdl b/sources/ip_cores/stub/TTCtoHostData_reclock_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..e9dedb660fc994909aed07f92d884a48e0403c2a --- /dev/null +++ b/sources/ip_cores/stub/TTCtoHostData_reclock_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 15:35:50 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/TTCtoHostData_reclock/TTCtoHostData_reclock_stub.vhdl +-- Design : TTCtoHostData_reclock +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity TTCtoHostData_reclock is + Port ( + rst : in STD_LOGIC; --@suppress + wr_clk : in STD_LOGIC; --@suppress + rd_clk : in STD_LOGIC; --@suppress + din : in STD_LOGIC_VECTOR ( 159 downto 0 ); --@suppress + wr_en : in STD_LOGIC; --@suppress + rd_en : in STD_LOGIC; --@suppress + dout : out STD_LOGIC_VECTOR ( 159 downto 0 ); --@suppress + full : out STD_LOGIC; --@suppress + empty : out STD_LOGIC; --@suppress + valid : out STD_LOGIC --@suppress + ); + +end TTCtoHostData_reclock; + +architecture stub of TTCtoHostData_reclock is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[159:0],wr_en,rd_en,dout[159:0],full,empty,valid"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/axi8_fifo_bif_stub.vhdl b/sources/ip_cores/stub/axi8_fifo_bif_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..4a99a046cb7c808daeb2f80aa83af7ad9207b424 --- /dev/null +++ b/sources/ip_cores/stub/axi8_fifo_bif_stub.vhdl @@ -0,0 +1,43 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 15:34:59 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/axi8_fifo_bif/axi8_fifo_bif_stub.vhdl +-- Design : axi8_fifo_bif +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity axi8_fifo_bif is + Port ( + wr_rst_busy : out STD_LOGIC; --@suppress + rd_rst_busy : out STD_LOGIC; --@suppress + m_aclk : in STD_LOGIC; --@suppress + s_aclk : in STD_LOGIC; --@suppress + s_aresetn : in STD_LOGIC; --@suppress + s_axis_tvalid : in STD_LOGIC; --@suppress + s_axis_tready : out STD_LOGIC; --@suppress + s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + s_axis_tlast : in STD_LOGIC; --@suppress + m_axis_tvalid : out STD_LOGIC; --@suppress + m_axis_tready : in STD_LOGIC; --@suppress + m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + m_axis_tlast : out STD_LOGIC; --@suppress + axis_prog_full : out STD_LOGIC --@suppress + ); + +end axi8_fifo_bif; + +architecture stub of axi8_fifo_bif is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "wr_rst_busy,rd_rst_busy,m_aclk,s_aclk,s_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[7:0],s_axis_tlast,m_axis_tvalid,m_axis_tready,m_axis_tdata[7:0],m_axis_tlast,axis_prog_full"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/axis32_fifo_bif_stub.vhdl b/sources/ip_cores/stub/axis32_fifo_bif_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..b9d1db5fb6e4643f53640a39223de3ebf9488df9 --- /dev/null +++ b/sources/ip_cores/stub/axis32_fifo_bif_stub.vhdl @@ -0,0 +1,43 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 15:35:00 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/axis32_fifo_bif/axis32_fifo_bif_stub.vhdl +-- Design : axis32_fifo_bif +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity axis32_fifo_bif is + Port ( + m_aclk : in STD_LOGIC; --@suppress + s_aclk : in STD_LOGIC; --@suppress + s_aresetn : in STD_LOGIC; --@suppress + s_axis_tvalid : in STD_LOGIC; --@suppress + s_axis_tready : out STD_LOGIC; --@suppress + s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + s_axis_tlast : in STD_LOGIC; --@suppress + s_axis_tuser : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + m_axis_tvalid : out STD_LOGIC; --@suppress + m_axis_tready : in STD_LOGIC; --@suppress + m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + m_axis_tlast : out STD_LOGIC; --@suppress + m_axis_tuser : out STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + axis_prog_empty : out STD_LOGIC --@suppress + ); + +end axis32_fifo_bif; + +architecture stub of axis32_fifo_bif is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "m_aclk,s_aclk,s_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],s_axis_tlast,s_axis_tuser[2:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0],m_axis_tlast,m_axis_tuser[2:0],axis_prog_empty"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/clk_wiz_100_0_stub.vhdl b/sources/ip_cores/stub/clk_wiz_100_0_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..895389016de924936511d7ae201ff233d08cbfb6 --- /dev/null +++ b/sources/ip_cores/stub/clk_wiz_100_0_stub.vhdl @@ -0,0 +1,33 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 15:29:57 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/clk_wiz_100_0/clk_wiz_100_0_stub.vhdl +-- Design : clk_wiz_100_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_100_0 is + Port ( + clk40 : out STD_LOGIC; -- @suppress "Unused port: clk40 is not used in work.clk_wiz_100_0(stub)" + clk10 : out STD_LOGIC; -- @suppress "Unused port: clk10 is not used in work.clk_wiz_100_0(stub)" + reset : in STD_LOGIC; -- @suppress "Unused port: reset is not used in work.clk_wiz_100_0(stub)" + locked : out STD_LOGIC; -- @suppress "Unused port: locked is not used in work.clk_wiz_100_0(stub)" + clk_in1_p : in STD_LOGIC; -- @suppress "Unused port: clk_in1_p is not used in work.clk_wiz_100_0(stub)" + clk_in1_n : in STD_LOGIC -- @suppress "Unused port: clk_in1_n is not used in work.clk_wiz_100_0(stub)" + ); + +end clk_wiz_100_0; + +architecture stub of clk_wiz_100_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk40,clk10,reset,locked,clk_in1_p,clk_in1_n"; +begin +end; diff --git a/sources/ip_cores/stub/clk_wiz_156_0_stub.vhdl b/sources/ip_cores/stub/clk_wiz_156_0_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..c70479bd0e96dff8e0a983cc53aa46550a805daa --- /dev/null +++ b/sources/ip_cores/stub/clk_wiz_156_0_stub.vhdl @@ -0,0 +1,33 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 15:29:57 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/clk_wiz_156_0/clk_wiz_156_0_stub.vhdl +-- Design : clk_wiz_156_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_156_0 is + Port ( + clk40 : out STD_LOGIC; -- @suppress "Unused port: clk40 is not used in work.clk_wiz_156_0(stub)" -- @suppress "Unused port: clk10 is not used in work.clk_wiz_156_0(stub)" + clk10 : out STD_LOGIC; -- @suppress "Unused port: clk10 is not used in work.clk_wiz_156_0(stub)" + reset : in STD_LOGIC; -- @suppress "Unused port: reset is not used in work.clk_wiz_156_0(stub)" + locked : out STD_LOGIC; -- @suppress "Unused port: locked is not used in work.clk_wiz_156_0(stub)" + clk_in1_p : in STD_LOGIC; -- @suppress "Unused port: clk_in1_p is not used in work.clk_wiz_156_0(stub)" + clk_in1_n : in STD_LOGIC -- @suppress "Unused port: clk_in1_n is not used in work.clk_wiz_156_0(stub)" + ); + +end clk_wiz_156_0; + +architecture stub of clk_wiz_156_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk40,clk10,reset,locked,clk_in1_p,clk_in1_n"; +begin +end; diff --git a/sources/ip_cores/stub/clk_wiz_200_0_stub.vhdl b/sources/ip_cores/stub/clk_wiz_200_0_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..b277cd977ed260f9bc8602b6f358427631f886fa --- /dev/null +++ b/sources/ip_cores/stub/clk_wiz_200_0_stub.vhdl @@ -0,0 +1,33 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 15:30:03 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/clk_wiz_200_0/clk_wiz_200_0_stub.vhdl +-- Design : clk_wiz_200_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_200_0 is + Port ( + clk40 : out STD_LOGIC; -- @suppress "Unused port: clk40 is not used in work.clk_wiz_200_0(stub)" + clk10 : out STD_LOGIC; -- @suppress "Unused port: clk10 is not used in work.clk_wiz_200_0(stub)" + reset : in STD_LOGIC; -- @suppress "Unused port: reset is not used in work.clk_wiz_200_0(stub)" + locked : out STD_LOGIC; -- @suppress "Unused port: locked is not used in work.clk_wiz_200_0(stub)" + clk_in1_p : in STD_LOGIC; -- @suppress "Unused port: clk_in1_p is not used in work.clk_wiz_200_0(stub)" + clk_in1_n : in STD_LOGIC -- @suppress "Unused port: clk_in1_n is not used in work.clk_wiz_200_0(stub)" + ); + +end clk_wiz_200_0; + +architecture stub of clk_wiz_200_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk40,clk10,reset,locked,clk_in1_p,clk_in1_n"; +begin +end; diff --git a/sources/ip_cores/stub/clk_wiz_250_stub.vhdl b/sources/ip_cores/stub/clk_wiz_250_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..0ef6c36551210b7366c30c8401309015b333c8b1 --- /dev/null +++ b/sources/ip_cores/stub/clk_wiz_250_stub.vhdl @@ -0,0 +1,33 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 15:30:00 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/clk_wiz_250/clk_wiz_250_stub.vhdl +-- Design : clk_wiz_250 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_250 is + Port ( + clk_in40_2 : in STD_LOGIC; -- @suppress "Unused port: clk_in40_2 is not used in work.clk_wiz_250(stub)" + clk_in_sel : in STD_LOGIC; -- @suppress "Unused port: clk_in_sel is not used in work.clk_wiz_250(stub)" + clk250 : out STD_LOGIC; -- @suppress "Unused port: clk250 is not used in work.clk_wiz_250(stub)" + reset : in STD_LOGIC; -- @suppress "Unused port: reset is not used in work.clk_wiz_250(stub)" + locked : out STD_LOGIC; -- @suppress "Unused port: locked is not used in work.clk_wiz_250(stub)" + clk_in40_1 : in STD_LOGIC -- @suppress "Unused port: clk_in40_1 is not used in work.clk_wiz_250(stub)" + ); + +end clk_wiz_250; + +architecture stub of clk_wiz_250 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_in40_2,clk_in_sel,clk250,reset,locked,clk_in40_1"; +begin +end; diff --git a/sources/ip_cores/stub/clk_wiz_40_0_stub.vhdl b/sources/ip_cores/stub/clk_wiz_40_0_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..b8b9010dd048d6e90c6707d9adabee64646f7226 --- /dev/null +++ b/sources/ip_cores/stub/clk_wiz_40_0_stub.vhdl @@ -0,0 +1,38 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:44:24 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/clk_wiz_40_0/clk_wiz_40_0_stub.vhdl +-- Design : clk_wiz_40_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_40_0 is + Port ( + clk_in2 : in STD_LOGIC; -- @suppress "Unused port: clk_in2 is not used in work.clk_wiz_40_0(stub)" + clk_in_sel : in STD_LOGIC; -- @suppress "Unused port: clk_in_sel is not used in work.clk_wiz_40_0(stub)" + clk40 : out STD_LOGIC; -- @suppress "Unused port: clk40 is not used in work.clk_wiz_40_0(stub)" + clk80 : out STD_LOGIC; -- @suppress "Unused port: clk80 is not used in work.clk_wiz_40_0(stub)" + clk160 : out STD_LOGIC; -- @suppress "Unused port: clk160 is not used in work.clk_wiz_40_0(stub)" + clk320 : out STD_LOGIC; -- @suppress "Unused port: clk320 is not used in work.clk_wiz_40_0(stub)" + clk240 : out STD_LOGIC; -- @suppress "Unused port: clk240 is not used in work.clk_wiz_40_0(stub)" + clk250 : out STD_LOGIC; -- @suppress "Unused port: clk250 is not used in work.clk_wiz_40_0(stub)" + reset : in STD_LOGIC; -- @suppress "Unused port: reset is not used in work.clk_wiz_40_0(stub)" + locked : out STD_LOGIC; -- @suppress "Unused port: locked is not used in work.clk_wiz_40_0(stub)" + clk_40_in : in STD_LOGIC -- @suppress "Unused port: clk_40_in is not used in work.clk_wiz_40_0(stub)" + ); + +end clk_wiz_40_0; + +architecture stub of clk_wiz_40_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_in2,clk_in_sel,clk40,clk80,clk160,clk320,clk240,clk250,reset,locked,clk_40_in"; +begin +end; diff --git a/sources/ip_cores/stub/clk_wiz_regmap_stub.vhdl b/sources/ip_cores/stub/clk_wiz_regmap_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..915d002332e54409f1d38cda8cd42d4fd0fa0cfc --- /dev/null +++ b/sources/ip_cores/stub/clk_wiz_regmap_stub.vhdl @@ -0,0 +1,31 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:44:46 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/clk_wiz_regmap/clk_wiz_regmap_stub.vhdl +-- Design : clk_wiz_regmap +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_regmap is + Port ( + clk_out25 : out STD_LOGIC;--@suppress + reset : in STD_LOGIC; --@suppress + locked : out STD_LOGIC; --@suppress + clk_in1 : in STD_LOGIC --@suppress + ); + +end clk_wiz_regmap; + +architecture stub of clk_wiz_regmap is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_out25,reset,locked,clk_in1"; +begin +end; diff --git a/sources/ip_cores/stub/emuram_0_stub.vhdl b/sources/ip_cores/stub/emuram_0_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..7d9de0595bd8b20412842cdfa1e9a0fe483369a1 --- /dev/null +++ b/sources/ip_cores/stub/emuram_0_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:46:31 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/emuram_0/emuram_0_stub.vhdl +-- Design : emuram_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity emuram_0 is + Port ( + clka : in STD_LOGIC; -- @suppress "Unused port: clka is not used in work.emuram_0(stub)" + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); -- @suppress "Unused port: wea is not used in work.emuram_0(stub)" -- @suppress "Unused port: addra is not used in work.emuram_0(stub)" + addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); -- @suppress "Unused port: addra is not used in work.emuram_0(stub)" + dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: dina is not used in work.emuram_0(stub)" + douta : out STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: douta is not used in work.emuram_0(stub)" + clkb : in STD_LOGIC; -- @suppress "Unused port: clkb is not used in work.emuram_0(stub)" + web : in STD_LOGIC_VECTOR ( 0 to 0 ); -- @suppress "Unused port: web is not used in work.emuram_0(stub)" + addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); -- @suppress "Unused port: addrb is not used in work.emuram_0(stub)" + dinb : in STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: dinb is not used in work.emuram_0(stub)" + doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ) -- @suppress "Unused port: doutb is not used in work.emuram_0(stub)" + ); + +end emuram_0; + +architecture stub of emuram_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[13:0],dina[15:0],douta[15:0],clkb,web[0:0],addrb[13:0],dinb[15:0],doutb[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/emuram_1_stub.vhdl b/sources/ip_cores/stub/emuram_1_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..22d651c57f21533780e3614ee44f55828eb317e7 --- /dev/null +++ b/sources/ip_cores/stub/emuram_1_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:46:33 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/emuram_1/emuram_1_stub.vhdl +-- Design : emuram_1 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity emuram_1 is + Port ( + clka : in STD_LOGIC; -- @suppress "Unused port: clka is not used in work.emuram_1(stub)" + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); -- @suppress "Unused port: wea is not used in work.emuram_1(stub)" + addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); -- @suppress "Unused port: addra is not used in work.emuram_1(stub)" + dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: dina is not used in work.emuram_1(stub)" + douta : out STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: douta is not used in work.emuram_1(stub)" + clkb : in STD_LOGIC; -- @suppress "Unused port: clkb is not used in work.emuram_1(stub)" + web : in STD_LOGIC_VECTOR ( 0 to 0 ); -- @suppress "Unused port: web is not used in work.emuram_1(stub)" + addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); -- @suppress "Unused port: addrb is not used in work.emuram_1(stub)" + dinb : in STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: dinb is not used in work.emuram_1(stub)" + doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ) -- @suppress "Unused port: doutb is not used in work.emuram_1(stub)" + ); + +end emuram_1; + +architecture stub of emuram_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[13:0],dina[15:0],douta[15:0],clkb,web[0:0],addrb[13:0],dinb[15:0],doutb[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/emuram_2_stub.vhdl b/sources/ip_cores/stub/emuram_2_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..6f578cd8e19d71c854d6fe38bc01026123561973 --- /dev/null +++ b/sources/ip_cores/stub/emuram_2_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:46:36 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/emuram_2/emuram_2_stub.vhdl +-- Design : emuram_2 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity emuram_2 is + Port ( + clka : in STD_LOGIC; -- @suppress "Unused port: clka is not used in work.emuram_2(stub)" + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); -- @suppress "Unused port: wea is not used in work.emuram_2(stub)" + addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); -- @suppress "Unused port: addra is not used in work.emuram_2(stub)" + dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: dina is not used in work.emuram_2(stub)" + douta : out STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: douta is not used in work.emuram_2(stub)" + clkb : in STD_LOGIC; -- @suppress "Unused port: clkb is not used in work.emuram_2(stub)" + web : in STD_LOGIC_VECTOR ( 0 to 0 ); -- @suppress "Unused port: web is not used in work.emuram_2(stub)" + addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); -- @suppress "Unused port: addrb is not used in work.emuram_2(stub)" + dinb : in STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: dinb is not used in work.emuram_2(stub)" + doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ) -- @suppress "Unused port: doutb is not used in work.emuram_2(stub)" + ); + +end emuram_2; + +architecture stub of emuram_2 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[13:0],dina[15:0],douta[15:0],clkb,web[0:0],addrb[13:0],dinb[15:0],doutb[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/emuram_3_stub.vhdl b/sources/ip_cores/stub/emuram_3_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..6acfa8d2e9279ea944a486a4771152b93106b340 --- /dev/null +++ b/sources/ip_cores/stub/emuram_3_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:46:39 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/emuram_3/emuram_3_stub.vhdl +-- Design : emuram_3 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity emuram_3 is + Port ( + clka : in STD_LOGIC; -- @suppress "Unused port: clka is not used in work.emuram_3(stub)" + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); -- @suppress "Unused port: wea is not used in work.emuram_3(stub)" + addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); -- @suppress "Unused port: addra is not used in work.emuram_3(stub)" + dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: dina is not used in work.emuram_3(stub)" + douta : out STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: douta is not used in work.emuram_3(stub)" + clkb : in STD_LOGIC; -- @suppress "Unused port: clkb is not used in work.emuram_3(stub)" + web : in STD_LOGIC_VECTOR ( 0 to 0 ); -- @suppress "Unused port: web is not used in work.emuram_3(stub)" + addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); -- @suppress "Unused port: addrb is not used in work.emuram_3(stub)" + dinb : in STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: dinb is not used in work.emuram_3(stub)" + doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ) -- @suppress "Unused port: doutb is not used in work.emuram_3(stub)" + ); + +end emuram_3; + +architecture stub of emuram_3 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[13:0],dina[15:0],douta[15:0],clkb,web[0:0],addrb[13:0],dinb[15:0],doutb[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/emuram_4_stub.vhdl b/sources/ip_cores/stub/emuram_4_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..10d30efacbb23937139a29c0478b06adbaa92327 --- /dev/null +++ b/sources/ip_cores/stub/emuram_4_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:46:37 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/emuram_4/emuram_4_stub.vhdl +-- Design : emuram_4 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity emuram_4 is + Port ( + clka : in STD_LOGIC; -- @suppress "Unused port: clka is not used in work.emuram_4(stub)" + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); -- @suppress "Unused port: wea is not used in work.emuram_4(stub)" -- @suppress "Unused port: addra is not used in work.emuram_4(stub)" + addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); -- @suppress "Unused port: addra is not used in work.emuram_4(stub)" + dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: dina is not used in work.emuram_4(stub)" + douta : out STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: douta is not used in work.emuram_4(stub)" + clkb : in STD_LOGIC; -- @suppress "Unused port: clkb is not used in work.emuram_4(stub)" + web : in STD_LOGIC_VECTOR ( 0 to 0 ); -- @suppress "Unused port: web is not used in work.emuram_4(stub)" + addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); -- @suppress "Unused port: addrb is not used in work.emuram_4(stub)" + dinb : in STD_LOGIC_VECTOR ( 15 downto 0 ); -- @suppress "Unused port: dinb is not used in work.emuram_4(stub)" + doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ) -- @suppress "Unused port: doutb is not used in work.emuram_4(stub)" + ); + +end emuram_4; + +architecture stub of emuram_4 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[13:0],dina[15:0],douta[15:0],clkb,web[0:0],addrb[13:0],dinb[15:0],doutb[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/fifo_GBT2CR_stub.vhdl b/sources/ip_cores/stub/fifo_GBT2CR_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..90e8b2c94656dfe89ace6f65644774324861ece6 --- /dev/null +++ b/sources/ip_cores/stub/fifo_GBT2CR_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:46:41 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/fifo_GBT2CR/fifo_GBT2CR_stub.vhdl +-- Design : fifo_GBT2CR +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity fifo_GBT2CR is + Port ( + wr_clk : in STD_LOGIC; --@suppress + wr_rst : in STD_LOGIC; --@suppress + rd_clk : in STD_LOGIC; --@suppress + rd_rst : in STD_LOGIC; --@suppress + din : in STD_LOGIC_VECTOR ( 119 downto 0 ); --@suppress + wr_en : in STD_LOGIC; --@suppress + rd_en : in STD_LOGIC; --@suppress + dout : out STD_LOGIC_VECTOR ( 119 downto 0 ); --@suppress + full : out STD_LOGIC; --@suppress + empty : out STD_LOGIC; --@suppress + prog_empty : out STD_LOGIC --@suppress + ); + +end fifo_GBT2CR; + +architecture stub of fifo_GBT2CR is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "wr_clk,wr_rst,rd_clk,rd_rst,din[119:0],wr_en,rd_en,dout[119:0],full,empty,prog_empty"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/fifo_generator_fe_stub.vhdl b/sources/ip_cores/stub/fifo_generator_fe_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..5557b36f66e3b526f424a17a933ab6a39daf9877 --- /dev/null +++ b/sources/ip_cores/stub/fifo_generator_fe_stub.vhdl @@ -0,0 +1,23 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +entity fifo_generator_fe IS + PORT ( + rst : IN STD_LOGIC; --@suppress + wr_clk : IN STD_LOGIC; --@suppress + rd_clk : IN STD_LOGIC; --@suppress + din : IN STD_LOGIC_VECTOR(35 DOWNTO 0); --@suppress + wr_en : IN STD_LOGIC; --@suppress + rd_en : IN STD_LOGIC; --@suppress + dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0); --@suppress + full : OUT STD_LOGIC; --@suppress + empty : OUT STD_LOGIC; --@suppress + prog_full : OUT STD_LOGIC; --@suppress + prog_empty : OUT STD_LOGIC; --@suppress + wr_rst_busy : OUT STD_LOGIC; --@suppress + rd_rst_busy : OUT STD_LOGIC --@suppress + ); +END fifo_generator_fe; + +architecture stub of fifo_generator_fe is +begin +end; diff --git a/sources/ip_cores/stub/fifo_generator_felix_stub.vhdl b/sources/ip_cores/stub/fifo_generator_felix_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..609a9f579532581aef45a749291d049da35f5d1a --- /dev/null +++ b/sources/ip_cores/stub/fifo_generator_felix_stub.vhdl @@ -0,0 +1,42 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:49:58 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/fifo_generator_felix/fifo_generator_felix_stub.vhdl +-- Design : fifo_generator_felix +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity fifo_generator_felix is + Port ( + rst : in STD_LOGIC; --@suppress + wr_clk : in STD_LOGIC; --@suppress + rd_clk : in STD_LOGIC; --@suppress + din : in STD_LOGIC_VECTOR ( 227 downto 0 );--@suppress + wr_en : in STD_LOGIC;--@suppress + rd_en : in STD_LOGIC;--@suppress + dout : out STD_LOGIC_VECTOR ( 227 downto 0 );--@suppress + full : out STD_LOGIC;--@suppress + empty : out STD_LOGIC;--@suppress + prog_full : out STD_LOGIC;--@suppress + prog_empty : out STD_LOGIC;--@suppress + wr_rst_busy : out STD_LOGIC;--@suppress + rd_rst_busy : out STD_LOGIC--@suppress + ); + +end fifo_generator_felix; + +architecture stub of fifo_generator_felix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[227:0],wr_en,rd_en,dout[227:0],full,empty,prog_full,prog_empty,wr_rst_busy,rd_rst_busy"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/fmemuram_stub.vhdl b/sources/ip_cores/stub/fmemuram_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..72fda93efdf111176fadd242705406bac58bdecf --- /dev/null +++ b/sources/ip_cores/stub/fmemuram_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:46:39 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/fmemuram/fmemuram_stub.vhdl +-- Design : fmemuram +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity fmemuram is + Port ( + clka : in STD_LOGIC;--@suppress + wea : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + addra : in STD_LOGIC_VECTOR ( 12 downto 0 );--@suppress + dina : in STD_LOGIC_VECTOR ( 35 downto 0 );--@suppress + douta : out STD_LOGIC_VECTOR ( 35 downto 0 );--@suppress + clkb : in STD_LOGIC;--@suppress + enb : in STD_LOGIC;--@suppress + web : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );--@suppress + dinb : in STD_LOGIC_VECTOR ( 35 downto 0 );--@suppress + doutb : out STD_LOGIC_VECTOR ( 35 downto 0 )--@suppress + ); + +end fmemuram; + +architecture stub of fmemuram is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[12:0],dina[35:0],douta[35:0],clkb,enb,web[0:0],addrb[12:0],dinb[35:0],doutb[35:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/gtwizard_CPLL_4p8g_V7_stub.vhdl b/sources/ip_cores/stub/gtwizard_CPLL_4p8g_V7_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..e4d9c8417bf0b9506f1a603bfacae50e844c8ee7 --- /dev/null +++ b/sources/ip_cores/stub/gtwizard_CPLL_4p8g_V7_stub.vhdl @@ -0,0 +1,83 @@ +-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 +-- Date : Mon Mar 9 16:45:10 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX709_FELIX/FLX709_FELIX.srcs/sources_1/ip/gtwizard_CPLL_4p8g_V7/gtwizard_CPLL_4p8g_V7_stub.vhdl +-- Design : gtwizard_CPLL_4p8g_V7 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7vx690tffg1761-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity gtwizard_CPLL_4p8g_V7 is + Port ( + SYSCLK_IN : in STD_LOGIC; --@suppress + SOFT_RESET_TX_IN : in STD_LOGIC; --@suppress + SOFT_RESET_RX_IN : in STD_LOGIC; --@suppress + DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC; --@suppress + GT0_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT0_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT0_DATA_VALID_IN : in STD_LOGIC; --@suppress + gt0_cpllfbclklost_out : out STD_LOGIC; --@suppress + gt0_cplllock_out : out STD_LOGIC; --@suppress + gt0_cplllockdetclk_in : in STD_LOGIC; --@suppress + gt0_cpllreset_in : in STD_LOGIC; --@suppress + gt0_gtrefclk0_in : in STD_LOGIC; --@suppress + gt0_gtrefclk1_in : in STD_LOGIC; --@suppress + gt0_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); --@suppress + gt0_drpclk_in : in STD_LOGIC; --@suppress + gt0_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt0_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt0_drpen_in : in STD_LOGIC; --@suppress + gt0_drprdy_out : out STD_LOGIC; --@suppress + gt0_drpwe_in : in STD_LOGIC; --@suppress + gt0_loopback_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + gt0_eyescanreset_in : in STD_LOGIC; --@suppress + gt0_rxuserrdy_in : in STD_LOGIC; --@suppress + gt0_eyescandataerror_out : out STD_LOGIC; --@suppress + gt0_eyescantrigger_in : in STD_LOGIC; --@suppress + gt0_rxcdrhold_in : in STD_LOGIC; --@suppress + gt0_rxslide_in : in STD_LOGIC; --@suppress + gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 ); --@suppress + gt0_rxusrclk_in : in STD_LOGIC; --@suppress + gt0_rxusrclk2_in : in STD_LOGIC; --@suppress + gt0_rxdata_out : out STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + gt0_gthrxn_in : in STD_LOGIC; --@suppress + gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 ); --@suppress + gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + gt0_rxoutclk_out : out STD_LOGIC; --@suppress + gt0_rxoutclkfabric_out : out STD_LOGIC; --@suppress + gt0_gtrxreset_in : in STD_LOGIC; --@suppress + gt0_rxpolarity_in : in STD_LOGIC; --@suppress + gt0_gthrxp_in : in STD_LOGIC; --@suppress + gt0_rxresetdone_out : out STD_LOGIC; --@suppress + gt0_gttxreset_in : in STD_LOGIC; --@suppress + gt0_txuserrdy_in : in STD_LOGIC; --@suppress + gt0_txusrclk_in : in STD_LOGIC; --@suppress + gt0_txusrclk2_in : in STD_LOGIC; --@suppress + gt0_txdata_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + gt0_gthtxn_out : out STD_LOGIC; --@suppress + gt0_gthtxp_out : out STD_LOGIC; --@suppress + gt0_txoutclk_out : out STD_LOGIC; --@suppress + gt0_txoutclkfabric_out : out STD_LOGIC; --@suppress + gt0_txoutclkpcs_out : out STD_LOGIC; --@suppress + gt0_txresetdone_out : out STD_LOGIC; --@suppress + gt0_txpolarity_in : in STD_LOGIC; --@suppress + GT0_QPLLOUTCLK_IN : in STD_LOGIC; --@suppress + GT0_QPLLOUTREFCLK_IN : in STD_LOGIC --@suppress + ); + +end gtwizard_CPLL_4p8g_V7; + +architecture stub of gtwizard_CPLL_4p8g_V7 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "SYSCLK_IN,SOFT_RESET_TX_IN,SOFT_RESET_RX_IN,DONT_RESET_ON_DATA_ERROR_IN,GT0_TX_FSM_RESET_DONE_OUT,GT0_RX_FSM_RESET_DONE_OUT,GT0_DATA_VALID_IN,gt0_cpllfbclklost_out,gt0_cplllock_out,gt0_cplllockdetclk_in,gt0_cpllreset_in,gt0_gtrefclk0_in,gt0_gtrefclk1_in,gt0_drpaddr_in[8:0],gt0_drpclk_in,gt0_drpdi_in[15:0],gt0_drpdo_out[15:0],gt0_drpen_in,gt0_drprdy_out,gt0_drpwe_in,gt0_loopback_in[2:0],gt0_eyescanreset_in,gt0_rxuserrdy_in,gt0_eyescandataerror_out,gt0_eyescantrigger_in,gt0_rxcdrhold_in,gt0_rxslide_in,gt0_dmonitorout_out[14:0],gt0_rxusrclk_in,gt0_rxusrclk2_in,gt0_rxdata_out[19:0],gt0_gthrxn_in,gt0_rxmonitorout_out[6:0],gt0_rxmonitorsel_in[1:0],gt0_rxoutclk_out,gt0_rxoutclkfabric_out,gt0_gtrxreset_in,gt0_rxpolarity_in,gt0_gthrxp_in,gt0_rxresetdone_out,gt0_gttxreset_in,gt0_txuserrdy_in,gt0_txusrclk_in,gt0_txusrclk2_in,gt0_txdata_in[19:0],gt0_gthtxn_out,gt0_gthtxp_out,gt0_txoutclk_out,gt0_txoutclkfabric_out,gt0_txoutclkpcs_out,gt0_txresetdone_out,gt0_txpolarity_in,GT0_QPLLOUTCLK_IN,GT0_QPLLOUTREFCLK_IN"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "gtwizard_CPLL_4p8g_V7,gtwizard_v3_6_9,{protocol_file=Start_from_scratch}"; +begin +end; diff --git a/sources/ip_cores/stub/gtwizard_QPLL_4p8g_V7_stub.vhdl b/sources/ip_cores/stub/gtwizard_QPLL_4p8g_V7_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..75274faa46327afab913dc2599b9495e3d216b71 --- /dev/null +++ b/sources/ip_cores/stub/gtwizard_QPLL_4p8g_V7_stub.vhdl @@ -0,0 +1,210 @@ +-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018 +-- Date : Mon Mar 9 16:46:01 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX709_FELIX/FLX709_FELIX.srcs/sources_1/ip/gtwizard_QPLL_4p8g_V7/gtwizard_QPLL_4p8g_V7_stub.vhdl +-- Design : gtwizard_QPLL_4p8g_V7 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7vx690tffg1761-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity gtwizard_QPLL_4p8g_V7 is + Port ( + SYSCLK_IN : in STD_LOGIC; --@suppress + SOFT_RESET_TX_IN : in STD_LOGIC; --@suppress + SOFT_RESET_RX_IN : in STD_LOGIC; --@suppress + DONT_RESET_ON_DATA_ERROR_IN : in STD_LOGIC; --@suppress + GT0_DRP_BUSY_OUT : out STD_LOGIC; --@suppress + GT0_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT0_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT0_DATA_VALID_IN : in STD_LOGIC; --@suppress + GT1_DRP_BUSY_OUT : out STD_LOGIC; --@suppress + GT1_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT1_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT1_DATA_VALID_IN : in STD_LOGIC; --@suppress + GT2_DRP_BUSY_OUT : out STD_LOGIC; --@suppress + GT2_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT2_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT2_DATA_VALID_IN : in STD_LOGIC; --@suppress + GT3_DRP_BUSY_OUT : out STD_LOGIC; --@suppress + GT3_TX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT3_RX_FSM_RESET_DONE_OUT : out STD_LOGIC; --@suppress + GT3_DATA_VALID_IN : in STD_LOGIC; --@suppress + gt0_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); --@suppress + gt0_drpclk_in : in STD_LOGIC; --@suppress + gt0_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt0_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt0_drpen_in : in STD_LOGIC; --@suppress + gt0_drprdy_out : out STD_LOGIC; --@suppress + gt0_drpwe_in : in STD_LOGIC; --@suppress + gt0_loopback_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + gt0_eyescanreset_in : in STD_LOGIC; --@suppress + gt0_rxuserrdy_in : in STD_LOGIC; --@suppress + gt0_eyescandataerror_out : out STD_LOGIC; --@suppress + gt0_eyescantrigger_in : in STD_LOGIC; --@suppress + gt0_rxcdrhold_in : in STD_LOGIC; --@suppress + gt0_rxslide_in : in STD_LOGIC; --@suppress + gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 ); --@suppress + gt0_rxusrclk_in : in STD_LOGIC; --@suppress + gt0_rxusrclk2_in : in STD_LOGIC; --@suppress + gt0_rxdata_out : out STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + gt0_gthrxn_in : in STD_LOGIC; --@suppress + gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 ); --@suppress + gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + gt0_rxoutclk_out : out STD_LOGIC; --@suppress + gt0_rxoutclkfabric_out : out STD_LOGIC; --@suppress + gt0_gtrxreset_in : in STD_LOGIC; --@suppress + gt0_rxpolarity_in : in STD_LOGIC; --@suppress + gt0_gthrxp_in : in STD_LOGIC; --@suppress + gt0_rxresetdone_out : out STD_LOGIC; --@suppress + gt0_gttxreset_in : in STD_LOGIC; --@suppress + gt0_txuserrdy_in : in STD_LOGIC; --@suppress + gt0_txusrclk_in : in STD_LOGIC; --@suppress + gt0_txusrclk2_in : in STD_LOGIC; --@suppress + gt0_txdata_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + gt0_gthtxn_out : out STD_LOGIC; --@suppress + gt0_gthtxp_out : out STD_LOGIC; --@suppress + gt0_txoutclk_out : out STD_LOGIC; --@suppress + gt0_txoutclkfabric_out : out STD_LOGIC; --@suppress + gt0_txoutclkpcs_out : out STD_LOGIC; --@suppress + gt0_txresetdone_out : out STD_LOGIC; --@suppress + gt0_txpolarity_in : in STD_LOGIC; --@suppress + gt1_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); --@suppress + gt1_drpclk_in : in STD_LOGIC; --@suppress + gt1_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt1_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt1_drpen_in : in STD_LOGIC; --@suppress + gt1_drprdy_out : out STD_LOGIC; --@suppress + gt1_drpwe_in : in STD_LOGIC; --@suppress + gt1_loopback_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + gt1_eyescanreset_in : in STD_LOGIC; --@suppress + gt1_rxuserrdy_in : in STD_LOGIC; --@suppress + gt1_eyescandataerror_out : out STD_LOGIC; --@suppress + gt1_eyescantrigger_in : in STD_LOGIC; --@suppress + gt1_rxcdrhold_in : in STD_LOGIC; --@suppress + gt1_rxslide_in : in STD_LOGIC; --@suppress + gt1_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 ); --@suppress + gt1_rxusrclk_in : in STD_LOGIC; --@suppress + gt1_rxusrclk2_in : in STD_LOGIC; --@suppress + gt1_rxdata_out : out STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + gt1_gthrxn_in : in STD_LOGIC; --@suppress + gt1_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 ); --@suppress + gt1_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + gt1_rxoutclk_out : out STD_LOGIC; --@suppress + gt1_rxoutclkfabric_out : out STD_LOGIC; --@suppress + gt1_gtrxreset_in : in STD_LOGIC; --@suppress + gt1_rxpolarity_in : in STD_LOGIC; --@suppress + gt1_gthrxp_in : in STD_LOGIC; --@suppress + gt1_rxresetdone_out : out STD_LOGIC; --@suppress + gt1_gttxreset_in : in STD_LOGIC; --@suppress + gt1_txuserrdy_in : in STD_LOGIC; --@suppress + gt1_txusrclk_in : in STD_LOGIC; --@suppress + gt1_txusrclk2_in : in STD_LOGIC; --@suppress + gt1_txdata_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + gt1_gthtxn_out : out STD_LOGIC; --@suppress + gt1_gthtxp_out : out STD_LOGIC; --@suppress + gt1_txoutclk_out : out STD_LOGIC; --@suppress + gt1_txoutclkfabric_out : out STD_LOGIC; --@suppress + gt1_txoutclkpcs_out : out STD_LOGIC; --@suppress + gt1_txresetdone_out : out STD_LOGIC; --@suppress + gt1_txpolarity_in : in STD_LOGIC; --@suppress + gt2_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); --@suppress + gt2_drpclk_in : in STD_LOGIC; --@suppress + gt2_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt2_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt2_drpen_in : in STD_LOGIC; --@suppress + gt2_drprdy_out : out STD_LOGIC; --@suppress + gt2_drpwe_in : in STD_LOGIC; --@suppress + gt2_loopback_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + gt2_eyescanreset_in : in STD_LOGIC; --@suppress + gt2_rxuserrdy_in : in STD_LOGIC; --@suppress + gt2_eyescandataerror_out : out STD_LOGIC; --@suppress + gt2_eyescantrigger_in : in STD_LOGIC; --@suppress + gt2_rxcdrhold_in : in STD_LOGIC; --@suppress + gt2_rxslide_in : in STD_LOGIC; --@suppress + gt2_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 ); --@suppress + gt2_rxusrclk_in : in STD_LOGIC; --@suppress + gt2_rxusrclk2_in : in STD_LOGIC; --@suppress + gt2_rxdata_out : out STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + gt2_gthrxn_in : in STD_LOGIC; --@suppress + gt2_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 ); --@suppress + gt2_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + gt2_rxoutclk_out : out STD_LOGIC; --@suppress + gt2_rxoutclkfabric_out : out STD_LOGIC; --@suppress + gt2_gtrxreset_in : in STD_LOGIC; --@suppress + gt2_rxpolarity_in : in STD_LOGIC; --@suppress + gt2_gthrxp_in : in STD_LOGIC; --@suppress + gt2_rxresetdone_out : out STD_LOGIC; --@suppress + gt2_gttxreset_in : in STD_LOGIC; --@suppress + gt2_txuserrdy_in : in STD_LOGIC; --@suppress + gt2_txusrclk_in : in STD_LOGIC; --@suppress + gt2_txusrclk2_in : in STD_LOGIC; --@suppress + gt2_txdata_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + gt2_gthtxn_out : out STD_LOGIC; --@suppress + gt2_gthtxp_out : out STD_LOGIC; --@suppress + gt2_txoutclk_out : out STD_LOGIC; --@suppress + gt2_txoutclkfabric_out : out STD_LOGIC; --@suppress + gt2_txoutclkpcs_out : out STD_LOGIC; --@suppress + gt2_txresetdone_out : out STD_LOGIC; --@suppress + gt2_txpolarity_in : in STD_LOGIC; --@suppress + gt3_drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); --@suppress + gt3_drpclk_in : in STD_LOGIC; --@suppress + gt3_drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt3_drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + gt3_drpen_in : in STD_LOGIC; --@suppress + gt3_drprdy_out : out STD_LOGIC; --@suppress + gt3_drpwe_in : in STD_LOGIC; --@suppress + gt3_loopback_in : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + gt3_eyescanreset_in : in STD_LOGIC; --@suppress + gt3_rxuserrdy_in : in STD_LOGIC; --@suppress + gt3_eyescandataerror_out : out STD_LOGIC; --@suppress + gt3_eyescantrigger_in : in STD_LOGIC; --@suppress + gt3_rxcdrhold_in : in STD_LOGIC; --@suppress + gt3_rxslide_in : in STD_LOGIC; --@suppress + gt3_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 ); --@suppress + gt3_rxusrclk_in : in STD_LOGIC; --@suppress + gt3_rxusrclk2_in : in STD_LOGIC; --@suppress + gt3_rxdata_out : out STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + gt3_gthrxn_in : in STD_LOGIC; --@suppress + gt3_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 ); --@suppress + gt3_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + gt3_rxoutclk_out : out STD_LOGIC; --@suppress + gt3_rxoutclkfabric_out : out STD_LOGIC; --@suppress + gt3_gtrxreset_in : in STD_LOGIC; --@suppress + gt3_rxpolarity_in : in STD_LOGIC; --@suppress + gt3_gthrxp_in : in STD_LOGIC; --@suppress + gt3_rxresetdone_out : out STD_LOGIC; --@suppress + gt3_gttxreset_in : in STD_LOGIC; --@suppress + gt3_txuserrdy_in : in STD_LOGIC; --@suppress + gt3_txusrclk_in : in STD_LOGIC; --@suppress + gt3_txusrclk2_in : in STD_LOGIC; --@suppress + gt3_txdata_in : in STD_LOGIC_VECTOR ( 19 downto 0 ); --@suppress + gt3_gthtxn_out : out STD_LOGIC; --@suppress + gt3_gthtxp_out : out STD_LOGIC; --@suppress + gt3_txoutclk_out : out STD_LOGIC; --@suppress + gt3_txoutclkfabric_out : out STD_LOGIC; --@suppress + gt3_txoutclkpcs_out : out STD_LOGIC; --@suppress + gt3_txresetdone_out : out STD_LOGIC; --@suppress + gt3_txpolarity_in : in STD_LOGIC; --@suppress + GT0_QPLLLOCK_IN : in STD_LOGIC; --@suppress + GT0_QPLLREFCLKLOST_IN : in STD_LOGIC; --@suppress + GT0_QPLLRESET_OUT : out STD_LOGIC; --@suppress + GT0_QPLLOUTCLK_IN : in STD_LOGIC; --@suppress + GT0_QPLLOUTREFCLK_IN : in STD_LOGIC --@suppress + ); + +end gtwizard_QPLL_4p8g_V7; + +architecture stub of gtwizard_QPLL_4p8g_V7 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "SYSCLK_IN,SOFT_RESET_TX_IN,SOFT_RESET_RX_IN,DONT_RESET_ON_DATA_ERROR_IN,GT0_DRP_BUSY_OUT,GT0_TX_FSM_RESET_DONE_OUT,GT0_RX_FSM_RESET_DONE_OUT,GT0_DATA_VALID_IN,GT1_DRP_BUSY_OUT,GT1_TX_FSM_RESET_DONE_OUT,GT1_RX_FSM_RESET_DONE_OUT,GT1_DATA_VALID_IN,GT2_DRP_BUSY_OUT,GT2_TX_FSM_RESET_DONE_OUT,GT2_RX_FSM_RESET_DONE_OUT,GT2_DATA_VALID_IN,GT3_DRP_BUSY_OUT,GT3_TX_FSM_RESET_DONE_OUT,GT3_RX_FSM_RESET_DONE_OUT,GT3_DATA_VALID_IN,gt0_drpaddr_in[8:0],gt0_drpclk_in,gt0_drpdi_in[15:0],gt0_drpdo_out[15:0],gt0_drpen_in,gt0_drprdy_out,gt0_drpwe_in,gt0_loopback_in[2:0],gt0_eyescanreset_in,gt0_rxuserrdy_in,gt0_eyescandataerror_out,gt0_eyescantrigger_in,gt0_rxcdrhold_in,gt0_rxslide_in,gt0_dmonitorout_out[14:0],gt0_rxusrclk_in,gt0_rxusrclk2_in,gt0_rxdata_out[19:0],gt0_gthrxn_in,gt0_rxmonitorout_out[6:0],gt0_rxmonitorsel_in[1:0],gt0_rxoutclk_out,gt0_rxoutclkfabric_out,gt0_gtrxreset_in,gt0_rxpolarity_in,gt0_gthrxp_in,gt0_rxresetdone_out,gt0_gttxreset_in,gt0_txuserrdy_in,gt0_txusrclk_in,gt0_txusrclk2_in,gt0_txdata_in[19:0],gt0_gthtxn_out,gt0_gthtxp_out,gt0_txoutclk_out,gt0_txoutclkfabric_out,gt0_txoutclkpcs_out,gt0_txresetdone_out,gt0_txpolarity_in,gt1_drpaddr_in[8:0],gt1_drpclk_in,gt1_drpdi_in[15:0],gt1_drpdo_out[15:0],gt1_drpen_in,gt1_drprdy_out,gt1_drpwe_in,gt1_loopback_in[2:0],gt1_eyescanreset_in,gt1_rxuserrdy_in,gt1_eyescandataerror_out,gt1_eyescantrigger_in,gt1_rxcdrhold_in,gt1_rxslide_in,gt1_dmonitorout_out[14:0],gt1_rxusrclk_in,gt1_rxusrclk2_in,gt1_rxdata_out[19:0],gt1_gthrxn_in,gt1_rxmonitorout_out[6:0],gt1_rxmonitorsel_in[1:0],gt1_rxoutclk_out,gt1_rxoutclkfabric_out,gt1_gtrxreset_in,gt1_rxpolarity_in,gt1_gthrxp_in,gt1_rxresetdone_out,gt1_gttxreset_in,gt1_txuserrdy_in,gt1_txusrclk_in,gt1_txusrclk2_in,gt1_txdata_in[19:0],gt1_gthtxn_out,gt1_gthtxp_out,gt1_txoutclk_out,gt1_txoutclkfabric_out,gt1_txoutclkpcs_out,gt1_txresetdone_out,gt1_txpolarity_in,gt2_drpaddr_in[8:0],gt2_drpclk_in,gt2_drpdi_in[15:0],gt2_drpdo_out[15:0],gt2_drpen_in,gt2_drprdy_out,gt2_drpwe_in,gt2_loopback_in[2:0],gt2_eyescanreset_in,gt2_rxuserrdy_in,gt2_eyescandataerror_out,gt2_eyescantrigger_in,gt2_rxcdrhold_in,gt2_rxslide_in,gt2_dmonitorout_out[14:0],gt2_rxusrclk_in,gt2_rxusrclk2_in,gt2_rxdata_out[19:0],gt2_gthrxn_in,gt2_rxmonitorout_out[6:0],gt2_rxmonitorsel_in[1:0],gt2_rxoutclk_out,gt2_rxoutclkfabric_out,gt2_gtrxreset_in,gt2_rxpolarity_in,gt2_gthrxp_in,gt2_rxresetdone_out,gt2_gttxreset_in,gt2_txuserrdy_in,gt2_txusrclk_in,gt2_txusrclk2_in,gt2_txdata_in[19:0],gt2_gthtxn_out,gt2_gthtxp_out,gt2_txoutclk_out,gt2_txoutclkfabric_out,gt2_txoutclkpcs_out,gt2_txresetdone_out,gt2_txpolarity_in,gt3_drpaddr_in[8:0],gt3_drpclk_in,gt3_drpdi_in[15:0],gt3_drpdo_out[15:0],gt3_drpen_in,gt3_drprdy_out,gt3_drpwe_in,gt3_loopback_in[2:0],gt3_eyescanreset_in,gt3_rxuserrdy_in,gt3_eyescandataerror_out,gt3_eyescantrigger_in,gt3_rxcdrhold_in,gt3_rxslide_in,gt3_dmonitorout_out[14:0],gt3_rxusrclk_in,gt3_rxusrclk2_in,gt3_rxdata_out[19:0],gt3_gthrxn_in,gt3_rxmonitorout_out[6:0],gt3_rxmonitorsel_in[1:0],gt3_rxoutclk_out,gt3_rxoutclkfabric_out,gt3_gtrxreset_in,gt3_rxpolarity_in,gt3_gthrxp_in,gt3_rxresetdone_out,gt3_gttxreset_in,gt3_txuserrdy_in,gt3_txusrclk_in,gt3_txusrclk2_in,gt3_txdata_in[19:0],gt3_gthtxn_out,gt3_gthtxp_out,gt3_txoutclk_out,gt3_txoutclkfabric_out,gt3_txoutclkpcs_out,gt3_txresetdone_out,gt3_txpolarity_in,GT0_QPLLLOCK_IN,GT0_QPLLREFCLKLOST_IN,GT0_QPLLRESET_OUT,GT0_QPLLOUTCLK_IN,GT0_QPLLOUTREFCLK_IN"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "gtwizard_QPLL_4p8g_V7,gtwizard_v3_6_9,{protocol_file=Start_from_scratch}"; +begin +end; diff --git a/sources/ip_cores/stub/gtwizard_fullmode_txcpll_rxqpll_ku_stub.vhdl b/sources/ip_cores/stub/gtwizard_fullmode_txcpll_rxqpll_ku_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..3db732899ffccbed7a9cecca47e5a35899400813 --- /dev/null +++ b/sources/ip_cores/stub/gtwizard_fullmode_txcpll_rxqpll_ku_stub.vhdl @@ -0,0 +1,83 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:44:51 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/gtwizard_fullmode_txcpll_rxqpll_ku/gtwizard_fullmode_txcpll_rxqpll_ku_stub.vhdl +-- Design : gtwizard_fullmode_txcpll_rxqpll_ku +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity gtwizard_fullmode_txcpll_rxqpll_ku is + Port ( + gtwiz_userclk_tx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_userclk_rx_active_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_buffbypass_tx_reset_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_buffbypass_tx_start_user_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_buffbypass_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_buffbypass_tx_error_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_clk_freerun_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_all_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_tx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_tx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_rx_pll_and_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_rx_datapath_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_rx_cdr_stable_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_tx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_reset_rx_done_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + gtwiz_userdata_tx_in : in STD_LOGIC_VECTOR ( 79 downto 0 );--@suppress + gtwiz_userdata_rx_out : out STD_LOGIC_VECTOR ( 127 downto 0 );--@suppress + gtrefclk01_in : in STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );--@suppress + cplllockdetclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + cpllreset_in : in STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + drpclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + gthrxn_in : in STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + gthrxp_in : in STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + gtrefclk0_in : in STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + rx8b10ben_in : in STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + rxcommadeten_in : in STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + rxmcommaalignen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + rxpcommaalignen_in : in STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + rxusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + rxusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + txusrclk_in : in STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + txusrclk2_in : in STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + cpllfbclklost_out : out STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + cplllock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + gthtxn_out : out STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + gthtxp_out : out STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + gtpowergood_out : out STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + rxbyteisaligned_out : out STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + rxbyterealign_out : out STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + rxcdrlock_out : out STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + rxcommadet_out : out STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + rxctrl0_out : out STD_LOGIC_VECTOR ( 63 downto 0 );--@suppress + rxctrl1_out : out STD_LOGIC_VECTOR ( 63 downto 0 );--@suppress + rxctrl2_out : out STD_LOGIC_VECTOR ( 31 downto 0 );--@suppress + rxctrl3_out : out STD_LOGIC_VECTOR ( 31 downto 0 );--@suppress + rxoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + rxpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + rxresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + txoutclk_out : out STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + txpmaresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + txresetdone_out : out STD_LOGIC_VECTOR ( 3 downto 0 )--@suppress + ); + +end gtwizard_fullmode_txcpll_rxqpll_ku; + +architecture stub of gtwizard_fullmode_txcpll_rxqpll_ku is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "gtwiz_userclk_tx_active_in[0:0],gtwiz_userclk_rx_active_in[0:0],gtwiz_buffbypass_tx_reset_in[0:0],gtwiz_buffbypass_tx_start_user_in[0:0],gtwiz_buffbypass_tx_done_out[0:0],gtwiz_buffbypass_tx_error_out[0:0],gtwiz_reset_clk_freerun_in[0:0],gtwiz_reset_all_in[0:0],gtwiz_reset_tx_pll_and_datapath_in[0:0],gtwiz_reset_tx_datapath_in[0:0],gtwiz_reset_rx_pll_and_datapath_in[0:0],gtwiz_reset_rx_datapath_in[0:0],gtwiz_reset_rx_cdr_stable_out[0:0],gtwiz_reset_tx_done_out[0:0],gtwiz_reset_rx_done_out[0:0],gtwiz_userdata_tx_in[79:0],gtwiz_userdata_rx_out[127:0],gtrefclk01_in[0:0],qpll1lock_out[0:0],qpll1outclk_out[0:0],qpll1outrefclk_out[0:0],cplllockdetclk_in[3:0],cpllreset_in[3:0],drpclk_in[3:0],gthrxn_in[3:0],gthrxp_in[3:0],gtrefclk0_in[3:0],rx8b10ben_in[3:0],rxcommadeten_in[3:0],rxmcommaalignen_in[3:0],rxpcommaalignen_in[3:0],rxusrclk_in[3:0],rxusrclk2_in[3:0],txusrclk_in[3:0],txusrclk2_in[3:0],cpllfbclklost_out[3:0],cplllock_out[3:0],gthtxn_out[3:0],gthtxp_out[3:0],gtpowergood_out[3:0],rxbyteisaligned_out[3:0],rxbyterealign_out[3:0],rxcdrlock_out[3:0],rxcommadet_out[3:0],rxctrl0_out[63:0],rxctrl1_out[63:0],rxctrl2_out[31:0],rxctrl3_out[31:0],rxoutclk_out[3:0],rxpmaresetdone_out[3:0],rxresetdone_out[3:0],txoutclk_out[3:0],txpmaresetdone_out[3:0],txresetdone_out[3:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "gtwizard_fullmode_txcpll_rxqpll_ku_gtwizard_top,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/gtwizard_fullmode_txcpll_rxqpll_vup_stub.vhdl b/sources/ip_cores/stub/gtwizard_fullmode_txcpll_rxqpll_vup_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..05b39e811210ae79c28cb14d45da09b4a7a2faf4 --- /dev/null +++ b/sources/ip_cores/stub/gtwizard_fullmode_txcpll_rxqpll_vup_stub.vhdl @@ -0,0 +1,80 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:44:51 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/gtwizard_fullmode_txcpll_rxqpll_ku/gtwizard_fullmode_txcpll_rxqpll_ku_stub.vhdl +-- Design : gtwizard_fullmode_txcpll_rxqpll_ku +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity gtwizard_fullmode_txcpll_rxqpll_vup is + PORT ( + gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_userclk_tx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_userclk_rx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_buffbypass_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_buffbypass_tx_start_user_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_buffbypass_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_buffbypass_tx_error_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(79 DOWNTO 0); --@suppress + gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(127 DOWNTO 0); --@suppress + gtrefclk01_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + qpll1lock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + qpll1outclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + qpll1outrefclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); --@suppress + cplllockdetclk_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + cpllreset_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + drpclk_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + gtrefclk0_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + gtyrxn_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + gtyrxp_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + rx8b10ben_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + rxcommadeten_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + rxmcommaalignen_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + rxpcommaalignen_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + rxusrclk_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + rxusrclk2_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + txusrclk_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + txusrclk2_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + cpllfbclklost_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + cplllock_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + gtpowergood_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + gtytxn_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + gtytxp_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + rxbyteisaligned_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + rxbyterealign_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + rxcdrlock_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + rxcommadet_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + rxctrl0_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); --@suppress + rxctrl1_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); --@suppress + rxctrl2_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --@suppress + rxctrl3_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --@suppress + rxoutclk_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + rxresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + txoutclk_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + txpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --@suppress + txresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) --@suppress + ); + +end gtwizard_fullmode_txcpll_rxqpll_vup; + +architecture stub of gtwizard_fullmode_txcpll_rxqpll_vup is + +begin +end; diff --git a/sources/ip_cores/stub/pcie3_ultrascale_7038_stub.vhdl b/sources/ip_cores/stub/pcie3_ultrascale_7038_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..55c60d4dbdb342fb559461c018cdd8e9b4338601 --- /dev/null +++ b/sources/ip_cores/stub/pcie3_ultrascale_7038_stub.vhdl @@ -0,0 +1,160 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:45:31 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/pcie3_ultrascale_7038/pcie3_ultrascale_7038_stub.vhdl +-- Design : pcie3_ultrascale_7038 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity pcie3_ultrascale_7038 is + Port ( + pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + user_clk : out STD_LOGIC; --@suppress + user_reset : out STD_LOGIC; --@suppress + user_lnk_up : out STD_LOGIC; --@suppress + s_axis_rq_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); --@suppress + s_axis_rq_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + s_axis_rq_tlast : in STD_LOGIC; --@suppress + s_axis_rq_tready : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + s_axis_rq_tuser : in STD_LOGIC_VECTOR ( 59 downto 0 ); --@suppress + s_axis_rq_tvalid : in STD_LOGIC; --@suppress + m_axis_rc_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 ); --@suppress + m_axis_rc_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + m_axis_rc_tlast : out STD_LOGIC; --@suppress + m_axis_rc_tready : in STD_LOGIC; --@suppress + m_axis_rc_tuser : out STD_LOGIC_VECTOR ( 74 downto 0 ); --@suppress + m_axis_rc_tvalid : out STD_LOGIC; --@suppress + m_axis_cq_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 ); --@suppress + m_axis_cq_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + m_axis_cq_tlast : out STD_LOGIC; --@suppress + m_axis_cq_tready : in STD_LOGIC; --@suppress + m_axis_cq_tuser : out STD_LOGIC_VECTOR ( 84 downto 0 ); --@suppress + m_axis_cq_tvalid : out STD_LOGIC; --@suppress + s_axis_cc_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); --@suppress + s_axis_cc_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + s_axis_cc_tlast : in STD_LOGIC; --@suppress + s_axis_cc_tready : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + s_axis_cc_tuser : in STD_LOGIC_VECTOR ( 32 downto 0 ); --@suppress + s_axis_cc_tvalid : in STD_LOGIC; --@suppress + pcie_rq_seq_num : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + pcie_rq_seq_num_vld : out STD_LOGIC; --@suppress + pcie_rq_tag : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + pcie_rq_tag_av : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + pcie_rq_tag_vld : out STD_LOGIC; --@suppress + pcie_tfc_nph_av : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + pcie_tfc_npd_av : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + pcie_cq_np_req : in STD_LOGIC; --@suppress + pcie_cq_np_req_count : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + cfg_phy_link_down : out STD_LOGIC; --@suppress + cfg_phy_link_status : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_negotiated_width : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_current_speed : out STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_max_payload : out STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_max_read_req : out STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_function_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + cfg_function_power_state : out STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + cfg_vf_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + cfg_vf_power_state : out STD_LOGIC_VECTOR ( 23 downto 0 ); --@suppress + cfg_link_power_state : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_mgmt_addr : in STD_LOGIC_VECTOR ( 18 downto 0 ); --@suppress + cfg_mgmt_write : in STD_LOGIC; --@suppress + cfg_mgmt_write_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + cfg_mgmt_byte_enable : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_mgmt_read : in STD_LOGIC; --@suppress + cfg_mgmt_read_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + cfg_mgmt_read_write_done : out STD_LOGIC; --@suppress + cfg_mgmt_type1_cfg_reg_access : in STD_LOGIC; --@suppress + cfg_err_cor_out : out STD_LOGIC; --@suppress + cfg_err_nonfatal_out : out STD_LOGIC; --@suppress + cfg_err_fatal_out : out STD_LOGIC; --@suppress + cfg_local_error : out STD_LOGIC; --@suppress + cfg_ltr_enable : out STD_LOGIC; --@suppress + cfg_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + cfg_rcb_status : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_dpa_substate_change : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_obff_enable : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_pl_status_change : out STD_LOGIC; --@suppress + cfg_tph_requester_enable : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_tph_st_mode : out STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + cfg_vf_tph_requester_enable : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_vf_tph_st_mode : out STD_LOGIC_VECTOR ( 23 downto 0 ); --@suppress + cfg_msg_received : out STD_LOGIC; --@suppress + cfg_msg_received_data : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_msg_received_type : out STD_LOGIC_VECTOR ( 4 downto 0 ); --@suppress + cfg_msg_transmit : in STD_LOGIC; --@suppress + cfg_msg_transmit_type : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_msg_transmit_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + cfg_msg_transmit_done : out STD_LOGIC; --@suppress + cfg_fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + cfg_fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + cfg_fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + cfg_fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_per_func_status_control : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_per_func_status_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + cfg_per_function_number : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_per_function_output_request : in STD_LOGIC; --@suppress + cfg_per_function_update_done : out STD_LOGIC; --@suppress + cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); --@suppress + cfg_power_state_change_ack : in STD_LOGIC; --@suppress + cfg_power_state_change_interrupt : out STD_LOGIC; --@suppress + cfg_err_cor_in : in STD_LOGIC; --@suppress + cfg_err_uncor_in : in STD_LOGIC; --@suppress + cfg_flr_in_process : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_flr_done : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_vf_flr_in_process : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_vf_flr_done : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_link_training_enable : in STD_LOGIC; --@suppress + cfg_interrupt_int : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_interrupt_pending : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_interrupt_sent : out STD_LOGIC; --@suppress + cfg_interrupt_msi_function_number : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_interrupt_msix_enable : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_interrupt_msix_mask : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_interrupt_msix_vf_enable : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_interrupt_msix_vf_mask : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_interrupt_msix_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + cfg_interrupt_msix_address : in STD_LOGIC_VECTOR ( 63 downto 0 ); --@suppress + cfg_interrupt_msix_int : in STD_LOGIC; --@suppress + cfg_interrupt_msix_sent : out STD_LOGIC; --@suppress + cfg_interrupt_msix_fail : out STD_LOGIC; --@suppress + cfg_hot_reset_out : out STD_LOGIC; --@suppress + cfg_config_space_enable : in STD_LOGIC; --@suppress + cfg_req_pm_transition_l23_ready : in STD_LOGIC; --@suppress + cfg_hot_reset_in : in STD_LOGIC; --@suppress + cfg_ds_port_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); --@suppress + cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_subsys_vend_id : in STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + sys_clk : in STD_LOGIC; --@suppress + sys_clk_gt : in STD_LOGIC; --@suppress + sys_reset : in STD_LOGIC; --@suppress + int_qpll1lock_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + int_qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + int_qpll1outclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + phy_rdy_out : out STD_LOGIC --@suppress + ); + +end pcie3_ultrascale_7038; + +architecture stub of pcie3_ultrascale_7038 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "pci_exp_txn[7:0],pci_exp_txp[7:0],pci_exp_rxn[7:0],pci_exp_rxp[7:0],user_clk,user_reset,user_lnk_up,s_axis_rq_tdata[255:0],s_axis_rq_tkeep[7:0],s_axis_rq_tlast,s_axis_rq_tready[3:0],s_axis_rq_tuser[59:0],s_axis_rq_tvalid,m_axis_rc_tdata[255:0],m_axis_rc_tkeep[7:0],m_axis_rc_tlast,m_axis_rc_tready,m_axis_rc_tuser[74:0],m_axis_rc_tvalid,m_axis_cq_tdata[255:0],m_axis_cq_tkeep[7:0],m_axis_cq_tlast,m_axis_cq_tready,m_axis_cq_tuser[84:0],m_axis_cq_tvalid,s_axis_cc_tdata[255:0],s_axis_cc_tkeep[7:0],s_axis_cc_tlast,s_axis_cc_tready[3:0],s_axis_cc_tuser[32:0],s_axis_cc_tvalid,pcie_rq_seq_num[3:0],pcie_rq_seq_num_vld,pcie_rq_tag[5:0],pcie_rq_tag_av[1:0],pcie_rq_tag_vld,pcie_tfc_nph_av[1:0],pcie_tfc_npd_av[1:0],pcie_cq_np_req,pcie_cq_np_req_count[5:0],cfg_phy_link_down,cfg_phy_link_status[1:0],cfg_negotiated_width[3:0],cfg_current_speed[2:0],cfg_max_payload[2:0],cfg_max_read_req[2:0],cfg_function_status[15:0],cfg_function_power_state[11:0],cfg_vf_status[15:0],cfg_vf_power_state[23:0],cfg_link_power_state[1:0],cfg_mgmt_addr[18:0],cfg_mgmt_write,cfg_mgmt_write_data[31:0],cfg_mgmt_byte_enable[3:0],cfg_mgmt_read,cfg_mgmt_read_data[31:0],cfg_mgmt_read_write_done,cfg_mgmt_type1_cfg_reg_access,cfg_err_cor_out,cfg_err_nonfatal_out,cfg_err_fatal_out,cfg_local_error,cfg_ltr_enable,cfg_ltssm_state[5:0],cfg_rcb_status[3:0],cfg_dpa_substate_change[3:0],cfg_obff_enable[1:0],cfg_pl_status_change,cfg_tph_requester_enable[3:0],cfg_tph_st_mode[11:0],cfg_vf_tph_requester_enable[7:0],cfg_vf_tph_st_mode[23:0],cfg_msg_received,cfg_msg_received_data[7:0],cfg_msg_received_type[4:0],cfg_msg_transmit,cfg_msg_transmit_type[2:0],cfg_msg_transmit_data[31:0],cfg_msg_transmit_done,cfg_fc_ph[7:0],cfg_fc_pd[11:0],cfg_fc_nph[7:0],cfg_fc_npd[11:0],cfg_fc_cplh[7:0],cfg_fc_cpld[11:0],cfg_fc_sel[2:0],cfg_per_func_status_control[2:0],cfg_per_func_status_data[15:0],cfg_per_function_number[3:0],cfg_per_function_output_request,cfg_per_function_update_done,cfg_dsn[63:0],cfg_power_state_change_ack,cfg_power_state_change_interrupt,cfg_err_cor_in,cfg_err_uncor_in,cfg_flr_in_process[3:0],cfg_flr_done[3:0],cfg_vf_flr_in_process[7:0],cfg_vf_flr_done[7:0],cfg_link_training_enable,cfg_interrupt_int[3:0],cfg_interrupt_pending[3:0],cfg_interrupt_sent,cfg_interrupt_msi_function_number[3:0],cfg_interrupt_msix_enable[3:0],cfg_interrupt_msix_mask[3:0],cfg_interrupt_msix_vf_enable[7:0],cfg_interrupt_msix_vf_mask[7:0],cfg_interrupt_msix_data[31:0],cfg_interrupt_msix_address[63:0],cfg_interrupt_msix_int,cfg_interrupt_msix_sent,cfg_interrupt_msix_fail,cfg_hot_reset_out,cfg_config_space_enable,cfg_req_pm_transition_l23_ready,cfg_hot_reset_in,cfg_ds_port_number[7:0],cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_subsys_vend_id[15:0],sys_clk,sys_clk_gt,sys_reset,int_qpll1lock_out[1:0],int_qpll1outrefclk_out[1:0],int_qpll1outclk_out[1:0],phy_rdy_out"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "pcie3_ultrascale_7038_pcie3_uscale_core_top,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/pcie3_ultrascale_7039_stub.vhdl b/sources/ip_cores/stub/pcie3_ultrascale_7039_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..c16d6387b1a1b67da33080e07f8f8c6c12a7d0ac --- /dev/null +++ b/sources/ip_cores/stub/pcie3_ultrascale_7039_stub.vhdl @@ -0,0 +1,160 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:46:32 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/pcie3_ultrascale_7039/pcie3_ultrascale_7039_stub.vhdl +-- Design : pcie3_ultrascale_7039 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity pcie3_ultrascale_7039 is + Port ( + pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + user_clk : out STD_LOGIC; --@suppress + user_reset : out STD_LOGIC; --@suppress + user_lnk_up : out STD_LOGIC; --@suppress + s_axis_rq_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); --@suppress + s_axis_rq_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + s_axis_rq_tlast : in STD_LOGIC; --@suppress + s_axis_rq_tready : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + s_axis_rq_tuser : in STD_LOGIC_VECTOR ( 59 downto 0 ); --@suppress + s_axis_rq_tvalid : in STD_LOGIC; --@suppress + m_axis_rc_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 ); --@suppress + m_axis_rc_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + m_axis_rc_tlast : out STD_LOGIC; --@suppress + m_axis_rc_tready : in STD_LOGIC; --@suppress + m_axis_rc_tuser : out STD_LOGIC_VECTOR ( 74 downto 0 ); --@suppress + m_axis_rc_tvalid : out STD_LOGIC; --@suppress + m_axis_cq_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 ); --@suppress + m_axis_cq_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + m_axis_cq_tlast : out STD_LOGIC; --@suppress + m_axis_cq_tready : in STD_LOGIC; --@suppress + m_axis_cq_tuser : out STD_LOGIC_VECTOR ( 84 downto 0 ); --@suppress + m_axis_cq_tvalid : out STD_LOGIC; --@suppress + s_axis_cc_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); --@suppress + s_axis_cc_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + s_axis_cc_tlast : in STD_LOGIC; --@suppress + s_axis_cc_tready : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + s_axis_cc_tuser : in STD_LOGIC_VECTOR ( 32 downto 0 ); --@suppress + s_axis_cc_tvalid : in STD_LOGIC; --@suppress + pcie_rq_seq_num : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + pcie_rq_seq_num_vld : out STD_LOGIC; --@suppress + pcie_rq_tag : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + pcie_rq_tag_av : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + pcie_rq_tag_vld : out STD_LOGIC; --@suppress + pcie_tfc_nph_av : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + pcie_tfc_npd_av : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + pcie_cq_np_req : in STD_LOGIC; --@suppress + pcie_cq_np_req_count : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + cfg_phy_link_down : out STD_LOGIC; --@suppress + cfg_phy_link_status : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_negotiated_width : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_current_speed : out STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_max_payload : out STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_max_read_req : out STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_function_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + cfg_function_power_state : out STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + cfg_vf_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + cfg_vf_power_state : out STD_LOGIC_VECTOR ( 23 downto 0 ); --@suppress + cfg_link_power_state : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_mgmt_addr : in STD_LOGIC_VECTOR ( 18 downto 0 ); --@suppress + cfg_mgmt_write : in STD_LOGIC; --@suppress + cfg_mgmt_write_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + cfg_mgmt_byte_enable : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_mgmt_read : in STD_LOGIC; --@suppress + cfg_mgmt_read_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + cfg_mgmt_read_write_done : out STD_LOGIC; --@suppress + cfg_mgmt_type1_cfg_reg_access : in STD_LOGIC; --@suppress + cfg_err_cor_out : out STD_LOGIC; --@suppress + cfg_err_nonfatal_out : out STD_LOGIC; --@suppress + cfg_err_fatal_out : out STD_LOGIC; --@suppress + cfg_local_error : out STD_LOGIC; --@suppress + cfg_ltr_enable : out STD_LOGIC; --@suppress + cfg_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + cfg_rcb_status : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_dpa_substate_change : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_obff_enable : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + cfg_pl_status_change : out STD_LOGIC; --@suppress + cfg_tph_requester_enable : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_tph_st_mode : out STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + cfg_vf_tph_requester_enable : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_vf_tph_st_mode : out STD_LOGIC_VECTOR ( 23 downto 0 ); --@suppress + cfg_msg_received : out STD_LOGIC; --@suppress + cfg_msg_received_data : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_msg_received_type : out STD_LOGIC_VECTOR ( 4 downto 0 ); --@suppress + cfg_msg_transmit : in STD_LOGIC; --@suppress + cfg_msg_transmit_type : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_msg_transmit_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + cfg_msg_transmit_done : out STD_LOGIC; --@suppress + cfg_fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + cfg_fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + cfg_fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 ); --@suppress + cfg_fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_per_func_status_control : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_per_func_status_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + cfg_per_function_number : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_per_function_output_request : in STD_LOGIC; --@suppress + cfg_per_function_update_done : out STD_LOGIC; --@suppress + cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); --@suppress + cfg_power_state_change_ack : in STD_LOGIC; --@suppress + cfg_power_state_change_interrupt : out STD_LOGIC; --@suppress + cfg_err_cor_in : in STD_LOGIC; --@suppress + cfg_err_uncor_in : in STD_LOGIC; --@suppress + cfg_flr_in_process : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_flr_done : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_vf_flr_in_process : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_vf_flr_done : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_link_training_enable : in STD_LOGIC; --@suppress + cfg_interrupt_int : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_interrupt_pending : in STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_interrupt_sent : out STD_LOGIC; --@suppress + cfg_interrupt_msi_function_number : in STD_LOGIC_VECTOR ( 3 downto 0 );--@suppress + cfg_interrupt_msix_enable : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_interrupt_msix_mask : out STD_LOGIC_VECTOR ( 3 downto 0 ); --@suppress + cfg_interrupt_msix_vf_enable : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_interrupt_msix_vf_mask : out STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_interrupt_msix_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); --@suppress + cfg_interrupt_msix_address : in STD_LOGIC_VECTOR ( 63 downto 0 ); --@suppress + cfg_interrupt_msix_int : in STD_LOGIC; --@suppress + cfg_interrupt_msix_sent : out STD_LOGIC; --@suppress + cfg_interrupt_msix_fail : out STD_LOGIC; --@suppress + cfg_hot_reset_out : out STD_LOGIC; --@suppress + cfg_config_space_enable : in STD_LOGIC; --@suppress + cfg_req_pm_transition_l23_ready : in STD_LOGIC; --@suppress + cfg_hot_reset_in : in STD_LOGIC; --@suppress + cfg_ds_port_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); --@suppress + cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); --@suppress + cfg_subsys_vend_id : in STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + sys_clk : in STD_LOGIC; --@suppress + sys_clk_gt : in STD_LOGIC; --@suppress + sys_reset : in STD_LOGIC; --@suppress + int_qpll1lock_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + int_qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + int_qpll1outclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); --@suppress + phy_rdy_out : out STD_LOGIC --@suppress + ); + +end pcie3_ultrascale_7039; + +architecture stub of pcie3_ultrascale_7039 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "pci_exp_txn[7:0],pci_exp_txp[7:0],pci_exp_rxn[7:0],pci_exp_rxp[7:0],user_clk,user_reset,user_lnk_up,s_axis_rq_tdata[255:0],s_axis_rq_tkeep[7:0],s_axis_rq_tlast,s_axis_rq_tready[3:0],s_axis_rq_tuser[59:0],s_axis_rq_tvalid,m_axis_rc_tdata[255:0],m_axis_rc_tkeep[7:0],m_axis_rc_tlast,m_axis_rc_tready,m_axis_rc_tuser[74:0],m_axis_rc_tvalid,m_axis_cq_tdata[255:0],m_axis_cq_tkeep[7:0],m_axis_cq_tlast,m_axis_cq_tready,m_axis_cq_tuser[84:0],m_axis_cq_tvalid,s_axis_cc_tdata[255:0],s_axis_cc_tkeep[7:0],s_axis_cc_tlast,s_axis_cc_tready[3:0],s_axis_cc_tuser[32:0],s_axis_cc_tvalid,pcie_rq_seq_num[3:0],pcie_rq_seq_num_vld,pcie_rq_tag[5:0],pcie_rq_tag_av[1:0],pcie_rq_tag_vld,pcie_tfc_nph_av[1:0],pcie_tfc_npd_av[1:0],pcie_cq_np_req,pcie_cq_np_req_count[5:0],cfg_phy_link_down,cfg_phy_link_status[1:0],cfg_negotiated_width[3:0],cfg_current_speed[2:0],cfg_max_payload[2:0],cfg_max_read_req[2:0],cfg_function_status[15:0],cfg_function_power_state[11:0],cfg_vf_status[15:0],cfg_vf_power_state[23:0],cfg_link_power_state[1:0],cfg_mgmt_addr[18:0],cfg_mgmt_write,cfg_mgmt_write_data[31:0],cfg_mgmt_byte_enable[3:0],cfg_mgmt_read,cfg_mgmt_read_data[31:0],cfg_mgmt_read_write_done,cfg_mgmt_type1_cfg_reg_access,cfg_err_cor_out,cfg_err_nonfatal_out,cfg_err_fatal_out,cfg_local_error,cfg_ltr_enable,cfg_ltssm_state[5:0],cfg_rcb_status[3:0],cfg_dpa_substate_change[3:0],cfg_obff_enable[1:0],cfg_pl_status_change,cfg_tph_requester_enable[3:0],cfg_tph_st_mode[11:0],cfg_vf_tph_requester_enable[7:0],cfg_vf_tph_st_mode[23:0],cfg_msg_received,cfg_msg_received_data[7:0],cfg_msg_received_type[4:0],cfg_msg_transmit,cfg_msg_transmit_type[2:0],cfg_msg_transmit_data[31:0],cfg_msg_transmit_done,cfg_fc_ph[7:0],cfg_fc_pd[11:0],cfg_fc_nph[7:0],cfg_fc_npd[11:0],cfg_fc_cplh[7:0],cfg_fc_cpld[11:0],cfg_fc_sel[2:0],cfg_per_func_status_control[2:0],cfg_per_func_status_data[15:0],cfg_per_function_number[3:0],cfg_per_function_output_request,cfg_per_function_update_done,cfg_dsn[63:0],cfg_power_state_change_ack,cfg_power_state_change_interrupt,cfg_err_cor_in,cfg_err_uncor_in,cfg_flr_in_process[3:0],cfg_flr_done[3:0],cfg_vf_flr_in_process[7:0],cfg_vf_flr_done[7:0],cfg_link_training_enable,cfg_interrupt_int[3:0],cfg_interrupt_pending[3:0],cfg_interrupt_sent,cfg_interrupt_msi_function_number[3:0],cfg_interrupt_msix_enable[3:0],cfg_interrupt_msix_mask[3:0],cfg_interrupt_msix_vf_enable[7:0],cfg_interrupt_msix_vf_mask[7:0],cfg_interrupt_msix_data[31:0],cfg_interrupt_msix_address[63:0],cfg_interrupt_msix_int,cfg_interrupt_msix_sent,cfg_interrupt_msix_fail,cfg_hot_reset_out,cfg_config_space_enable,cfg_req_pm_transition_l23_ready,cfg_hot_reset_in,cfg_ds_port_number[7:0],cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_subsys_vend_id[15:0],sys_clk,sys_clk_gt,sys_reset,int_qpll1lock_out[1:0],int_qpll1outrefclk_out[1:0],int_qpll1outclk_out[1:0],phy_rdy_out"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "pcie3_ultrascale_7039_pcie3_uscale_core_top,Vivado 2020.1"; +begin +end; diff --git a/sources/ip_cores/stub/rxclkgen_stub.vhdl b/sources/ip_cores/stub/rxclkgen_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..012af5ae23a2a1f65fc3c56eb373005274b0b59c --- /dev/null +++ b/sources/ip_cores/stub/rxclkgen_stub.vhdl @@ -0,0 +1,31 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:44:30 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/rxclkgen/rxclkgen_stub.vhdl +-- Design : rxclkgen +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity rxclkgen is + Port ( + clk_out1 : out STD_LOGIC; --@suppress + reset : in STD_LOGIC; --@suppress + locked : out STD_LOGIC; --@suppress + clk_in1 : in STD_LOGIC --@suppress + ); + +end rxclkgen; + +architecture stub of rxclkgen is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1"; +begin +end; diff --git a/sources/ip_cores/stub/system_management_wiz_0_stub.vhdl b/sources/ip_cores/stub/system_management_wiz_0_stub.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..5c17e2937662c0e279a5bd40a245e93d712aa3f7 --- /dev/null +++ b/sources/ip_cores/stub/system_management_wiz_0_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 +-- Date : Mon Sep 28 16:48:22 2020 +-- Host : tarfa running 64-bit CentOS Linux release 7.6.1810 (Core) +-- Command : write_vhdl -force -mode synth_stub +-- /localstore/et/franss/felix/firmware2/Projects/FLX712_FELIX/FLX712_FELIX.srcs/sources_1/ip/system_management_wiz_0/system_management_wiz_0_stub.vhdl +-- Design : system_management_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xcku115-flvf1924-2-e +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity system_management_wiz_0 is + Port ( + daddr_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); --@suppress + den_in : in STD_LOGIC; --@suppress + di_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + dwe_in : in STD_LOGIC; --@suppress + do_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); --@suppress + drdy_out : out STD_LOGIC; --@suppress + dclk_in : in STD_LOGIC; --@suppress + reset_in : in STD_LOGIC; --@suppress + busy_out : out STD_LOGIC; --@suppress + channel_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); --@suppress + eoc_out : out STD_LOGIC; --@suppress + eos_out : out STD_LOGIC; --@suppress + alarm_out : out STD_LOGIC --@suppress + ); + +end system_management_wiz_0; + +architecture stub of system_management_wiz_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "daddr_in[7:0],den_in,di_in[15:0],dwe_in,do_out[15:0],drdy_out,dclk_in,reset_in,busy_out,channel_out[5:0],eoc_out,eos_out,alarm_out"; +begin +end; diff --git a/sources/opencores/application.vhd b/sources/opencores/application.vhd index 66f7478ff6fa2b2098bbf5e09c0cf07850d3433d..304c86b1f15e5929e507b46f0431f8b9bf68d98e 100644 --- a/sources/opencores/application.vhd +++ b/sources/opencores/application.vhd @@ -55,30 +55,25 @@ -library ieee, UNISIM, work; +library ieee, UNISIM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use ieee.std_logic_1164.all; use work.pcie_package.all; entity application is - generic( - NUMBER_OF_INTERRUPTS : integer := 8; - CARD_TYPE : integer := 709; - DATA_WIDTH : integer := 512); port ( - appreg_clk : in std_logic; clk250 : in std_logic; flush_fifo : in std_logic; - fromHostFifo_dout : in std_logic_vector(511 downto 0); - fromHostFifo_empty : in std_logic; + --fromHostFifo_dout : in std_logic_vector(511 downto 0); + --fromHostFifo_empty : in std_logic; fromHostFifo_rd_clk : out std_logic; - fromHostFifo_rd_en : out std_logic; - fromHostFifo_rst : out std_logic; + --fromHostFifo_rd_en : out std_logic; + --fromHostFifo_rst : out std_logic; register_map_control : in register_map_control_type; --! contains all read/write registers that control the application. The record members are described in pcie_package.vhd reset_hard : in std_logic; - reset_soft : in std_logic; + --reset_soft : in std_logic; toHostFifo_din : out std_logic_vector(511 downto 0); toHostFifo_prog_full : in std_logic; toHostFifo_rst : out std_logic; diff --git a/sources/opencores/wupper_oc_top.vhd b/sources/opencores/wupper_oc_top.vhd index 3172d86f49f2526921afc2e0fb79f31f6cc75e08..9a1d13f5376d571eee3da1d63f271988ed0a7ffa 100644 --- a/sources/opencores/wupper_oc_top.vhd +++ b/sources/opencores/wupper_oc_top.vhd @@ -51,10 +51,10 @@ -library ieee, UNISIM, work; +library ieee, UNISIM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use ieee.std_logic_1164.all; use work.pcie_package.all; @@ -63,7 +63,6 @@ entity wupper_oc_top is NUMBER_OF_INTERRUPTS : integer := 8; NUMBER_OF_DESCRIPTORS : integer := 8; CARD_TYPE : integer := 709; - SVN_VERSION : integer := 0; BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE"; GIT_HASH : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000"; COMMIT_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE"; @@ -80,11 +79,11 @@ entity wupper_oc_top is pcie_txn : out std_logic_vector((ENDPOINTS*PCIE_LANES)-1 downto 0); pcie_txp : out std_logic_vector((ENDPOINTS*PCIE_LANES)-1 downto 0); --! PCIe link lanes sys_clk_n : in std_logic_vector(ENDPOINTS-1 downto 0); - sys_clk_p : in std_logic_vector(ENDPOINTS-1 downto 0) --! 100MHz PCIe reference clock - --sys_reset_n : in std_logic; - --SDA : inout std_logic; - --SCL : inout std_logic; - --i2cmux_rst : out std_logic + sys_clk_p : in std_logic_vector(ENDPOINTS-1 downto 0); --! 100MHz PCIe reference clock + sys_reset_n : in std_logic; + SDA : inout std_logic; + SCL : inout std_logic; + i2cmux_rst : out std_logic ); --! Active-low system reset from PCIe interface end entity wupper_oc_top; @@ -92,127 +91,147 @@ end entity wupper_oc_top; architecture structure of wupper_oc_top is signal leds_s : std_logic_vector(ENDPOINTS*8-1 downto 0); - signal pll_locked : std_logic; - signal appreg_clk : std_logic; - signal register_map_hk_monitor : register_map_hk_monitor_type; - signal register_map_gen_board_info : register_map_gen_board_info_type; - signal register_map_ttc_monitor : register_map_ttc_monitor_type; - --signal register_map_gbt_monitor : register_map_gbt_monitor_type; - signal register_map_control : register_map_control_type; --! contains all read/write registers that control the application. The record members are described in pcie_package.vhd - signal reset_soft : std_logic; - signal reset_hard : std_logic; - signal lnk_up : std_logic_vector(1 downto 0); - + signal pll_locked : std_logic; -- @suppress "signal pll_locked is never read" + signal appreg_clk : std_logic; + signal register_map_hk_monitor : register_map_hk_monitor_type; -- @suppress "signal register_map_hk_monitor is never written" + signal register_map_gen_board_info : register_map_gen_board_info_type; -- @suppress "signal register_map_gen_board_info is never written" + signal register_map_ttc_monitor : register_map_ttc_monitor_type; -- @suppress "signal register_map_ttc_monitor is never written" + signal register_map_link_monitor : register_map_link_monitor_type; -- @suppress "signal register_map_link_monitor is never written" + signal register_map_control : register_map_control_type; --! contains all read/write registers that control the application. The record members are described in pcie_package.vhd -- @suppress "signal register_map_control is never read" + signal reset_soft : std_logic; -- @suppress "signal reset_soft is never read" + signal reset_hard : std_logic; + signal lnk_up : std_logic_vector(1 downto 0); -- @suppress "signal lnk_up is never read" + signal RXUSRCLK : std_logic_vector(24*ENDPOINTS-1 downto 0); begin + + RXUSRCLK <= (others => appreg_clk); --- hk0: entity work.housekeeping_module --- generic map ( --- CARD_TYPE => CARD_TYPE --- ) --- port map( --- MMCM_Locked_in => pll_locked, --- MMCM_OscSelect_in => '0', --- SCL => SCL, --- SDA => SDA, --- SI5345_A => open, --- SI5345_INSEL => open, --- SI5345_OE => open, --- SI5345_RSTN => open, --- SI5345_SEL => open, --- SI5345_nLOL => open, --- appreg_clk => appreg_clk, --- emcclk => '0', --- flash_SEL => '0', --- flash_a => open, --- flash_a_msb => open, --- flash_adv => open, --- flash_cclk => open, --- flash_ce => open, --- flash_d => open, --- flash_re => open, --- flash_we => open, --- i2cmux_rst => i2cmux_rst, --- TACH => '0', --- clk10_xtal => '0', --- clk40_xtal => appreg_clk, --- leds => open, --- opto_inhibit => open, --- opto_los => (others => '0'), --- register_map_control => register_map_control, --- register_map_gen_board_info => register_map_gen_board_info, --- register_map_hk_monitor => register_map_hk_monitor, --- rst_soft => reset_soft, --- sys_reset_n => sys_reset_n, --- rst_hw => rst_hw, --- CLK40_FPGA2LMK_P => open, --- CLK40_FPGA2LMK_N => open, --- LMK_DATA => open, --- LMK_CLK => open, --- LMK_LE => open, --- LMK_GOE => open, --- LMK_LD => '0', --- LMK_SYNCn => open, --- I2C_SMB => open, --- I2C_SMBUS_CFG_nEN => open, --- MGMT_PORT_EN => open, --- PCIE_PERSTn1 => open, --- PCIE_PERSTn2 => open, --- PEX_PERSTn => open, --- PEX_SCL => open, --- PEX_SDA => open, --- PORT_GOOD => (others => '0'), --- SHPC_INT => '0', --- lnk_up => lnk_up - --- ); + hk0: entity work.housekeeping_module + generic map ( + CARD_TYPE => CARD_TYPE, + OPTO_TRX => 4, + GBT_NUM => 24, + ENDPOINTS => ENDPOINTS, + generateTTCemu => false, + AUTOMATIC_CLOCK_SWITCH => false, + FIRMWARE_MODE => 0, + USE_Si5324_RefCLK => false, + GENERATE_XOFF => false, + IncludeDecodingEpath2_HDLC => "0000000", + IncludeDecodingEpath2_8b10b => "0000000", + IncludeDecodingEpath4_8b10b => "0000000", + IncludeDecodingEpath8_8b10b => "0000000", + IncludeDecodingEpath16_8b10b => "0000000", + IncludeEncodingEpath2_HDLC => "00000", + IncludeEncodingEpath2_8b10b => "00000", + IncludeEncodingEpath4_8b10b => "00000", + IncludeEncodingEpath8_8b10b => "00000", + SUPER_CHUNK_FACTOR => 1, + BLOCKSIZE => 1024, + CHUNK_TRAILER_32B => true + ) + port map( + MMCM_Locked_in => pll_locked, + MMCM_OscSelect_in => '0', + SCL => SCL, + SDA => SDA, + SI5345_A => open, + SI5345_INSEL => open, + SI5345_OE => open, + SI5345_RSTN => open, + SI5345_SEL => open, + SI5345_nLOL => open, + appreg_clk => appreg_clk, + emcclk => '0', + flash_SEL => '0', + flash_a => open, + flash_a_msb => open, + flash_adv => open, + flash_cclk => open, + flash_ce => open, + flash_d => open, + flash_re => open, + flash_we => open, + i2cmux_rst => i2cmux_rst, + TACH => '0', + clk10_xtal => '0', + clk40_xtal => appreg_clk, + clk40 => appreg_clk, + leds => open, + opto_inhibit => open, + register_map_control => register_map_control, + register_map_gen_board_info => register_map_gen_board_info, + register_map_hk_monitor => register_map_hk_monitor, + rst_soft => reset_soft, + sys_reset_n => sys_reset_n, + rst_hw => reset_hard, + CLK40_FPGA2LMK_P => open, + CLK40_FPGA2LMK_N => open, + LMK_DATA => open, + LMK_CLK => open, + LMK_LE => open, + LMK_GOE => open, + LMK_LD => '0', + LMK_SYNCn => open, + I2C_SMB => open, + I2C_SMBUS_CFG_nEN => open, + MGMT_PORT_EN => open, + PCIE_PERSTn1 => open, + PCIE_PERSTn2 => open, + PEX_PERSTn => open, + PEX_SCL => open, + PEX_SDA => open, + PORT_GOOD => (others => '0'), + SHPC_INT => '0', + lnk_up => lnk_up, + RXUSRCLK_IN => RXUSRCLK + ); g_endpoints: for i in 0 to ENDPOINTS-1 generate signal ep_register_map_control : register_map_control_type; --! contains all read/write registers that control the application. The record members are described in pcie_package.vhd - signal register_map_control_appreg_clk : register_map_control_type; - --signal register_map_cr_monitor : register_map_cr_monitor_type; - signal register_map_gbtemu_monitor : register_map_gbtemu_monitor_type; - signal register_map_xoff_monitor : register_map_xoff_monitor_type; - signal register_map_link_monitor : register_map_link_monitor_type; - signal register_map_decoding_monitor : register_map_decoding_monitor_type; - signal register_map_crtohost_monitor : register_map_crtohost_monitor_type; - signal register_map_crfromhost_monitor : register_map_crfromhost_monitor_type; - signal register_map_encoding_monitor : register_map_encoding_monitor_type; - signal register_map_generators : register_map_generators_type; - signal wishbone_monitor : wishbone_monitor_type; - signal regmap_mrod_monitor : regmap_mrod_monitor_type; - signal reset_soft_appreg_clk : std_logic; + signal register_map_control_appreg_clk : register_map_control_type; -- @suppress "signal register_map_control_appreg_clk is never read" + signal register_map_gbtemu_monitor : register_map_gbtemu_monitor_type; -- @suppress "signal register_map_gbtemu_monitor is never written" + signal register_map_xoff_monitor : register_map_xoff_monitor_type; -- @suppress "signal register_map_xoff_monitor is never written" + signal register_map_decoding_monitor : register_map_decoding_monitor_type; -- @suppress "signal register_map_decoding_monitor is never written" -- @suppress "signal register_map_crtohost_monitor is never written" + signal register_map_crtohost_monitor : register_map_crtohost_monitor_type; -- @suppress "signal register_map_crtohost_monitor is never written" + signal register_map_crfromhost_monitor : register_map_crfromhost_monitor_type; -- @suppress "signal register_map_crfromhost_monitor is never written" + signal register_map_encoding_monitor : register_map_encoding_monitor_type; -- @suppress "signal register_map_encoding_monitor is never written" + signal register_map_generators : register_map_generators_type; -- @suppress "signal register_map_generators is never written" + signal wishbone_monitor : wishbone_monitor_type; -- @suppress "signal wishbone_monitor is never written" + signal regmap_mrod_monitor : regmap_mrod_monitor_type; -- @suppress "signal regmap_mrod_monitor is never written" + signal reset_soft_appreg_clk : std_logic; -- @suppress "signal reset_soft_appreg_clk is never read" - signal interrupt_call : std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4); + --signal interrupt_call : std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4); signal ep_reset_soft : std_logic; signal ep_reset_hard : std_logic; - signal flush_fifo : std_logic; - signal fromHostFifo_pfull_threshold_assert : std_logic_vector(8 downto 0); - signal fromHostFifo_pfull_threshold_negate : std_logic_vector(8 downto 0); - signal fromHostFifo_we : std_logic; - signal fromHostFifo_din : std_logic_vector(DATA_WIDTH-1 downto 0); - signal fromHostFifo_prog_full : std_logic; - signal toHostFifo_dout : std_logic_vector(DATA_WIDTH-1 downto 0); - signal toHostFifo_re : std_logic; - signal toHostFifo_prog_empty : std_logic; - signal toHostFifo_empty_thresh : std_logic_vector(11 downto 0); - signal toHostFifo_rd_clk : std_logic; - signal toHostFifo_pfull_threshold_assert : std_logic_vector(11 downto 0); - signal toHostFifo_pfull_threshold_negate : std_logic_vector(11 downto 0); - signal fromHostFifo_dout : std_logic_vector(DATA_WIDTH-1 downto 0); + --signal flush_fifo : std_logic; + --signal fromHostFifo_pfull_threshold_assert : std_logic_vector(8 downto 0); + --signal fromHostFifo_pfull_threshold_negate : std_logic_vector(8 downto 0); + --signal fromHostFifo_we : std_logic; + --signal fromHostFifo_din : std_logic_vector(DATA_WIDTH-1 downto 0); + --signal fromHostFifo_prog_full : std_logic; + --signal toHostFifo_dout : std_logic_vector(DATA_WIDTH-1 downto 0); + --signal toHostFifo_re : std_logic; + --signal toHostFifo_prog_empty : std_logic; + --signal toHostFifo_empty_thresh : std_logic_vector(11 downto 0); + --signal toHostFifo_rd_clk : std_logic; + --signal toHostFifo_pfull_threshold_assert : std_logic_vector(11 downto 0); + --signal toHostFifo_pfull_threshold_negate : std_logic_vector(11 downto 0); + signal fromHostFifo_dout : std_logic_vector(DATA_WIDTH-1 downto 0); -- @suppress "signal fromHostFifo_dout is never read" signal fromHostFifo_rd_en : std_logic; signal fromHostFifo_empty : std_logic; signal fromHostFifo_rd_clk : std_logic; signal fromHostFifo_rst : std_logic; signal toHostFifo_wr_clk : std_logic; signal toHostFifo_rst : std_logic; - signal fromHostFifo_wr_clk : std_logic; + --signal fromHostFifo_wr_clk : std_logic; signal ep_appreg_clk: std_logic; - signal ep_pll_locked: std_logic; + signal ep_pll_locked: std_logic; -- @suppress "signal ep_pll_locked is never read" signal toHostFifo_din : slv_array(0 to NUMBER_OF_DESCRIPTORS-2); signal toHostFifo_prog_full : std_logic_vector(NUMBER_OF_DESCRIPTORS-2 downto 0); - signal wr_data_count : slv12_array(0 to NUMBER_OF_DESCRIPTORS-2); + signal wr_data_count : slv12_array(0 to NUMBER_OF_DESCRIPTORS-2); -- @suppress "signal wr_data_count is never read" signal toHostFifo_wr_en : std_logic_vector(NUMBER_OF_DESCRIPTORS-2 downto 0); signal clk250: std_logic; signal rst_hw : std_logic; @@ -235,7 +254,6 @@ begin NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS, NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS, BUILD_DATETIME => BUILD_DATETIME, - SVN_VERSION => SVN_VERSION, CARD_TYPE => CARD_TYPE, GIT_HASH => GIT_HASH, COMMIT_DATETIME => COMMIT_DATETIME, @@ -243,16 +261,20 @@ begin GIT_COMMIT_NUMBER => GIT_COMMIT_NUMBER, GBT_GENERATE_ALL_REGS => true, EMU_GENERATE_REGS => true, + MROD_GENERATE_REGS => false, + GBT_NUM => 12, + FIRMWARE_MODE => 0, PCIE_ENDPOINT => i, PCIE_LANES => PCIE_LANES, DATA_WIDTH => DATA_WIDTH, - SIMULATION => false) + SIMULATION => false, + BLOCKSIZE => 1024) port map( appreg_clk => ep_appreg_clk, - sync_clk => ep_appreg_clk, - flush_fifo => flush_fifo, + sync_clk => ep_appreg_clk, + flush_fifo => open, fromhost_busy_out => open, - interrupt_call => interrupt_call, + interrupt_call => (others => '0'), lnk_up => lnk_up(i), pcie_rxn => pcie_rxn(PCIE_LANES*i+(PCIE_LANES-1) downto PCIE_LANES*i), pcie_rxp => pcie_rxp(PCIE_LANES*i+(PCIE_LANES-1) downto PCIE_LANES*i), @@ -261,19 +283,19 @@ begin pll_locked => ep_pll_locked, register_map_control_sync => ep_register_map_control, register_map_control_appreg_clk => register_map_control_appreg_clk, - register_map_gbtemu_monitor => register_map_gbtemu_monitor, - register_map_link_monitor => register_map_link_monitor, register_map_gen_board_info => register_map_gen_board_info, - register_map_hk_monitor => register_map_hk_monitor, register_map_crtohost_monitor => register_map_crtohost_monitor, register_map_crfromhost_monitor => register_map_crfromhost_monitor, + register_map_decoding_monitor => register_map_decoding_monitor, register_map_encoding_monitor => register_map_encoding_monitor, + register_map_gbtemu_monitor => register_map_gbtemu_monitor, + register_map_link_monitor => register_map_link_monitor, + register_map_ttc_monitor => register_map_ttc_monitor, + register_map_xoff_monitor => register_map_xoff_monitor, + register_map_hk_monitor => register_map_hk_monitor, register_map_generators => register_map_generators, wishbone_monitor => wishbone_monitor, regmap_mrod_monitor => regmap_mrod_monitor, - register_map_ttc_monitor => register_map_ttc_monitor, - register_map_xoff_monitor => register_map_xoff_monitor, - register_map_decoding_monitor => register_map_decoding_monitor, reset_hard => ep_reset_hard, reset_soft => ep_reset_soft, reset_soft_appreg_clk => reset_soft_appreg_clk, @@ -293,8 +315,8 @@ begin toHostFifo_wr_clk => toHostFifo_wr_clk, wr_data_count => wr_data_count, toHostFifo_wr_en => toHostFifo_wr_en, - clk250_out => clk250, - master_busy_in => '0'); + clk250_out => clk250, + master_busy_in => '0'); toHostFifo_wr_clk <= clk250; fromHostFifo_rd_clk <= clk250; diff --git a/sources/packages/axi_stream_package.vhd b/sources/packages/axi_stream_package.vhd index 6c5ccdba718a9cef48f426514637dd771437fd98..a0f007ca502dd54d9765e0dd7be0a7bbecc286e8 100644 --- a/sources/packages/axi_stream_package.vhd +++ b/sources/packages/axi_stream_package.vhd @@ -16,7 +16,6 @@ --!----------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; package axi_stream_package is diff --git a/sources/packages/centralRouter_package.vhd b/sources/packages/centralRouter_package.vhd index 896144f5a46a5ca0a593d7f0c3bc5b2d9d3dafce..e5911c108e4ab3129ad02c4995dac0a338c29fba 100644 --- a/sources/packages/centralRouter_package.vhd +++ b/sources/packages/centralRouter_package.vhd @@ -19,7 +19,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; +--use ieee.std_logic_unsigned.all; package centralRouter_package is diff --git a/sources/pcie/WupperFifos.vhd b/sources/pcie/WupperFifos.vhd index 6c267ff249e37486a32e12670c2f01563cb5a8a0..9cc78a2aa68694426dc4d52723ff54c170e16cc6 100644 --- a/sources/pcie/WupperFifos.vhd +++ b/sources/pcie/WupperFifos.vhd @@ -6,7 +6,7 @@ library ieee, UNISIM, XPM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; use XPM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use ieee.std_logic_1164.all; use work.pcie_package.all; use work.FELIX_package.all; @@ -16,7 +16,7 @@ entity WupperFifos is NUMBER_OF_DESCRIPTORS : integer := 3; DATA_WIDTH : integer := 256); port ( - fromHostFifoIndex : in integer range 0 to 0; + --fromHostFifoIndex : in integer range 0 to 0; fromHostFifo_din : in std_logic_vector(DATA_WIDTH-1 downto 0); fromHostFifo_dout : out std_logic_vector(DATA_WIDTH-1 downto 0); fromHostFifo_empty : out std_logic; @@ -57,7 +57,7 @@ architecture rtl of WupperFifos is begin fromHostFifo0 : xpm_fifo_async - generic map ( + generic map ( -- @suppress "Generic map uses default values. Missing optional actuals: USE_ADV_FEATURES, SIM_ASSERT_CHK" FIFO_MEMORY_TYPE => "block", --string; "auto", "block", or "distributed"; ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc"; RELATED_CLOCKS => 0, --positive integer; 0 or 1 @@ -76,28 +76,32 @@ begin WAKEUP_TIME => 0 --positive integer; 0 or 2; ) port map ( - sleep => '0', - rst => fromHostFifo_rst, - wr_clk => fromHostFifo_wr_clk, - wr_en => fromHostFifo_we, - din => fromHostFifo_din, - full => open, - overflow => open, - wr_rst_busy => open, - rd_clk => fromHostFifo_rd_clk, - rd_en => fromHostFifo_rd_en, - dout => fromHostFifo_dout, - empty => fromHostFifo_empty, - underflow => open, - rd_rst_busy => open, - prog_full => open, + sleep => '0', + rst => fromHostFifo_rst, + wr_clk => fromHostFifo_wr_clk, + wr_en => fromHostFifo_we, + din => fromHostFifo_din, + full => open, + prog_full => open, wr_data_count => fromHostFifo_wr_data_count, - prog_empty => open, + overflow => open, + wr_rst_busy => open, + almost_full => open, + wr_ack => open, + rd_clk => fromHostFifo_rd_clk, + rd_en => fromHostFifo_rd_en, + dout => fromHostFifo_dout, + empty => fromHostFifo_empty, + prog_empty => open, rd_data_count => open, + underflow => open, + rd_rst_busy => open, + almost_empty => open, + data_valid => open, injectsbiterr => '0', injectdbiterr => '0', - sbiterr => open, - dbiterr => open + sbiterr => open, + dbiterr => open ); @@ -139,7 +143,7 @@ begin begin toHostFifo0 : xpm_fifo_async - generic map ( + generic map ( -- @suppress "Generic map uses default values. Missing optional actuals: USE_ADV_FEATURES, SIM_ASSERT_CHK" FIFO_MEMORY_TYPE => "block", --string; "auto", "block", or "distributed"; ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc"; RELATED_CLOCKS => 0, --positive integer; 0 or 1 @@ -158,28 +162,32 @@ begin WAKEUP_TIME => 0 --positive integer; 0 or 2; ) port map ( - sleep => '0', - rst => toHostFifo_rst, - wr_clk => toHostFifo_wr_clk, - wr_en => toHostFifo_wr_en_pipe, - din => toHostFifo_din_pipe, - full => open, - overflow => open, - wr_rst_busy => open, - rd_clk => toHostFifo_rd_clk, - rd_en => toHostFifo_re_array(i), - dout => toHostFifo_dout_array(i), - empty => open, - underflow => open, - rd_rst_busy => open, - prog_full => open, + sleep => '0', + rst => toHostFifo_rst, + wr_clk => toHostFifo_wr_clk, + wr_en => toHostFifo_wr_en_pipe, + din => toHostFifo_din_pipe, + full => open, + prog_full => open, wr_data_count => toHostFifo_wr_data_count_s, - prog_empty => open, + overflow => open, + wr_rst_busy => open, + almost_full => open, + wr_ack => open, + rd_clk => toHostFifo_rd_clk, + rd_en => toHostFifo_re_array(i), + dout => toHostFifo_dout_array(i), + empty => open, + prog_empty => open, rd_data_count => toHostFifo_rd_data_count_s, + underflow => open, + rd_rst_busy => open, + almost_empty => open, + data_valid => open, injectsbiterr => '0', injectdbiterr => '0', - sbiterr => open, - dbiterr => open + sbiterr => open, + dbiterr => open ); tohost_prog_full_proc: process(toHostFifo_wr_clk) diff --git a/sources/pcie/data_width_package_256.vhd b/sources/pcie/data_width_package_256.vhd index c8e2c5a3143bcd10e61a5fcdb25bccb5057b1a80..7ec6a0ec9f31b33a7d84ca1c8b0d46a33a4cb35d 100644 --- a/sources/pcie/data_width_package_256.vhd +++ b/sources/pcie/data_width_package_256.vhd @@ -1,6 +1,5 @@ library ieee; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; diff --git a/sources/pcie/dma_read_write.vhd b/sources/pcie/dma_read_write.vhd index 72800f396321f64dc135a2e793ce8ce43202437d..58421cd5b9da3d49a8c335e796a82cfc79364aad 100644 --- a/sources/pcie/dma_read_write.vhd +++ b/sources/pcie/dma_read_write.vhd @@ -49,10 +49,10 @@ -library ieee, UNISIM, work; +library ieee, UNISIM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use ieee.std_logic_1164.all; use work.pcie_package.all; Library xpm; @@ -88,27 +88,27 @@ end entity dma_read_write; architecture rtl of dma_read_write is constant NUMBER_OF_DESCRIPTORS_TOHOST: integer := NUMBER_OF_DESCRIPTORS -1; - constant NUMBER_OF_DESCRIPTORS_FROMHOST: integer := 1; + --constant NUMBER_OF_DESCRIPTORS_FROMHOST: integer := 1; type rw_state_type is(IDLE, START_WRITE, CONT_WRITE, END_WRITE, START_READ, CONT_READ, END_READ); signal rw_state: rw_state_type := IDLE; - signal rw_state_slv: std_logic_vector(2 downto 0); + signal rw_state_slv: std_logic_vector(2 downto 0); -- @suppress "signal rw_state_slv is never read" attribute dont_touch : string; attribute dont_touch of rw_state_slv : signal is "true"; constant IDLE_SLV : std_logic_vector(2 downto 0) := "000"; constant START_WRITE_SLV : std_logic_vector(2 downto 0) := "001"; constant CONT_WRITE_SLV : std_logic_vector(2 downto 0) := "010"; - constant END_WRITE_SLV : std_logic_vector(2 downto 0) := "011"; + --constant END_WRITE_SLV : std_logic_vector(2 downto 0) := "011"; constant START_READ_SLV : std_logic_vector(2 downto 0) := "100"; - constant CONT_READ_SLV : std_logic_vector(2 downto 0) := "101"; - constant END_READ_SLV : std_logic_vector(2 downto 0) := "110"; + --constant CONT_READ_SLV : std_logic_vector(2 downto 0) := "101"; + --constant END_READ_SLV : std_logic_vector(2 downto 0) := "110"; type strip_state_type is(IDLE, PUSH_DATA); signal strip_state: strip_state_type := IDLE; - signal strip_state_slv: std_logic_vector(2 downto 0); + signal strip_state_slv: std_logic_vector(2 downto 0); -- @suppress "signal strip_state_slv is never read" attribute dont_touch of strip_state_slv : signal is "true"; constant PUSH_DATA_SLV : std_logic_vector(2 downto 0) := "001"; @@ -118,10 +118,10 @@ architecture rtl of dma_read_write is signal mem_dina_pipe: std_logic_vector(DATA_WIDTH-97 downto 0); --pipe part of the fifo data 1 clock cycle for 256 bit alignment constant req_tc: std_logic_vector (2 downto 0) := "000"; constant req_attr: std_logic_vector(2 downto 0) := "000"; --ID based ordering, Relaxed ordering, No Snoop (should be "001"?) - signal s_axis_rc_tlast_pipe, s_axis_rc_tvalid_pipe: std_logic; + signal s_axis_rc_tlast_pipe: std_logic; signal receive_word_count: std_logic_vector(10 downto 0); signal active_descriptor_s: integer range 0 to (NUMBER_OF_DESCRIPTORS-1); - signal next_active_descriptor_s: integer range 0 to (NUMBER_OF_DESCRIPTORS-1); + --signal next_active_descriptor_s: integer range 0 to (NUMBER_OF_DESCRIPTORS-1); signal current_dword_count_s: std_logic_vector(10 downto 0); signal toHostFifoIndex_s : integer range 0 to NUMBER_OF_DESCRIPTORS_TOHOST-1; @@ -142,7 +142,7 @@ architecture rtl of dma_read_write is signal mem_full : std_logic_vector(127 downto 0); signal mem_full_p1 : std_logic_vector(127 downto 0); signal reading_mem : std_logic; - signal fromHostFifo_we_p0 : std_logic; + --signal fromHostFifo_we_p0 : std_logic; signal clear_wait_for_4k_boundary : std_logic; begin @@ -451,8 +451,8 @@ begin s_axis_r_rc.tready <= '1'; --not fromHostFifo_prog_full; - strip_hdr: process(clk, reset, dma_soft_reset) - variable receive_word_count_v: std_logic_vector(10 downto 0); + strip_hdr: process(clk) + --variable receive_word_count_v: std_logic_vector(10 downto 0); begin if(rising_edge(clk)) then if(reset = '1') or (dma_soft_reset = '1') then @@ -467,7 +467,7 @@ begin strip_state <= IDLE; mem_wea <= "0"; s_axis_rc_tlast_pipe <= s_axis_rc.tlast; - s_axis_rc_tvalid_pipe <= s_axis_rc.tvalid; + --s_axis_rc_tvalid_pipe <= s_axis_rc.tvalid; receive_word_count <= receive_word_count; case (strip_state) is when IDLE => @@ -544,7 +544,7 @@ begin fromHostFifo_din <= mem_doutb; rc_interface_mem : xpm_memory_sdpram - generic map ( + generic map ( -- @suppress "Generic map uses default values. Missing optional actuals: USE_EMBEDDED_CONSTRAINT, CASCADE_HEIGHT, SIM_ASSERT_CHK, RST_MODE_A, RST_MODE_B" ADDR_WIDTH_A => 7, ADDR_WIDTH_B => 7, AUTO_SLEEP_TIME => 0, @@ -571,21 +571,21 @@ begin WRITE_MODE_B => "no_change" ) port map ( - dbiterrb => open, - doutb => mem_doutb, - sbiterrb => open, - addra => mem_addra, - addrb => mem_addrb, + sleep => '0', clka => clk, - clkb => clk, - dina => mem_dina, ena => '1', - enb => '1', - injectdbiterra => '0', + wea => mem_wea, + addra => mem_addra, + dina => mem_dina, injectsbiterra => '0', - regceb => '1', + injectdbiterra => '0', + clkb => clk, rstb => reset, - sleep => '0', - wea => mem_wea + enb => '1', + regceb => '1', + addrb => mem_addrb, + doutb => mem_doutb, + sbiterrb => open, + dbiterrb => open ); end architecture rtl ; -- of dma_read_write diff --git a/sources/pcie/intr_ctrl.vhd b/sources/pcie/intr_ctrl.vhd index 7f6d2c139458aeb83db8c7c73dff71673a2c052b..e72b91d098752a776f40e408007e183371a37d42 100644 --- a/sources/pcie/intr_ctrl.vhd +++ b/sources/pcie/intr_ctrl.vhd @@ -54,10 +54,10 @@ -library ieee, UNISIM, work; +library ieee, UNISIM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +--use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; use work.pcie_package.all; @@ -68,9 +68,9 @@ entity intr_ctrl is cfg_interrupt_msix_address : out std_logic_vector(63 downto 0); cfg_interrupt_msix_data : out std_logic_vector(31 downto 0); cfg_interrupt_msix_enable : in std_logic_vector(3 downto 0); - cfg_interrupt_msix_fail : in std_logic; + --cfg_interrupt_msix_fail : in std_logic; cfg_interrupt_msix_int : out std_logic; - cfg_interrupt_msix_sent : in std_logic; + --cfg_interrupt_msix_sent : in std_logic; clk : in std_logic; regmap_clk : in std_logic; dma_interrupt_call : in std_logic_vector(3 downto 0); @@ -96,15 +96,15 @@ architecture rtl of intr_ctrl is signal s_cfg_interrupt_msix_data : std_logic_vector(31 downto 0); signal s_cfg_interrupt_msix_address : std_logic_vector(63 downto 0); - signal monitor_cfg_interrupt_msix_data : std_logic_vector(31 downto 0); - signal monitor_cfg_interrupt_msix_address : std_logic_vector(63 downto 0); + --signal monitor_cfg_interrupt_msix_data : std_logic_vector(31 downto 0); + --signal monitor_cfg_interrupt_msix_address : std_logic_vector(63 downto 0); signal s_interrupt_call : std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 0); signal s_interrupt_latch : std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 0); signal clear_interrupt_pending_s : std_logic; - attribute dont_touch : string; - attribute dont_touch of monitor_cfg_interrupt_msix_data : signal is "true"; - attribute dont_touch of monitor_cfg_interrupt_msix_address : signal is "true"; + --attribute dont_touch : string; + --attribute dont_touch of monitor_cfg_interrupt_msix_data : signal is "true"; + --attribute dont_touch of monitor_cfg_interrupt_msix_address : signal is "true"; signal axi_busy : std_logic; signal s_interrupt_pending : std_logic := '0'; @@ -113,7 +113,7 @@ architecture rtl of intr_ctrl is begin -- Interrupt vector assignments - interrupt_assign : process (regmap_clk, interrupt_vector) + interrupt_assign : process (regmap_clk) begin if rising_edge (regmap_clk) then for i in 0 to (NUMBER_OF_INTERRUPTS-1) loop @@ -145,8 +145,8 @@ begin -- -- Monitor Signals -- - monitor_cfg_interrupt_msix_data <= s_cfg_interrupt_msix_data; - monitor_cfg_interrupt_msix_address <= s_cfg_interrupt_msix_address; + --monitor_cfg_interrupt_msix_data <= s_cfg_interrupt_msix_data; + --monitor_cfg_interrupt_msix_address <= s_cfg_interrupt_msix_address; s_interrupt_call <= interrupt_call & dma_interrupt_call; -- diff --git a/sources/pcie/pcie_clocking.vhd b/sources/pcie/pcie_clocking.vhd index 85720672b254866f11c72eebf1ff45c95a65abea..2576621fe9574527b94b1df78dd68bc495fddc99 100644 --- a/sources/pcie/pcie_clocking.vhd +++ b/sources/pcie/pcie_clocking.vhd @@ -46,9 +46,9 @@ --! @brief ieee -library work, ieee, UNISIM; +library ieee, UNISIM; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +--use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; @@ -57,7 +57,7 @@ entity pcie_clocking is generic ( PCIE_ASYNC_EN : string := "FALSE"; -- PCIe async enable - PCIE_TXBUF_EN : string := "FALSE"; -- PCIe TX buffer enable for Gen1/Gen2 only + --PCIE_TXBUF_EN : string := "FALSE"; -- PCIe TX buffer enable for Gen1/Gen2 only PCIE_CLK_SHARING_EN: string := "FALSE"; -- Enable Clock Sharing PCIE_LANE : integer := 8; -- PCIe number of lanes PCIE_LINK_SPEED : integer := 3; -- PCIe link speed @@ -69,13 +69,13 @@ generic ); port ( - CLK_CLK : in std_logic; + --CLK_CLK : in std_logic; CLK_TXOUTCLK : in std_logic; CLK_RXOUTCLK_IN : in std_logic_vector(PCIE_LANE-1 downto 0); CLK_RST_N : in std_logic; CLK_PCLK_SEL : in std_logic_vector(PCIE_LANE-1 downto 0); CLK_PCLK_SEL_SLAVE : in std_logic_vector(PCIE_LANE-1 downto 0); - CLK_GEN3 : in std_logic; + --CLK_GEN3 : in std_logic; CLK_PCLK : out std_logic; CLK_PCLK_SLAVE : out std_logic; @@ -131,31 +131,31 @@ architecture rtl of pcie_clocking is ---------- Input Registers --------------------------- signal pclk_sel_reg1 : std_logic_vector(PCIE_LANE-1 downto 0) := (others => '0'); signal pclk_sel_slave_reg1 : std_logic_vector(PCIE_LANE-1 downto 0) := (others => '0'); - signal gen3_reg1 : std_logic := '0'; + --signal gen3_reg1 : std_logic := '0'; signal pclk_sel_reg2 : std_logic_vector(PCIE_LANE-1 downto 0) := (others => '0'); signal pclk_sel_slave_reg2 : std_logic_vector(PCIE_LANE-1 downto 0) := (others => '0'); - signal gen3_reg2 : std_logic := '0'; + --signal gen3_reg2 : std_logic := '0'; attribute ASYNC_REG : string; attribute SHIFT_EXTRACT : string; attribute ASYNC_REG of pclk_sel_reg1: signal is "TRUE"; attribute ASYNC_REG of pclk_sel_slave_reg1: signal is "TRUE"; - attribute ASYNC_REG of gen3_reg1: signal is "TRUE"; + --attribute ASYNC_REG of gen3_reg1: signal is "TRUE"; attribute ASYNC_REG of pclk_sel_reg2: signal is "TRUE"; attribute ASYNC_REG of pclk_sel_slave_reg2: signal is "TRUE"; - attribute ASYNC_REG of gen3_reg2: signal is "TRUE"; + --attribute ASYNC_REG of gen3_reg2: signal is "TRUE"; attribute SHIFT_EXTRACT of pclk_sel_reg1: signal is "NO"; attribute SHIFT_EXTRACT of pclk_sel_slave_reg1: signal is "NO"; - attribute SHIFT_EXTRACT of gen3_reg1: signal is "NO"; + ---attribute SHIFT_EXTRACT of gen3_reg1: signal is "NO"; attribute SHIFT_EXTRACT of pclk_sel_reg2: signal is "NO"; attribute SHIFT_EXTRACT of pclk_sel_slave_reg2: signal is "NO"; - attribute SHIFT_EXTRACT of gen3_reg2: signal is "NO"; + --attribute SHIFT_EXTRACT of gen3_reg2: signal is "NO"; ---------- Internal Signals -------------------------- - signal refclk : std_logic; + --signal refclk : std_logic; signal mmcm_fb : std_logic; signal clk_125mhz : std_logic; signal clk_125mhz_buf : std_logic; @@ -185,20 +185,20 @@ begin ---------- 1st Stage FF -------------------------- pclk_sel_reg1 <= (others => '0'); pclk_sel_slave_reg1 <= (others => '0'); - gen3_reg1 <= '0'; + --gen3_reg1 <= '0'; ---------- 2nd Stage FF -------------------------- pclk_sel_reg2 <= (others => '0'); pclk_sel_slave_reg2 <= (others => '0'); - gen3_reg2 <= '0'; + --gen3_reg2 <= '0'; elsif(rising_edge(pclk)) then ---------- 1st Stage FF -------------------------- pclk_sel_reg1 <= CLK_PCLK_SEL; pclk_sel_slave_reg1 <= CLK_PCLK_SEL_SLAVE; - gen3_reg1 <= CLK_GEN3; + --gen3_reg1 <= CLK_GEN3; ---------- 2nd Stage FF -------------------------- pclk_sel_reg2 <= pclk_sel_reg1; pclk_sel_slave_reg2 <= pclk_sel_slave_reg1; - gen3_reg2 <= gen3_reg1; + --gen3_reg2 <= gen3_reg1; end if; end process; @@ -207,7 +207,7 @@ CLK_RST <= not CLK_RST_N; ---------- MMCM -------------------------------------------------------------- mmcm0: MMCME2_ADV -generic map +generic map -- @suppress "Generic map uses default values. Missing optional actuals: CLKIN2_PERIOD, CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, CLKOUT5_PHASE, CLKOUT5_USE_FINE_PS, CLKOUT6_DIVIDE, CLKOUT6_DUTY_CYCLE, CLKOUT6_PHASE, CLKOUT6_USE_FINE_PS, IS_CLKINSEL_INVERTED, IS_PSEN_INVERTED, IS_PSINCDEC_INVERTED, IS_PWRDWN_INVERTED, IS_RST_INVERTED, REF_JITTER2, SS_EN, SS_MODE, SS_MOD_PERIOD" ( BANDWIDTH => ("OPTIMIZED"), @@ -242,7 +242,7 @@ generic map REF_JITTER1 => (0.010) ) -port map +port map -- @suppress "The order of the associations is different from the declaration order" ( ---------- Input ------------------------------------ @@ -294,8 +294,8 @@ port map pclk_sel_n <= not pclk_sel; ---------- Select PCLK MUX --------------------------------------------------- g0: if (PCIE_LINK_SPEED /= 1) generate - pclk_i1: BUFGCTRL - port map + pclk_i1: BUFGCTRL -- @suppress "Generic map uses default values. Missing optional actuals: CE_TYPE_CE0, CE_TYPE_CE1, INIT_OUT, IS_CE0_INVERTED, IS_CE1_INVERTED, IS_I0_INVERTED, IS_I1_INVERTED, IS_IGNORE0_INVERTED, IS_IGNORE1_INVERTED, IS_S0_INVERTED, IS_S1_INVERTED, PRESELECT_I0, PRESELECT_I1, SIM_DEVICE, STARTUP_SYNC" + port map -- @suppress "The order of the associations is different from the declaration order" ( ---------- Input --------------------------------- CE0 => '1', @@ -317,8 +317,8 @@ g1: if (PCIE_LINK_SPEED = 1) generate pclk_i1: BUFG port map ( - I => clk_125mhz, - O => clk_125mhz_buf + O => clk_125mhz_buf, + I => clk_125mhz ); pclk_1 <= clk_125mhz_buf; end generate; @@ -334,8 +334,8 @@ pclk_sel_slave_n <= not pclk_sel_slave; g3: if(PCIE_CLK_SHARING_EN /= "FALSE") generate g3a: if (PCIE_LINK_SPEED /= 1) generate ---------- PCLK Mux ---------------------------------- - pclk_slave: BUFGCTRL - port map + pclk_slave: BUFGCTRL -- @suppress "Generic map uses default values. Missing optional actuals: CE_TYPE_CE0, CE_TYPE_CE1, INIT_OUT, IS_CE0_INVERTED, IS_CE1_INVERTED, IS_I0_INVERTED, IS_I1_INVERTED, IS_IGNORE0_INVERTED, IS_IGNORE1_INVERTED, IS_S0_INVERTED, IS_S1_INVERTED, PRESELECT_I0, PRESELECT_I1, SIM_DEVICE, STARTUP_SYNC" + port map -- @suppress "The order of the associations is different from the declaration order" ( ---------- Input --------------------------------- CE0 => '1', @@ -357,8 +357,8 @@ g3: if(PCIE_CLK_SHARING_EN /= "FALSE") generate pclk_slave: BUFG port map ( - I => clk_125mhz, - O => CLK_PCLK_SLAVE + O => CLK_PCLK_SLAVE, + I => clk_125mhz ); end generate; end generate; @@ -371,8 +371,8 @@ g4: if ((PCIE_DEBUG_MODE = 1) or (PCIE_ASYNC_EN = "TRUE")) generate bufg0: BUFG port map ( - I => CLK_RXOUTCLK_IN(i), - O => CLK_RXOUTCLK_OUT(i) + O => CLK_RXOUTCLK_OUT(i), + I => CLK_RXOUTCLK_IN(i) ); end generate; end generate; @@ -394,8 +394,8 @@ g7: if (PCIE_USERCLK2_FREQ > 3) generate dclk_i: BUFG port map ( - I => clk_125mhz, - O => CLK_DCLK + O => CLK_DCLK, + I => clk_125mhz ); end generate; @@ -413,8 +413,8 @@ g9: if (not((PCIE_GEN1_MODE = 1) and (PCIE_USERCLK1_FREQ = 3))) generate usrclk1_i1: BUFG port map ( - I => (userclk1), - O => (userclk1_1) + O => (userclk1_1), + I => (userclk1) ); end generate; @@ -436,8 +436,8 @@ g12: if not ((not ((PCIE_GEN1_MODE = 1) and (PCIE_USERCLK2_FREQ = 3 ))) and (PCI usrclk2_i1: BUFG port map ( - I => userclk2, - O => userclk2_1 + O => userclk2_1, + I => userclk2 ); end generate; @@ -448,8 +448,8 @@ g13: if (PCIE_OOBCLK_MODE = 2) generate oobclk_i1: BUFG port map ( - I => oobclk, - O => CLK_OOBCLK + O => CLK_OOBCLK, + I => oobclk ); end generate; diff --git a/sources/pcie/pcie_ep_wrap.vhd b/sources/pcie/pcie_ep_wrap.vhd index 90040e27314f5bf124b61f0e8391195a5da309bc..eeca6b191ecfb613c0e377ecaf124f43d0371878 100644 --- a/sources/pcie/pcie_ep_wrap.vhd +++ b/sources/pcie/pcie_ep_wrap.vhd @@ -134,23 +134,23 @@ type devid_array is array(0 to 1) of std_logic_vector(15 downto 0); - probe0 : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + probe0 : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); probe1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - probe5 : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + probe5 : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); probe6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - probe10 : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + probe10 : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); probe11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe14 : IN STD_LOGIC_VECTOR(182 DOWNTO 0); probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - probe16 : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + probe16 : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); probe17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); @@ -191,44 +191,34 @@ type devid_array is array(0 to 1) of std_logic_vector(15 downto 0); component pcie_clocking - generic - ( - PCIE_ASYNC_EN : string := "FALSE" ; -- PCIe async enable - PCIE_TXBUF_EN : string := "FALSE" ; -- PCIe TX buffer enable for Gen1/Gen2 only - PCIE_CLK_SHARING_EN : string := "FALSE" ; -- Enable Clock Sharing - PCIE_LANE : integer := 8 ; -- PCIe number of lanes - PCIE_LINK_SPEED : integer := 3 ; -- PCIe Maximum Link Speed - PCIE_REFCLK_FREQ : integer := 0 ; -- PCIe Reference Clock Frequency - PCIE_USERCLK1_FREQ : integer := 5 ; -- PCIe Core Clock Frequency - Core Clock Freq - PCIE_USERCLK2_FREQ : integer := 4 ; -- PCIe User Clock Frequency - User Clock Freq - PCIE_OOBCLK_MODE : integer := 1 ; - PCIE_DEBUG_MODE : integer := 0 -- Debug Enable - ); - port - ( - - ---------- Input ------------------------------------- - CLK_CLK : in std_logic; - CLK_TXOUTCLK : in std_logic; -- Reference clock from lane 0 - CLK_RXOUTCLK_IN : in std_logic_vector(7 downto 0); - CLK_RST_N : in std_logic; -- Allow system reset for error_recovery - CLK_PCLK_SEL : in std_logic_vector(7 downto 0); - CLK_PCLK_SEL_SLAVE : in std_logic_vector(7 downto 0); - CLK_GEN3 : in std_logic; - - ---------- Output ------------------------------------ - CLK_PCLK : out std_logic; - CLK_PCLK_SLAVE : out std_logic; - CLK_RXUSRCLK : out std_logic; - CLK_RXOUTCLK_OUT : out std_logic_vector(7 downto 0); - CLK_DCLK : out std_logic; - CLK_OOBCLK : out std_logic; - CLK_USERCLK1 : out std_logic; - CLK_USERCLK2 : out std_logic; - CLK_MMCM_LOCK : out std_logic - + generic( + PCIE_ASYNC_EN : string; + PCIE_CLK_SHARING_EN : string; + PCIE_LANE : integer; + PCIE_LINK_SPEED : integer; + PCIE_REFCLK_FREQ : integer; + PCIE_USERCLK1_FREQ : integer; + PCIE_USERCLK2_FREQ : integer; + PCIE_OOBCLK_MODE : integer; + PCIE_DEBUG_MODE : integer + ); + port( + CLK_TXOUTCLK : in std_logic; + CLK_RXOUTCLK_IN : in std_logic_vector(PCIE_LANE - 1 downto 0); + CLK_RST_N : in std_logic; + CLK_PCLK_SEL : in std_logic_vector(PCIE_LANE - 1 downto 0); + CLK_PCLK_SEL_SLAVE : in std_logic_vector(PCIE_LANE - 1 downto 0); + CLK_PCLK : out std_logic; + CLK_PCLK_SLAVE : out std_logic; + CLK_RXUSRCLK : out std_logic; + CLK_RXOUTCLK_OUT : out std_logic_vector(PCIE_LANE - 1 downto 0); + CLK_DCLK : out std_logic; + CLK_OOBCLK : out std_logic; + CLK_USERCLK1 : out std_logic; + CLK_USERCLK2 : out std_logic; + CLK_MMCM_LOCK : out std_logic ); - end component; + end component pcie_clocking; COMPONENT pcie_x8_gen3_3_0 -- @suppress "Component declaration is not equal to its matching entity" PORT ( @@ -674,25 +664,25 @@ type devid_array is array(0 to 1) of std_logic_vector(15 downto 0); user_clk : OUT STD_LOGIC; user_reset : OUT STD_LOGIC; user_lnk_up : OUT STD_LOGIC; - s_axis_rq_tdata : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + s_axis_rq_tdata : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); s_axis_rq_tkeep : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s_axis_rq_tlast : IN STD_LOGIC; s_axis_rq_tready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axis_rq_tuser : IN STD_LOGIC_VECTOR(136 DOWNTO 0); s_axis_rq_tvalid : IN STD_LOGIC; - m_axis_rc_tdata : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + m_axis_rc_tdata : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); m_axis_rc_tkeep : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); m_axis_rc_tlast : OUT STD_LOGIC; m_axis_rc_tready : IN STD_LOGIC; m_axis_rc_tuser : OUT STD_LOGIC_VECTOR(160 DOWNTO 0); m_axis_rc_tvalid : OUT STD_LOGIC; - m_axis_cq_tdata : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + m_axis_cq_tdata : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); m_axis_cq_tkeep : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); m_axis_cq_tlast : OUT STD_LOGIC; m_axis_cq_tready : IN STD_LOGIC; m_axis_cq_tuser : OUT STD_LOGIC_VECTOR(182 DOWNTO 0); m_axis_cq_tvalid : OUT STD_LOGIC; - s_axis_cc_tdata : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + s_axis_cc_tdata : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); s_axis_cc_tkeep : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s_axis_cc_tlast : IN STD_LOGIC; s_axis_cc_tready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); @@ -828,25 +818,25 @@ type devid_array is array(0 to 1) of std_logic_vector(15 downto 0); user_clk : OUT STD_LOGIC; user_reset : OUT STD_LOGIC; user_lnk_up : OUT STD_LOGIC; - s_axis_rq_tdata : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + s_axis_rq_tdata : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); s_axis_rq_tkeep : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s_axis_rq_tlast : IN STD_LOGIC; s_axis_rq_tready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axis_rq_tuser : IN STD_LOGIC_VECTOR(136 DOWNTO 0); s_axis_rq_tvalid : IN STD_LOGIC; - m_axis_rc_tdata : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + m_axis_rc_tdata : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); m_axis_rc_tkeep : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); m_axis_rc_tlast : OUT STD_LOGIC; m_axis_rc_tready : IN STD_LOGIC; m_axis_rc_tuser : OUT STD_LOGIC_VECTOR(160 DOWNTO 0); m_axis_rc_tvalid : OUT STD_LOGIC; - m_axis_cq_tdata : OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + m_axis_cq_tdata : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); m_axis_cq_tkeep : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); m_axis_cq_tlast : OUT STD_LOGIC; m_axis_cq_tready : IN STD_LOGIC; m_axis_cq_tuser : OUT STD_LOGIC_VECTOR(182 DOWNTO 0); m_axis_cq_tvalid : OUT STD_LOGIC; - s_axis_cc_tdata : IN STD_LOGIC_VECTOR(511 DOWNTO 0); + s_axis_cc_tdata : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); s_axis_cc_tkeep : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s_axis_cc_tlast : IN STD_LOGIC; s_axis_cc_tready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); @@ -1123,13 +1113,13 @@ port ( GT_PCIEA0_TX_0_txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); GT_REFCLK0_D_0_clk_n : in STD_LOGIC; GT_REFCLK0_D_0_clk_p : in STD_LOGIC; - M_AXIS_PCIE0_CQ_0_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 ); + M_AXIS_PCIE0_CQ_0_tdata : out STD_LOGIC_VECTOR ( DATA_WIDTH-1 downto 0 ); M_AXIS_PCIE0_CQ_0_tkeep : out STD_LOGIC_VECTOR ( 15 downto 0 ); M_AXIS_PCIE0_CQ_0_tlast : out STD_LOGIC; M_AXIS_PCIE0_CQ_0_tready : in STD_LOGIC; M_AXIS_PCIE0_CQ_0_tuser : out STD_LOGIC_VECTOR ( 228 downto 0 ); M_AXIS_PCIE0_CQ_0_tvalid : out STD_LOGIC; - M_AXIS_PCIE0_RC_0_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 ); + M_AXIS_PCIE0_RC_0_tdata : out STD_LOGIC_VECTOR ( DATA_WIDTH-1 downto 0 ); M_AXIS_PCIE0_RC_0_tkeep : out STD_LOGIC_VECTOR ( 15 downto 0 ); M_AXIS_PCIE0_RC_0_tlast : out STD_LOGIC; M_AXIS_PCIE0_RC_0_tready : in STD_LOGIC; @@ -1191,13 +1181,13 @@ port ( PCIE0_CFG_STS_0_tph_requester_enable : out STD_LOGIC_VECTOR ( 3 downto 0 ); PCIE0_CFG_STS_0_tph_st_mode : out STD_LOGIC_VECTOR ( 11 downto 0 ); PCIE0_CFG_STS_0_tx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 ); - S_AXIS_PCIE0_CC_0_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 ); + S_AXIS_PCIE0_CC_0_tdata : in STD_LOGIC_VECTOR ( DATA_WIDTH-1 downto 0 ); S_AXIS_PCIE0_CC_0_tkeep : in STD_LOGIC_VECTOR ( 15 downto 0 ); S_AXIS_PCIE0_CC_0_tlast : in STD_LOGIC; S_AXIS_PCIE0_CC_0_tready : out STD_LOGIC; S_AXIS_PCIE0_CC_0_tuser : in STD_LOGIC_VECTOR ( 80 downto 0 ); S_AXIS_PCIE0_CC_0_tvalid : in STD_LOGIC; - S_AXIS_PCIE0_RQ_0_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 ); + S_AXIS_PCIE0_RQ_0_tdata : in STD_LOGIC_VECTOR ( DATA_WIDTH-1 downto 0 ); S_AXIS_PCIE0_RQ_0_tkeep : in STD_LOGIC_VECTOR ( 15 downto 0 ); S_AXIS_PCIE0_RQ_0_tlast : in STD_LOGIC; S_AXIS_PCIE0_RQ_0_tready : out STD_LOGIC; @@ -1229,7 +1219,7 @@ port ( signal pipe_rxoutclk_out: std_logic_vector(7 downto 0); signal pipe_pclk_sel_out: std_logic_vector(7 downto 0); signal pipe_mmcm_rst_n : std_logic; - signal pipe_gen3_out : std_logic; + --signal pipe_gen3_out : std_logic; signal cfg_power_state_change_ack : std_logic; @@ -1285,7 +1275,7 @@ begin pipe_txoutclk_out => pipe_txoutclk_out, pipe_rxoutclk_out => pipe_rxoutclk_out, pipe_pclk_sel_out => pipe_pclk_sel_out, - pipe_gen3_out => pipe_gen3_out, + pipe_gen3_out => open, --pipe_gen3_out, pipe_mmcm_rst_n => pipe_mmcm_rst_n, mmcm_lock => open, user_clk => user_clk, @@ -1417,7 +1407,7 @@ begin pipe_clock0: pcie_clocking generic map( PCIE_ASYNC_EN => "FALSE" , -- PCIe async enable - PCIE_TXBUF_EN => "FALSE" , -- PCIe TX buffer enable for Gen1/Gen2 only + --PCIE_TXBUF_EN => "FALSE" , -- PCIe TX buffer enable for Gen1/Gen2 only PCIE_CLK_SHARING_EN => "FALSE" , -- Enable Clock Sharing PCIE_LANE => 8 , -- PCIe number of lanes PCIE_LINK_SPEED => 3 , -- PCIe Maximum Link Speed @@ -1428,15 +1418,15 @@ begin PCIE_DEBUG_MODE => 0 -- Debug Enable ) port map - ( + ( ---------- Input ------------------------------------- - CLK_CLK => ( sys_clk ), + --CLK_CLK => ( sys_clk ), CLK_TXOUTCLK => ( pipe_txoutclk_out ), -- Reference clock from lane 0 CLK_RXOUTCLK_IN => ( pipe_rxoutclk_out ), CLK_RST_N => ( pipe_mmcm_rst_n ), -- Allow system reset for error_recovery CLK_PCLK_SEL => ( pipe_pclk_sel_out ), CLK_PCLK_SEL_SLAVE => ( x"00"), - CLK_GEN3 => ( pipe_gen3_out ), + --CLK_GEN3 => ( pipe_gen3_out ), ---------- Output ------------------------------------ CLK_PCLK => ( pipe_pclk_in), @@ -1863,7 +1853,7 @@ begin user_clk => user_clk, user_reset => user_reset, user_lnk_up => user_lnk_up, - s_axis_rq_tdata => s_axis_rq.tdata, + s_axis_rq_tdata => s_axis_rq.tdata(DATA_WIDTH-1 downto 0), s_axis_rq_tkeep => s_axis_rq.tkeep, s_axis_rq_tlast => s_axis_rq.tlast, s_axis_rq_tready => s_axis_rq_tready, @@ -1873,19 +1863,19 @@ begin --27:26 => "01" : is_eop for single TLP s_axis_rq_tuser => s_axis_rq_tuser, s_axis_rq_tvalid => s_axis_rq.tvalid, - m_axis_rc_tdata => m_axis_rc_s.tdata, + m_axis_rc_tdata => m_axis_rc_s.tdata(DATA_WIDTH-1 downto 0), m_axis_rc_tkeep => m_axis_rc_s.tkeep, m_axis_rc_tlast => m_axis_rc_s.tlast, m_axis_rc_tready => m_axis_r_rc.tready, m_axis_rc_tuser => open, m_axis_rc_tvalid => m_axis_rc_s.tvalid, - m_axis_cq_tdata => m_axis_cq_s.tdata, + m_axis_cq_tdata => m_axis_cq_s.tdata(DATA_WIDTH-1 downto 0), m_axis_cq_tkeep => m_axis_cq_s.tkeep, m_axis_cq_tlast => m_axis_cq_s.tlast, m_axis_cq_tready => m_axis_r_cq.tready, m_axis_cq_tuser => m_axis_cq_s.tuser, m_axis_cq_tvalid => m_axis_cq_s.tvalid, - s_axis_cc_tdata => s_axis_cc.tdata, + s_axis_cc_tdata => s_axis_cc.tdata(DATA_WIDTH-1 downto 0), s_axis_cc_tkeep => s_axis_cc.tkeep, s_axis_cc_tlast => s_axis_cc.tlast, s_axis_cc_tready => s_axis_cc_tready, @@ -2021,7 +2011,7 @@ begin user_clk => user_clk, user_reset => user_reset, user_lnk_up => user_lnk_up, - s_axis_rq_tdata => s_axis_rq.tdata, + s_axis_rq_tdata => s_axis_rq.tdata(DATA_WIDTH-1 downto 0), s_axis_rq_tkeep => s_axis_rq.tkeep, s_axis_rq_tlast => s_axis_rq.tlast, s_axis_rq_tready => s_axis_rq_tready, @@ -2031,19 +2021,19 @@ begin --27:26 => "01" : is_eop for single TLP s_axis_rq_tuser => s_axis_rq_tuser, s_axis_rq_tvalid => s_axis_rq.tvalid, - m_axis_rc_tdata => m_axis_rc_s.tdata, + m_axis_rc_tdata => m_axis_rc_s.tdata(DATA_WIDTH-1 downto 0), m_axis_rc_tkeep => m_axis_rc_s.tkeep, m_axis_rc_tlast => m_axis_rc_s.tlast, m_axis_rc_tready => m_axis_r_rc.tready, m_axis_rc_tuser => open, m_axis_rc_tvalid => m_axis_rc_s.tvalid, - m_axis_cq_tdata => m_axis_cq_s.tdata, + m_axis_cq_tdata => m_axis_cq_s.tdata(DATA_WIDTH-1 downto 0), m_axis_cq_tkeep => m_axis_cq_s.tkeep, m_axis_cq_tlast => m_axis_cq_s.tlast, m_axis_cq_tready => m_axis_r_cq.tready, m_axis_cq_tuser => m_axis_cq_s.tuser, m_axis_cq_tvalid => m_axis_cq_s.tvalid, - s_axis_cc_tdata => s_axis_cc.tdata, + s_axis_cc_tdata => s_axis_cc.tdata(DATA_WIDTH-1 downto 0), s_axis_cc_tkeep => s_axis_cc.tkeep, s_axis_cc_tlast => s_axis_cc.tlast, s_axis_cc_tready => s_axis_cc_tready, @@ -2232,23 +2222,23 @@ begin ila0: ila_0 port map ( clk => user_clk, - probe0 => s_axis_rq.tdata, + probe0 => s_axis_rq.tdata(DATA_WIDTH-1 downto 0), probe1 => s_axis_rq.tkeep, probe2(0) => s_axis_rq.tlast, probe3(0) => s_axis_rq_tready(0), probe4(0) => s_axis_rq.tvalid, - probe5 => m_axis_rc_s.tdata, + probe5 => m_axis_rc_s.tdata(DATA_WIDTH-1 downto 0), probe6 => m_axis_rc_s.tkeep, probe7(0) => m_axis_rc_s.tlast, probe8(0) => m_axis_r_rc.tready, probe9(0) => m_axis_rc_s.tvalid, - probe10 => m_axis_cq_s.tdata, + probe10 => m_axis_cq_s.tdata(DATA_WIDTH-1 downto 0), probe11 => m_axis_cq_s.tkeep, probe12(0) => m_axis_cq_s.tlast, probe13(0) => m_axis_r_cq.tready, probe14 => m_axis_cq_s.tuser, probe15(0) => m_axis_cq_s.tvalid, - probe16 => s_axis_cc.tdata, + probe16 => s_axis_cc.tdata(DATA_WIDTH-1 downto 0), probe17 => s_axis_cc.tkeep, probe18(0) => s_axis_cc.tlast, probe19(0) => s_axis_cc_tready(0), @@ -2366,13 +2356,13 @@ begin GT_PCIEA0_TX_0_txp => pci_exp_txp(7 downto 0), --: out STD_LOGIC_VECTOR ( 7 downto 0 ); GT_REFCLK0_D_0_clk_n => sys_clk_n, --: in STD_LOGIC; GT_REFCLK0_D_0_clk_p => sys_clk_p, --: in STD_LOGIC; - M_AXIS_PCIE0_CQ_0_tdata => m_axis_cq_s.tdata, --: out STD_LOGIC_VECTOR ( 511 downto 0 ); + M_AXIS_PCIE0_CQ_0_tdata => m_axis_cq_s.tdata(DATA_WIDTH-1 downto 0), --: out STD_LOGIC_VECTOR ( 511 downto 0 ); M_AXIS_PCIE0_CQ_0_tkeep => m_axis_cq_s.tkeep, --: out STD_LOGIC_VECTOR ( 15 downto 0 ); M_AXIS_PCIE0_CQ_0_tlast => m_axis_cq_s.tlast, --: out STD_LOGIC; M_AXIS_PCIE0_CQ_0_tready => m_axis_r_cq.tready, --: in STD_LOGIC; M_AXIS_PCIE0_CQ_0_tuser => m_axis_cq_tuser_s, --: out STD_LOGIC_VECTOR ( 228 downto 0 ); M_AXIS_PCIE0_CQ_0_tvalid => m_axis_cq_s.tvalid, --: out STD_LOGIC; - M_AXIS_PCIE0_RC_0_tdata => m_axis_rc_s.tdata, --: out STD_LOGIC_VECTOR ( 511 downto 0 ); + M_AXIS_PCIE0_RC_0_tdata => m_axis_rc_s.tdata(DATA_WIDTH-1 downto 0), --: out STD_LOGIC_VECTOR ( 511 downto 0 ); M_AXIS_PCIE0_RC_0_tkeep => m_axis_rc_s.tkeep, --: out STD_LOGIC_VECTOR ( 15 downto 0 ); M_AXIS_PCIE0_RC_0_tlast => m_axis_rc_s.tlast, --: out STD_LOGIC; M_AXIS_PCIE0_RC_0_tready => m_axis_r_rc.tready, --: in STD_LOGIC; @@ -2389,13 +2379,13 @@ begin PCIE0_CFG_MSIX_0_vec_pending_status => open, --: out STD_LOGIC; PCIE0_CFG_MSIX_0_function_number => x"00", PCIE0_CFG_MSIX_0_mint_vector => x"00000000", - S_AXIS_PCIE0_CC_0_tdata => s_axis_cc.tdata, --: in STD_LOGIC_VECTOR ( 511 downto 0 ); + S_AXIS_PCIE0_CC_0_tdata => s_axis_cc.tdata(DATA_WIDTH-1 downto 0), --: in STD_LOGIC_VECTOR ( 511 downto 0 ); S_AXIS_PCIE0_CC_0_tkeep => s_axis_cc.tkeep, --: in STD_LOGIC_VECTOR ( 15 downto 0 ); S_AXIS_PCIE0_CC_0_tlast => s_axis_cc.tlast, --: in STD_LOGIC; S_AXIS_PCIE0_CC_0_tready => s_axis_cc_tready(0), --: out STD_LOGIC; S_AXIS_PCIE0_CC_0_tuser => (others => '0'), --: in STD_LOGIC_VECTOR ( 80 downto 0 ); S_AXIS_PCIE0_CC_0_tvalid => s_axis_cc.tvalid, --: in STD_LOGIC; - S_AXIS_PCIE0_RQ_0_tdata => s_axis_rq.tdata, --: in STD_LOGIC_VECTOR ( 511 downto 0 ); + S_AXIS_PCIE0_RQ_0_tdata => s_axis_rq.tdata(DATA_WIDTH-1 downto 0), --: in STD_LOGIC_VECTOR ( 511 downto 0 ); S_AXIS_PCIE0_RQ_0_tkeep => s_axis_rq.tkeep, --: in STD_LOGIC_VECTOR ( 15 downto 0 ); S_AXIS_PCIE0_RQ_0_tlast => s_axis_rq.tlast, --: in STD_LOGIC; S_AXIS_PCIE0_RQ_0_tready => s_axis_rq_tready(0), --: out STD_LOGIC; @@ -2414,23 +2404,23 @@ begin ila0: ila_0 port map ( clk => user_clk, - probe0 => s_axis_rq.tdata, + probe0 => s_axis_rq.tdata(DATA_WIDTH-1 downto 0), probe1 => s_axis_rq.tkeep, probe2(0) => s_axis_rq.tlast, probe3(0) => s_axis_rq_tready(0), probe4(0) => s_axis_rq.tvalid, - probe5 => m_axis_rc_s.tdata, + probe5 => m_axis_rc_s.tdata(DATA_WIDTH-1 downto 0), probe6 => m_axis_rc_s.tkeep, probe7(0) => m_axis_rc_s.tlast, probe8(0) => m_axis_r_rc.tready, probe9(0) => m_axis_rc_s.tvalid, - probe10 => m_axis_cq_s.tdata, + probe10 => m_axis_cq_s.tdata(DATA_WIDTH-1 downto 0), probe11 => m_axis_cq_s.tkeep, probe12(0) => m_axis_cq_s.tlast, probe13(0) => m_axis_r_cq.tready, probe14 => m_axis_cq_s.tuser, probe15(0) => m_axis_cq_s.tvalid, - probe16 => s_axis_cc.tdata, + probe16 => s_axis_cc.tdata(DATA_WIDTH-1 downto 0), probe17 => s_axis_cc.tkeep, probe18(0) => s_axis_cc.tlast, probe19(0) => s_axis_cc_tready(0), diff --git a/sources/pcie/pcie_init.vhd b/sources/pcie/pcie_init.vhd index b35110f9d594ac88f6ef4e1ea7cf93ef5483fe74..fadec6705ddc1f75575d9e5a8f08f3012d334642 100644 --- a/sources/pcie/pcie_init.vhd +++ b/sources/pcie/pcie_init.vhd @@ -52,17 +52,17 @@ library ieee, UNISIM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +--use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity pcie_init is port ( - cfg_fc_cpld : in std_logic_vector(11 downto 0); - cfg_fc_cplh : in std_logic_vector(7 downto 0); - cfg_fc_npd : in std_logic_vector(11 downto 0); - cfg_fc_nph : in std_logic_vector(7 downto 0); - cfg_fc_pd : in std_logic_vector(11 downto 0); - cfg_fc_ph : in std_logic_vector(7 downto 0); + --cfg_fc_cpld : in std_logic_vector(11 downto 0); + --cfg_fc_cplh : in std_logic_vector(7 downto 0); + --cfg_fc_npd : in std_logic_vector(11 downto 0); + --cfg_fc_nph : in std_logic_vector(7 downto 0); + --cfg_fc_pd : in std_logic_vector(11 downto 0); + --cfg_fc_ph : in std_logic_vector(7 downto 0); cfg_fc_sel : out std_logic_vector(2 downto 0); cfg_mgmt_addr : out std_logic_vector(18 downto 0); cfg_mgmt_byte_enable : out std_logic_vector(3 downto 0); @@ -79,14 +79,14 @@ end entity pcie_init; architecture rtl of pcie_init is - signal s_cfg_fc_cpld : std_logic_vector(11 downto 0); - signal s_cfg_fc_cplh : std_logic_vector(7 downto 0); - signal s_cfg_fc_npd : std_logic_vector(11 downto 0); - signal s_cfg_fc_nph : std_logic_vector(7 downto 0); - signal s_cfg_fc_pd : std_logic_vector(11 downto 0); - signal s_cfg_fc_ph : std_logic_vector(7 downto 0); + --signal s_cfg_fc_cpld : std_logic_vector(11 downto 0); + --signal s_cfg_fc_cplh : std_logic_vector(7 downto 0); + --signal s_cfg_fc_npd : std_logic_vector(11 downto 0); + --signal s_cfg_fc_nph : std_logic_vector(7 downto 0); + --signal s_cfg_fc_pd : std_logic_vector(11 downto 0); + --signal s_cfg_fc_ph : std_logic_vector(7 downto 0); - attribute dont_touch : string; + --attribute dont_touch : string; --attribute dont_touch of s_cfg_fc_cpld : signal is "true"; --attribute dont_touch of s_cfg_fc_cplh : signal is "true"; --attribute dont_touch of s_cfg_fc_npd : signal is "true"; @@ -95,15 +95,15 @@ architecture rtl of pcie_init is --attribute dont_touch of s_cfg_fc_ph : signal is "true"; signal write_cfg_done_1: std_logic; - signal bar_index : std_logic_vector(2 downto 0); + --signal bar_index : std_logic_vector(2 downto 0); signal uncor_err_stat: std_logic_vector(31 downto 0); --config register 104 signal cor_err_stat: std_logic_vector(31 downto 0); --config register 110 signal adv_err_cap: std_logic_vector(31 downto 0); --config register 118 - attribute dont_touch of uncor_err_stat : signal is "true"; - attribute dont_touch of cor_err_stat : signal is "true"; - attribute dont_touch of adv_err_cap : signal is "true"; + --attribute dont_touch of uncor_err_stat : signal is "true"; + --attribute dont_touch of cor_err_stat : signal is "true"; + --attribute dont_touch of adv_err_cap : signal is "true"; @@ -114,12 +114,12 @@ begin cfg_fc_sel <= "100"; - s_cfg_fc_cpld <= cfg_fc_cpld ; - s_cfg_fc_cplh <= cfg_fc_cplh ; - s_cfg_fc_npd <= cfg_fc_npd ; - s_cfg_fc_nph <= cfg_fc_nph ; - s_cfg_fc_pd <= cfg_fc_pd ; - s_cfg_fc_ph <= cfg_fc_ph ; + --s_cfg_fc_cpld <= cfg_fc_cpld ; + --s_cfg_fc_cplh <= cfg_fc_cplh ; + --s_cfg_fc_npd <= cfg_fc_npd ; + --s_cfg_fc_nph <= cfg_fc_nph ; + --s_cfg_fc_pd <= cfg_fc_pd ; + --s_cfg_fc_ph <= cfg_fc_ph ; cfg_write_skp_nolfsr : process(clk) begin @@ -136,7 +136,7 @@ begin cfg_mgmt_write <= '0'; cfg_mgmt_read <= '0'; write_cfg_done_1 <= '0'; - bar_index <= "000"; + --bar_index <= "000"; -- elsif(write_cfg_done_1 = '1') then -- case(bar_index) is -- when "000" => diff --git a/sources/pcie/pcie_slow_clock.vhd b/sources/pcie/pcie_slow_clock.vhd index fa41f9142fc86b1918ab8976d900950de7086c57..db442f07d6c4ad0aa662e6dd67648adac73cca5c 100644 --- a/sources/pcie/pcie_slow_clock.vhd +++ b/sources/pcie/pcie_slow_clock.vhd @@ -50,7 +50,7 @@ library ieee, UNISIM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use ieee.std_logic_1164.all; entity pcie_slow_clock is @@ -66,16 +66,13 @@ end entity pcie_slow_clock; architecture rtl of pcie_slow_clock is component clk_wiz_regmap -port - (-- Clock in ports - clk_in1 : in std_logic; - -- Clock out ports - clk_out25 : out std_logic; - -- Status and control signals - reset : in std_logic; - locked : out std_logic - ); -end component; + port( + clk_out25 : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); +end component clk_wiz_regmap; @@ -93,14 +90,10 @@ regmap_clk <= regmap_clk_s; clk0 : clk_wiz_regmap port map ( - - -- Clock in ports - clk_in1 => clk, - -- Clock out ports clk_out25 => regmap_clk_s, - -- Status and control signals reset => reset_s, - locked => locked_s + locked => locked_s, + clk_in1 => clk ); diff --git a/sources/pcie/wupper_core.vhd b/sources/pcie/wupper_core.vhd index 22130ef2db032e020215eb11ce7ab27f557ea69f..fc6a39d1aa8ea8e061b22d6a338e14e073d21d60 100644 --- a/sources/pcie/wupper_core.vhd +++ b/sources/pcie/wupper_core.vhd @@ -49,10 +49,10 @@ -library ieee, UNISIM, work; +library ieee, UNISIM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use ieee.std_logic_1164.all; use work.pcie_package.all; @@ -60,7 +60,6 @@ entity wupper_core is generic( NUMBER_OF_DESCRIPTORS : integer := 8; NUMBER_OF_INTERRUPTS : integer := 8; - SVN_VERSION : integer := 0; BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE"; CARD_TYPE : integer := 710; GIT_HASH : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000"; @@ -108,8 +107,7 @@ entity wupper_core is toHostFifo_re : out std_logic; tohost_busy_out : out std_logic; tohost_pfull_threshold_assert : out std_logic_vector(11 downto 0); - tohost_pfull_threshold_negate : out std_logic_vector(11 downto 0); - user_lnk_up : in std_logic); + tohost_pfull_threshold_negate : out std_logic_vector(11 downto 0)); end entity wupper_core; @@ -149,48 +147,46 @@ begin u1: entity work.dma_control generic map( NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS, - NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS, - SVN_VERSION => SVN_VERSION, - BUILD_DATETIME => BUILD_DATETIME, - CARD_TYPE => CARD_TYPE, - GIT_HASH => GIT_HASH, - COMMIT_DATETIME => COMMIT_DATETIME, - GIT_TAG => GIT_TAG, - GIT_COMMIT_NUMBER => GIT_COMMIT_NUMBER, + NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS, + CARD_TYPE => CARD_TYPE, + BUILD_DATETIME => BUILD_DATETIME, + GIT_HASH => GIT_HASH, + GIT_TAG => GIT_TAG, + GIT_COMMIT_NUMBER => GIT_COMMIT_NUMBER, + COMMIT_DATETIME => COMMIT_DATETIME, GBT_GENERATE_ALL_REGS => GBT_GENERATE_ALL_REGS, - EMU_GENERATE_REGS => EMU_GENERATE_REGS, - MROD_GENERATE_REGS => MROD_GENERATE_REGS, - FIRMWARE_MODE => FIRMWARE_MODE, - GBT_NUM => GBT_NUM, - PCIE_ENDPOINT => PCIE_ENDPOINT, - DATA_WIDTH => DATA_WIDTH, - BLOCKSIZE => BLOCKSIZE) + EMU_GENERATE_REGS => EMU_GENERATE_REGS, + GBT_NUM => GBT_NUM, + FIRMWARE_MODE => FIRMWARE_MODE, + MROD_GENERATE_REGS => MROD_GENERATE_REGS, + PCIE_ENDPOINT => PCIE_ENDPOINT, + DATA_WIDTH => DATA_WIDTH, + BLOCKSIZE => BLOCKSIZE) port map( - clk => clk, - regmap_clk => regmap_clk, - dma_descriptors => u1_dma_descriptors, - dma_soft_reset => dma_soft_reset, - dma_status => dma_status, - flush_fifo => flush_fifo, - interrupt_vector => interrupt_vector, - m_axis_cc => m_axis_cc, - m_axis_r_cc => m_axis_r_cc, - reset => reset, - reset_global_soft => reset_global_soft, - s_axis_cq => s_axis_cq, - s_axis_r_cq => s_axis_r_cq, - register_map_monitor => register_map_monitor, - register_map_control => register_map_control, - interrupt_table_en => interrupt_table_en, - dma_interrupt_call => dma_interrupt_call, - fifo_empty => toHostFifo_prog_empty, - fifo_full => fromHostFifo_prog_full, + clk => clk, + regmap_clk => regmap_clk, + dma_descriptors => u1_dma_descriptors, + dma_soft_reset => dma_soft_reset, + dma_status => dma_status, + flush_fifo => flush_fifo, + interrupt_table_en => interrupt_table_en, + interrupt_vector => interrupt_vector, + m_axis_cc => m_axis_cc, + m_axis_r_cc => m_axis_r_cc, + register_map_monitor => register_map_monitor, + register_map_control => register_map_control, + reset => reset, + reset_global_soft => reset_global_soft, + s_axis_cq => s_axis_cq, + s_axis_r_cq => s_axis_r_cq, + fifo_empty => toHostFifo_prog_empty, + dma_interrupt_call => dma_interrupt_call, fromhost_pfull_threshold_assert => fromhost_pfull_threshold_assert, fromhost_pfull_threshold_negate => fromhost_pfull_threshold_negate, - tohost_pfull_threshold_assert => tohost_pfull_threshold_assert, - tohost_pfull_threshold_negate => tohost_pfull_threshold_negate, - tohost_busy_out => tohost_busy_out, - fromhost_busy_out => fromhost_busy_out); + tohost_pfull_threshold_assert => tohost_pfull_threshold_assert, + tohost_pfull_threshold_negate => tohost_pfull_threshold_negate, + tohost_busy_out => tohost_busy_out, + fromhost_busy_out => fromhost_busy_out); end architecture structure ; -- of wupper_core diff --git a/sources/shared/dna.vhd b/sources/shared/dna.vhd index 6d54646bcab1e1688ff160683a303a284cad71f8..c1d114f1e6c86a4e1252d6e692e2bbbbb5f50f07 100644 --- a/sources/shared/dna.vhd +++ b/sources/shared/dna.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" Library UNISIM; use UNISIM.VCOMPONENTS.ALL; @@ -22,7 +22,7 @@ architecture rtl of dna is signal dna_read_q: std_logic; signal dna_shift_cnt: std_logic_vector(7 downto 0); signal dna_value: std_logic_vector(95 downto 0); - signal dna_ready: std_logic; + --signal dna_ready: std_logic; signal dna_dout_s: std_logic; begin @@ -46,7 +46,7 @@ g0: if (CARD_TYPE = 709 or CARD_TYPE = 710) generate ); - process(clk40, reset) + process(clk40) begin if(rising_edge(clk40)) then @@ -57,7 +57,7 @@ g0: if (CARD_TYPE = 709 or CARD_TYPE = 710) generate dna_shift_cnt <= "00111001"; --57 decimal dna_shift <= '0'; dna_value <= x"0000_0000_0000_0000_0000_0000"; - dna_ready <= '0'; + --dna_ready <= '0'; else dna_read_q <= '1'; dna_read <= '1' and (not dna_read_q); @@ -71,11 +71,11 @@ g0: if (CARD_TYPE = 709 or CARD_TYPE = 710) generate dna_shift_cnt <= dna_shift_cnt - "00000001"; end if; if(dna_shift_cnt = "00000000") then - dna_ready <= '1'; + --dna_ready <= '1'; dna_out <= dna_value(95 downto 0); else dna_out <= (others => '0'); - dna_ready <= '0'; + --dna_ready <= '0'; end if; end if; end if; @@ -96,7 +96,7 @@ DNA_PORT_inst : DNA_PORTE2 ); - process(clk40, reset) + process(clk40) begin if(rising_edge(clk40)) then @@ -107,7 +107,7 @@ DNA_PORT_inst : DNA_PORTE2 dna_shift_cnt <= "01100000"; --96 decimal dna_shift <= '0'; dna_value <= x"0000_0000_0000_0000_0000_0000"; - dna_ready <= '0'; + --dna_ready <= '0'; else dna_read_q <= '1'; dna_read <= '1' and (not dna_read_q); @@ -121,13 +121,13 @@ DNA_PORT_inst : DNA_PORTE2 dna_shift_cnt <= dna_shift_cnt - "00000001"; end if; if(dna_shift_cnt = "00000000") then - dna_ready <= '1'; + --dna_ready <= '1'; for i in 0 to 95 loop dna_out(i) <= dna_value(95 - i); end loop; else dna_out <= (others => '0'); - dna_ready <= '0'; + --dna_ready <= '0'; end if; end if; end if; diff --git a/sources/shared/pex_init.vhd b/sources/shared/pex_init.vhd index 09943087812b0f2db02de014bb6ce6243a99291b..2a7354f297666206f8323b738b52184d8581aa79 100644 --- a/sources/shared/pex_init.vhd +++ b/sources/shared/pex_init.vhd @@ -32,7 +32,7 @@ library ieee, UNISIM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use ieee.std_logic_1164.all; entity pex_init is @@ -53,39 +53,39 @@ entity pex_init is clk40 : in std_logic; lnk_up0 : in std_logic; lnk_up1 : in std_logic; - reset_pcie : out std_logic_vector(0 downto 0); + --reset_pcie : out std_logic_vector(0 downto 0); sys_reset_n : in std_logic); end entity pex_init; architecture rtl of pex_init is - component i2c_master_pex - PORT( - data_clk : IN std_logic; - no_data : in std_logic; - wr_mod : in std_logic; --'1' WR, '0' RD - reset_n : in std_logic; - special : IN std_logic; - ena : IN std_logic; - wr_data_update : out std_logic; - rd_data_refresh : out std_logic; - rd_number_in : in std_logic_vector(3 downto 0); - wr_number_in : in std_logic_vector(3 downto 0); - state_display : out std_logic_vector(4 DOWNTO 0); - addr : IN std_logic_vector(6 DOWNTO 0); - -- rw : IN std_logic; - data_wr : IN std_logic_vector(31 DOWNTO 0); - addr_wr : IN std_logic_vector(31 DOWNTO 0); - data_rd : OUT std_logic_vector(31 DOWNTO 0); - i2c_process_finished : out std_logic; - ack_error_o : OUT std_logic; - sda : INOUT std_logic; - scl : out std_logic; - sda_o_debug : out std_logic; - sda_i_debug : OUT std_logic - ); - END component; + --component i2c_master_pex + -- PORT( + -- data_clk : IN std_logic; + -- no_data : in std_logic; + -- wr_mod : in std_logic; --'1' WR, '0' RD + -- reset_n : in std_logic; + -- special : IN std_logic; + -- ena : IN std_logic; + -- wr_data_update : out std_logic; + -- rd_data_refresh : out std_logic; + -- rd_number_in : in std_logic_vector(3 downto 0); + -- wr_number_in : in std_logic_vector(3 downto 0); + -- state_display : out std_logic_vector(4 DOWNTO 0); + -- addr : IN std_logic_vector(6 DOWNTO 0); + -- -- rw : IN std_logic; + -- data_wr : IN std_logic_vector(31 DOWNTO 0); + -- addr_wr : IN std_logic_vector(31 DOWNTO 0); + -- data_rd : OUT std_logic_vector(31 DOWNTO 0); + -- i2c_process_finished : out std_logic; + -- ack_error_o : OUT std_logic; + -- sda : INOUT std_logic; + -- scl : out std_logic; + -- sda_o_debug : out std_logic; + -- sda_i_debug : OUT std_logic + -- ); + --END component; signal clk400k : std_logic:='0'; @@ -119,21 +119,21 @@ architecture rtl of pex_init is signal data_clk : std_logic; signal FSM_RST_ORIG : std_logic; signal FSM_RST_ORIG_r : std_logic; - signal manual_rst : std_logic_vector(0 downto 0); - signal lnk_up0_vec : std_logic_vector(0 downto 0); - signal lnk_up1_vec : std_logic_vector(0 downto 0); - signal PCIE_PERSTn1_vec : std_logic_vector(0 downto 0); - signal PCIE_PERSTn2_vec : std_logic_vector(0 downto 0); + --signal manual_rst : std_logic_vector(0 downto 0); + --signal lnk_up0_vec : std_logic_vector(0 downto 0); + --signal lnk_up1_vec : std_logic_vector(0 downto 0); + --signal PCIE_PERSTn1_vec : std_logic_vector(0 downto 0); + --signal PCIE_PERSTn2_vec : std_logic_vector(0 downto 0); signal i2c_address : std_logic_vector(6 downto 0); - function To_Std_Logic(L: BOOLEAN) return std_ulogic is - begin - if L then - return('1'); - else - return('0'); - end if; - end function To_Std_Logic; + --function To_Std_Logic(L: BOOLEAN) return std_ulogic is + --begin + -- if L then + -- return('1'); + -- else + -- return('0'); + -- end if; + --end function To_Std_Logic; begin @@ -165,8 +165,8 @@ begin ); - lnk_up0_vec(0) <= lnk_up0; - lnk_up1_vec(0) <= lnk_up1; + --lnk_up0_vec(0) <= lnk_up0; + --lnk_up1_vec(0) <= lnk_up1; I2C_SMB <= '0'; I2C_SMBUS_CFG_nEN <= '0'; @@ -298,7 +298,7 @@ begin end if; when PHASE3 => PEX_STATE <= IDLE; - when others => + when others => -- @suppress "Case statement contains all choices explicitly. You can safely remove the redundant 'others'" PEX_STATE <= IDLE; end case; end if; diff --git a/sources/shared/xadc_drp.vhd b/sources/shared/xadc_drp.vhd index fc8ce2ee65e1752c8a7906edddefee1d83369e75..9f497dff86c528918308b9470c45453183f0146d 100644 --- a/sources/shared/xadc_drp.vhd +++ b/sources/shared/xadc_drp.vhd @@ -19,44 +19,43 @@ port( end xadc_drp; architecture rtl of xadc_drp is - -COMPONENT xadc_wiz_0 - PORT ( - di_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - daddr_in : IN STD_LOGIC_VECTOR(6 DOWNTO 0); - den_in : IN STD_LOGIC; - dwe_in : IN STD_LOGIC; - drdy_out : OUT STD_LOGIC; - do_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - dclk_in : IN STD_LOGIC; - reset_in : IN STD_LOGIC; - vp_in : IN STD_LOGIC; - vn_in : IN STD_LOGIC; - channel_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - eoc_out : OUT STD_LOGIC; - alarm_out : OUT STD_LOGIC; - eos_out : OUT STD_LOGIC; - busy_out : OUT STD_LOGIC - ); -END COMPONENT; + component xadc_wiz_0 + port( + daddr_in : in STD_LOGIC_VECTOR(6 downto 0); + den_in : in STD_LOGIC; + di_in : in STD_LOGIC_VECTOR(15 downto 0); + dwe_in : in STD_LOGIC; + do_out : out STD_LOGIC_VECTOR(15 downto 0); + drdy_out : out STD_LOGIC; + dclk_in : in STD_LOGIC; + reset_in : in STD_LOGIC; + busy_out : out STD_LOGIC; + channel_out : out STD_LOGIC_VECTOR(4 downto 0); + eoc_out : out STD_LOGIC; + eos_out : out STD_LOGIC; + alarm_out : out STD_LOGIC; + vp_in : in STD_LOGIC; + vn_in : in STD_LOGIC + ); + end component xadc_wiz_0; -COMPONENT system_management_wiz_0 - PORT ( - di_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - daddr_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - den_in : IN STD_LOGIC; - dwe_in : IN STD_LOGIC; - drdy_out : OUT STD_LOGIC; - do_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - dclk_in : IN STD_LOGIC; - reset_in : IN STD_LOGIC; - channel_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - eoc_out : OUT STD_LOGIC; - alarm_out : OUT STD_LOGIC; - eos_out : OUT STD_LOGIC; - busy_out : OUT STD_LOGIC - ); -END COMPONENT; +component system_management_wiz_0 + port( + daddr_in : in STD_LOGIC_VECTOR(7 downto 0); + den_in : in STD_LOGIC; + di_in : in STD_LOGIC_VECTOR(15 downto 0); + dwe_in : in STD_LOGIC; + do_out : out STD_LOGIC_VECTOR(15 downto 0); + drdy_out : out STD_LOGIC; + dclk_in : in STD_LOGIC; + reset_in : in STD_LOGIC; + busy_out : out STD_LOGIC; + channel_out : out STD_LOGIC_VECTOR(5 downto 0); + eoc_out : out STD_LOGIC; + eos_out : out STD_LOGIC; + alarm_out : out STD_LOGIC + ); +end component system_management_wiz_0; type state_type is (IDLE, READTEMP, READVCCINT, READVCCAUX, READVCCBRAM); signal state: state_type; @@ -67,13 +66,13 @@ signal den_in : std_logic; signal dwe_in : std_logic; signal drdy_out : std_logic; signal do_out : std_logic_vector(15 downto 0); -signal vp_in : std_logic; -signal vn_in : std_logic; +signal vp_in : std_logic; -- @suppress "signal vp_in is never written" +signal vn_in : std_logic; -- @suppress "signal vn_in is never written" --signal channel_out : std_logic_vector(4 downto 0); signal eoc_out : std_logic; -signal alarm_out : std_logic; -signal eos_out : std_logic; -signal busy_out : std_logic; +signal alarm_out : std_logic; -- @suppress "signal alarm_out is never read" +signal eos_out : std_logic; -- @suppress "signal eos_out is never read" +signal busy_out : std_logic; -- @suppress "signal busy_out is never read" signal temp_s : std_logic_vector(11 downto 0); signal vccint_s : std_logic_vector(11 downto 0); @@ -84,21 +83,21 @@ begin g0: if CARD_TYPE = 709 or CARD_TYPE = 710 generate xadc0 : xadc_wiz_0 PORT MAP ( - di_in => di_in, daddr_in => daddr_in, den_in => den_in, + di_in => di_in, dwe_in => dwe_in, - drdy_out => drdy_out, do_out => do_out, + drdy_out => drdy_out, dclk_in => clk40, reset_in => reset, - vp_in => vp_in, - vn_in => vn_in, + busy_out => busy_out, channel_out => open, eoc_out => eoc_out, - alarm_out => alarm_out, eos_out => eos_out, - busy_out => busy_out + alarm_out => alarm_out, + vp_in => vp_in, + vn_in => vn_in ); end generate; @@ -108,19 +107,19 @@ begin daddr_in_s <= "0" & daddr_in; xadc0 : system_management_wiz_0 PORT MAP ( - di_in => di_in, daddr_in => daddr_in_s, den_in => den_in, + di_in => di_in, dwe_in => dwe_in, - drdy_out => drdy_out, do_out => do_out, + drdy_out => drdy_out, dclk_in => clk40, reset_in => reset, + busy_out => busy_out, channel_out => open, eoc_out => eoc_out, - alarm_out => alarm_out, eos_out => eos_out, - busy_out => busy_out + alarm_out => alarm_out ); end generate; @@ -166,7 +165,7 @@ begin vccbram_s <= do_out(15 downto 4); state <= IDLE; end if; - when others => + when others => -- @suppress "Case statement contains all choices explicitly. You can safely remove the redundant 'others'" state <= IDLE; end case; end if; diff --git a/sources/spi/LMK03200_spi.vhd b/sources/spi/LMK03200_spi.vhd index 926f2f2494d9b9e1b7c507abd09c3d04ac75c97e..c3e6cfdf62fe99c8a4143cdde9868563044d13c8 100644 --- a/sources/spi/LMK03200_spi.vhd +++ b/sources/spi/LMK03200_spi.vhd @@ -5,8 +5,8 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_ARITH.ALL;-- @suppress "Deprecated package" +USE IEEE.STD_LOGIC_UNSIGNED.ALL;-- @suppress "Deprecated package" library UNISIM; use UNISIM.VComponents.all; @@ -36,8 +36,8 @@ architecture Behavioral of LMK03200_spi is signal LMK_STATE: fsm_state_type := FSM_IDLE; SIGNAL SPI_CLK : std_logic; signal LMK_DATA_wr32_shift :std_logic_vector(31 downto 0); - signal LMK_SPI_wr_6, wr_cnt : std_logic_vector(5 downto 0):="000000"; - signal LMK_SPI_wr_l, LMK_SPI_wr, LMK_SPI_wr_r,LMK_SPI_wr_l_r, clk_en :std_logic:='0'; + signal wr_cnt : std_logic_vector(5 downto 0):="000000"; + signal LMK_SPI_wr, LMK_SPI_wr_r, clk_en :std_logic:='0'; begin @@ -113,7 +113,7 @@ begin clk_en <= '1'; end if; - when others=> + when others=> -- @suppress "Case statement contains all choices explicitly. You can safely remove the redundant 'others'" LMK_STATE <= FSM_IDLE; LMK_WR_finished <= '0'; LMK_SPI_LE <= '1'; diff --git a/sources/spi/LMK03200_wrapper.vhd b/sources/spi/LMK03200_wrapper.vhd index fb5b0c7206b09a3a9cf4328ef54b9ae0885f9376..82d4b613f959567c07e59e631ea5f6690a6d6e0a 100644 --- a/sources/spi/LMK03200_wrapper.vhd +++ b/sources/spi/LMK03200_wrapper.vhd @@ -5,8 +5,8 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; +--use IEEE.STD_LOGIC_ARITH.ALL; +--USE IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; @@ -77,7 +77,7 @@ begin lmk_status <= CFG0; elsif (clk10m_in'event and clk10m_in='1') then case lmk_status is - when IDLE => + when IDLE => -- @suppress "Dead state 'IDLE': state does not have outgoing transitions" LMK_SYNCn <= '1'; LMK_GOE <= '1'; lmk_status <= IDLE; @@ -378,7 +378,7 @@ begin LMK_SYNCn <= '0'; LMK_GOE <= '1'; lmk_status <= IDLE; - when others => + when others => -- @suppress "Case statement contains all choices explicitly. You can safely remove the redundant 'others'" lmk_status <= IDLE; end case; end if; @@ -388,6 +388,7 @@ end process; lmk40m : OBUFDS generic map ( + CAPACITANCE => "DONT_CARE", IOSTANDARD => "DEFAULT", SLEW => "FAST" ) diff --git a/sources/templates/dma_control.vhd b/sources/templates/dma_control.vhd index 0a7157da22d2bf0898c4935fa98ac8b97b03d76a..141e9d04054f4fc2605043caa8a182539f796f4d 100644 --- a/sources/templates/dma_control.vhd +++ b/sources/templates/dma_control.vhd @@ -82,7 +82,6 @@ entity dma_control is generic( NUMBER_OF_DESCRIPTORS : integer := 8; NUMBER_OF_INTERRUPTS : integer := 16; - SVN_VERSION : integer := 0; CARD_TYPE : integer := 710; BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE"; GIT_HASH : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000"; @@ -114,7 +113,6 @@ entity dma_control is reset_global_soft : out std_logic; s_axis_cq : in axis_type; s_axis_r_cq : out axis_r_type; - fifo_full : in std_logic; fifo_empty : in std_logic_vector(NUMBER_OF_DESCRIPTORS-2 downto 0); dma_interrupt_call : out std_logic_vector(3 downto 0); fromhost_pfull_threshold_assert: out std_logic_vector(8 downto 0); @@ -131,7 +129,7 @@ architecture rtl of dma_control is type completer_state_type is(IDLE, READ_REGISTER, WRITE_REGISTER_READ, WRITE_REGISTER_MODIFYWRITE, WAIT_RW_DONE, SEND_UNKNOWN_REQUEST); signal completer_state: completer_state_type := IDLE; - signal completer_state_slv: std_logic_vector(2 downto 0); + signal completer_state_slv: std_logic_vector(2 downto 0); --@suppress attribute dont_touch : string; attribute dont_touch of completer_state_slv : signal is "true"; @@ -505,7 +503,7 @@ begin else completer_state <= IDLE; end if; - when others => + when others => -- @suppress "Case statement contains all choices explicitly. You can safely remove the redundant 'others'" completer_state <= IDLE; completer_state_slv <= IDLE_SLV; end case; @@ -543,8 +541,6 @@ begin variable register_write_enable_v : std_logic; variable register_write_data_v : std_logic_vector(63 downto 0); variable bar_id_v : std_logic_vector(2 downto 0); - variable bar1_v : std_logic_vector(31 downto 0); - variable bar2_v : std_logic_vector(31 downto 0); variable dma_descriptors_v : dma_descriptors_type(0 to 7); variable dma_status_v : dma_statuses_type(0 to 7); variable int_vector_v : interrupt_vectors_type(0 to NUMBER_OF_INTERRUPTS-1); @@ -10081,10 +10077,10 @@ end process; if (GBT_NUM > 3 and FIRMWARE_MODE = 5) then register_map_control_s.R3L1_CTRL (3)(3).R3_ENABLE <= REG_CR_ITK_R3L1_LINK_03_R3L1_3_R3_ENABLE_C; -- enables sending RoI R3 signals to the front-end end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_CTRL.OPTIONS <= REG_MROD_CTRL_OPTIONS_C; -- Extra options for MROD end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_CTRL.GOLTESTMODE <= REG_MROD_CTRL_GOLTESTMODE_C; -- GOL Test Mode (emulate CSM): -- 0: Run Data Emulator when 1; 0: stop, load emulator fifo -- 1: Enable Circulate when 1; 0: send fifo data only once @@ -10092,58 +10088,58 @@ end process; -- 3: Enable pattern generator when 1; 0: off end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_CSMENABLE <= REG_MROD_EP0_CSMENABLE_C; -- EP0 CSM Data Enable channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_EMPTYSUPPR <= REG_MROD_EP0_EMPTYSUPPR_C; -- EP0 Set Empty Suppression channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_HPTDCMODE <= REG_MROD_EP0_HPTDCMODE_C; -- EP0 Set HPTDC Mode channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_CLRFIFOS <= REG_MROD_EP0_CLRFIFOS_C; -- EP0 Clear FIFOs channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_EMULOADENA <= REG_MROD_EP0_EMULOADENA_C; -- EP0 Emulator Load Enable channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_TRXLOOPBACK <= REG_MROD_EP0_TRXLOOPBACK_C; -- EP0 Transceiver Loopback Enable channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_TXCVRRESET <= REG_MROD_EP0_TXCVRRESET_C; -- EP0 Transceiver Reset all channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_RXRESET <= REG_MROD_EP0_RXRESET_C; -- EP0 Receiver Reset channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_TXRESET <= REG_MROD_EP0_TXRESET_C; -- EP0 Transmitter Reset channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_CSMENABLE <= REG_MROD_EP1_CSMENABLE_C; -- EP1 CSM Data Enable channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_EMPTYSUPPR <= REG_MROD_EP1_EMPTYSUPPR_C; -- EP1 Set Empty Suppression channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_HPTDCMODE <= REG_MROD_EP1_HPTDCMODE_C; -- EP1 Set HPTDC Mode channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_CLRFIFOS <= REG_MROD_EP1_CLRFIFOS_C; -- EP1 Clear FIFOs channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_EMULOADENA <= REG_MROD_EP1_EMULOADENA_C; -- EP1 Emulator Load Enable channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_TRXLOOPBACK <= REG_MROD_EP1_TRXLOOPBACK_C; -- EP1 Transceiver Loopback Enable channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_TXCVRRESET <= REG_MROD_EP1_TXCVRRESET_C; -- EP1 Transceiver Reset all channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_RXRESET <= REG_MROD_EP1_RXRESET_C; -- EP1 Receiver Reset channel 23-0 end if; - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_TXRESET <= REG_MROD_EP1_TXRESET_C; -- EP1 Transmitter Reset channel 23-0 end if; ----------------------------------- @@ -17220,7 +17216,7 @@ end process; when REG_STRIPS_L1_TRIGGER => register_read_data_25_s(64 downto 64) <= register_map_control_s.STRIPS_L1_TRIGGER; -- (for tests only) simulate L1 trigger (issues 4-5 sequential triggers) when REG_STRIPS_R3L1_TRIGGER => register_read_data_25_s(64 downto 64) <= register_map_control_s.STRIPS_R3L1_TRIGGER; -- (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers) when REG_MROD_CTRL => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(15 downto 4) <= register_map_control_s.MROD_CTRL.OPTIONS; -- Extra options for MROD register_read_data_25_s(3 downto 0) <= register_map_control_s.MROD_CTRL.GOLTESTMODE; -- GOL Test Mode (emulate CSM): -- 0: Run Data Emulator when 1; 0: stop, load emulator fifo @@ -17230,75 +17226,75 @@ end process; end if; when REG_MROD_EP0_CSMENABLE => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_CSMENABLE; -- EP0 CSM Data Enable channel 23-0 end if; when REG_MROD_EP0_EMPTYSUPPR => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_EMPTYSUPPR; -- EP0 Set Empty Suppression channel 23-0 end if; when REG_MROD_EP0_HPTDCMODE => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_HPTDCMODE; -- EP0 Set HPTDC Mode channel 23-0 end if; when REG_MROD_EP0_CLRFIFOS => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_CLRFIFOS; -- EP0 Clear FIFOs channel 23-0 end if; when REG_MROD_EP0_EMULOADENA => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_EMULOADENA; -- EP0 Emulator Load Enable channel 23-0 end if; when REG_MROD_EP0_TRXLOOPBACK => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_TRXLOOPBACK; -- EP0 Transceiver Loopback Enable channel 23-0 end if; when REG_MROD_EP0_TXCVRRESET => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_TXCVRRESET; -- EP0 Transceiver Reset all channel 23-0 end if; when REG_MROD_EP0_RXRESET => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_RXRESET; -- EP0 Receiver Reset channel 23-0 end if; when REG_MROD_EP0_TXRESET => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP0_TXRESET; -- EP0 Transmitter Reset channel 23-0 end if; when REG_MROD_EP1_CSMENABLE => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_CSMENABLE; -- EP1 CSM Data Enable channel 23-0 end if; when REG_MROD_EP1_EMPTYSUPPR => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_EMPTYSUPPR; -- EP1 Set Empty Suppression channel 23-0 end if; when REG_MROD_EP1_HPTDCMODE => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_HPTDCMODE; -- EP1 Set HPTDC Mode channel 23-0 end if; when REG_MROD_EP1_CLRFIFOS => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_CLRFIFOS; -- EP1 Clear FIFOs channel 23-0 end if; when REG_MROD_EP1_EMULOADENA => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_EMULOADENA; -- EP1 Emulator Load Enable channel 23-0 end if; when REG_MROD_EP1_TRXLOOPBACK => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_TRXLOOPBACK; -- EP1 Transceiver Loopback Enable channel 23-0 end if; when REG_MROD_EP1_TXCVRRESET => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_TXCVRRESET; -- EP1 Transceiver Reset all channel 23-0 end if; when REG_MROD_EP1_RXRESET => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_RXRESET; -- EP1 Receiver Reset channel 23-0 end if; when REG_MROD_EP1_TXRESET => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_control_s.MROD_EP1_TXRESET; -- EP1 Transmitter Reset channel 23-0 end if; @@ -18797,35 +18793,35 @@ end process; -- MRODmonitors when REG_MROD_EP0_CSMH_EMPTY => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_CSMH_EMPTY; -- CSM Handler FIFO Empty 23-0 end if; when REG_MROD_EP0_CSMH_FULL => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_CSMH_FULL; -- CSM Handler FIFO Full 23-0 end if; when REG_MROD_EP0_RXLOCKED => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_RXLOCKED; -- EP0 Receiver Locked monitor 23-0 end if; when REG_MROD_EP0_TXLOCKED => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP0_TXLOCKED; -- EP0 Transmitter Locked monitor 23-0 end if; when REG_MROD_EP1_CSMH_EMPTY => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_CSMH_EMPTY; -- CSM Handler FIFO Empty 23-0 end if; when REG_MROD_EP1_CSMH_FULL => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_CSMH_FULL; -- CSM Handler FIFO Full 23-0 end if; when REG_MROD_EP1_RXLOCKED => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_RXLOCKED; -- EP1 Receiver Locked monitor 23-0 end if; when REG_MROD_EP1_TXLOCKED => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_read_data_25_s(23 downto 0) <= register_map_monitor_s.regmap_mrod_monitor.MROD_EP1_TXLOCKED; -- EP1 Transmitter Locked monitor 23-0 end if; ----------------------------------- @@ -25412,7 +25408,7 @@ end process; when REG_STRIPS_L1_TRIGGER => register_map_control_s.STRIPS_L1_TRIGGER <= "1"; -- (for tests only) simulate L1 trigger (issues 4-5 sequential triggers) when REG_STRIPS_R3L1_TRIGGER => register_map_control_s.STRIPS_R3L1_TRIGGER <= "1"; -- (for tests only) simulate simultaneous R3 and L1 trigger (issues 4-5 sequential triggers) when REG_MROD_CTRL => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_CTRL.OPTIONS <= register_write_data_25_v(15 downto 4); -- Extra options for MROD register_map_control_s.MROD_CTRL.GOLTESTMODE <= register_write_data_25_v(3 downto 0); -- GOL Test Mode (emulate CSM): -- 0: Run Data Emulator when 1; 0: stop, load emulator fifo @@ -25422,75 +25418,75 @@ end process; end if; when REG_MROD_EP0_CSMENABLE => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_CSMENABLE <= register_write_data_25_v(23 downto 0); -- EP0 CSM Data Enable channel 23-0 end if; when REG_MROD_EP0_EMPTYSUPPR => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_EMPTYSUPPR <= register_write_data_25_v(23 downto 0); -- EP0 Set Empty Suppression channel 23-0 end if; when REG_MROD_EP0_HPTDCMODE => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_HPTDCMODE <= register_write_data_25_v(23 downto 0); -- EP0 Set HPTDC Mode channel 23-0 end if; when REG_MROD_EP0_CLRFIFOS => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_CLRFIFOS <= register_write_data_25_v(23 downto 0); -- EP0 Clear FIFOs channel 23-0 end if; when REG_MROD_EP0_EMULOADENA => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_EMULOADENA <= register_write_data_25_v(23 downto 0); -- EP0 Emulator Load Enable channel 23-0 end if; when REG_MROD_EP0_TRXLOOPBACK => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_TRXLOOPBACK <= register_write_data_25_v(23 downto 0); -- EP0 Transceiver Loopback Enable channel 23-0 end if; when REG_MROD_EP0_TXCVRRESET => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_TXCVRRESET <= register_write_data_25_v(23 downto 0); -- EP0 Transceiver Reset all channel 23-0 end if; when REG_MROD_EP0_RXRESET => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_RXRESET <= register_write_data_25_v(23 downto 0); -- EP0 Receiver Reset channel 23-0 end if; when REG_MROD_EP0_TXRESET => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP0_TXRESET <= register_write_data_25_v(23 downto 0); -- EP0 Transmitter Reset channel 23-0 end if; when REG_MROD_EP1_CSMENABLE => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_CSMENABLE <= register_write_data_25_v(23 downto 0); -- EP1 CSM Data Enable channel 23-0 end if; when REG_MROD_EP1_EMPTYSUPPR => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_EMPTYSUPPR <= register_write_data_25_v(23 downto 0); -- EP1 Set Empty Suppression channel 23-0 end if; when REG_MROD_EP1_HPTDCMODE => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_HPTDCMODE <= register_write_data_25_v(23 downto 0); -- EP1 Set HPTDC Mode channel 23-0 end if; when REG_MROD_EP1_CLRFIFOS => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_CLRFIFOS <= register_write_data_25_v(23 downto 0); -- EP1 Clear FIFOs channel 23-0 end if; when REG_MROD_EP1_EMULOADENA => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_EMULOADENA <= register_write_data_25_v(23 downto 0); -- EP1 Emulator Load Enable channel 23-0 end if; when REG_MROD_EP1_TRXLOOPBACK => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_TRXLOOPBACK <= register_write_data_25_v(23 downto 0); -- EP1 Transceiver Loopback Enable channel 23-0 end if; when REG_MROD_EP1_TXCVRRESET => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_TXCVRRESET <= register_write_data_25_v(23 downto 0); -- EP1 Transceiver Reset all channel 23-0 end if; when REG_MROD_EP1_RXRESET => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_RXRESET <= register_write_data_25_v(23 downto 0); -- EP1 Receiver Reset channel 23-0 end if; when REG_MROD_EP1_TXRESET => - if MROD_GENERATE_REGS = true then + if MROD_GENERATE_REGS then register_map_control_s.MROD_EP1_TXRESET <= register_write_data_25_v(23 downto 0); -- EP1 Transmitter Reset channel 23-0 end if; ----------------------------------- diff --git a/sources/templates/dma_control.vhd.template b/sources/templates/dma_control.vhd.template index 7345c8e11364b7e9f8c19a2006a1e3d589458867..768a4f8d20516399b1d18bdc7b544c743899f2d3 100644 --- a/sources/templates/dma_control.vhd.template +++ b/sources/templates/dma_control.vhd.template @@ -61,7 +61,6 @@ entity dma_control is generic( NUMBER_OF_DESCRIPTORS : integer := 8; NUMBER_OF_INTERRUPTS : integer := 16; - SVN_VERSION : integer := 0; CARD_TYPE : integer := 710; BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE"; GIT_HASH : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000"; @@ -93,7 +92,6 @@ entity dma_control is reset_global_soft : out std_logic; s_axis_cq : in axis_type; s_axis_r_cq : out axis_r_type; - fifo_full : in std_logic; fifo_empty : in std_logic_vector(NUMBER_OF_DESCRIPTORS-2 downto 0); dma_interrupt_call : out std_logic_vector(3 downto 0); fromhost_pfull_threshold_assert: out std_logic_vector(8 downto 0); @@ -110,7 +108,7 @@ architecture rtl of dma_control is type completer_state_type is(IDLE, READ_REGISTER, WRITE_REGISTER_READ, WRITE_REGISTER_MODIFYWRITE, WAIT_RW_DONE, SEND_UNKNOWN_REQUEST); signal completer_state: completer_state_type := IDLE; - signal completer_state_slv: std_logic_vector(2 downto 0); + signal completer_state_slv: std_logic_vector(2 downto 0); --@suppress attribute dont_touch : string; attribute dont_touch of completer_state_slv : signal is "true"; @@ -484,7 +482,7 @@ begin else completer_state <= IDLE; end if; - when others => + when others => -- @suppress "Case statement contains all choices explicitly. You can safely remove the redundant 'others'" completer_state <= IDLE; completer_state_slv <= IDLE_SLV; end case; @@ -522,8 +520,6 @@ begin variable register_write_enable_v : std_logic; variable register_write_data_v : std_logic_vector(63 downto 0); variable bar_id_v : std_logic_vector(2 downto 0); - variable bar1_v : std_logic_vector(31 downto 0); - variable bar2_v : std_logic_vector(31 downto 0); variable dma_descriptors_v : dma_descriptors_type(0 to 7); variable dma_status_v : dma_statuses_type(0 to 7); variable int_vector_v : interrupt_vectors_type(0 to NUMBER_OF_INTERRUPTS-1); diff --git a/sources/templates/dma_control.vhd.template.orig b/sources/templates/dma_control.vhd.template.orig index 2d6692d71471781b7fdbcf9088a85cf483dcc5d4..9cadd1691bd8b86db9f8668423599113d3d25e63 100644 --- a/sources/templates/dma_control.vhd.template.orig +++ b/sources/templates/dma_control.vhd.template.orig @@ -54,7 +54,7 @@ library ieee, UNISIM; use work.pcie_package.all; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; -- @suppress "Deprecated package" +use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity dma_control is diff --git a/sources/templates/pcie_package.vhd b/sources/templates/pcie_package.vhd index b5895e2ecbbb89c796e4ced33372b1acb05ac33e..22acf26ae2d52f72ef39a1828cdf181f5e0842b5 100644 --- a/sources/templates/pcie_package.vhd +++ b/sources/templates/pcie_package.vhd @@ -73,10 +73,9 @@ library ieee; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all; +--use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; -library work; use work.centralRouter_package.all; use work.data_width_package.all; @@ -87,7 +86,7 @@ package pcie_package is -- -- PCIe DMA core: AXI-4 Stream interface type axis_type is record - tdata : std_logic_vector(pcie_data_width-1 downto 0); + tdata : std_logic_vector(PCIE_DATA_WIDTH-1 downto 0); tkeep : std_logic_vector(15 downto 0); tuser : std_logic_vector(182 downto 0); tlast : std_logic; @@ -132,7 +131,7 @@ package pcie_package is type interrupt_vectors_type is array (natural range <>) of interrupt_vector_type; - type slv_array is array (natural range <>) of std_logic_vector(pcie_data_width-1 downto 0); + type slv_array is array (natural range <>) of std_logic_vector(PCIE_DATA_WIDTH-1 downto 0); type slv12_array is array (natural range <>) of std_logic_vector(11 downto 0); --! Address Offset assignment diff --git a/sources/templates/pcie_package.vhd.template b/sources/templates/pcie_package.vhd.template index 01450df1ae70e5ad07dea24a034c274ffcc8d345..ea09c52f6b3b7eecaf37f2b38d46335c5adaa177 100644 --- a/sources/templates/pcie_package.vhd.template +++ b/sources/templates/pcie_package.vhd.template @@ -52,10 +52,9 @@ library ieee; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all; +--use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; -library work; use work.centralRouter_package.all; use work.data_width_package.all; @@ -66,7 +65,7 @@ package pcie_package is -- -- PCIe DMA core: AXI-4 Stream interface type axis_type is record - tdata : std_logic_vector(pcie_data_width-1 downto 0); + tdata : std_logic_vector(PCIE_DATA_WIDTH-1 downto 0); tkeep : std_logic_vector(15 downto 0); tuser : std_logic_vector(182 downto 0); tlast : std_logic; @@ -111,7 +110,7 @@ package pcie_package is type interrupt_vectors_type is array (natural range <>) of interrupt_vector_type; - type slv_array is array (natural range <>) of std_logic_vector(pcie_data_width-1 downto 0); + type slv_array is array (natural range <>) of std_logic_vector(PCIE_DATA_WIDTH-1 downto 0); type slv12_array is array (natural range <>) of std_logic_vector(11 downto 0); --! Address Offset assignment diff --git a/sources/templates/register_map_sync.vhd b/sources/templates/register_map_sync.vhd index 9a3649aa81a9be06a708ed06d08ee5b0b49fd34b..2b0b67579a86f5f5869880798a87c9b771d542dc 100644 --- a/sources/templates/register_map_sync.vhd +++ b/sources/templates/register_map_sync.vhd @@ -2,10 +2,10 @@ -library ieee, UNISIM, work; +library ieee, UNISIM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +--use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; use work.pcie_package.all; diff --git a/sources/templates/register_map_sync.vhd.template b/sources/templates/register_map_sync.vhd.template index 1979a0113aab6a6f311b4b8defa58eedbe4dd516..08049bc7ded13b46a7fbefe68d69a00514894647 100644 --- a/sources/templates/register_map_sync.vhd.template +++ b/sources/templates/register_map_sync.vhd.template @@ -2,10 +2,10 @@ -library ieee, UNISIM, work; +library ieee, UNISIM; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +--use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; use work.pcie_package.all; diff --git a/sources/templates/registers-5.0.yaml b/sources/templates/registers-5.0.yaml index b877d0c571a039dcad743327ca669ed4e81f1dfc..5dcae205c7c31428f034e765333910a3c34c6cc7 100644 --- a/sources/templates/registers-5.0.yaml +++ b/sources/templates/registers-5.0.yaml @@ -2985,7 +2985,7 @@ MRODregisters: group: MROD desc: Specific registers for MROD endpoints: 0 - generate: MROD_GENERATE_REGS = true + generate: MROD_GENERATE_REGS entries: - name: MROD_CTRL type: W @@ -3116,7 +3116,7 @@ MRODmonitors: group: MROD desc: Specific registers for MROD endpoints: 0 - generate: MROD_GENERATE_REGS = true + generate: MROD_GENERATE_REGS entries: - name: MROD_EP0_CSMH_EMPTY type: R diff --git a/sources/templates/strips_config_package.vhd.template b/sources/templates/strips_config_package.vhd.template old mode 100755 new mode 100644 diff --git a/sources/templates/strips_phase1_long_stave_mapping.vhd.template b/sources/templates/strips_phase1_long_stave_mapping.vhd.template old mode 100755 new mode 100644 diff --git a/sources/templates/strips_phase1_unknown_mapping.vhd.template b/sources/templates/strips_phase1_unknown_mapping.vhd.template old mode 100755 new mode 100644 diff --git a/sources/templates/strips_register_map.py.template b/sources/templates/strips_register_map.py.template old mode 100755 new mode 100644 diff --git a/sources/templates/wupper.vhd b/sources/templates/wupper.vhd index 35944cf3f14fa46f0a1eea60e233f485d4e31c11..40e8608491068e1c13380ebf70e48fecb7e657f2 100644 --- a/sources/templates/wupper.vhd +++ b/sources/templates/wupper.vhd @@ -60,7 +60,6 @@ entity wupper is NUMBER_OF_INTERRUPTS : integer := 8; NUMBER_OF_DESCRIPTORS : integer := 8; BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE"; - SVN_VERSION : integer := 0; CARD_TYPE : integer := 710; GIT_HASH : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000"; COMMIT_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE"; @@ -133,8 +132,8 @@ architecture structure of wupper is signal s_axis_r_S2MM : axis_r_type; signal m_axis_r_CNTRL : axis_r_type; signal s_axis_r_STS : axis_r_type; - signal cfg_interrupt_msix_sent : std_logic; - signal cfg_interrupt_msix_fail : std_logic; + --signal cfg_interrupt_msix_sent : std_logic; + --signal cfg_interrupt_msix_fail : std_logic; signal cfg_interrupt_msix_int : std_logic; signal cfg_interrupt_msix_address : std_logic_vector(63 downto 0); signal cfg_interrupt_msix_data : std_logic_vector(31 downto 0); @@ -156,12 +155,12 @@ architecture structure of wupper is signal m_axis_cc : axis_type; signal m_axis_rc : axis_type; signal m_axis_rq : axis_type; - signal cfg_fc_ph : std_logic_vector(7 downto 0); - signal cfg_fc_pd : std_logic_vector(11 downto 0); - signal cfg_fc_nph : std_logic_vector(7 downto 0); - signal cfg_fc_npd : std_logic_vector(11 downto 0); - signal cfg_fc_cplh : std_logic_vector(7 downto 0); - signal cfg_fc_cpld : std_logic_vector(11 downto 0); + --signal cfg_fc_ph : std_logic_vector(7 downto 0); + --signal cfg_fc_pd : std_logic_vector(11 downto 0); + --signal cfg_fc_nph : std_logic_vector(7 downto 0); + --signal cfg_fc_npd : std_logic_vector(11 downto 0); + --signal cfg_fc_cplh : std_logic_vector(7 downto 0); + --signal cfg_fc_cpld : std_logic_vector(11 downto 0); signal cfg_fc_sel : std_logic_vector(2 downto 0); signal sys_rst_n : std_logic; signal lnk_up_net : std_logic; @@ -169,7 +168,6 @@ architecture structure of wupper is signal fromHostFifo_din : std_logic_vector(DATA_WIDTH-1 downto 0); - signal fromHostFifoIndex : integer range 0 to 0; signal fromHostFifo_pfull_threshold_assert : std_logic_vector(8 downto 0); signal fromHostFifo_pfull_threshold_negate : std_logic_vector(8 downto 0); signal fromHostFifo_prog_full : std_logic; @@ -211,19 +209,19 @@ begin DATA_WIDTH => DATA_WIDTH, SIMULATION => SIMULATION) port map( - cfg_fc_cpld => cfg_fc_cpld, - cfg_fc_cplh => cfg_fc_cplh, - cfg_fc_npd => cfg_fc_npd, - cfg_fc_nph => cfg_fc_nph, - cfg_fc_pd => cfg_fc_pd, - cfg_fc_ph => cfg_fc_ph, + cfg_fc_cpld => open, --cfg_fc_cpld, + cfg_fc_cplh => open, --cfg_fc_cplh, + cfg_fc_npd => open, --cfg_fc_npd, + cfg_fc_nph => open, --cfg_fc_nph, + cfg_fc_pd => open, --cfg_fc_pd, + cfg_fc_ph => open, --cfg_fc_ph, cfg_fc_sel => cfg_fc_sel, cfg_interrupt_msix_address => cfg_interrupt_msix_address, cfg_interrupt_msix_data => cfg_interrupt_msix_data, cfg_interrupt_msix_enable => cfg_interrupt_msix_enable, - cfg_interrupt_msix_fail => cfg_interrupt_msix_fail, + cfg_interrupt_msix_fail => open, cfg_interrupt_msix_int => cfg_interrupt_msix_int, - cfg_interrupt_msix_sent => cfg_interrupt_msix_sent, + cfg_interrupt_msix_sent => open, cfg_mgmt_addr => cfg_mgmt_addr, cfg_mgmt_byte_enable => cfg_mgmt_byte_enable, cfg_mgmt_read => cfg_mgmt_read, @@ -254,7 +252,6 @@ begin generic map( NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS, NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS, - SVN_VERSION => SVN_VERSION, BUILD_DATETIME => BUILD_DATETIME, CARD_TYPE => CARD_TYPE, GIT_HASH => GIT_HASH, @@ -264,8 +261,8 @@ begin GBT_GENERATE_ALL_REGS => GBT_GENERATE_ALL_REGS, EMU_GENERATE_REGS => EMU_GENERATE_REGS, MROD_GENERATE_REGS => MROD_GENERATE_REGS, - FIRMWARE_MODE => FIRMWARE_MODE, GBT_NUM => GBT_NUM, + FIRMWARE_MODE => FIRMWARE_MODE, PCIE_ENDPOINT => PCIE_ENDPOINT, DATA_WIDTH => DATA_WIDTH, BLOCKSIZE => BLOCKSIZE) @@ -275,7 +272,7 @@ begin dma_interrupt_call => dma_interrupt_call, flush_fifo => flush_fifo, fromHostFifo_din => fromHostFifo_din, - fromHostFifoIndex => fromHostFifoIndex, + fromHostFifoIndex => open, fromHostFifo_prog_full => fromHostFifo_prog_full, fromHostFifo_we => fromHostFifo_we, fromhost_busy_out => fromhost_busy_out, @@ -302,8 +299,7 @@ begin toHostFifo_re => toHostFifo_re, tohost_busy_out => tohost_busy_out, tohost_pfull_threshold_assert => toHostFifo_pfull_threshold_assert, - tohost_pfull_threshold_negate => toHostFifo_pfull_threshold_negate, - user_lnk_up => lnk_up_net); + tohost_pfull_threshold_negate => toHostFifo_pfull_threshold_negate); irq0: entity work.intr_ctrl generic map( @@ -312,9 +308,7 @@ begin cfg_interrupt_msix_address => cfg_interrupt_msix_address, cfg_interrupt_msix_data => cfg_interrupt_msix_data, cfg_interrupt_msix_enable => cfg_interrupt_msix_enable, - cfg_interrupt_msix_fail => cfg_interrupt_msix_fail, cfg_interrupt_msix_int => cfg_interrupt_msix_int, - cfg_interrupt_msix_sent => cfg_interrupt_msix_sent, clk => clk, regmap_clk => regmap_clk, dma_interrupt_call => dma_interrupt_call, @@ -330,12 +324,6 @@ begin init0: entity work.pcie_init port map( - cfg_fc_cpld => cfg_fc_cpld, - cfg_fc_cplh => cfg_fc_cplh, - cfg_fc_npd => cfg_fc_npd, - cfg_fc_nph => cfg_fc_nph, - cfg_fc_pd => cfg_fc_pd, - cfg_fc_ph => cfg_fc_ph, cfg_fc_sel => cfg_fc_sel, cfg_mgmt_addr => cfg_mgmt_addr, cfg_mgmt_byte_enable => cfg_mgmt_byte_enable, @@ -365,7 +353,6 @@ begin DATA_WIDTH => DATA_WIDTH ) port map( - fromHostFifoIndex => fromHostFifoIndex, fromHostFifo_din => fromHostFifo_din, fromHostFifo_dout => fromHostFifo_dout, fromHostFifo_empty => fromHostFifo_empty, @@ -403,7 +390,6 @@ begin interrupt_call_cr => interrupt_call, register_map_40_control => register_map_control_sync, register_map_control => register_map_control_appreg_clk_s, - register_map_monitor => register_map_monitor, register_map_gen_board_info => register_map_gen_board_info, register_map_crtohost_monitor => register_map_crtohost_monitor, register_map_crfromhost_monitor => register_map_crfromhost_monitor, @@ -417,6 +403,7 @@ begin register_map_generators => register_map_generators, wishbone_monitor => wishbone_monitor, regmap_mrod_monitor => regmap_mrod_monitor, + register_map_monitor => register_map_monitor, rst_hw => reset_hw_in, rst_soft_40 => reset_soft, rst_soft_appregclk => reset_soft_appreg_clk_s, diff --git a/sources/templates/wupper.vhd.template b/sources/templates/wupper.vhd.template index 640650f148f96ef0820072b0f0776171656b1163..32fb6d60399f3c86b3fa0260f38e9498bb8505b2 100644 --- a/sources/templates/wupper.vhd.template +++ b/sources/templates/wupper.vhd.template @@ -60,7 +60,6 @@ entity wupper is NUMBER_OF_INTERRUPTS : integer := 8; NUMBER_OF_DESCRIPTORS : integer := 8; BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE"; - SVN_VERSION : integer := 0; CARD_TYPE : integer := 710; GIT_HASH : std_logic_vector(159 downto 0) := x"0000000000000000000000000000000000000000"; COMMIT_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE"; @@ -123,8 +122,8 @@ architecture structure of wupper is signal s_axis_r_S2MM : axis_r_type; signal m_axis_r_CNTRL : axis_r_type; signal s_axis_r_STS : axis_r_type; - signal cfg_interrupt_msix_sent : std_logic; - signal cfg_interrupt_msix_fail : std_logic; + --signal cfg_interrupt_msix_sent : std_logic; + --signal cfg_interrupt_msix_fail : std_logic; signal cfg_interrupt_msix_int : std_logic; signal cfg_interrupt_msix_address : std_logic_vector(63 downto 0); signal cfg_interrupt_msix_data : std_logic_vector(31 downto 0); @@ -146,12 +145,12 @@ architecture structure of wupper is signal m_axis_cc : axis_type; signal m_axis_rc : axis_type; signal m_axis_rq : axis_type; - signal cfg_fc_ph : std_logic_vector(7 downto 0); - signal cfg_fc_pd : std_logic_vector(11 downto 0); - signal cfg_fc_nph : std_logic_vector(7 downto 0); - signal cfg_fc_npd : std_logic_vector(11 downto 0); - signal cfg_fc_cplh : std_logic_vector(7 downto 0); - signal cfg_fc_cpld : std_logic_vector(11 downto 0); + --signal cfg_fc_ph : std_logic_vector(7 downto 0); + --signal cfg_fc_pd : std_logic_vector(11 downto 0); + --signal cfg_fc_nph : std_logic_vector(7 downto 0); + --signal cfg_fc_npd : std_logic_vector(11 downto 0); + --signal cfg_fc_cplh : std_logic_vector(7 downto 0); + --signal cfg_fc_cpld : std_logic_vector(11 downto 0); signal cfg_fc_sel : std_logic_vector(2 downto 0); signal sys_rst_n : std_logic; signal lnk_up_net : std_logic; @@ -159,7 +158,6 @@ architecture structure of wupper is signal fromHostFifo_din : std_logic_vector(DATA_WIDTH-1 downto 0); - signal fromHostFifoIndex : integer range 0 to 0; signal fromHostFifo_pfull_threshold_assert : std_logic_vector(8 downto 0); signal fromHostFifo_pfull_threshold_negate : std_logic_vector(8 downto 0); signal fromHostFifo_prog_full : std_logic; @@ -201,19 +199,19 @@ begin DATA_WIDTH => DATA_WIDTH, SIMULATION => SIMULATION) port map( - cfg_fc_cpld => cfg_fc_cpld, - cfg_fc_cplh => cfg_fc_cplh, - cfg_fc_npd => cfg_fc_npd, - cfg_fc_nph => cfg_fc_nph, - cfg_fc_pd => cfg_fc_pd, - cfg_fc_ph => cfg_fc_ph, + cfg_fc_cpld => open, --cfg_fc_cpld, + cfg_fc_cplh => open, --cfg_fc_cplh, + cfg_fc_npd => open, --cfg_fc_npd, + cfg_fc_nph => open, --cfg_fc_nph, + cfg_fc_pd => open, --cfg_fc_pd, + cfg_fc_ph => open, --cfg_fc_ph, cfg_fc_sel => cfg_fc_sel, cfg_interrupt_msix_address => cfg_interrupt_msix_address, cfg_interrupt_msix_data => cfg_interrupt_msix_data, cfg_interrupt_msix_enable => cfg_interrupt_msix_enable, - cfg_interrupt_msix_fail => cfg_interrupt_msix_fail, + cfg_interrupt_msix_fail => open, cfg_interrupt_msix_int => cfg_interrupt_msix_int, - cfg_interrupt_msix_sent => cfg_interrupt_msix_sent, + cfg_interrupt_msix_sent => open, cfg_mgmt_addr => cfg_mgmt_addr, cfg_mgmt_byte_enable => cfg_mgmt_byte_enable, cfg_mgmt_read => cfg_mgmt_read, @@ -244,7 +242,6 @@ begin generic map( NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS, NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS, - SVN_VERSION => SVN_VERSION, BUILD_DATETIME => BUILD_DATETIME, CARD_TYPE => CARD_TYPE, GIT_HASH => GIT_HASH, @@ -254,8 +251,8 @@ begin GBT_GENERATE_ALL_REGS => GBT_GENERATE_ALL_REGS, EMU_GENERATE_REGS => EMU_GENERATE_REGS, MROD_GENERATE_REGS => MROD_GENERATE_REGS, - FIRMWARE_MODE => FIRMWARE_MODE, GBT_NUM => GBT_NUM, + FIRMWARE_MODE => FIRMWARE_MODE, PCIE_ENDPOINT => PCIE_ENDPOINT, DATA_WIDTH => DATA_WIDTH, BLOCKSIZE => BLOCKSIZE) @@ -265,7 +262,7 @@ begin dma_interrupt_call => dma_interrupt_call, flush_fifo => flush_fifo, fromHostFifo_din => fromHostFifo_din, - fromHostFifoIndex => fromHostFifoIndex, + fromHostFifoIndex => open, fromHostFifo_prog_full => fromHostFifo_prog_full, fromHostFifo_we => fromHostFifo_we, fromhost_busy_out => fromhost_busy_out, @@ -292,8 +289,7 @@ begin toHostFifo_re => toHostFifo_re, tohost_busy_out => tohost_busy_out, tohost_pfull_threshold_assert => toHostFifo_pfull_threshold_assert, - tohost_pfull_threshold_negate => toHostFifo_pfull_threshold_negate, - user_lnk_up => lnk_up_net); + tohost_pfull_threshold_negate => toHostFifo_pfull_threshold_negate); irq0: entity work.intr_ctrl generic map( @@ -302,9 +298,7 @@ begin cfg_interrupt_msix_address => cfg_interrupt_msix_address, cfg_interrupt_msix_data => cfg_interrupt_msix_data, cfg_interrupt_msix_enable => cfg_interrupt_msix_enable, - cfg_interrupt_msix_fail => cfg_interrupt_msix_fail, cfg_interrupt_msix_int => cfg_interrupt_msix_int, - cfg_interrupt_msix_sent => cfg_interrupt_msix_sent, clk => clk, regmap_clk => regmap_clk, dma_interrupt_call => dma_interrupt_call, @@ -320,12 +314,6 @@ begin init0: entity work.pcie_init port map( - cfg_fc_cpld => cfg_fc_cpld, - cfg_fc_cplh => cfg_fc_cplh, - cfg_fc_npd => cfg_fc_npd, - cfg_fc_nph => cfg_fc_nph, - cfg_fc_pd => cfg_fc_pd, - cfg_fc_ph => cfg_fc_ph, cfg_fc_sel => cfg_fc_sel, cfg_mgmt_addr => cfg_mgmt_addr, cfg_mgmt_byte_enable => cfg_mgmt_byte_enable, @@ -355,7 +343,6 @@ begin DATA_WIDTH => DATA_WIDTH ) port map( - fromHostFifoIndex => fromHostFifoIndex, fromHostFifo_din => fromHostFifo_din, fromHostFifo_dout => fromHostFifo_dout, fromHostFifo_empty => fromHostFifo_empty, @@ -393,10 +380,10 @@ begin interrupt_call_cr => interrupt_call, register_map_40_control => register_map_control_sync, register_map_control => register_map_control_appreg_clk_s, - register_map_monitor => register_map_monitor, {% for monitorsection in registers if monitorsection is in_group('Monitorsections') %} {{monitorsection.record_name}} => {{monitorsection.record_name}}, {% endfor %} + register_map_monitor => register_map_monitor, rst_hw => reset_hw_in, rst_soft_40 => reset_soft, rst_soft_appregclk => reset_soft_appreg_clk_s, diff --git a/sources/ttc/ttc_busy/ttc_busy_limiter.vhd b/sources/ttc/ttc_busy/ttc_busy_limiter.vhd index f7439ecb5c5ff71b44b37f93162129801345152c..1dba06a351269d0de98abac5299ce08fd24123cf 100644 --- a/sources/ttc/ttc_busy/ttc_busy_limiter.vhd +++ b/sources/ttc/ttc_busy/ttc_busy_limiter.vhd @@ -26,8 +26,8 @@ library IEEE; use IEEE.std_logic_1164.all; -- needed for logical operations -use IEEE.std_logic_arith.all; -- needed for +/- operations -use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; -- @suppress "Deprecated package" -- needed for +/- operations +use IEEE.std_logic_unsigned.all;-- @suppress "Deprecated package" -- pragma translate_off library UNISIM; diff --git a/sources/ttc/ttc_busy/ttc_busy_or.vhd b/sources/ttc/ttc_busy/ttc_busy_or.vhd index 0bb8d638a4f24dd202a893118faeb6657fdf35e4..5d0ecce3e85607ca442aa67fefe77b59f4cf4e05 100644 --- a/sources/ttc/ttc_busy/ttc_busy_or.vhd +++ b/sources/ttc/ttc_busy/ttc_busy_or.vhd @@ -38,11 +38,11 @@ -- Library Declaration ------------------------------------------------------------------------------- -library work, ieee, UNISIM; +library ieee, UNISIM; use work.lpgbtfpga_package.all; use ieee.numeric_std.all; use UNISIM.VCOMPONENTS.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use ieee.std_logic_1164.all; use work.pcie_package.all; use work.centralRouter_package.all; @@ -78,7 +78,7 @@ end ttc_busy; architecture rtl of ttc_busy is -- controls for clock prescaling logic -signal PRESCALE_VALUE : std_logic_vector(19 downto 0); +--signal PRESCALE_VALUE : std_logic_vector(19 downto 0); -- controls for limiter logic signal TEST_MODEs : std_logic_vector(GBT_NUM downto 1); --if set, can manually drive busy low or high for testing signal TEST_VALUEs : std_logic_vector(GBT_NUM downto 1); --the value BUSY should have in test mode @@ -87,13 +87,13 @@ signal BUSY_LIMIT_TIME : std_logic_vector(15 downto 0); --sets time that signal ANY_BUSY_WIDTH_REG : std_logic_vector(15 downto 0); --how wide to make the final output pulse (minimum) -signal PRESCALED_CLOCK_ENABLE : std_logic; --connects output of limit timer to all limiter machines +--signal PRESCALED_CLOCK_ENABLE : std_logic; --connects output of limit timer to all limiter machines signal ACCEPTED_BUSY_OUTs : busyOut_array_type (0 to (GBT_NUM-1)); --BUSYs from each limited if passed by limit logic --signal LIMITER_STATE_MON_ARR : busyOut_SM_array_type (0 to (GBT_NUM-1)); signal ANY_BUSY_COUNT : std_logic_vector(15 downto 0); -- counter for ANY BUSY output -signal ANY_BUSY_REQUEST : std_logic; +--signal ANY_BUSY_REQUEST : std_logic; signal GBT_Busy : std_logic_vector((GBT_NUM-1) downto 0); --first rank OR, per GBT signal ANY_GBT_BUSY : std_logic; @@ -166,7 +166,7 @@ end generate; dma_busy_enable <= to_sl(register_map_control.DMA_BUSY_STATUS.ENABLE); -- controls for clock prescaling logic -PRESCALE_VALUE <= register_map_control.TTC_BUSY_TIMING_CTRL.PRESCALE; --controls for limiter logic +--PRESCALE_VALUE <= register_map_control.TTC_BUSY_TIMING_CTRL.PRESCALE; --controls for limiter logic TEST_MODEs <= (others => '0'); --if set, can manually drive busy low or high for testing TEST_VALUEs <= (others => '0'); --the value BUSY should have in test mode @@ -272,12 +272,12 @@ FILTER_OUTER_LOOP : for GBTnum in 0 to (GBT_NUM-1) generate begin if (mclk'event AND (mclk = '1')) then if (mrst = '1') then --synchronous reset - GBT_BUSY(GBTnum) <= '0'; + GBT_Busy(GBTnum) <= '0'; else - GBT_BUSY(GBTnum) <= '0'; + GBT_Busy(GBTnum) <= '0'; for i in 0 to 56 loop if ACCEPTED_BUSY_OUTs(GBTnum)(i) = '1' and elink_busy_enable(GBTnum)(i) = '1' then - GBT_BUSY(GBTnum) <= '1'; + GBT_Busy(GBTnum) <= '1'; end if; end loop; end if; @@ -289,10 +289,10 @@ end generate FILTER_OUTER_LOOP; --closes outer loop TTC_BUSY_mon_array <= internal_BUSY_mon_array; -SECOND_RANK_OR: process(mrst, mclk) +SECOND_RANK_OR: process(mclk) begin if (mclk'event AND (mclk = '1')) then - if (GBT_BUSY /= VAR_SIZE_ZERO or ((ACCEPTED_BUSY_OUTs_DMA = '1' and dma_busy_enable = '1') or ACCEPTED_BUSY_OUTs_FIFO = '1')) then + if (GBT_Busy /= VAR_SIZE_ZERO or ((ACCEPTED_BUSY_OUTs_DMA = '1' and dma_busy_enable = '1') or ACCEPTED_BUSY_OUTs_FIFO = '1')) then ANY_GBT_BUSY <= '1'; else ANY_GBT_BUSY <= '0'; diff --git a/sources/ttc/ttc_decoder/TTC_hamming_decoder_alme.vhd b/sources/ttc/ttc_decoder/TTC_hamming_decoder_alme.vhd index 6f449c3fe0dd5dc47c255ac2ac31c2299e40579c..a964746994ca3e58283560b03eefabfbb0e0b639 100644 --- a/sources/ttc/ttc_decoder/TTC_hamming_decoder_alme.vhd +++ b/sources/ttc/ttc_decoder/TTC_hamming_decoder_alme.vhd @@ -32,7 +32,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -USE ieee.std_logic_unsigned.ALL; +USE ieee.std_logic_unsigned.ALL;-- @suppress "Deprecated package" entity serialb_com is generic ( @@ -407,7 +407,7 @@ begin single_bit_error_i <= single_bit_error_i; double_bit_error_i <= double_bit_error_i; next_state <= s_idle; - when others => + when others => -- @suppress "Case statement contains all choices explicitly. You can safely remove the redundant 'others'" communication_error <= '0'; single_bit_error_i <= '0'; double_bit_error_i <= '0'; @@ -466,13 +466,13 @@ end generate hamming; ------------------------------------------------------------------------------------------------ Nothamming : if include_hamming = false generate signal d_adr : std_logic_vector(31 downto 0); - signal d_br : std_logic_vector(7 downto 0); + --signal d_br : std_logic_vector(7 downto 0); signal next_state : state; begin ------------------------------------------------------------------------------------ -d_br <= received_word(12 downto 5) when testmode <= '0' else (others => '0'); +--d_br <= received_word(12 downto 5) when testmode <= '0' else (others => '0'); d_adr <= received_word(38 downto 7) when testmode <= '0' else "00000000000000" & "11" & "0001" & "000" & '1' & "1010" & '1' & '0' & "11"; ------------------------------------------------------------------------------------ -- purpose: receiving serial B messages by shifting them into a shift register. @@ -550,7 +550,7 @@ begin when s_error => communication_error <= '1'; next_state <= s_idle; - when others => + when others => -- @suppress "Case statement contains all choices explicitly. You can safely remove the redundant 'others'" communication_error <= '0'; single_bit_error <= '0'; double_bit_error <= '0'; @@ -598,4 +598,4 @@ end generate Nothamming; ------------------------------------------------------------------------------------------------ -- NOT include hamming ------------------------------------------------------------------------------------------------ -end arc; \ No newline at end of file +end arc; diff --git a/sources/ttc/ttc_decoder/cdr2a_b_clk.vhd b/sources/ttc/ttc_decoder/cdr2a_b_clk.vhd index dfa882dd345ac325eb257ce13bbf8496b0d61004..92970787ad40124c1f3ade261a73fe5f3c781018 100644 --- a/sources/ttc/ttc_decoder/cdr2a_b_clk.vhd +++ b/sources/ttc/ttc_decoder/cdr2a_b_clk.vhd @@ -49,28 +49,23 @@ -- IEEE VHDL standard library: library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_misc.all; +use ieee.std_logic_arith.all;-- @suppress "Deprecated package" +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" +--use ieee.std_logic_misc.all; -- Xilinx devices library: library unisim; use unisim.vcomponents.all; --- Custom libraries and packages: -use work.all; - - --=================================================================================================-- --======================================= Module Body =============================================-- --=================================================================================================-- entity cdr2a_b_clk is -generic (pll_locked_delay: integer:= 100000); port ( - RESET_N : in std_logic; + --RESET_N : in std_logic; --=======================-- -- adn2814 cdr interface -- --=======================-- @@ -104,7 +99,7 @@ architecture behavioral of cdr2a_b_clk is -- Comment: The "keep" constant is used to avoid that ISE changes the name of -- the signals to be analysed with Chipscope. - attribute keep : string; + --attribute keep : string; --========================================================================-- @@ -128,51 +123,34 @@ architecture behavioral of cdr2a_b_clk is signal strng_length : std_logic_vector(3 downto 0) := (others =>'0'); signal div_rst_cnt : std_logic_vector(4 downto 0) := (others =>'0'); signal ttc_str, ttcclk : std_logic := '0'; - signal sr : std_logic_vector(12 downto 0) := (others => '0'); - signal rec_cntr : std_logic_vector(5 downto 0) := (others => '0'); - signal rec_frame : std_logic := '0'; - signal fmt : std_logic := '0'; + --signal sr : std_logic_vector(12 downto 0) := (others => '0'); + --signal rec_cntr : std_logic_vector(5 downto 0) := (others => '0'); + --signal rec_frame : std_logic := '0'; + --signal fmt : std_logic := '0'; --MMCM signals - signal locked, psen, psdone: std_logic; + --signal locked, psen, psdone: std_logic; --MMCM generated clock, phase locked to 40MHz logic generated clock - signal ttcclk_mmcm: std_logic; + --signal ttcclk_mmcm: std_logic; --Timeout counter, starts counting if phases don't match, only change phase when counter times out. - signal cnt: integer range 0 to 1023; + --signal cnt: integer range 0 to 1023; --If PLL runs at 1000MHz, we need 350 steps to change 90 degrees phase shift @40MHz - signal phaseinc: integer range 0 to 511; + --signal phaseinc: integer range 0 to 511; --Helper signal, tells process to wait for the psdone to come up. - signal waitforpsdone: std_logic; + --signal waitforpsdone: std_logic; --Shift register signals to sample both logic generated ttcclk and mmcm generated ttcclk_mmcm --at 160 MHz, this way a 90 degree phase shift can be detected and adjusted. --The MMCM always starts at 0 degree with respect to input clock - signal ttcclk_sample: std_logic_vector(3 downto 0); - signal mmcmclk_sample: std_logic_vector(3 downto 0); - - component ttc_phase_clock_wizard - port - (-- Clock in ports - clk_in1 : in std_logic; - -- Clock out ports - clk_out1 : out std_logic; - -- Dynamic phase shift ports - psclk : in std_logic; - psen : in std_logic; - psincdec : in std_logic; - psdone : out std_logic; - -- Status and control signals - reset : in std_logic; - locked : out std_logic - ); - end component; + --signal ttcclk_sample: std_logic_vector(3 downto 0); + --signal mmcmclk_sample: std_logic_vector(3 downto 0); - signal reset: std_logic; + --signal reset: std_logic; begin - reset <= not RESET_N; + --reset <= not RESET_N; Achannel <= l1a; @@ -205,7 +183,7 @@ begin --end process; ----===================================================-- - cdrlock_out <= cdr_lock and locked; + cdrlock_out <= cdr_lock; cdr_lock <= cdrlock_in; @@ -335,10 +313,10 @@ end process; ttc_strobe <=ttc_str; -- ttc_clock <= ttcclk_mmcm; -clock_iter : bufg +clock_iter : BUFG port map( - I => ttcclk , - O => ttc_clock); + O => ttc_clock, + I => ttcclk); -- ttc_clock <= ttcclk; diff --git a/sources/ttc/ttc_decoder/ttc_decoder_core.vhd b/sources/ttc/ttc_decoder/ttc_decoder_core.vhd index e94096f3a31fadb5c794629af32f5d14e4da5b03..53d7855e4fb3e4ff979c07e8487994faa3d93cc5 100644 --- a/sources/ttc/ttc_decoder/ttc_decoder_core.vhd +++ b/sources/ttc/ttc_decoder/ttc_decoder_core.vhd @@ -80,10 +80,10 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all;-- @suppress "Deprecated package" +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" -use work.all; +--use work.all; @@ -93,7 +93,7 @@ use work.all; entity ttc_decoder_core is port ( - RESET_N : in std_logic; + --RESET_N : in std_logic; --== cdr interface ==-- cdrclk_in_locked : in std_logic; --160 MHz clock cdrclk_in : in std_logic; @@ -162,17 +162,17 @@ begin --================== Architecture Body ==================-- --=====================================-- from_cdr_to_AandB: entity work.cdr2a_b_clk --=====================================-- -generic map (pll_locked_delay => 100000) +--generic map (pll_locked_delay => 100000) port map ( - RESET_N => RESET_N, + --RESET_N => RESET_N, --== cdr interface ==-- cdrclk_in => cdrclk_in, cdrdata_in => cdrdata_in, cdrlock_in => cdrclk_in_locked, cdrlock_out => ready, - div_nrst => div_nrst, + div_nrst => div_nrst, --== A/B channel decoding ==-- ttc_clock => ttc_clk_gated, Achannel => l1a_i, diff --git a/sources/ttc/ttc_decoder/ttc_fmc_wrapper_xilinx.vhd b/sources/ttc/ttc_decoder/ttc_fmc_wrapper_xilinx.vhd index b6488df9100d1c724e7b9cc5cb797f283c731067..380719f6b2d225c7797d488750bb43f510f7ca87 100644 --- a/sources/ttc/ttc_decoder/ttc_fmc_wrapper_xilinx.vhd +++ b/sources/ttc/ttc_decoder/ttc_fmc_wrapper_xilinx.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all;-- @suppress "Deprecated package" +use ieee.std_logic_unsigned.all;-- @suppress "Deprecated package" use IEEE.NUMERIC_STD.ALL; library UNISIM; @@ -24,7 +24,7 @@ port ( DATA_TTC_N : in std_logic; -- ADN2812 CDR Serial Data output LOL_ADN : in std_logic; -- ADN2812 CDR Loss of Lock output LOS_ADN : in std_logic; -- ADN2812 CDR Loss of Signal output - RESET_N : in std_logic; -- if low, stop PLL inside wrapper + --RESET_N : in std_logic; -- if low, stop PLL inside wrapper register_map_control : in register_map_control_type; register_map_ttc_monitor : out register_map_ttc_monitor_type; --== to Central Router ==--- @@ -77,10 +77,10 @@ signal TTCEmu_TTCout : std_logic_vector(9 downto 0); --====================-- -- ttc wrapper control --====================-- -signal RESET_N_s : std_logic; +--signal RESET_N_s : std_logic; signal rst_TTCtoHost : std_logic; signal rst_TTCtoHost_40 : std_logic; -- in the TTC clock domain (40 MHz) -signal MMCM_MAIN_LCLK_SEL : std_logic; +--signal MMCM_MAIN_LCLK_SEL : std_logic; --signal master_BUSY : std_logic; -- to throtlle the L1A --signal L1A_throttle : std_logic; signal TTC_BIT_ERR_REG : std_logic_vector(2 downto 0); @@ -218,19 +218,19 @@ signal BCR_MISMATCH_cntr_reset_0, BCR_MISMATCH_cntr_reset_1 : std_logic; signal BCR_period : std_logic_vector(11 downto 0):= x"000"; --FIFO for Trigger type synchronization -component TTCtoHostData_fwft is - PORT ( - clk : IN STD_LOGIC; - srst : IN STD_LOGIC; - din : IN STD_LOGIC_VECTOR(144 DOWNTO 0); - wr_en : IN STD_LOGIC; - rd_en : IN STD_LOGIC; - dout : OUT STD_LOGIC_VECTOR(144 DOWNTO 0); - full : OUT STD_LOGIC; - empty : OUT STD_LOGIC; - data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0) - ); -END component; +component TTCtoHostData_fwft + port( + clk : in STD_LOGIC; + srst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR(144 downto 0); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR(144 downto 0); + full : out STD_LOGIC; + empty : out STD_LOGIC; + data_count : out STD_LOGIC_VECTOR(10 downto 0) + ); + end component TTCtoHostData_fwft; --fifo for clock domain crossing component TTCtoHostData_reclock is @@ -273,8 +273,8 @@ begin --=====================-- - MMCM_MAIN_LCLK_SEL <= to_sl(register_map_control.MMCM_MAIN.LCLK_SEL); - RESET_N_s <= RESET_N and (not MMCM_MAIN_LCLK_SEL); + --MMCM_MAIN_LCLK_SEL <= to_sl(register_map_control.MMCM_MAIN.LCLK_SEL); + --RESET_N_s <= RESET_N and (not MMCM_MAIN_LCLK_SEL); rst_TTCtoHost <= to_sl(register_map_control.TTC_DEC_CTRL.TOHOST_RST) or (not div_nrst); BCID_reg <= register_map_control.TTC_DEC_CTRL.BCID_ONBCR; -- BCID is set to this when reset @@ -681,14 +681,14 @@ begin Fifo_ToHostData: TTCtoHostData_fwft port map ( - srst => rst_TTCtoHost_40, - clk => local_ttc_clk, --ttc_clk_gated, - din => ToHostData_in, - wr_en => wr_en_ToHostData, - rd_en => rd_en_ToHostData, - dout => ToHostData_out, - full => ToHostData_full, - empty => ToHostData_empty, + clk => local_ttc_clk, --ttc_clk_gated, + srst => rst_TTCtoHost_40, + din => ToHostData_in, + wr_en => wr_en_ToHostData, + rd_en => rd_en_ToHostData, + dout => ToHostData_out, + full => ToHostData_full, + empty => ToHostData_empty, data_count => ToHostData_count ); --ToHostData_count_o <= ToHostData_count; @@ -758,18 +758,16 @@ begin Fifo_ToHostData_reclock: TTCtoHostData_reclock port map ( - rst => rst_TTCtoHost, - -- + rst => rst_TTCtoHost, wr_clk => local_ttc_clk, --ttc_clk_gated, - din => ToHostData_tmp(159 downto 0), - wr_en => ToHostData_tmp(160), - -- rd_clk => clk40, - rd_en => '1', - dout => ToHostData_fifo(159 downto 0), - valid => ToHostData_fifo(160), - full => open, - empty => open + din => ToHostData_tmp(159 downto 0), + wr_en => ToHostData_tmp(160), + rd_en => '1', + dout => ToHostData_fifo(159 downto 0), + full => open, + empty => open, + valid => ToHostData_fifo(160) ); TTC_ToHost_Data_out.FMT <= ToHostData_fifo(7 downto 0); @@ -824,14 +822,21 @@ begin ibufgds_block: block signal cdrclk_in_temp: std_logic; begin - ibuf_ttc_clk : ibufds - port map (I=> CLK_TTC_P, IB=> CLK_TTC_N, O=> cdrclk_in_temp); + ibuf_ttc_clk : ibufds -- @suppress "Generic map uses default values. Missing optional actuals: CAPACITANCE, DIFF_TERM, DQS_BIAS, IBUF_DELAY_VALUE, IBUF_LOW_PWR, IFD_DELAY_VALUE, IOSTANDARD" + port map (O => cdrclk_in_temp, + I => CLK_TTC_P, + IB => CLK_TTC_N); bufg_ttc_clk: bufg - port map (I=> cdrclk_in_temp, O=> cdrclk_in); + port map ( + O => cdrclk_in, + I => cdrclk_in_temp); end block; -- ttc data - ibuf_ttc_data : ibufds - port map (I=> DATA_TTC_P, IB=> DATA_TTC_N, O=> xcdrdata_in); + ibuf_ttc_data : ibufds -- @suppress "Generic map uses default values. Missing optional actuals: CAPACITANCE, DIFF_TERM, DQS_BIAS, IBUF_DELAY_VALUE, IBUF_LOW_PWR, IFD_DELAY_VALUE, IOSTANDARD" + port map ( + O => xcdrdata_in, + I => DATA_TTC_P, + IB => DATA_TTC_N); CDR_IN_LATCH : process (cdrclk_in) begin @@ -888,33 +893,33 @@ ttc_dec: entity work.ttc_decoder_core --=====================================-- port map ( - RESET_N => RESET_N_s, - --== cdr interface ==-- - cdrclk_in_locked => cdrclk_in_locked, - cdrclk_in => cdrclk_in, - cdrdata_in => cdrdata_in, - --== ttc decoder output ==-- - single_bit_error => single_bit_error_ttcdec, - double_bit_error => double_bit_error_ttcdec, - communication_error => communication_error_ttcdec, - l1a => l1a_dec_ttcdec, - brc_strobe => open, --brc_strobe_ttcdec, --not used - add_strobe => add_strobe_ttcdec, --used for extracting the trigger ID from the long b-channel commands - --TTDDDDDEB - brc_t2 => brc_t2_ttcdec, - brc_d4 => brc_d4_ttcdec, - brc_e => brc_ei_ttcdec, --ECR - brc_b => brc_bi_ttcdec, --BCR - --AAAAAAAAAAAAAAE1SSSSSSSSDDDDDDDD - add_a14 => open, --add_a14_ttcdec, --not used - add_e => add_e_ttcdec, --used for extracting the trigger ID from the long b-channel commands - add_s8 => add_s8_ttcdec, --used for extracting the trigger ID from the long b-channel commands - add_d8 => add_d8_ttcdec, --used for extracting the trigger ID from the long b-channel commands - --== ttc decoder aux flags ==-- - ready => ready, -- the ttc_clk_gated is present - div_nrst => div_nrst_ttcdec, --1 when the TTC bistream is aligned and recognied. the TTC decoder core outputs garbage before that happens - channelB_o => channelB_ttcdec, - ttc_clk_gated => ttc_clk_gated--, + --RESET_N => RESET_N_s, + --== cdr interface ==-- + cdrclk_in_locked => cdrclk_in_locked, + cdrclk_in => cdrclk_in, + cdrdata_in => cdrdata_in, + --== ttc decoder output ==-- + single_bit_error => single_bit_error_ttcdec, + double_bit_error => double_bit_error_ttcdec, + communication_error => communication_error_ttcdec, + l1a => l1a_dec_ttcdec, + channelB_o => channelB_ttcdec, + brc_strobe => open, --brc_strobe_ttcdec, --not used + add_strobe => add_strobe_ttcdec, --used for extracting the trigger ID from the long b-channel commands + --TTDDDDDEB + brc_t2 => brc_t2_ttcdec, + brc_d4 => brc_d4_ttcdec, + brc_e => brc_ei_ttcdec, --ECR + brc_b => brc_bi_ttcdec, --BCR + --AAAAAAAAAAAAAAE1SSSSSSSSDDDDDDDD + add_a14 => open, --add_a14_ttcdec, --not used + add_e => add_e_ttcdec, --used for extracting the trigger ID from the long b-channel commands + add_s8 => add_s8_ttcdec, --used for extracting the trigger ID from the long b-channel commands + add_d8 => add_d8_ttcdec, --used for extracting the trigger ID from the long b-channel commands + --== ttc decoder aux flags ==-- + ready => ready, -- the ttc_clk_gated is present + div_nrst => div_nrst_ttcdec, --1 when the TTC bistream is aligned and recognied. the TTC decoder core outputs garbage before that happens + ttc_clk_gated => ttc_clk_gated --, --cdrclk_en => cdrclk_en );