From 7de72d725ac3ec530623dbeec09792c3cc2e233f Mon Sep 17 00:00:00 2001
From: Shakil Mahmud <smahmud@felix01.hep.anl.gov>
Date: Thu, 27 Jun 2024 00:52:27 -0500
Subject: [PATCH 1/6] Made changes to the framealigner, uplink, and gearbox
files
---
...lix_gbt_minipod_BNL712_transceiver_8ch.xdc | 7 +-
constraints/felix_top_BNL712.xdc | 271 +++++++++---------
sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE.vhd | 2 +-
.../LpGBT_FELIX/lpgbtfpga_framealigner.vhd | 215 ++++++++++----
.../LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd | 31 +-
sources/ip_cores/kintexUltrascale/ila_0.xci | 147 ++++------
6 files changed, 389 insertions(+), 284 deletions(-)
diff --git a/constraints/felix_gbt_minipod_BNL712_transceiver_8ch.xdc b/constraints/felix_gbt_minipod_BNL712_transceiver_8ch.xdc
index ff539ad0f..d76057fad 100644
--- a/constraints/felix_gbt_minipod_BNL712_transceiver_8ch.xdc
+++ b/constraints/felix_gbt_minipod_BNL712_transceiver_8ch.xdc
@@ -10,15 +10,12 @@ set_property PACKAGE_PIN AG43 [get_ports {RX_P[1]}]
#set_property PACKAGE_PIN AN43 [get_ports {RX_P[6]}]
#set_property PACKAGE_PIN AL43 [get_ports {RX_P[7]}]
#bank 133
-set_property -quiet PACKAGE_PIN C43 [get_ports {RX_P[4]}]
-set_property -quiet PACKAGE_PIN E43 [get_ports {RX_P[5]}]
-set_property -quiet PACKAGE_PIN G43 [get_ports {RX_P[6]}]
-set_property -quiet PACKAGE_PIN J43 [get_ports {RX_P[7]}]
#bank 231
-set_property -quiet PACKAGE_PIN J2 [get_ports {RX_P_LTITTC[0]}]
#MGT0,1,2,4 bank 128, use clk from bank 127 AH37
#MGT3,5,6,7 bank 127, use clk from bank 127 AH37
#MGT8k,9,10,11 bank 126, use clk from bank 127 AH37
#MGT12,13,14,15 bank 133, use clk from bank 132 T37
+
+
diff --git a/constraints/felix_top_BNL712.xdc b/constraints/felix_top_BNL712.xdc
index 46800dbce..7705bea00 100644
--- a/constraints/felix_top_BNL712.xdc
+++ b/constraints/felix_top_BNL712.xdc
@@ -1,3 +1,25 @@
+set_false_path -to [get_cells [list {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_rxresetdone_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_txresetdone_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[1].bit_synchronizer_rxresetdone_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[1].bit_synchronizer_txresetdone_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[2].bit_synchronizer_rxresetdone_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[2].bit_synchronizer_txresetdone_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[3].bit_synchronizer_rxresetdone_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[3].bit_synchronizer_txresetdone_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtpowergood_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_userclk_rx_active_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_userclk_tx_active_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_plllock_rx_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_plllock_tx_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_rxcdrlock_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.bit_synchronizer_masterphaligndone_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.bit_synchronizer_mastersyncdone_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst/gen_gtwiz_buffbypass_tx_main.gen_auto_mode.bit_synchronizer_master_phaligndone_inst/i_in_meta_reg} \
+ {linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0].g_712.GTH_TOP712_INST/RXNOBUF_GEN.g_712.gtwizard_ultrascale_four_channel_qpll_inst/inst/gen_gtwizard_gthe3_top.KCU_PMA_QPLL_4CH_LPGBT_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst/gen_gtwiz_buffbypass_tx_main.gen_auto_mode.bit_synchronizer_master_syncdone_inst/i_in_meta_reg}]]
###############################################################################
# User Configuration
# Link Width - x16
@@ -24,8 +46,8 @@
#! file TEST.XDC
#! net constraints for TEST design
-set_property IOSTANDARD LVCMOS25 [get_ports emcclk]
-set_property PACKAGE_PIN AK26 [get_ports emcclk]
+set_property IOSTANDARD LVCMOS25 [get_ports {emcclk[0]}]
+set_property PACKAGE_PIN AK26 [get_ports {emcclk[0]}]
#unused pin on bank 66
#set_property IOSTANDARD LVCMOS18 [get_ports emcclk_out]
@@ -65,14 +87,6 @@ set_property IOSTANDARD LVCMOS33 [get_ports {leds[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[6]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {leds[7]}]
-set_property -quiet PACKAGE_PIN P10 [get_ports {OPTO_LOS[0]}]
-set_property -quiet PACKAGE_PIN P14 [get_ports {OPTO_LOS[1]}]
-set_property -quiet PACKAGE_PIN P13 [get_ports {OPTO_LOS[2]}]
-set_property -quiet PACKAGE_PIN T13 [get_ports {OPTO_LOS[3]}]
-set_property -quiet IOSTANDARD LVCMOS33 [get_ports {OPTO_LOS[0]}]
-set_property -quiet IOSTANDARD LVCMOS33 [get_ports {OPTO_LOS[1]}]
-set_property -quiet IOSTANDARD LVCMOS33 [get_ports {OPTO_LOS[2]}]
-set_property -quiet IOSTANDARD LVCMOS33 [get_ports {OPTO_LOS[3]}]
################################################################################
# End User Constraints
@@ -109,11 +123,11 @@ set_property PULLUP true [get_ports sys_reset_n]
###############################################################################
# Timing Constraints, specific to BNL711 design. Other timing constraints are in timing_constraints.xdc
###############################################################################
-create_clock -period 10.000 -name sys_clk0 [get_pins g_endpoints[0].pcie0/ep0/g_NoSim.g_ultrascale.refclk_buff/O]
-create_clock -period 10.000 -name sys_clk1 [get_pins g_endpoints[1].pcie0/ep0/g_NoSim.g_ultrascale.refclk_buff/O]
-create_clock -period 20.000 -name sys_clkdiv2_0 [get_pins g_endpoints[0].pcie0/ep0/g_NoSim.g_ultrascale.refclk_buff/ODIV2]
-create_clock -period 20.000 -name sys_clkdiv2_1 [get_pins g_endpoints[1].pcie0/ep0/g_NoSim.g_ultrascale.refclk_buff/ODIV2]
-create_clock -period 2500 -name clk400 [get_pins hk0/*.pex_init0/data_clk_reg/Q]
+create_clock -period 10.000 -name sys_clk0 [get_pins {g_endpoints[0].pcie0/ep0/g_NoSim.g_ultrascale.refclk_buff/O}]
+create_clock -period 10.000 -name sys_clk1 [get_pins {g_endpoints[1].pcie0/ep0/g_NoSim.g_ultrascale.refclk_buff/O}]
+create_clock -period 20.000 -name sys_clkdiv2_0 [get_pins {g_endpoints[0].pcie0/ep0/g_NoSim.g_ultrascale.refclk_buff/ODIV2}]
+create_clock -period 20.000 -name sys_clkdiv2_1 [get_pins {g_endpoints[1].pcie0/ep0/g_NoSim.g_ultrascale.refclk_buff/ODIV2}]
+create_clock -period 2500.000 -name clk400 [get_pins hk0/*.pex_init0/data_clk_reg/Q]
create_clock -period 20.000 -name emcclk [get_ports emcclk]
#create_generated_clock -name clk_250mhz_x0y1 [get_pins g_endpoints[1].pcie0/ep0/g_NoSim.g_ultrascale.g_devid_7039.u1/U0/gt_top_i/phy_clk_i/bufg_gt_pclk/O]
@@ -182,8 +196,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports SDA]
#set_property PACKAGE_PIN W11 [get_ports I2C_nRESET]
#set_property IOSTANDARD LVCMOS33 [get_ports I2C_nRESET]
-set_property PACKAGE_PIN W10 [get_ports I2C_nRESET_PCIe]
-set_property IOSTANDARD LVCMOS33 [get_ports I2C_nRESET_PCIe]
+set_property PACKAGE_PIN W10 [get_ports {I2C_nRESET_PCIe[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {I2C_nRESET_PCIe[0]}]
## 200 MHz crystal clock input
#set_property IOSTANDARD LVDS [get_ports SYSCLK_P]
@@ -198,8 +212,8 @@ set_property DIFF_TERM_ADV TERM_100 [get_ports {TB_trigger_P[0]}]
set_property DIFF_TERM_ADV TERM_100 [get_ports {TB_trigger_N[0]}]
set_property PACKAGE_PIN G17 [get_ports {TB_trigger_P[0]}]
set_property PACKAGE_PIN F17 [get_ports {TB_trigger_N[0]}]
-set_property PULLTYPE PULLDOWN [get_ports {TB_trigger_P[0]}]
-set_property PULLTYPE PULLUP [get_ports {TB_trigger_N[0]}]
+set_property PULLDOWN true [get_ports {TB_trigger_P[0]}]
+set_property PULLUP true [get_ports {TB_trigger_N[0]}]
set_property IOSTANDARD LVDS [get_ports app_clk_in_p]
set_property IOSTANDARD LVDS [get_ports app_clk_in_n]
@@ -208,20 +222,20 @@ set_property DIFF_TERM_ADV TERM_100 [get_ports app_clk_in_n]
set_property PACKAGE_PIN AT18 [get_ports app_clk_in_p]
## ADN TTC inputs (Data and Clock)
-set_property PACKAGE_PIN H26 [get_ports DATA_TTC_P]
-set_property PACKAGE_PIN G25 [get_ports CLK_TTC_P]
-set_property IOSTANDARD LVDS [get_ports DATA_TTC_P]
-set_property IOSTANDARD LVDS [get_ports DATA_TTC_N]
-set_property IOSTANDARD LVDS [get_ports CLK_TTC_P]
-set_property IOSTANDARD LVDS [get_ports CLK_TTC_N]
-set_property IOSTANDARD LVCMOS33 [get_ports LOL_ADN]
-set_property PACKAGE_PIN L12 [get_ports LOL_ADN]
-set_property IOSTANDARD LVCMOS33 [get_ports LOS_ADN]
-set_property PACKAGE_PIN M11 [get_ports LOS_ADN]
+set_property PACKAGE_PIN H26 [get_ports {DATA_TTC_P[0]}]
+set_property PACKAGE_PIN G25 [get_ports {CLK_TTC_P[0]}]
+set_property IOSTANDARD LVDS [get_ports {DATA_TTC_P[0]}]
+set_property IOSTANDARD LVDS [get_ports {DATA_TTC_N[0]}]
+set_property IOSTANDARD LVDS [get_ports {CLK_TTC_P[0]}]
+set_property IOSTANDARD LVDS [get_ports {CLK_TTC_N[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LOL_ADN[0]}]
+set_property PACKAGE_PIN L12 [get_ports {LOL_ADN[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LOS_ADN[0]}]
+set_property PACKAGE_PIN M11 [get_ports {LOS_ADN[0]}]
## BUSY Out LEMO connector
-set_property PACKAGE_PIN J11 [get_ports BUSY_OUT]
-set_property IOSTANDARD LVCMOS33 [get_ports BUSY_OUT]
+set_property PACKAGE_PIN J11 [get_ports {BUSY_OUT[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {BUSY_OUT[0]}]
## These input buffers have to be declared but are unconnected in the design
set_property PACKAGE_PIN AN27 [get_ports {Perstn_open[0]}]
@@ -230,24 +244,24 @@ set_property PACKAGE_PIN AV28 [get_ports {Perstn_open[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Perstn_open[1]}]
## Ports to configure the PEX switch
-set_property PACKAGE_PIN AL12 [get_ports I2C_SMB]
-set_property IOSTANDARD LVCMOS18 [get_ports I2C_SMB]
-set_property PACKAGE_PIN AN22 [get_ports I2C_SMBUS_CFG_nEN]
-set_property IOSTANDARD LVCMOS18 [get_ports I2C_SMBUS_CFG_nEN]
-set_property PACKAGE_PIN AJ10 [get_ports MGMT_PORT_EN]
-set_property IOSTANDARD LVCMOS18 [get_ports MGMT_PORT_EN]
-set_property PACKAGE_PIN AK10 [get_ports SHPC_INT]
-set_property IOSTANDARD LVCMOS18 [get_ports SHPC_INT]
-set_property PACKAGE_PIN AH12 [get_ports PEX_PERSTn]
-set_property IOSTANDARD LVCMOS18 [get_ports PEX_PERSTn]
+set_property PACKAGE_PIN AL12 [get_ports {I2C_SMB[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {I2C_SMB[0]}]
+set_property PACKAGE_PIN AN22 [get_ports {I2C_SMBUS_CFG_nEN[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {I2C_SMBUS_CFG_nEN[0]}]
+set_property PACKAGE_PIN AJ10 [get_ports {MGMT_PORT_EN[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MGMT_PORT_EN[0]}]
+set_property PACKAGE_PIN AK10 [get_ports {SHPC_INT[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SHPC_INT[0]}]
+set_property PACKAGE_PIN AH12 [get_ports {PEX_PERSTn[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {PEX_PERSTn[0]}]
set_property PACKAGE_PIN AH11 [get_ports {PCIE_PERSTn_out[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {PCIE_PERSTn_out[0]}]
set_property PACKAGE_PIN AG11 [get_ports {PCIE_PERSTn_out[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {PCIE_PERSTn_out[1]}]
-set_property PACKAGE_PIN AT12 [get_ports PEX_SDA]
-set_property IOSTANDARD LVCMOS18 [get_ports PEX_SDA]
-set_property PACKAGE_PIN AU12 [get_ports PEX_SCL]
-set_property IOSTANDARD LVCMOS18 [get_ports PEX_SCL]
+set_property PACKAGE_PIN AT12 [get_ports {PEX_SDA[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {PEX_SDA[0]}]
+set_property PACKAGE_PIN AU12 [get_ports {PEX_SCL[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {PEX_SCL[0]}]
#Test points
#set_property PACKAGE_PIN AL14 [get_ports TP1_P]
@@ -277,53 +291,51 @@ set_property PACKAGE_PIN AL15 [get_ports {PORT_GOOD[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {PORT_GOOD[7]}]
## LMK03200
-set_property PACKAGE_PIN AU22 [get_ports CLK40_FPGA2LMK_P]
-set_property PACKAGE_PIN AV22 [get_ports CLK40_FPGA2LMK_N]
-set_property IOSTANDARD LVDS [get_ports CLK40_FPGA2LMK_P]
-set_property IOSTANDARD LVDS [get_ports CLK40_FPGA2LMK_N]
-set_property PACKAGE_PIN K13 [get_ports LMK_DATA]
-set_property IOSTANDARD LVCMOS33 [get_ports LMK_DATA]
-set_property PACKAGE_PIN J13 [get_ports LMK_CLK]
-set_property IOSTANDARD LVCMOS33 [get_ports LMK_CLK]
-set_property PACKAGE_PIN K12 [get_ports LMK_LE]
-set_property IOSTANDARD LVCMOS33 [get_ports LMK_LE]
-set_property PACKAGE_PIN L14 [get_ports LMK_GOE]
-set_property IOSTANDARD LVCMOS33 [get_ports LMK_GOE]
-set_property PACKAGE_PIN J14 [get_ports LMK_SYNCn]
-set_property IOSTANDARD LVCMOS33 [get_ports LMK_SYNCn]
-set_property PACKAGE_PIN L13 [get_ports LMK_LD]
-set_property IOSTANDARD LVCMOS33 [get_ports LMK_LD]
+set_property PACKAGE_PIN AU22 [get_ports {CLK40_FPGA2LMK_P[0]}]
+set_property PACKAGE_PIN AV22 [get_ports {CLK40_FPGA2LMK_N[0]}]
+set_property IOSTANDARD LVDS [get_ports {CLK40_FPGA2LMK_P[0]}]
+set_property IOSTANDARD LVDS [get_ports {CLK40_FPGA2LMK_N[0]}]
+set_property PACKAGE_PIN K13 [get_ports {LMK_DATA[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LMK_DATA[0]}]
+set_property PACKAGE_PIN J13 [get_ports {LMK_CLK[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LMK_CLK[0]}]
+set_property PACKAGE_PIN K12 [get_ports {LMK_LE[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LMK_LE[0]}]
+set_property PACKAGE_PIN L14 [get_ports {LMK_GOE[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LMK_GOE[0]}]
+set_property PACKAGE_PIN J14 [get_ports {LMK_SYNCn[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LMK_SYNCn[0]}]
+set_property PACKAGE_PIN L13 [get_ports {LMK_LD[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LMK_LD[0]}]
## Si5345 constraints
set_property PACKAGE_PIN N16 [get_ports {SI5345_INSEL[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {SI5345_INSEL[0]}]
set_property PACKAGE_PIN M16 [get_ports {SI5345_INSEL[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {SI5345_INSEL[1]}]
-set_property PACKAGE_PIN P16 [get_ports SI5345_nLOL]
-set_property IOSTANDARD LVCMOS18 [get_ports SI5345_nLOL]
-set_property PACKAGE_PIN R18 [get_ports SI5345_SEL]
-set_property IOSTANDARD LVCMOS18 [get_ports SI5345_SEL]
-set_property PACKAGE_PIN R17 [get_ports SI5345_OE]
-set_property IOSTANDARD LVCMOS18 [get_ports SI5345_OE]
+set_property PACKAGE_PIN P16 [get_ports {SI5345_nLOL[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SI5345_nLOL[0]}]
+set_property PACKAGE_PIN R18 [get_ports {SI5345_SEL[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SI5345_SEL[0]}]
+set_property PACKAGE_PIN R17 [get_ports {SI5345_OE[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SI5345_OE[0]}]
set_property PACKAGE_PIN R15 [get_ports {SI5345_A[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {SI5345_A[0]}]
set_property PACKAGE_PIN P15 [get_ports {SI5345_A[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {SI5345_A[1]}]
-set_property PACKAGE_PIN D35 [get_ports SI5345_RSTN]
-set_property IOSTANDARD LVCMOS18 [get_ports SI5345_RSTN]
set_property PACKAGE_PIN N18 [get_ports {SI5345_FDEC_B[0]}]
-set_property IOSTANDARD LVCMOS18 [get_ports {SI5345_FDEC_B[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SI5345_FDEC_B[0]}]
set_property PACKAGE_PIN R16 [get_ports {SI5345_FINC_B[0]}]
-set_property IOSTANDARD LVCMOS18 [get_ports {SI5345_FINC_B[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SI5345_FINC_B[0]}]
set_property PACKAGE_PIN P18 [get_ports {SI5345_INTR_B[0]}]
-set_property IOSTANDARD LVCMOS18 [get_ports {SI5345_INTR_B[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SI5345_INTR_B[0]}]
# Si5345 input from the main MMCM
-set_property IOSTANDARD LVDS [get_ports clk40_ttc_ref_out_p]
-set_property PACKAGE_PIN AT20 [get_ports clk40_ttc_ref_out_n]
-set_property IOSTANDARD LVDS [get_ports clk40_ttc_ref_out_n]
+set_property IOSTANDARD LVDS [get_ports {clk40_ttc_ref_out_p[0]}]
+set_property PACKAGE_PIN AT20 [get_ports {clk40_ttc_ref_out_n[0]}]
+set_property IOSTANDARD LVDS [get_ports {clk40_ttc_ref_out_n[0]}]
# Si5345 output to the FPGA fabric
## those are abused pins called DDR4 clocks
#set_property IOSTANDARD LVDS [get_ports clk_ttcfx_ref1_in_p]
@@ -333,39 +345,39 @@ set_property IOSTANDARD LVDS [get_ports clk40_ttc_ref_out_n]
#set_property PACKAGE_PIN H22 [get_ports clk_ttcfx_ref2_in_n]
#set_property IOSTANDARD LVDS [get_ports clk_ttcfx_ref2_in_n]
#unused, assign to random pin
-#set_property PACKAGE_PIN H21 [get_ports clk_adn_160_out_p]
-#set_property IOSTANDARD LVDS [get_ports clk_adn_160_out_p]
-#set_property IOSTANDARD LVDS [get_ports clk_adn_160_out_n]
+#set_property PACKAGE_PIN H21 [get_ports clk_adn_160_out_p]
+#set_property IOSTANDARD LVDS [get_ports clk_adn_160_out_p]
+#set_property IOSTANDARD LVDS [get_ports clk_adn_160_out_n]
-#set_property PACKAGE_PIN R21 [get_ports GTREFCLK_Si5324_P_IN]
-#set_property IOSTANDARD LVCMOS18 [get_ports GTREFCLK_Si5324_P_IN]
-#set_property PACKAGE_PIN R20 [get_ports GTREFCLK_Si5324_N_IN]
-#set_property IOSTANDARD LVCMOS18 [get_ports GTREFCLK_Si5324_N_IN]
+#set_property PACKAGE_PIN R21 [get_ports GTREFCLK_Si5324_P_IN]
+#set_property IOSTANDARD LVCMOS18 [get_ports GTREFCLK_Si5324_P_IN]
+#set_property PACKAGE_PIN R20 [get_ports GTREFCLK_Si5324_N_IN]
+#set_property IOSTANDARD LVCMOS18 [get_ports GTREFCLK_Si5324_N_IN]
-#set_property PACKAGE_PIN R22 [get_ports si5324_resetn]
-#set_property IOSTANDARD LVCMOS18 [get_ports si5324_resetn]
-set_property PACKAGE_PIN D35 [get_ports SI5345_RSTN]
-set_property IOSTANDARD LVCMOS18 [get_ports SI5345_RSTN]
+#set_property PACKAGE_PIN R22 [get_ports si5324_resetn]
+#set_property IOSTANDARD LVCMOS18 [get_ports si5324_resetn]
+set_property PACKAGE_PIN D35 [get_ports {SI5345_RSTN[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SI5345_RSTN[0]}]
-set_property PACKAGE_PIN P20 [get_ports i2cmux_rst]
-set_property IOSTANDARD LVCMOS18 [get_ports i2cmux_rst]
+set_property PACKAGE_PIN P20 [get_ports {i2cmux_rst[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {i2cmux_rst[0]}]
# Test Points connected to the Debug Port
# TP1_P - J3
-set_property PACKAGE_PIN AU17 [get_ports {SmaOut[0]}]
+set_property PACKAGE_PIN AU17 [get_ports {SmaOut[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {SmaOut[0]}]
# TP1_N - J4
-set_property PACKAGE_PIN AU16 [get_ports {SmaOut[1]}]
+set_property PACKAGE_PIN AU16 [get_ports {SmaOut[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {SmaOut[1]}]
# TP2_P - J5
-set_property PACKAGE_PIN P34 [get_ports {SmaOut[2]}]
+set_property PACKAGE_PIN P34 [get_ports {SmaOut[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {SmaOut[2]}]
# TP2_N - J9
-set_property PACKAGE_PIN P35 [get_ports {SmaOut[3]}]
+set_property PACKAGE_PIN P35 [get_ports {SmaOut[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {SmaOut[3]}]
-set_property PACKAGE_PIN B34 [get_ports uC_reset_N]
-set_property IOSTANDARD LVCMOS18 [get_ports uC_reset_N]
+set_property PACKAGE_PIN B34 [get_ports {uC_reset_N[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {uC_reset_N[0]}]
## some more constraints
@@ -506,21 +518,21 @@ set_property PACKAGE_PIN AP24 [get_ports {flash_d[15]}]
#set_property IOSTANDARD LVCMOS25 [get_ports clk]
#set_property PACKAGE_PIN AK26 [get_ports clk]
-set_property IOSTANDARD LVCMOS25 [get_ports flash_re]
-set_property PACKAGE_PIN BC24 [get_ports flash_re]
+set_property IOSTANDARD LVCMOS25 [get_ports {flash_re[0]}]
+set_property PACKAGE_PIN BC24 [get_ports {flash_re[0]}]
-set_property PACKAGE_PIN BD24 [get_ports flash_we]
-set_property IOSTANDARD LVCMOS25 [get_ports flash_we]
+set_property PACKAGE_PIN BD24 [get_ports {flash_we[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {flash_we[0]}]
-set_property PACKAGE_PIN AT24 [get_ports flash_adv]
-set_property IOSTANDARD LVCMOS25 [get_ports flash_adv]
+set_property PACKAGE_PIN AT24 [get_ports {flash_adv[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {flash_adv[0]}]
-set_property IOSTANDARD LVCMOS25 [get_ports flash_ce]
-set_property PACKAGE_PIN BA24 [get_ports flash_ce]
+set_property IOSTANDARD LVCMOS25 [get_ports {flash_ce[0]}]
+set_property PACKAGE_PIN BA24 [get_ports {flash_ce[0]}]
-set_property IOSTANDARD LVCMOS18 [get_ports flash_SEL]
-set_property PACKAGE_PIN AY18 [get_ports flash_SEL]
+set_property IOSTANDARD LVCMOS18 [get_ports {flash_SEL[0]}]
+set_property PACKAGE_PIN AY18 [get_ports {flash_SEL[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports PEX_SEL1]
#set_property PACKAGE_PIN AP20 [get_ports PEX_SEL1]
@@ -529,52 +541,47 @@ set_property PACKAGE_PIN AY18 [get_ports flash_SEL]
#set_property PACKAGE_PIN AR20 [get_ports PEX_SEL0]
-set_property IOSTANDARD LVCMOS25 [get_ports flash_cclk]
-set_property PACKAGE_PIN AJ25 [get_ports flash_cclk]
+set_property IOSTANDARD LVCMOS25 [get_ports {flash_cclk[0]}]
+set_property PACKAGE_PIN AJ25 [get_ports {flash_cclk[0]}]
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets emcclk_IBUF[0]_inst/O]
set_property IOSTANDARD LVCMOS18 [get_ports {TACH[0]}]
set_property PACKAGE_PIN AU36 [get_ports {TACH[0]}]
#bank 126, 127, 128 use clk from bank 127 Refclk1
-set_property PACKAGE_PIN AH37 [get_ports {GTREFCLK_P_IN[0]}]
set_property PACKAGE_PIN AH38 [get_ports {GTREFCLK_N_IN[0]}]
+set_property PACKAGE_PIN AH37 [get_ports {GTREFCLK_P_IN[0]}]
#bank 131, 132, 133 use clk from bank 132 Refclk1
set_property PACKAGE_PIN T37 [get_ports {GTREFCLK_P_IN[1]}]
set_property PACKAGE_PIN T38 [get_ports {GTREFCLK_N_IN[1]}]
#bank 231, 232, 233,use clk from bank 232 Refclk1, Q4_CLK0_GTREFCLK_PAD_N_IN
-set_property -quiet PACKAGE_PIN M8 [get_ports {GTREFCLK_P_IN[2]}]
-set_property -quiet PACKAGE_PIN M7 [get_ports {GTREFCLK_N_IN[2]}]
+set_property PACKAGE_PIN M8 [get_ports {GTREFCLK_P_IN[2]}]
+set_property PACKAGE_PIN M7 [get_ports {GTREFCLK_N_IN[2]}]
#bank 228 use clk from bank 228 Refclk0 Q5_CLK0_GTREFCLK_PAD_N_IN
-set_property -quiet PACKAGE_PIN AF8 [get_ports {GTREFCLK_P_IN[3]}]
-set_property -quiet PACKAGE_PIN AF7 [get_ports {GTREFCLK_N_IN[3]}]
+set_property PACKAGE_PIN AF8 [get_ports {GTREFCLK_P_IN[3]}]
+set_property PACKAGE_PIN AF7 [get_ports {GTREFCLK_N_IN[3]}]
#bank 224, 225 use clk from bank 225 Refclk0 Q6_CLK0_GTREFCLK_PAD_P_IN
-set_property -quiet PACKAGE_PIN AP8 [get_ports {GTREFCLK_P_IN[4]}]
-set_property -quiet PACKAGE_PIN AP7 [get_ports {GTREFCLK_N_IN[4]}]
+set_property PACKAGE_PIN AP8 [get_ports {GTREFCLK_P_IN[4]}]
+set_property PACKAGE_PIN AP7 [get_ports {GTREFCLK_N_IN[4]}]
#GTREFCLK0_LTITTC_P/N is the same pin as GTREFCLK_P_IN[6]
-set_property -quiet PACKAGE_PIN N6 [get_ports {GTREFCLK0_LTITTC_P[0]}]
-set_property -quiet PACKAGE_PIN N5 [get_ports {GTREFCLK0_LTITTC_N[0]}]
-
-set_property -quiet PACKAGE_PIN AL40 [get_ports {LMK_N[0]}]
-set_property -quiet PACKAGE_PIN AL39 [get_ports {LMK_P[0]}]
-set_property -quiet PACKAGE_PIN AF38 [get_ports {LMK_N[1]}]
-set_property -quiet PACKAGE_PIN AF37 [get_ports {LMK_P[1]}]
-set_property -quiet PACKAGE_PIN Y38 [get_ports {LMK_N[2]}]
-set_property -quiet PACKAGE_PIN Y37 [get_ports {LMK_P[2]}]
-set_property -quiet PACKAGE_PIN R40 [get_ports {LMK_N[3]}]
-set_property -quiet PACKAGE_PIN R39 [get_ports {LMK_P[3]}]
-set_property -quiet PACKAGE_PIN AD7 [get_ports {LMK_N[4]}]
-set_property -quiet PACKAGE_PIN AD8 [get_ports {LMK_P[4]}]
-set_property -quiet PACKAGE_PIN AN5 [get_ports {LMK_N[5]}]
-set_property -quiet PACKAGE_PIN AN6 [get_ports {LMK_P[5]}]
+
+set_property PACKAGE_PIN AL40 [get_ports {LMK_N[0]}]
+set_property PACKAGE_PIN AL39 [get_ports {LMK_P[0]}]
+set_property PACKAGE_PIN AF38 [get_ports {LMK_N[1]}]
+set_property PACKAGE_PIN AF37 [get_ports {LMK_P[1]}]
+set_property PACKAGE_PIN Y38 [get_ports {LMK_N[2]}]
+set_property PACKAGE_PIN Y37 [get_ports {LMK_P[2]}]
+set_property PACKAGE_PIN R40 [get_ports {LMK_N[3]}]
+set_property PACKAGE_PIN R39 [get_ports {LMK_P[3]}]
+set_property PACKAGE_PIN AD7 [get_ports {LMK_N[4]}]
+set_property PACKAGE_PIN AD8 [get_ports {LMK_P[4]}]
+set_property PACKAGE_PIN AN5 [get_ports {LMK_N[5]}]
+set_property PACKAGE_PIN AN6 [get_ports {LMK_P[5]}]
#GTREFCLK1_LTITTC_P/N is the same pin as LMK_P/N[6], either of them is used in the design
-set_property -quiet PACKAGE_PIN P7 [get_ports {GTREFCLK1_LTITTC_N[0]}]
-set_property -quiet PACKAGE_PIN P8 [get_ports {GTREFCLK1_LTITTC_P[0]}]
#set_property -quiet PACKAGE_PIN P7 [get_ports {LMK_N[6]}]
#set_property -quiet PACKAGE_PIN P8 [get_ports {LMK_P[6]}]
@@ -584,3 +591,5 @@ set_property -quiet PACKAGE_PIN P8 [get_ports {GTREFCLK1_LTITTC_P[0]}]
###############################################################################
# End
###############################################################################
+
+
diff --git a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE.vhd b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE.vhd
index b62f18aca..425fb0dfc 100644
--- a/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/FLX_LpGBT_BE.vhd
@@ -449,7 +449,7 @@ begin
-- Expert parameters
c_clockRatio => 8,
c_mgtWordWidth => 32,
- c_allowedFalseHeader => 32,
+ c_allowedFalseHeader => 38, --32,
c_allowedFalseHeaderOverN => 40,
c_requiredTrueHeader => 30,
c_MaxFecErrors => 5,
diff --git a/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_framealigner.vhd b/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_framealigner.vhd
index f2874cd41..d21a56f67 100644
--- a/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_framealigner.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_framealigner.vhd
@@ -5,6 +5,9 @@
--! @brief MGT word aligner (Pattern search)
-------------------------------------------------------
+-- This VHDL code represents the implementation of a frame aligner module (lpgbtfpga_framealigner) for MGT word alignment.
+-- It includes logic for pattern search, bitslip control, header detection, and state management to ensure proper alignment and synchronization of incoming data frames.
+
--! Include the IEEE VHDL standard LIBRARY
LIBRARY ieee;
USE ieee.std_logic_1164.all;
@@ -20,20 +23,20 @@ LIBRARY ieee;
ENTITY lpgbtfpga_framealigner IS
GENERIC (
c_wordRatio : integer; --! Word ration: frameclock / mgt_wordclock
- c_wordSize : integer; --! Size of the mgt word
+ c_wordSize : integer; --! Size of the mgt word (32 b)
c_headerPattern : std_logic_vector; --! Header pattern specified by the standard
- c_allowedFalseHeader : integer; --! Number of false header allowed to avoid unlock on frame error
+ c_allowedFalseHeader : integer; --! Number of false header allowed to avoid unlock on frame error // 32
c_allowedFalseHeaderOverN : integer; --! Number of header checked to know wether the lock is lost or not
- c_requiredTrueHeader : integer; --! Number of true header required to go in locked state
- c_MaxFecErrors : integer; --! Max FEC errors before to go in locked state
+ c_requiredTrueHeader : integer; --! Number of true header required to go in locked state // 30
+ c_MaxFecErrors : integer; --! Max FEC errors before to go in locked state // 5
c_bitslip_mindly : integer := 1; --! Number of clock cycle required WHEN asserting the bitslip SIGNAL
c_bitslip_waitdly : integer := 40 --! Number of clock cycle required before being back in a stable state
);
PORT (
-- Clock(s)
- clk_pcsRx_i : in std_logic; --! MGT Wordclock
+ clk_pcsRx_i : in std_logic; --! MGT Wordclock (320 MHz)
-- Reset(s)
rst_pattsearch_i : in std_logic; --! Rst the pattern search state machines
@@ -41,7 +44,7 @@ ENTITY lpgbtfpga_framealigner IS
cmd_bitslipCtrl_o : out std_logic; --! Bitslip SIGNAL to shift the parrallel word
-- Status
- sta_headerFecLocked_o : out std_logic; --! Status: header is FEC are locked
+ sta_headerFecLocked_o : out std_logic; --! Status: header is FEC are locked
sta_headerLocked_o : out std_logic; --! Status: header is locked
sta_headerFlag_o : out std_logic; --! Status: header flag (1 pulse over c_wordRatio)
sta_bitSlipEven_o : out std_logic; --! Status: number of bit slips is even
@@ -59,19 +62,21 @@ END lpgbtfpga_framealigner;
--! Check IF the header set on dat_word_i is equal to the c_headerPattern everytime a full
--! loop has been executed (c_wordRatio clock cycles). Manage the bitslip SIGNAL to shift
--! the mgt parallel word until the header is aligned.
+
+
ARCHITECTURE behavioral OF lpgbtfpga_framealigner IS
--================================ Signal Declarations ================================--
- TYPE machine IS (UNLOCKED, CHECK_HEADER, GOING_LOCK, LOCKED, GOING_UNLOCK);
+ TYPE machine IS (UNLOCKED, CHECK_HEADER, LOCKED, GOING_UNLOCK); --GOING_LOCK
SIGNAL state : machine;
- SIGNAL psAddress : integer RANGE 0 TO c_wordRatio;
+ SIGNAL psAddress : integer RANGE 0 TO c_wordRatio; -- Declares a signal psAddress to keep track of the pattern search address within a range determined by c_wordRatio.
SIGNAL shiftPsAddr : std_logic;
SIGNAL bitSlipCmd_s : std_logic;
SIGNAL headerFlag_s : std_logic;
SIGNAL sta_headerLocked_s : std_logic;
SIGNAL sta_headerFecLocked_s : std_logic;
- SIGNAL bitSlipCounter_s : integer RANGE 0 TO c_wordSize+1;
+ SIGNAL bitSlipCounter_s : integer RANGE 0 TO c_wordSize; -- changed c_wordSize+1 to c_wordSize
SIGNAL cmd_bitslipDone_s : std_logic;
@@ -81,11 +86,45 @@ ARCHITECTURE behavioral OF lpgbtfpga_framealigner IS
SIGNAL stateBitSlip : rxBitSlipCtrlStateLatOpt_T;
SIGNAL dat_word_s : std_logic_vector(c_headerPattern'length-1 downto 0);
+
+ signal num_fec_errors : integer range 0 to c_MaxFecErrors;
+ signal consec_false_headers : integer range 0 to c_allowedFalseHeader;
+ signal consec_correct_headers: integer range 0 to c_requiredTrueHeader;
+
+ --test
+
+ signal cmd_bitslipCtrl_s : std_logic;
+
+ COMPONENT ila_2 IS
+ PORT (
+ clk : IN STD_LOGIC;
+ probe0 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe6 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+ probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe9 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe13 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ probe14 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+ probe15 : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
+ );
+ END COMPONENT;
+
--=================================================================================================--
BEGIN --========#### Architecture Body ####========--
--=================================================================================================--
--==================================== User Logic =====================================--
+
+ -- Process for handling data word pipeline logic, which updates dat_word_s based on clock and reset signals.
+
rxWordPipeline_proc: PROCESS(rst_pattsearch_i, clk_pcsRx_i)
BEGIN
IF rst_pattsearch_i = '1' THEN
@@ -96,6 +135,9 @@ BEGIN --========#### Architecture Body ####========--
END PROCESS;
--! MGT: Bitslip controller
+
+ -- Process for managing the bitslip control logic, including state transitions and timing.
+
clkSlipProcess: PROCESS(rst_pattsearch_i, clk_pcsRx_i)
VARIABLE timer : integer RANGE 0 TO (c_bitslip_waitdly+c_bitslip_mindly);
BEGIN
@@ -103,6 +145,7 @@ BEGIN --========#### Architecture Body ####========--
IF rst_pattsearch_i = '1' THEN
stateBitSlip <= e0_idle;
cmd_bitslipCtrl_o <= '0';
+ cmd_bitslipCtrl_s <= '0';
cmd_bitslipDone_s <= '0';
ELSIF rising_edge(clk_pcsRx_i) THEN
@@ -116,7 +159,8 @@ BEGIN --========#### Architecture Body ####========--
END IF;
WHEN e4_doBitslip => cmd_bitslipCtrl_o <= '1';
- IF timer >= c_bitslip_mindly-1 THEN
+ cmd_bitslipCtrl_s <= '1';
+ IF timer = c_bitslip_mindly-1 THEN
stateBitSlip <= e5_waitNcycles;
timer := 0;
ELSE
@@ -124,7 +168,8 @@ BEGIN --========#### Architecture Body ####========--
END IF;
WHEN e5_waitNcycles => cmd_bitslipCtrl_o <= '0';
- IF timer >= c_bitslip_waitdly-1 THEN
+ cmd_bitslipCtrl_s <= '0';
+ IF timer = c_bitslip_waitdly-1 THEN
stateBitSlip <= e0_idle;
ELSE
timer := timer + 1;
@@ -140,6 +185,9 @@ BEGIN --========#### Architecture Body ####========--
sta_headerFecLocked_o <= sta_headerFecLocked_s;
--! Pattern searcher: check the header and ask for bitslip
+
+ -- Process for performing pattern search and generating bitslip commands based on the received data word.
+
patternSearch_proc: PROCESS(rst_pattsearch_i, clk_pcsRx_i)
BEGIN
@@ -157,8 +205,8 @@ BEGIN --========#### Architecture Body ####========--
IF (dat_word_s(c_headerPattern'length-1 downto 0) /= c_headerPattern) THEN
- if bitSlipCounter_s < c_wordSize+1 then
- sta_bitSlipEven_s <= not(sta_bitSlipEven_s);
+ if bitSlipCounter_s < c_wordSize then -- it should be bitSlipCounter_s < c_wordSize
+ sta_bitSlipEven_s <= not(sta_bitSlipEven_s); -- Why we need this?
bitSlipCmd_s <= '1';
bitSlipCounter_s <= bitSlipCounter_s + 1;
else
@@ -173,6 +221,9 @@ BEGIN --========#### Architecture Body ####========--
END PROCESS;
--! Pattern search address controller
+
+ -- Process for controlling the pattern search address and updating psAddress.
+
patternSearchAddr_proc: PROCESS(rst_pattsearch_i, clk_pcsRx_i)
BEGIN
@@ -198,78 +249,88 @@ BEGIN --========#### Architecture Body ####========--
END IF;
END PROCESS;
+
--! Header locked state machine
+
+ -- Process implementing the header locked state machine logic, determining the state based on received data word and FEC errors.
+
lockFSM_proc: PROCESS(rst_pattsearch_i, clk_pcsRx_i)
VARIABLE consecFalseHeaders : integer RANGE 0 TO c_allowedFalseHeader;
VARIABLE consecCorrectHeaders : integer RANGE 0 TO c_requiredTrueHeader;
VARIABLE nbCheckedHeaders : integer RANGE 0 TO c_allowedFalseHeaderOverN;
- VARIABLE numFecErrors : integer RANGE 0 TO c_MaxFecErrors;
+ VARIABLE numFecErrors : integer RANGE 0 TO c_MaxFecErrors;
BEGIN
-
IF rst_pattsearch_i = '1' THEN
- state <= UNLOCKED;
- numFecErrors := 0;
+ state <= UNLOCKED;
+ consecFalseHeaders := 0;
+ consecCorrectHeaders:= 0;
+ nbCheckedHeaders := 0;
+ numFecErrors := 0;
ELSIF rising_edge(clk_pcsRx_i) THEN
- IF psAddress = 0 and cmd_bitslipDone_s = '1' THEN
+ -- Added the following signals for ILA
+ num_fec_errors <= numFecErrors;
+ consec_false_headers <= consecFalseHeaders;
+ consec_correct_headers <= consecCorrectHeaders;
- IF (state = UNLOCKED) THEN
- numFecErrors := 0;
- ELSIF (fec_error_i = '1' and numFecErrors < c_MaxFecErrors) THEN
- numFecErrors := numFecErrors + 1;
- END IF;
+ IF psAddress = 0 THEN
- CASE state is
+ -- IF (fec_error_i = '1' AND numFecErrors < c_MaxFecErrors) THEN
+ -- numFecErrors := numFecErrors + 1;
+ -- END IF;
- WHEN UNLOCKED => IF (dat_word_s(c_headerPattern'length-1 downto 0) = c_headerPattern) THEN
+ CASE state IS
+ WHEN UNLOCKED =>
+ IF (dat_word_s(c_headerPattern'length-1 DOWNTO 0) = c_headerPattern AND fec_error_i = '0') THEN
state <= CHECK_HEADER;
consecCorrectHeaders := 0;
+
END IF;
- WHEN CHECK_HEADER => IF (dat_word_s(c_headerPattern'length-1 downto 0) /= c_headerPattern) THEN
+ WHEN CHECK_HEADER =>
+ IF (dat_word_s(c_headerPattern'length-1 DOWNTO 0) /= c_headerPattern OR fec_error_i = '1') THEN
state <= UNLOCKED;
-
ELSE
consecCorrectHeaders := consecCorrectHeaders + 1;
- IF (consecCorrectHeaders >= c_requiredTrueHeader) THEN
- state <= GOING_LOCK;
+ IF (consecCorrectHeaders = c_requiredTrueHeader) THEN
+ state <= LOCKED; -- GOING_LOCK;
END IF;
END IF;
- WHEN GOING_LOCK => IF (numFecErrors = c_MaxFecErrors) THEN
- state <= UNLOCKED;
- ELSE
- state <= LOCKED;
- END IF;
-
- WHEN LOCKED =>
- IF (numFecErrors = c_MaxFecErrors) THEN
- consecFalseHeaders := 0;
- nbCheckedHeaders := 0;
- state <= UNLOCKED;
- ELSIF (dat_word_s(c_headerPattern'length-1 downto 0) /= c_headerPattern) THEN
- consecFalseHeaders := 0;
- nbCheckedHeaders := 0;
+ -- WHEN GOING_LOCK =>
+ -- IF (numFecErrors = c_MaxFecErrors) THEN -- It was numFecErrors = c_MaxFecErrors
+ -- state <= UNLOCKED;
+ -- ELSE
+ -- state <= LOCKED;
+ -- END IF;
+
+ WHEN LOCKED =>
+ -- IF (numFecErrors = c_MaxFecErrors) THEN
+ -- state <= UNLOCKED;
+ -- numFecErrors := 0; -- Reset numFecErrors when transitioning to UNLOCKED
+ -- ELS
+ IF (dat_word_s(c_headerPattern'length-1 DOWNTO 0) /= c_headerPattern OR fec_error_i = '1') THEN
state <= GOING_UNLOCK;
+ consecFalseHeaders := 0; -- Reset after transition
+ nbCheckedHeaders := 0;
+
END IF;
+ WHEN GOING_UNLOCK =>
+ -- IF (numFecErrors >= c_MaxFecErrors) THEN
+ -- state <= UNLOCKED;
+ -- ELS
- WHEN GOING_UNLOCK =>
- IF (numFecErrors = c_MaxFecErrors) THEN
- state <= UNLOCKED;
- ELSIF (dat_word_s(c_headerPattern'length-1 downto 0) = c_headerPattern) THEN
+ IF (dat_word_s(c_headerPattern'length-1 DOWNTO 0) = c_headerPattern AND fec_error_i = '0') THEN
IF nbCheckedHeaders = c_allowedFalseHeaderOverN THEN
state <= LOCKED;
ELSE
nbCheckedHeaders := nbCheckedHeaders + 1;
END IF;
-
ELSE
-
consecFalseHeaders := consecFalseHeaders + 1;
-
- IF consecFalseHeaders >= c_allowedFalseHeader THEN
+ IF consecFalseHeaders = c_allowedFalseHeader THEN
state <= UNLOCKED;
END IF;
END IF;
@@ -279,6 +340,10 @@ BEGIN --========#### Architecture Body ####========--
END IF;
END PROCESS;
+
+
+ -- Process for synchronizing and updating the header locked status based on the current state.
+
headerLocked_sync: PROCESS(rst_pattsearch_i, clk_pcsRx_i)
BEGIN
IF rst_pattsearch_i = '1' THEN
@@ -299,8 +364,52 @@ BEGIN --========#### Architecture Body ####========--
END IF;
END PROCESS;
- sta_headerFlag_o <= headerFlag_s WHEN (state /= UNLOCKED) ELSE '0';
---=====================================================================================--
+ sta_headerFlag_o <= '1' when psAddress = 7 else '0'; -- headerFlag_s WHEN (state /= UNLOCKED) ELSE '0';
+ --=====================================================================================--
+
+
+
+ --ILA goes here
+ --psAddress : integer RANGE 0 TO c_wordRatio; -- 3b
+ --shiftPsAddr : std_logic; *****
+ --bitSlipCmd_s : std_logic;
+ --headerFlag_s : std_logic;
+ --sta_headerLocked_s : std_logic;
+ --sta_headerFecLocked_s : std_logic;
+ --bitSlipCounter_s : integer RANGE 0 TO c_wordSize+1; -- 5b
+ --cmd_bitslipDone_s : std_logic;
+ --sta_bitSlipEven_s : std_logic;
+ --dat_word_s : std_logic_vector(c_headerPattern'length-1 downto 0); -- 2b
+ --fec_error_i : in std_logic;
+ --rst_pattsearch_i : in std_logic;
+ --cmd_bitslipCtrl_o : out std_logic;
+ --num_fec_errors : integer range 0 to c_MaxFecErrors; ***** -- 3b
+ --consec_false_headers : integer range 0 to c_allowedFalseHeader; --5b
+ --consec_correct_headers: integer range 0 to c_requiredTrueHeader; --5b
+
+
+ instance_name: ila_2
+ PORT MAP (
+ clk => clk_pcsRx_i,
+ probe0 => std_logic_vector(to_unsigned(psAddress, 3)),
+ probe1(0) => shiftPsAddr,
+ probe2(0) => bitSlipCmd_s,
+ probe3(0) => headerFlag_s,
+ probe4(0) => sta_headerLocked_s,
+ probe5(0) => sta_headerFecLocked_s,
+ probe6 => std_logic_vector(to_unsigned(bitSlipCounter_s, 5)),
+ probe7(0) => cmd_bitslipDone_s,
+ probe8(0) => sta_bitSlipEven_s,
+ probe9 => dat_word_s,
+ probe10(0) => fec_error_i,
+ probe11(0) => rst_pattsearch_i,
+ probe12(0) => cmd_bitslipCtrl_s,
+ probe13 => std_logic_vector(to_unsigned(num_fec_errors, 3)),
+ probe14 => std_logic_vector(to_unsigned(consec_false_headers, 5)),
+ probe15 => std_logic_vector(to_unsigned(consec_correct_headers, 5))
+ );
+
+
END behavioral;
--=================================================================================================--
--#################################################################################################--
diff --git a/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd b/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd
index 6ef1787e3..da30857ab 100644
--- a/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd
@@ -286,15 +286,20 @@ ARCHITECTURE behavioral OF lpgbtfpga_uplink IS
SIGNAL uplinkCorrEc_10g24_s : std_logic_vector(1 downto 0); --! Uplink correction flag output for 10g24 datarate configuration (EC)
SIGNAL uplinkCorrIc_10g24_s : std_logic_vector(1 downto 0); --! Uplink correction flag output for 10g24 datarate configuration (IC)
+ SIGNAL uplinkCorrData_10g24_fa : std_logic_vector(229 downto 0);
+
SIGNAL uplinkCorrData_5g12_s : std_logic_vector(229 downto 0); --! Uplink correction flag output for 5g12 datarate configuration (User data)
SIGNAL uplinkCorrEc_5g12_s : std_logic_vector(1 downto 0); --! Uplink correction flag output for 5g12 datarate configuration (EC)
SIGNAL uplinkCorrIc_5g12_s : std_logic_vector(1 downto 0); --! Uplink correction flag output for 5g12 datarate configuration (IC)
+ SIGNAL uplinkCorrData_5g12_fa : std_logic_vector(229 downto 0);
+
SIGNAL frame_pipelined_s : std_logic_vector(255 downto 0); --! Store input data in register to ensure stability
SIGNAL clkEnOut_s : std_logic;
- SIGNAL rst_synch_s : std_logic;
+ SIGNAL rst_synch_s : std_logic := '1';
signal fec_error_i : std_logic;
+ signal fec_error_fa : std_logic;
signal fec_error_40_i : std_logic;
signal fec_err_cnt_i : unsigned(31 downto 0);
signal dataCorrected_s : std_logic_vector(229 downto 0);
@@ -303,6 +308,9 @@ ARCHITECTURE behavioral OF lpgbtfpga_uplink IS
signal uplinkRst_n_40_i : std_logic;
+ CONSTANT ZERO_VECTOR_10G24 : std_logic_vector(uplinkCorrData_10g24_fa'length - 1 DOWNTO 0) := (OTHERS => '0');
+ CONSTANT ZERO_VECTOR_5G12 : std_logic_vector(uplinkCorrData_5g12_fa'length - 1 DOWNTO 0) := (OTHERS => '0');
+
--attribute MARK_DEBUG : string;
--attribute MARK_DEBUG of dataCorrected_s: signal is "true";
@@ -346,17 +354,28 @@ BEGIN --========#### Architecture Body ####========--
dat_word_i => mgt_word_i(1 downto 0),
-- FEC error
- fec_error_i => fec_error_i
+ fec_error_i => fec_error_fa
);
+ uplinkCorrData_10g24_fa <= fec5_correction_s(229 downto 0) WHEN (FEC = FEC5) ELSE "0000000000000000000000000000" & fec12_correction_s(201 downto 0);
+ uplinkCorrData_5g12_fa <= x"00000000000000000000000000000" & "00" & fec5_correction_s(111 downto 0) WHEN (FEC = FEC5) ELSE
+ x"000000000000000000000000000000000" & fec12_correction_s(97 downto 0);
+
+ -- fec_error_fa <= '0' when (uplinkCorrData_10g24_fa = (others => '0') AND DATARATE = DATARATE_10G24) OR
+ -- uplinkCorrData_5g12_fa = (others => '0') else '1';
+
+ fec_error_fa <= '0' WHEN (uplinkCorrData_10g24_fa = ZERO_VECTOR_10G24 AND DATARATE = DATARATE_10G24) OR
+ (uplinkCorrData_5g12_fa = ZERO_VECTOR_5G12) ELSE '1';
+
+
sta_headerFecLocked_out <= sta_headerFecLocked_s;
sta_headerFlag_out <= sta_headerFlag_s;
rst_gearbox_s <= not(sta_headerLocked_s);
-- lpgbtfpga_rxGearbox is used to pass from mgt word size (e.g.: 32b @ 320MHz)
- -- to lpgbt frame size (e.g.: 256b at 40MHz)
+ -- to lpgbt frame size (e.g.: 256b at 40MHz)s
rxgearbox_10g_gen: IF DATARATE = DATARATE_10G24 GENERATE
rxGearbox_10g24_inst: lpgbtfpga_rxGearbox
GENERIC MAP(
@@ -370,13 +389,13 @@ BEGIN --========#### Architecture Body ####========--
clk_inClk_i => uplinkClk_i,
clk_outClk_i => uplinkClk_i,
clk_clkEn_i => sta_headerFlag_s,
- clk_dataFlag_o => sta_dataflag_s,
+ clk_dataFlag_o => sta_dataflag_s, -- ILA signal
rst_gearbox_i => rst_gearbox_s,
-- Data
dat_inFrame_i => mgt_word_i,
- dat_outFrame_o => gbxFrame_s,
+ dat_outFrame_o => gbxFrame_s, -- ILA signal
-- Status
sta_gbRdy_o => sta_gbRdy_s
@@ -631,7 +650,7 @@ BEGIN --========#### Architecture Body ####========--
clk_i => uplinkClk_i,
clkEn_i => clkEnOut_s,
- reset_i => datapath_rst_s,
+ reset_i => rst_gearbox_s, -- datapath_rst_s,
-- Data
fec5_data_i => fec5_data_from_decoder_s,
diff --git a/sources/ip_cores/kintexUltrascale/ila_0.xci b/sources/ip_cores/kintexUltrascale/ila_0.xci
index b1927a604..9156ca212 100644
--- a/sources/ip_cores/kintexUltrascale/ila_0.xci
+++ b/sources/ip_cores/kintexUltrascale/ila_0.xci
@@ -16,31 +16,31 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.PHASE">0.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.ADDR_WIDTH">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.BUSER_WIDTH">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.CLK_DOMAIN"/>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.DATA_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.DATA_WIDTH">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_BRESP">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_BURST">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_CACHE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_LOCK">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_PROT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_PROT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_QOS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_REGION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_RRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.ID_WIDTH">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.INSERT_VIP">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.PHASE">0.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.PROTOCOL"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
@@ -56,17 +56,17 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.PHASE">0.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TDATA_NUM_BYTES">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TDEST_WIDTH">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TID_WIDTH">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TUSER_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TDEST_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TID_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADV_TRIGGER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFBOUT_MULT_F">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_DIVIDE_F">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_FREQ">200</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_PERIOD">5.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORE_MAJOR_VER">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_DEPTH">4096</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_DEPTH">2048</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DDR_CLK_GEN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK_DIVIDE">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_ILA_AXI_MON">0</spirit:configurableElementValue>
@@ -78,7 +78,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MAJOR_VERSION">2021</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MINOR_VERSION">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_MONITOR_SLOTS">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OF_PROBES">26</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OF_PROBES">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SLOT_0_AXI_PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TIME_TAG_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIGIN_EN">0</spirit:configurableElementValue>
@@ -96,7 +96,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CLKOUT0_DIVIDE_F">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CLK_FREQ">200</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CLK_PERIOD">5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DATA_DEPTH">4096</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DATA_DEPTH">2048</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DDR_CLK_GEN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DIVCLK_DIVIDE">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ENABLE_ILA_AXI_MON">FALSE</spirit:configurableElementValue>
@@ -107,10 +107,10 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INPUT_PIPE_STAGES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MONITOR_TYPE">Native</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_MONITOR_SLOTS">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_OF_PROBES">26</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_OF_PROBES">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE0_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE0_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE0_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE0_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1000_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1000_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1000_WIDTH">1</spirit:configurableElementValue>
@@ -215,7 +215,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE109_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE10_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE10_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE10_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE10_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE110_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE110_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE110_WIDTH">1</spirit:configurableElementValue>
@@ -248,7 +248,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE119_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE11_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE11_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE11_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE11_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE120_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE120_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE120_WIDTH">1</spirit:configurableElementValue>
@@ -281,7 +281,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE129_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE12_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE12_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE12_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE12_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE130_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE130_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE130_WIDTH">1</spirit:configurableElementValue>
@@ -314,7 +314,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE139_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE13_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE13_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE13_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE13_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE140_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE140_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE140_WIDTH">1</spirit:configurableElementValue>
@@ -347,7 +347,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE149_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE14_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE14_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE14_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE14_WIDTH">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE150_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE150_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE150_WIDTH">1</spirit:configurableElementValue>
@@ -380,7 +380,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE159_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE15_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE15_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE15_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE15_WIDTH">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE160_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE160_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE160_WIDTH">1</spirit:configurableElementValue>
@@ -411,9 +411,9 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE169_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE169_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE169_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE16_MU_CNT">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE16_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE16_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE16_WIDTH">80</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE16_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE170_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE170_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE170_WIDTH">1</spirit:configurableElementValue>
@@ -444,9 +444,9 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE179_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE179_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE179_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE17_MU_CNT">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE17_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE17_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE17_WIDTH">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE17_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE180_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE180_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE180_WIDTH">1</spirit:configurableElementValue>
@@ -477,9 +477,9 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE189_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE189_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE189_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE18_MU_CNT">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE18_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE18_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE18_WIDTH">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE18_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE190_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE190_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE190_WIDTH">1</spirit:configurableElementValue>
@@ -510,12 +510,12 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE199_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE199_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE199_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE19_MU_CNT">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE19_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE19_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE19_WIDTH">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE19_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1_WIDTH">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE200_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE200_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE200_WIDTH">1</spirit:configurableElementValue>
@@ -546,9 +546,9 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE209_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE209_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE209_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE20_MU_CNT">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE20_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE20_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE20_WIDTH">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE20_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE210_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE210_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE210_WIDTH">1</spirit:configurableElementValue>
@@ -579,9 +579,9 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE219_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE219_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE219_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE21_MU_CNT">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE21_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE21_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE21_WIDTH">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE21_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE220_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE220_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE220_WIDTH">1</spirit:configurableElementValue>
@@ -612,9 +612,9 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE229_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE229_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE229_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE22_MU_CNT">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE22_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE22_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE22_WIDTH">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE22_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE230_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE230_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE230_WIDTH">1</spirit:configurableElementValue>
@@ -645,9 +645,9 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE239_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE239_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE239_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE23_MU_CNT">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE23_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE23_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE23_WIDTH">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE23_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE240_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE240_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE240_WIDTH">1</spirit:configurableElementValue>
@@ -678,7 +678,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE249_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE249_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE249_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE24_MU_CNT">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE24_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE24_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE24_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE250_MU_CNT">1</spirit:configurableElementValue>
@@ -711,9 +711,9 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE259_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE259_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE259_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE25_MU_CNT">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE25_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE25_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE25_WIDTH">120</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE25_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE260_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE260_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE260_WIDTH">1</spirit:configurableElementValue>
@@ -848,7 +848,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE29_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE2_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE2_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE2_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE2_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE300_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE300_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE300_WIDTH">1</spirit:configurableElementValue>
@@ -1181,7 +1181,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE39_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE3_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE3_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE3_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE3_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE400_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE400_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE400_WIDTH">1</spirit:configurableElementValue>
@@ -1514,7 +1514,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE49_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE4_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE4_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE4_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE4_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE500_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE500_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE500_WIDTH">1</spirit:configurableElementValue>
@@ -1847,7 +1847,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE59_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE5_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE5_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE5_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE5_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE600_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE600_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE600_WIDTH">1</spirit:configurableElementValue>
@@ -2180,7 +2180,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE69_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE6_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE6_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE6_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE6_WIDTH">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE700_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE700_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE700_WIDTH">1</spirit:configurableElementValue>
@@ -2513,7 +2513,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE79_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE7_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE7_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE7_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE7_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE800_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE800_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE800_WIDTH">1</spirit:configurableElementValue>
@@ -2846,7 +2846,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE89_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE8_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE8_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE8_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE8_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE900_MU_CNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE900_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE900_WIDTH">1</spirit:configurableElementValue>
@@ -3179,7 +3179,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE99_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE9_MU_CNT">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE9_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE9_WIDTH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE9_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SLOT_0_AXIS_TDATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SLOT_0_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SLOT_0_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
@@ -3215,7 +3215,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">12</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIG.gen/sources_1/ip/ila_0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../FLX712_FELIX.gen/sources_1/ip/ila_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
@@ -3225,13 +3225,13 @@
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.BUSER_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_REGION" xilinx:valueSource="auto"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.HAS_TKEEP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.HAS_TLAST" xilinx:valueSource="auto"/>
@@ -3246,62 +3246,33 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EN_STRG_QUAL" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUM_OF_PROBES" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE0_MU_CNT" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE0_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE10_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE10_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE11_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE11_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE12_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE12_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE13_MU_CNT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE13_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE14_MU_CNT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE14_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE15_MU_CNT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE15_WIDTH" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE16_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE16_WIDTH" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE17_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE17_WIDTH" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE18_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE18_WIDTH" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE19_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE19_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE1_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE1_WIDTH" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE20_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE20_WIDTH" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE21_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE21_WIDTH" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE22_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE22_WIDTH" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE23_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE23_WIDTH" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE24_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE25_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE25_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE2_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE2_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE3_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE3_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE4_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE4_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE5_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE5_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE6_MU_CNT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE6_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE7_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE7_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE8_MU_CNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE8_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE9_MU_CNT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE9_WIDTH" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
<xilinx:boundaryDescriptionInfo>
- <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"clk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"probe0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"probe1":[{"direction":"in","physical_left":"15","physical_right":"0","is_vector":"true"}],"probe10":[{"direction":"in","physical_left":"9","physical_right":"0","is_vector":"true"}],"probe11":[{"direction":"in","physical_left":"9","physical_right":"0","is_vector":"true"}],"probe12":[{"direction":"in","physical_left":"9","physical_right":"0","is_vector":"true"}],"probe13":[{"direction":"in","physical_left":"9","physical_right":"0","is_vector":"true"}],"probe14":[{"direction":"in","physical_left":"9","physical_right":"0","is_vector":"true"}],"probe15":[{"direction":"in","physical_left":"9","physical_right":"0","is_vector":"true"}],"probe16":[{"direction":"in","physical_left":"79","physical_right":"0","is_vector":"true"}],"probe17":[{"direction":"in","physical_left":"2","physical_right":"
-0","is_vector":"true"}],"probe18":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"probe19":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"probe2":[{"direction":"in","physical_left":"9","physical_right":"0","is_vector":"true"}],"probe20":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"probe21":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"probe22":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"probe23":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"probe24":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"probe25":[{"direction":"in","physical_left":"119","physical_right":"0","is_vector":"true"}],"probe3":[{"direction":"in","physical_left":"9","physical_right":"0","is_vector":"true"}],"probe4":[{"direction":"in","physical_left":"9","physical_right":
-"0","is_vector":"true"}],"probe5":[{"direction":"in","physical_left":"9","physical_right":"0","is_vector":"true"}],"probe6":[{"direction":"in","physical_left":"9","physical_right":"0","is_vector":"true"}],"probe7":[{"direction":"in","physical_left":"9","physical_right":"0","is_vector":"true"}],"probe8":[{"direction":"in","physical_left":"9","physical_right":"0","is_vector":"true"}],"probe9":[{"direction":"in","physical_left":"9","physical_right":"0","is_vector":"true"}]},"interfaces":{"signal_clock":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"SLOT_0_AXI:SLOT_0_AXIS","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"ASSOCIATED_PORT":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,
-"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"d
-efault","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"clk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
+ <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"clk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"probe0":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"probe1":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"probe10":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"probe11":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"probe12":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"probe13":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"probe14":[{"direction":"in","physical_left":"4","physical_right":"0","is_vector":"true"}],"probe15":[{"direction":"in","physical_left":"4","physical_right":"0","is_vector":"true"}],"probe2":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"probe3":[{"direction":"in","physical_left":"0","physical_right":"0","
+is_vector":"true"}],"probe4":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"probe5":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"probe6":[{"direction":"in","physical_left":"5","physical_right":"0","is_vector":"true"}],"probe7":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"probe8":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"probe9":[{"direction":"in","physical_left":"1","physical_right":"0","is_vector":"true"}]},"interfaces":{"signal_clock":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"SLOT_0_AXI:SLOT_0_AXIS","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"ASSOCIATED_PORT":[{"value":"","value_src":"default","value_permission":"user
+","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is
+_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"clk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
</xilinx:boundaryDescriptionInfo>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
--
GitLab
From cd0d420c615bfa4332616fc0d47db64b3bcce6c9 Mon Sep 17 00:00:00 2001
From: Shakil Mahmud <smahmud@hpcfpga01.hep.anl.gov>
Date: Fri, 5 Jul 2024 13:44:38 -0500
Subject: [PATCH 2/6] Updated rxgearbox file
---
.../LpGBT/LpGBT_FELIX/lpgbtfpga_rxgearbox.vhd | 203 ++++++++++++++++++
1 file changed, 203 insertions(+)
create mode 100644 sources/LpGBT/LpGBT_FELIX/lpgbtfpga_rxgearbox.vhd
diff --git a/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_rxgearbox.vhd b/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_rxgearbox.vhd
new file mode 100644
index 000000000..4ef11c5de
--- /dev/null
+++ b/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_rxgearbox.vhd
@@ -0,0 +1,203 @@
+-------------------------------------------------------
+--! @file
+--! @author Julian Mendez <julian.mendez@cern.ch> (CERN - EP-ESE-BE)
+--! @version 2.0
+--! @brief Rx gearbox
+-------------------------------------------------------
+
+--! Include the IEEE VHDL standard LIBRARY
+LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+ USE ieee.numeric_std.all;
+
+--! @brief lpgbtfpga_rxGearbox - Rx Gearbox
+--! @details
+--! The Rx gearbox module is USEd to ensure the MGT to Datapath clock domain
+--! crossing. It takes the c_inputWidth bit words in input and generates an c_outputWidth bit
+--! word every c_clockRatio clock cycle. When the clock ratio is bigger than the word ratio (oversampling),
+--! each word get from each phase is stored in different words that are concatenated and set in output.
+--! E.g.: (A0)(A1)(B0)(B1)(C0)(C1) where (A0) and (A1) are the "same bit" (2 samples took by the MGT in the same UI,
+--! becaUSE of the oversampling), the output is (A0)(B0)(C0)(A1)(B1)(B1).
+ENTITY lpgbtfpga_rxGearbox IS
+ GENERIC (
+ c_clockRatio : integer; --! Clock ratio is clock_out / clock_in (shall be an integer)
+ c_inputWidth : integer; --! Bus size of the input word
+ c_outputWidth : integer; --! Bus size of the output word (Warning: c_clockRatio/(c_inputWidth/c_outputWidth) shall be an integer)
+ c_counterInitValue : integer := 2 --! Initialization value of the gearbox counter (3 for simulation / 2 for real HW)
+ );
+ PORT (
+ -- Clock and reset
+ clk_inClk_i : in std_logic; --! Input clock (from MGT)
+ clk_outClk_i : in std_logic; --! Output clock (from MGT)
+ clk_clkEn_i : in std_logic; --! Clock enable (e.g.: header flag)
+ clk_dataFlag_o : out std_logic;
+
+ rst_gearbox_i : in std_logic; --! Reset SIGNAL
+
+ -- Data
+ dat_inFrame_i : in std_logic_vector((c_inputWidth-1) downto 0); --! Input data from MGT
+ dat_outFrame_o : out std_logic_vector((c_inputWidth*c_clockRatio)-1 downto 0); --! Output data, concatenation of word WHEN the word ratio is lower than clock ration (e.g.: out <= word & word;)
+
+ -- Status
+ sta_gbRdy_o : out std_logic --! Ready SIGNAL
+ );
+END lpgbtfpga_rxGearbox;
+
+--! @brief lpgbtfpga_rxGearbox - Rx Gearbox
+--! @details
+--! The rxGearbox implements a register based clock domain crossing system. Using different clock
+--! for the input and output require a special attention on the phase relation between these two
+--! signals.
+ARCHITECTURE behavioral OF lpgbtfpga_rxGearbox IS
+
+ --==================================== User Logic =====================================--
+ CONSTANT c_oversampling : integer := c_clockRatio/(c_outputWidth/c_inputWidth);
+
+ SIGNAL reg0 : std_logic_vector (((c_inputWidth*c_clockRatio)-1) downto 0);
+ SIGNAL reg1 : std_logic_vector (((c_inputWidth*c_clockRatio)-1) downto 0);
+ SIGNAL rxFrame_inverted_s : std_logic_vector (((c_inputWidth*c_clockRatio)-1) downto 0);
+
+ SIGNAL gbReset_s : std_logic;
+ SIGNAL sta_gbRdy_s0 : std_logic;
+ SIGNAL sta_gbRdy_s : std_logic;
+ SIGNAL clk_dataFlag_s : std_logic;
+
+ SIGNAL dat_outFrame_s : std_logic_vector((c_inputWidth*c_clockRatio)-1 downto 0);
+
+ SIGNAL dat_inFrame_s : std_logic_vector((c_inputWidth-1) downto 0);
+
+ SIGNAL gbReset_outsynch_s : std_logic;
+ --=====================================================================================--
+
+
+ COMPONENT ila_3 IS
+ PORT (
+ clk : IN STD_LOGIC;
+ probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ probe1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0)
+ );
+ END COMPONENT;
+
+
+
+--=================================================================================================--
+BEGIN --========#### Architecture Body ####========--
+ --=================================================================================================--
+
+ -- gbRstSynch_proc: PROCESS(rst_gearbox_i, clk_inClk_i)
+ -- BEGIN
+
+ -- IF rst_gearbox_i = '1' THEN
+ -- gbReset_s <= '1';
+
+ -- ELSIF rising_edge(clk_inClk_i) THEN
+
+ -- IF clk_clkEn_i = '1' THEN
+ -- gbReset_s <= '0';
+ -- END IF;
+
+ -- END IF;
+ -- END PROCESS;
+
+ -- rxWordPipeline_proc: PROCESS(gbReset_s, clk_inClk_i)
+ -- BEGIN
+ -- IF gbReset_s = '1' THEN
+ -- dat_inFrame_s <= (OTHERS => '0');
+ -- ELSIF rising_edge(clk_inClk_i) THEN
+ -- dat_inFrame_s <= dat_inFrame_i;
+ -- END IF;
+ -- END PROCESS;
+
+
+ gbRegMan_proc: PROCESS(clk_inClk_i) -- gbReset_s,
+ VARIABLE cnter : integer RANGE 0 to (c_clockRatio-1) := 0;
+ BEGIN
+
+ -- IF gbReset_s = '1' THEN
+ -- reg0 <= (OTHERS => '0');
+ -- reg1 <= (OTHERS => '0');
+ -- sta_gbRdy_s0 <= '0';
+
+ -- cnter := c_counterInitValue;
+
+ -- ELS
+ IF rising_edge(clk_inClk_i) THEN
+ clk_dataFlag_s <= '0';
+
+ if clk_clkEn_i = '1' then
+ cnter := 0; --clk_clkEn_i is at the same clock cycle as a header word
+ end if;
+
+ IF cnter = 0 THEN --the counter is 0 when a word with a header is receivd. The full word can be output and we fill in a new word.
+ reg1 <= reg0;
+ clk_dataFlag_s <= '1';
+ --sta_gbRdy_s0 <= '1';
+ --sta_gbRdy_s <= sta_gbRdy_s0; --Delay ready for 1 word. First word could be corrupted
+ END IF;
+
+ reg0((c_inputWidth*(1+cnter))-1 downto (c_inputWidth*cnter)) <= dat_inFrame_i; -- dat_inFrame_s;
+
+ IF cnter = (c_clockRatio-1) THEN
+ cnter := 0;
+ else
+ cnter := cnter + 1;
+ END IF;
+ END IF;
+
+ END PROCESS;
+
+ frameInverter: FOR i IN ((c_inputWidth*c_clockRatio)-1) downto 0 GENERATE
+ rxFrame_inverted_s(i) <= reg1(((c_inputWidth*c_clockRatio)-1)-i);
+ END GENERATE;
+
+ oversamplerMultPh: FOR i IN 0 TO (c_oversampling-1) GENERATE
+ oversamplerPhN: FOR j IN 0 TO (c_outputWidth-1) GENERATE
+ dat_outFrame_s((i*c_outputWidth)+j) <= rxFrame_inverted_s((j*c_oversampling)+i);
+ END GENERATE;
+ END GENERATE;
+
+ -- Pipeline dat_outFrame_o to avoid clocking issue
+ -- clkEnPipeline_proc: PROCESS(clk_outClk_i)
+ -- BEGIN
+ -- IF rising_edge(clk_outClk_i) THEN
+ -- gbReset_outsynch_s <= gbReset_s;
+ -- END IF;
+ -- END PROCESS;
+
+ outPipeline_proc: PROCESS(clk_outClk_i) --gbReset_outsynch_s
+ BEGIN
+ -- IF gbReset_outsynch_s = '1' THEN
+ -- dat_outFrame_o <= (OTHERS => '0');
+ -- clk_dataFlag_o <= '0';
+ -- sta_gbRdy_o <= '0';
+
+ -- ELS
+ IF rising_edge(clk_outClk_i) THEN
+
+ clk_dataFlag_o <= clk_dataFlag_s;
+ dat_outFrame_o <= dat_outFrame_s;
+ --sta_gbRdy_o <= sta_gbRdy_s;
+
+ END IF;
+ END PROCESS;
+
+ sta_gbRdy_o <= '1';
+ --=====================================================================================--
+
+ --ILA goes here
+ --clk_dataFlag_o : out std_logic;
+ --dat_outFrame_o : out std_logic_vector((c_inputWidth*c_clockRatio)-1 downto 0);-- c_inputWidth=32,c_clockRatio=8 -- 255 downto 0
+
+
+ instance_name: ila_3
+ PORT MAP (
+ clk => clk_inClk_i,
+ probe0(0) => clk_dataFlag_s,
+ probe1 => dat_outFrame_s
+ );
+
+
+END behavioral;
+--=================================================================================================--
+--#################################################################################################--
+--=================================================================================================--
--
GitLab
From f07cd7e4d162d61a08787386ba05a97d2f0ad859 Mon Sep 17 00:00:00 2001
From: Shakil Mahmud <smahmud@hpcfpga01.hep.anl.gov>
Date: Fri, 5 Jul 2024 14:18:03 -0500
Subject: [PATCH 3/6] Updated scripts
---
scripts/filesets/lpgbt_core_fileset.tcl | 1 +
scripts/filesets/lpgbt_fe_core_fileset.tcl | 1 +
2 files changed, 2 insertions(+)
diff --git a/scripts/filesets/lpgbt_core_fileset.tcl b/scripts/filesets/lpgbt_core_fileset.tcl
index f6ba6c499..10209b1a4 100644
--- a/scripts/filesets/lpgbt_core_fileset.tcl
+++ b/scripts/filesets/lpgbt_core_fileset.tcl
@@ -27,6 +27,7 @@ set VHDL_FILES [concat $VHDL_FILES \
LpGBT/LpGBT_FELIX/Regs_RW.vhd \
LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd \
LpGBT/LpGBT_FELIX/lpgbtfpga_framealigner.vhd \
+ LpGBT/LpGBT_FELIX/lpgbtfpga_rxgearbox.vhd \
LpGBT/LpGBT_CERN/BE/lpgbt-fpga/lpgbtfpga_package.vhd \
LpGBT/LpGBT_CERN/BE/lpgbt-fpga/lpgbtfpga_downlink.vhd \
LpGBT/LpGBT_CERN/BE/lpgbt-fpga/downlink/lpgbtfpga_encoder.vhd \
diff --git a/scripts/filesets/lpgbt_fe_core_fileset.tcl b/scripts/filesets/lpgbt_fe_core_fileset.tcl
index faf2df05a..3f0adf85a 100644
--- a/scripts/filesets/lpgbt_fe_core_fileset.tcl
+++ b/scripts/filesets/lpgbt_fe_core_fileset.tcl
@@ -27,6 +27,7 @@ set VHDL_FILES [concat $VHDL_FILES \
LpGBT/LpGBT_FELIX/Regs_RW.vhd \
LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd \
LpGBT/LpGBT_FELIX/lpgbtfpga_framealigner.vhd \
+ LpGBT/LpGBT_FELIX/lpgbtfpga_rxgearbox.vhd \
LpGBT/LpGBT_CERN/FE/lpgbt-emul/lpgbtemul_top.vhd \
LpGBT/LpGBT_CERN/FE/lpgbt-emul/mgt_frameAligner_pv.vhd \
LpGBT/LpGBT_CERN/FE/lpgbt-emul/rxgearbox.vhd \
--
GitLab
From 3eb61b952e3a989c15094cd77c009b3716a8d02c Mon Sep 17 00:00:00 2001
From: aparamonov1 <alexander.paramonov@cern.ch>
Date: Mon, 8 Jul 2024 19:49:51 -0500
Subject: [PATCH 4/6] FLX-2395 updated scripts and removed ilas
---
scripts/filesets/lpgbt_core_fileset.tcl | 1 -
scripts/filesets/lpgbt_fe_core_fileset.tcl | 1 -
.../LpGBT_FELIX/lpgbtfpga_framealigner.vhd | 74 +------------------
.../LpGBT/LpGBT_FELIX/lpgbtfpga_rxgearbox.vhd | 27 +------
4 files changed, 3 insertions(+), 100 deletions(-)
diff --git a/scripts/filesets/lpgbt_core_fileset.tcl b/scripts/filesets/lpgbt_core_fileset.tcl
index 10209b1a4..fbc77e79c 100644
--- a/scripts/filesets/lpgbt_core_fileset.tcl
+++ b/scripts/filesets/lpgbt_core_fileset.tcl
@@ -40,7 +40,6 @@ set VHDL_FILES [concat $VHDL_FILES \
LpGBT/LpGBT_CERN/BE/lpgbt-fpga/uplink/fec_rsDecoderN15K13.vhd \
LpGBT/LpGBT_CERN/BE/lpgbt-fpga/uplink/lpgbtfpga_decoder.vhd \
LpGBT/LpGBT_CERN/BE/lpgbt-fpga/uplink/lpgbtfpga_descrambler.vhd \
- LpGBT/LpGBT_CERN/BE/lpgbt-fpga/uplink/lpgbtfpga_rxgearbox.vhd \
LpGBT/LpGBT_CERN/BE/lpgbt-fpga/uplink/descrambler_53bitOrder49.vhd \
LpGBT/LpGBT_CERN/BE/lpgbt-fpga/uplink/descrambler_60bitOrder58.vhd \
LpGBT/LpGBT_CERN/BE/lpgbt-fpga/uplink/fec_rsDecoderN31K29.vhd \
diff --git a/scripts/filesets/lpgbt_fe_core_fileset.tcl b/scripts/filesets/lpgbt_fe_core_fileset.tcl
index 3f0adf85a..e1f0ce987 100644
--- a/scripts/filesets/lpgbt_fe_core_fileset.tcl
+++ b/scripts/filesets/lpgbt_fe_core_fileset.tcl
@@ -30,7 +30,6 @@ set VHDL_FILES [concat $VHDL_FILES \
LpGBT/LpGBT_FELIX/lpgbtfpga_rxgearbox.vhd \
LpGBT/LpGBT_CERN/FE/lpgbt-emul/lpgbtemul_top.vhd \
LpGBT/LpGBT_CERN/FE/lpgbt-emul/mgt_frameAligner_pv.vhd \
- LpGBT/LpGBT_CERN/FE/lpgbt-emul/rxgearbox.vhd \
LpGBT/LpGBT_CERN/FE/lpgbt-emul/txgearbox.vhd]
set XCI_FILES_V7 [concat $XCI_FILES_V7 \
diff --git a/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_framealigner.vhd b/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_framealigner.vhd
index d21a56f67..683444673 100644
--- a/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_framealigner.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_framealigner.vhd
@@ -91,31 +91,6 @@ ARCHITECTURE behavioral OF lpgbtfpga_framealigner IS
signal consec_false_headers : integer range 0 to c_allowedFalseHeader;
signal consec_correct_headers: integer range 0 to c_requiredTrueHeader;
- --test
-
- signal cmd_bitslipCtrl_s : std_logic;
-
- COMPONENT ila_2 IS
- PORT (
- clk : IN STD_LOGIC;
- probe0 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
- probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe6 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
- probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe9 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe13 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
- probe14 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
- probe15 : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
- );
- END COMPONENT;
--=================================================================================================--
BEGIN --========#### Architecture Body ####========--
@@ -145,7 +120,6 @@ BEGIN --========#### Architecture Body ####========--
IF rst_pattsearch_i = '1' THEN
stateBitSlip <= e0_idle;
cmd_bitslipCtrl_o <= '0';
- cmd_bitslipCtrl_s <= '0';
cmd_bitslipDone_s <= '0';
ELSIF rising_edge(clk_pcsRx_i) THEN
@@ -159,7 +133,6 @@ BEGIN --========#### Architecture Body ####========--
END IF;
WHEN e4_doBitslip => cmd_bitslipCtrl_o <= '1';
- cmd_bitslipCtrl_s <= '1';
IF timer = c_bitslip_mindly-1 THEN
stateBitSlip <= e5_waitNcycles;
timer := 0;
@@ -168,7 +141,6 @@ BEGIN --========#### Architecture Body ####========--
END IF;
WHEN e5_waitNcycles => cmd_bitslipCtrl_o <= '0';
- cmd_bitslipCtrl_s <= '0';
IF timer = c_bitslip_waitdly-1 THEN
stateBitSlip <= e0_idle;
ELSE
@@ -340,8 +312,6 @@ BEGIN --========#### Architecture Body ####========--
END IF;
END PROCESS;
-
-
-- Process for synchronizing and updating the header locked status based on the current state.
headerLocked_sync: PROCESS(rst_pattsearch_i, clk_pcsRx_i)
@@ -365,49 +335,7 @@ BEGIN --========#### Architecture Body ####========--
END PROCESS;
sta_headerFlag_o <= '1' when psAddress = 7 else '0'; -- headerFlag_s WHEN (state /= UNLOCKED) ELSE '0';
- --=====================================================================================--
-
-
-
- --ILA goes here
- --psAddress : integer RANGE 0 TO c_wordRatio; -- 3b
- --shiftPsAddr : std_logic; *****
- --bitSlipCmd_s : std_logic;
- --headerFlag_s : std_logic;
- --sta_headerLocked_s : std_logic;
- --sta_headerFecLocked_s : std_logic;
- --bitSlipCounter_s : integer RANGE 0 TO c_wordSize+1; -- 5b
- --cmd_bitslipDone_s : std_logic;
- --sta_bitSlipEven_s : std_logic;
- --dat_word_s : std_logic_vector(c_headerPattern'length-1 downto 0); -- 2b
- --fec_error_i : in std_logic;
- --rst_pattsearch_i : in std_logic;
- --cmd_bitslipCtrl_o : out std_logic;
- --num_fec_errors : integer range 0 to c_MaxFecErrors; ***** -- 3b
- --consec_false_headers : integer range 0 to c_allowedFalseHeader; --5b
- --consec_correct_headers: integer range 0 to c_requiredTrueHeader; --5b
-
-
- instance_name: ila_2
- PORT MAP (
- clk => clk_pcsRx_i,
- probe0 => std_logic_vector(to_unsigned(psAddress, 3)),
- probe1(0) => shiftPsAddr,
- probe2(0) => bitSlipCmd_s,
- probe3(0) => headerFlag_s,
- probe4(0) => sta_headerLocked_s,
- probe5(0) => sta_headerFecLocked_s,
- probe6 => std_logic_vector(to_unsigned(bitSlipCounter_s, 5)),
- probe7(0) => cmd_bitslipDone_s,
- probe8(0) => sta_bitSlipEven_s,
- probe9 => dat_word_s,
- probe10(0) => fec_error_i,
- probe11(0) => rst_pattsearch_i,
- probe12(0) => cmd_bitslipCtrl_s,
- probe13 => std_logic_vector(to_unsigned(num_fec_errors, 3)),
- probe14 => std_logic_vector(to_unsigned(consec_false_headers, 5)),
- probe15 => std_logic_vector(to_unsigned(consec_correct_headers, 5))
- );
+--=====================================================================================--
END behavioral;
diff --git a/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_rxgearbox.vhd b/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_rxgearbox.vhd
index 4ef11c5de..c7c39ae7f 100644
--- a/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_rxgearbox.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/lpgbtfpga_rxgearbox.vhd
@@ -67,17 +67,7 @@ ARCHITECTURE behavioral OF lpgbtfpga_rxGearbox IS
SIGNAL dat_inFrame_s : std_logic_vector((c_inputWidth-1) downto 0);
SIGNAL gbReset_outsynch_s : std_logic;
- --=====================================================================================--
-
-
- COMPONENT ila_3 IS
- PORT (
- clk : IN STD_LOGIC;
- probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- probe1 : IN STD_LOGIC_VECTOR(255 DOWNTO 0)
- );
- END COMPONENT;
-
+--=====================================================================================--
--=================================================================================================--
@@ -182,20 +172,7 @@ BEGIN --========#### Architecture Body ####========--
END PROCESS;
sta_gbRdy_o <= '1';
- --=====================================================================================--
-
- --ILA goes here
- --clk_dataFlag_o : out std_logic;
- --dat_outFrame_o : out std_logic_vector((c_inputWidth*c_clockRatio)-1 downto 0);-- c_inputWidth=32,c_clockRatio=8 -- 255 downto 0
-
-
- instance_name: ila_3
- PORT MAP (
- clk => clk_inClk_i,
- probe0(0) => clk_dataFlag_s,
- probe1 => dat_outFrame_s
- );
-
+--=====================================================================================--
END behavioral;
--=================================================================================================--
--
GitLab
From f989abc9d4b2aa62784c471c6017ed024a940a13 Mon Sep 17 00:00:00 2001
From: Frans Schreuder <f.schreuder@nikhef.nl>
Date: Tue, 9 Jul 2024 10:46:06 +0200
Subject: [PATCH 5/6] Moved lpgbtemul_top.vhd to LpGBT/LpGBT_FELIX
---
scripts/filesets/lpgbt_fe_core_fileset.tcl | 2 +-
sources/LpGBT/LpGBT_FELIX/lpgbtemul_top.vhd | 413 ++++++++++++++++++++
2 files changed, 414 insertions(+), 1 deletion(-)
create mode 100644 sources/LpGBT/LpGBT_FELIX/lpgbtemul_top.vhd
diff --git a/scripts/filesets/lpgbt_fe_core_fileset.tcl b/scripts/filesets/lpgbt_fe_core_fileset.tcl
index e1f0ce987..5c1a21fd9 100644
--- a/scripts/filesets/lpgbt_fe_core_fileset.tcl
+++ b/scripts/filesets/lpgbt_fe_core_fileset.tcl
@@ -28,7 +28,7 @@ set VHDL_FILES [concat $VHDL_FILES \
LpGBT/LpGBT_FELIX/lpgbtfpga_uplink.vhd \
LpGBT/LpGBT_FELIX/lpgbtfpga_framealigner.vhd \
LpGBT/LpGBT_FELIX/lpgbtfpga_rxgearbox.vhd \
- LpGBT/LpGBT_CERN/FE/lpgbt-emul/lpgbtemul_top.vhd \
+ LpGBT/LpGBT_FELIX/lpgbtemul_top.vhd \
LpGBT/LpGBT_CERN/FE/lpgbt-emul/mgt_frameAligner_pv.vhd \
LpGBT/LpGBT_CERN/FE/lpgbt-emul/txgearbox.vhd]
diff --git a/sources/LpGBT/LpGBT_FELIX/lpgbtemul_top.vhd b/sources/LpGBT/LpGBT_FELIX/lpgbtemul_top.vhd
new file mode 100644
index 000000000..41162920e
--- /dev/null
+++ b/sources/LpGBT/LpGBT_FELIX/lpgbtemul_top.vhd
@@ -0,0 +1,413 @@
+-- IEEE VHDL standard library:
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--use work.lpgbtfpga_package.all;
+--=================================================================================================--
+--####################################### Entity ##############################################--
+--=================================================================================================--
+
+entity lpgbtemul_top is
+ generic(
+ -- MGT-specific parameters
+ -- Read your MGT user guide before connecting them
+ rxslide_pulse_duration : integer:= 2; -- Duration of GT_RXSLIDE_OUT pulse
+ rxslide_pulse_delay : integer:= 128 -- Minimum time between two GT_RXSLIDE_OUT pulses
+ );
+ port(
+ -- DownLink
+ downlinkClkEn_o : out std_logic;
+ downLinkDataGroup0 : out std_logic_vector(15 downto 0);
+ downLinkDataGroup1 : out std_logic_vector(15 downto 0);
+ downLinkDataEc : out std_logic_vector(1 downto 0);
+ downLinkDataIc : out std_logic_vector(1 downto 0);
+ downlinkRdy_o : out std_logic;
+
+ -- Uplink
+ uplinkClkEn_i : in std_logic;
+ upLinkData0 : in std_logic_vector(31 downto 0);
+ upLinkData1 : in std_logic_vector(31 downto 0);
+ upLinkData2 : in std_logic_vector(31 downto 0);
+ upLinkData3 : in std_logic_vector(31 downto 0);
+ upLinkData4 : in std_logic_vector(31 downto 0);
+ upLinkData5 : in std_logic_vector(31 downto 0);
+ upLinkData6 : in std_logic_vector(31 downto 0);
+ upLinkDataIC : in std_logic_vector(1 downto 0);
+ upLinkDataEC : in std_logic_vector(1 downto 0);
+ uplinkRdy_o : out std_logic;
+
+ -- Uplink mode
+ fecMode : in std_logic; -- 0=FEC5, 1=FEC12
+ txDataRate : in std_logic; -- 1=5G , 2=10G
+
+ -- Transceiver
+ GT_RXUSRCLK_IN : in std_logic;
+ GT_TXUSRCLK_IN : in std_logic;
+ GT_RXSLIDE_OUT : out std_logic;
+ GT_TXREADY_IN : in std_logic;
+ GT_RXREADY_IN : in std_logic;
+ GT_TXDATA_OUT : out std_logic_vector(31 downto 0);
+ GT_RXDATA_IN : in std_logic_vector(31 downto 0)
+
+ );
+end lpgbtemul_top;
+
+--=================================================================================================--
+--#################################### Architecture ###########################################--
+--=================================================================================================--
+
+architecture behavioral of lpgbtemul_top is
+
+ -- Downlink
+ signal dat_downLinkWord_fromMgt_s : std_logic_vector(31 downto 0);
+ signal sta_mgtRxRdy_s : std_logic;
+ signal rst_pattsearch_s : std_logic;
+ signal ctr_clkSlip_s : std_logic;
+ signal sta_headeLocked_s : std_logic;
+ signal sta_headerFlag_s : std_logic;
+ signal sta_rxgbxRdy_s : std_logic;
+ signal rst_datapath_s : std_logic;
+ signal dat_downLinkWord_fromGb_s : std_logic_vector(255 downto 0);
+ signal dat_downLinkWord_fromGbInv_s : std_logic_vector(63 downto 0);
+ signal dat_downLinkWord_toPattSrch_s : std_logic_vector(15 downto 0);
+ signal clk_mgtRxUsrclk_s : std_logic;
+ signal downlinkRdy_s0 : std_logic;
+ signal downlinkRdy_s1 : std_logic;
+ signal RX_CLKEn_s : std_logic;
+ signal downLinkDataIc_s : std_logic_vector(1 downto 0);
+ signal downLinkDataEc_s : std_logic_vector(1 downto 0);
+ signal downLinkDataGroup1_s : std_logic_vector(15 downto 0);
+ signal downLinkDataGroup0_s : std_logic_vector(15 downto 0);
+ signal clk_dataFlag_rxGb_s : std_logic;
+
+ -- Uplink
+ signal clk_mgtTxUsrclk_s : std_logic;
+ signal sta_mgtTxRdy_s : std_logic;
+ signal uplinkClkEn_shgb_s : std_logic;
+ signal sta_txGbRdy_s : std_logic;
+ signal dat_upLinkWord_fromLpGBT_s : std_logic_vector(255 downto 0);
+ signal dat_upLinkWord_fromLpGBT_pipeline_s : std_logic_vector(255 downto 0);
+ signal dat_upLinkWord_toGb_s : std_logic_vector(255 downto 0);
+ signal dat_upLinkWord_toGb_pipeline_s : std_logic_vector(255 downto 0);
+ signal dat_upLinkWord_fromGb_s : std_logic_vector(31 downto 0);
+ signal rst_uplinkGb_s : std_logic;
+ signal rst_uplinkGb_synch_s : std_logic;
+ signal rst_uplinkMgt_s : std_logic;
+ signal rst_uplinkInitDone_s : std_logic;
+ signal rst_downlinkInitDone_s : std_logic;
+ signal upLinkData0_s : std_logic_vector(31 downto 0);
+ signal upLinkData1_s : std_logic_vector(31 downto 0);
+ signal upLinkData2_s : std_logic_vector(31 downto 0);
+ signal upLinkData3_s : std_logic_vector(31 downto 0);
+ signal upLinkData4_s : std_logic_vector(31 downto 0);
+ signal upLinkData5_s : std_logic_vector(31 downto 0);
+ signal upLinkData6_s : std_logic_vector(31 downto 0);
+ signal upLinkDataIC_s : std_logic_vector(1 downto 0);
+ signal upLinkDataEC_s : std_logic_vector(1 downto 0);
+
+ component upLinkTxDataPath
+ port (
+ clk : in std_logic;
+ dataEnable : in std_logic;
+ txDataGroup0 : in std_logic_vector(31 downto 0);
+ txDataGroup1 : in std_logic_vector(31 downto 0);
+ txDataGroup2 : in std_logic_vector(31 downto 0);
+ txDataGroup3 : in std_logic_vector(31 downto 0);
+ txDataGroup4 : in std_logic_vector(31 downto 0);
+ txDataGroup5 : in std_logic_vector(31 downto 0);
+ txDataGroup6 : in std_logic_vector(31 downto 0);
+
+ txIC : in std_logic_vector( 1 downto 0);
+ txEC : in std_logic_vector( 1 downto 0);
+ txDummyFec5 : in std_logic_vector( 5 downto 0);
+ txDummyFec12 : in std_logic_vector( 9 downto 0);
+ scramblerBypass : in std_logic;
+ interleaverBypass : in std_logic;
+ fecMode : in std_logic;
+ txDataRate : in std_logic;
+ fecDisable : in std_logic;
+ scramblerReset : in std_logic;
+ upLinkFrame : out std_logic_vector(255 downto 0)
+ );
+ end component;
+
+ component downLinkRxDataPath
+ port (
+ clk : in std_logic;
+ downLinkFrame : in std_logic_vector( 63 downto 0);
+ dataStrobe : out std_logic;
+ dataOut : out std_logic_vector( 31 downto 0);
+ dataEC : out std_logic_vector( 1 downto 0);
+ dataIC : out std_logic_vector( 1 downto 0);
+ header : out std_logic_vector( 3 downto 0);
+ dataEnable : in std_logic;
+ bypassDeinterleaver : in std_logic;
+ bypassFECDecoder : in std_logic;
+ bypassDescrambler : in std_logic;
+ fecCorrectionCount : out std_logic_vector( 15 downto 0)
+ );
+ end component;
+
+
+begin --========#### Architecture Body ####========--
+
+ ---------------------------- Downlink ----------------------------
+ sta_mgtRxRdy_s <= GT_RXREADY_IN ;
+ rst_pattsearch_s <= not(sta_mgtRxRdy_s) ;
+ rst_datapath_s <= not(sta_headeLocked_s);
+
+ clk_mgtRxUsrclk_s <= GT_RXUSRCLK_IN ;
+ GT_RXSLIDE_OUT <= ctr_clkSlip_s ;
+ dat_downLinkWord_fromMgt_s <= GT_RXDATA_IN ;
+
+
+ --Rdy process (delay from 1 clock)
+ process(sta_rxgbxRdy_s, clk_mgtRxUsrclk_s)
+ begin
+ if sta_rxgbxRdy_s = '0' then
+ downlinkRdy_o <= '0';
+ downlinkRdy_s0 <= '0';
+ downlinkRdy_s1 <= '0';
+ elsif rising_edge(clk_mgtRxUsrclk_s) then
+ if RX_CLKEn_s = '1' then
+ downlinkRdy_s0 <= '1';
+ downlinkRdy_s1 <= downlinkRdy_s0;
+ downlinkRdy_o <= downlinkRdy_s1;
+ end if;
+ end if;
+ end process;
+
+ --! Multicycle path configuration (downlink)
+ syncShiftRegDown_proc: process(sta_rxgbxRdy_s, clk_mgtRxUsrclk_s)
+ variable cnter : integer range 0 to 7;
+ begin
+
+ if sta_rxgbxRdy_s = '0' then
+ cnter := 0;
+ RX_CLKEn_s <= '0';
+ rst_downlinkInitDone_s <= '0';
+
+ elsif rising_edge(clk_mgtRxUsrclk_s) then
+ if clk_dataFlag_rxGb_s = '1' then
+ cnter := 0;
+ rst_downlinkInitDone_s <= '1';
+ elsif rst_downlinkInitDone_s = '1' then
+ cnter := cnter + 1;
+ end if;
+ RX_CLKEn_s <= '0';
+ if cnter = 4 then
+ RX_CLKEn_s <= rst_downlinkInitDone_s;
+ end if;
+ end if;
+ end process;
+
+ -- Pattern aligner
+ mgt_framealigner_inst: entity work.mgt_framealigner
+ GENERIC map (
+ c_wordRatio => 8,
+ c_headerPattern => x"F00F",
+ c_wordSize => 32,
+ c_allowedFalseHeader => 32,
+ c_allowedFalseHeaderOverN => 40,
+ c_requiredTrueHeader => 30,
+ c_bitslip_mindly => rxslide_pulse_duration,
+ c_bitslip_waitdly => rxslide_pulse_delay
+
+ )
+ PORT map (
+ -- Clock(s)
+ clk_pcsRx_i => clk_mgtRxUsrclk_s,
+
+ -- Reset(s)
+ rst_pattsearch_i => rst_pattsearch_s,
+
+ -- Control
+ cmd_bitslipCtrl_o => ctr_clkSlip_s,
+
+ -- Status
+ sta_headerLocked_o => sta_headeLocked_s,
+ sta_headerFlag_o => sta_headerFlag_s,
+ sta_bitSlipEven_o => open,
+ -- Data
+ dat_word_i => dat_downLinkWord_toPattSrch_s
+ );
+
+ dat_downLinkWord_toPattSrch_s <= dat_downLinkWord_fromMgt_s(24) & dat_downLinkWord_fromMgt_s(25) & dat_downLinkWord_fromMgt_s(26) & dat_downLinkWord_fromMgt_s(27) &
+ dat_downLinkWord_fromMgt_s(16) & dat_downLinkWord_fromMgt_s(17) & dat_downLinkWord_fromMgt_s(18) & dat_downLinkWord_fromMgt_s(19) &
+ dat_downLinkWord_fromMgt_s(8) & dat_downLinkWord_fromMgt_s(9) & dat_downLinkWord_fromMgt_s(10) & dat_downLinkWord_fromMgt_s(11) &
+ dat_downLinkWord_fromMgt_s(3) & dat_downLinkWord_fromMgt_s(2) & dat_downLinkWord_fromMgt_s(1) & dat_downLinkWord_fromMgt_s(0);
+
+ -- Downlink gearbox
+ rxGearbox_inst: entity work.lpgbtfpga_rxGearbox
+ generic map(
+ c_clockRatio => 8,
+ c_inputWidth => 32,
+ c_outputWidth => 64,
+ c_counterInitValue => 2
+ )
+ port map(
+ -- Clock and reset
+ clk_inClk_i => clk_mgtRxUsrclk_s,
+ clk_outClk_i => clk_mgtRxUsrclk_s,
+ clk_clkEn_i => sta_headerFlag_s,
+ clk_dataFlag_o => clk_dataFlag_rxGb_s,
+ rst_gearbox_i => rst_datapath_s,
+
+ -- Data
+ dat_inFrame_i => dat_downLinkWord_fromMgt_s,
+ dat_outFrame_o => dat_downLinkWord_fromGb_s,
+
+ -- Status
+ sta_gbRdy_o => sta_rxgbxRdy_s
+ );
+
+ rxdatapath_inst : downLinkRxDataPath
+ port map (
+ clk => clk_mgtRxUsrclk_s,
+ downLinkFrame => dat_downLinkWord_fromGb_s(63 downto 0),
+ dataStrobe => open,
+ dataOut(15 downto 0) => downLinkDataGroup0_s,
+ dataOut(31 downto 16) => downLinkDataGroup1_s,
+ dataEC => downLinkDataEc_s,
+ dataIC => downLinkDataIc_s,
+ header => open,
+ dataEnable => RX_CLKEn_s,
+ bypassDeinterleaver => '0',
+ bypassFECDecoder => '0',
+ bypassDescrambler => '0',
+ fecCorrectionCount => open
+ );
+
+ downlinkClkEn_o <= RX_CLKEn_s;
+ downLinkDataGroup0 <= downLinkDataGroup0_s;
+ downLinkDataGroup1 <= downLinkDataGroup1_s;
+ downLinkDataEc <= downLinkDataEc_s;
+ downLinkDataIc <= downLinkDataIc_s;
+ -------------------------------------------------------------------
+
+ ---------------------------- Uplink -------------------------------
+ sta_mgtTxRdy_s <= GT_TXREADY_IN;
+ rst_uplinkGb_s <= not(sta_mgtTxRdy_s);
+ uplinkRdy_o <= sta_txGbRdy_s;
+ clk_mgtTxUsrclk_s <= GT_TXUSRCLK_IN;
+
+ -- Multicycle path configuration
+ syncShiftRegUp_proc: process(rst_uplinkGb_s, clk_mgtTxUsrclk_s)
+ variable cnter : integer range 0 to 7;
+ begin
+ if rst_uplinkGb_s = '1' then
+ cnter := 0;
+ uplinkClkEn_shgb_s <= '0';
+ rst_uplinkGb_synch_s <= '1';
+ rst_uplinkInitDone_s <= '0';
+ upLinkData0_s <= (others => '0');
+ upLinkData1_s <= (others => '0');
+ upLinkData2_s <= (others => '0');
+ upLinkData3_s <= (others => '0');
+ upLinkData4_s <= (others => '0');
+ upLinkData5_s <= (others => '0');
+ upLinkData6_s <= (others => '0');
+ upLinkDataIC_s <= (others => '0');
+ upLinkDataEC_s <= (others => '0');
+ elsif rising_edge(clk_mgtTxUsrclk_s) then
+ if uplinkClkEn_i = '1' then
+ cnter := 0;
+ upLinkData0_s <= upLinkData0;
+ upLinkData1_s <= upLinkData1;
+ upLinkData2_s <= upLinkData2;
+ upLinkData3_s <= upLinkData3;
+ upLinkData4_s <= upLinkData4;
+ upLinkData5_s <= upLinkData5;
+ upLinkData6_s <= upLinkData6;
+ upLinkDataIC_s <= upLinkDataIC;
+ upLinkDataEC_s <= upLinkDataEC;
+ rst_uplinkInitDone_s <= '1';
+ elsif rst_uplinkInitDone_s = '1' then
+ cnter := cnter + 1;
+ end if;
+ uplinkClkEn_shgb_s <= '0';
+ if cnter = 4 then
+ uplinkClkEn_shgb_s <= '1';
+ rst_uplinkGb_synch_s <= rst_uplinkGb_s or not(rst_uplinkInitDone_s);
+ end if;
+ end if;
+ end process;
+
+ txdatapath_inst : upLinkTxDataPath
+ port map (
+ clk => clk_mgtTxUsrclk_s,
+ dataEnable => uplinkClkEn_i,
+ txDataGroup0 => upLinkData0_s,
+ txDataGroup1 => upLinkData1_s,
+ txDataGroup2 => upLinkData2_s,
+ txDataGroup3 => upLinkData3_s,
+ txDataGroup4 => upLinkData4_s,
+ txDataGroup5 => upLinkData5_s,
+ txDataGroup6 => upLinkData6_s,
+ txIC => upLinkDataIC_s,
+ txEC => upLinkDataEC_s,
+ txDummyFec5 => "001100",
+ txDummyFec12 => "1001110011",
+ scramblerBypass => '0',
+ interleaverBypass => '0',
+ fecMode => fecMode,
+ txDataRate => txDataRate,
+ fecDisable => '0',
+ scramblerReset => rst_uplinkGb_s,
+ upLinkFrame => dat_upLinkWord_fromLpGBT_s
+ );
+
+ upLinkPipelineBeforeOversampling_proc: process(rst_uplinkGb_s, clk_mgtTxUsrclk_s)
+ begin
+ if rst_uplinkGb_s = '1' then
+ dat_upLinkWord_fromLpGBT_pipeline_s <= (others => '0');
+ elsif rising_edge(clk_mgtTxUsrclk_s) then
+ if uplinkClkEn_i='1' then
+ dat_upLinkWord_fromLpGBT_pipeline_s <= dat_upLinkWord_fromLpGBT_s;
+ end if;
+ end if;
+ end process;
+
+ oversampler_gen: for i in 0 to 127 generate
+ oversampler_ph_gen: for j in 0 to 1 generate
+ dat_upLinkWord_toGb_s((i*2)+j) <= dat_upLinkWord_fromLpGBT_pipeline_s(i) when txDataRate = '0' else
+ dat_upLinkWord_fromLpGBT_pipeline_s((i*2)+j);
+ end generate;
+ end generate;
+
+ upLinkPipelineAfterOversampling_proc: process(rst_uplinkGb_s, clk_mgtTxUsrclk_s)
+ begin
+ if rst_uplinkGb_s = '1' then
+ dat_upLinkWord_toGb_pipeline_s <= (others => '0');
+ elsif rising_edge(clk_mgtTxUsrclk_s) then
+ if uplinkClkEn_shgb_s = '1' then
+ dat_upLinkWord_toGb_pipeline_s <= dat_upLinkWord_toGb_s;
+ end if;
+ end if;
+ end process;
+
+ txGearbox_inst: entity work.txGearbox
+ generic map (
+ c_clockRatio => 8 ,
+ c_inputWidth => 256 ,
+ c_outputWidth => 32
+ )
+ port map (
+ -- Clock and reset
+ clk_inClk_i => clk_mgtTxUsrclk_s ,
+ clk_clkEn_i => uplinkClkEn_shgb_s ,
+ clk_outClk_i => clk_mgtTxUsrclk_s ,
+ rst_gearbox_i => rst_uplinkGb_synch_s ,
+ dat_inFrame_i => dat_upLinkWord_toGb_pipeline_s,
+ dat_outFrame_o => dat_upLinkWord_fromGb_s ,
+ sta_gbRdy_o => sta_txGbRdy_s
+ );
+
+ GT_TXDATA_OUT <= dat_upLinkWord_fromGb_s;
+ -------------------------------------------------------------------
+
+end behavioral;
+--=================================================================================================--
+--#################################################################################################--
+--=================================================================================================--
--
GitLab
From 4cbda4f66b7c672d4551f6163198fdf886089bda Mon Sep 17 00:00:00 2001
From: Frans Schreuder <f.schreuder@nikhef.nl>
Date: Tue, 9 Jul 2024 10:57:57 +0200
Subject: [PATCH 6/6] VSG fix on lpgbtemul_top
---
sources/LpGBT/LpGBT_FELIX/lpgbtemul_top.vhd | 208 ++++++++++----------
1 file changed, 104 insertions(+), 104 deletions(-)
diff --git a/sources/LpGBT/LpGBT_FELIX/lpgbtemul_top.vhd b/sources/LpGBT/LpGBT_FELIX/lpgbtemul_top.vhd
index 41162920e..7afabec7a 100644
--- a/sources/LpGBT/LpGBT_FELIX/lpgbtemul_top.vhd
+++ b/sources/LpGBT/LpGBT_FELIX/lpgbtemul_top.vhd
@@ -1,7 +1,7 @@
-- IEEE VHDL standard library:
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
--use work.lpgbtfpga_package.all;
--=================================================================================================--
@@ -11,20 +11,20 @@ use ieee.numeric_std.all;
entity lpgbtemul_top is
generic(
-- MGT-specific parameters
- -- Read your MGT user guide before connecting them
+ -- Read your MGT user guide before connecting them
rxslide_pulse_duration : integer:= 2; -- Duration of GT_RXSLIDE_OUT pulse
rxslide_pulse_delay : integer:= 128 -- Minimum time between two GT_RXSLIDE_OUT pulses
);
- port(
+ port(
-- DownLink
- downlinkClkEn_o : out std_logic;
+ downlinkClkEn_o : out std_logic;
downLinkDataGroup0 : out std_logic_vector(15 downto 0);
downLinkDataGroup1 : out std_logic_vector(15 downto 0);
downLinkDataEc : out std_logic_vector(1 downto 0);
downLinkDataIc : out std_logic_vector(1 downto 0);
downlinkRdy_o : out std_logic;
-
- -- Uplink
+
+ -- Uplink
uplinkClkEn_i : in std_logic;
upLinkData0 : in std_logic_vector(31 downto 0);
upLinkData1 : in std_logic_vector(31 downto 0);
@@ -36,30 +36,30 @@ entity lpgbtemul_top is
upLinkDataIC : in std_logic_vector(1 downto 0);
upLinkDataEC : in std_logic_vector(1 downto 0);
uplinkRdy_o : out std_logic;
-
- -- Uplink mode
+
+ -- Uplink mode
fecMode : in std_logic; -- 0=FEC5, 1=FEC12
txDataRate : in std_logic; -- 1=5G , 2=10G
- -- Transceiver
+ -- Transceiver
GT_RXUSRCLK_IN : in std_logic;
GT_TXUSRCLK_IN : in std_logic;
- GT_RXSLIDE_OUT : out std_logic;
+ GT_RXSLIDE_OUT : out std_logic;
GT_TXREADY_IN : in std_logic;
GT_RXREADY_IN : in std_logic;
GT_TXDATA_OUT : out std_logic_vector(31 downto 0);
GT_RXDATA_IN : in std_logic_vector(31 downto 0)
- );
+ );
end lpgbtemul_top;
--=================================================================================================--
---#################################### Architecture ###########################################--
+--#################################### Architecture ###########################################--
--=================================================================================================--
architecture behavioral of lpgbtemul_top is
- -- Downlink
+ -- Downlink
signal dat_downLinkWord_fromMgt_s : std_logic_vector(31 downto 0);
signal sta_mgtRxRdy_s : std_logic;
signal rst_pattsearch_s : std_logic;
@@ -106,59 +106,59 @@ architecture behavioral of lpgbtemul_top is
signal upLinkDataIC_s : std_logic_vector(1 downto 0);
signal upLinkDataEC_s : std_logic_vector(1 downto 0);
- component upLinkTxDataPath
- port (
- clk : in std_logic;
- dataEnable : in std_logic;
- txDataGroup0 : in std_logic_vector(31 downto 0);
- txDataGroup1 : in std_logic_vector(31 downto 0);
- txDataGroup2 : in std_logic_vector(31 downto 0);
- txDataGroup3 : in std_logic_vector(31 downto 0);
- txDataGroup4 : in std_logic_vector(31 downto 0);
- txDataGroup5 : in std_logic_vector(31 downto 0);
- txDataGroup6 : in std_logic_vector(31 downto 0);
-
- txIC : in std_logic_vector( 1 downto 0);
- txEC : in std_logic_vector( 1 downto 0);
- txDummyFec5 : in std_logic_vector( 5 downto 0);
- txDummyFec12 : in std_logic_vector( 9 downto 0);
- scramblerBypass : in std_logic;
- interleaverBypass : in std_logic;
- fecMode : in std_logic;
- txDataRate : in std_logic;
- fecDisable : in std_logic;
- scramblerReset : in std_logic;
- upLinkFrame : out std_logic_vector(255 downto 0)
- );
+ component upLinkTxDataPath
+ port (
+ clk : in std_logic;
+ dataEnable : in std_logic;
+ txDataGroup0 : in std_logic_vector(31 downto 0);
+ txDataGroup1 : in std_logic_vector(31 downto 0);
+ txDataGroup2 : in std_logic_vector(31 downto 0);
+ txDataGroup3 : in std_logic_vector(31 downto 0);
+ txDataGroup4 : in std_logic_vector(31 downto 0);
+ txDataGroup5 : in std_logic_vector(31 downto 0);
+ txDataGroup6 : in std_logic_vector(31 downto 0);
+
+ txIC : in std_logic_vector( 1 downto 0);
+ txEC : in std_logic_vector( 1 downto 0);
+ txDummyFec5 : in std_logic_vector( 5 downto 0);
+ txDummyFec12 : in std_logic_vector( 9 downto 0);
+ scramblerBypass : in std_logic;
+ interleaverBypass : in std_logic;
+ fecMode : in std_logic;
+ txDataRate : in std_logic;
+ fecDisable : in std_logic;
+ scramblerReset : in std_logic;
+ upLinkFrame : out std_logic_vector(255 downto 0)
+ );
end component;
-
- component downLinkRxDataPath
- port (
- clk : in std_logic;
- downLinkFrame : in std_logic_vector( 63 downto 0);
- dataStrobe : out std_logic;
- dataOut : out std_logic_vector( 31 downto 0);
- dataEC : out std_logic_vector( 1 downto 0);
- dataIC : out std_logic_vector( 1 downto 0);
- header : out std_logic_vector( 3 downto 0);
- dataEnable : in std_logic;
- bypassDeinterleaver : in std_logic;
- bypassFECDecoder : in std_logic;
- bypassDescrambler : in std_logic;
- fecCorrectionCount : out std_logic_vector( 15 downto 0)
+
+ component downLinkRxDataPath
+ port (
+ clk : in std_logic;
+ downLinkFrame : in std_logic_vector( 63 downto 0);
+ dataStrobe : out std_logic;
+ dataOut : out std_logic_vector( 31 downto 0);
+ dataEC : out std_logic_vector( 1 downto 0);
+ dataIC : out std_logic_vector( 1 downto 0);
+ header : out std_logic_vector( 3 downto 0);
+ dataEnable : in std_logic;
+ bypassDeinterleaver : in std_logic;
+ bypassFECDecoder : in std_logic;
+ bypassDescrambler : in std_logic;
+ fecCorrectionCount : out std_logic_vector( 15 downto 0)
);
end component;
-
-begin --========#### Architecture Body ####========--
+
+begin --========#### Architecture Body ####========--
---------------------------- Downlink ----------------------------
sta_mgtRxRdy_s <= GT_RXREADY_IN ;
rst_pattsearch_s <= not(sta_mgtRxRdy_s) ;
rst_datapath_s <= not(sta_headeLocked_s);
- clk_mgtRxUsrclk_s <= GT_RXUSRCLK_IN ;
- GT_RXSLIDE_OUT <= ctr_clkSlip_s ;
+ clk_mgtRxUsrclk_s <= GT_RXUSRCLK_IN ;
+ GT_RXSLIDE_OUT <= ctr_clkSlip_s ;
dat_downLinkWord_fromMgt_s <= GT_RXDATA_IN ;
@@ -175,19 +175,19 @@ begin --========#### Architecture Body ####========--
downlinkRdy_s1 <= downlinkRdy_s0;
downlinkRdy_o <= downlinkRdy_s1;
end if;
- end if;
+ end if;
end process;
--! Multicycle path configuration (downlink)
syncShiftRegDown_proc: process(sta_rxgbxRdy_s, clk_mgtRxUsrclk_s)
variable cnter : integer range 0 to 7;
begin
-
+
if sta_rxgbxRdy_s = '0' then
- cnter := 0;
- RX_CLKEn_s <= '0';
- rst_downlinkInitDone_s <= '0';
-
+ cnter := 0;
+ RX_CLKEn_s <= '0';
+ rst_downlinkInitDone_s <= '0';
+
elsif rising_edge(clk_mgtRxUsrclk_s) then
if clk_dataFlag_rxGb_s = '1' then
cnter := 0;
@@ -198,10 +198,10 @@ begin --========#### Architecture Body ####========--
RX_CLKEn_s <= '0';
if cnter = 4 then
RX_CLKEn_s <= rst_downlinkInitDone_s;
- end if;
+ end if;
end if;
end process;
-
+
-- Pattern aligner
mgt_framealigner_inst: entity work.mgt_framealigner
GENERIC map (
@@ -215,27 +215,27 @@ begin --========#### Architecture Body ####========--
c_bitslip_waitdly => rxslide_pulse_delay
)
- PORT map (
+ PORT map (
-- Clock(s)
clk_pcsRx_i => clk_mgtRxUsrclk_s,
-
+
-- Reset(s)
rst_pattsearch_i => rst_pattsearch_s,
-
+
-- Control
cmd_bitslipCtrl_o => ctr_clkSlip_s,
-
+
-- Status
sta_headerLocked_o => sta_headeLocked_s,
sta_headerFlag_o => sta_headerFlag_s,
sta_bitSlipEven_o => open,
-- Data
dat_word_i => dat_downLinkWord_toPattSrch_s
- );
+ );
- dat_downLinkWord_toPattSrch_s <= dat_downLinkWord_fromMgt_s(24) & dat_downLinkWord_fromMgt_s(25) & dat_downLinkWord_fromMgt_s(26) & dat_downLinkWord_fromMgt_s(27) &
- dat_downLinkWord_fromMgt_s(16) & dat_downLinkWord_fromMgt_s(17) & dat_downLinkWord_fromMgt_s(18) & dat_downLinkWord_fromMgt_s(19) &
- dat_downLinkWord_fromMgt_s(8) & dat_downLinkWord_fromMgt_s(9) & dat_downLinkWord_fromMgt_s(10) & dat_downLinkWord_fromMgt_s(11) &
+ dat_downLinkWord_toPattSrch_s <= dat_downLinkWord_fromMgt_s(24) & dat_downLinkWord_fromMgt_s(25) & dat_downLinkWord_fromMgt_s(26) & dat_downLinkWord_fromMgt_s(27) &
+ dat_downLinkWord_fromMgt_s(16) & dat_downLinkWord_fromMgt_s(17) & dat_downLinkWord_fromMgt_s(18) & dat_downLinkWord_fromMgt_s(19) &
+ dat_downLinkWord_fromMgt_s(8) & dat_downLinkWord_fromMgt_s(9) & dat_downLinkWord_fromMgt_s(10) & dat_downLinkWord_fromMgt_s(11) &
dat_downLinkWord_fromMgt_s(3) & dat_downLinkWord_fromMgt_s(2) & dat_downLinkWord_fromMgt_s(1) & dat_downLinkWord_fromMgt_s(0);
-- Downlink gearbox
@@ -257,7 +257,7 @@ begin --========#### Architecture Body ####========--
-- Data
dat_inFrame_i => dat_downLinkWord_fromMgt_s,
dat_outFrame_o => dat_downLinkWord_fromGb_s,
-
+
-- Status
sta_gbRdy_o => sta_rxgbxRdy_s
);
@@ -266,7 +266,7 @@ begin --========#### Architecture Body ####========--
port map (
clk => clk_mgtRxUsrclk_s,
downLinkFrame => dat_downLinkWord_fromGb_s(63 downto 0),
- dataStrobe => open,
+ dataStrobe => open,
dataOut(15 downto 0) => downLinkDataGroup0_s,
dataOut(31 downto 16) => downLinkDataGroup1_s,
dataEC => downLinkDataEc_s,
@@ -279,15 +279,15 @@ begin --========#### Architecture Body ####========--
fecCorrectionCount => open
);
- downlinkClkEn_o <= RX_CLKEn_s;
+ downlinkClkEn_o <= RX_CLKEn_s;
downLinkDataGroup0 <= downLinkDataGroup0_s;
downLinkDataGroup1 <= downLinkDataGroup1_s;
downLinkDataEc <= downLinkDataEc_s;
downLinkDataIc <= downLinkDataIc_s;
-------------------------------------------------------------------
- ---------------------------- Uplink -------------------------------
- sta_mgtTxRdy_s <= GT_TXREADY_IN;
+ ---------------------------- Uplink -------------------------------
+ sta_mgtTxRdy_s <= GT_TXREADY_IN;
rst_uplinkGb_s <= not(sta_mgtTxRdy_s);
uplinkRdy_o <= sta_txGbRdy_s;
clk_mgtTxUsrclk_s <= GT_TXUSRCLK_IN;
@@ -297,19 +297,19 @@ begin --========#### Architecture Body ####========--
variable cnter : integer range 0 to 7;
begin
if rst_uplinkGb_s = '1' then
- cnter := 0;
- uplinkClkEn_shgb_s <= '0';
- rst_uplinkGb_synch_s <= '1';
- rst_uplinkInitDone_s <= '0';
- upLinkData0_s <= (others => '0');
- upLinkData1_s <= (others => '0');
- upLinkData2_s <= (others => '0');
- upLinkData3_s <= (others => '0');
- upLinkData4_s <= (others => '0');
- upLinkData5_s <= (others => '0');
- upLinkData6_s <= (others => '0');
- upLinkDataIC_s <= (others => '0');
- upLinkDataEC_s <= (others => '0');
+ cnter := 0;
+ uplinkClkEn_shgb_s <= '0';
+ rst_uplinkGb_synch_s <= '1';
+ rst_uplinkInitDone_s <= '0';
+ upLinkData0_s <= (others => '0');
+ upLinkData1_s <= (others => '0');
+ upLinkData2_s <= (others => '0');
+ upLinkData3_s <= (others => '0');
+ upLinkData4_s <= (others => '0');
+ upLinkData5_s <= (others => '0');
+ upLinkData6_s <= (others => '0');
+ upLinkDataIC_s <= (others => '0');
+ upLinkDataEC_s <= (others => '0');
elsif rising_edge(clk_mgtTxUsrclk_s) then
if uplinkClkEn_i = '1' then
cnter := 0;
@@ -330,14 +330,14 @@ begin --========#### Architecture Body ####========--
if cnter = 4 then
uplinkClkEn_shgb_s <= '1';
rst_uplinkGb_synch_s <= rst_uplinkGb_s or not(rst_uplinkInitDone_s);
- end if;
+ end if;
end if;
end process;
txdatapath_inst : upLinkTxDataPath
port map (
clk => clk_mgtTxUsrclk_s,
- dataEnable => uplinkClkEn_i,
+ dataEnable => uplinkClkEn_i,
txDataGroup0 => upLinkData0_s,
txDataGroup1 => upLinkData1_s,
txDataGroup2 => upLinkData2_s,
@@ -359,33 +359,33 @@ begin --========#### Architecture Body ####========--
);
upLinkPipelineBeforeOversampling_proc: process(rst_uplinkGb_s, clk_mgtTxUsrclk_s)
- begin
+ begin
if rst_uplinkGb_s = '1' then
dat_upLinkWord_fromLpGBT_pipeline_s <= (others => '0');
elsif rising_edge(clk_mgtTxUsrclk_s) then
if uplinkClkEn_i='1' then
- dat_upLinkWord_fromLpGBT_pipeline_s <= dat_upLinkWord_fromLpGBT_s;
+ dat_upLinkWord_fromLpGBT_pipeline_s <= dat_upLinkWord_fromLpGBT_s;
end if;
- end if;
- end process;
+ end if;
+ end process;
oversampler_gen: for i in 0 to 127 generate
oversampler_ph_gen: for j in 0 to 1 generate
dat_upLinkWord_toGb_s((i*2)+j) <= dat_upLinkWord_fromLpGBT_pipeline_s(i) when txDataRate = '0' else
dat_upLinkWord_fromLpGBT_pipeline_s((i*2)+j);
end generate;
- end generate;
+ end generate;
upLinkPipelineAfterOversampling_proc: process(rst_uplinkGb_s, clk_mgtTxUsrclk_s)
- begin
+ begin
if rst_uplinkGb_s = '1' then
dat_upLinkWord_toGb_pipeline_s <= (others => '0');
elsif rising_edge(clk_mgtTxUsrclk_s) then
if uplinkClkEn_shgb_s = '1' then
- dat_upLinkWord_toGb_pipeline_s <= dat_upLinkWord_toGb_s;
+ dat_upLinkWord_toGb_pipeline_s <= dat_upLinkWord_toGb_s;
end if;
- end if;
- end process;
+ end if;
+ end process;
txGearbox_inst: entity work.txGearbox
generic map (
@@ -395,7 +395,7 @@ begin --========#### Architecture Body ####========--
)
port map (
-- Clock and reset
- clk_inClk_i => clk_mgtTxUsrclk_s ,
+ clk_inClk_i => clk_mgtTxUsrclk_s ,
clk_clkEn_i => uplinkClkEn_shgb_s ,
clk_outClk_i => clk_mgtTxUsrclk_s ,
rst_gearbox_i => rst_uplinkGb_synch_s ,
@@ -405,7 +405,7 @@ begin --========#### Architecture Body ####========--
);
GT_TXDATA_OUT <= dat_upLinkWord_fromGb_s;
- -------------------------------------------------------------------
+-------------------------------------------------------------------
end behavioral;
--=================================================================================================--
--
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